1*85840bd2SDaniel Henrique Barboza /* 2*85840bd2SDaniel Henrique Barboza * QEMU RISC-V CPU QOM header 3*85840bd2SDaniel Henrique Barboza * 4*85840bd2SDaniel Henrique Barboza * Copyright (c) 2023 Ventana Micro Systems Inc. 5*85840bd2SDaniel Henrique Barboza * 6*85840bd2SDaniel Henrique Barboza * This program is free software; you can redistribute it and/or modify it 7*85840bd2SDaniel Henrique Barboza * under the terms and conditions of the GNU General Public License, 8*85840bd2SDaniel Henrique Barboza * version 2 or later, as published by the Free Software Foundation. 9*85840bd2SDaniel Henrique Barboza * 10*85840bd2SDaniel Henrique Barboza * This program is distributed in the hope it will be useful, but WITHOUT 11*85840bd2SDaniel Henrique Barboza * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*85840bd2SDaniel Henrique Barboza * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*85840bd2SDaniel Henrique Barboza * more details. 14*85840bd2SDaniel Henrique Barboza * 15*85840bd2SDaniel Henrique Barboza * You should have received a copy of the GNU General Public License along with 16*85840bd2SDaniel Henrique Barboza * this program. If not, see <http://www.gnu.org/licenses/>. 17*85840bd2SDaniel Henrique Barboza */ 18*85840bd2SDaniel Henrique Barboza 19*85840bd2SDaniel Henrique Barboza #ifndef RISCV_CPU_QOM_H 20*85840bd2SDaniel Henrique Barboza #define RISCV_CPU_QOM_H 21*85840bd2SDaniel Henrique Barboza 22*85840bd2SDaniel Henrique Barboza #include "hw/core/cpu.h" 23*85840bd2SDaniel Henrique Barboza #include "qom/object.h" 24*85840bd2SDaniel Henrique Barboza 25*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU "riscv-cpu" 26*85840bd2SDaniel Henrique Barboza 27*85840bd2SDaniel Henrique Barboza #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 28*85840bd2SDaniel Henrique Barboza #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 29*85840bd2SDaniel Henrique Barboza #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 30*85840bd2SDaniel Henrique Barboza 31*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 32*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 33*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 34*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 35*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 36*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 37*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 38*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 39*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 40*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 41*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 42*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 43*85840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 44*85840bd2SDaniel Henrique Barboza 45*85840bd2SDaniel Henrique Barboza #if defined(TARGET_RISCV32) 46*85840bd2SDaniel Henrique Barboza # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 47*85840bd2SDaniel Henrique Barboza #elif defined(TARGET_RISCV64) 48*85840bd2SDaniel Henrique Barboza # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 49*85840bd2SDaniel Henrique Barboza #endif 50*85840bd2SDaniel Henrique Barboza 51*85840bd2SDaniel Henrique Barboza typedef struct CPUArchState CPURISCVState; 52*85840bd2SDaniel Henrique Barboza 53*85840bd2SDaniel Henrique Barboza OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 54*85840bd2SDaniel Henrique Barboza 55*85840bd2SDaniel Henrique Barboza /** 56*85840bd2SDaniel Henrique Barboza * RISCVCPUClass: 57*85840bd2SDaniel Henrique Barboza * @parent_realize: The parent class' realize handler. 58*85840bd2SDaniel Henrique Barboza * @parent_phases: The parent class' reset phase handlers. 59*85840bd2SDaniel Henrique Barboza * 60*85840bd2SDaniel Henrique Barboza * A RISCV CPU model. 61*85840bd2SDaniel Henrique Barboza */ 62*85840bd2SDaniel Henrique Barboza struct RISCVCPUClass { 63*85840bd2SDaniel Henrique Barboza /*< private >*/ 64*85840bd2SDaniel Henrique Barboza CPUClass parent_class; 65*85840bd2SDaniel Henrique Barboza /*< public >*/ 66*85840bd2SDaniel Henrique Barboza DeviceRealize parent_realize; 67*85840bd2SDaniel Henrique Barboza ResettablePhases parent_phases; 68*85840bd2SDaniel Henrique Barboza }; 69*85840bd2SDaniel Henrique Barboza 70*85840bd2SDaniel Henrique Barboza #endif /* RISCV_CPU_QOM_H */ 71