xref: /openbmc/qemu/target/ppc/translate.c (revision 0e76929d)
1 /*
2  *  PowerPC emulation for qemu: main translation routines.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *  Copyright (C) 2011 Freescale Semiconductor, Inc.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31 
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 
35 #include "exec/translator.h"
36 #include "exec/log.h"
37 #include "qemu/atomic128.h"
38 #include "spr_common.h"
39 
40 #include "qemu/qemu-print.h"
41 #include "qapi/error.h"
42 
43 #define CPU_SINGLE_STEP 0x1
44 #define CPU_BRANCH_STEP 0x2
45 
46 /* Include definitions for instructions classes and implementations flags */
47 /* #define PPC_DEBUG_DISAS */
48 
49 #ifdef PPC_DEBUG_DISAS
50 #  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
51 #else
52 #  define LOG_DISAS(...) do { } while (0)
53 #endif
54 /*****************************************************************************/
55 /* Code translation helpers                                                  */
56 
57 /* global register indexes */
58 static char cpu_reg_names[10 * 3 + 22 * 4   /* GPR */
59                           + 10 * 4 + 22 * 5 /* SPE GPRh */
60                           + 8 * 5           /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
72 static TCGv cpu_reserve;
73 static TCGv cpu_reserve_val;
74 static TCGv cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76 
77 #include "exec/gen-icount.h"
78 
79 void ppc_translate_init(void)
80 {
81     int i;
82     char *p;
83     size_t cpu_reg_names_size;
84 
85     p = cpu_reg_names;
86     cpu_reg_names_size = sizeof(cpu_reg_names);
87 
88     for (i = 0; i < 8; i++) {
89         snprintf(p, cpu_reg_names_size, "crf%d", i);
90         cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
91                                             offsetof(CPUPPCState, crf[i]), p);
92         p += 5;
93         cpu_reg_names_size -= 5;
94     }
95 
96     for (i = 0; i < 32; i++) {
97         snprintf(p, cpu_reg_names_size, "r%d", i);
98         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
99                                         offsetof(CPUPPCState, gpr[i]), p);
100         p += (i < 10) ? 3 : 4;
101         cpu_reg_names_size -= (i < 10) ? 3 : 4;
102         snprintf(p, cpu_reg_names_size, "r%dH", i);
103         cpu_gprh[i] = tcg_global_mem_new(cpu_env,
104                                          offsetof(CPUPPCState, gprh[i]), p);
105         p += (i < 10) ? 4 : 5;
106         cpu_reg_names_size -= (i < 10) ? 4 : 5;
107     }
108 
109     cpu_nip = tcg_global_mem_new(cpu_env,
110                                  offsetof(CPUPPCState, nip), "nip");
111 
112     cpu_msr = tcg_global_mem_new(cpu_env,
113                                  offsetof(CPUPPCState, msr), "msr");
114 
115     cpu_ctr = tcg_global_mem_new(cpu_env,
116                                  offsetof(CPUPPCState, ctr), "ctr");
117 
118     cpu_lr = tcg_global_mem_new(cpu_env,
119                                 offsetof(CPUPPCState, lr), "lr");
120 
121 #if defined(TARGET_PPC64)
122     cpu_cfar = tcg_global_mem_new(cpu_env,
123                                   offsetof(CPUPPCState, cfar), "cfar");
124 #endif
125 
126     cpu_xer = tcg_global_mem_new(cpu_env,
127                                  offsetof(CPUPPCState, xer), "xer");
128     cpu_so = tcg_global_mem_new(cpu_env,
129                                 offsetof(CPUPPCState, so), "SO");
130     cpu_ov = tcg_global_mem_new(cpu_env,
131                                 offsetof(CPUPPCState, ov), "OV");
132     cpu_ca = tcg_global_mem_new(cpu_env,
133                                 offsetof(CPUPPCState, ca), "CA");
134     cpu_ov32 = tcg_global_mem_new(cpu_env,
135                                   offsetof(CPUPPCState, ov32), "OV32");
136     cpu_ca32 = tcg_global_mem_new(cpu_env,
137                                   offsetof(CPUPPCState, ca32), "CA32");
138 
139     cpu_reserve = tcg_global_mem_new(cpu_env,
140                                      offsetof(CPUPPCState, reserve_addr),
141                                      "reserve_addr");
142     cpu_reserve_val = tcg_global_mem_new(cpu_env,
143                                      offsetof(CPUPPCState, reserve_val),
144                                      "reserve_val");
145 
146     cpu_fpscr = tcg_global_mem_new(cpu_env,
147                                    offsetof(CPUPPCState, fpscr), "fpscr");
148 
149     cpu_access_type = tcg_global_mem_new_i32(cpu_env,
150                                              offsetof(CPUPPCState, access_type),
151                                              "access_type");
152 }
153 
154 /* internal defines */
155 struct DisasContext {
156     DisasContextBase base;
157     target_ulong cia;  /* current instruction address */
158     uint32_t opcode;
159     /* Routine used to access memory */
160     bool pr, hv, dr, le_mode;
161     bool lazy_tlb_flush;
162     bool need_access_type;
163     int mem_idx;
164     int access_type;
165     /* Translation flags */
166     MemOp default_tcg_memop_mask;
167 #if defined(TARGET_PPC64)
168     bool sf_mode;
169     bool has_cfar;
170 #endif
171     bool fpu_enabled;
172     bool altivec_enabled;
173     bool vsx_enabled;
174     bool spe_enabled;
175     bool tm_enabled;
176     bool gtse;
177     bool hr;
178     bool mmcr0_pmcc0;
179     bool mmcr0_pmcc1;
180     bool pmu_insn_cnt;
181     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
182     int singlestep_enabled;
183     uint32_t flags;
184     uint64_t insns_flags;
185     uint64_t insns_flags2;
186 };
187 
188 #define DISAS_EXIT         DISAS_TARGET_0  /* exit to main loop, pc updated */
189 #define DISAS_EXIT_UPDATE  DISAS_TARGET_1  /* exit to main loop, pc stale */
190 #define DISAS_CHAIN        DISAS_TARGET_2  /* lookup next tb, pc updated */
191 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3  /* lookup next tb, pc stale */
192 
193 /* Return true iff byteswap is needed in a scalar memop */
194 static inline bool need_byteswap(const DisasContext *ctx)
195 {
196 #if TARGET_BIG_ENDIAN
197      return ctx->le_mode;
198 #else
199      return !ctx->le_mode;
200 #endif
201 }
202 
203 /* True when active word size < size of target_long.  */
204 #ifdef TARGET_PPC64
205 # define NARROW_MODE(C)  (!(C)->sf_mode)
206 #else
207 # define NARROW_MODE(C)  0
208 #endif
209 
210 struct opc_handler_t {
211     /* invalid bits for instruction 1 (Rc(opcode) == 0) */
212     uint32_t inval1;
213     /* invalid bits for instruction 2 (Rc(opcode) == 1) */
214     uint32_t inval2;
215     /* instruction type */
216     uint64_t type;
217     /* extended instruction type */
218     uint64_t type2;
219     /* handler */
220     void (*handler)(DisasContext *ctx);
221 };
222 
223 /* SPR load/store helpers */
224 static inline void gen_load_spr(TCGv t, int reg)
225 {
226     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
227 }
228 
229 static inline void gen_store_spr(int reg, TCGv t)
230 {
231     tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
232 }
233 
234 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
235 {
236     if (ctx->need_access_type && ctx->access_type != access_type) {
237         tcg_gen_movi_i32(cpu_access_type, access_type);
238         ctx->access_type = access_type;
239     }
240 }
241 
242 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
243 {
244     if (NARROW_MODE(ctx)) {
245         nip = (uint32_t)nip;
246     }
247     tcg_gen_movi_tl(cpu_nip, nip);
248 }
249 
250 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
251 {
252     TCGv_i32 t0, t1;
253 
254     /*
255      * These are all synchronous exceptions, we set the PC back to the
256      * faulting instruction
257      */
258     gen_update_nip(ctx, ctx->cia);
259     t0 = tcg_const_i32(excp);
260     t1 = tcg_const_i32(error);
261     gen_helper_raise_exception_err(cpu_env, t0, t1);
262     tcg_temp_free_i32(t0);
263     tcg_temp_free_i32(t1);
264     ctx->base.is_jmp = DISAS_NORETURN;
265 }
266 
267 static void gen_exception(DisasContext *ctx, uint32_t excp)
268 {
269     TCGv_i32 t0;
270 
271     /*
272      * These are all synchronous exceptions, we set the PC back to the
273      * faulting instruction
274      */
275     gen_update_nip(ctx, ctx->cia);
276     t0 = tcg_const_i32(excp);
277     gen_helper_raise_exception(cpu_env, t0);
278     tcg_temp_free_i32(t0);
279     ctx->base.is_jmp = DISAS_NORETURN;
280 }
281 
282 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
283                               target_ulong nip)
284 {
285     TCGv_i32 t0;
286 
287     gen_update_nip(ctx, nip);
288     t0 = tcg_const_i32(excp);
289     gen_helper_raise_exception(cpu_env, t0);
290     tcg_temp_free_i32(t0);
291     ctx->base.is_jmp = DISAS_NORETURN;
292 }
293 
294 static void gen_icount_io_start(DisasContext *ctx)
295 {
296     if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
297         gen_io_start();
298         /*
299          * An I/O instruction must be last in the TB.
300          * Chain to the next TB, and let the code from gen_tb_start
301          * decide if we need to return to the main loop.
302          * Doing this first also allows this value to be overridden.
303          */
304         ctx->base.is_jmp = DISAS_TOO_MANY;
305     }
306 }
307 
308 /*
309  * Tells the caller what is the appropriate exception to generate and prepares
310  * SPR registers for this exception.
311  *
312  * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
313  * POWERPC_EXCP_DEBUG (on BookE).
314  */
315 static uint32_t gen_prep_dbgex(DisasContext *ctx)
316 {
317     if (ctx->flags & POWERPC_FLAG_DE) {
318         target_ulong dbsr = 0;
319         if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
320             dbsr = DBCR0_ICMP;
321         } else {
322             /* Must have been branch */
323             dbsr = DBCR0_BRT;
324         }
325         TCGv t0 = tcg_temp_new();
326         gen_load_spr(t0, SPR_BOOKE_DBSR);
327         tcg_gen_ori_tl(t0, t0, dbsr);
328         gen_store_spr(SPR_BOOKE_DBSR, t0);
329         tcg_temp_free(t0);
330         return POWERPC_EXCP_DEBUG;
331     } else {
332         return POWERPC_EXCP_TRACE;
333     }
334 }
335 
336 static void gen_debug_exception(DisasContext *ctx)
337 {
338     gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
339     ctx->base.is_jmp = DISAS_NORETURN;
340 }
341 
342 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
343 {
344     /* Will be converted to program check if needed */
345     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
346 }
347 
348 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
349 {
350     gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
351 }
352 
353 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
354 {
355     /* Will be converted to program check if needed */
356     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
357 }
358 
359 /*****************************************************************************/
360 /* SPR READ/WRITE CALLBACKS */
361 
362 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
363 {
364 #if 0
365     sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
366     printf("ERROR: try to access SPR %d !\n", sprn);
367 #endif
368 }
369 
370 /* #define PPC_DUMP_SPR_ACCESSES */
371 
372 /*
373  * Generic callbacks:
374  * do nothing but store/retrieve spr value
375  */
376 static void spr_load_dump_spr(int sprn)
377 {
378 #ifdef PPC_DUMP_SPR_ACCESSES
379     TCGv_i32 t0 = tcg_const_i32(sprn);
380     gen_helper_load_dump_spr(cpu_env, t0);
381     tcg_temp_free_i32(t0);
382 #endif
383 }
384 
385 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
386 {
387     gen_load_spr(cpu_gpr[gprn], sprn);
388     spr_load_dump_spr(sprn);
389 }
390 
391 static void spr_store_dump_spr(int sprn)
392 {
393 #ifdef PPC_DUMP_SPR_ACCESSES
394     TCGv_i32 t0 = tcg_const_i32(sprn);
395     gen_helper_store_dump_spr(cpu_env, t0);
396     tcg_temp_free_i32(t0);
397 #endif
398 }
399 
400 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
401 {
402     gen_store_spr(sprn, cpu_gpr[gprn]);
403     spr_store_dump_spr(sprn);
404 }
405 
406 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
407 {
408     spr_write_generic(ctx, sprn, gprn);
409 
410     /*
411      * SPR_CTRL writes must force a new translation block,
412      * allowing the PMU to calculate the run latch events with
413      * more accuracy.
414      */
415     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
416 }
417 
418 #if !defined(CONFIG_USER_ONLY)
419 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
420 {
421 #ifdef TARGET_PPC64
422     TCGv t0 = tcg_temp_new();
423     tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
424     gen_store_spr(sprn, t0);
425     tcg_temp_free(t0);
426     spr_store_dump_spr(sprn);
427 #else
428     spr_write_generic(ctx, sprn, gprn);
429 #endif
430 }
431 
432 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
433 {
434     TCGv t0 = tcg_temp_new();
435     TCGv t1 = tcg_temp_new();
436     gen_load_spr(t0, sprn);
437     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
438     tcg_gen_and_tl(t0, t0, t1);
439     gen_store_spr(sprn, t0);
440     tcg_temp_free(t0);
441     tcg_temp_free(t1);
442 }
443 
444 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
445 {
446 }
447 
448 #endif
449 
450 /* SPR common to all PowerPC */
451 /* XER */
452 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
453 {
454     TCGv dst = cpu_gpr[gprn];
455     TCGv t0 = tcg_temp_new();
456     TCGv t1 = tcg_temp_new();
457     TCGv t2 = tcg_temp_new();
458     tcg_gen_mov_tl(dst, cpu_xer);
459     tcg_gen_shli_tl(t0, cpu_so, XER_SO);
460     tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
461     tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
462     tcg_gen_or_tl(t0, t0, t1);
463     tcg_gen_or_tl(dst, dst, t2);
464     tcg_gen_or_tl(dst, dst, t0);
465     if (is_isa300(ctx)) {
466         tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
467         tcg_gen_or_tl(dst, dst, t0);
468         tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
469         tcg_gen_or_tl(dst, dst, t0);
470     }
471     tcg_temp_free(t0);
472     tcg_temp_free(t1);
473     tcg_temp_free(t2);
474 }
475 
476 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
477 {
478     TCGv src = cpu_gpr[gprn];
479     /* Write all flags, while reading back check for isa300 */
480     tcg_gen_andi_tl(cpu_xer, src,
481                     ~((1u << XER_SO) |
482                       (1u << XER_OV) | (1u << XER_OV32) |
483                       (1u << XER_CA) | (1u << XER_CA32)));
484     tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
485     tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
486     tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
487     tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
488     tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
489 }
490 
491 /* LR */
492 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
493 {
494     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
495 }
496 
497 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
498 {
499     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
500 }
501 
502 /* CFAR */
503 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
504 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
505 {
506     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
507 }
508 
509 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
510 {
511     tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
512 }
513 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
514 
515 /* CTR */
516 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
517 {
518     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
519 }
520 
521 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
522 {
523     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
524 }
525 
526 /* User read access to SPR */
527 /* USPRx */
528 /* UMMCRx */
529 /* UPMCx */
530 /* USIA */
531 /* UDECR */
532 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
533 {
534     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
535 }
536 
537 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
538 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
539 {
540     gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
541 }
542 #endif
543 
544 /* SPR common to all non-embedded PowerPC */
545 /* DECR */
546 #if !defined(CONFIG_USER_ONLY)
547 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
548 {
549     gen_icount_io_start(ctx);
550     gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
551 }
552 
553 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
554 {
555     gen_icount_io_start(ctx);
556     gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
557 }
558 #endif
559 
560 /* SPR common to all non-embedded PowerPC, except 601 */
561 /* Time base */
562 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
563 {
564     gen_icount_io_start(ctx);
565     gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
566 }
567 
568 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
569 {
570     gen_icount_io_start(ctx);
571     gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
572 }
573 
574 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
575 {
576     gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
577 }
578 
579 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
580 {
581     gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
582 }
583 
584 #if !defined(CONFIG_USER_ONLY)
585 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
586 {
587     gen_icount_io_start(ctx);
588     gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
589 }
590 
591 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
592 {
593     gen_icount_io_start(ctx);
594     gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
595 }
596 
597 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
598 {
599     gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
600 }
601 
602 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
603 {
604     gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
605 }
606 
607 #if defined(TARGET_PPC64)
608 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
609 {
610     gen_icount_io_start(ctx);
611     gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
612 }
613 
614 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
615 {
616     gen_icount_io_start(ctx);
617     gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
618 }
619 
620 /* HDECR */
621 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
622 {
623     gen_icount_io_start(ctx);
624     gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
625 }
626 
627 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
628 {
629     gen_icount_io_start(ctx);
630     gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
631 }
632 
633 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
634 {
635     gen_icount_io_start(ctx);
636     gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
637 }
638 
639 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
640 {
641     gen_icount_io_start(ctx);
642     gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
643 }
644 
645 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
646 {
647     gen_icount_io_start(ctx);
648     gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
649 }
650 
651 #endif
652 #endif
653 
654 #if !defined(CONFIG_USER_ONLY)
655 /* IBAT0U...IBAT0U */
656 /* IBAT0L...IBAT7L */
657 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
658 {
659     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
660                   offsetof(CPUPPCState,
661                            IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
662 }
663 
664 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
665 {
666     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
667                   offsetof(CPUPPCState,
668                            IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
669 }
670 
671 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
672 {
673     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
674     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
675     tcg_temp_free_i32(t0);
676 }
677 
678 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
679 {
680     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
681     gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
682     tcg_temp_free_i32(t0);
683 }
684 
685 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
686 {
687     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
688     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
689     tcg_temp_free_i32(t0);
690 }
691 
692 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
693 {
694     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
695     gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
696     tcg_temp_free_i32(t0);
697 }
698 
699 /* DBAT0U...DBAT7U */
700 /* DBAT0L...DBAT7L */
701 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
702 {
703     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
704                   offsetof(CPUPPCState,
705                            DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
706 }
707 
708 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
709 {
710     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
711                   offsetof(CPUPPCState,
712                            DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
713 }
714 
715 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
716 {
717     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
718     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
719     tcg_temp_free_i32(t0);
720 }
721 
722 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
723 {
724     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
725     gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
726     tcg_temp_free_i32(t0);
727 }
728 
729 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
730 {
731     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
732     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
733     tcg_temp_free_i32(t0);
734 }
735 
736 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
737 {
738     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
739     gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
740     tcg_temp_free_i32(t0);
741 }
742 
743 /* SDR1 */
744 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
745 {
746     gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
747 }
748 
749 #if defined(TARGET_PPC64)
750 /* 64 bits PowerPC specific SPRs */
751 /* PIDR */
752 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
753 {
754     gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
755 }
756 
757 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
758 {
759     gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
760 }
761 
762 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
763 {
764     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
765 }
766 
767 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
768 {
769     TCGv t0 = tcg_temp_new();
770     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
771     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
772     tcg_temp_free(t0);
773 }
774 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
775 {
776     gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
777 }
778 
779 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
780 {
781     gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
782 }
783 
784 /* DPDES */
785 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
786 {
787     gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
788 }
789 
790 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
791 {
792     gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
793 }
794 #endif
795 #endif
796 
797 /* PowerPC 40x specific registers */
798 #if !defined(CONFIG_USER_ONLY)
799 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
800 {
801     gen_icount_io_start(ctx);
802     gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
803 }
804 
805 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
806 {
807     gen_icount_io_start(ctx);
808     gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
809 }
810 
811 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
812 {
813     gen_icount_io_start(ctx);
814     gen_store_spr(sprn, cpu_gpr[gprn]);
815     gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
816     /* We must stop translation as we may have rebooted */
817     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
818 }
819 
820 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
821 {
822     gen_icount_io_start(ctx);
823     gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
824 }
825 
826 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
827 {
828     gen_icount_io_start(ctx);
829     gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
830 }
831 
832 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
833 {
834     gen_icount_io_start(ctx);
835     gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
836 }
837 
838 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
839 {
840     TCGv t0 = tcg_temp_new();
841     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
842     gen_helper_store_40x_pid(cpu_env, t0);
843     tcg_temp_free(t0);
844 }
845 
846 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
847 {
848     gen_icount_io_start(ctx);
849     gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
850 }
851 
852 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
853 {
854     gen_icount_io_start(ctx);
855     gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
856 }
857 #endif
858 
859 /* PIR */
860 #if !defined(CONFIG_USER_ONLY)
861 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
862 {
863     TCGv t0 = tcg_temp_new();
864     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
865     gen_store_spr(SPR_PIR, t0);
866     tcg_temp_free(t0);
867 }
868 #endif
869 
870 /* SPE specific registers */
871 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
872 {
873     TCGv_i32 t0 = tcg_temp_new_i32();
874     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
875     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
876     tcg_temp_free_i32(t0);
877 }
878 
879 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
880 {
881     TCGv_i32 t0 = tcg_temp_new_i32();
882     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
883     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
884     tcg_temp_free_i32(t0);
885 }
886 
887 #if !defined(CONFIG_USER_ONLY)
888 /* Callback used to write the exception vector base */
889 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
890 {
891     TCGv t0 = tcg_temp_new();
892     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
893     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
894     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
895     gen_store_spr(sprn, t0);
896     tcg_temp_free(t0);
897 }
898 
899 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
900 {
901     int sprn_offs;
902 
903     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
904         sprn_offs = sprn - SPR_BOOKE_IVOR0;
905     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
906         sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
907     } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
908         sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
909     } else {
910         printf("Trying to write an unknown exception vector %d %03x\n",
911                sprn, sprn);
912         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
913         return;
914     }
915 
916     TCGv t0 = tcg_temp_new();
917     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
918     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
919     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
920     gen_store_spr(sprn, t0);
921     tcg_temp_free(t0);
922 }
923 #endif
924 
925 #ifdef TARGET_PPC64
926 #ifndef CONFIG_USER_ONLY
927 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
928 {
929     TCGv t0 = tcg_temp_new();
930     TCGv t1 = tcg_temp_new();
931     TCGv t2 = tcg_temp_new();
932 
933     /*
934      * Note, the HV=1 PR=0 case is handled earlier by simply using
935      * spr_write_generic for HV mode in the SPR table
936      */
937 
938     /* Build insertion mask into t1 based on context */
939     if (ctx->pr) {
940         gen_load_spr(t1, SPR_UAMOR);
941     } else {
942         gen_load_spr(t1, SPR_AMOR);
943     }
944 
945     /* Mask new bits into t2 */
946     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
947 
948     /* Load AMR and clear new bits in t0 */
949     gen_load_spr(t0, SPR_AMR);
950     tcg_gen_andc_tl(t0, t0, t1);
951 
952     /* Or'in new bits and write it out */
953     tcg_gen_or_tl(t0, t0, t2);
954     gen_store_spr(SPR_AMR, t0);
955     spr_store_dump_spr(SPR_AMR);
956 
957     tcg_temp_free(t0);
958     tcg_temp_free(t1);
959     tcg_temp_free(t2);
960 }
961 
962 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
963 {
964     TCGv t0 = tcg_temp_new();
965     TCGv t1 = tcg_temp_new();
966     TCGv t2 = tcg_temp_new();
967 
968     /*
969      * Note, the HV=1 case is handled earlier by simply using
970      * spr_write_generic for HV mode in the SPR table
971      */
972 
973     /* Build insertion mask into t1 based on context */
974     gen_load_spr(t1, SPR_AMOR);
975 
976     /* Mask new bits into t2 */
977     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
978 
979     /* Load AMR and clear new bits in t0 */
980     gen_load_spr(t0, SPR_UAMOR);
981     tcg_gen_andc_tl(t0, t0, t1);
982 
983     /* Or'in new bits and write it out */
984     tcg_gen_or_tl(t0, t0, t2);
985     gen_store_spr(SPR_UAMOR, t0);
986     spr_store_dump_spr(SPR_UAMOR);
987 
988     tcg_temp_free(t0);
989     tcg_temp_free(t1);
990     tcg_temp_free(t2);
991 }
992 
993 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
994 {
995     TCGv t0 = tcg_temp_new();
996     TCGv t1 = tcg_temp_new();
997     TCGv t2 = tcg_temp_new();
998 
999     /*
1000      * Note, the HV=1 case is handled earlier by simply using
1001      * spr_write_generic for HV mode in the SPR table
1002      */
1003 
1004     /* Build insertion mask into t1 based on context */
1005     gen_load_spr(t1, SPR_AMOR);
1006 
1007     /* Mask new bits into t2 */
1008     tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1009 
1010     /* Load AMR and clear new bits in t0 */
1011     gen_load_spr(t0, SPR_IAMR);
1012     tcg_gen_andc_tl(t0, t0, t1);
1013 
1014     /* Or'in new bits and write it out */
1015     tcg_gen_or_tl(t0, t0, t2);
1016     gen_store_spr(SPR_IAMR, t0);
1017     spr_store_dump_spr(SPR_IAMR);
1018 
1019     tcg_temp_free(t0);
1020     tcg_temp_free(t1);
1021     tcg_temp_free(t2);
1022 }
1023 #endif
1024 #endif
1025 
1026 #ifndef CONFIG_USER_ONLY
1027 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1028 {
1029     gen_helper_fixup_thrm(cpu_env);
1030     gen_load_spr(cpu_gpr[gprn], sprn);
1031     spr_load_dump_spr(sprn);
1032 }
1033 #endif /* !CONFIG_USER_ONLY */
1034 
1035 #if !defined(CONFIG_USER_ONLY)
1036 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1037 {
1038     TCGv t0 = tcg_temp_new();
1039 
1040     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1041     gen_store_spr(sprn, t0);
1042     tcg_temp_free(t0);
1043 }
1044 
1045 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1046 {
1047     TCGv t0 = tcg_temp_new();
1048 
1049     tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1050     gen_store_spr(sprn, t0);
1051     tcg_temp_free(t0);
1052 }
1053 
1054 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1055 {
1056     TCGv t0 = tcg_temp_new();
1057 
1058     tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1059                     ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1060     gen_store_spr(sprn, t0);
1061     tcg_temp_free(t0);
1062 }
1063 
1064 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1065 {
1066     gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1067 }
1068 
1069 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1070 {
1071     TCGv_i32 t0 = tcg_const_i32(sprn);
1072     gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1073     tcg_temp_free_i32(t0);
1074 }
1075 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1076 {
1077     gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1078 }
1079 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1080 {
1081     gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1082 }
1083 
1084 #endif
1085 
1086 #if !defined(CONFIG_USER_ONLY)
1087 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1088 {
1089     TCGv val = tcg_temp_new();
1090     tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1091     gen_store_spr(SPR_BOOKE_MAS3, val);
1092     tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1093     gen_store_spr(SPR_BOOKE_MAS7, val);
1094     tcg_temp_free(val);
1095 }
1096 
1097 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1098 {
1099     TCGv mas7 = tcg_temp_new();
1100     TCGv mas3 = tcg_temp_new();
1101     gen_load_spr(mas7, SPR_BOOKE_MAS7);
1102     tcg_gen_shli_tl(mas7, mas7, 32);
1103     gen_load_spr(mas3, SPR_BOOKE_MAS3);
1104     tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1105     tcg_temp_free(mas3);
1106     tcg_temp_free(mas7);
1107 }
1108 
1109 #endif
1110 
1111 #ifdef TARGET_PPC64
1112 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1113                                     int bit, int sprn, int cause)
1114 {
1115     TCGv_i32 t1 = tcg_const_i32(bit);
1116     TCGv_i32 t2 = tcg_const_i32(sprn);
1117     TCGv_i32 t3 = tcg_const_i32(cause);
1118 
1119     gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1120 
1121     tcg_temp_free_i32(t3);
1122     tcg_temp_free_i32(t2);
1123     tcg_temp_free_i32(t1);
1124 }
1125 
1126 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1127                                    int bit, int sprn, int cause)
1128 {
1129     TCGv_i32 t1 = tcg_const_i32(bit);
1130     TCGv_i32 t2 = tcg_const_i32(sprn);
1131     TCGv_i32 t3 = tcg_const_i32(cause);
1132 
1133     gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1134 
1135     tcg_temp_free_i32(t3);
1136     tcg_temp_free_i32(t2);
1137     tcg_temp_free_i32(t1);
1138 }
1139 
1140 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1141 {
1142     TCGv spr_up = tcg_temp_new();
1143     TCGv spr = tcg_temp_new();
1144 
1145     gen_load_spr(spr, sprn - 1);
1146     tcg_gen_shri_tl(spr_up, spr, 32);
1147     tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1148 
1149     tcg_temp_free(spr);
1150     tcg_temp_free(spr_up);
1151 }
1152 
1153 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1154 {
1155     TCGv spr = tcg_temp_new();
1156 
1157     gen_load_spr(spr, sprn - 1);
1158     tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1159     gen_store_spr(sprn - 1, spr);
1160 
1161     tcg_temp_free(spr);
1162 }
1163 
1164 #if !defined(CONFIG_USER_ONLY)
1165 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1166 {
1167     TCGv hmer = tcg_temp_new();
1168 
1169     gen_load_spr(hmer, sprn);
1170     tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1171     gen_store_spr(sprn, hmer);
1172     spr_store_dump_spr(sprn);
1173     tcg_temp_free(hmer);
1174 }
1175 
1176 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1177 {
1178     gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1179 }
1180 #endif /* !defined(CONFIG_USER_ONLY) */
1181 
1182 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1183 {
1184     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1185     spr_read_generic(ctx, gprn, sprn);
1186 }
1187 
1188 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1189 {
1190     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1191     spr_write_generic(ctx, sprn, gprn);
1192 }
1193 
1194 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1195 {
1196     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1197     spr_read_generic(ctx, gprn, sprn);
1198 }
1199 
1200 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1201 {
1202     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1203     spr_write_generic(ctx, sprn, gprn);
1204 }
1205 
1206 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1207 {
1208     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1209     spr_read_prev_upper32(ctx, gprn, sprn);
1210 }
1211 
1212 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1213 {
1214     gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1215     spr_write_prev_upper32(ctx, sprn, gprn);
1216 }
1217 
1218 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1219 {
1220     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1221     spr_read_generic(ctx, gprn, sprn);
1222 }
1223 
1224 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1225 {
1226     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1227     spr_write_generic(ctx, sprn, gprn);
1228 }
1229 
1230 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1231 {
1232     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1233     spr_read_prev_upper32(ctx, gprn, sprn);
1234 }
1235 
1236 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1237 {
1238     gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1239     spr_write_prev_upper32(ctx, sprn, gprn);
1240 }
1241 #endif
1242 
1243 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
1244 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1245 
1246 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \
1247 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1248 
1249 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
1250 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1251 
1252 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \
1253 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1254 
1255 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
1256 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1257 
1258 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1259 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1260 
1261 typedef struct opcode_t {
1262     unsigned char opc1, opc2, opc3, opc4;
1263 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1264     unsigned char pad[4];
1265 #endif
1266     opc_handler_t handler;
1267     const char *oname;
1268 } opcode_t;
1269 
1270 /* Helpers for priv. check */
1271 #define GEN_PRIV                                                \
1272     do {                                                        \
1273         gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1274     } while (0)
1275 
1276 #if defined(CONFIG_USER_ONLY)
1277 #define CHK_HV GEN_PRIV
1278 #define CHK_SV GEN_PRIV
1279 #define CHK_HVRM GEN_PRIV
1280 #else
1281 #define CHK_HV                                                          \
1282     do {                                                                \
1283         if (unlikely(ctx->pr || !ctx->hv)) {                            \
1284             GEN_PRIV;                                                   \
1285         }                                                               \
1286     } while (0)
1287 #define CHK_SV                   \
1288     do {                         \
1289         if (unlikely(ctx->pr)) { \
1290             GEN_PRIV;            \
1291         }                        \
1292     } while (0)
1293 #define CHK_HVRM                                            \
1294     do {                                                    \
1295         if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) {     \
1296             GEN_PRIV;                                       \
1297         }                                                   \
1298     } while (0)
1299 #endif
1300 
1301 #define CHK_NONE
1302 
1303 /*****************************************************************************/
1304 /* PowerPC instructions table                                                */
1305 
1306 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
1307 {                                                                             \
1308     .opc1 = op1,                                                              \
1309     .opc2 = op2,                                                              \
1310     .opc3 = op3,                                                              \
1311     .opc4 = 0xff,                                                             \
1312     .handler = {                                                              \
1313         .inval1  = invl,                                                      \
1314         .type = _typ,                                                         \
1315         .type2 = _typ2,                                                       \
1316         .handler = &gen_##name,                                               \
1317     },                                                                        \
1318     .oname = stringify(name),                                                 \
1319 }
1320 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
1321 {                                                                             \
1322     .opc1 = op1,                                                              \
1323     .opc2 = op2,                                                              \
1324     .opc3 = op3,                                                              \
1325     .opc4 = 0xff,                                                             \
1326     .handler = {                                                              \
1327         .inval1  = invl1,                                                     \
1328         .inval2  = invl2,                                                     \
1329         .type = _typ,                                                         \
1330         .type2 = _typ2,                                                       \
1331         .handler = &gen_##name,                                               \
1332     },                                                                        \
1333     .oname = stringify(name),                                                 \
1334 }
1335 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
1336 {                                                                             \
1337     .opc1 = op1,                                                              \
1338     .opc2 = op2,                                                              \
1339     .opc3 = op3,                                                              \
1340     .opc4 = 0xff,                                                             \
1341     .handler = {                                                              \
1342         .inval1  = invl,                                                      \
1343         .type = _typ,                                                         \
1344         .type2 = _typ2,                                                       \
1345         .handler = &gen_##name,                                               \
1346     },                                                                        \
1347     .oname = onam,                                                            \
1348 }
1349 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2)              \
1350 {                                                                             \
1351     .opc1 = op1,                                                              \
1352     .opc2 = op2,                                                              \
1353     .opc3 = op3,                                                              \
1354     .opc4 = op4,                                                              \
1355     .handler = {                                                              \
1356         .inval1  = invl,                                                      \
1357         .type = _typ,                                                         \
1358         .type2 = _typ2,                                                       \
1359         .handler = &gen_##name,                                               \
1360     },                                                                        \
1361     .oname = stringify(name),                                                 \
1362 }
1363 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
1364 {                                                                             \
1365     .opc1 = op1,                                                              \
1366     .opc2 = op2,                                                              \
1367     .opc3 = op3,                                                              \
1368     .opc4 = op4,                                                              \
1369     .handler = {                                                              \
1370         .inval1  = invl,                                                      \
1371         .type = _typ,                                                         \
1372         .type2 = _typ2,                                                       \
1373         .handler = &gen_##name,                                               \
1374     },                                                                        \
1375     .oname = onam,                                                            \
1376 }
1377 
1378 /* Invalid instruction */
1379 static void gen_invalid(DisasContext *ctx)
1380 {
1381     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1382 }
1383 
1384 static opc_handler_t invalid_handler = {
1385     .inval1  = 0xFFFFFFFF,
1386     .inval2  = 0xFFFFFFFF,
1387     .type    = PPC_NONE,
1388     .type2   = PPC_NONE,
1389     .handler = gen_invalid,
1390 };
1391 
1392 /***                           Integer comparison                          ***/
1393 
1394 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1395 {
1396     TCGv t0 = tcg_temp_new();
1397     TCGv t1 = tcg_temp_new();
1398     TCGv_i32 t = tcg_temp_new_i32();
1399 
1400     tcg_gen_movi_tl(t0, CRF_EQ);
1401     tcg_gen_movi_tl(t1, CRF_LT);
1402     tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1403                        t0, arg0, arg1, t1, t0);
1404     tcg_gen_movi_tl(t1, CRF_GT);
1405     tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1406                        t0, arg0, arg1, t1, t0);
1407 
1408     tcg_gen_trunc_tl_i32(t, t0);
1409     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1410     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1411 
1412     tcg_temp_free(t0);
1413     tcg_temp_free(t1);
1414     tcg_temp_free_i32(t);
1415 }
1416 
1417 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1418 {
1419     TCGv t0 = tcg_const_tl(arg1);
1420     gen_op_cmp(arg0, t0, s, crf);
1421     tcg_temp_free(t0);
1422 }
1423 
1424 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1425 {
1426     TCGv t0, t1;
1427     t0 = tcg_temp_new();
1428     t1 = tcg_temp_new();
1429     if (s) {
1430         tcg_gen_ext32s_tl(t0, arg0);
1431         tcg_gen_ext32s_tl(t1, arg1);
1432     } else {
1433         tcg_gen_ext32u_tl(t0, arg0);
1434         tcg_gen_ext32u_tl(t1, arg1);
1435     }
1436     gen_op_cmp(t0, t1, s, crf);
1437     tcg_temp_free(t1);
1438     tcg_temp_free(t0);
1439 }
1440 
1441 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1442 {
1443     TCGv t0 = tcg_const_tl(arg1);
1444     gen_op_cmp32(arg0, t0, s, crf);
1445     tcg_temp_free(t0);
1446 }
1447 
1448 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1449 {
1450     if (NARROW_MODE(ctx)) {
1451         gen_op_cmpi32(reg, 0, 1, 0);
1452     } else {
1453         gen_op_cmpi(reg, 0, 1, 0);
1454     }
1455 }
1456 
1457 /* cmprb - range comparison: isupper, isaplha, islower*/
1458 static void gen_cmprb(DisasContext *ctx)
1459 {
1460     TCGv_i32 src1 = tcg_temp_new_i32();
1461     TCGv_i32 src2 = tcg_temp_new_i32();
1462     TCGv_i32 src2lo = tcg_temp_new_i32();
1463     TCGv_i32 src2hi = tcg_temp_new_i32();
1464     TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1465 
1466     tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1467     tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1468 
1469     tcg_gen_andi_i32(src1, src1, 0xFF);
1470     tcg_gen_ext8u_i32(src2lo, src2);
1471     tcg_gen_shri_i32(src2, src2, 8);
1472     tcg_gen_ext8u_i32(src2hi, src2);
1473 
1474     tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1475     tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1476     tcg_gen_and_i32(crf, src2lo, src2hi);
1477 
1478     if (ctx->opcode & 0x00200000) {
1479         tcg_gen_shri_i32(src2, src2, 8);
1480         tcg_gen_ext8u_i32(src2lo, src2);
1481         tcg_gen_shri_i32(src2, src2, 8);
1482         tcg_gen_ext8u_i32(src2hi, src2);
1483         tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1484         tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1485         tcg_gen_and_i32(src2lo, src2lo, src2hi);
1486         tcg_gen_or_i32(crf, crf, src2lo);
1487     }
1488     tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1489     tcg_temp_free_i32(src1);
1490     tcg_temp_free_i32(src2);
1491     tcg_temp_free_i32(src2lo);
1492     tcg_temp_free_i32(src2hi);
1493 }
1494 
1495 #if defined(TARGET_PPC64)
1496 /* cmpeqb */
1497 static void gen_cmpeqb(DisasContext *ctx)
1498 {
1499     gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1500                       cpu_gpr[rB(ctx->opcode)]);
1501 }
1502 #endif
1503 
1504 /* isel (PowerPC 2.03 specification) */
1505 static void gen_isel(DisasContext *ctx)
1506 {
1507     uint32_t bi = rC(ctx->opcode);
1508     uint32_t mask = 0x08 >> (bi & 0x03);
1509     TCGv t0 = tcg_temp_new();
1510     TCGv zr;
1511 
1512     tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1513     tcg_gen_andi_tl(t0, t0, mask);
1514 
1515     zr = tcg_const_tl(0);
1516     tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1517                        rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1518                        cpu_gpr[rB(ctx->opcode)]);
1519     tcg_temp_free(zr);
1520     tcg_temp_free(t0);
1521 }
1522 
1523 /* cmpb: PowerPC 2.05 specification */
1524 static void gen_cmpb(DisasContext *ctx)
1525 {
1526     gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1527                     cpu_gpr[rB(ctx->opcode)]);
1528 }
1529 
1530 /***                           Integer arithmetic                          ***/
1531 
1532 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1533                                            TCGv arg1, TCGv arg2, int sub)
1534 {
1535     TCGv t0 = tcg_temp_new();
1536 
1537     tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1538     tcg_gen_xor_tl(t0, arg1, arg2);
1539     if (sub) {
1540         tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1541     } else {
1542         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1543     }
1544     tcg_temp_free(t0);
1545     if (NARROW_MODE(ctx)) {
1546         tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1547         if (is_isa300(ctx)) {
1548             tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1549         }
1550     } else {
1551         if (is_isa300(ctx)) {
1552             tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1553         }
1554         tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1555     }
1556     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1557 }
1558 
1559 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1560                                              TCGv res, TCGv arg0, TCGv arg1,
1561                                              TCGv ca32, int sub)
1562 {
1563     TCGv t0;
1564 
1565     if (!is_isa300(ctx)) {
1566         return;
1567     }
1568 
1569     t0 = tcg_temp_new();
1570     if (sub) {
1571         tcg_gen_eqv_tl(t0, arg0, arg1);
1572     } else {
1573         tcg_gen_xor_tl(t0, arg0, arg1);
1574     }
1575     tcg_gen_xor_tl(t0, t0, res);
1576     tcg_gen_extract_tl(ca32, t0, 32, 1);
1577     tcg_temp_free(t0);
1578 }
1579 
1580 /* Common add function */
1581 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1582                                     TCGv arg2, TCGv ca, TCGv ca32,
1583                                     bool add_ca, bool compute_ca,
1584                                     bool compute_ov, bool compute_rc0)
1585 {
1586     TCGv t0 = ret;
1587 
1588     if (compute_ca || compute_ov) {
1589         t0 = tcg_temp_new();
1590     }
1591 
1592     if (compute_ca) {
1593         if (NARROW_MODE(ctx)) {
1594             /*
1595              * Caution: a non-obvious corner case of the spec is that
1596              * we must produce the *entire* 64-bit addition, but
1597              * produce the carry into bit 32.
1598              */
1599             TCGv t1 = tcg_temp_new();
1600             tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
1601             tcg_gen_add_tl(t0, arg1, arg2);
1602             if (add_ca) {
1603                 tcg_gen_add_tl(t0, t0, ca);
1604             }
1605             tcg_gen_xor_tl(ca, t0, t1);        /* bits changed w/ carry */
1606             tcg_temp_free(t1);
1607             tcg_gen_extract_tl(ca, ca, 32, 1);
1608             if (is_isa300(ctx)) {
1609                 tcg_gen_mov_tl(ca32, ca);
1610             }
1611         } else {
1612             TCGv zero = tcg_const_tl(0);
1613             if (add_ca) {
1614                 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1615                 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1616             } else {
1617                 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1618             }
1619             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1620             tcg_temp_free(zero);
1621         }
1622     } else {
1623         tcg_gen_add_tl(t0, arg1, arg2);
1624         if (add_ca) {
1625             tcg_gen_add_tl(t0, t0, ca);
1626         }
1627     }
1628 
1629     if (compute_ov) {
1630         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1631     }
1632     if (unlikely(compute_rc0)) {
1633         gen_set_Rc0(ctx, t0);
1634     }
1635 
1636     if (t0 != ret) {
1637         tcg_gen_mov_tl(ret, t0);
1638         tcg_temp_free(t0);
1639     }
1640 }
1641 /* Add functions with two operands */
1642 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov)     \
1643 static void glue(gen_, name)(DisasContext *ctx)                               \
1644 {                                                                             \
1645     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1646                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1647                      ca, glue(ca, 32),                                        \
1648                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1649 }
1650 /* Add functions with one operand and one immediate */
1651 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca,                    \
1652                                 add_ca, compute_ca, compute_ov)               \
1653 static void glue(gen_, name)(DisasContext *ctx)                               \
1654 {                                                                             \
1655     TCGv t0 = tcg_const_tl(const_val);                                        \
1656     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
1657                      cpu_gpr[rA(ctx->opcode)], t0,                            \
1658                      ca, glue(ca, 32),                                        \
1659                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
1660     tcg_temp_free(t0);                                                        \
1661 }
1662 
1663 /* add  add.  addo  addo. */
1664 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1665 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1666 /* addc  addc.  addco  addco. */
1667 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1668 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1669 /* adde  adde.  addeo  addeo. */
1670 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1671 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1672 /* addme  addme.  addmeo  addmeo.  */
1673 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1674 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1675 /* addex */
1676 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1677 /* addze  addze.  addzeo  addzeo.*/
1678 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1679 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1680 /* addic  addic.*/
1681 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1682 {
1683     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1684     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1685                      c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1686     tcg_temp_free(c);
1687 }
1688 
1689 static void gen_addic(DisasContext *ctx)
1690 {
1691     gen_op_addic(ctx, 0);
1692 }
1693 
1694 static void gen_addic_(DisasContext *ctx)
1695 {
1696     gen_op_addic(ctx, 1);
1697 }
1698 
1699 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1700                                      TCGv arg2, int sign, int compute_ov)
1701 {
1702     TCGv_i32 t0 = tcg_temp_new_i32();
1703     TCGv_i32 t1 = tcg_temp_new_i32();
1704     TCGv_i32 t2 = tcg_temp_new_i32();
1705     TCGv_i32 t3 = tcg_temp_new_i32();
1706 
1707     tcg_gen_trunc_tl_i32(t0, arg1);
1708     tcg_gen_trunc_tl_i32(t1, arg2);
1709     if (sign) {
1710         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1711         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1712         tcg_gen_and_i32(t2, t2, t3);
1713         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1714         tcg_gen_or_i32(t2, t2, t3);
1715         tcg_gen_movi_i32(t3, 0);
1716         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1717         tcg_gen_div_i32(t3, t0, t1);
1718         tcg_gen_extu_i32_tl(ret, t3);
1719     } else {
1720         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1721         tcg_gen_movi_i32(t3, 0);
1722         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1723         tcg_gen_divu_i32(t3, t0, t1);
1724         tcg_gen_extu_i32_tl(ret, t3);
1725     }
1726     if (compute_ov) {
1727         tcg_gen_extu_i32_tl(cpu_ov, t2);
1728         if (is_isa300(ctx)) {
1729             tcg_gen_extu_i32_tl(cpu_ov32, t2);
1730         }
1731         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1732     }
1733     tcg_temp_free_i32(t0);
1734     tcg_temp_free_i32(t1);
1735     tcg_temp_free_i32(t2);
1736     tcg_temp_free_i32(t3);
1737 
1738     if (unlikely(Rc(ctx->opcode) != 0)) {
1739         gen_set_Rc0(ctx, ret);
1740     }
1741 }
1742 /* Div functions */
1743 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1744 static void glue(gen_, name)(DisasContext *ctx)                               \
1745 {                                                                             \
1746     gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1747                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1748                      sign, compute_ov);                                       \
1749 }
1750 /* divwu  divwu.  divwuo  divwuo.   */
1751 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1752 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1753 /* divw  divw.  divwo  divwo.   */
1754 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1755 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1756 
1757 /* div[wd]eu[o][.] */
1758 #define GEN_DIVE(name, hlpr, compute_ov)                                      \
1759 static void gen_##name(DisasContext *ctx)                                     \
1760 {                                                                             \
1761     TCGv_i32 t0 = tcg_const_i32(compute_ov);                                  \
1762     gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
1763                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1764     tcg_temp_free_i32(t0);                                                    \
1765     if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
1766         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1767     }                                                                         \
1768 }
1769 
1770 GEN_DIVE(divweu, divweu, 0);
1771 GEN_DIVE(divweuo, divweu, 1);
1772 GEN_DIVE(divwe, divwe, 0);
1773 GEN_DIVE(divweo, divwe, 1);
1774 
1775 #if defined(TARGET_PPC64)
1776 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1777                                      TCGv arg2, int sign, int compute_ov)
1778 {
1779     TCGv_i64 t0 = tcg_temp_new_i64();
1780     TCGv_i64 t1 = tcg_temp_new_i64();
1781     TCGv_i64 t2 = tcg_temp_new_i64();
1782     TCGv_i64 t3 = tcg_temp_new_i64();
1783 
1784     tcg_gen_mov_i64(t0, arg1);
1785     tcg_gen_mov_i64(t1, arg2);
1786     if (sign) {
1787         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1788         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1789         tcg_gen_and_i64(t2, t2, t3);
1790         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1791         tcg_gen_or_i64(t2, t2, t3);
1792         tcg_gen_movi_i64(t3, 0);
1793         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1794         tcg_gen_div_i64(ret, t0, t1);
1795     } else {
1796         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1797         tcg_gen_movi_i64(t3, 0);
1798         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1799         tcg_gen_divu_i64(ret, t0, t1);
1800     }
1801     if (compute_ov) {
1802         tcg_gen_mov_tl(cpu_ov, t2);
1803         if (is_isa300(ctx)) {
1804             tcg_gen_mov_tl(cpu_ov32, t2);
1805         }
1806         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1807     }
1808     tcg_temp_free_i64(t0);
1809     tcg_temp_free_i64(t1);
1810     tcg_temp_free_i64(t2);
1811     tcg_temp_free_i64(t3);
1812 
1813     if (unlikely(Rc(ctx->opcode) != 0)) {
1814         gen_set_Rc0(ctx, ret);
1815     }
1816 }
1817 
1818 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1819 static void glue(gen_, name)(DisasContext *ctx)                               \
1820 {                                                                             \
1821     gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1822                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1823                       sign, compute_ov);                                      \
1824 }
1825 /* divdu  divdu.  divduo  divduo.   */
1826 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1827 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1828 /* divd  divd.  divdo  divdo.   */
1829 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1830 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1831 
1832 GEN_DIVE(divdeu, divdeu, 0);
1833 GEN_DIVE(divdeuo, divdeu, 1);
1834 GEN_DIVE(divde, divde, 0);
1835 GEN_DIVE(divdeo, divde, 1);
1836 #endif
1837 
1838 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1839                                      TCGv arg2, int sign)
1840 {
1841     TCGv_i32 t0 = tcg_temp_new_i32();
1842     TCGv_i32 t1 = tcg_temp_new_i32();
1843 
1844     tcg_gen_trunc_tl_i32(t0, arg1);
1845     tcg_gen_trunc_tl_i32(t1, arg2);
1846     if (sign) {
1847         TCGv_i32 t2 = tcg_temp_new_i32();
1848         TCGv_i32 t3 = tcg_temp_new_i32();
1849         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1850         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1851         tcg_gen_and_i32(t2, t2, t3);
1852         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1853         tcg_gen_or_i32(t2, t2, t3);
1854         tcg_gen_movi_i32(t3, 0);
1855         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1856         tcg_gen_rem_i32(t3, t0, t1);
1857         tcg_gen_ext_i32_tl(ret, t3);
1858         tcg_temp_free_i32(t2);
1859         tcg_temp_free_i32(t3);
1860     } else {
1861         TCGv_i32 t2 = tcg_const_i32(1);
1862         TCGv_i32 t3 = tcg_const_i32(0);
1863         tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1864         tcg_gen_remu_i32(t3, t0, t1);
1865         tcg_gen_extu_i32_tl(ret, t3);
1866         tcg_temp_free_i32(t2);
1867         tcg_temp_free_i32(t3);
1868     }
1869     tcg_temp_free_i32(t0);
1870     tcg_temp_free_i32(t1);
1871 }
1872 
1873 #define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
1874 static void glue(gen_, name)(DisasContext *ctx)                             \
1875 {                                                                           \
1876     gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1877                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1878                       sign);                                                \
1879 }
1880 
1881 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1882 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1883 
1884 #if defined(TARGET_PPC64)
1885 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1886                                      TCGv arg2, int sign)
1887 {
1888     TCGv_i64 t0 = tcg_temp_new_i64();
1889     TCGv_i64 t1 = tcg_temp_new_i64();
1890 
1891     tcg_gen_mov_i64(t0, arg1);
1892     tcg_gen_mov_i64(t1, arg2);
1893     if (sign) {
1894         TCGv_i64 t2 = tcg_temp_new_i64();
1895         TCGv_i64 t3 = tcg_temp_new_i64();
1896         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1897         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1898         tcg_gen_and_i64(t2, t2, t3);
1899         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1900         tcg_gen_or_i64(t2, t2, t3);
1901         tcg_gen_movi_i64(t3, 0);
1902         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1903         tcg_gen_rem_i64(ret, t0, t1);
1904         tcg_temp_free_i64(t2);
1905         tcg_temp_free_i64(t3);
1906     } else {
1907         TCGv_i64 t2 = tcg_const_i64(1);
1908         TCGv_i64 t3 = tcg_const_i64(0);
1909         tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1910         tcg_gen_remu_i64(ret, t0, t1);
1911         tcg_temp_free_i64(t2);
1912         tcg_temp_free_i64(t3);
1913     }
1914     tcg_temp_free_i64(t0);
1915     tcg_temp_free_i64(t1);
1916 }
1917 
1918 #define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
1919 static void glue(gen_, name)(DisasContext *ctx)                           \
1920 {                                                                         \
1921   gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1922                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1923                     sign);                                                \
1924 }
1925 
1926 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1927 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1928 #endif
1929 
1930 /* mulhw  mulhw. */
1931 static void gen_mulhw(DisasContext *ctx)
1932 {
1933     TCGv_i32 t0 = tcg_temp_new_i32();
1934     TCGv_i32 t1 = tcg_temp_new_i32();
1935 
1936     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1937     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1938     tcg_gen_muls2_i32(t0, t1, t0, t1);
1939     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1940     tcg_temp_free_i32(t0);
1941     tcg_temp_free_i32(t1);
1942     if (unlikely(Rc(ctx->opcode) != 0)) {
1943         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1944     }
1945 }
1946 
1947 /* mulhwu  mulhwu.  */
1948 static void gen_mulhwu(DisasContext *ctx)
1949 {
1950     TCGv_i32 t0 = tcg_temp_new_i32();
1951     TCGv_i32 t1 = tcg_temp_new_i32();
1952 
1953     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1954     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1955     tcg_gen_mulu2_i32(t0, t1, t0, t1);
1956     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1957     tcg_temp_free_i32(t0);
1958     tcg_temp_free_i32(t1);
1959     if (unlikely(Rc(ctx->opcode) != 0)) {
1960         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1961     }
1962 }
1963 
1964 /* mullw  mullw. */
1965 static void gen_mullw(DisasContext *ctx)
1966 {
1967 #if defined(TARGET_PPC64)
1968     TCGv_i64 t0, t1;
1969     t0 = tcg_temp_new_i64();
1970     t1 = tcg_temp_new_i64();
1971     tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1972     tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1973     tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1974     tcg_temp_free(t0);
1975     tcg_temp_free(t1);
1976 #else
1977     tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1978                     cpu_gpr[rB(ctx->opcode)]);
1979 #endif
1980     if (unlikely(Rc(ctx->opcode) != 0)) {
1981         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1982     }
1983 }
1984 
1985 /* mullwo  mullwo. */
1986 static void gen_mullwo(DisasContext *ctx)
1987 {
1988     TCGv_i32 t0 = tcg_temp_new_i32();
1989     TCGv_i32 t1 = tcg_temp_new_i32();
1990 
1991     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1992     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1993     tcg_gen_muls2_i32(t0, t1, t0, t1);
1994 #if defined(TARGET_PPC64)
1995     tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1996 #else
1997     tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1998 #endif
1999 
2000     tcg_gen_sari_i32(t0, t0, 31);
2001     tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2002     tcg_gen_extu_i32_tl(cpu_ov, t0);
2003     if (is_isa300(ctx)) {
2004         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2005     }
2006     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2007 
2008     tcg_temp_free_i32(t0);
2009     tcg_temp_free_i32(t1);
2010     if (unlikely(Rc(ctx->opcode) != 0)) {
2011         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2012     }
2013 }
2014 
2015 /* mulli */
2016 static void gen_mulli(DisasContext *ctx)
2017 {
2018     tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2019                     SIMM(ctx->opcode));
2020 }
2021 
2022 #if defined(TARGET_PPC64)
2023 /* mulhd  mulhd. */
2024 static void gen_mulhd(DisasContext *ctx)
2025 {
2026     TCGv lo = tcg_temp_new();
2027     tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2028                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2029     tcg_temp_free(lo);
2030     if (unlikely(Rc(ctx->opcode) != 0)) {
2031         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2032     }
2033 }
2034 
2035 /* mulhdu  mulhdu. */
2036 static void gen_mulhdu(DisasContext *ctx)
2037 {
2038     TCGv lo = tcg_temp_new();
2039     tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2040                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2041     tcg_temp_free(lo);
2042     if (unlikely(Rc(ctx->opcode) != 0)) {
2043         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2044     }
2045 }
2046 
2047 /* mulld  mulld. */
2048 static void gen_mulld(DisasContext *ctx)
2049 {
2050     tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2051                    cpu_gpr[rB(ctx->opcode)]);
2052     if (unlikely(Rc(ctx->opcode) != 0)) {
2053         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2054     }
2055 }
2056 
2057 /* mulldo  mulldo. */
2058 static void gen_mulldo(DisasContext *ctx)
2059 {
2060     TCGv_i64 t0 = tcg_temp_new_i64();
2061     TCGv_i64 t1 = tcg_temp_new_i64();
2062 
2063     tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2064                       cpu_gpr[rB(ctx->opcode)]);
2065     tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2066 
2067     tcg_gen_sari_i64(t0, t0, 63);
2068     tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
2069     if (is_isa300(ctx)) {
2070         tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2071     }
2072     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2073 
2074     tcg_temp_free_i64(t0);
2075     tcg_temp_free_i64(t1);
2076 
2077     if (unlikely(Rc(ctx->opcode) != 0)) {
2078         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2079     }
2080 }
2081 #endif
2082 
2083 /* Common subf function */
2084 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2085                                      TCGv arg2, bool add_ca, bool compute_ca,
2086                                      bool compute_ov, bool compute_rc0)
2087 {
2088     TCGv t0 = ret;
2089 
2090     if (compute_ca || compute_ov) {
2091         t0 = tcg_temp_new();
2092     }
2093 
2094     if (compute_ca) {
2095         /* dest = ~arg1 + arg2 [+ ca].  */
2096         if (NARROW_MODE(ctx)) {
2097             /*
2098              * Caution: a non-obvious corner case of the spec is that
2099              * we must produce the *entire* 64-bit addition, but
2100              * produce the carry into bit 32.
2101              */
2102             TCGv inv1 = tcg_temp_new();
2103             TCGv t1 = tcg_temp_new();
2104             tcg_gen_not_tl(inv1, arg1);
2105             if (add_ca) {
2106                 tcg_gen_add_tl(t0, arg2, cpu_ca);
2107             } else {
2108                 tcg_gen_addi_tl(t0, arg2, 1);
2109             }
2110             tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
2111             tcg_gen_add_tl(t0, t0, inv1);
2112             tcg_temp_free(inv1);
2113             tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
2114             tcg_temp_free(t1);
2115             tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2116             if (is_isa300(ctx)) {
2117                 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2118             }
2119         } else if (add_ca) {
2120             TCGv zero, inv1 = tcg_temp_new();
2121             tcg_gen_not_tl(inv1, arg1);
2122             zero = tcg_const_tl(0);
2123             tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2124             tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2125             gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2126             tcg_temp_free(zero);
2127             tcg_temp_free(inv1);
2128         } else {
2129             tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2130             tcg_gen_sub_tl(t0, arg2, arg1);
2131             gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2132         }
2133     } else if (add_ca) {
2134         /*
2135          * Since we're ignoring carry-out, we can simplify the
2136          * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2137          */
2138         tcg_gen_sub_tl(t0, arg2, arg1);
2139         tcg_gen_add_tl(t0, t0, cpu_ca);
2140         tcg_gen_subi_tl(t0, t0, 1);
2141     } else {
2142         tcg_gen_sub_tl(t0, arg2, arg1);
2143     }
2144 
2145     if (compute_ov) {
2146         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2147     }
2148     if (unlikely(compute_rc0)) {
2149         gen_set_Rc0(ctx, t0);
2150     }
2151 
2152     if (t0 != ret) {
2153         tcg_gen_mov_tl(ret, t0);
2154         tcg_temp_free(t0);
2155     }
2156 }
2157 /* Sub functions with Two operands functions */
2158 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
2159 static void glue(gen_, name)(DisasContext *ctx)                               \
2160 {                                                                             \
2161     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2162                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
2163                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2164 }
2165 /* Sub functions with one operand and one immediate */
2166 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
2167                                 add_ca, compute_ca, compute_ov)               \
2168 static void glue(gen_, name)(DisasContext *ctx)                               \
2169 {                                                                             \
2170     TCGv t0 = tcg_const_tl(const_val);                                        \
2171     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
2172                       cpu_gpr[rA(ctx->opcode)], t0,                           \
2173                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
2174     tcg_temp_free(t0);                                                        \
2175 }
2176 /* subf  subf.  subfo  subfo. */
2177 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2178 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2179 /* subfc  subfc.  subfco  subfco. */
2180 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2181 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2182 /* subfe  subfe.  subfeo  subfo. */
2183 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2184 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2185 /* subfme  subfme.  subfmeo  subfmeo.  */
2186 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2187 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2188 /* subfze  subfze.  subfzeo  subfzeo.*/
2189 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2190 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2191 
2192 /* subfic */
2193 static void gen_subfic(DisasContext *ctx)
2194 {
2195     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
2196     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2197                       c, 0, 1, 0, 0);
2198     tcg_temp_free(c);
2199 }
2200 
2201 /* neg neg. nego nego. */
2202 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2203 {
2204     TCGv zero = tcg_const_tl(0);
2205     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2206                       zero, 0, 0, compute_ov, Rc(ctx->opcode));
2207     tcg_temp_free(zero);
2208 }
2209 
2210 static void gen_neg(DisasContext *ctx)
2211 {
2212     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2213     if (unlikely(Rc(ctx->opcode))) {
2214         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2215     }
2216 }
2217 
2218 static void gen_nego(DisasContext *ctx)
2219 {
2220     gen_op_arith_neg(ctx, 1);
2221 }
2222 
2223 /***                            Integer logical                            ***/
2224 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
2225 static void glue(gen_, name)(DisasContext *ctx)                               \
2226 {                                                                             \
2227     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
2228        cpu_gpr[rB(ctx->opcode)]);                                             \
2229     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2230         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2231 }
2232 
2233 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
2234 static void glue(gen_, name)(DisasContext *ctx)                               \
2235 {                                                                             \
2236     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
2237     if (unlikely(Rc(ctx->opcode) != 0))                                       \
2238         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
2239 }
2240 
2241 /* and & and. */
2242 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2243 /* andc & andc. */
2244 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2245 
2246 /* andi. */
2247 static void gen_andi_(DisasContext *ctx)
2248 {
2249     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2250                     UIMM(ctx->opcode));
2251     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2252 }
2253 
2254 /* andis. */
2255 static void gen_andis_(DisasContext *ctx)
2256 {
2257     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2258                     UIMM(ctx->opcode) << 16);
2259     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2260 }
2261 
2262 /* cntlzw */
2263 static void gen_cntlzw(DisasContext *ctx)
2264 {
2265     TCGv_i32 t = tcg_temp_new_i32();
2266 
2267     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2268     tcg_gen_clzi_i32(t, t, 32);
2269     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2270     tcg_temp_free_i32(t);
2271 
2272     if (unlikely(Rc(ctx->opcode) != 0)) {
2273         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2274     }
2275 }
2276 
2277 /* cnttzw */
2278 static void gen_cnttzw(DisasContext *ctx)
2279 {
2280     TCGv_i32 t = tcg_temp_new_i32();
2281 
2282     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2283     tcg_gen_ctzi_i32(t, t, 32);
2284     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2285     tcg_temp_free_i32(t);
2286 
2287     if (unlikely(Rc(ctx->opcode) != 0)) {
2288         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2289     }
2290 }
2291 
2292 /* eqv & eqv. */
2293 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2294 /* extsb & extsb. */
2295 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2296 /* extsh & extsh. */
2297 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2298 /* nand & nand. */
2299 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2300 /* nor & nor. */
2301 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2302 
2303 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2304 static void gen_pause(DisasContext *ctx)
2305 {
2306     TCGv_i32 t0 = tcg_const_i32(0);
2307     tcg_gen_st_i32(t0, cpu_env,
2308                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2309     tcg_temp_free_i32(t0);
2310 
2311     /* Stop translation, this gives other CPUs a chance to run */
2312     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2313 }
2314 #endif /* defined(TARGET_PPC64) */
2315 
2316 /* or & or. */
2317 static void gen_or(DisasContext *ctx)
2318 {
2319     int rs, ra, rb;
2320 
2321     rs = rS(ctx->opcode);
2322     ra = rA(ctx->opcode);
2323     rb = rB(ctx->opcode);
2324     /* Optimisation for mr. ri case */
2325     if (rs != ra || rs != rb) {
2326         if (rs != rb) {
2327             tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2328         } else {
2329             tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2330         }
2331         if (unlikely(Rc(ctx->opcode) != 0)) {
2332             gen_set_Rc0(ctx, cpu_gpr[ra]);
2333         }
2334     } else if (unlikely(Rc(ctx->opcode) != 0)) {
2335         gen_set_Rc0(ctx, cpu_gpr[rs]);
2336 #if defined(TARGET_PPC64)
2337     } else if (rs != 0) { /* 0 is nop */
2338         int prio = 0;
2339 
2340         switch (rs) {
2341         case 1:
2342             /* Set process priority to low */
2343             prio = 2;
2344             break;
2345         case 6:
2346             /* Set process priority to medium-low */
2347             prio = 3;
2348             break;
2349         case 2:
2350             /* Set process priority to normal */
2351             prio = 4;
2352             break;
2353 #if !defined(CONFIG_USER_ONLY)
2354         case 31:
2355             if (!ctx->pr) {
2356                 /* Set process priority to very low */
2357                 prio = 1;
2358             }
2359             break;
2360         case 5:
2361             if (!ctx->pr) {
2362                 /* Set process priority to medium-hight */
2363                 prio = 5;
2364             }
2365             break;
2366         case 3:
2367             if (!ctx->pr) {
2368                 /* Set process priority to high */
2369                 prio = 6;
2370             }
2371             break;
2372         case 7:
2373             if (ctx->hv && !ctx->pr) {
2374                 /* Set process priority to very high */
2375                 prio = 7;
2376             }
2377             break;
2378 #endif
2379         default:
2380             break;
2381         }
2382         if (prio) {
2383             TCGv t0 = tcg_temp_new();
2384             gen_load_spr(t0, SPR_PPR);
2385             tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2386             tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2387             gen_store_spr(SPR_PPR, t0);
2388             tcg_temp_free(t0);
2389         }
2390 #if !defined(CONFIG_USER_ONLY)
2391         /*
2392          * Pause out of TCG otherwise spin loops with smt_low eat too
2393          * much CPU and the kernel hangs.  This applies to all
2394          * encodings other than no-op, e.g., miso(rs=26), yield(27),
2395          * mdoio(29), mdoom(30), and all currently undefined.
2396          */
2397         gen_pause(ctx);
2398 #endif
2399 #endif
2400     }
2401 }
2402 /* orc & orc. */
2403 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2404 
2405 /* xor & xor. */
2406 static void gen_xor(DisasContext *ctx)
2407 {
2408     /* Optimisation for "set to zero" case */
2409     if (rS(ctx->opcode) != rB(ctx->opcode)) {
2410         tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2411                        cpu_gpr[rB(ctx->opcode)]);
2412     } else {
2413         tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2414     }
2415     if (unlikely(Rc(ctx->opcode) != 0)) {
2416         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2417     }
2418 }
2419 
2420 /* ori */
2421 static void gen_ori(DisasContext *ctx)
2422 {
2423     target_ulong uimm = UIMM(ctx->opcode);
2424 
2425     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2426         return;
2427     }
2428     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2429 }
2430 
2431 /* oris */
2432 static void gen_oris(DisasContext *ctx)
2433 {
2434     target_ulong uimm = UIMM(ctx->opcode);
2435 
2436     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2437         /* NOP */
2438         return;
2439     }
2440     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2441                    uimm << 16);
2442 }
2443 
2444 /* xori */
2445 static void gen_xori(DisasContext *ctx)
2446 {
2447     target_ulong uimm = UIMM(ctx->opcode);
2448 
2449     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2450         /* NOP */
2451         return;
2452     }
2453     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2454 }
2455 
2456 /* xoris */
2457 static void gen_xoris(DisasContext *ctx)
2458 {
2459     target_ulong uimm = UIMM(ctx->opcode);
2460 
2461     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2462         /* NOP */
2463         return;
2464     }
2465     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2466                     uimm << 16);
2467 }
2468 
2469 /* popcntb : PowerPC 2.03 specification */
2470 static void gen_popcntb(DisasContext *ctx)
2471 {
2472     gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2473 }
2474 
2475 static void gen_popcntw(DisasContext *ctx)
2476 {
2477 #if defined(TARGET_PPC64)
2478     gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2479 #else
2480     tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2481 #endif
2482 }
2483 
2484 #if defined(TARGET_PPC64)
2485 /* popcntd: PowerPC 2.06 specification */
2486 static void gen_popcntd(DisasContext *ctx)
2487 {
2488     tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2489 }
2490 #endif
2491 
2492 /* prtyw: PowerPC 2.05 specification */
2493 static void gen_prtyw(DisasContext *ctx)
2494 {
2495     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2496     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2497     TCGv t0 = tcg_temp_new();
2498     tcg_gen_shri_tl(t0, rs, 16);
2499     tcg_gen_xor_tl(ra, rs, t0);
2500     tcg_gen_shri_tl(t0, ra, 8);
2501     tcg_gen_xor_tl(ra, ra, t0);
2502     tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2503     tcg_temp_free(t0);
2504 }
2505 
2506 #if defined(TARGET_PPC64)
2507 /* prtyd: PowerPC 2.05 specification */
2508 static void gen_prtyd(DisasContext *ctx)
2509 {
2510     TCGv ra = cpu_gpr[rA(ctx->opcode)];
2511     TCGv rs = cpu_gpr[rS(ctx->opcode)];
2512     TCGv t0 = tcg_temp_new();
2513     tcg_gen_shri_tl(t0, rs, 32);
2514     tcg_gen_xor_tl(ra, rs, t0);
2515     tcg_gen_shri_tl(t0, ra, 16);
2516     tcg_gen_xor_tl(ra, ra, t0);
2517     tcg_gen_shri_tl(t0, ra, 8);
2518     tcg_gen_xor_tl(ra, ra, t0);
2519     tcg_gen_andi_tl(ra, ra, 1);
2520     tcg_temp_free(t0);
2521 }
2522 #endif
2523 
2524 #if defined(TARGET_PPC64)
2525 /* bpermd */
2526 static void gen_bpermd(DisasContext *ctx)
2527 {
2528     gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2529                       cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2530 }
2531 #endif
2532 
2533 #if defined(TARGET_PPC64)
2534 /* extsw & extsw. */
2535 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2536 
2537 /* cntlzd */
2538 static void gen_cntlzd(DisasContext *ctx)
2539 {
2540     tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2541     if (unlikely(Rc(ctx->opcode) != 0)) {
2542         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2543     }
2544 }
2545 
2546 /* cnttzd */
2547 static void gen_cnttzd(DisasContext *ctx)
2548 {
2549     tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2550     if (unlikely(Rc(ctx->opcode) != 0)) {
2551         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2552     }
2553 }
2554 
2555 /* darn */
2556 static void gen_darn(DisasContext *ctx)
2557 {
2558     int l = L(ctx->opcode);
2559 
2560     if (l > 2) {
2561         tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2562     } else {
2563         gen_icount_io_start(ctx);
2564         if (l == 0) {
2565             gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2566         } else {
2567             /* Return 64-bit random for both CRN and RRN */
2568             gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2569         }
2570     }
2571 }
2572 #endif
2573 
2574 /***                             Integer rotate                            ***/
2575 
2576 /* rlwimi & rlwimi. */
2577 static void gen_rlwimi(DisasContext *ctx)
2578 {
2579     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2580     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2581     uint32_t sh = SH(ctx->opcode);
2582     uint32_t mb = MB(ctx->opcode);
2583     uint32_t me = ME(ctx->opcode);
2584 
2585     if (sh == (31 - me) && mb <= me) {
2586         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2587     } else {
2588         target_ulong mask;
2589         bool mask_in_32b = true;
2590         TCGv t1;
2591 
2592 #if defined(TARGET_PPC64)
2593         mb += 32;
2594         me += 32;
2595 #endif
2596         mask = MASK(mb, me);
2597 
2598 #if defined(TARGET_PPC64)
2599         if (mask > 0xffffffffu) {
2600             mask_in_32b = false;
2601         }
2602 #endif
2603         t1 = tcg_temp_new();
2604         if (mask_in_32b) {
2605             TCGv_i32 t0 = tcg_temp_new_i32();
2606             tcg_gen_trunc_tl_i32(t0, t_rs);
2607             tcg_gen_rotli_i32(t0, t0, sh);
2608             tcg_gen_extu_i32_tl(t1, t0);
2609             tcg_temp_free_i32(t0);
2610         } else {
2611 #if defined(TARGET_PPC64)
2612             tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2613             tcg_gen_rotli_i64(t1, t1, sh);
2614 #else
2615             g_assert_not_reached();
2616 #endif
2617         }
2618 
2619         tcg_gen_andi_tl(t1, t1, mask);
2620         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2621         tcg_gen_or_tl(t_ra, t_ra, t1);
2622         tcg_temp_free(t1);
2623     }
2624     if (unlikely(Rc(ctx->opcode) != 0)) {
2625         gen_set_Rc0(ctx, t_ra);
2626     }
2627 }
2628 
2629 /* rlwinm & rlwinm. */
2630 static void gen_rlwinm(DisasContext *ctx)
2631 {
2632     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2633     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2634     int sh = SH(ctx->opcode);
2635     int mb = MB(ctx->opcode);
2636     int me = ME(ctx->opcode);
2637     int len = me - mb + 1;
2638     int rsh = (32 - sh) & 31;
2639 
2640     if (sh != 0 && len > 0 && me == (31 - sh)) {
2641         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2642     } else if (me == 31 && rsh + len <= 32) {
2643         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2644     } else {
2645         target_ulong mask;
2646         bool mask_in_32b = true;
2647 #if defined(TARGET_PPC64)
2648         mb += 32;
2649         me += 32;
2650 #endif
2651         mask = MASK(mb, me);
2652 #if defined(TARGET_PPC64)
2653         if (mask > 0xffffffffu) {
2654             mask_in_32b = false;
2655         }
2656 #endif
2657         if (mask_in_32b) {
2658             if (sh == 0) {
2659                 tcg_gen_andi_tl(t_ra, t_rs, mask);
2660             } else {
2661                 TCGv_i32 t0 = tcg_temp_new_i32();
2662                 tcg_gen_trunc_tl_i32(t0, t_rs);
2663                 tcg_gen_rotli_i32(t0, t0, sh);
2664                 tcg_gen_andi_i32(t0, t0, mask);
2665                 tcg_gen_extu_i32_tl(t_ra, t0);
2666                 tcg_temp_free_i32(t0);
2667             }
2668         } else {
2669 #if defined(TARGET_PPC64)
2670             tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2671             tcg_gen_rotli_i64(t_ra, t_ra, sh);
2672             tcg_gen_andi_i64(t_ra, t_ra, mask);
2673 #else
2674             g_assert_not_reached();
2675 #endif
2676         }
2677     }
2678     if (unlikely(Rc(ctx->opcode) != 0)) {
2679         gen_set_Rc0(ctx, t_ra);
2680     }
2681 }
2682 
2683 /* rlwnm & rlwnm. */
2684 static void gen_rlwnm(DisasContext *ctx)
2685 {
2686     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2687     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2688     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2689     uint32_t mb = MB(ctx->opcode);
2690     uint32_t me = ME(ctx->opcode);
2691     target_ulong mask;
2692     bool mask_in_32b = true;
2693 
2694 #if defined(TARGET_PPC64)
2695     mb += 32;
2696     me += 32;
2697 #endif
2698     mask = MASK(mb, me);
2699 
2700 #if defined(TARGET_PPC64)
2701     if (mask > 0xffffffffu) {
2702         mask_in_32b = false;
2703     }
2704 #endif
2705     if (mask_in_32b) {
2706         TCGv_i32 t0 = tcg_temp_new_i32();
2707         TCGv_i32 t1 = tcg_temp_new_i32();
2708         tcg_gen_trunc_tl_i32(t0, t_rb);
2709         tcg_gen_trunc_tl_i32(t1, t_rs);
2710         tcg_gen_andi_i32(t0, t0, 0x1f);
2711         tcg_gen_rotl_i32(t1, t1, t0);
2712         tcg_gen_extu_i32_tl(t_ra, t1);
2713         tcg_temp_free_i32(t0);
2714         tcg_temp_free_i32(t1);
2715     } else {
2716 #if defined(TARGET_PPC64)
2717         TCGv_i64 t0 = tcg_temp_new_i64();
2718         tcg_gen_andi_i64(t0, t_rb, 0x1f);
2719         tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2720         tcg_gen_rotl_i64(t_ra, t_ra, t0);
2721         tcg_temp_free_i64(t0);
2722 #else
2723         g_assert_not_reached();
2724 #endif
2725     }
2726 
2727     tcg_gen_andi_tl(t_ra, t_ra, mask);
2728 
2729     if (unlikely(Rc(ctx->opcode) != 0)) {
2730         gen_set_Rc0(ctx, t_ra);
2731     }
2732 }
2733 
2734 #if defined(TARGET_PPC64)
2735 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
2736 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2737 {                                                                             \
2738     gen_##name(ctx, 0);                                                       \
2739 }                                                                             \
2740                                                                               \
2741 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2742 {                                                                             \
2743     gen_##name(ctx, 1);                                                       \
2744 }
2745 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
2746 static void glue(gen_, name##0)(DisasContext *ctx)                            \
2747 {                                                                             \
2748     gen_##name(ctx, 0, 0);                                                    \
2749 }                                                                             \
2750                                                                               \
2751 static void glue(gen_, name##1)(DisasContext *ctx)                            \
2752 {                                                                             \
2753     gen_##name(ctx, 0, 1);                                                    \
2754 }                                                                             \
2755                                                                               \
2756 static void glue(gen_, name##2)(DisasContext *ctx)                            \
2757 {                                                                             \
2758     gen_##name(ctx, 1, 0);                                                    \
2759 }                                                                             \
2760                                                                               \
2761 static void glue(gen_, name##3)(DisasContext *ctx)                            \
2762 {                                                                             \
2763     gen_##name(ctx, 1, 1);                                                    \
2764 }
2765 
2766 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2767 {
2768     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2769     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2770     int len = me - mb + 1;
2771     int rsh = (64 - sh) & 63;
2772 
2773     if (sh != 0 && len > 0 && me == (63 - sh)) {
2774         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2775     } else if (me == 63 && rsh + len <= 64) {
2776         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2777     } else {
2778         tcg_gen_rotli_tl(t_ra, t_rs, sh);
2779         tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2780     }
2781     if (unlikely(Rc(ctx->opcode) != 0)) {
2782         gen_set_Rc0(ctx, t_ra);
2783     }
2784 }
2785 
2786 /* rldicl - rldicl. */
2787 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2788 {
2789     uint32_t sh, mb;
2790 
2791     sh = SH(ctx->opcode) | (shn << 5);
2792     mb = MB(ctx->opcode) | (mbn << 5);
2793     gen_rldinm(ctx, mb, 63, sh);
2794 }
2795 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2796 
2797 /* rldicr - rldicr. */
2798 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2799 {
2800     uint32_t sh, me;
2801 
2802     sh = SH(ctx->opcode) | (shn << 5);
2803     me = MB(ctx->opcode) | (men << 5);
2804     gen_rldinm(ctx, 0, me, sh);
2805 }
2806 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2807 
2808 /* rldic - rldic. */
2809 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2810 {
2811     uint32_t sh, mb;
2812 
2813     sh = SH(ctx->opcode) | (shn << 5);
2814     mb = MB(ctx->opcode) | (mbn << 5);
2815     gen_rldinm(ctx, mb, 63 - sh, sh);
2816 }
2817 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2818 
2819 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2820 {
2821     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2822     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2823     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2824     TCGv t0;
2825 
2826     t0 = tcg_temp_new();
2827     tcg_gen_andi_tl(t0, t_rb, 0x3f);
2828     tcg_gen_rotl_tl(t_ra, t_rs, t0);
2829     tcg_temp_free(t0);
2830 
2831     tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2832     if (unlikely(Rc(ctx->opcode) != 0)) {
2833         gen_set_Rc0(ctx, t_ra);
2834     }
2835 }
2836 
2837 /* rldcl - rldcl. */
2838 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2839 {
2840     uint32_t mb;
2841 
2842     mb = MB(ctx->opcode) | (mbn << 5);
2843     gen_rldnm(ctx, mb, 63);
2844 }
2845 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2846 
2847 /* rldcr - rldcr. */
2848 static inline void gen_rldcr(DisasContext *ctx, int men)
2849 {
2850     uint32_t me;
2851 
2852     me = MB(ctx->opcode) | (men << 5);
2853     gen_rldnm(ctx, 0, me);
2854 }
2855 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2856 
2857 /* rldimi - rldimi. */
2858 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2859 {
2860     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2861     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2862     uint32_t sh = SH(ctx->opcode) | (shn << 5);
2863     uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2864     uint32_t me = 63 - sh;
2865 
2866     if (mb <= me) {
2867         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2868     } else {
2869         target_ulong mask = MASK(mb, me);
2870         TCGv t1 = tcg_temp_new();
2871 
2872         tcg_gen_rotli_tl(t1, t_rs, sh);
2873         tcg_gen_andi_tl(t1, t1, mask);
2874         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2875         tcg_gen_or_tl(t_ra, t_ra, t1);
2876         tcg_temp_free(t1);
2877     }
2878     if (unlikely(Rc(ctx->opcode) != 0)) {
2879         gen_set_Rc0(ctx, t_ra);
2880     }
2881 }
2882 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2883 #endif
2884 
2885 /***                             Integer shift                             ***/
2886 
2887 /* slw & slw. */
2888 static void gen_slw(DisasContext *ctx)
2889 {
2890     TCGv t0, t1;
2891 
2892     t0 = tcg_temp_new();
2893     /* AND rS with a mask that is 0 when rB >= 0x20 */
2894 #if defined(TARGET_PPC64)
2895     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2896     tcg_gen_sari_tl(t0, t0, 0x3f);
2897 #else
2898     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2899     tcg_gen_sari_tl(t0, t0, 0x1f);
2900 #endif
2901     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2902     t1 = tcg_temp_new();
2903     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2904     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2905     tcg_temp_free(t1);
2906     tcg_temp_free(t0);
2907     tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2908     if (unlikely(Rc(ctx->opcode) != 0)) {
2909         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2910     }
2911 }
2912 
2913 /* sraw & sraw. */
2914 static void gen_sraw(DisasContext *ctx)
2915 {
2916     gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2917                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2918     if (unlikely(Rc(ctx->opcode) != 0)) {
2919         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2920     }
2921 }
2922 
2923 /* srawi & srawi. */
2924 static void gen_srawi(DisasContext *ctx)
2925 {
2926     int sh = SH(ctx->opcode);
2927     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2928     TCGv src = cpu_gpr[rS(ctx->opcode)];
2929     if (sh == 0) {
2930         tcg_gen_ext32s_tl(dst, src);
2931         tcg_gen_movi_tl(cpu_ca, 0);
2932         if (is_isa300(ctx)) {
2933             tcg_gen_movi_tl(cpu_ca32, 0);
2934         }
2935     } else {
2936         TCGv t0;
2937         tcg_gen_ext32s_tl(dst, src);
2938         tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2939         t0 = tcg_temp_new();
2940         tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2941         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2942         tcg_temp_free(t0);
2943         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2944         if (is_isa300(ctx)) {
2945             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2946         }
2947         tcg_gen_sari_tl(dst, dst, sh);
2948     }
2949     if (unlikely(Rc(ctx->opcode) != 0)) {
2950         gen_set_Rc0(ctx, dst);
2951     }
2952 }
2953 
2954 /* srw & srw. */
2955 static void gen_srw(DisasContext *ctx)
2956 {
2957     TCGv t0, t1;
2958 
2959     t0 = tcg_temp_new();
2960     /* AND rS with a mask that is 0 when rB >= 0x20 */
2961 #if defined(TARGET_PPC64)
2962     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2963     tcg_gen_sari_tl(t0, t0, 0x3f);
2964 #else
2965     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2966     tcg_gen_sari_tl(t0, t0, 0x1f);
2967 #endif
2968     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2969     tcg_gen_ext32u_tl(t0, t0);
2970     t1 = tcg_temp_new();
2971     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2972     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2973     tcg_temp_free(t1);
2974     tcg_temp_free(t0);
2975     if (unlikely(Rc(ctx->opcode) != 0)) {
2976         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2977     }
2978 }
2979 
2980 #if defined(TARGET_PPC64)
2981 /* sld & sld. */
2982 static void gen_sld(DisasContext *ctx)
2983 {
2984     TCGv t0, t1;
2985 
2986     t0 = tcg_temp_new();
2987     /* AND rS with a mask that is 0 when rB >= 0x40 */
2988     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2989     tcg_gen_sari_tl(t0, t0, 0x3f);
2990     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2991     t1 = tcg_temp_new();
2992     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2993     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2994     tcg_temp_free(t1);
2995     tcg_temp_free(t0);
2996     if (unlikely(Rc(ctx->opcode) != 0)) {
2997         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2998     }
2999 }
3000 
3001 /* srad & srad. */
3002 static void gen_srad(DisasContext *ctx)
3003 {
3004     gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
3005                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3006     if (unlikely(Rc(ctx->opcode) != 0)) {
3007         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3008     }
3009 }
3010 /* sradi & sradi. */
3011 static inline void gen_sradi(DisasContext *ctx, int n)
3012 {
3013     int sh = SH(ctx->opcode) + (n << 5);
3014     TCGv dst = cpu_gpr[rA(ctx->opcode)];
3015     TCGv src = cpu_gpr[rS(ctx->opcode)];
3016     if (sh == 0) {
3017         tcg_gen_mov_tl(dst, src);
3018         tcg_gen_movi_tl(cpu_ca, 0);
3019         if (is_isa300(ctx)) {
3020             tcg_gen_movi_tl(cpu_ca32, 0);
3021         }
3022     } else {
3023         TCGv t0;
3024         tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
3025         t0 = tcg_temp_new();
3026         tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
3027         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3028         tcg_temp_free(t0);
3029         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3030         if (is_isa300(ctx)) {
3031             tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3032         }
3033         tcg_gen_sari_tl(dst, src, sh);
3034     }
3035     if (unlikely(Rc(ctx->opcode) != 0)) {
3036         gen_set_Rc0(ctx, dst);
3037     }
3038 }
3039 
3040 static void gen_sradi0(DisasContext *ctx)
3041 {
3042     gen_sradi(ctx, 0);
3043 }
3044 
3045 static void gen_sradi1(DisasContext *ctx)
3046 {
3047     gen_sradi(ctx, 1);
3048 }
3049 
3050 /* extswsli & extswsli. */
3051 static inline void gen_extswsli(DisasContext *ctx, int n)
3052 {
3053     int sh = SH(ctx->opcode) + (n << 5);
3054     TCGv dst = cpu_gpr[rA(ctx->opcode)];
3055     TCGv src = cpu_gpr[rS(ctx->opcode)];
3056 
3057     tcg_gen_ext32s_tl(dst, src);
3058     tcg_gen_shli_tl(dst, dst, sh);
3059     if (unlikely(Rc(ctx->opcode) != 0)) {
3060         gen_set_Rc0(ctx, dst);
3061     }
3062 }
3063 
3064 static void gen_extswsli0(DisasContext *ctx)
3065 {
3066     gen_extswsli(ctx, 0);
3067 }
3068 
3069 static void gen_extswsli1(DisasContext *ctx)
3070 {
3071     gen_extswsli(ctx, 1);
3072 }
3073 
3074 /* srd & srd. */
3075 static void gen_srd(DisasContext *ctx)
3076 {
3077     TCGv t0, t1;
3078 
3079     t0 = tcg_temp_new();
3080     /* AND rS with a mask that is 0 when rB >= 0x40 */
3081     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3082     tcg_gen_sari_tl(t0, t0, 0x3f);
3083     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3084     t1 = tcg_temp_new();
3085     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3086     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3087     tcg_temp_free(t1);
3088     tcg_temp_free(t0);
3089     if (unlikely(Rc(ctx->opcode) != 0)) {
3090         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3091     }
3092 }
3093 #endif
3094 
3095 /***                           Addressing modes                            ***/
3096 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3097 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3098                                       target_long maskl)
3099 {
3100     target_long simm = SIMM(ctx->opcode);
3101 
3102     simm &= ~maskl;
3103     if (rA(ctx->opcode) == 0) {
3104         if (NARROW_MODE(ctx)) {
3105             simm = (uint32_t)simm;
3106         }
3107         tcg_gen_movi_tl(EA, simm);
3108     } else if (likely(simm != 0)) {
3109         tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3110         if (NARROW_MODE(ctx)) {
3111             tcg_gen_ext32u_tl(EA, EA);
3112         }
3113     } else {
3114         if (NARROW_MODE(ctx)) {
3115             tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3116         } else {
3117             tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3118         }
3119     }
3120 }
3121 
3122 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3123 {
3124     if (rA(ctx->opcode) == 0) {
3125         if (NARROW_MODE(ctx)) {
3126             tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3127         } else {
3128             tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3129         }
3130     } else {
3131         tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3132         if (NARROW_MODE(ctx)) {
3133             tcg_gen_ext32u_tl(EA, EA);
3134         }
3135     }
3136 }
3137 
3138 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3139 {
3140     if (rA(ctx->opcode) == 0) {
3141         tcg_gen_movi_tl(EA, 0);
3142     } else if (NARROW_MODE(ctx)) {
3143         tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3144     } else {
3145         tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3146     }
3147 }
3148 
3149 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3150                                 target_long val)
3151 {
3152     tcg_gen_addi_tl(ret, arg1, val);
3153     if (NARROW_MODE(ctx)) {
3154         tcg_gen_ext32u_tl(ret, ret);
3155     }
3156 }
3157 
3158 static inline void gen_align_no_le(DisasContext *ctx)
3159 {
3160     gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3161                       (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3162 }
3163 
3164 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ)
3165 {
3166     TCGv ea = tcg_temp_new();
3167     if (ra) {
3168         tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
3169     } else {
3170         tcg_gen_mov_tl(ea, displ);
3171     }
3172     if (NARROW_MODE(ctx)) {
3173         tcg_gen_ext32u_tl(ea, ea);
3174     }
3175     return ea;
3176 }
3177 
3178 /***                             Integer load                              ***/
3179 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3180 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3181 
3182 #define GEN_QEMU_LOAD_TL(ldop, op)                                      \
3183 static void glue(gen_qemu_, ldop)(DisasContext *ctx,                    \
3184                                   TCGv val,                             \
3185                                   TCGv addr)                            \
3186 {                                                                       \
3187     tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op);                    \
3188 }
3189 
3190 GEN_QEMU_LOAD_TL(ld8u,  DEF_MEMOP(MO_UB))
3191 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3192 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3193 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3194 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3195 
3196 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3197 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3198 
3199 #define GEN_QEMU_LOAD_64(ldop, op)                                  \
3200 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx,    \
3201                                              TCGv_i64 val,          \
3202                                              TCGv addr)             \
3203 {                                                                   \
3204     tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op);               \
3205 }
3206 
3207 GEN_QEMU_LOAD_64(ld8u,  DEF_MEMOP(MO_UB))
3208 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3209 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3210 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3211 GEN_QEMU_LOAD_64(ld64,  DEF_MEMOP(MO_UQ))
3212 
3213 #if defined(TARGET_PPC64)
3214 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
3215 #endif
3216 
3217 #define GEN_QEMU_STORE_TL(stop, op)                                     \
3218 static void glue(gen_qemu_, stop)(DisasContext *ctx,                    \
3219                                   TCGv val,                             \
3220                                   TCGv addr)                            \
3221 {                                                                       \
3222     tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op);                    \
3223 }
3224 
3225 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
3226 GEN_QEMU_STORE_TL(st8,  DEF_MEMOP(MO_UB))
3227 #endif
3228 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3229 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3230 
3231 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3232 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3233 
3234 #define GEN_QEMU_STORE_64(stop, op)                               \
3235 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx,  \
3236                                               TCGv_i64 val,       \
3237                                               TCGv addr)          \
3238 {                                                                 \
3239     tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op);             \
3240 }
3241 
3242 GEN_QEMU_STORE_64(st8,  DEF_MEMOP(MO_UB))
3243 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3244 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3245 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ))
3246 
3247 #if defined(TARGET_PPC64)
3248 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
3249 #endif
3250 
3251 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
3252 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3253 {                                                                             \
3254     TCGv EA;                                                                  \
3255     chk;                                                                      \
3256     gen_set_access_type(ctx, ACCESS_INT);                                     \
3257     EA = tcg_temp_new();                                                      \
3258     gen_addr_reg_index(ctx, EA);                                              \
3259     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
3260     tcg_temp_free(EA);                                                        \
3261 }
3262 
3263 #define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
3264     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3265 
3266 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type)                            \
3267     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3268 
3269 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
3270 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3271 {                                                                             \
3272     TCGv EA;                                                                  \
3273     CHK_SV;                                                                   \
3274     gen_set_access_type(ctx, ACCESS_INT);                                     \
3275     EA = tcg_temp_new();                                                      \
3276     gen_addr_reg_index(ctx, EA);                                              \
3277     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3278     tcg_temp_free(EA);                                                        \
3279 }
3280 
3281 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3282 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3283 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3284 #if defined(TARGET_PPC64)
3285 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
3286 #endif
3287 
3288 #if defined(TARGET_PPC64)
3289 /* CI load/store variants */
3290 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3291 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3292 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3293 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3294 #endif
3295 
3296 /***                              Integer store                            ***/
3297 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
3298 static void glue(gen_, name##x)(DisasContext *ctx)                            \
3299 {                                                                             \
3300     TCGv EA;                                                                  \
3301     chk;                                                                      \
3302     gen_set_access_type(ctx, ACCESS_INT);                                     \
3303     EA = tcg_temp_new();                                                      \
3304     gen_addr_reg_index(ctx, EA);                                              \
3305     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3306     tcg_temp_free(EA);                                                        \
3307 }
3308 #define GEN_STX(name, stop, opc2, opc3, type)                                 \
3309     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3310 
3311 #define GEN_STX_HVRM(name, stop, opc2, opc3, type)                            \
3312     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3313 
3314 #define GEN_STEPX(name, stop, opc2, opc3)                                     \
3315 static void glue(gen_, name##epx)(DisasContext *ctx)                          \
3316 {                                                                             \
3317     TCGv EA;                                                                  \
3318     CHK_SV;                                                                   \
3319     gen_set_access_type(ctx, ACCESS_INT);                                     \
3320     EA = tcg_temp_new();                                                      \
3321     gen_addr_reg_index(ctx, EA);                                              \
3322     tcg_gen_qemu_st_tl(                                                       \
3323         cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop);              \
3324     tcg_temp_free(EA);                                                        \
3325 }
3326 
3327 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3328 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3329 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3330 #if defined(TARGET_PPC64)
3331 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04)
3332 #endif
3333 
3334 #if defined(TARGET_PPC64)
3335 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3336 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3337 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3338 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3339 #endif
3340 /***                Integer load and store with byte reverse               ***/
3341 
3342 /* lhbrx */
3343 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3344 
3345 /* lwbrx */
3346 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3347 
3348 #if defined(TARGET_PPC64)
3349 /* ldbrx */
3350 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3351 /* stdbrx */
3352 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3353 #endif  /* TARGET_PPC64 */
3354 
3355 /* sthbrx */
3356 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3357 /* stwbrx */
3358 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3359 
3360 /***                    Integer load and store multiple                    ***/
3361 
3362 /* lmw */
3363 static void gen_lmw(DisasContext *ctx)
3364 {
3365     TCGv t0;
3366     TCGv_i32 t1;
3367 
3368     if (ctx->le_mode) {
3369         gen_align_no_le(ctx);
3370         return;
3371     }
3372     gen_set_access_type(ctx, ACCESS_INT);
3373     t0 = tcg_temp_new();
3374     t1 = tcg_const_i32(rD(ctx->opcode));
3375     gen_addr_imm_index(ctx, t0, 0);
3376     gen_helper_lmw(cpu_env, t0, t1);
3377     tcg_temp_free(t0);
3378     tcg_temp_free_i32(t1);
3379 }
3380 
3381 /* stmw */
3382 static void gen_stmw(DisasContext *ctx)
3383 {
3384     TCGv t0;
3385     TCGv_i32 t1;
3386 
3387     if (ctx->le_mode) {
3388         gen_align_no_le(ctx);
3389         return;
3390     }
3391     gen_set_access_type(ctx, ACCESS_INT);
3392     t0 = tcg_temp_new();
3393     t1 = tcg_const_i32(rS(ctx->opcode));
3394     gen_addr_imm_index(ctx, t0, 0);
3395     gen_helper_stmw(cpu_env, t0, t1);
3396     tcg_temp_free(t0);
3397     tcg_temp_free_i32(t1);
3398 }
3399 
3400 /***                    Integer load and store strings                     ***/
3401 
3402 /* lswi */
3403 /*
3404  * PowerPC32 specification says we must generate an exception if rA is
3405  * in the range of registers to be loaded.  In an other hand, IBM says
3406  * this is valid, but rA won't be loaded.  For now, I'll follow the
3407  * spec...
3408  */
3409 static void gen_lswi(DisasContext *ctx)
3410 {
3411     TCGv t0;
3412     TCGv_i32 t1, t2;
3413     int nb = NB(ctx->opcode);
3414     int start = rD(ctx->opcode);
3415     int ra = rA(ctx->opcode);
3416     int nr;
3417 
3418     if (ctx->le_mode) {
3419         gen_align_no_le(ctx);
3420         return;
3421     }
3422     if (nb == 0) {
3423         nb = 32;
3424     }
3425     nr = DIV_ROUND_UP(nb, 4);
3426     if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3427         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3428         return;
3429     }
3430     gen_set_access_type(ctx, ACCESS_INT);
3431     t0 = tcg_temp_new();
3432     gen_addr_register(ctx, t0);
3433     t1 = tcg_const_i32(nb);
3434     t2 = tcg_const_i32(start);
3435     gen_helper_lsw(cpu_env, t0, t1, t2);
3436     tcg_temp_free(t0);
3437     tcg_temp_free_i32(t1);
3438     tcg_temp_free_i32(t2);
3439 }
3440 
3441 /* lswx */
3442 static void gen_lswx(DisasContext *ctx)
3443 {
3444     TCGv t0;
3445     TCGv_i32 t1, t2, t3;
3446 
3447     if (ctx->le_mode) {
3448         gen_align_no_le(ctx);
3449         return;
3450     }
3451     gen_set_access_type(ctx, ACCESS_INT);
3452     t0 = tcg_temp_new();
3453     gen_addr_reg_index(ctx, t0);
3454     t1 = tcg_const_i32(rD(ctx->opcode));
3455     t2 = tcg_const_i32(rA(ctx->opcode));
3456     t3 = tcg_const_i32(rB(ctx->opcode));
3457     gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3458     tcg_temp_free(t0);
3459     tcg_temp_free_i32(t1);
3460     tcg_temp_free_i32(t2);
3461     tcg_temp_free_i32(t3);
3462 }
3463 
3464 /* stswi */
3465 static void gen_stswi(DisasContext *ctx)
3466 {
3467     TCGv t0;
3468     TCGv_i32 t1, t2;
3469     int nb = NB(ctx->opcode);
3470 
3471     if (ctx->le_mode) {
3472         gen_align_no_le(ctx);
3473         return;
3474     }
3475     gen_set_access_type(ctx, ACCESS_INT);
3476     t0 = tcg_temp_new();
3477     gen_addr_register(ctx, t0);
3478     if (nb == 0) {
3479         nb = 32;
3480     }
3481     t1 = tcg_const_i32(nb);
3482     t2 = tcg_const_i32(rS(ctx->opcode));
3483     gen_helper_stsw(cpu_env, t0, t1, t2);
3484     tcg_temp_free(t0);
3485     tcg_temp_free_i32(t1);
3486     tcg_temp_free_i32(t2);
3487 }
3488 
3489 /* stswx */
3490 static void gen_stswx(DisasContext *ctx)
3491 {
3492     TCGv t0;
3493     TCGv_i32 t1, t2;
3494 
3495     if (ctx->le_mode) {
3496         gen_align_no_le(ctx);
3497         return;
3498     }
3499     gen_set_access_type(ctx, ACCESS_INT);
3500     t0 = tcg_temp_new();
3501     gen_addr_reg_index(ctx, t0);
3502     t1 = tcg_temp_new_i32();
3503     tcg_gen_trunc_tl_i32(t1, cpu_xer);
3504     tcg_gen_andi_i32(t1, t1, 0x7F);
3505     t2 = tcg_const_i32(rS(ctx->opcode));
3506     gen_helper_stsw(cpu_env, t0, t1, t2);
3507     tcg_temp_free(t0);
3508     tcg_temp_free_i32(t1);
3509     tcg_temp_free_i32(t2);
3510 }
3511 
3512 /***                        Memory synchronisation                         ***/
3513 /* eieio */
3514 static void gen_eieio(DisasContext *ctx)
3515 {
3516     TCGBar bar = TCG_MO_ALL;
3517 
3518     /*
3519      * eieio has complex semanitcs. It provides memory ordering between
3520      * operations in the set:
3521      * - loads from CI memory.
3522      * - stores to CI memory.
3523      * - stores to WT memory.
3524      *
3525      * It separately also orders memory for operations in the set:
3526      * - stores to cacheble memory.
3527      *
3528      * It also serializes instructions:
3529      * - dcbt and dcbst.
3530      *
3531      * It separately serializes:
3532      * - tlbie and tlbsync.
3533      *
3534      * And separately serializes:
3535      * - slbieg, slbiag, and slbsync.
3536      *
3537      * The end result is that CI memory ordering requires TCG_MO_ALL
3538      * and it is not possible to special-case more relaxed ordering for
3539      * cacheable accesses. TCG_BAR_SC is required to provide this
3540      * serialization.
3541      */
3542 
3543     /*
3544      * POWER9 has a eieio instruction variant using bit 6 as a hint to
3545      * tell the CPU it is a store-forwarding barrier.
3546      */
3547     if (ctx->opcode & 0x2000000) {
3548         /*
3549          * ISA says that "Reserved fields in instructions are ignored
3550          * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3551          * as this is not an instruction software should be using,
3552          * complain to the user.
3553          */
3554         if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3555             qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3556                           TARGET_FMT_lx "\n", ctx->cia);
3557         } else {
3558             bar = TCG_MO_ST_LD;
3559         }
3560     }
3561 
3562     tcg_gen_mb(bar | TCG_BAR_SC);
3563 }
3564 
3565 #if !defined(CONFIG_USER_ONLY)
3566 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3567 {
3568     TCGv_i32 t;
3569     TCGLabel *l;
3570 
3571     if (!ctx->lazy_tlb_flush) {
3572         return;
3573     }
3574     l = gen_new_label();
3575     t = tcg_temp_new_i32();
3576     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3577     tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3578     if (global) {
3579         gen_helper_check_tlb_flush_global(cpu_env);
3580     } else {
3581         gen_helper_check_tlb_flush_local(cpu_env);
3582     }
3583     gen_set_label(l);
3584     tcg_temp_free_i32(t);
3585 }
3586 #else
3587 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3588 #endif
3589 
3590 /* isync */
3591 static void gen_isync(DisasContext *ctx)
3592 {
3593     /*
3594      * We need to check for a pending TLB flush. This can only happen in
3595      * kernel mode however so check MSR_PR
3596      */
3597     if (!ctx->pr) {
3598         gen_check_tlb_flush(ctx, false);
3599     }
3600     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3601     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
3602 }
3603 
3604 #define MEMOP_GET_SIZE(x)  (1 << ((x) & MO_SIZE))
3605 
3606 static void gen_load_locked(DisasContext *ctx, MemOp memop)
3607 {
3608     TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3609     TCGv t0 = tcg_temp_new();
3610 
3611     gen_set_access_type(ctx, ACCESS_RES);
3612     gen_addr_reg_index(ctx, t0);
3613     tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3614     tcg_gen_mov_tl(cpu_reserve, t0);
3615     tcg_gen_mov_tl(cpu_reserve_val, gpr);
3616     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3617     tcg_temp_free(t0);
3618 }
3619 
3620 #define LARX(name, memop)                  \
3621 static void gen_##name(DisasContext *ctx)  \
3622 {                                          \
3623     gen_load_locked(ctx, memop);           \
3624 }
3625 
3626 /* lwarx */
3627 LARX(lbarx, DEF_MEMOP(MO_UB))
3628 LARX(lharx, DEF_MEMOP(MO_UW))
3629 LARX(lwarx, DEF_MEMOP(MO_UL))
3630 
3631 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
3632                                       TCGv EA, TCGCond cond, int addend)
3633 {
3634     TCGv t = tcg_temp_new();
3635     TCGv t2 = tcg_temp_new();
3636     TCGv u = tcg_temp_new();
3637 
3638     tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3639     tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3640     tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3641     tcg_gen_addi_tl(u, t, addend);
3642 
3643     /* E.g. for fetch and increment bounded... */
3644     /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3645     tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3646     tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3647 
3648     /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3649     tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3650     tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3651 
3652     tcg_temp_free(t);
3653     tcg_temp_free(t2);
3654     tcg_temp_free(u);
3655 }
3656 
3657 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
3658 {
3659     uint32_t gpr_FC = FC(ctx->opcode);
3660     TCGv EA = tcg_temp_new();
3661     int rt = rD(ctx->opcode);
3662     bool need_serial;
3663     TCGv src, dst;
3664 
3665     gen_addr_register(ctx, EA);
3666     dst = cpu_gpr[rt];
3667     src = cpu_gpr[(rt + 1) & 31];
3668 
3669     need_serial = false;
3670     memop |= MO_ALIGN;
3671     switch (gpr_FC) {
3672     case 0: /* Fetch and add */
3673         tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3674         break;
3675     case 1: /* Fetch and xor */
3676         tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3677         break;
3678     case 2: /* Fetch and or */
3679         tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3680         break;
3681     case 3: /* Fetch and 'and' */
3682         tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3683         break;
3684     case 4:  /* Fetch and max unsigned */
3685         tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3686         break;
3687     case 5:  /* Fetch and max signed */
3688         tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3689         break;
3690     case 6:  /* Fetch and min unsigned */
3691         tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3692         break;
3693     case 7:  /* Fetch and min signed */
3694         tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3695         break;
3696     case 8: /* Swap */
3697         tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3698         break;
3699 
3700     case 16: /* Compare and swap not equal */
3701         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3702             need_serial = true;
3703         } else {
3704             TCGv t0 = tcg_temp_new();
3705             TCGv t1 = tcg_temp_new();
3706 
3707             tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3708             if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3709                 tcg_gen_mov_tl(t1, src);
3710             } else {
3711                 tcg_gen_ext32u_tl(t1, src);
3712             }
3713             tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3714                                cpu_gpr[(rt + 2) & 31], t0);
3715             tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3716             tcg_gen_mov_tl(dst, t0);
3717 
3718             tcg_temp_free(t0);
3719             tcg_temp_free(t1);
3720         }
3721         break;
3722 
3723     case 24: /* Fetch and increment bounded */
3724         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3725             need_serial = true;
3726         } else {
3727             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3728         }
3729         break;
3730     case 25: /* Fetch and increment equal */
3731         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3732             need_serial = true;
3733         } else {
3734             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3735         }
3736         break;
3737     case 28: /* Fetch and decrement bounded */
3738         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3739             need_serial = true;
3740         } else {
3741             gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3742         }
3743         break;
3744 
3745     default:
3746         /* invoke data storage error handler */
3747         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3748     }
3749     tcg_temp_free(EA);
3750 
3751     if (need_serial) {
3752         /* Restart with exclusive lock.  */
3753         gen_helper_exit_atomic(cpu_env);
3754         ctx->base.is_jmp = DISAS_NORETURN;
3755     }
3756 }
3757 
3758 static void gen_lwat(DisasContext *ctx)
3759 {
3760     gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3761 }
3762 
3763 #ifdef TARGET_PPC64
3764 static void gen_ldat(DisasContext *ctx)
3765 {
3766     gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ));
3767 }
3768 #endif
3769 
3770 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
3771 {
3772     uint32_t gpr_FC = FC(ctx->opcode);
3773     TCGv EA = tcg_temp_new();
3774     TCGv src, discard;
3775 
3776     gen_addr_register(ctx, EA);
3777     src = cpu_gpr[rD(ctx->opcode)];
3778     discard = tcg_temp_new();
3779 
3780     memop |= MO_ALIGN;
3781     switch (gpr_FC) {
3782     case 0: /* add and Store */
3783         tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3784         break;
3785     case 1: /* xor and Store */
3786         tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3787         break;
3788     case 2: /* Or and Store */
3789         tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3790         break;
3791     case 3: /* 'and' and Store */
3792         tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3793         break;
3794     case 4:  /* Store max unsigned */
3795         tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3796         break;
3797     case 5:  /* Store max signed */
3798         tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3799         break;
3800     case 6:  /* Store min unsigned */
3801         tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3802         break;
3803     case 7:  /* Store min signed */
3804         tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3805         break;
3806     case 24: /* Store twin  */
3807         if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3808             /* Restart with exclusive lock.  */
3809             gen_helper_exit_atomic(cpu_env);
3810             ctx->base.is_jmp = DISAS_NORETURN;
3811         } else {
3812             TCGv t = tcg_temp_new();
3813             TCGv t2 = tcg_temp_new();
3814             TCGv s = tcg_temp_new();
3815             TCGv s2 = tcg_temp_new();
3816             TCGv ea_plus_s = tcg_temp_new();
3817 
3818             tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3819             tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3820             tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3821             tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3822             tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3823             tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3824             tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3825 
3826             tcg_temp_free(ea_plus_s);
3827             tcg_temp_free(s2);
3828             tcg_temp_free(s);
3829             tcg_temp_free(t2);
3830             tcg_temp_free(t);
3831         }
3832         break;
3833     default:
3834         /* invoke data storage error handler */
3835         gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3836     }
3837     tcg_temp_free(discard);
3838     tcg_temp_free(EA);
3839 }
3840 
3841 static void gen_stwat(DisasContext *ctx)
3842 {
3843     gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3844 }
3845 
3846 #ifdef TARGET_PPC64
3847 static void gen_stdat(DisasContext *ctx)
3848 {
3849     gen_st_atomic(ctx, DEF_MEMOP(MO_UQ));
3850 }
3851 #endif
3852 
3853 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
3854 {
3855     TCGLabel *l1 = gen_new_label();
3856     TCGLabel *l2 = gen_new_label();
3857     TCGv t0 = tcg_temp_new();
3858     int reg = rS(ctx->opcode);
3859 
3860     gen_set_access_type(ctx, ACCESS_RES);
3861     gen_addr_reg_index(ctx, t0);
3862     tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3863     tcg_temp_free(t0);
3864 
3865     t0 = tcg_temp_new();
3866     tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3867                               cpu_gpr[reg], ctx->mem_idx,
3868                               DEF_MEMOP(memop) | MO_ALIGN);
3869     tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3870     tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3871     tcg_gen_or_tl(t0, t0, cpu_so);
3872     tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3873     tcg_temp_free(t0);
3874     tcg_gen_br(l2);
3875 
3876     gen_set_label(l1);
3877 
3878     /*
3879      * Address mismatch implies failure.  But we still need to provide
3880      * the memory barrier semantics of the instruction.
3881      */
3882     tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3883     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3884 
3885     gen_set_label(l2);
3886     tcg_gen_movi_tl(cpu_reserve, -1);
3887 }
3888 
3889 #define STCX(name, memop)                  \
3890 static void gen_##name(DisasContext *ctx)  \
3891 {                                          \
3892     gen_conditional_store(ctx, memop);     \
3893 }
3894 
3895 STCX(stbcx_, DEF_MEMOP(MO_UB))
3896 STCX(sthcx_, DEF_MEMOP(MO_UW))
3897 STCX(stwcx_, DEF_MEMOP(MO_UL))
3898 
3899 #if defined(TARGET_PPC64)
3900 /* ldarx */
3901 LARX(ldarx, DEF_MEMOP(MO_UQ))
3902 /* stdcx. */
3903 STCX(stdcx_, DEF_MEMOP(MO_UQ))
3904 
3905 /* lqarx */
3906 static void gen_lqarx(DisasContext *ctx)
3907 {
3908     int rd = rD(ctx->opcode);
3909     TCGv EA, hi, lo;
3910 
3911     if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3912                  (rd == rB(ctx->opcode)))) {
3913         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3914         return;
3915     }
3916 
3917     gen_set_access_type(ctx, ACCESS_RES);
3918     EA = tcg_temp_new();
3919     gen_addr_reg_index(ctx, EA);
3920 
3921     /* Note that the low part is always in RD+1, even in LE mode.  */
3922     lo = cpu_gpr[rd + 1];
3923     hi = cpu_gpr[rd];
3924 
3925     if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3926         if (HAVE_ATOMIC128) {
3927             TCGv_i32 oi = tcg_temp_new_i32();
3928             if (ctx->le_mode) {
3929                 tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN,
3930                                                     ctx->mem_idx));
3931                 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3932             } else {
3933                 tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN,
3934                                                     ctx->mem_idx));
3935                 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3936             }
3937             tcg_temp_free_i32(oi);
3938             tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3939         } else {
3940             /* Restart with exclusive lock.  */
3941             gen_helper_exit_atomic(cpu_env);
3942             ctx->base.is_jmp = DISAS_NORETURN;
3943             tcg_temp_free(EA);
3944             return;
3945         }
3946     } else if (ctx->le_mode) {
3947         tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16);
3948         tcg_gen_mov_tl(cpu_reserve, EA);
3949         gen_addr_add(ctx, EA, EA, 8);
3950         tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ);
3951     } else {
3952         tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16);
3953         tcg_gen_mov_tl(cpu_reserve, EA);
3954         gen_addr_add(ctx, EA, EA, 8);
3955         tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ);
3956     }
3957     tcg_temp_free(EA);
3958 
3959     tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3960     tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3961 }
3962 
3963 /* stqcx. */
3964 static void gen_stqcx_(DisasContext *ctx)
3965 {
3966     int rs = rS(ctx->opcode);
3967     TCGv EA, hi, lo;
3968 
3969     if (unlikely(rs & 1)) {
3970         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3971         return;
3972     }
3973 
3974     gen_set_access_type(ctx, ACCESS_RES);
3975     EA = tcg_temp_new();
3976     gen_addr_reg_index(ctx, EA);
3977 
3978     /* Note that the low part is always in RS+1, even in LE mode.  */
3979     lo = cpu_gpr[rs + 1];
3980     hi = cpu_gpr[rs];
3981 
3982     if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3983         if (HAVE_CMPXCHG128) {
3984             TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN);
3985             if (ctx->le_mode) {
3986                 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
3987                                              EA, lo, hi, oi);
3988             } else {
3989                 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
3990                                              EA, lo, hi, oi);
3991             }
3992             tcg_temp_free_i32(oi);
3993         } else {
3994             /* Restart with exclusive lock.  */
3995             gen_helper_exit_atomic(cpu_env);
3996             ctx->base.is_jmp = DISAS_NORETURN;
3997         }
3998         tcg_temp_free(EA);
3999     } else {
4000         TCGLabel *lab_fail = gen_new_label();
4001         TCGLabel *lab_over = gen_new_label();
4002         TCGv_i64 t0 = tcg_temp_new_i64();
4003         TCGv_i64 t1 = tcg_temp_new_i64();
4004 
4005         tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
4006         tcg_temp_free(EA);
4007 
4008         gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
4009         tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4010                                      ? offsetof(CPUPPCState, reserve_val2)
4011                                      : offsetof(CPUPPCState, reserve_val)));
4012         tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4013 
4014         tcg_gen_addi_i64(t0, cpu_reserve, 8);
4015         gen_qemu_ld64_i64(ctx, t0, t0);
4016         tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4017                                      ? offsetof(CPUPPCState, reserve_val)
4018                                      : offsetof(CPUPPCState, reserve_val2)));
4019         tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4020 
4021         /* Success */
4022         gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
4023         tcg_gen_addi_i64(t0, cpu_reserve, 8);
4024         gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
4025 
4026         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4027         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4028         tcg_gen_br(lab_over);
4029 
4030         gen_set_label(lab_fail);
4031         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4032 
4033         gen_set_label(lab_over);
4034         tcg_gen_movi_tl(cpu_reserve, -1);
4035         tcg_temp_free_i64(t0);
4036         tcg_temp_free_i64(t1);
4037     }
4038 }
4039 #endif /* defined(TARGET_PPC64) */
4040 
4041 /* sync */
4042 static void gen_sync(DisasContext *ctx)
4043 {
4044     TCGBar bar = TCG_MO_ALL;
4045     uint32_t l = (ctx->opcode >> 21) & 3;
4046 
4047     if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
4048         bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
4049     }
4050 
4051     /*
4052      * We may need to check for a pending TLB flush.
4053      *
4054      * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4055      *
4056      * Additionally, this can only happen in kernel mode however so
4057      * check MSR_PR as well.
4058      */
4059     if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
4060         gen_check_tlb_flush(ctx, true);
4061     }
4062 
4063     tcg_gen_mb(bar | TCG_BAR_SC);
4064 }
4065 
4066 /* wait */
4067 static void gen_wait(DisasContext *ctx)
4068 {
4069     TCGv_i32 t0 = tcg_const_i32(1);
4070     tcg_gen_st_i32(t0, cpu_env,
4071                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
4072     tcg_temp_free_i32(t0);
4073     /* Stop translation, as the CPU is supposed to sleep from now */
4074     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4075 }
4076 
4077 #if defined(TARGET_PPC64)
4078 static void gen_doze(DisasContext *ctx)
4079 {
4080 #if defined(CONFIG_USER_ONLY)
4081     GEN_PRIV;
4082 #else
4083     TCGv_i32 t;
4084 
4085     CHK_HV;
4086     t = tcg_const_i32(PPC_PM_DOZE);
4087     gen_helper_pminsn(cpu_env, t);
4088     tcg_temp_free_i32(t);
4089     /* Stop translation, as the CPU is supposed to sleep from now */
4090     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4091 #endif /* defined(CONFIG_USER_ONLY) */
4092 }
4093 
4094 static void gen_nap(DisasContext *ctx)
4095 {
4096 #if defined(CONFIG_USER_ONLY)
4097     GEN_PRIV;
4098 #else
4099     TCGv_i32 t;
4100 
4101     CHK_HV;
4102     t = tcg_const_i32(PPC_PM_NAP);
4103     gen_helper_pminsn(cpu_env, t);
4104     tcg_temp_free_i32(t);
4105     /* Stop translation, as the CPU is supposed to sleep from now */
4106     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4107 #endif /* defined(CONFIG_USER_ONLY) */
4108 }
4109 
4110 static void gen_stop(DisasContext *ctx)
4111 {
4112 #if defined(CONFIG_USER_ONLY)
4113     GEN_PRIV;
4114 #else
4115     TCGv_i32 t;
4116 
4117     CHK_HV;
4118     t = tcg_const_i32(PPC_PM_STOP);
4119     gen_helper_pminsn(cpu_env, t);
4120     tcg_temp_free_i32(t);
4121     /* Stop translation, as the CPU is supposed to sleep from now */
4122     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4123 #endif /* defined(CONFIG_USER_ONLY) */
4124 }
4125 
4126 static void gen_sleep(DisasContext *ctx)
4127 {
4128 #if defined(CONFIG_USER_ONLY)
4129     GEN_PRIV;
4130 #else
4131     TCGv_i32 t;
4132 
4133     CHK_HV;
4134     t = tcg_const_i32(PPC_PM_SLEEP);
4135     gen_helper_pminsn(cpu_env, t);
4136     tcg_temp_free_i32(t);
4137     /* Stop translation, as the CPU is supposed to sleep from now */
4138     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4139 #endif /* defined(CONFIG_USER_ONLY) */
4140 }
4141 
4142 static void gen_rvwinkle(DisasContext *ctx)
4143 {
4144 #if defined(CONFIG_USER_ONLY)
4145     GEN_PRIV;
4146 #else
4147     TCGv_i32 t;
4148 
4149     CHK_HV;
4150     t = tcg_const_i32(PPC_PM_RVWINKLE);
4151     gen_helper_pminsn(cpu_env, t);
4152     tcg_temp_free_i32(t);
4153     /* Stop translation, as the CPU is supposed to sleep from now */
4154     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4155 #endif /* defined(CONFIG_USER_ONLY) */
4156 }
4157 #endif /* #if defined(TARGET_PPC64) */
4158 
4159 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4160 {
4161 #if defined(TARGET_PPC64)
4162     if (ctx->has_cfar) {
4163         tcg_gen_movi_tl(cpu_cfar, nip);
4164     }
4165 #endif
4166 }
4167 
4168 #if defined(TARGET_PPC64)
4169 static void pmu_count_insns(DisasContext *ctx)
4170 {
4171     /*
4172      * Do not bother calling the helper if the PMU isn't counting
4173      * instructions.
4174      */
4175     if (!ctx->pmu_insn_cnt) {
4176         return;
4177     }
4178 
4179  #if !defined(CONFIG_USER_ONLY)
4180     /*
4181      * The PMU insns_inc() helper stops the internal PMU timer if a
4182      * counter overflows happens. In that case, if the guest is
4183      * running with icount and we do not handle it beforehand,
4184      * the helper can trigger a 'bad icount read'.
4185      */
4186     gen_icount_io_start(ctx);
4187 
4188     gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns));
4189 #else
4190     /*
4191      * User mode can read (but not write) PMC5 and start/stop
4192      * the PMU via MMCR0_FC. In this case just increment
4193      * PMC5 with base.num_insns.
4194      */
4195     TCGv t0 = tcg_temp_new();
4196 
4197     gen_load_spr(t0, SPR_POWER_PMC5);
4198     tcg_gen_addi_tl(t0, t0, ctx->base.num_insns);
4199     gen_store_spr(SPR_POWER_PMC5, t0);
4200 
4201     tcg_temp_free(t0);
4202 #endif /* #if !defined(CONFIG_USER_ONLY) */
4203 }
4204 #else
4205 static void pmu_count_insns(DisasContext *ctx)
4206 {
4207     return;
4208 }
4209 #endif /* #if defined(TARGET_PPC64) */
4210 
4211 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4212 {
4213     return translator_use_goto_tb(&ctx->base, dest);
4214 }
4215 
4216 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4217 {
4218     if (unlikely(ctx->singlestep_enabled)) {
4219         gen_debug_exception(ctx);
4220     } else {
4221         /*
4222          * tcg_gen_lookup_and_goto_ptr will exit the TB if
4223          * CF_NO_GOTO_PTR is set. Count insns now.
4224          */
4225         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
4226             pmu_count_insns(ctx);
4227         }
4228 
4229         tcg_gen_lookup_and_goto_ptr();
4230     }
4231 }
4232 
4233 /***                                Branch                                 ***/
4234 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4235 {
4236     if (NARROW_MODE(ctx)) {
4237         dest = (uint32_t) dest;
4238     }
4239     if (use_goto_tb(ctx, dest)) {
4240         pmu_count_insns(ctx);
4241         tcg_gen_goto_tb(n);
4242         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4243         tcg_gen_exit_tb(ctx->base.tb, n);
4244     } else {
4245         tcg_gen_movi_tl(cpu_nip, dest & ~3);
4246         gen_lookup_and_goto_ptr(ctx);
4247     }
4248 }
4249 
4250 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4251 {
4252     if (NARROW_MODE(ctx)) {
4253         nip = (uint32_t)nip;
4254     }
4255     tcg_gen_movi_tl(cpu_lr, nip);
4256 }
4257 
4258 /* b ba bl bla */
4259 static void gen_b(DisasContext *ctx)
4260 {
4261     target_ulong li, target;
4262 
4263     /* sign extend LI */
4264     li = LI(ctx->opcode);
4265     li = (li ^ 0x02000000) - 0x02000000;
4266     if (likely(AA(ctx->opcode) == 0)) {
4267         target = ctx->cia + li;
4268     } else {
4269         target = li;
4270     }
4271     if (LK(ctx->opcode)) {
4272         gen_setlr(ctx, ctx->base.pc_next);
4273     }
4274     gen_update_cfar(ctx, ctx->cia);
4275     gen_goto_tb(ctx, 0, target);
4276     ctx->base.is_jmp = DISAS_NORETURN;
4277 }
4278 
4279 #define BCOND_IM  0
4280 #define BCOND_LR  1
4281 #define BCOND_CTR 2
4282 #define BCOND_TAR 3
4283 
4284 static void gen_bcond(DisasContext *ctx, int type)
4285 {
4286     uint32_t bo = BO(ctx->opcode);
4287     TCGLabel *l1;
4288     TCGv target;
4289 
4290     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4291         target = tcg_temp_local_new();
4292         if (type == BCOND_CTR) {
4293             tcg_gen_mov_tl(target, cpu_ctr);
4294         } else if (type == BCOND_TAR) {
4295             gen_load_spr(target, SPR_TAR);
4296         } else {
4297             tcg_gen_mov_tl(target, cpu_lr);
4298         }
4299     } else {
4300         target = NULL;
4301     }
4302     if (LK(ctx->opcode)) {
4303         gen_setlr(ctx, ctx->base.pc_next);
4304     }
4305     l1 = gen_new_label();
4306     if ((bo & 0x4) == 0) {
4307         /* Decrement and test CTR */
4308         TCGv temp = tcg_temp_new();
4309 
4310         if (type == BCOND_CTR) {
4311             /*
4312              * All ISAs up to v3 describe this form of bcctr as invalid but
4313              * some processors, ie. 64-bit server processors compliant with
4314              * arch 2.x, do implement a "test and decrement" logic instead,
4315              * as described in their respective UMs. This logic involves CTR
4316              * to act as both the branch target and a counter, which makes
4317              * it basically useless and thus never used in real code.
4318              *
4319              * This form was hence chosen to trigger extra micro-architectural
4320              * side-effect on real HW needed for the Spectre v2 workaround.
4321              * It is up to guests that implement such workaround, ie. linux, to
4322              * use this form in a way it just triggers the side-effect without
4323              * doing anything else harmful.
4324              */
4325             if (unlikely(!is_book3s_arch2x(ctx))) {
4326                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4327                 tcg_temp_free(temp);
4328                 tcg_temp_free(target);
4329                 return;
4330             }
4331 
4332             if (NARROW_MODE(ctx)) {
4333                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4334             } else {
4335                 tcg_gen_mov_tl(temp, cpu_ctr);
4336             }
4337             if (bo & 0x2) {
4338                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4339             } else {
4340                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4341             }
4342             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4343         } else {
4344             tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4345             if (NARROW_MODE(ctx)) {
4346                 tcg_gen_ext32u_tl(temp, cpu_ctr);
4347             } else {
4348                 tcg_gen_mov_tl(temp, cpu_ctr);
4349             }
4350             if (bo & 0x2) {
4351                 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4352             } else {
4353                 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4354             }
4355         }
4356         tcg_temp_free(temp);
4357     }
4358     if ((bo & 0x10) == 0) {
4359         /* Test CR */
4360         uint32_t bi = BI(ctx->opcode);
4361         uint32_t mask = 0x08 >> (bi & 0x03);
4362         TCGv_i32 temp = tcg_temp_new_i32();
4363 
4364         if (bo & 0x8) {
4365             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4366             tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4367         } else {
4368             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4369             tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4370         }
4371         tcg_temp_free_i32(temp);
4372     }
4373     gen_update_cfar(ctx, ctx->cia);
4374     if (type == BCOND_IM) {
4375         target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4376         if (likely(AA(ctx->opcode) == 0)) {
4377             gen_goto_tb(ctx, 0, ctx->cia + li);
4378         } else {
4379             gen_goto_tb(ctx, 0, li);
4380         }
4381     } else {
4382         if (NARROW_MODE(ctx)) {
4383             tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4384         } else {
4385             tcg_gen_andi_tl(cpu_nip, target, ~3);
4386         }
4387         gen_lookup_and_goto_ptr(ctx);
4388         tcg_temp_free(target);
4389     }
4390     if ((bo & 0x14) != 0x14) {
4391         /* fallthrough case */
4392         gen_set_label(l1);
4393         gen_goto_tb(ctx, 1, ctx->base.pc_next);
4394     }
4395     ctx->base.is_jmp = DISAS_NORETURN;
4396 }
4397 
4398 static void gen_bc(DisasContext *ctx)
4399 {
4400     gen_bcond(ctx, BCOND_IM);
4401 }
4402 
4403 static void gen_bcctr(DisasContext *ctx)
4404 {
4405     gen_bcond(ctx, BCOND_CTR);
4406 }
4407 
4408 static void gen_bclr(DisasContext *ctx)
4409 {
4410     gen_bcond(ctx, BCOND_LR);
4411 }
4412 
4413 static void gen_bctar(DisasContext *ctx)
4414 {
4415     gen_bcond(ctx, BCOND_TAR);
4416 }
4417 
4418 /***                      Condition register logical                       ***/
4419 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
4420 static void glue(gen_, name)(DisasContext *ctx)                               \
4421 {                                                                             \
4422     uint8_t bitmask;                                                          \
4423     int sh;                                                                   \
4424     TCGv_i32 t0, t1;                                                          \
4425     sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
4426     t0 = tcg_temp_new_i32();                                                  \
4427     if (sh > 0)                                                               \
4428         tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
4429     else if (sh < 0)                                                          \
4430         tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
4431     else                                                                      \
4432         tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
4433     t1 = tcg_temp_new_i32();                                                  \
4434     sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
4435     if (sh > 0)                                                               \
4436         tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
4437     else if (sh < 0)                                                          \
4438         tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
4439     else                                                                      \
4440         tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
4441     tcg_op(t0, t0, t1);                                                       \
4442     bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);                             \
4443     tcg_gen_andi_i32(t0, t0, bitmask);                                        \
4444     tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
4445     tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
4446     tcg_temp_free_i32(t0);                                                    \
4447     tcg_temp_free_i32(t1);                                                    \
4448 }
4449 
4450 /* crand */
4451 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4452 /* crandc */
4453 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4454 /* creqv */
4455 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4456 /* crnand */
4457 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4458 /* crnor */
4459 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4460 /* cror */
4461 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4462 /* crorc */
4463 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4464 /* crxor */
4465 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4466 
4467 /* mcrf */
4468 static void gen_mcrf(DisasContext *ctx)
4469 {
4470     tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4471 }
4472 
4473 /***                           System linkage                              ***/
4474 
4475 /* rfi (supervisor only) */
4476 static void gen_rfi(DisasContext *ctx)
4477 {
4478 #if defined(CONFIG_USER_ONLY)
4479     GEN_PRIV;
4480 #else
4481     /*
4482      * This instruction doesn't exist anymore on 64-bit server
4483      * processors compliant with arch 2.x
4484      */
4485     if (is_book3s_arch2x(ctx)) {
4486         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4487         return;
4488     }
4489     /* Restore CPU state */
4490     CHK_SV;
4491     gen_icount_io_start(ctx);
4492     gen_update_cfar(ctx, ctx->cia);
4493     gen_helper_rfi(cpu_env);
4494     ctx->base.is_jmp = DISAS_EXIT;
4495 #endif
4496 }
4497 
4498 #if defined(TARGET_PPC64)
4499 static void gen_rfid(DisasContext *ctx)
4500 {
4501 #if defined(CONFIG_USER_ONLY)
4502     GEN_PRIV;
4503 #else
4504     /* Restore CPU state */
4505     CHK_SV;
4506     gen_icount_io_start(ctx);
4507     gen_update_cfar(ctx, ctx->cia);
4508     gen_helper_rfid(cpu_env);
4509     ctx->base.is_jmp = DISAS_EXIT;
4510 #endif
4511 }
4512 
4513 #if !defined(CONFIG_USER_ONLY)
4514 static void gen_rfscv(DisasContext *ctx)
4515 {
4516 #if defined(CONFIG_USER_ONLY)
4517     GEN_PRIV;
4518 #else
4519     /* Restore CPU state */
4520     CHK_SV;
4521     gen_icount_io_start(ctx);
4522     gen_update_cfar(ctx, ctx->cia);
4523     gen_helper_rfscv(cpu_env);
4524     ctx->base.is_jmp = DISAS_EXIT;
4525 #endif
4526 }
4527 #endif
4528 
4529 static void gen_hrfid(DisasContext *ctx)
4530 {
4531 #if defined(CONFIG_USER_ONLY)
4532     GEN_PRIV;
4533 #else
4534     /* Restore CPU state */
4535     CHK_HV;
4536     gen_helper_hrfid(cpu_env);
4537     ctx->base.is_jmp = DISAS_EXIT;
4538 #endif
4539 }
4540 #endif
4541 
4542 /* sc */
4543 #if defined(CONFIG_USER_ONLY)
4544 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4545 #else
4546 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4547 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
4548 #endif
4549 static void gen_sc(DisasContext *ctx)
4550 {
4551     uint32_t lev;
4552 
4553     lev = (ctx->opcode >> 5) & 0x7F;
4554     gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4555 }
4556 
4557 #if defined(TARGET_PPC64)
4558 #if !defined(CONFIG_USER_ONLY)
4559 static void gen_scv(DisasContext *ctx)
4560 {
4561     uint32_t lev = (ctx->opcode >> 5) & 0x7F;
4562 
4563     /* Set the PC back to the faulting instruction. */
4564     gen_update_nip(ctx, ctx->cia);
4565     gen_helper_scv(cpu_env, tcg_constant_i32(lev));
4566 
4567     ctx->base.is_jmp = DISAS_NORETURN;
4568 }
4569 #endif
4570 #endif
4571 
4572 /***                                Trap                                   ***/
4573 
4574 /* Check for unconditional traps (always or never) */
4575 static bool check_unconditional_trap(DisasContext *ctx)
4576 {
4577     /* Trap never */
4578     if (TO(ctx->opcode) == 0) {
4579         return true;
4580     }
4581     /* Trap always */
4582     if (TO(ctx->opcode) == 31) {
4583         gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4584         return true;
4585     }
4586     return false;
4587 }
4588 
4589 /* tw */
4590 static void gen_tw(DisasContext *ctx)
4591 {
4592     TCGv_i32 t0;
4593 
4594     if (check_unconditional_trap(ctx)) {
4595         return;
4596     }
4597     t0 = tcg_const_i32(TO(ctx->opcode));
4598     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4599                   t0);
4600     tcg_temp_free_i32(t0);
4601 }
4602 
4603 /* twi */
4604 static void gen_twi(DisasContext *ctx)
4605 {
4606     TCGv t0;
4607     TCGv_i32 t1;
4608 
4609     if (check_unconditional_trap(ctx)) {
4610         return;
4611     }
4612     t0 = tcg_const_tl(SIMM(ctx->opcode));
4613     t1 = tcg_const_i32(TO(ctx->opcode));
4614     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4615     tcg_temp_free(t0);
4616     tcg_temp_free_i32(t1);
4617 }
4618 
4619 #if defined(TARGET_PPC64)
4620 /* td */
4621 static void gen_td(DisasContext *ctx)
4622 {
4623     TCGv_i32 t0;
4624 
4625     if (check_unconditional_trap(ctx)) {
4626         return;
4627     }
4628     t0 = tcg_const_i32(TO(ctx->opcode));
4629     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4630                   t0);
4631     tcg_temp_free_i32(t0);
4632 }
4633 
4634 /* tdi */
4635 static void gen_tdi(DisasContext *ctx)
4636 {
4637     TCGv t0;
4638     TCGv_i32 t1;
4639 
4640     if (check_unconditional_trap(ctx)) {
4641         return;
4642     }
4643     t0 = tcg_const_tl(SIMM(ctx->opcode));
4644     t1 = tcg_const_i32(TO(ctx->opcode));
4645     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4646     tcg_temp_free(t0);
4647     tcg_temp_free_i32(t1);
4648 }
4649 #endif
4650 
4651 /***                          Processor control                            ***/
4652 
4653 /* mcrxr */
4654 static void gen_mcrxr(DisasContext *ctx)
4655 {
4656     TCGv_i32 t0 = tcg_temp_new_i32();
4657     TCGv_i32 t1 = tcg_temp_new_i32();
4658     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4659 
4660     tcg_gen_trunc_tl_i32(t0, cpu_so);
4661     tcg_gen_trunc_tl_i32(t1, cpu_ov);
4662     tcg_gen_trunc_tl_i32(dst, cpu_ca);
4663     tcg_gen_shli_i32(t0, t0, 3);
4664     tcg_gen_shli_i32(t1, t1, 2);
4665     tcg_gen_shli_i32(dst, dst, 1);
4666     tcg_gen_or_i32(dst, dst, t0);
4667     tcg_gen_or_i32(dst, dst, t1);
4668     tcg_temp_free_i32(t0);
4669     tcg_temp_free_i32(t1);
4670 
4671     tcg_gen_movi_tl(cpu_so, 0);
4672     tcg_gen_movi_tl(cpu_ov, 0);
4673     tcg_gen_movi_tl(cpu_ca, 0);
4674 }
4675 
4676 #ifdef TARGET_PPC64
4677 /* mcrxrx */
4678 static void gen_mcrxrx(DisasContext *ctx)
4679 {
4680     TCGv t0 = tcg_temp_new();
4681     TCGv t1 = tcg_temp_new();
4682     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4683 
4684     /* copy OV and OV32 */
4685     tcg_gen_shli_tl(t0, cpu_ov, 1);
4686     tcg_gen_or_tl(t0, t0, cpu_ov32);
4687     tcg_gen_shli_tl(t0, t0, 2);
4688     /* copy CA and CA32 */
4689     tcg_gen_shli_tl(t1, cpu_ca, 1);
4690     tcg_gen_or_tl(t1, t1, cpu_ca32);
4691     tcg_gen_or_tl(t0, t0, t1);
4692     tcg_gen_trunc_tl_i32(dst, t0);
4693     tcg_temp_free(t0);
4694     tcg_temp_free(t1);
4695 }
4696 #endif
4697 
4698 /* mfcr mfocrf */
4699 static void gen_mfcr(DisasContext *ctx)
4700 {
4701     uint32_t crm, crn;
4702 
4703     if (likely(ctx->opcode & 0x00100000)) {
4704         crm = CRM(ctx->opcode);
4705         if (likely(crm && ((crm & (crm - 1)) == 0))) {
4706             crn = ctz32(crm);
4707             tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4708             tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4709                             cpu_gpr[rD(ctx->opcode)], crn * 4);
4710         }
4711     } else {
4712         TCGv_i32 t0 = tcg_temp_new_i32();
4713         tcg_gen_mov_i32(t0, cpu_crf[0]);
4714         tcg_gen_shli_i32(t0, t0, 4);
4715         tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4716         tcg_gen_shli_i32(t0, t0, 4);
4717         tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4718         tcg_gen_shli_i32(t0, t0, 4);
4719         tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4720         tcg_gen_shli_i32(t0, t0, 4);
4721         tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4722         tcg_gen_shli_i32(t0, t0, 4);
4723         tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4724         tcg_gen_shli_i32(t0, t0, 4);
4725         tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4726         tcg_gen_shli_i32(t0, t0, 4);
4727         tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4728         tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4729         tcg_temp_free_i32(t0);
4730     }
4731 }
4732 
4733 /* mfmsr */
4734 static void gen_mfmsr(DisasContext *ctx)
4735 {
4736     CHK_SV;
4737     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4738 }
4739 
4740 /* mfspr */
4741 static inline void gen_op_mfspr(DisasContext *ctx)
4742 {
4743     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4744     uint32_t sprn = SPR(ctx->opcode);
4745 
4746 #if defined(CONFIG_USER_ONLY)
4747     read_cb = ctx->spr_cb[sprn].uea_read;
4748 #else
4749     if (ctx->pr) {
4750         read_cb = ctx->spr_cb[sprn].uea_read;
4751     } else if (ctx->hv) {
4752         read_cb = ctx->spr_cb[sprn].hea_read;
4753     } else {
4754         read_cb = ctx->spr_cb[sprn].oea_read;
4755     }
4756 #endif
4757     if (likely(read_cb != NULL)) {
4758         if (likely(read_cb != SPR_NOACCESS)) {
4759             (*read_cb)(ctx, rD(ctx->opcode), sprn);
4760         } else {
4761             /* Privilege exception */
4762             /*
4763              * This is a hack to avoid warnings when running Linux:
4764              * this OS breaks the PowerPC virtualisation model,
4765              * allowing userland application to read the PVR
4766              */
4767             if (sprn != SPR_PVR) {
4768                 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4769                               "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4770                               ctx->cia);
4771             }
4772             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4773         }
4774     } else {
4775         /* ISA 2.07 defines these as no-ops */
4776         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4777             (sprn >= 808 && sprn <= 811)) {
4778             /* This is a nop */
4779             return;
4780         }
4781         /* Not defined */
4782         qemu_log_mask(LOG_GUEST_ERROR,
4783                       "Trying to read invalid spr %d (0x%03x) at "
4784                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4785 
4786         /*
4787          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4788          * generate a priv, a hv emu or a no-op
4789          */
4790         if (sprn & 0x10) {
4791             if (ctx->pr) {
4792                 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4793             }
4794         } else {
4795             if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4796                 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4797             }
4798         }
4799     }
4800 }
4801 
4802 static void gen_mfspr(DisasContext *ctx)
4803 {
4804     gen_op_mfspr(ctx);
4805 }
4806 
4807 /* mftb */
4808 static void gen_mftb(DisasContext *ctx)
4809 {
4810     gen_op_mfspr(ctx);
4811 }
4812 
4813 /* mtcrf mtocrf*/
4814 static void gen_mtcrf(DisasContext *ctx)
4815 {
4816     uint32_t crm, crn;
4817 
4818     crm = CRM(ctx->opcode);
4819     if (likely((ctx->opcode & 0x00100000))) {
4820         if (crm && ((crm & (crm - 1)) == 0)) {
4821             TCGv_i32 temp = tcg_temp_new_i32();
4822             crn = ctz32(crm);
4823             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4824             tcg_gen_shri_i32(temp, temp, crn * 4);
4825             tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4826             tcg_temp_free_i32(temp);
4827         }
4828     } else {
4829         TCGv_i32 temp = tcg_temp_new_i32();
4830         tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4831         for (crn = 0 ; crn < 8 ; crn++) {
4832             if (crm & (1 << crn)) {
4833                     tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4834                     tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4835             }
4836         }
4837         tcg_temp_free_i32(temp);
4838     }
4839 }
4840 
4841 /* mtmsr */
4842 #if defined(TARGET_PPC64)
4843 static void gen_mtmsrd(DisasContext *ctx)
4844 {
4845     if (unlikely(!is_book3s_arch2x(ctx))) {
4846         gen_invalid(ctx);
4847         return;
4848     }
4849 
4850     CHK_SV;
4851 
4852 #if !defined(CONFIG_USER_ONLY)
4853     TCGv t0, t1;
4854     target_ulong mask;
4855 
4856     t0 = tcg_temp_new();
4857     t1 = tcg_temp_new();
4858 
4859     gen_icount_io_start(ctx);
4860 
4861     if (ctx->opcode & 0x00010000) {
4862         /* L=1 form only updates EE and RI */
4863         mask = (1ULL << MSR_RI) | (1ULL << MSR_EE);
4864     } else {
4865         /* mtmsrd does not alter HV, S, ME, or LE */
4866         mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) |
4867                  (1ULL << MSR_HV));
4868         /*
4869          * XXX: we need to update nip before the store if we enter
4870          *      power saving mode, we will exit the loop directly from
4871          *      ppc_store_msr
4872          */
4873         gen_update_nip(ctx, ctx->base.pc_next);
4874     }
4875 
4876     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4877     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4878     tcg_gen_or_tl(t0, t0, t1);
4879 
4880     gen_helper_store_msr(cpu_env, t0);
4881 
4882     /* Must stop the translation as machine state (may have) changed */
4883     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4884 
4885     tcg_temp_free(t0);
4886     tcg_temp_free(t1);
4887 #endif /* !defined(CONFIG_USER_ONLY) */
4888 }
4889 #endif /* defined(TARGET_PPC64) */
4890 
4891 static void gen_mtmsr(DisasContext *ctx)
4892 {
4893     CHK_SV;
4894 
4895 #if !defined(CONFIG_USER_ONLY)
4896     TCGv t0, t1;
4897     target_ulong mask = 0xFFFFFFFF;
4898 
4899     t0 = tcg_temp_new();
4900     t1 = tcg_temp_new();
4901 
4902     gen_icount_io_start(ctx);
4903     if (ctx->opcode & 0x00010000) {
4904         /* L=1 form only updates EE and RI */
4905         mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);
4906     } else {
4907         /* mtmsr does not alter S, ME, or LE */
4908         mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S));
4909 
4910         /*
4911          * XXX: we need to update nip before the store if we enter
4912          *      power saving mode, we will exit the loop directly from
4913          *      ppc_store_msr
4914          */
4915         gen_update_nip(ctx, ctx->base.pc_next);
4916     }
4917 
4918     tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask);
4919     tcg_gen_andi_tl(t1, cpu_msr, ~mask);
4920     tcg_gen_or_tl(t0, t0, t1);
4921 
4922     gen_helper_store_msr(cpu_env, t0);
4923 
4924     /* Must stop the translation as machine state (may have) changed */
4925     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
4926 
4927     tcg_temp_free(t0);
4928     tcg_temp_free(t1);
4929 #endif
4930 }
4931 
4932 /* mtspr */
4933 static void gen_mtspr(DisasContext *ctx)
4934 {
4935     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4936     uint32_t sprn = SPR(ctx->opcode);
4937 
4938 #if defined(CONFIG_USER_ONLY)
4939     write_cb = ctx->spr_cb[sprn].uea_write;
4940 #else
4941     if (ctx->pr) {
4942         write_cb = ctx->spr_cb[sprn].uea_write;
4943     } else if (ctx->hv) {
4944         write_cb = ctx->spr_cb[sprn].hea_write;
4945     } else {
4946         write_cb = ctx->spr_cb[sprn].oea_write;
4947     }
4948 #endif
4949     if (likely(write_cb != NULL)) {
4950         if (likely(write_cb != SPR_NOACCESS)) {
4951             (*write_cb)(ctx, sprn, rS(ctx->opcode));
4952         } else {
4953             /* Privilege exception */
4954             qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4955                           "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4956                           ctx->cia);
4957             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4958         }
4959     } else {
4960         /* ISA 2.07 defines these as no-ops */
4961         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4962             (sprn >= 808 && sprn <= 811)) {
4963             /* This is a nop */
4964             return;
4965         }
4966 
4967         /* Not defined */
4968         qemu_log_mask(LOG_GUEST_ERROR,
4969                       "Trying to write invalid spr %d (0x%03x) at "
4970                       TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
4971 
4972 
4973         /*
4974          * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4975          * generate a priv, a hv emu or a no-op
4976          */
4977         if (sprn & 0x10) {
4978             if (ctx->pr) {
4979                 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4980             }
4981         } else {
4982             if (ctx->pr || sprn == 0) {
4983                 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4984             }
4985         }
4986     }
4987 }
4988 
4989 #if defined(TARGET_PPC64)
4990 /* setb */
4991 static void gen_setb(DisasContext *ctx)
4992 {
4993     TCGv_i32 t0 = tcg_temp_new_i32();
4994     TCGv_i32 t8 = tcg_constant_i32(8);
4995     TCGv_i32 tm1 = tcg_constant_i32(-1);
4996     int crf = crfS(ctx->opcode);
4997 
4998     tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4999     tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
5000     tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5001 
5002     tcg_temp_free_i32(t0);
5003 }
5004 #endif
5005 
5006 /***                         Cache management                              ***/
5007 
5008 /* dcbf */
5009 static void gen_dcbf(DisasContext *ctx)
5010 {
5011     /* XXX: specification says this is treated as a load by the MMU */
5012     TCGv t0;
5013     gen_set_access_type(ctx, ACCESS_CACHE);
5014     t0 = tcg_temp_new();
5015     gen_addr_reg_index(ctx, t0);
5016     gen_qemu_ld8u(ctx, t0, t0);
5017     tcg_temp_free(t0);
5018 }
5019 
5020 /* dcbfep (external PID dcbf) */
5021 static void gen_dcbfep(DisasContext *ctx)
5022 {
5023     /* XXX: specification says this is treated as a load by the MMU */
5024     TCGv t0;
5025     CHK_SV;
5026     gen_set_access_type(ctx, ACCESS_CACHE);
5027     t0 = tcg_temp_new();
5028     gen_addr_reg_index(ctx, t0);
5029     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5030     tcg_temp_free(t0);
5031 }
5032 
5033 /* dcbi (Supervisor only) */
5034 static void gen_dcbi(DisasContext *ctx)
5035 {
5036 #if defined(CONFIG_USER_ONLY)
5037     GEN_PRIV;
5038 #else
5039     TCGv EA, val;
5040 
5041     CHK_SV;
5042     EA = tcg_temp_new();
5043     gen_set_access_type(ctx, ACCESS_CACHE);
5044     gen_addr_reg_index(ctx, EA);
5045     val = tcg_temp_new();
5046     /* XXX: specification says this should be treated as a store by the MMU */
5047     gen_qemu_ld8u(ctx, val, EA);
5048     gen_qemu_st8(ctx, val, EA);
5049     tcg_temp_free(val);
5050     tcg_temp_free(EA);
5051 #endif /* defined(CONFIG_USER_ONLY) */
5052 }
5053 
5054 /* dcdst */
5055 static void gen_dcbst(DisasContext *ctx)
5056 {
5057     /* XXX: specification say this is treated as a load by the MMU */
5058     TCGv t0;
5059     gen_set_access_type(ctx, ACCESS_CACHE);
5060     t0 = tcg_temp_new();
5061     gen_addr_reg_index(ctx, t0);
5062     gen_qemu_ld8u(ctx, t0, t0);
5063     tcg_temp_free(t0);
5064 }
5065 
5066 /* dcbstep (dcbstep External PID version) */
5067 static void gen_dcbstep(DisasContext *ctx)
5068 {
5069     /* XXX: specification say this is treated as a load by the MMU */
5070     TCGv t0;
5071     gen_set_access_type(ctx, ACCESS_CACHE);
5072     t0 = tcg_temp_new();
5073     gen_addr_reg_index(ctx, t0);
5074     tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5075     tcg_temp_free(t0);
5076 }
5077 
5078 /* dcbt */
5079 static void gen_dcbt(DisasContext *ctx)
5080 {
5081     /*
5082      * interpreted as no-op
5083      * XXX: specification say this is treated as a load by the MMU but
5084      *      does not generate any exception
5085      */
5086 }
5087 
5088 /* dcbtep */
5089 static void gen_dcbtep(DisasContext *ctx)
5090 {
5091     /*
5092      * interpreted as no-op
5093      * XXX: specification say this is treated as a load by the MMU but
5094      *      does not generate any exception
5095      */
5096 }
5097 
5098 /* dcbtst */
5099 static void gen_dcbtst(DisasContext *ctx)
5100 {
5101     /*
5102      * interpreted as no-op
5103      * XXX: specification say this is treated as a load by the MMU but
5104      *      does not generate any exception
5105      */
5106 }
5107 
5108 /* dcbtstep */
5109 static void gen_dcbtstep(DisasContext *ctx)
5110 {
5111     /*
5112      * interpreted as no-op
5113      * XXX: specification say this is treated as a load by the MMU but
5114      *      does not generate any exception
5115      */
5116 }
5117 
5118 /* dcbtls */
5119 static void gen_dcbtls(DisasContext *ctx)
5120 {
5121     /* Always fails locking the cache */
5122     TCGv t0 = tcg_temp_new();
5123     gen_load_spr(t0, SPR_Exxx_L1CSR0);
5124     tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5125     gen_store_spr(SPR_Exxx_L1CSR0, t0);
5126     tcg_temp_free(t0);
5127 }
5128 
5129 /* dcbz */
5130 static void gen_dcbz(DisasContext *ctx)
5131 {
5132     TCGv tcgv_addr;
5133     TCGv_i32 tcgv_op;
5134 
5135     gen_set_access_type(ctx, ACCESS_CACHE);
5136     tcgv_addr = tcg_temp_new();
5137     tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5138     gen_addr_reg_index(ctx, tcgv_addr);
5139     gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5140     tcg_temp_free(tcgv_addr);
5141     tcg_temp_free_i32(tcgv_op);
5142 }
5143 
5144 /* dcbzep */
5145 static void gen_dcbzep(DisasContext *ctx)
5146 {
5147     TCGv tcgv_addr;
5148     TCGv_i32 tcgv_op;
5149 
5150     gen_set_access_type(ctx, ACCESS_CACHE);
5151     tcgv_addr = tcg_temp_new();
5152     tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5153     gen_addr_reg_index(ctx, tcgv_addr);
5154     gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5155     tcg_temp_free(tcgv_addr);
5156     tcg_temp_free_i32(tcgv_op);
5157 }
5158 
5159 /* dst / dstt */
5160 static void gen_dst(DisasContext *ctx)
5161 {
5162     if (rA(ctx->opcode) == 0) {
5163         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5164     } else {
5165         /* interpreted as no-op */
5166     }
5167 }
5168 
5169 /* dstst /dststt */
5170 static void gen_dstst(DisasContext *ctx)
5171 {
5172     if (rA(ctx->opcode) == 0) {
5173         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5174     } else {
5175         /* interpreted as no-op */
5176     }
5177 
5178 }
5179 
5180 /* dss / dssall */
5181 static void gen_dss(DisasContext *ctx)
5182 {
5183     /* interpreted as no-op */
5184 }
5185 
5186 /* icbi */
5187 static void gen_icbi(DisasContext *ctx)
5188 {
5189     TCGv t0;
5190     gen_set_access_type(ctx, ACCESS_CACHE);
5191     t0 = tcg_temp_new();
5192     gen_addr_reg_index(ctx, t0);
5193     gen_helper_icbi(cpu_env, t0);
5194     tcg_temp_free(t0);
5195 }
5196 
5197 /* icbiep */
5198 static void gen_icbiep(DisasContext *ctx)
5199 {
5200     TCGv t0;
5201     gen_set_access_type(ctx, ACCESS_CACHE);
5202     t0 = tcg_temp_new();
5203     gen_addr_reg_index(ctx, t0);
5204     gen_helper_icbiep(cpu_env, t0);
5205     tcg_temp_free(t0);
5206 }
5207 
5208 /* Optional: */
5209 /* dcba */
5210 static void gen_dcba(DisasContext *ctx)
5211 {
5212     /*
5213      * interpreted as no-op
5214      * XXX: specification say this is treated as a store by the MMU
5215      *      but does not generate any exception
5216      */
5217 }
5218 
5219 /***                    Segment register manipulation                      ***/
5220 /* Supervisor only: */
5221 
5222 /* mfsr */
5223 static void gen_mfsr(DisasContext *ctx)
5224 {
5225 #if defined(CONFIG_USER_ONLY)
5226     GEN_PRIV;
5227 #else
5228     TCGv t0;
5229 
5230     CHK_SV;
5231     t0 = tcg_const_tl(SR(ctx->opcode));
5232     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5233     tcg_temp_free(t0);
5234 #endif /* defined(CONFIG_USER_ONLY) */
5235 }
5236 
5237 /* mfsrin */
5238 static void gen_mfsrin(DisasContext *ctx)
5239 {
5240 #if defined(CONFIG_USER_ONLY)
5241     GEN_PRIV;
5242 #else
5243     TCGv t0;
5244 
5245     CHK_SV;
5246     t0 = tcg_temp_new();
5247     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5248     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5249     tcg_temp_free(t0);
5250 #endif /* defined(CONFIG_USER_ONLY) */
5251 }
5252 
5253 /* mtsr */
5254 static void gen_mtsr(DisasContext *ctx)
5255 {
5256 #if defined(CONFIG_USER_ONLY)
5257     GEN_PRIV;
5258 #else
5259     TCGv t0;
5260 
5261     CHK_SV;
5262     t0 = tcg_const_tl(SR(ctx->opcode));
5263     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5264     tcg_temp_free(t0);
5265 #endif /* defined(CONFIG_USER_ONLY) */
5266 }
5267 
5268 /* mtsrin */
5269 static void gen_mtsrin(DisasContext *ctx)
5270 {
5271 #if defined(CONFIG_USER_ONLY)
5272     GEN_PRIV;
5273 #else
5274     TCGv t0;
5275     CHK_SV;
5276 
5277     t0 = tcg_temp_new();
5278     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5279     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5280     tcg_temp_free(t0);
5281 #endif /* defined(CONFIG_USER_ONLY) */
5282 }
5283 
5284 #if defined(TARGET_PPC64)
5285 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5286 
5287 /* mfsr */
5288 static void gen_mfsr_64b(DisasContext *ctx)
5289 {
5290 #if defined(CONFIG_USER_ONLY)
5291     GEN_PRIV;
5292 #else
5293     TCGv t0;
5294 
5295     CHK_SV;
5296     t0 = tcg_const_tl(SR(ctx->opcode));
5297     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5298     tcg_temp_free(t0);
5299 #endif /* defined(CONFIG_USER_ONLY) */
5300 }
5301 
5302 /* mfsrin */
5303 static void gen_mfsrin_64b(DisasContext *ctx)
5304 {
5305 #if defined(CONFIG_USER_ONLY)
5306     GEN_PRIV;
5307 #else
5308     TCGv t0;
5309 
5310     CHK_SV;
5311     t0 = tcg_temp_new();
5312     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5313     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5314     tcg_temp_free(t0);
5315 #endif /* defined(CONFIG_USER_ONLY) */
5316 }
5317 
5318 /* mtsr */
5319 static void gen_mtsr_64b(DisasContext *ctx)
5320 {
5321 #if defined(CONFIG_USER_ONLY)
5322     GEN_PRIV;
5323 #else
5324     TCGv t0;
5325 
5326     CHK_SV;
5327     t0 = tcg_const_tl(SR(ctx->opcode));
5328     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5329     tcg_temp_free(t0);
5330 #endif /* defined(CONFIG_USER_ONLY) */
5331 }
5332 
5333 /* mtsrin */
5334 static void gen_mtsrin_64b(DisasContext *ctx)
5335 {
5336 #if defined(CONFIG_USER_ONLY)
5337     GEN_PRIV;
5338 #else
5339     TCGv t0;
5340 
5341     CHK_SV;
5342     t0 = tcg_temp_new();
5343     tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5344     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5345     tcg_temp_free(t0);
5346 #endif /* defined(CONFIG_USER_ONLY) */
5347 }
5348 
5349 /* slbmte */
5350 static void gen_slbmte(DisasContext *ctx)
5351 {
5352 #if defined(CONFIG_USER_ONLY)
5353     GEN_PRIV;
5354 #else
5355     CHK_SV;
5356 
5357     gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5358                          cpu_gpr[rS(ctx->opcode)]);
5359 #endif /* defined(CONFIG_USER_ONLY) */
5360 }
5361 
5362 static void gen_slbmfee(DisasContext *ctx)
5363 {
5364 #if defined(CONFIG_USER_ONLY)
5365     GEN_PRIV;
5366 #else
5367     CHK_SV;
5368 
5369     gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5370                              cpu_gpr[rB(ctx->opcode)]);
5371 #endif /* defined(CONFIG_USER_ONLY) */
5372 }
5373 
5374 static void gen_slbmfev(DisasContext *ctx)
5375 {
5376 #if defined(CONFIG_USER_ONLY)
5377     GEN_PRIV;
5378 #else
5379     CHK_SV;
5380 
5381     gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5382                              cpu_gpr[rB(ctx->opcode)]);
5383 #endif /* defined(CONFIG_USER_ONLY) */
5384 }
5385 
5386 static void gen_slbfee_(DisasContext *ctx)
5387 {
5388 #if defined(CONFIG_USER_ONLY)
5389     gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5390 #else
5391     TCGLabel *l1, *l2;
5392 
5393     if (unlikely(ctx->pr)) {
5394         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5395         return;
5396     }
5397     gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5398                              cpu_gpr[rB(ctx->opcode)]);
5399     l1 = gen_new_label();
5400     l2 = gen_new_label();
5401     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5402     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5403     tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
5404     tcg_gen_br(l2);
5405     gen_set_label(l1);
5406     tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5407     gen_set_label(l2);
5408 #endif
5409 }
5410 #endif /* defined(TARGET_PPC64) */
5411 
5412 /***                      Lookaside buffer management                      ***/
5413 /* Optional & supervisor only: */
5414 
5415 /* tlbia */
5416 static void gen_tlbia(DisasContext *ctx)
5417 {
5418 #if defined(CONFIG_USER_ONLY)
5419     GEN_PRIV;
5420 #else
5421     CHK_HV;
5422 
5423     gen_helper_tlbia(cpu_env);
5424 #endif  /* defined(CONFIG_USER_ONLY) */
5425 }
5426 
5427 /* tlbiel */
5428 static void gen_tlbiel(DisasContext *ctx)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431     GEN_PRIV;
5432 #else
5433     bool psr = (ctx->opcode >> 17) & 0x1;
5434 
5435     if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) {
5436         /*
5437          * tlbiel is privileged except when PSR=0 and HR=1, making it
5438          * hypervisor privileged.
5439          */
5440         GEN_PRIV;
5441     }
5442 
5443     gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5444 #endif /* defined(CONFIG_USER_ONLY) */
5445 }
5446 
5447 /* tlbie */
5448 static void gen_tlbie(DisasContext *ctx)
5449 {
5450 #if defined(CONFIG_USER_ONLY)
5451     GEN_PRIV;
5452 #else
5453     bool psr = (ctx->opcode >> 17) & 0x1;
5454     TCGv_i32 t1;
5455 
5456     if (ctx->pr) {
5457         /* tlbie is privileged... */
5458         GEN_PRIV;
5459     } else if (!ctx->hv) {
5460         if (!ctx->gtse || (!psr && ctx->hr)) {
5461             /*
5462              * ... except when GTSE=0 or when PSR=0 and HR=1, making it
5463              * hypervisor privileged.
5464              */
5465             GEN_PRIV;
5466         }
5467     }
5468 
5469     if (NARROW_MODE(ctx)) {
5470         TCGv t0 = tcg_temp_new();
5471         tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
5472         gen_helper_tlbie(cpu_env, t0);
5473         tcg_temp_free(t0);
5474     } else {
5475         gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5476     }
5477     t1 = tcg_temp_new_i32();
5478     tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
5479     tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
5480     tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
5481     tcg_temp_free_i32(t1);
5482 #endif /* defined(CONFIG_USER_ONLY) */
5483 }
5484 
5485 /* tlbsync */
5486 static void gen_tlbsync(DisasContext *ctx)
5487 {
5488 #if defined(CONFIG_USER_ONLY)
5489     GEN_PRIV;
5490 #else
5491 
5492     if (ctx->gtse) {
5493         CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
5494     } else {
5495         CHK_HV; /* Else hypervisor privileged */
5496     }
5497 
5498     /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
5499     if (ctx->insns_flags & PPC_BOOKE) {
5500         gen_check_tlb_flush(ctx, true);
5501     }
5502 #endif /* defined(CONFIG_USER_ONLY) */
5503 }
5504 
5505 #if defined(TARGET_PPC64)
5506 /* slbia */
5507 static void gen_slbia(DisasContext *ctx)
5508 {
5509 #if defined(CONFIG_USER_ONLY)
5510     GEN_PRIV;
5511 #else
5512     uint32_t ih = (ctx->opcode >> 21) & 0x7;
5513     TCGv_i32 t0 = tcg_const_i32(ih);
5514 
5515     CHK_SV;
5516 
5517     gen_helper_slbia(cpu_env, t0);
5518     tcg_temp_free_i32(t0);
5519 #endif /* defined(CONFIG_USER_ONLY) */
5520 }
5521 
5522 /* slbie */
5523 static void gen_slbie(DisasContext *ctx)
5524 {
5525 #if defined(CONFIG_USER_ONLY)
5526     GEN_PRIV;
5527 #else
5528     CHK_SV;
5529 
5530     gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5531 #endif /* defined(CONFIG_USER_ONLY) */
5532 }
5533 
5534 /* slbieg */
5535 static void gen_slbieg(DisasContext *ctx)
5536 {
5537 #if defined(CONFIG_USER_ONLY)
5538     GEN_PRIV;
5539 #else
5540     CHK_SV;
5541 
5542     gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5543 #endif /* defined(CONFIG_USER_ONLY) */
5544 }
5545 
5546 /* slbsync */
5547 static void gen_slbsync(DisasContext *ctx)
5548 {
5549 #if defined(CONFIG_USER_ONLY)
5550     GEN_PRIV;
5551 #else
5552     CHK_SV;
5553     gen_check_tlb_flush(ctx, true);
5554 #endif /* defined(CONFIG_USER_ONLY) */
5555 }
5556 
5557 #endif  /* defined(TARGET_PPC64) */
5558 
5559 /***                              External control                         ***/
5560 /* Optional: */
5561 
5562 /* eciwx */
5563 static void gen_eciwx(DisasContext *ctx)
5564 {
5565     TCGv t0;
5566     /* Should check EAR[E] ! */
5567     gen_set_access_type(ctx, ACCESS_EXT);
5568     t0 = tcg_temp_new();
5569     gen_addr_reg_index(ctx, t0);
5570     tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5571                        DEF_MEMOP(MO_UL | MO_ALIGN));
5572     tcg_temp_free(t0);
5573 }
5574 
5575 /* ecowx */
5576 static void gen_ecowx(DisasContext *ctx)
5577 {
5578     TCGv t0;
5579     /* Should check EAR[E] ! */
5580     gen_set_access_type(ctx, ACCESS_EXT);
5581     t0 = tcg_temp_new();
5582     gen_addr_reg_index(ctx, t0);
5583     tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5584                        DEF_MEMOP(MO_UL | MO_ALIGN));
5585     tcg_temp_free(t0);
5586 }
5587 
5588 /* 602 - 603 - G2 TLB management */
5589 
5590 /* tlbld */
5591 static void gen_tlbld_6xx(DisasContext *ctx)
5592 {
5593 #if defined(CONFIG_USER_ONLY)
5594     GEN_PRIV;
5595 #else
5596     CHK_SV;
5597     gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5598 #endif /* defined(CONFIG_USER_ONLY) */
5599 }
5600 
5601 /* tlbli */
5602 static void gen_tlbli_6xx(DisasContext *ctx)
5603 {
5604 #if defined(CONFIG_USER_ONLY)
5605     GEN_PRIV;
5606 #else
5607     CHK_SV;
5608     gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5609 #endif /* defined(CONFIG_USER_ONLY) */
5610 }
5611 
5612 /* BookE specific instructions */
5613 
5614 /* XXX: not implemented on 440 ? */
5615 static void gen_mfapidi(DisasContext *ctx)
5616 {
5617     /* XXX: TODO */
5618     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5619 }
5620 
5621 /* XXX: not implemented on 440 ? */
5622 static void gen_tlbiva(DisasContext *ctx)
5623 {
5624 #if defined(CONFIG_USER_ONLY)
5625     GEN_PRIV;
5626 #else
5627     TCGv t0;
5628 
5629     CHK_SV;
5630     t0 = tcg_temp_new();
5631     gen_addr_reg_index(ctx, t0);
5632     gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5633     tcg_temp_free(t0);
5634 #endif /* defined(CONFIG_USER_ONLY) */
5635 }
5636 
5637 /* All 405 MAC instructions are translated here */
5638 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5639                                         int ra, int rb, int rt, int Rc)
5640 {
5641     TCGv t0, t1;
5642 
5643     t0 = tcg_temp_local_new();
5644     t1 = tcg_temp_local_new();
5645 
5646     switch (opc3 & 0x0D) {
5647     case 0x05:
5648         /* macchw    - macchw.    - macchwo   - macchwo.   */
5649         /* macchws   - macchws.   - macchwso  - macchwso.  */
5650         /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
5651         /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
5652         /* mulchw - mulchw. */
5653         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5654         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5655         tcg_gen_ext16s_tl(t1, t1);
5656         break;
5657     case 0x04:
5658         /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
5659         /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
5660         /* mulchwu - mulchwu. */
5661         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5662         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5663         tcg_gen_ext16u_tl(t1, t1);
5664         break;
5665     case 0x01:
5666         /* machhw    - machhw.    - machhwo   - machhwo.   */
5667         /* machhws   - machhws.   - machhwso  - machhwso.  */
5668         /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
5669         /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
5670         /* mulhhw - mulhhw. */
5671         tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5672         tcg_gen_ext16s_tl(t0, t0);
5673         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5674         tcg_gen_ext16s_tl(t1, t1);
5675         break;
5676     case 0x00:
5677         /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
5678         /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
5679         /* mulhhwu - mulhhwu. */
5680         tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5681         tcg_gen_ext16u_tl(t0, t0);
5682         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5683         tcg_gen_ext16u_tl(t1, t1);
5684         break;
5685     case 0x0D:
5686         /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
5687         /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
5688         /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
5689         /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
5690         /* mullhw - mullhw. */
5691         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5692         tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5693         break;
5694     case 0x0C:
5695         /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
5696         /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
5697         /* mullhwu - mullhwu. */
5698         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5699         tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5700         break;
5701     }
5702     if (opc2 & 0x04) {
5703         /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5704         tcg_gen_mul_tl(t1, t0, t1);
5705         if (opc2 & 0x02) {
5706             /* nmultiply-and-accumulate (0x0E) */
5707             tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5708         } else {
5709             /* multiply-and-accumulate (0x0C) */
5710             tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5711         }
5712 
5713         if (opc3 & 0x12) {
5714             /* Check overflow and/or saturate */
5715             TCGLabel *l1 = gen_new_label();
5716 
5717             if (opc3 & 0x10) {
5718                 /* Start with XER OV disabled, the most likely case */
5719                 tcg_gen_movi_tl(cpu_ov, 0);
5720             }
5721             if (opc3 & 0x01) {
5722                 /* Signed */
5723                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5724                 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5725                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5726                 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5727                 if (opc3 & 0x02) {
5728                     /* Saturate */
5729                     tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5730                     tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5731                 }
5732             } else {
5733                 /* Unsigned */
5734                 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5735                 if (opc3 & 0x02) {
5736                     /* Saturate */
5737                     tcg_gen_movi_tl(t0, UINT32_MAX);
5738                 }
5739             }
5740             if (opc3 & 0x10) {
5741                 /* Check overflow */
5742                 tcg_gen_movi_tl(cpu_ov, 1);
5743                 tcg_gen_movi_tl(cpu_so, 1);
5744             }
5745             gen_set_label(l1);
5746             tcg_gen_mov_tl(cpu_gpr[rt], t0);
5747         }
5748     } else {
5749         tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5750     }
5751     tcg_temp_free(t0);
5752     tcg_temp_free(t1);
5753     if (unlikely(Rc) != 0) {
5754         /* Update Rc0 */
5755         gen_set_Rc0(ctx, cpu_gpr[rt]);
5756     }
5757 }
5758 
5759 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
5760 static void glue(gen_, name)(DisasContext *ctx)                               \
5761 {                                                                             \
5762     gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
5763                          rD(ctx->opcode), Rc(ctx->opcode));                   \
5764 }
5765 
5766 /* macchw    - macchw.    */
5767 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5768 /* macchwo   - macchwo.   */
5769 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5770 /* macchws   - macchws.   */
5771 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5772 /* macchwso  - macchwso.  */
5773 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5774 /* macchwsu  - macchwsu.  */
5775 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5776 /* macchwsuo - macchwsuo. */
5777 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5778 /* macchwu   - macchwu.   */
5779 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5780 /* macchwuo  - macchwuo.  */
5781 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5782 /* machhw    - machhw.    */
5783 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5784 /* machhwo   - machhwo.   */
5785 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5786 /* machhws   - machhws.   */
5787 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5788 /* machhwso  - machhwso.  */
5789 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5790 /* machhwsu  - machhwsu.  */
5791 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5792 /* machhwsuo - machhwsuo. */
5793 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5794 /* machhwu   - machhwu.   */
5795 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5796 /* machhwuo  - machhwuo.  */
5797 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5798 /* maclhw    - maclhw.    */
5799 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5800 /* maclhwo   - maclhwo.   */
5801 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5802 /* maclhws   - maclhws.   */
5803 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5804 /* maclhwso  - maclhwso.  */
5805 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5806 /* maclhwu   - maclhwu.   */
5807 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5808 /* maclhwuo  - maclhwuo.  */
5809 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5810 /* maclhwsu  - maclhwsu.  */
5811 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5812 /* maclhwsuo - maclhwsuo. */
5813 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5814 /* nmacchw   - nmacchw.   */
5815 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5816 /* nmacchwo  - nmacchwo.  */
5817 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5818 /* nmacchws  - nmacchws.  */
5819 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5820 /* nmacchwso - nmacchwso. */
5821 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5822 /* nmachhw   - nmachhw.   */
5823 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5824 /* nmachhwo  - nmachhwo.  */
5825 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5826 /* nmachhws  - nmachhws.  */
5827 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5828 /* nmachhwso - nmachhwso. */
5829 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5830 /* nmaclhw   - nmaclhw.   */
5831 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5832 /* nmaclhwo  - nmaclhwo.  */
5833 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5834 /* nmaclhws  - nmaclhws.  */
5835 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5836 /* nmaclhwso - nmaclhwso. */
5837 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5838 
5839 /* mulchw  - mulchw.  */
5840 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5841 /* mulchwu - mulchwu. */
5842 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5843 /* mulhhw  - mulhhw.  */
5844 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5845 /* mulhhwu - mulhhwu. */
5846 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5847 /* mullhw  - mullhw.  */
5848 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5849 /* mullhwu - mullhwu. */
5850 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5851 
5852 /* mfdcr */
5853 static void gen_mfdcr(DisasContext *ctx)
5854 {
5855 #if defined(CONFIG_USER_ONLY)
5856     GEN_PRIV;
5857 #else
5858     TCGv dcrn;
5859 
5860     CHK_SV;
5861     dcrn = tcg_const_tl(SPR(ctx->opcode));
5862     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5863     tcg_temp_free(dcrn);
5864 #endif /* defined(CONFIG_USER_ONLY) */
5865 }
5866 
5867 /* mtdcr */
5868 static void gen_mtdcr(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871     GEN_PRIV;
5872 #else
5873     TCGv dcrn;
5874 
5875     CHK_SV;
5876     dcrn = tcg_const_tl(SPR(ctx->opcode));
5877     gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5878     tcg_temp_free(dcrn);
5879 #endif /* defined(CONFIG_USER_ONLY) */
5880 }
5881 
5882 /* mfdcrx */
5883 /* XXX: not implemented on 440 ? */
5884 static void gen_mfdcrx(DisasContext *ctx)
5885 {
5886 #if defined(CONFIG_USER_ONLY)
5887     GEN_PRIV;
5888 #else
5889     CHK_SV;
5890     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5891                         cpu_gpr[rA(ctx->opcode)]);
5892     /* Note: Rc update flag set leads to undefined state of Rc0 */
5893 #endif /* defined(CONFIG_USER_ONLY) */
5894 }
5895 
5896 /* mtdcrx */
5897 /* XXX: not implemented on 440 ? */
5898 static void gen_mtdcrx(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901     GEN_PRIV;
5902 #else
5903     CHK_SV;
5904     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5905                          cpu_gpr[rS(ctx->opcode)]);
5906     /* Note: Rc update flag set leads to undefined state of Rc0 */
5907 #endif /* defined(CONFIG_USER_ONLY) */
5908 }
5909 
5910 /* mfdcrux (PPC 460) : user-mode access to DCR */
5911 static void gen_mfdcrux(DisasContext *ctx)
5912 {
5913     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5914                         cpu_gpr[rA(ctx->opcode)]);
5915     /* Note: Rc update flag set leads to undefined state of Rc0 */
5916 }
5917 
5918 /* mtdcrux (PPC 460) : user-mode access to DCR */
5919 static void gen_mtdcrux(DisasContext *ctx)
5920 {
5921     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5922                          cpu_gpr[rS(ctx->opcode)]);
5923     /* Note: Rc update flag set leads to undefined state of Rc0 */
5924 }
5925 
5926 /* dccci */
5927 static void gen_dccci(DisasContext *ctx)
5928 {
5929     CHK_SV;
5930     /* interpreted as no-op */
5931 }
5932 
5933 /* dcread */
5934 static void gen_dcread(DisasContext *ctx)
5935 {
5936 #if defined(CONFIG_USER_ONLY)
5937     GEN_PRIV;
5938 #else
5939     TCGv EA, val;
5940 
5941     CHK_SV;
5942     gen_set_access_type(ctx, ACCESS_CACHE);
5943     EA = tcg_temp_new();
5944     gen_addr_reg_index(ctx, EA);
5945     val = tcg_temp_new();
5946     gen_qemu_ld32u(ctx, val, EA);
5947     tcg_temp_free(val);
5948     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5949     tcg_temp_free(EA);
5950 #endif /* defined(CONFIG_USER_ONLY) */
5951 }
5952 
5953 /* icbt */
5954 static void gen_icbt_40x(DisasContext *ctx)
5955 {
5956     /*
5957      * interpreted as no-op
5958      * XXX: specification say this is treated as a load by the MMU but
5959      *      does not generate any exception
5960      */
5961 }
5962 
5963 /* iccci */
5964 static void gen_iccci(DisasContext *ctx)
5965 {
5966     CHK_SV;
5967     /* interpreted as no-op */
5968 }
5969 
5970 /* icread */
5971 static void gen_icread(DisasContext *ctx)
5972 {
5973     CHK_SV;
5974     /* interpreted as no-op */
5975 }
5976 
5977 /* rfci (supervisor only) */
5978 static void gen_rfci_40x(DisasContext *ctx)
5979 {
5980 #if defined(CONFIG_USER_ONLY)
5981     GEN_PRIV;
5982 #else
5983     CHK_SV;
5984     /* Restore CPU state */
5985     gen_helper_40x_rfci(cpu_env);
5986     ctx->base.is_jmp = DISAS_EXIT;
5987 #endif /* defined(CONFIG_USER_ONLY) */
5988 }
5989 
5990 static void gen_rfci(DisasContext *ctx)
5991 {
5992 #if defined(CONFIG_USER_ONLY)
5993     GEN_PRIV;
5994 #else
5995     CHK_SV;
5996     /* Restore CPU state */
5997     gen_helper_rfci(cpu_env);
5998     ctx->base.is_jmp = DISAS_EXIT;
5999 #endif /* defined(CONFIG_USER_ONLY) */
6000 }
6001 
6002 /* BookE specific */
6003 
6004 /* XXX: not implemented on 440 ? */
6005 static void gen_rfdi(DisasContext *ctx)
6006 {
6007 #if defined(CONFIG_USER_ONLY)
6008     GEN_PRIV;
6009 #else
6010     CHK_SV;
6011     /* Restore CPU state */
6012     gen_helper_rfdi(cpu_env);
6013     ctx->base.is_jmp = DISAS_EXIT;
6014 #endif /* defined(CONFIG_USER_ONLY) */
6015 }
6016 
6017 /* XXX: not implemented on 440 ? */
6018 static void gen_rfmci(DisasContext *ctx)
6019 {
6020 #if defined(CONFIG_USER_ONLY)
6021     GEN_PRIV;
6022 #else
6023     CHK_SV;
6024     /* Restore CPU state */
6025     gen_helper_rfmci(cpu_env);
6026     ctx->base.is_jmp = DISAS_EXIT;
6027 #endif /* defined(CONFIG_USER_ONLY) */
6028 }
6029 
6030 /* TLB management - PowerPC 405 implementation */
6031 
6032 /* tlbre */
6033 static void gen_tlbre_40x(DisasContext *ctx)
6034 {
6035 #if defined(CONFIG_USER_ONLY)
6036     GEN_PRIV;
6037 #else
6038     CHK_SV;
6039     switch (rB(ctx->opcode)) {
6040     case 0:
6041         gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6042                                 cpu_gpr[rA(ctx->opcode)]);
6043         break;
6044     case 1:
6045         gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6046                                 cpu_gpr[rA(ctx->opcode)]);
6047         break;
6048     default:
6049         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6050         break;
6051     }
6052 #endif /* defined(CONFIG_USER_ONLY) */
6053 }
6054 
6055 /* tlbsx - tlbsx. */
6056 static void gen_tlbsx_40x(DisasContext *ctx)
6057 {
6058 #if defined(CONFIG_USER_ONLY)
6059     GEN_PRIV;
6060 #else
6061     TCGv t0;
6062 
6063     CHK_SV;
6064     t0 = tcg_temp_new();
6065     gen_addr_reg_index(ctx, t0);
6066     gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6067     tcg_temp_free(t0);
6068     if (Rc(ctx->opcode)) {
6069         TCGLabel *l1 = gen_new_label();
6070         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6071         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6072         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6073         gen_set_label(l1);
6074     }
6075 #endif /* defined(CONFIG_USER_ONLY) */
6076 }
6077 
6078 /* tlbwe */
6079 static void gen_tlbwe_40x(DisasContext *ctx)
6080 {
6081 #if defined(CONFIG_USER_ONLY)
6082     GEN_PRIV;
6083 #else
6084     CHK_SV;
6085 
6086     switch (rB(ctx->opcode)) {
6087     case 0:
6088         gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6089                                 cpu_gpr[rS(ctx->opcode)]);
6090         break;
6091     case 1:
6092         gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6093                                 cpu_gpr[rS(ctx->opcode)]);
6094         break;
6095     default:
6096         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6097         break;
6098     }
6099 #endif /* defined(CONFIG_USER_ONLY) */
6100 }
6101 
6102 /* TLB management - PowerPC 440 implementation */
6103 
6104 /* tlbre */
6105 static void gen_tlbre_440(DisasContext *ctx)
6106 {
6107 #if defined(CONFIG_USER_ONLY)
6108     GEN_PRIV;
6109 #else
6110     CHK_SV;
6111 
6112     switch (rB(ctx->opcode)) {
6113     case 0:
6114     case 1:
6115     case 2:
6116         {
6117             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6118             gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6119                                  t0, cpu_gpr[rA(ctx->opcode)]);
6120             tcg_temp_free_i32(t0);
6121         }
6122         break;
6123     default:
6124         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6125         break;
6126     }
6127 #endif /* defined(CONFIG_USER_ONLY) */
6128 }
6129 
6130 /* tlbsx - tlbsx. */
6131 static void gen_tlbsx_440(DisasContext *ctx)
6132 {
6133 #if defined(CONFIG_USER_ONLY)
6134     GEN_PRIV;
6135 #else
6136     TCGv t0;
6137 
6138     CHK_SV;
6139     t0 = tcg_temp_new();
6140     gen_addr_reg_index(ctx, t0);
6141     gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6142     tcg_temp_free(t0);
6143     if (Rc(ctx->opcode)) {
6144         TCGLabel *l1 = gen_new_label();
6145         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6146         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6147         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6148         gen_set_label(l1);
6149     }
6150 #endif /* defined(CONFIG_USER_ONLY) */
6151 }
6152 
6153 /* tlbwe */
6154 static void gen_tlbwe_440(DisasContext *ctx)
6155 {
6156 #if defined(CONFIG_USER_ONLY)
6157     GEN_PRIV;
6158 #else
6159     CHK_SV;
6160     switch (rB(ctx->opcode)) {
6161     case 0:
6162     case 1:
6163     case 2:
6164         {
6165             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6166             gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6167                                  cpu_gpr[rS(ctx->opcode)]);
6168             tcg_temp_free_i32(t0);
6169         }
6170         break;
6171     default:
6172         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6173         break;
6174     }
6175 #endif /* defined(CONFIG_USER_ONLY) */
6176 }
6177 
6178 /* TLB management - PowerPC BookE 2.06 implementation */
6179 
6180 /* tlbre */
6181 static void gen_tlbre_booke206(DisasContext *ctx)
6182 {
6183  #if defined(CONFIG_USER_ONLY)
6184     GEN_PRIV;
6185 #else
6186    CHK_SV;
6187     gen_helper_booke206_tlbre(cpu_env);
6188 #endif /* defined(CONFIG_USER_ONLY) */
6189 }
6190 
6191 /* tlbsx - tlbsx. */
6192 static void gen_tlbsx_booke206(DisasContext *ctx)
6193 {
6194 #if defined(CONFIG_USER_ONLY)
6195     GEN_PRIV;
6196 #else
6197     TCGv t0;
6198 
6199     CHK_SV;
6200     if (rA(ctx->opcode)) {
6201         t0 = tcg_temp_new();
6202         tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6203     } else {
6204         t0 = tcg_const_tl(0);
6205     }
6206 
6207     tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6208     gen_helper_booke206_tlbsx(cpu_env, t0);
6209     tcg_temp_free(t0);
6210 #endif /* defined(CONFIG_USER_ONLY) */
6211 }
6212 
6213 /* tlbwe */
6214 static void gen_tlbwe_booke206(DisasContext *ctx)
6215 {
6216 #if defined(CONFIG_USER_ONLY)
6217     GEN_PRIV;
6218 #else
6219     CHK_SV;
6220     gen_helper_booke206_tlbwe(cpu_env);
6221 #endif /* defined(CONFIG_USER_ONLY) */
6222 }
6223 
6224 static void gen_tlbivax_booke206(DisasContext *ctx)
6225 {
6226 #if defined(CONFIG_USER_ONLY)
6227     GEN_PRIV;
6228 #else
6229     TCGv t0;
6230 
6231     CHK_SV;
6232     t0 = tcg_temp_new();
6233     gen_addr_reg_index(ctx, t0);
6234     gen_helper_booke206_tlbivax(cpu_env, t0);
6235     tcg_temp_free(t0);
6236 #endif /* defined(CONFIG_USER_ONLY) */
6237 }
6238 
6239 static void gen_tlbilx_booke206(DisasContext *ctx)
6240 {
6241 #if defined(CONFIG_USER_ONLY)
6242     GEN_PRIV;
6243 #else
6244     TCGv t0;
6245 
6246     CHK_SV;
6247     t0 = tcg_temp_new();
6248     gen_addr_reg_index(ctx, t0);
6249 
6250     switch ((ctx->opcode >> 21) & 0x3) {
6251     case 0:
6252         gen_helper_booke206_tlbilx0(cpu_env, t0);
6253         break;
6254     case 1:
6255         gen_helper_booke206_tlbilx1(cpu_env, t0);
6256         break;
6257     case 3:
6258         gen_helper_booke206_tlbilx3(cpu_env, t0);
6259         break;
6260     default:
6261         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6262         break;
6263     }
6264 
6265     tcg_temp_free(t0);
6266 #endif /* defined(CONFIG_USER_ONLY) */
6267 }
6268 
6269 
6270 /* wrtee */
6271 static void gen_wrtee(DisasContext *ctx)
6272 {
6273 #if defined(CONFIG_USER_ONLY)
6274     GEN_PRIV;
6275 #else
6276     TCGv t0;
6277 
6278     CHK_SV;
6279     t0 = tcg_temp_new();
6280     tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6281     tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6282     tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6283     tcg_temp_free(t0);
6284     /*
6285      * Stop translation to have a chance to raise an exception if we
6286      * just set msr_ee to 1
6287      */
6288     ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6289 #endif /* defined(CONFIG_USER_ONLY) */
6290 }
6291 
6292 /* wrteei */
6293 static void gen_wrteei(DisasContext *ctx)
6294 {
6295 #if defined(CONFIG_USER_ONLY)
6296     GEN_PRIV;
6297 #else
6298     CHK_SV;
6299     if (ctx->opcode & 0x00008000) {
6300         tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6301         /* Stop translation to have a chance to raise an exception */
6302         ctx->base.is_jmp = DISAS_EXIT_UPDATE;
6303     } else {
6304         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6305     }
6306 #endif /* defined(CONFIG_USER_ONLY) */
6307 }
6308 
6309 /* PowerPC 440 specific instructions */
6310 
6311 /* dlmzb */
6312 static void gen_dlmzb(DisasContext *ctx)
6313 {
6314     TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6315     gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6316                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6317     tcg_temp_free_i32(t0);
6318 }
6319 
6320 /* mbar replaces eieio on 440 */
6321 static void gen_mbar(DisasContext *ctx)
6322 {
6323     /* interpreted as no-op */
6324 }
6325 
6326 /* msync replaces sync on 440 */
6327 static void gen_msync_4xx(DisasContext *ctx)
6328 {
6329     /* Only e500 seems to treat reserved bits as invalid */
6330     if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
6331         (ctx->opcode & 0x03FFF801)) {
6332         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6333     }
6334     /* otherwise interpreted as no-op */
6335 }
6336 
6337 /* icbt */
6338 static void gen_icbt_440(DisasContext *ctx)
6339 {
6340     /*
6341      * interpreted as no-op
6342      * XXX: specification say this is treated as a load by the MMU but
6343      *      does not generate any exception
6344      */
6345 }
6346 
6347 /* Embedded.Processor Control */
6348 
6349 static void gen_msgclr(DisasContext *ctx)
6350 {
6351 #if defined(CONFIG_USER_ONLY)
6352     GEN_PRIV;
6353 #else
6354     CHK_HV;
6355     if (is_book3s_arch2x(ctx)) {
6356         gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6357     } else {
6358         gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6359     }
6360 #endif /* defined(CONFIG_USER_ONLY) */
6361 }
6362 
6363 static void gen_msgsnd(DisasContext *ctx)
6364 {
6365 #if defined(CONFIG_USER_ONLY)
6366     GEN_PRIV;
6367 #else
6368     CHK_HV;
6369     if (is_book3s_arch2x(ctx)) {
6370         gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6371     } else {
6372         gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6373     }
6374 #endif /* defined(CONFIG_USER_ONLY) */
6375 }
6376 
6377 #if defined(TARGET_PPC64)
6378 static void gen_msgclrp(DisasContext *ctx)
6379 {
6380 #if defined(CONFIG_USER_ONLY)
6381     GEN_PRIV;
6382 #else
6383     CHK_SV;
6384     gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6385 #endif /* defined(CONFIG_USER_ONLY) */
6386 }
6387 
6388 static void gen_msgsndp(DisasContext *ctx)
6389 {
6390 #if defined(CONFIG_USER_ONLY)
6391     GEN_PRIV;
6392 #else
6393     CHK_SV;
6394     gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6395 #endif /* defined(CONFIG_USER_ONLY) */
6396 }
6397 #endif
6398 
6399 static void gen_msgsync(DisasContext *ctx)
6400 {
6401 #if defined(CONFIG_USER_ONLY)
6402     GEN_PRIV;
6403 #else
6404     CHK_HV;
6405 #endif /* defined(CONFIG_USER_ONLY) */
6406     /* interpreted as no-op */
6407 }
6408 
6409 #if defined(TARGET_PPC64)
6410 static void gen_maddld(DisasContext *ctx)
6411 {
6412     TCGv_i64 t1 = tcg_temp_new_i64();
6413 
6414     tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6415     tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6416     tcg_temp_free_i64(t1);
6417 }
6418 
6419 /* maddhd maddhdu */
6420 static void gen_maddhd_maddhdu(DisasContext *ctx)
6421 {
6422     TCGv_i64 lo = tcg_temp_new_i64();
6423     TCGv_i64 hi = tcg_temp_new_i64();
6424     TCGv_i64 t1 = tcg_temp_new_i64();
6425 
6426     if (Rc(ctx->opcode)) {
6427         tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6428                           cpu_gpr[rB(ctx->opcode)]);
6429         tcg_gen_movi_i64(t1, 0);
6430     } else {
6431         tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6432                           cpu_gpr[rB(ctx->opcode)]);
6433         tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6434     }
6435     tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6436                      cpu_gpr[rC(ctx->opcode)], t1);
6437     tcg_temp_free_i64(lo);
6438     tcg_temp_free_i64(hi);
6439     tcg_temp_free_i64(t1);
6440 }
6441 #endif /* defined(TARGET_PPC64) */
6442 
6443 static void gen_tbegin(DisasContext *ctx)
6444 {
6445     if (unlikely(!ctx->tm_enabled)) {
6446         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6447         return;
6448     }
6449     gen_helper_tbegin(cpu_env);
6450 }
6451 
6452 #define GEN_TM_NOOP(name)                                      \
6453 static inline void gen_##name(DisasContext *ctx)               \
6454 {                                                              \
6455     if (unlikely(!ctx->tm_enabled)) {                          \
6456         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6457         return;                                                \
6458     }                                                          \
6459     /*                                                         \
6460      * Because tbegin always fails in QEMU, these user         \
6461      * space instructions all have a simple implementation:    \
6462      *                                                         \
6463      *     CR[0] = 0b0 || MSR[TS] || 0b0                       \
6464      *           = 0b0 || 0b00    || 0b0                       \
6465      */                                                        \
6466     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6467 }
6468 
6469 GEN_TM_NOOP(tend);
6470 GEN_TM_NOOP(tabort);
6471 GEN_TM_NOOP(tabortwc);
6472 GEN_TM_NOOP(tabortwci);
6473 GEN_TM_NOOP(tabortdc);
6474 GEN_TM_NOOP(tabortdci);
6475 GEN_TM_NOOP(tsr);
6476 
6477 static inline void gen_cp_abort(DisasContext *ctx)
6478 {
6479     /* Do Nothing */
6480 }
6481 
6482 #define GEN_CP_PASTE_NOOP(name)                           \
6483 static inline void gen_##name(DisasContext *ctx)          \
6484 {                                                         \
6485     /*                                                    \
6486      * Generate invalid exception until we have an        \
6487      * implementation of the copy paste facility          \
6488      */                                                   \
6489     gen_invalid(ctx);                                     \
6490 }
6491 
6492 GEN_CP_PASTE_NOOP(copy)
6493 GEN_CP_PASTE_NOOP(paste)
6494 
6495 static void gen_tcheck(DisasContext *ctx)
6496 {
6497     if (unlikely(!ctx->tm_enabled)) {
6498         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6499         return;
6500     }
6501     /*
6502      * Because tbegin always fails, the tcheck implementation is
6503      * simple:
6504      *
6505      * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6506      *         = 0b1 || 0b00 || 0b0
6507      */
6508     tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6509 }
6510 
6511 #if defined(CONFIG_USER_ONLY)
6512 #define GEN_TM_PRIV_NOOP(name)                                 \
6513 static inline void gen_##name(DisasContext *ctx)               \
6514 {                                                              \
6515     gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);            \
6516 }
6517 
6518 #else
6519 
6520 #define GEN_TM_PRIV_NOOP(name)                                 \
6521 static inline void gen_##name(DisasContext *ctx)               \
6522 {                                                              \
6523     CHK_SV;                                                    \
6524     if (unlikely(!ctx->tm_enabled)) {                          \
6525         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6526         return;                                                \
6527     }                                                          \
6528     /*                                                         \
6529      * Because tbegin always fails, the implementation is      \
6530      * simple:                                                 \
6531      *                                                         \
6532      *   CR[0] = 0b0 || MSR[TS] || 0b0                         \
6533      *         = 0b0 || 0b00 | 0b0                             \
6534      */                                                        \
6535     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6536 }
6537 
6538 #endif
6539 
6540 GEN_TM_PRIV_NOOP(treclaim);
6541 GEN_TM_PRIV_NOOP(trechkpt);
6542 
6543 static inline void get_fpr(TCGv_i64 dst, int regno)
6544 {
6545     tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
6546 }
6547 
6548 static inline void set_fpr(int regno, TCGv_i64 src)
6549 {
6550     tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
6551 }
6552 
6553 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
6554 {
6555     tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
6556 }
6557 
6558 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
6559 {
6560     tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
6561 }
6562 
6563 /*
6564  * Helpers for decodetree used by !function for decoding arguments.
6565  */
6566 static int times_2(DisasContext *ctx, int x)
6567 {
6568     return x * 2;
6569 }
6570 
6571 static int times_4(DisasContext *ctx, int x)
6572 {
6573     return x * 4;
6574 }
6575 
6576 static int times_16(DisasContext *ctx, int x)
6577 {
6578     return x * 16;
6579 }
6580 
6581 /*
6582  * Helpers for trans_* functions to check for specific insns flags.
6583  * Use token pasting to ensure that we use the proper flag with the
6584  * proper variable.
6585  */
6586 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \
6587     do {                                                \
6588         if (((CTX)->insns_flags & PPC_##NAME) == 0) {   \
6589             return false;                               \
6590         }                                               \
6591     } while (0)
6592 
6593 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
6594     do {                                                \
6595         if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
6596             return false;                               \
6597         }                                               \
6598     } while (0)
6599 
6600 /* Then special-case the check for 64-bit so that we elide code for ppc32. */
6601 #if TARGET_LONG_BITS == 32
6602 # define REQUIRE_64BIT(CTX)  return false
6603 #else
6604 # define REQUIRE_64BIT(CTX)  REQUIRE_INSNS_FLAGS(CTX, 64B)
6605 #endif
6606 
6607 #define REQUIRE_VECTOR(CTX)                             \
6608     do {                                                \
6609         if (unlikely(!(CTX)->altivec_enabled)) {        \
6610             gen_exception((CTX), POWERPC_EXCP_VPU);     \
6611             return true;                                \
6612         }                                               \
6613     } while (0)
6614 
6615 #define REQUIRE_VSX(CTX)                                \
6616     do {                                                \
6617         if (unlikely(!(CTX)->vsx_enabled)) {            \
6618             gen_exception((CTX), POWERPC_EXCP_VSXU);    \
6619             return true;                                \
6620         }                                               \
6621     } while (0)
6622 
6623 #define REQUIRE_FPU(ctx)                                \
6624     do {                                                \
6625         if (unlikely(!(ctx)->fpu_enabled)) {            \
6626             gen_exception((ctx), POWERPC_EXCP_FPU);     \
6627             return true;                                \
6628         }                                               \
6629     } while (0)
6630 
6631 /*
6632  * Helpers for implementing sets of trans_* functions.
6633  * Defer the implementation of NAME to FUNC, with optional extra arguments.
6634  */
6635 #define TRANS(NAME, FUNC, ...) \
6636     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6637     { return FUNC(ctx, a, __VA_ARGS__); }
6638 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
6639     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6640     {                                                          \
6641         REQUIRE_INSNS_FLAGS(ctx, FLAGS);                       \
6642         return FUNC(ctx, a, __VA_ARGS__);                      \
6643     }
6644 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6645     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6646     {                                                          \
6647         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6648         return FUNC(ctx, a, __VA_ARGS__);                      \
6649     }
6650 
6651 #define TRANS64(NAME, FUNC, ...) \
6652     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6653     { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
6654 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
6655     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
6656     {                                                          \
6657         REQUIRE_64BIT(ctx);                                    \
6658         REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
6659         return FUNC(ctx, a, __VA_ARGS__);                      \
6660     }
6661 
6662 /* TODO: More TRANS* helpers for extra insn_flags checks. */
6663 
6664 
6665 #include "decode-insn32.c.inc"
6666 #include "decode-insn64.c.inc"
6667 #include "power8-pmu-regs.c.inc"
6668 
6669 /*
6670  * Incorporate CIA into the constant when R=1.
6671  * Validate that when R=1, RA=0.
6672  */
6673 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
6674 {
6675     d->rt = a->rt;
6676     d->ra = a->ra;
6677     d->si = a->si;
6678     if (a->r) {
6679         if (unlikely(a->ra != 0)) {
6680             gen_invalid(ctx);
6681             return false;
6682         }
6683         d->si += ctx->cia;
6684     }
6685     return true;
6686 }
6687 
6688 #include "translate/fixedpoint-impl.c.inc"
6689 
6690 #include "translate/fp-impl.c.inc"
6691 
6692 #include "translate/vmx-impl.c.inc"
6693 
6694 #include "translate/vsx-impl.c.inc"
6695 
6696 #include "translate/dfp-impl.c.inc"
6697 
6698 #include "translate/spe-impl.c.inc"
6699 
6700 #include "translate/branch-impl.c.inc"
6701 
6702 /* Handles lfdp */
6703 static void gen_dform39(DisasContext *ctx)
6704 {
6705     if ((ctx->opcode & 0x3) == 0) {
6706         if (ctx->insns_flags2 & PPC2_ISA205) {
6707             return gen_lfdp(ctx);
6708         }
6709     }
6710     return gen_invalid(ctx);
6711 }
6712 
6713 /* Handles stfdp */
6714 static void gen_dform3D(DisasContext *ctx)
6715 {
6716     if ((ctx->opcode & 3) == 0) { /* DS-FORM */
6717         /* stfdp */
6718         if (ctx->insns_flags2 & PPC2_ISA205) {
6719             return gen_stfdp(ctx);
6720         }
6721     }
6722     return gen_invalid(ctx);
6723 }
6724 
6725 #if defined(TARGET_PPC64)
6726 /* brd */
6727 static void gen_brd(DisasContext *ctx)
6728 {
6729     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6730 }
6731 
6732 /* brw */
6733 static void gen_brw(DisasContext *ctx)
6734 {
6735     tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6736     tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
6737 
6738 }
6739 
6740 /* brh */
6741 static void gen_brh(DisasContext *ctx)
6742 {
6743     TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
6744     TCGv_i64 t1 = tcg_temp_new_i64();
6745     TCGv_i64 t2 = tcg_temp_new_i64();
6746 
6747     tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
6748     tcg_gen_and_i64(t2, t1, mask);
6749     tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask);
6750     tcg_gen_shli_i64(t1, t1, 8);
6751     tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
6752 
6753     tcg_temp_free_i64(t1);
6754     tcg_temp_free_i64(t2);
6755 }
6756 #endif
6757 
6758 static opcode_t opcodes[] = {
6759 #if defined(TARGET_PPC64)
6760 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
6761 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
6762 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
6763 #endif
6764 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6765 #if defined(TARGET_PPC64)
6766 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6767 #endif
6768 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6769 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6770 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6771 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6772 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6773 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6774 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6775 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6776 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6777 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6778 #if defined(TARGET_PPC64)
6779 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6780 #endif
6781 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6782 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6783 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6784 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6785 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6786 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6787 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6788 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6789 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6790 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6791 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6792 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6793 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6794 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6795 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6796 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6797 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6798 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6799 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6800 #if defined(TARGET_PPC64)
6801 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6802 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6803 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6804 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6805 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6806 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6807 #endif
6808 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6809 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6810 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6811 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6812 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6813 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6814 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6815 #if defined(TARGET_PPC64)
6816 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6817 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6818 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6819 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6820 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6821 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6822                PPC_NONE, PPC2_ISA300),
6823 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6824                PPC_NONE, PPC2_ISA300),
6825 #endif
6826 /* handles lfdp, lxsd, lxssp */
6827 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6828 /* handles stfdp, stxsd, stxssp */
6829 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6830 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6831 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6832 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6833 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6834 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6835 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6836 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6837 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6838 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6839 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6840 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6841 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6842 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6843 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6844 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6845 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6846 #if defined(TARGET_PPC64)
6847 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6848 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6849 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6850 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6851 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6852 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6853 #endif
6854 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6855 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6856 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6857 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6858 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6859 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6860 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6861 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6862 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6863 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6864 #if defined(TARGET_PPC64)
6865 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6866 #if !defined(CONFIG_USER_ONLY)
6867 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6868 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6869 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
6870 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
6871 #endif
6872 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6873 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6874 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6875 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6876 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6877 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6878 #endif
6879 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
6880 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
6881 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
6882 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6883 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6884 #if defined(TARGET_PPC64)
6885 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6886 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6887 #endif
6888 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6889 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6890 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6891 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6892 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6893 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6894 #if defined(TARGET_PPC64)
6895 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6896 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6897 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6898 #endif
6899 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6900 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6901 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6902 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6903 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6904 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6905 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6906 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6907 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6908 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6909 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6910 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6911 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6912 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6913 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6914 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6915 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6916 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6917 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6918 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6919 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6920 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6921 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6922 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6923 #if defined(TARGET_PPC64)
6924 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6925 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6926              PPC_SEGMENT_64B),
6927 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6928 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6929              PPC_SEGMENT_64B),
6930 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6931 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6932 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6933 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6934 #endif
6935 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6936 /*
6937  * XXX Those instructions will need to be handled differently for
6938  * different ISA versions
6939  */
6940 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6941 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6942 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6943 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6944 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6945 #if defined(TARGET_PPC64)
6946 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6947 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6948 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6949 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6950 #endif
6951 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6952 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6953 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6954 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6955 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6956 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6957 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6958 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6959 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6960 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6961 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6962 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6963 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6964 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6965 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6966 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6967 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6968 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6969 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6970 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6971 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6972 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6973 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6974 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6975 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6976 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6977 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6978 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6979                PPC_NONE, PPC2_BOOKE206),
6980 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6981                PPC_NONE, PPC2_BOOKE206),
6982 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6983                PPC_NONE, PPC2_BOOKE206),
6984 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6985                PPC_NONE, PPC2_BOOKE206),
6986 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6987                PPC_NONE, PPC2_BOOKE206),
6988 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6989                PPC_NONE, PPC2_PRCNTL),
6990 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6991                PPC_NONE, PPC2_PRCNTL),
6992 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
6993                PPC_NONE, PPC2_PRCNTL),
6994 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6995 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6996 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6997 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6998               PPC_BOOKE, PPC2_BOOKE206),
6999 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
7000 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7001                PPC_BOOKE, PPC2_BOOKE206),
7002 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7003              PPC_440_SPEC),
7004 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7005 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7006 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7007 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
7008 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
7009 #if defined(TARGET_PPC64)
7010 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7011               PPC2_ISA300),
7012 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
7013 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
7014                PPC_NONE, PPC2_ISA207S),
7015 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
7016                PPC_NONE, PPC2_ISA207S),
7017 #endif
7018 
7019 #undef GEN_INT_ARITH_ADD
7020 #undef GEN_INT_ARITH_ADD_CONST
7021 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
7022 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7023 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
7024                                 add_ca, compute_ca, compute_ov)               \
7025 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7026 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7027 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7028 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7029 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7030 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7031 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7032 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7033 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
7034 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
7035 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7036 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7037 
7038 #undef GEN_INT_ARITH_DIVW
7039 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
7040 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7041 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7042 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7043 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7044 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
7045 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7046 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7047 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7048 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7049 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7050 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7051 
7052 #if defined(TARGET_PPC64)
7053 #undef GEN_INT_ARITH_DIVD
7054 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
7055 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7056 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7057 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7058 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7059 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7060 
7061 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7062 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7063 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7064 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7065 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7066 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7067 
7068 #undef GEN_INT_ARITH_MUL_HELPER
7069 #define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
7070 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7071 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7072 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7073 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7074 #endif
7075 
7076 #undef GEN_INT_ARITH_SUBF
7077 #undef GEN_INT_ARITH_SUBF_CONST
7078 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
7079 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7080 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
7081                                 add_ca, compute_ca, compute_ov)               \
7082 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7083 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7084 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7085 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7086 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7087 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7088 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7089 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7090 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7091 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7092 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7093 
7094 #undef GEN_LOGICAL1
7095 #undef GEN_LOGICAL2
7096 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
7097 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7098 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
7099 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7100 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7101 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7102 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7103 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7104 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7105 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7106 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7107 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7108 #if defined(TARGET_PPC64)
7109 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7110 #endif
7111 
7112 #if defined(TARGET_PPC64)
7113 #undef GEN_PPC64_R2
7114 #undef GEN_PPC64_R4
7115 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
7116 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7117 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
7118              PPC_64B)
7119 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
7120 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7121 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
7122              PPC_64B),                                                        \
7123 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
7124              PPC_64B),                                                        \
7125 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
7126              PPC_64B)
7127 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7128 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7129 GEN_PPC64_R4(rldic, 0x1E, 0x04),
7130 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7131 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7132 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7133 #endif
7134 
7135 #undef GEN_LDX_E
7136 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
7137 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7138 
7139 #if defined(TARGET_PPC64)
7140 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
7141 
7142 /* HV/P7 and later only */
7143 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
7144 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7145 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7146 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
7147 #endif
7148 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
7149 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
7150 
7151 /* External PID based load */
7152 #undef GEN_LDEPX
7153 #define GEN_LDEPX(name, ldop, opc2, opc3)                                     \
7154 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
7155               0x00000001, PPC_NONE, PPC2_BOOKE206),
7156 
7157 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
7158 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
7159 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
7160 #if defined(TARGET_PPC64)
7161 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00)
7162 #endif
7163 
7164 #undef GEN_STX_E
7165 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
7166 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7167 
7168 #if defined(TARGET_PPC64)
7169 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
7170 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
7171 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
7172 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
7173 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
7174 #endif
7175 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
7176 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
7177 
7178 #undef GEN_STEPX
7179 #define GEN_STEPX(name, ldop, opc2, opc3)                                     \
7180 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3,                                    \
7181               0x00000001, PPC_NONE, PPC2_BOOKE206),
7182 
7183 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
7184 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
7185 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
7186 #if defined(TARGET_PPC64)
7187 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04)
7188 #endif
7189 
7190 #undef GEN_CRLOGIC
7191 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
7192 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7193 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
7194 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
7195 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
7196 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
7197 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
7198 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
7199 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
7200 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
7201 
7202 #undef GEN_MAC_HANDLER
7203 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
7204 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7205 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
7206 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
7207 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
7208 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7209 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7210 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7211 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7212 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7213 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7214 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7215 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7216 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7217 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7218 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7219 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7220 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7221 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7222 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7223 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7224 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7225 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7226 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7227 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7228 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7229 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7230 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7231 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7232 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7233 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7234 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7235 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7236 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7237 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7238 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7239 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7240 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7241 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7242 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7243 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7244 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7245 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7246 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7247 
7248 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7249                PPC_NONE, PPC2_TM),
7250 GEN_HANDLER2_E(tend,   "tend",   0x1F, 0x0E, 0x15, 0x01FFF800, \
7251                PPC_NONE, PPC2_TM),
7252 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7253                PPC_NONE, PPC2_TM),
7254 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7255                PPC_NONE, PPC2_TM),
7256 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7257                PPC_NONE, PPC2_TM),
7258 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7259                PPC_NONE, PPC2_TM),
7260 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7261                PPC_NONE, PPC2_TM),
7262 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7263                PPC_NONE, PPC2_TM),
7264 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7265                PPC_NONE, PPC2_TM),
7266 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7267                PPC_NONE, PPC2_TM),
7268 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7269                PPC_NONE, PPC2_TM),
7270 
7271 #include "translate/fp-ops.c.inc"
7272 
7273 #include "translate/vmx-ops.c.inc"
7274 
7275 #include "translate/vsx-ops.c.inc"
7276 
7277 #include "translate/spe-ops.c.inc"
7278 };
7279 
7280 /*****************************************************************************/
7281 /* Opcode types */
7282 enum {
7283     PPC_DIRECT   = 0, /* Opcode routine        */
7284     PPC_INDIRECT = 1, /* Indirect opcode table */
7285 };
7286 
7287 #define PPC_OPCODE_MASK 0x3
7288 
7289 static inline int is_indirect_opcode(void *handler)
7290 {
7291     return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
7292 }
7293 
7294 static inline opc_handler_t **ind_table(void *handler)
7295 {
7296     return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
7297 }
7298 
7299 /* Instruction table creation */
7300 /* Opcodes tables creation */
7301 static void fill_new_table(opc_handler_t **table, int len)
7302 {
7303     int i;
7304 
7305     for (i = 0; i < len; i++) {
7306         table[i] = &invalid_handler;
7307     }
7308 }
7309 
7310 static int create_new_table(opc_handler_t **table, unsigned char idx)
7311 {
7312     opc_handler_t **tmp;
7313 
7314     tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
7315     fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
7316     table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7317 
7318     return 0;
7319 }
7320 
7321 static int insert_in_table(opc_handler_t **table, unsigned char idx,
7322                             opc_handler_t *handler)
7323 {
7324     if (table[idx] != &invalid_handler) {
7325         return -1;
7326     }
7327     table[idx] = handler;
7328 
7329     return 0;
7330 }
7331 
7332 static int register_direct_insn(opc_handler_t **ppc_opcodes,
7333                                 unsigned char idx, opc_handler_t *handler)
7334 {
7335     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7336         printf("*** ERROR: opcode %02x already assigned in main "
7337                "opcode table\n", idx);
7338         return -1;
7339     }
7340 
7341     return 0;
7342 }
7343 
7344 static int register_ind_in_table(opc_handler_t **table,
7345                                  unsigned char idx1, unsigned char idx2,
7346                                  opc_handler_t *handler)
7347 {
7348     if (table[idx1] == &invalid_handler) {
7349         if (create_new_table(table, idx1) < 0) {
7350             printf("*** ERROR: unable to create indirect table "
7351                    "idx=%02x\n", idx1);
7352             return -1;
7353         }
7354     } else {
7355         if (!is_indirect_opcode(table[idx1])) {
7356             printf("*** ERROR: idx %02x already assigned to a direct "
7357                    "opcode\n", idx1);
7358             return -1;
7359         }
7360     }
7361     if (handler != NULL &&
7362         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7363         printf("*** ERROR: opcode %02x already assigned in "
7364                "opcode table %02x\n", idx2, idx1);
7365         return -1;
7366     }
7367 
7368     return 0;
7369 }
7370 
7371 static int register_ind_insn(opc_handler_t **ppc_opcodes,
7372                              unsigned char idx1, unsigned char idx2,
7373                              opc_handler_t *handler)
7374 {
7375     return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7376 }
7377 
7378 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
7379                                 unsigned char idx1, unsigned char idx2,
7380                                 unsigned char idx3, opc_handler_t *handler)
7381 {
7382     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7383         printf("*** ERROR: unable to join indirect table idx "
7384                "[%02x-%02x]\n", idx1, idx2);
7385         return -1;
7386     }
7387     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7388                               handler) < 0) {
7389         printf("*** ERROR: unable to insert opcode "
7390                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7391         return -1;
7392     }
7393 
7394     return 0;
7395 }
7396 
7397 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
7398                                  unsigned char idx1, unsigned char idx2,
7399                                  unsigned char idx3, unsigned char idx4,
7400                                  opc_handler_t *handler)
7401 {
7402     opc_handler_t **table;
7403 
7404     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7405         printf("*** ERROR: unable to join indirect table idx "
7406                "[%02x-%02x]\n", idx1, idx2);
7407         return -1;
7408     }
7409     table = ind_table(ppc_opcodes[idx1]);
7410     if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
7411         printf("*** ERROR: unable to join 2nd-level indirect table idx "
7412                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7413         return -1;
7414     }
7415     table = ind_table(table[idx2]);
7416     if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
7417         printf("*** ERROR: unable to insert opcode "
7418                "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
7419         return -1;
7420     }
7421     return 0;
7422 }
7423 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
7424 {
7425     if (insn->opc2 != 0xFF) {
7426         if (insn->opc3 != 0xFF) {
7427             if (insn->opc4 != 0xFF) {
7428                 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7429                                           insn->opc3, insn->opc4,
7430                                           &insn->handler) < 0) {
7431                     return -1;
7432                 }
7433             } else {
7434                 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7435                                          insn->opc3, &insn->handler) < 0) {
7436                     return -1;
7437                 }
7438             }
7439         } else {
7440             if (register_ind_insn(ppc_opcodes, insn->opc1,
7441                                   insn->opc2, &insn->handler) < 0) {
7442                 return -1;
7443             }
7444         }
7445     } else {
7446         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
7447             return -1;
7448         }
7449     }
7450 
7451     return 0;
7452 }
7453 
7454 static int test_opcode_table(opc_handler_t **table, int len)
7455 {
7456     int i, count, tmp;
7457 
7458     for (i = 0, count = 0; i < len; i++) {
7459         /* Consistency fixup */
7460         if (table[i] == NULL) {
7461             table[i] = &invalid_handler;
7462         }
7463         if (table[i] != &invalid_handler) {
7464             if (is_indirect_opcode(table[i])) {
7465                 tmp = test_opcode_table(ind_table(table[i]),
7466                     PPC_CPU_INDIRECT_OPCODES_LEN);
7467                 if (tmp == 0) {
7468                     free(table[i]);
7469                     table[i] = &invalid_handler;
7470                 } else {
7471                     count++;
7472                 }
7473             } else {
7474                 count++;
7475             }
7476         }
7477     }
7478 
7479     return count;
7480 }
7481 
7482 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
7483 {
7484     if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
7485         printf("*** WARNING: no opcode defined !\n");
7486     }
7487 }
7488 
7489 /*****************************************************************************/
7490 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7491 {
7492     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7493     opcode_t *opc;
7494 
7495     fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
7496     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7497         if (((opc->handler.type & pcc->insns_flags) != 0) ||
7498             ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7499             if (register_insn(cpu->opcodes, opc) < 0) {
7500                 error_setg(errp, "ERROR initializing PowerPC instruction "
7501                            "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7502                            opc->opc3);
7503                 return;
7504             }
7505         }
7506     }
7507     fix_opcode_tables(cpu->opcodes);
7508     fflush(stdout);
7509     fflush(stderr);
7510 }
7511 
7512 void destroy_ppc_opcodes(PowerPCCPU *cpu)
7513 {
7514     opc_handler_t **table, **table_2;
7515     int i, j, k;
7516 
7517     for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
7518         if (cpu->opcodes[i] == &invalid_handler) {
7519             continue;
7520         }
7521         if (is_indirect_opcode(cpu->opcodes[i])) {
7522             table = ind_table(cpu->opcodes[i]);
7523             for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
7524                 if (table[j] == &invalid_handler) {
7525                     continue;
7526                 }
7527                 if (is_indirect_opcode(table[j])) {
7528                     table_2 = ind_table(table[j]);
7529                     for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
7530                         if (table_2[k] != &invalid_handler &&
7531                             is_indirect_opcode(table_2[k])) {
7532                             g_free((opc_handler_t *)((uintptr_t)table_2[k] &
7533                                                      ~PPC_INDIRECT));
7534                         }
7535                     }
7536                     g_free((opc_handler_t *)((uintptr_t)table[j] &
7537                                              ~PPC_INDIRECT));
7538                 }
7539             }
7540             g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
7541                 ~PPC_INDIRECT));
7542         }
7543     }
7544 }
7545 
7546 int ppc_fixup_cpu(PowerPCCPU *cpu)
7547 {
7548     CPUPPCState *env = &cpu->env;
7549 
7550     /*
7551      * TCG doesn't (yet) emulate some groups of instructions that are
7552      * implemented on some otherwise supported CPUs (e.g. VSX and
7553      * decimal floating point instructions on POWER7).  We remove
7554      * unsupported instruction groups from the cpu state's instruction
7555      * masks and hope the guest can cope.  For at least the pseries
7556      * machine, the unavailability of these instructions can be
7557      * advertised to the guest via the device tree.
7558      */
7559     if ((env->insns_flags & ~PPC_TCG_INSNS)
7560         || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7561         warn_report("Disabling some instructions which are not "
7562                     "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
7563                     env->insns_flags & ~PPC_TCG_INSNS,
7564                     env->insns_flags2 & ~PPC_TCG_INSNS2);
7565     }
7566     env->insns_flags &= PPC_TCG_INSNS;
7567     env->insns_flags2 &= PPC_TCG_INSNS2;
7568     return 0;
7569 }
7570 
7571 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
7572 {
7573     opc_handler_t **table, *handler;
7574     uint32_t inval;
7575 
7576     ctx->opcode = insn;
7577 
7578     LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7579               insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7580               ctx->le_mode ? "little" : "big");
7581 
7582     table = cpu->opcodes;
7583     handler = table[opc1(insn)];
7584     if (is_indirect_opcode(handler)) {
7585         table = ind_table(handler);
7586         handler = table[opc2(insn)];
7587         if (is_indirect_opcode(handler)) {
7588             table = ind_table(handler);
7589             handler = table[opc3(insn)];
7590             if (is_indirect_opcode(handler)) {
7591                 table = ind_table(handler);
7592                 handler = table[opc4(insn)];
7593             }
7594         }
7595     }
7596 
7597     /* Is opcode *REALLY* valid ? */
7598     if (unlikely(handler->handler == &gen_invalid)) {
7599         qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7600                       "%02x - %02x - %02x - %02x (%08x) "
7601                       TARGET_FMT_lx "\n",
7602                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7603                       insn, ctx->cia);
7604         return false;
7605     }
7606 
7607     if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7608                  && Rc(insn))) {
7609         inval = handler->inval2;
7610     } else {
7611         inval = handler->inval1;
7612     }
7613 
7614     if (unlikely((insn & inval) != 0)) {
7615         qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7616                       "%02x - %02x - %02x - %02x (%08x) "
7617                       TARGET_FMT_lx "\n", insn & inval,
7618                       opc1(insn), opc2(insn), opc3(insn), opc4(insn),
7619                       insn, ctx->cia);
7620         return false;
7621     }
7622 
7623     handler->handler(ctx);
7624     return true;
7625 }
7626 
7627 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7628 {
7629     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7630     CPUPPCState *env = cs->env_ptr;
7631     uint32_t hflags = ctx->base.tb->flags;
7632 
7633     ctx->spr_cb = env->spr_cb;
7634     ctx->pr = (hflags >> HFLAGS_PR) & 1;
7635     ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
7636     ctx->dr = (hflags >> HFLAGS_DR) & 1;
7637     ctx->hv = (hflags >> HFLAGS_HV) & 1;
7638     ctx->insns_flags = env->insns_flags;
7639     ctx->insns_flags2 = env->insns_flags2;
7640     ctx->access_type = -1;
7641     ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
7642     ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
7643     ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7644     ctx->flags = env->flags;
7645 #if defined(TARGET_PPC64)
7646     ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
7647     ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7648 #endif
7649     ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7650         || env->mmu_model & POWERPC_MMU_64;
7651 
7652     ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
7653     ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
7654     ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
7655     ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
7656     ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
7657     ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
7658     ctx->hr = (hflags >> HFLAGS_HR) & 1;
7659     ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
7660     ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
7661     ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
7662 
7663     ctx->singlestep_enabled = 0;
7664     if ((hflags >> HFLAGS_SE) & 1) {
7665         ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7666         ctx->base.max_insns = 1;
7667     }
7668     if ((hflags >> HFLAGS_BE) & 1) {
7669         ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7670     }
7671 }
7672 
7673 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7674 {
7675 }
7676 
7677 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7678 {
7679     tcg_gen_insn_start(dcbase->pc_next);
7680 }
7681 
7682 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
7683 {
7684     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
7685     return opc1(insn) == 1;
7686 }
7687 
7688 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7689 {
7690     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7691     PowerPCCPU *cpu = POWERPC_CPU(cs);
7692     CPUPPCState *env = cs->env_ptr;
7693     target_ulong pc;
7694     uint32_t insn;
7695     bool ok;
7696 
7697     LOG_DISAS("----------------\n");
7698     LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7699               ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7700 
7701     ctx->cia = pc = ctx->base.pc_next;
7702     insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
7703     ctx->base.pc_next = pc += 4;
7704 
7705     if (!is_prefix_insn(ctx, insn)) {
7706         ok = (decode_insn32(ctx, insn) ||
7707               decode_legacy(cpu, ctx, insn));
7708     } else if ((pc & 63) == 0) {
7709         /*
7710          * Power v3.1, section 1.9 Exceptions:
7711          * attempt to execute a prefixed instruction that crosses a
7712          * 64-byte address boundary (system alignment error).
7713          */
7714         gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
7715         ok = true;
7716     } else {
7717         uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
7718                                              need_byteswap(ctx));
7719         ctx->base.pc_next = pc += 4;
7720         ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
7721     }
7722     if (!ok) {
7723         gen_invalid(ctx);
7724     }
7725 
7726     /* End the TB when crossing a page boundary. */
7727     if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
7728         ctx->base.is_jmp = DISAS_TOO_MANY;
7729     }
7730 
7731     translator_loop_temp_check(&ctx->base);
7732 }
7733 
7734 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7735 {
7736     DisasContext *ctx = container_of(dcbase, DisasContext, base);
7737     DisasJumpType is_jmp = ctx->base.is_jmp;
7738     target_ulong nip = ctx->base.pc_next;
7739 
7740     if (is_jmp == DISAS_NORETURN) {
7741         /* We have already exited the TB. */
7742         return;
7743     }
7744 
7745     /* Honor single stepping. */
7746     if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
7747         && (nip <= 0x100 || nip > 0xf00)) {
7748         switch (is_jmp) {
7749         case DISAS_TOO_MANY:
7750         case DISAS_EXIT_UPDATE:
7751         case DISAS_CHAIN_UPDATE:
7752             gen_update_nip(ctx, nip);
7753             break;
7754         case DISAS_EXIT:
7755         case DISAS_CHAIN:
7756             break;
7757         default:
7758             g_assert_not_reached();
7759         }
7760 
7761         gen_debug_exception(ctx);
7762         return;
7763     }
7764 
7765     switch (is_jmp) {
7766     case DISAS_TOO_MANY:
7767         if (use_goto_tb(ctx, nip)) {
7768             pmu_count_insns(ctx);
7769             tcg_gen_goto_tb(0);
7770             gen_update_nip(ctx, nip);
7771             tcg_gen_exit_tb(ctx->base.tb, 0);
7772             break;
7773         }
7774         /* fall through */
7775     case DISAS_CHAIN_UPDATE:
7776         gen_update_nip(ctx, nip);
7777         /* fall through */
7778     case DISAS_CHAIN:
7779         /*
7780          * tcg_gen_lookup_and_goto_ptr will exit the TB if
7781          * CF_NO_GOTO_PTR is set. Count insns now.
7782          */
7783         if (ctx->base.tb->flags & CF_NO_GOTO_PTR) {
7784             pmu_count_insns(ctx);
7785         }
7786 
7787         tcg_gen_lookup_and_goto_ptr();
7788         break;
7789 
7790     case DISAS_EXIT_UPDATE:
7791         gen_update_nip(ctx, nip);
7792         /* fall through */
7793     case DISAS_EXIT:
7794         pmu_count_insns(ctx);
7795         tcg_gen_exit_tb(NULL, 0);
7796         break;
7797 
7798     default:
7799         g_assert_not_reached();
7800     }
7801 }
7802 
7803 static void ppc_tr_disas_log(const DisasContextBase *dcbase,
7804                              CPUState *cs, FILE *logfile)
7805 {
7806     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
7807     target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size);
7808 }
7809 
7810 static const TranslatorOps ppc_tr_ops = {
7811     .init_disas_context = ppc_tr_init_disas_context,
7812     .tb_start           = ppc_tr_tb_start,
7813     .insn_start         = ppc_tr_insn_start,
7814     .translate_insn     = ppc_tr_translate_insn,
7815     .tb_stop            = ppc_tr_tb_stop,
7816     .disas_log          = ppc_tr_disas_log,
7817 };
7818 
7819 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
7820 {
7821     DisasContext ctx;
7822 
7823     translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
7824 }
7825 
7826 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7827                           target_ulong *data)
7828 {
7829     env->nip = data[0];
7830 }
7831