1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "trace-tcg.h" 36 #include "exec/translator.h" 37 #include "exec/log.h" 38 #include "qemu/atomic128.h" 39 40 41 #define CPU_SINGLE_STEP 0x1 42 #define CPU_BRANCH_STEP 0x2 43 #define GDBSTUB_SINGLE_STEP 0x4 44 45 /* Include definitions for instructions classes and implementations flags */ 46 /* #define PPC_DEBUG_DISAS */ 47 /* #define DO_PPC_STATISTICS */ 48 49 #ifdef PPC_DEBUG_DISAS 50 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51 #else 52 # define LOG_DISAS(...) do { } while (0) 53 #endif 54 /*****************************************************************************/ 55 /* Code translation helpers */ 56 57 /* global register indexes */ 58 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59 + 10 * 4 + 22 * 5 /* SPE GPRh */ 60 + 8 * 5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i32 cpu_crf[8]; 64 static TCGv cpu_nip; 65 static TCGv cpu_msr; 66 static TCGv cpu_ctr; 67 static TCGv cpu_lr; 68 #if defined(TARGET_PPC64) 69 static TCGv cpu_cfar; 70 #endif 71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72 static TCGv cpu_reserve; 73 static TCGv cpu_reserve_val; 74 static TCGv cpu_fpscr; 75 static TCGv_i32 cpu_access_type; 76 77 #include "exec/gen-icount.h" 78 79 void ppc_translate_init(void) 80 { 81 int i; 82 char *p; 83 size_t cpu_reg_names_size; 84 85 p = cpu_reg_names; 86 cpu_reg_names_size = sizeof(cpu_reg_names); 87 88 for (i = 0; i < 8; i++) { 89 snprintf(p, cpu_reg_names_size, "crf%d", i); 90 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91 offsetof(CPUPPCState, crf[i]), p); 92 p += 5; 93 cpu_reg_names_size -= 5; 94 } 95 96 for (i = 0; i < 32; i++) { 97 snprintf(p, cpu_reg_names_size, "r%d", i); 98 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99 offsetof(CPUPPCState, gpr[i]), p); 100 p += (i < 10) ? 3 : 4; 101 cpu_reg_names_size -= (i < 10) ? 3 : 4; 102 snprintf(p, cpu_reg_names_size, "r%dH", i); 103 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gprh[i]), p); 105 p += (i < 10) ? 4 : 5; 106 cpu_reg_names_size -= (i < 10) ? 4 : 5; 107 } 108 109 cpu_nip = tcg_global_mem_new(cpu_env, 110 offsetof(CPUPPCState, nip), "nip"); 111 112 cpu_msr = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, msr), "msr"); 114 115 cpu_ctr = tcg_global_mem_new(cpu_env, 116 offsetof(CPUPPCState, ctr), "ctr"); 117 118 cpu_lr = tcg_global_mem_new(cpu_env, 119 offsetof(CPUPPCState, lr), "lr"); 120 121 #if defined(TARGET_PPC64) 122 cpu_cfar = tcg_global_mem_new(cpu_env, 123 offsetof(CPUPPCState, cfar), "cfar"); 124 #endif 125 126 cpu_xer = tcg_global_mem_new(cpu_env, 127 offsetof(CPUPPCState, xer), "xer"); 128 cpu_so = tcg_global_mem_new(cpu_env, 129 offsetof(CPUPPCState, so), "SO"); 130 cpu_ov = tcg_global_mem_new(cpu_env, 131 offsetof(CPUPPCState, ov), "OV"); 132 cpu_ca = tcg_global_mem_new(cpu_env, 133 offsetof(CPUPPCState, ca), "CA"); 134 cpu_ov32 = tcg_global_mem_new(cpu_env, 135 offsetof(CPUPPCState, ov32), "OV32"); 136 cpu_ca32 = tcg_global_mem_new(cpu_env, 137 offsetof(CPUPPCState, ca32), "CA32"); 138 139 cpu_reserve = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, reserve_addr), 141 "reserve_addr"); 142 cpu_reserve_val = tcg_global_mem_new(cpu_env, 143 offsetof(CPUPPCState, reserve_val), 144 "reserve_val"); 145 146 cpu_fpscr = tcg_global_mem_new(cpu_env, 147 offsetof(CPUPPCState, fpscr), "fpscr"); 148 149 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150 offsetof(CPUPPCState, access_type), 151 "access_type"); 152 } 153 154 /* internal defines */ 155 struct DisasContext { 156 DisasContextBase base; 157 uint32_t opcode; 158 uint32_t exception; 159 /* Routine used to access memory */ 160 bool pr, hv, dr, le_mode; 161 bool lazy_tlb_flush; 162 bool need_access_type; 163 int mem_idx; 164 int access_type; 165 /* Translation flags */ 166 MemOp default_tcg_memop_mask; 167 #if defined(TARGET_PPC64) 168 bool sf_mode; 169 bool has_cfar; 170 #endif 171 bool fpu_enabled; 172 bool altivec_enabled; 173 bool vsx_enabled; 174 bool spe_enabled; 175 bool tm_enabled; 176 bool gtse; 177 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 178 int singlestep_enabled; 179 uint32_t flags; 180 uint64_t insns_flags; 181 uint64_t insns_flags2; 182 }; 183 184 /* Return true iff byteswap is needed in a scalar memop */ 185 static inline bool need_byteswap(const DisasContext *ctx) 186 { 187 #if defined(TARGET_WORDS_BIGENDIAN) 188 return ctx->le_mode; 189 #else 190 return !ctx->le_mode; 191 #endif 192 } 193 194 /* True when active word size < size of target_long. */ 195 #ifdef TARGET_PPC64 196 # define NARROW_MODE(C) (!(C)->sf_mode) 197 #else 198 # define NARROW_MODE(C) 0 199 #endif 200 201 struct opc_handler_t { 202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 203 uint32_t inval1; 204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 205 uint32_t inval2; 206 /* instruction type */ 207 uint64_t type; 208 /* extended instruction type */ 209 uint64_t type2; 210 /* handler */ 211 void (*handler)(DisasContext *ctx); 212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 213 const char *oname; 214 #endif 215 #if defined(DO_PPC_STATISTICS) 216 uint64_t count; 217 #endif 218 }; 219 220 /* SPR load/store helpers */ 221 static inline void gen_load_spr(TCGv t, int reg) 222 { 223 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 224 } 225 226 static inline void gen_store_spr(int reg, TCGv t) 227 { 228 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 229 } 230 231 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232 { 233 if (ctx->need_access_type && ctx->access_type != access_type) { 234 tcg_gen_movi_i32(cpu_access_type, access_type); 235 ctx->access_type = access_type; 236 } 237 } 238 239 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240 { 241 if (NARROW_MODE(ctx)) { 242 nip = (uint32_t)nip; 243 } 244 tcg_gen_movi_tl(cpu_nip, nip); 245 } 246 247 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248 { 249 TCGv_i32 t0, t1; 250 251 /* 252 * These are all synchronous exceptions, we set the PC back to the 253 * faulting instruction 254 */ 255 if (ctx->exception == POWERPC_EXCP_NONE) { 256 gen_update_nip(ctx, ctx->base.pc_next - 4); 257 } 258 t0 = tcg_const_i32(excp); 259 t1 = tcg_const_i32(error); 260 gen_helper_raise_exception_err(cpu_env, t0, t1); 261 tcg_temp_free_i32(t0); 262 tcg_temp_free_i32(t1); 263 ctx->exception = (excp); 264 } 265 266 static void gen_exception(DisasContext *ctx, uint32_t excp) 267 { 268 TCGv_i32 t0; 269 270 /* 271 * These are all synchronous exceptions, we set the PC back to the 272 * faulting instruction 273 */ 274 if (ctx->exception == POWERPC_EXCP_NONE) { 275 gen_update_nip(ctx, ctx->base.pc_next - 4); 276 } 277 t0 = tcg_const_i32(excp); 278 gen_helper_raise_exception(cpu_env, t0); 279 tcg_temp_free_i32(t0); 280 ctx->exception = (excp); 281 } 282 283 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 284 target_ulong nip) 285 { 286 TCGv_i32 t0; 287 288 gen_update_nip(ctx, nip); 289 t0 = tcg_const_i32(excp); 290 gen_helper_raise_exception(cpu_env, t0); 291 tcg_temp_free_i32(t0); 292 ctx->exception = (excp); 293 } 294 295 /* 296 * Tells the caller what is the appropriate exception to generate and prepares 297 * SPR registers for this exception. 298 * 299 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 300 * POWERPC_EXCP_DEBUG (on BookE). 301 */ 302 static uint32_t gen_prep_dbgex(DisasContext *ctx) 303 { 304 if (ctx->flags & POWERPC_FLAG_DE) { 305 target_ulong dbsr = 0; 306 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 307 dbsr = DBCR0_ICMP; 308 } else { 309 /* Must have been branch */ 310 dbsr = DBCR0_BRT; 311 } 312 TCGv t0 = tcg_temp_new(); 313 gen_load_spr(t0, SPR_BOOKE_DBSR); 314 tcg_gen_ori_tl(t0, t0, dbsr); 315 gen_store_spr(SPR_BOOKE_DBSR, t0); 316 tcg_temp_free(t0); 317 return POWERPC_EXCP_DEBUG; 318 } else { 319 return POWERPC_EXCP_TRACE; 320 } 321 } 322 323 static void gen_debug_exception(DisasContext *ctx) 324 { 325 TCGv_i32 t0; 326 327 /* 328 * These are all synchronous exceptions, we set the PC back to the 329 * faulting instruction 330 */ 331 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 332 (ctx->exception != POWERPC_EXCP_SYNC)) { 333 gen_update_nip(ctx, ctx->base.pc_next); 334 } 335 t0 = tcg_const_i32(EXCP_DEBUG); 336 gen_helper_raise_exception(cpu_env, t0); 337 tcg_temp_free_i32(t0); 338 } 339 340 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341 { 342 /* Will be converted to program check if needed */ 343 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344 } 345 346 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347 { 348 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349 } 350 351 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352 { 353 /* Will be converted to program check if needed */ 354 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355 } 356 357 /* Stop translation */ 358 static inline void gen_stop_exception(DisasContext *ctx) 359 { 360 gen_update_nip(ctx, ctx->base.pc_next); 361 ctx->exception = POWERPC_EXCP_STOP; 362 } 363 364 #ifndef CONFIG_USER_ONLY 365 /* No need to update nip here, as execution flow will change */ 366 static inline void gen_sync_exception(DisasContext *ctx) 367 { 368 ctx->exception = POWERPC_EXCP_SYNC; 369 } 370 #endif 371 372 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 373 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 374 375 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 376 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 377 378 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 379 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 380 381 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 382 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 383 384 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 385 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 386 387 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 388 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 389 390 typedef struct opcode_t { 391 unsigned char opc1, opc2, opc3, opc4; 392 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 393 unsigned char pad[4]; 394 #endif 395 opc_handler_t handler; 396 const char *oname; 397 } opcode_t; 398 399 /* Helpers for priv. check */ 400 #define GEN_PRIV \ 401 do { \ 402 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 403 } while (0) 404 405 #if defined(CONFIG_USER_ONLY) 406 #define CHK_HV GEN_PRIV 407 #define CHK_SV GEN_PRIV 408 #define CHK_HVRM GEN_PRIV 409 #else 410 #define CHK_HV \ 411 do { \ 412 if (unlikely(ctx->pr || !ctx->hv)) { \ 413 GEN_PRIV; \ 414 } \ 415 } while (0) 416 #define CHK_SV \ 417 do { \ 418 if (unlikely(ctx->pr)) { \ 419 GEN_PRIV; \ 420 } \ 421 } while (0) 422 #define CHK_HVRM \ 423 do { \ 424 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 425 GEN_PRIV; \ 426 } \ 427 } while (0) 428 #endif 429 430 #define CHK_NONE 431 432 /*****************************************************************************/ 433 /* PowerPC instructions table */ 434 435 #if defined(DO_PPC_STATISTICS) 436 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 437 { \ 438 .opc1 = op1, \ 439 .opc2 = op2, \ 440 .opc3 = op3, \ 441 .opc4 = 0xff, \ 442 .handler = { \ 443 .inval1 = invl, \ 444 .type = _typ, \ 445 .type2 = _typ2, \ 446 .handler = &gen_##name, \ 447 .oname = stringify(name), \ 448 }, \ 449 .oname = stringify(name), \ 450 } 451 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 452 { \ 453 .opc1 = op1, \ 454 .opc2 = op2, \ 455 .opc3 = op3, \ 456 .opc4 = 0xff, \ 457 .handler = { \ 458 .inval1 = invl1, \ 459 .inval2 = invl2, \ 460 .type = _typ, \ 461 .type2 = _typ2, \ 462 .handler = &gen_##name, \ 463 .oname = stringify(name), \ 464 }, \ 465 .oname = stringify(name), \ 466 } 467 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 468 { \ 469 .opc1 = op1, \ 470 .opc2 = op2, \ 471 .opc3 = op3, \ 472 .opc4 = 0xff, \ 473 .handler = { \ 474 .inval1 = invl, \ 475 .type = _typ, \ 476 .type2 = _typ2, \ 477 .handler = &gen_##name, \ 478 .oname = onam, \ 479 }, \ 480 .oname = onam, \ 481 } 482 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 483 { \ 484 .opc1 = op1, \ 485 .opc2 = op2, \ 486 .opc3 = op3, \ 487 .opc4 = op4, \ 488 .handler = { \ 489 .inval1 = invl, \ 490 .type = _typ, \ 491 .type2 = _typ2, \ 492 .handler = &gen_##name, \ 493 .oname = stringify(name), \ 494 }, \ 495 .oname = stringify(name), \ 496 } 497 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 498 { \ 499 .opc1 = op1, \ 500 .opc2 = op2, \ 501 .opc3 = op3, \ 502 .opc4 = op4, \ 503 .handler = { \ 504 .inval1 = invl, \ 505 .type = _typ, \ 506 .type2 = _typ2, \ 507 .handler = &gen_##name, \ 508 .oname = onam, \ 509 }, \ 510 .oname = onam, \ 511 } 512 #else 513 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 514 { \ 515 .opc1 = op1, \ 516 .opc2 = op2, \ 517 .opc3 = op3, \ 518 .opc4 = 0xff, \ 519 .handler = { \ 520 .inval1 = invl, \ 521 .type = _typ, \ 522 .type2 = _typ2, \ 523 .handler = &gen_##name, \ 524 }, \ 525 .oname = stringify(name), \ 526 } 527 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 528 { \ 529 .opc1 = op1, \ 530 .opc2 = op2, \ 531 .opc3 = op3, \ 532 .opc4 = 0xff, \ 533 .handler = { \ 534 .inval1 = invl1, \ 535 .inval2 = invl2, \ 536 .type = _typ, \ 537 .type2 = _typ2, \ 538 .handler = &gen_##name, \ 539 }, \ 540 .oname = stringify(name), \ 541 } 542 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 543 { \ 544 .opc1 = op1, \ 545 .opc2 = op2, \ 546 .opc3 = op3, \ 547 .opc4 = 0xff, \ 548 .handler = { \ 549 .inval1 = invl, \ 550 .type = _typ, \ 551 .type2 = _typ2, \ 552 .handler = &gen_##name, \ 553 }, \ 554 .oname = onam, \ 555 } 556 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 557 { \ 558 .opc1 = op1, \ 559 .opc2 = op2, \ 560 .opc3 = op3, \ 561 .opc4 = op4, \ 562 .handler = { \ 563 .inval1 = invl, \ 564 .type = _typ, \ 565 .type2 = _typ2, \ 566 .handler = &gen_##name, \ 567 }, \ 568 .oname = stringify(name), \ 569 } 570 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 571 { \ 572 .opc1 = op1, \ 573 .opc2 = op2, \ 574 .opc3 = op3, \ 575 .opc4 = op4, \ 576 .handler = { \ 577 .inval1 = invl, \ 578 .type = _typ, \ 579 .type2 = _typ2, \ 580 .handler = &gen_##name, \ 581 }, \ 582 .oname = onam, \ 583 } 584 #endif 585 586 /* Invalid instruction */ 587 static void gen_invalid(DisasContext *ctx) 588 { 589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 590 } 591 592 static opc_handler_t invalid_handler = { 593 .inval1 = 0xFFFFFFFF, 594 .inval2 = 0xFFFFFFFF, 595 .type = PPC_NONE, 596 .type2 = PPC_NONE, 597 .handler = gen_invalid, 598 }; 599 600 /*** Integer comparison ***/ 601 602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 603 { 604 TCGv t0 = tcg_temp_new(); 605 TCGv t1 = tcg_temp_new(); 606 TCGv_i32 t = tcg_temp_new_i32(); 607 608 tcg_gen_movi_tl(t0, CRF_EQ); 609 tcg_gen_movi_tl(t1, CRF_LT); 610 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 611 t0, arg0, arg1, t1, t0); 612 tcg_gen_movi_tl(t1, CRF_GT); 613 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 614 t0, arg0, arg1, t1, t0); 615 616 tcg_gen_trunc_tl_i32(t, t0); 617 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 618 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 619 620 tcg_temp_free(t0); 621 tcg_temp_free(t1); 622 tcg_temp_free_i32(t); 623 } 624 625 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 626 { 627 TCGv t0 = tcg_const_tl(arg1); 628 gen_op_cmp(arg0, t0, s, crf); 629 tcg_temp_free(t0); 630 } 631 632 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 633 { 634 TCGv t0, t1; 635 t0 = tcg_temp_new(); 636 t1 = tcg_temp_new(); 637 if (s) { 638 tcg_gen_ext32s_tl(t0, arg0); 639 tcg_gen_ext32s_tl(t1, arg1); 640 } else { 641 tcg_gen_ext32u_tl(t0, arg0); 642 tcg_gen_ext32u_tl(t1, arg1); 643 } 644 gen_op_cmp(t0, t1, s, crf); 645 tcg_temp_free(t1); 646 tcg_temp_free(t0); 647 } 648 649 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 650 { 651 TCGv t0 = tcg_const_tl(arg1); 652 gen_op_cmp32(arg0, t0, s, crf); 653 tcg_temp_free(t0); 654 } 655 656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 657 { 658 if (NARROW_MODE(ctx)) { 659 gen_op_cmpi32(reg, 0, 1, 0); 660 } else { 661 gen_op_cmpi(reg, 0, 1, 0); 662 } 663 } 664 665 /* cmp */ 666 static void gen_cmp(DisasContext *ctx) 667 { 668 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 669 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 670 1, crfD(ctx->opcode)); 671 } else { 672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 673 1, crfD(ctx->opcode)); 674 } 675 } 676 677 /* cmpi */ 678 static void gen_cmpi(DisasContext *ctx) 679 { 680 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 681 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 682 1, crfD(ctx->opcode)); 683 } else { 684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 685 1, crfD(ctx->opcode)); 686 } 687 } 688 689 /* cmpl */ 690 static void gen_cmpl(DisasContext *ctx) 691 { 692 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 693 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 694 0, crfD(ctx->opcode)); 695 } else { 696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 697 0, crfD(ctx->opcode)); 698 } 699 } 700 701 /* cmpli */ 702 static void gen_cmpli(DisasContext *ctx) 703 { 704 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 705 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 706 0, crfD(ctx->opcode)); 707 } else { 708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 709 0, crfD(ctx->opcode)); 710 } 711 } 712 713 /* cmprb - range comparison: isupper, isaplha, islower*/ 714 static void gen_cmprb(DisasContext *ctx) 715 { 716 TCGv_i32 src1 = tcg_temp_new_i32(); 717 TCGv_i32 src2 = tcg_temp_new_i32(); 718 TCGv_i32 src2lo = tcg_temp_new_i32(); 719 TCGv_i32 src2hi = tcg_temp_new_i32(); 720 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 721 722 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 723 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 724 725 tcg_gen_andi_i32(src1, src1, 0xFF); 726 tcg_gen_ext8u_i32(src2lo, src2); 727 tcg_gen_shri_i32(src2, src2, 8); 728 tcg_gen_ext8u_i32(src2hi, src2); 729 730 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 731 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 732 tcg_gen_and_i32(crf, src2lo, src2hi); 733 734 if (ctx->opcode & 0x00200000) { 735 tcg_gen_shri_i32(src2, src2, 8); 736 tcg_gen_ext8u_i32(src2lo, src2); 737 tcg_gen_shri_i32(src2, src2, 8); 738 tcg_gen_ext8u_i32(src2hi, src2); 739 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 740 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 741 tcg_gen_and_i32(src2lo, src2lo, src2hi); 742 tcg_gen_or_i32(crf, crf, src2lo); 743 } 744 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 745 tcg_temp_free_i32(src1); 746 tcg_temp_free_i32(src2); 747 tcg_temp_free_i32(src2lo); 748 tcg_temp_free_i32(src2hi); 749 } 750 751 #if defined(TARGET_PPC64) 752 /* cmpeqb */ 753 static void gen_cmpeqb(DisasContext *ctx) 754 { 755 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 756 cpu_gpr[rB(ctx->opcode)]); 757 } 758 #endif 759 760 /* isel (PowerPC 2.03 specification) */ 761 static void gen_isel(DisasContext *ctx) 762 { 763 uint32_t bi = rC(ctx->opcode); 764 uint32_t mask = 0x08 >> (bi & 0x03); 765 TCGv t0 = tcg_temp_new(); 766 TCGv zr; 767 768 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 769 tcg_gen_andi_tl(t0, t0, mask); 770 771 zr = tcg_const_tl(0); 772 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 773 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 774 cpu_gpr[rB(ctx->opcode)]); 775 tcg_temp_free(zr); 776 tcg_temp_free(t0); 777 } 778 779 /* cmpb: PowerPC 2.05 specification */ 780 static void gen_cmpb(DisasContext *ctx) 781 { 782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 783 cpu_gpr[rB(ctx->opcode)]); 784 } 785 786 /*** Integer arithmetic ***/ 787 788 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 789 TCGv arg1, TCGv arg2, int sub) 790 { 791 TCGv t0 = tcg_temp_new(); 792 793 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 794 tcg_gen_xor_tl(t0, arg1, arg2); 795 if (sub) { 796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 797 } else { 798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 799 } 800 tcg_temp_free(t0); 801 if (NARROW_MODE(ctx)) { 802 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 803 if (is_isa300(ctx)) { 804 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 805 } 806 } else { 807 if (is_isa300(ctx)) { 808 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 809 } 810 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 811 } 812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813 } 814 815 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 816 TCGv res, TCGv arg0, TCGv arg1, 817 TCGv ca32, int sub) 818 { 819 TCGv t0; 820 821 if (!is_isa300(ctx)) { 822 return; 823 } 824 825 t0 = tcg_temp_new(); 826 if (sub) { 827 tcg_gen_eqv_tl(t0, arg0, arg1); 828 } else { 829 tcg_gen_xor_tl(t0, arg0, arg1); 830 } 831 tcg_gen_xor_tl(t0, t0, res); 832 tcg_gen_extract_tl(ca32, t0, 32, 1); 833 tcg_temp_free(t0); 834 } 835 836 /* Common add function */ 837 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 838 TCGv arg2, TCGv ca, TCGv ca32, 839 bool add_ca, bool compute_ca, 840 bool compute_ov, bool compute_rc0) 841 { 842 TCGv t0 = ret; 843 844 if (compute_ca || compute_ov) { 845 t0 = tcg_temp_new(); 846 } 847 848 if (compute_ca) { 849 if (NARROW_MODE(ctx)) { 850 /* 851 * Caution: a non-obvious corner case of the spec is that 852 * we must produce the *entire* 64-bit addition, but 853 * produce the carry into bit 32. 854 */ 855 TCGv t1 = tcg_temp_new(); 856 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 857 tcg_gen_add_tl(t0, arg1, arg2); 858 if (add_ca) { 859 tcg_gen_add_tl(t0, t0, ca); 860 } 861 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 862 tcg_temp_free(t1); 863 tcg_gen_extract_tl(ca, ca, 32, 1); 864 if (is_isa300(ctx)) { 865 tcg_gen_mov_tl(ca32, ca); 866 } 867 } else { 868 TCGv zero = tcg_const_tl(0); 869 if (add_ca) { 870 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 871 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 872 } else { 873 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 874 } 875 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 876 tcg_temp_free(zero); 877 } 878 } else { 879 tcg_gen_add_tl(t0, arg1, arg2); 880 if (add_ca) { 881 tcg_gen_add_tl(t0, t0, ca); 882 } 883 } 884 885 if (compute_ov) { 886 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 887 } 888 if (unlikely(compute_rc0)) { 889 gen_set_Rc0(ctx, t0); 890 } 891 892 if (t0 != ret) { 893 tcg_gen_mov_tl(ret, t0); 894 tcg_temp_free(t0); 895 } 896 } 897 /* Add functions with two operands */ 898 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 899 static void glue(gen_, name)(DisasContext *ctx) \ 900 { \ 901 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 902 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 903 ca, glue(ca, 32), \ 904 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 905 } 906 /* Add functions with one operand and one immediate */ 907 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 908 add_ca, compute_ca, compute_ov) \ 909 static void glue(gen_, name)(DisasContext *ctx) \ 910 { \ 911 TCGv t0 = tcg_const_tl(const_val); \ 912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 913 cpu_gpr[rA(ctx->opcode)], t0, \ 914 ca, glue(ca, 32), \ 915 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 916 tcg_temp_free(t0); \ 917 } 918 919 /* add add. addo addo. */ 920 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 921 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 922 /* addc addc. addco addco. */ 923 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 924 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 925 /* adde adde. addeo addeo. */ 926 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 927 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 928 /* addme addme. addmeo addmeo. */ 929 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 930 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 931 /* addex */ 932 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 933 /* addze addze. addzeo addzeo.*/ 934 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 935 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 936 /* addi */ 937 static void gen_addi(DisasContext *ctx) 938 { 939 target_long simm = SIMM(ctx->opcode); 940 941 if (rA(ctx->opcode) == 0) { 942 /* li case */ 943 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 944 } else { 945 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 946 cpu_gpr[rA(ctx->opcode)], simm); 947 } 948 } 949 /* addic addic.*/ 950 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 951 { 952 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 953 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 954 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 955 tcg_temp_free(c); 956 } 957 958 static void gen_addic(DisasContext *ctx) 959 { 960 gen_op_addic(ctx, 0); 961 } 962 963 static void gen_addic_(DisasContext *ctx) 964 { 965 gen_op_addic(ctx, 1); 966 } 967 968 /* addis */ 969 static void gen_addis(DisasContext *ctx) 970 { 971 target_long simm = SIMM(ctx->opcode); 972 973 if (rA(ctx->opcode) == 0) { 974 /* lis case */ 975 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 976 } else { 977 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 978 cpu_gpr[rA(ctx->opcode)], simm << 16); 979 } 980 } 981 982 /* addpcis */ 983 static void gen_addpcis(DisasContext *ctx) 984 { 985 target_long d = DX(ctx->opcode); 986 987 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 988 } 989 990 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 991 TCGv arg2, int sign, int compute_ov) 992 { 993 TCGv_i32 t0 = tcg_temp_new_i32(); 994 TCGv_i32 t1 = tcg_temp_new_i32(); 995 TCGv_i32 t2 = tcg_temp_new_i32(); 996 TCGv_i32 t3 = tcg_temp_new_i32(); 997 998 tcg_gen_trunc_tl_i32(t0, arg1); 999 tcg_gen_trunc_tl_i32(t1, arg2); 1000 if (sign) { 1001 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1002 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1003 tcg_gen_and_i32(t2, t2, t3); 1004 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1005 tcg_gen_or_i32(t2, t2, t3); 1006 tcg_gen_movi_i32(t3, 0); 1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008 tcg_gen_div_i32(t3, t0, t1); 1009 tcg_gen_extu_i32_tl(ret, t3); 1010 } else { 1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1012 tcg_gen_movi_i32(t3, 0); 1013 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1014 tcg_gen_divu_i32(t3, t0, t1); 1015 tcg_gen_extu_i32_tl(ret, t3); 1016 } 1017 if (compute_ov) { 1018 tcg_gen_extu_i32_tl(cpu_ov, t2); 1019 if (is_isa300(ctx)) { 1020 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1021 } 1022 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1023 } 1024 tcg_temp_free_i32(t0); 1025 tcg_temp_free_i32(t1); 1026 tcg_temp_free_i32(t2); 1027 tcg_temp_free_i32(t3); 1028 1029 if (unlikely(Rc(ctx->opcode) != 0)) { 1030 gen_set_Rc0(ctx, ret); 1031 } 1032 } 1033 /* Div functions */ 1034 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1035 static void glue(gen_, name)(DisasContext *ctx) \ 1036 { \ 1037 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1039 sign, compute_ov); \ 1040 } 1041 /* divwu divwu. divwuo divwuo. */ 1042 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1043 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1044 /* divw divw. divwo divwo. */ 1045 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1046 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1047 1048 /* div[wd]eu[o][.] */ 1049 #define GEN_DIVE(name, hlpr, compute_ov) \ 1050 static void gen_##name(DisasContext *ctx) \ 1051 { \ 1052 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1053 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1055 tcg_temp_free_i32(t0); \ 1056 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1058 } \ 1059 } 1060 1061 GEN_DIVE(divweu, divweu, 0); 1062 GEN_DIVE(divweuo, divweu, 1); 1063 GEN_DIVE(divwe, divwe, 0); 1064 GEN_DIVE(divweo, divwe, 1); 1065 1066 #if defined(TARGET_PPC64) 1067 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1068 TCGv arg2, int sign, int compute_ov) 1069 { 1070 TCGv_i64 t0 = tcg_temp_new_i64(); 1071 TCGv_i64 t1 = tcg_temp_new_i64(); 1072 TCGv_i64 t2 = tcg_temp_new_i64(); 1073 TCGv_i64 t3 = tcg_temp_new_i64(); 1074 1075 tcg_gen_mov_i64(t0, arg1); 1076 tcg_gen_mov_i64(t1, arg2); 1077 if (sign) { 1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1080 tcg_gen_and_i64(t2, t2, t3); 1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1082 tcg_gen_or_i64(t2, t2, t3); 1083 tcg_gen_movi_i64(t3, 0); 1084 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1085 tcg_gen_div_i64(ret, t0, t1); 1086 } else { 1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1088 tcg_gen_movi_i64(t3, 0); 1089 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1090 tcg_gen_divu_i64(ret, t0, t1); 1091 } 1092 if (compute_ov) { 1093 tcg_gen_mov_tl(cpu_ov, t2); 1094 if (is_isa300(ctx)) { 1095 tcg_gen_mov_tl(cpu_ov32, t2); 1096 } 1097 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1098 } 1099 tcg_temp_free_i64(t0); 1100 tcg_temp_free_i64(t1); 1101 tcg_temp_free_i64(t2); 1102 tcg_temp_free_i64(t3); 1103 1104 if (unlikely(Rc(ctx->opcode) != 0)) { 1105 gen_set_Rc0(ctx, ret); 1106 } 1107 } 1108 1109 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1110 static void glue(gen_, name)(DisasContext *ctx) \ 1111 { \ 1112 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1114 sign, compute_ov); \ 1115 } 1116 /* divdu divdu. divduo divduo. */ 1117 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1118 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1119 /* divd divd. divdo divdo. */ 1120 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1121 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1122 1123 GEN_DIVE(divdeu, divdeu, 0); 1124 GEN_DIVE(divdeuo, divdeu, 1); 1125 GEN_DIVE(divde, divde, 0); 1126 GEN_DIVE(divdeo, divde, 1); 1127 #endif 1128 1129 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1130 TCGv arg2, int sign) 1131 { 1132 TCGv_i32 t0 = tcg_temp_new_i32(); 1133 TCGv_i32 t1 = tcg_temp_new_i32(); 1134 1135 tcg_gen_trunc_tl_i32(t0, arg1); 1136 tcg_gen_trunc_tl_i32(t1, arg2); 1137 if (sign) { 1138 TCGv_i32 t2 = tcg_temp_new_i32(); 1139 TCGv_i32 t3 = tcg_temp_new_i32(); 1140 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1141 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1142 tcg_gen_and_i32(t2, t2, t3); 1143 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1144 tcg_gen_or_i32(t2, t2, t3); 1145 tcg_gen_movi_i32(t3, 0); 1146 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1147 tcg_gen_rem_i32(t3, t0, t1); 1148 tcg_gen_ext_i32_tl(ret, t3); 1149 tcg_temp_free_i32(t2); 1150 tcg_temp_free_i32(t3); 1151 } else { 1152 TCGv_i32 t2 = tcg_const_i32(1); 1153 TCGv_i32 t3 = tcg_const_i32(0); 1154 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1155 tcg_gen_remu_i32(t3, t0, t1); 1156 tcg_gen_extu_i32_tl(ret, t3); 1157 tcg_temp_free_i32(t2); 1158 tcg_temp_free_i32(t3); 1159 } 1160 tcg_temp_free_i32(t0); 1161 tcg_temp_free_i32(t1); 1162 } 1163 1164 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1165 static void glue(gen_, name)(DisasContext *ctx) \ 1166 { \ 1167 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1168 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1169 sign); \ 1170 } 1171 1172 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1173 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1174 1175 #if defined(TARGET_PPC64) 1176 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1177 TCGv arg2, int sign) 1178 { 1179 TCGv_i64 t0 = tcg_temp_new_i64(); 1180 TCGv_i64 t1 = tcg_temp_new_i64(); 1181 1182 tcg_gen_mov_i64(t0, arg1); 1183 tcg_gen_mov_i64(t1, arg2); 1184 if (sign) { 1185 TCGv_i64 t2 = tcg_temp_new_i64(); 1186 TCGv_i64 t3 = tcg_temp_new_i64(); 1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1189 tcg_gen_and_i64(t2, t2, t3); 1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1191 tcg_gen_or_i64(t2, t2, t3); 1192 tcg_gen_movi_i64(t3, 0); 1193 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1194 tcg_gen_rem_i64(ret, t0, t1); 1195 tcg_temp_free_i64(t2); 1196 tcg_temp_free_i64(t3); 1197 } else { 1198 TCGv_i64 t2 = tcg_const_i64(1); 1199 TCGv_i64 t3 = tcg_const_i64(0); 1200 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1201 tcg_gen_remu_i64(ret, t0, t1); 1202 tcg_temp_free_i64(t2); 1203 tcg_temp_free_i64(t3); 1204 } 1205 tcg_temp_free_i64(t0); 1206 tcg_temp_free_i64(t1); 1207 } 1208 1209 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1210 static void glue(gen_, name)(DisasContext *ctx) \ 1211 { \ 1212 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1213 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1214 sign); \ 1215 } 1216 1217 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1218 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1219 #endif 1220 1221 /* mulhw mulhw. */ 1222 static void gen_mulhw(DisasContext *ctx) 1223 { 1224 TCGv_i32 t0 = tcg_temp_new_i32(); 1225 TCGv_i32 t1 = tcg_temp_new_i32(); 1226 1227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1229 tcg_gen_muls2_i32(t0, t1, t0, t1); 1230 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1231 tcg_temp_free_i32(t0); 1232 tcg_temp_free_i32(t1); 1233 if (unlikely(Rc(ctx->opcode) != 0)) { 1234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1235 } 1236 } 1237 1238 /* mulhwu mulhwu. */ 1239 static void gen_mulhwu(DisasContext *ctx) 1240 { 1241 TCGv_i32 t0 = tcg_temp_new_i32(); 1242 TCGv_i32 t1 = tcg_temp_new_i32(); 1243 1244 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1245 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1246 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1247 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1248 tcg_temp_free_i32(t0); 1249 tcg_temp_free_i32(t1); 1250 if (unlikely(Rc(ctx->opcode) != 0)) { 1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1252 } 1253 } 1254 1255 /* mullw mullw. */ 1256 static void gen_mullw(DisasContext *ctx) 1257 { 1258 #if defined(TARGET_PPC64) 1259 TCGv_i64 t0, t1; 1260 t0 = tcg_temp_new_i64(); 1261 t1 = tcg_temp_new_i64(); 1262 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1263 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1264 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1265 tcg_temp_free(t0); 1266 tcg_temp_free(t1); 1267 #else 1268 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1269 cpu_gpr[rB(ctx->opcode)]); 1270 #endif 1271 if (unlikely(Rc(ctx->opcode) != 0)) { 1272 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1273 } 1274 } 1275 1276 /* mullwo mullwo. */ 1277 static void gen_mullwo(DisasContext *ctx) 1278 { 1279 TCGv_i32 t0 = tcg_temp_new_i32(); 1280 TCGv_i32 t1 = tcg_temp_new_i32(); 1281 1282 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1283 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1284 tcg_gen_muls2_i32(t0, t1, t0, t1); 1285 #if defined(TARGET_PPC64) 1286 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1287 #else 1288 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1289 #endif 1290 1291 tcg_gen_sari_i32(t0, t0, 31); 1292 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1293 tcg_gen_extu_i32_tl(cpu_ov, t0); 1294 if (is_isa300(ctx)) { 1295 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1296 } 1297 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1298 1299 tcg_temp_free_i32(t0); 1300 tcg_temp_free_i32(t1); 1301 if (unlikely(Rc(ctx->opcode) != 0)) { 1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1303 } 1304 } 1305 1306 /* mulli */ 1307 static void gen_mulli(DisasContext *ctx) 1308 { 1309 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1310 SIMM(ctx->opcode)); 1311 } 1312 1313 #if defined(TARGET_PPC64) 1314 /* mulhd mulhd. */ 1315 static void gen_mulhd(DisasContext *ctx) 1316 { 1317 TCGv lo = tcg_temp_new(); 1318 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320 tcg_temp_free(lo); 1321 if (unlikely(Rc(ctx->opcode) != 0)) { 1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323 } 1324 } 1325 1326 /* mulhdu mulhdu. */ 1327 static void gen_mulhdu(DisasContext *ctx) 1328 { 1329 TCGv lo = tcg_temp_new(); 1330 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1331 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1332 tcg_temp_free(lo); 1333 if (unlikely(Rc(ctx->opcode) != 0)) { 1334 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1335 } 1336 } 1337 1338 /* mulld mulld. */ 1339 static void gen_mulld(DisasContext *ctx) 1340 { 1341 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1342 cpu_gpr[rB(ctx->opcode)]); 1343 if (unlikely(Rc(ctx->opcode) != 0)) { 1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1345 } 1346 } 1347 1348 /* mulldo mulldo. */ 1349 static void gen_mulldo(DisasContext *ctx) 1350 { 1351 TCGv_i64 t0 = tcg_temp_new_i64(); 1352 TCGv_i64 t1 = tcg_temp_new_i64(); 1353 1354 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1355 cpu_gpr[rB(ctx->opcode)]); 1356 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1357 1358 tcg_gen_sari_i64(t0, t0, 63); 1359 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1360 if (is_isa300(ctx)) { 1361 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1362 } 1363 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1364 1365 tcg_temp_free_i64(t0); 1366 tcg_temp_free_i64(t1); 1367 1368 if (unlikely(Rc(ctx->opcode) != 0)) { 1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1370 } 1371 } 1372 #endif 1373 1374 /* Common subf function */ 1375 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1376 TCGv arg2, bool add_ca, bool compute_ca, 1377 bool compute_ov, bool compute_rc0) 1378 { 1379 TCGv t0 = ret; 1380 1381 if (compute_ca || compute_ov) { 1382 t0 = tcg_temp_new(); 1383 } 1384 1385 if (compute_ca) { 1386 /* dest = ~arg1 + arg2 [+ ca]. */ 1387 if (NARROW_MODE(ctx)) { 1388 /* 1389 * Caution: a non-obvious corner case of the spec is that 1390 * we must produce the *entire* 64-bit addition, but 1391 * produce the carry into bit 32. 1392 */ 1393 TCGv inv1 = tcg_temp_new(); 1394 TCGv t1 = tcg_temp_new(); 1395 tcg_gen_not_tl(inv1, arg1); 1396 if (add_ca) { 1397 tcg_gen_add_tl(t0, arg2, cpu_ca); 1398 } else { 1399 tcg_gen_addi_tl(t0, arg2, 1); 1400 } 1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1402 tcg_gen_add_tl(t0, t0, inv1); 1403 tcg_temp_free(inv1); 1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1405 tcg_temp_free(t1); 1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1407 if (is_isa300(ctx)) { 1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1409 } 1410 } else if (add_ca) { 1411 TCGv zero, inv1 = tcg_temp_new(); 1412 tcg_gen_not_tl(inv1, arg1); 1413 zero = tcg_const_tl(0); 1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1417 tcg_temp_free(zero); 1418 tcg_temp_free(inv1); 1419 } else { 1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1421 tcg_gen_sub_tl(t0, arg2, arg1); 1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1423 } 1424 } else if (add_ca) { 1425 /* 1426 * Since we're ignoring carry-out, we can simplify the 1427 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1428 */ 1429 tcg_gen_sub_tl(t0, arg2, arg1); 1430 tcg_gen_add_tl(t0, t0, cpu_ca); 1431 tcg_gen_subi_tl(t0, t0, 1); 1432 } else { 1433 tcg_gen_sub_tl(t0, arg2, arg1); 1434 } 1435 1436 if (compute_ov) { 1437 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1438 } 1439 if (unlikely(compute_rc0)) { 1440 gen_set_Rc0(ctx, t0); 1441 } 1442 1443 if (t0 != ret) { 1444 tcg_gen_mov_tl(ret, t0); 1445 tcg_temp_free(t0); 1446 } 1447 } 1448 /* Sub functions with Two operands functions */ 1449 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1450 static void glue(gen_, name)(DisasContext *ctx) \ 1451 { \ 1452 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1453 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1454 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1455 } 1456 /* Sub functions with one operand and one immediate */ 1457 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1458 add_ca, compute_ca, compute_ov) \ 1459 static void glue(gen_, name)(DisasContext *ctx) \ 1460 { \ 1461 TCGv t0 = tcg_const_tl(const_val); \ 1462 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1463 cpu_gpr[rA(ctx->opcode)], t0, \ 1464 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1465 tcg_temp_free(t0); \ 1466 } 1467 /* subf subf. subfo subfo. */ 1468 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1469 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1470 /* subfc subfc. subfco subfco. */ 1471 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1472 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1473 /* subfe subfe. subfeo subfo. */ 1474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1476 /* subfme subfme. subfmeo subfmeo. */ 1477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1479 /* subfze subfze. subfzeo subfzeo.*/ 1480 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1481 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1482 1483 /* subfic */ 1484 static void gen_subfic(DisasContext *ctx) 1485 { 1486 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488 c, 0, 1, 0, 0); 1489 tcg_temp_free(c); 1490 } 1491 1492 /* neg neg. nego nego. */ 1493 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1494 { 1495 TCGv zero = tcg_const_tl(0); 1496 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1497 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1498 tcg_temp_free(zero); 1499 } 1500 1501 static void gen_neg(DisasContext *ctx) 1502 { 1503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1504 if (unlikely(Rc(ctx->opcode))) { 1505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1506 } 1507 } 1508 1509 static void gen_nego(DisasContext *ctx) 1510 { 1511 gen_op_arith_neg(ctx, 1); 1512 } 1513 1514 /*** Integer logical ***/ 1515 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1516 static void glue(gen_, name)(DisasContext *ctx) \ 1517 { \ 1518 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1519 cpu_gpr[rB(ctx->opcode)]); \ 1520 if (unlikely(Rc(ctx->opcode) != 0)) \ 1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1522 } 1523 1524 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1525 static void glue(gen_, name)(DisasContext *ctx) \ 1526 { \ 1527 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1528 if (unlikely(Rc(ctx->opcode) != 0)) \ 1529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1530 } 1531 1532 /* and & and. */ 1533 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1534 /* andc & andc. */ 1535 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1536 1537 /* andi. */ 1538 static void gen_andi_(DisasContext *ctx) 1539 { 1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1541 UIMM(ctx->opcode)); 1542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1543 } 1544 1545 /* andis. */ 1546 static void gen_andis_(DisasContext *ctx) 1547 { 1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549 UIMM(ctx->opcode) << 16); 1550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1551 } 1552 1553 /* cntlzw */ 1554 static void gen_cntlzw(DisasContext *ctx) 1555 { 1556 TCGv_i32 t = tcg_temp_new_i32(); 1557 1558 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1559 tcg_gen_clzi_i32(t, t, 32); 1560 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1561 tcg_temp_free_i32(t); 1562 1563 if (unlikely(Rc(ctx->opcode) != 0)) { 1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1565 } 1566 } 1567 1568 /* cnttzw */ 1569 static void gen_cnttzw(DisasContext *ctx) 1570 { 1571 TCGv_i32 t = tcg_temp_new_i32(); 1572 1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1574 tcg_gen_ctzi_i32(t, t, 32); 1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1576 tcg_temp_free_i32(t); 1577 1578 if (unlikely(Rc(ctx->opcode) != 0)) { 1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1580 } 1581 } 1582 1583 /* eqv & eqv. */ 1584 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1585 /* extsb & extsb. */ 1586 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1587 /* extsh & extsh. */ 1588 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1589 /* nand & nand. */ 1590 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1591 /* nor & nor. */ 1592 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1593 1594 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1595 static void gen_pause(DisasContext *ctx) 1596 { 1597 TCGv_i32 t0 = tcg_const_i32(0); 1598 tcg_gen_st_i32(t0, cpu_env, 1599 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1600 tcg_temp_free_i32(t0); 1601 1602 /* Stop translation, this gives other CPUs a chance to run */ 1603 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1604 } 1605 #endif /* defined(TARGET_PPC64) */ 1606 1607 /* or & or. */ 1608 static void gen_or(DisasContext *ctx) 1609 { 1610 int rs, ra, rb; 1611 1612 rs = rS(ctx->opcode); 1613 ra = rA(ctx->opcode); 1614 rb = rB(ctx->opcode); 1615 /* Optimisation for mr. ri case */ 1616 if (rs != ra || rs != rb) { 1617 if (rs != rb) { 1618 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1619 } else { 1620 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1621 } 1622 if (unlikely(Rc(ctx->opcode) != 0)) { 1623 gen_set_Rc0(ctx, cpu_gpr[ra]); 1624 } 1625 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1626 gen_set_Rc0(ctx, cpu_gpr[rs]); 1627 #if defined(TARGET_PPC64) 1628 } else if (rs != 0) { /* 0 is nop */ 1629 int prio = 0; 1630 1631 switch (rs) { 1632 case 1: 1633 /* Set process priority to low */ 1634 prio = 2; 1635 break; 1636 case 6: 1637 /* Set process priority to medium-low */ 1638 prio = 3; 1639 break; 1640 case 2: 1641 /* Set process priority to normal */ 1642 prio = 4; 1643 break; 1644 #if !defined(CONFIG_USER_ONLY) 1645 case 31: 1646 if (!ctx->pr) { 1647 /* Set process priority to very low */ 1648 prio = 1; 1649 } 1650 break; 1651 case 5: 1652 if (!ctx->pr) { 1653 /* Set process priority to medium-hight */ 1654 prio = 5; 1655 } 1656 break; 1657 case 3: 1658 if (!ctx->pr) { 1659 /* Set process priority to high */ 1660 prio = 6; 1661 } 1662 break; 1663 case 7: 1664 if (ctx->hv && !ctx->pr) { 1665 /* Set process priority to very high */ 1666 prio = 7; 1667 } 1668 break; 1669 #endif 1670 default: 1671 break; 1672 } 1673 if (prio) { 1674 TCGv t0 = tcg_temp_new(); 1675 gen_load_spr(t0, SPR_PPR); 1676 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1677 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1678 gen_store_spr(SPR_PPR, t0); 1679 tcg_temp_free(t0); 1680 } 1681 #if !defined(CONFIG_USER_ONLY) 1682 /* 1683 * Pause out of TCG otherwise spin loops with smt_low eat too 1684 * much CPU and the kernel hangs. This applies to all 1685 * encodings other than no-op, e.g., miso(rs=26), yield(27), 1686 * mdoio(29), mdoom(30), and all currently undefined. 1687 */ 1688 gen_pause(ctx); 1689 #endif 1690 #endif 1691 } 1692 } 1693 /* orc & orc. */ 1694 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1695 1696 /* xor & xor. */ 1697 static void gen_xor(DisasContext *ctx) 1698 { 1699 /* Optimisation for "set to zero" case */ 1700 if (rS(ctx->opcode) != rB(ctx->opcode)) { 1701 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1702 cpu_gpr[rB(ctx->opcode)]); 1703 } else { 1704 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1705 } 1706 if (unlikely(Rc(ctx->opcode) != 0)) { 1707 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1708 } 1709 } 1710 1711 /* ori */ 1712 static void gen_ori(DisasContext *ctx) 1713 { 1714 target_ulong uimm = UIMM(ctx->opcode); 1715 1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1717 return; 1718 } 1719 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1720 } 1721 1722 /* oris */ 1723 static void gen_oris(DisasContext *ctx) 1724 { 1725 target_ulong uimm = UIMM(ctx->opcode); 1726 1727 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1728 /* NOP */ 1729 return; 1730 } 1731 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1732 uimm << 16); 1733 } 1734 1735 /* xori */ 1736 static void gen_xori(DisasContext *ctx) 1737 { 1738 target_ulong uimm = UIMM(ctx->opcode); 1739 1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741 /* NOP */ 1742 return; 1743 } 1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1745 } 1746 1747 /* xoris */ 1748 static void gen_xoris(DisasContext *ctx) 1749 { 1750 target_ulong uimm = UIMM(ctx->opcode); 1751 1752 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1753 /* NOP */ 1754 return; 1755 } 1756 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1757 uimm << 16); 1758 } 1759 1760 /* popcntb : PowerPC 2.03 specification */ 1761 static void gen_popcntb(DisasContext *ctx) 1762 { 1763 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1764 } 1765 1766 static void gen_popcntw(DisasContext *ctx) 1767 { 1768 #if defined(TARGET_PPC64) 1769 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1770 #else 1771 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1772 #endif 1773 } 1774 1775 #if defined(TARGET_PPC64) 1776 /* popcntd: PowerPC 2.06 specification */ 1777 static void gen_popcntd(DisasContext *ctx) 1778 { 1779 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1780 } 1781 #endif 1782 1783 /* prtyw: PowerPC 2.05 specification */ 1784 static void gen_prtyw(DisasContext *ctx) 1785 { 1786 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1787 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1788 TCGv t0 = tcg_temp_new(); 1789 tcg_gen_shri_tl(t0, rs, 16); 1790 tcg_gen_xor_tl(ra, rs, t0); 1791 tcg_gen_shri_tl(t0, ra, 8); 1792 tcg_gen_xor_tl(ra, ra, t0); 1793 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1794 tcg_temp_free(t0); 1795 } 1796 1797 #if defined(TARGET_PPC64) 1798 /* prtyd: PowerPC 2.05 specification */ 1799 static void gen_prtyd(DisasContext *ctx) 1800 { 1801 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1802 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1803 TCGv t0 = tcg_temp_new(); 1804 tcg_gen_shri_tl(t0, rs, 32); 1805 tcg_gen_xor_tl(ra, rs, t0); 1806 tcg_gen_shri_tl(t0, ra, 16); 1807 tcg_gen_xor_tl(ra, ra, t0); 1808 tcg_gen_shri_tl(t0, ra, 8); 1809 tcg_gen_xor_tl(ra, ra, t0); 1810 tcg_gen_andi_tl(ra, ra, 1); 1811 tcg_temp_free(t0); 1812 } 1813 #endif 1814 1815 #if defined(TARGET_PPC64) 1816 /* bpermd */ 1817 static void gen_bpermd(DisasContext *ctx) 1818 { 1819 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1820 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1821 } 1822 #endif 1823 1824 #if defined(TARGET_PPC64) 1825 /* extsw & extsw. */ 1826 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1827 1828 /* cntlzd */ 1829 static void gen_cntlzd(DisasContext *ctx) 1830 { 1831 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1832 if (unlikely(Rc(ctx->opcode) != 0)) { 1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1834 } 1835 } 1836 1837 /* cnttzd */ 1838 static void gen_cnttzd(DisasContext *ctx) 1839 { 1840 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1841 if (unlikely(Rc(ctx->opcode) != 0)) { 1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1843 } 1844 } 1845 1846 /* darn */ 1847 static void gen_darn(DisasContext *ctx) 1848 { 1849 int l = L(ctx->opcode); 1850 1851 if (l > 2) { 1852 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1853 } else { 1854 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1855 gen_io_start(); 1856 } 1857 if (l == 0) { 1858 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1859 } else { 1860 /* Return 64-bit random for both CRN and RRN */ 1861 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1862 } 1863 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1864 gen_stop_exception(ctx); 1865 } 1866 } 1867 } 1868 #endif 1869 1870 /*** Integer rotate ***/ 1871 1872 /* rlwimi & rlwimi. */ 1873 static void gen_rlwimi(DisasContext *ctx) 1874 { 1875 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1876 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1877 uint32_t sh = SH(ctx->opcode); 1878 uint32_t mb = MB(ctx->opcode); 1879 uint32_t me = ME(ctx->opcode); 1880 1881 if (sh == (31 - me) && mb <= me) { 1882 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1883 } else { 1884 target_ulong mask; 1885 bool mask_in_32b = true; 1886 TCGv t1; 1887 1888 #if defined(TARGET_PPC64) 1889 mb += 32; 1890 me += 32; 1891 #endif 1892 mask = MASK(mb, me); 1893 1894 #if defined(TARGET_PPC64) 1895 if (mask > 0xffffffffu) { 1896 mask_in_32b = false; 1897 } 1898 #endif 1899 t1 = tcg_temp_new(); 1900 if (mask_in_32b) { 1901 TCGv_i32 t0 = tcg_temp_new_i32(); 1902 tcg_gen_trunc_tl_i32(t0, t_rs); 1903 tcg_gen_rotli_i32(t0, t0, sh); 1904 tcg_gen_extu_i32_tl(t1, t0); 1905 tcg_temp_free_i32(t0); 1906 } else { 1907 #if defined(TARGET_PPC64) 1908 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1909 tcg_gen_rotli_i64(t1, t1, sh); 1910 #else 1911 g_assert_not_reached(); 1912 #endif 1913 } 1914 1915 tcg_gen_andi_tl(t1, t1, mask); 1916 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1917 tcg_gen_or_tl(t_ra, t_ra, t1); 1918 tcg_temp_free(t1); 1919 } 1920 if (unlikely(Rc(ctx->opcode) != 0)) { 1921 gen_set_Rc0(ctx, t_ra); 1922 } 1923 } 1924 1925 /* rlwinm & rlwinm. */ 1926 static void gen_rlwinm(DisasContext *ctx) 1927 { 1928 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1929 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1930 int sh = SH(ctx->opcode); 1931 int mb = MB(ctx->opcode); 1932 int me = ME(ctx->opcode); 1933 int len = me - mb + 1; 1934 int rsh = (32 - sh) & 31; 1935 1936 if (sh != 0 && len > 0 && me == (31 - sh)) { 1937 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1938 } else if (me == 31 && rsh + len <= 32) { 1939 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1940 } else { 1941 target_ulong mask; 1942 bool mask_in_32b = true; 1943 #if defined(TARGET_PPC64) 1944 mb += 32; 1945 me += 32; 1946 #endif 1947 mask = MASK(mb, me); 1948 #if defined(TARGET_PPC64) 1949 if (mask > 0xffffffffu) { 1950 mask_in_32b = false; 1951 } 1952 #endif 1953 if (mask_in_32b) { 1954 if (sh == 0) { 1955 tcg_gen_andi_tl(t_ra, t_rs, mask); 1956 } else { 1957 TCGv_i32 t0 = tcg_temp_new_i32(); 1958 tcg_gen_trunc_tl_i32(t0, t_rs); 1959 tcg_gen_rotli_i32(t0, t0, sh); 1960 tcg_gen_andi_i32(t0, t0, mask); 1961 tcg_gen_extu_i32_tl(t_ra, t0); 1962 tcg_temp_free_i32(t0); 1963 } 1964 } else { 1965 #if defined(TARGET_PPC64) 1966 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1967 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1968 tcg_gen_andi_i64(t_ra, t_ra, mask); 1969 #else 1970 g_assert_not_reached(); 1971 #endif 1972 } 1973 } 1974 if (unlikely(Rc(ctx->opcode) != 0)) { 1975 gen_set_Rc0(ctx, t_ra); 1976 } 1977 } 1978 1979 /* rlwnm & rlwnm. */ 1980 static void gen_rlwnm(DisasContext *ctx) 1981 { 1982 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1983 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1984 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1985 uint32_t mb = MB(ctx->opcode); 1986 uint32_t me = ME(ctx->opcode); 1987 target_ulong mask; 1988 bool mask_in_32b = true; 1989 1990 #if defined(TARGET_PPC64) 1991 mb += 32; 1992 me += 32; 1993 #endif 1994 mask = MASK(mb, me); 1995 1996 #if defined(TARGET_PPC64) 1997 if (mask > 0xffffffffu) { 1998 mask_in_32b = false; 1999 } 2000 #endif 2001 if (mask_in_32b) { 2002 TCGv_i32 t0 = tcg_temp_new_i32(); 2003 TCGv_i32 t1 = tcg_temp_new_i32(); 2004 tcg_gen_trunc_tl_i32(t0, t_rb); 2005 tcg_gen_trunc_tl_i32(t1, t_rs); 2006 tcg_gen_andi_i32(t0, t0, 0x1f); 2007 tcg_gen_rotl_i32(t1, t1, t0); 2008 tcg_gen_extu_i32_tl(t_ra, t1); 2009 tcg_temp_free_i32(t0); 2010 tcg_temp_free_i32(t1); 2011 } else { 2012 #if defined(TARGET_PPC64) 2013 TCGv_i64 t0 = tcg_temp_new_i64(); 2014 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2015 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2016 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2017 tcg_temp_free_i64(t0); 2018 #else 2019 g_assert_not_reached(); 2020 #endif 2021 } 2022 2023 tcg_gen_andi_tl(t_ra, t_ra, mask); 2024 2025 if (unlikely(Rc(ctx->opcode) != 0)) { 2026 gen_set_Rc0(ctx, t_ra); 2027 } 2028 } 2029 2030 #if defined(TARGET_PPC64) 2031 #define GEN_PPC64_R2(name, opc1, opc2) \ 2032 static void glue(gen_, name##0)(DisasContext *ctx) \ 2033 { \ 2034 gen_##name(ctx, 0); \ 2035 } \ 2036 \ 2037 static void glue(gen_, name##1)(DisasContext *ctx) \ 2038 { \ 2039 gen_##name(ctx, 1); \ 2040 } 2041 #define GEN_PPC64_R4(name, opc1, opc2) \ 2042 static void glue(gen_, name##0)(DisasContext *ctx) \ 2043 { \ 2044 gen_##name(ctx, 0, 0); \ 2045 } \ 2046 \ 2047 static void glue(gen_, name##1)(DisasContext *ctx) \ 2048 { \ 2049 gen_##name(ctx, 0, 1); \ 2050 } \ 2051 \ 2052 static void glue(gen_, name##2)(DisasContext *ctx) \ 2053 { \ 2054 gen_##name(ctx, 1, 0); \ 2055 } \ 2056 \ 2057 static void glue(gen_, name##3)(DisasContext *ctx) \ 2058 { \ 2059 gen_##name(ctx, 1, 1); \ 2060 } 2061 2062 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2063 { 2064 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2065 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2066 int len = me - mb + 1; 2067 int rsh = (64 - sh) & 63; 2068 2069 if (sh != 0 && len > 0 && me == (63 - sh)) { 2070 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2071 } else if (me == 63 && rsh + len <= 64) { 2072 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2073 } else { 2074 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2075 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2076 } 2077 if (unlikely(Rc(ctx->opcode) != 0)) { 2078 gen_set_Rc0(ctx, t_ra); 2079 } 2080 } 2081 2082 /* rldicl - rldicl. */ 2083 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2084 { 2085 uint32_t sh, mb; 2086 2087 sh = SH(ctx->opcode) | (shn << 5); 2088 mb = MB(ctx->opcode) | (mbn << 5); 2089 gen_rldinm(ctx, mb, 63, sh); 2090 } 2091 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2092 2093 /* rldicr - rldicr. */ 2094 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2095 { 2096 uint32_t sh, me; 2097 2098 sh = SH(ctx->opcode) | (shn << 5); 2099 me = MB(ctx->opcode) | (men << 5); 2100 gen_rldinm(ctx, 0, me, sh); 2101 } 2102 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2103 2104 /* rldic - rldic. */ 2105 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2106 { 2107 uint32_t sh, mb; 2108 2109 sh = SH(ctx->opcode) | (shn << 5); 2110 mb = MB(ctx->opcode) | (mbn << 5); 2111 gen_rldinm(ctx, mb, 63 - sh, sh); 2112 } 2113 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2114 2115 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2116 { 2117 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2118 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2119 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2120 TCGv t0; 2121 2122 t0 = tcg_temp_new(); 2123 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2124 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2125 tcg_temp_free(t0); 2126 2127 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2128 if (unlikely(Rc(ctx->opcode) != 0)) { 2129 gen_set_Rc0(ctx, t_ra); 2130 } 2131 } 2132 2133 /* rldcl - rldcl. */ 2134 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2135 { 2136 uint32_t mb; 2137 2138 mb = MB(ctx->opcode) | (mbn << 5); 2139 gen_rldnm(ctx, mb, 63); 2140 } 2141 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2142 2143 /* rldcr - rldcr. */ 2144 static inline void gen_rldcr(DisasContext *ctx, int men) 2145 { 2146 uint32_t me; 2147 2148 me = MB(ctx->opcode) | (men << 5); 2149 gen_rldnm(ctx, 0, me); 2150 } 2151 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2152 2153 /* rldimi - rldimi. */ 2154 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2155 { 2156 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2157 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2158 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2159 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2160 uint32_t me = 63 - sh; 2161 2162 if (mb <= me) { 2163 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2164 } else { 2165 target_ulong mask = MASK(mb, me); 2166 TCGv t1 = tcg_temp_new(); 2167 2168 tcg_gen_rotli_tl(t1, t_rs, sh); 2169 tcg_gen_andi_tl(t1, t1, mask); 2170 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2171 tcg_gen_or_tl(t_ra, t_ra, t1); 2172 tcg_temp_free(t1); 2173 } 2174 if (unlikely(Rc(ctx->opcode) != 0)) { 2175 gen_set_Rc0(ctx, t_ra); 2176 } 2177 } 2178 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2179 #endif 2180 2181 /*** Integer shift ***/ 2182 2183 /* slw & slw. */ 2184 static void gen_slw(DisasContext *ctx) 2185 { 2186 TCGv t0, t1; 2187 2188 t0 = tcg_temp_new(); 2189 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2190 #if defined(TARGET_PPC64) 2191 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2192 tcg_gen_sari_tl(t0, t0, 0x3f); 2193 #else 2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2195 tcg_gen_sari_tl(t0, t0, 0x1f); 2196 #endif 2197 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2198 t1 = tcg_temp_new(); 2199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2200 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2201 tcg_temp_free(t1); 2202 tcg_temp_free(t0); 2203 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2204 if (unlikely(Rc(ctx->opcode) != 0)) { 2205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2206 } 2207 } 2208 2209 /* sraw & sraw. */ 2210 static void gen_sraw(DisasContext *ctx) 2211 { 2212 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2213 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2214 if (unlikely(Rc(ctx->opcode) != 0)) { 2215 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2216 } 2217 } 2218 2219 /* srawi & srawi. */ 2220 static void gen_srawi(DisasContext *ctx) 2221 { 2222 int sh = SH(ctx->opcode); 2223 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2224 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2225 if (sh == 0) { 2226 tcg_gen_ext32s_tl(dst, src); 2227 tcg_gen_movi_tl(cpu_ca, 0); 2228 if (is_isa300(ctx)) { 2229 tcg_gen_movi_tl(cpu_ca32, 0); 2230 } 2231 } else { 2232 TCGv t0; 2233 tcg_gen_ext32s_tl(dst, src); 2234 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2235 t0 = tcg_temp_new(); 2236 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2237 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2238 tcg_temp_free(t0); 2239 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2240 if (is_isa300(ctx)) { 2241 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2242 } 2243 tcg_gen_sari_tl(dst, dst, sh); 2244 } 2245 if (unlikely(Rc(ctx->opcode) != 0)) { 2246 gen_set_Rc0(ctx, dst); 2247 } 2248 } 2249 2250 /* srw & srw. */ 2251 static void gen_srw(DisasContext *ctx) 2252 { 2253 TCGv t0, t1; 2254 2255 t0 = tcg_temp_new(); 2256 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2257 #if defined(TARGET_PPC64) 2258 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2259 tcg_gen_sari_tl(t0, t0, 0x3f); 2260 #else 2261 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2262 tcg_gen_sari_tl(t0, t0, 0x1f); 2263 #endif 2264 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2265 tcg_gen_ext32u_tl(t0, t0); 2266 t1 = tcg_temp_new(); 2267 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2268 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2269 tcg_temp_free(t1); 2270 tcg_temp_free(t0); 2271 if (unlikely(Rc(ctx->opcode) != 0)) { 2272 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2273 } 2274 } 2275 2276 #if defined(TARGET_PPC64) 2277 /* sld & sld. */ 2278 static void gen_sld(DisasContext *ctx) 2279 { 2280 TCGv t0, t1; 2281 2282 t0 = tcg_temp_new(); 2283 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2284 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2285 tcg_gen_sari_tl(t0, t0, 0x3f); 2286 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2287 t1 = tcg_temp_new(); 2288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2289 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2290 tcg_temp_free(t1); 2291 tcg_temp_free(t0); 2292 if (unlikely(Rc(ctx->opcode) != 0)) { 2293 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2294 } 2295 } 2296 2297 /* srad & srad. */ 2298 static void gen_srad(DisasContext *ctx) 2299 { 2300 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2301 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2302 if (unlikely(Rc(ctx->opcode) != 0)) { 2303 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2304 } 2305 } 2306 /* sradi & sradi. */ 2307 static inline void gen_sradi(DisasContext *ctx, int n) 2308 { 2309 int sh = SH(ctx->opcode) + (n << 5); 2310 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2311 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2312 if (sh == 0) { 2313 tcg_gen_mov_tl(dst, src); 2314 tcg_gen_movi_tl(cpu_ca, 0); 2315 if (is_isa300(ctx)) { 2316 tcg_gen_movi_tl(cpu_ca32, 0); 2317 } 2318 } else { 2319 TCGv t0; 2320 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2321 t0 = tcg_temp_new(); 2322 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2323 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2324 tcg_temp_free(t0); 2325 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2326 if (is_isa300(ctx)) { 2327 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2328 } 2329 tcg_gen_sari_tl(dst, src, sh); 2330 } 2331 if (unlikely(Rc(ctx->opcode) != 0)) { 2332 gen_set_Rc0(ctx, dst); 2333 } 2334 } 2335 2336 static void gen_sradi0(DisasContext *ctx) 2337 { 2338 gen_sradi(ctx, 0); 2339 } 2340 2341 static void gen_sradi1(DisasContext *ctx) 2342 { 2343 gen_sradi(ctx, 1); 2344 } 2345 2346 /* extswsli & extswsli. */ 2347 static inline void gen_extswsli(DisasContext *ctx, int n) 2348 { 2349 int sh = SH(ctx->opcode) + (n << 5); 2350 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2351 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2352 2353 tcg_gen_ext32s_tl(dst, src); 2354 tcg_gen_shli_tl(dst, dst, sh); 2355 if (unlikely(Rc(ctx->opcode) != 0)) { 2356 gen_set_Rc0(ctx, dst); 2357 } 2358 } 2359 2360 static void gen_extswsli0(DisasContext *ctx) 2361 { 2362 gen_extswsli(ctx, 0); 2363 } 2364 2365 static void gen_extswsli1(DisasContext *ctx) 2366 { 2367 gen_extswsli(ctx, 1); 2368 } 2369 2370 /* srd & srd. */ 2371 static void gen_srd(DisasContext *ctx) 2372 { 2373 TCGv t0, t1; 2374 2375 t0 = tcg_temp_new(); 2376 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2377 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2378 tcg_gen_sari_tl(t0, t0, 0x3f); 2379 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2380 t1 = tcg_temp_new(); 2381 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2382 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2383 tcg_temp_free(t1); 2384 tcg_temp_free(t0); 2385 if (unlikely(Rc(ctx->opcode) != 0)) { 2386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2387 } 2388 } 2389 #endif 2390 2391 /*** Addressing modes ***/ 2392 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2393 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2394 target_long maskl) 2395 { 2396 target_long simm = SIMM(ctx->opcode); 2397 2398 simm &= ~maskl; 2399 if (rA(ctx->opcode) == 0) { 2400 if (NARROW_MODE(ctx)) { 2401 simm = (uint32_t)simm; 2402 } 2403 tcg_gen_movi_tl(EA, simm); 2404 } else if (likely(simm != 0)) { 2405 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2406 if (NARROW_MODE(ctx)) { 2407 tcg_gen_ext32u_tl(EA, EA); 2408 } 2409 } else { 2410 if (NARROW_MODE(ctx)) { 2411 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2412 } else { 2413 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2414 } 2415 } 2416 } 2417 2418 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2419 { 2420 if (rA(ctx->opcode) == 0) { 2421 if (NARROW_MODE(ctx)) { 2422 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2423 } else { 2424 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2425 } 2426 } else { 2427 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2428 if (NARROW_MODE(ctx)) { 2429 tcg_gen_ext32u_tl(EA, EA); 2430 } 2431 } 2432 } 2433 2434 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2435 { 2436 if (rA(ctx->opcode) == 0) { 2437 tcg_gen_movi_tl(EA, 0); 2438 } else if (NARROW_MODE(ctx)) { 2439 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2440 } else { 2441 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2442 } 2443 } 2444 2445 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2446 target_long val) 2447 { 2448 tcg_gen_addi_tl(ret, arg1, val); 2449 if (NARROW_MODE(ctx)) { 2450 tcg_gen_ext32u_tl(ret, ret); 2451 } 2452 } 2453 2454 static inline void gen_align_no_le(DisasContext *ctx) 2455 { 2456 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2457 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2458 } 2459 2460 /*** Integer load ***/ 2461 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2462 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2463 2464 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2465 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2466 TCGv val, \ 2467 TCGv addr) \ 2468 { \ 2469 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2470 } 2471 2472 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2473 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2474 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2475 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2476 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2477 2478 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2479 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2480 2481 #define GEN_QEMU_LOAD_64(ldop, op) \ 2482 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2483 TCGv_i64 val, \ 2484 TCGv addr) \ 2485 { \ 2486 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2487 } 2488 2489 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2490 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2491 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2492 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2493 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2494 2495 #if defined(TARGET_PPC64) 2496 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2497 #endif 2498 2499 #define GEN_QEMU_STORE_TL(stop, op) \ 2500 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2501 TCGv val, \ 2502 TCGv addr) \ 2503 { \ 2504 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2505 } 2506 2507 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2508 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2509 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2510 2511 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2512 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2513 2514 #define GEN_QEMU_STORE_64(stop, op) \ 2515 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2516 TCGv_i64 val, \ 2517 TCGv addr) \ 2518 { \ 2519 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2520 } 2521 2522 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2523 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2524 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2525 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2526 2527 #if defined(TARGET_PPC64) 2528 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2529 #endif 2530 2531 #define GEN_LD(name, ldop, opc, type) \ 2532 static void glue(gen_, name)(DisasContext *ctx) \ 2533 { \ 2534 TCGv EA; \ 2535 gen_set_access_type(ctx, ACCESS_INT); \ 2536 EA = tcg_temp_new(); \ 2537 gen_addr_imm_index(ctx, EA, 0); \ 2538 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2539 tcg_temp_free(EA); \ 2540 } 2541 2542 #define GEN_LDU(name, ldop, opc, type) \ 2543 static void glue(gen_, name##u)(DisasContext *ctx) \ 2544 { \ 2545 TCGv EA; \ 2546 if (unlikely(rA(ctx->opcode) == 0 || \ 2547 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2548 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2549 return; \ 2550 } \ 2551 gen_set_access_type(ctx, ACCESS_INT); \ 2552 EA = tcg_temp_new(); \ 2553 if (type == PPC_64B) \ 2554 gen_addr_imm_index(ctx, EA, 0x03); \ 2555 else \ 2556 gen_addr_imm_index(ctx, EA, 0); \ 2557 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2558 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2559 tcg_temp_free(EA); \ 2560 } 2561 2562 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2563 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2564 { \ 2565 TCGv EA; \ 2566 if (unlikely(rA(ctx->opcode) == 0 || \ 2567 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2568 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2569 return; \ 2570 } \ 2571 gen_set_access_type(ctx, ACCESS_INT); \ 2572 EA = tcg_temp_new(); \ 2573 gen_addr_reg_index(ctx, EA); \ 2574 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2575 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2576 tcg_temp_free(EA); \ 2577 } 2578 2579 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2580 static void glue(gen_, name##x)(DisasContext *ctx) \ 2581 { \ 2582 TCGv EA; \ 2583 chk; \ 2584 gen_set_access_type(ctx, ACCESS_INT); \ 2585 EA = tcg_temp_new(); \ 2586 gen_addr_reg_index(ctx, EA); \ 2587 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2588 tcg_temp_free(EA); \ 2589 } 2590 2591 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2592 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2593 2594 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2595 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2596 2597 #define GEN_LDS(name, ldop, op, type) \ 2598 GEN_LD(name, ldop, op | 0x20, type); \ 2599 GEN_LDU(name, ldop, op | 0x21, type); \ 2600 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2601 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2602 2603 /* lbz lbzu lbzux lbzx */ 2604 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2605 /* lha lhau lhaux lhax */ 2606 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2607 /* lhz lhzu lhzux lhzx */ 2608 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2609 /* lwz lwzu lwzux lwzx */ 2610 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2611 2612 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2613 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2614 { \ 2615 TCGv EA; \ 2616 CHK_SV; \ 2617 gen_set_access_type(ctx, ACCESS_INT); \ 2618 EA = tcg_temp_new(); \ 2619 gen_addr_reg_index(ctx, EA); \ 2620 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2621 tcg_temp_free(EA); \ 2622 } 2623 2624 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2625 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2626 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2627 #if defined(TARGET_PPC64) 2628 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 2629 #endif 2630 2631 #if defined(TARGET_PPC64) 2632 /* lwaux */ 2633 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2634 /* lwax */ 2635 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2636 /* ldux */ 2637 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2638 /* ldx */ 2639 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2640 2641 /* CI load/store variants */ 2642 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2643 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2644 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2645 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2646 2647 static void gen_ld(DisasContext *ctx) 2648 { 2649 TCGv EA; 2650 if (Rc(ctx->opcode)) { 2651 if (unlikely(rA(ctx->opcode) == 0 || 2652 rA(ctx->opcode) == rD(ctx->opcode))) { 2653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2654 return; 2655 } 2656 } 2657 gen_set_access_type(ctx, ACCESS_INT); 2658 EA = tcg_temp_new(); 2659 gen_addr_imm_index(ctx, EA, 0x03); 2660 if (ctx->opcode & 0x02) { 2661 /* lwa (lwau is undefined) */ 2662 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2663 } else { 2664 /* ld - ldu */ 2665 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2666 } 2667 if (Rc(ctx->opcode)) { 2668 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2669 } 2670 tcg_temp_free(EA); 2671 } 2672 2673 /* lq */ 2674 static void gen_lq(DisasContext *ctx) 2675 { 2676 int ra, rd; 2677 TCGv EA, hi, lo; 2678 2679 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2680 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2681 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2682 2683 if (!legal_in_user_mode && ctx->pr) { 2684 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2685 return; 2686 } 2687 2688 if (!le_is_supported && ctx->le_mode) { 2689 gen_align_no_le(ctx); 2690 return; 2691 } 2692 ra = rA(ctx->opcode); 2693 rd = rD(ctx->opcode); 2694 if (unlikely((rd & 1) || rd == ra)) { 2695 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2696 return; 2697 } 2698 2699 gen_set_access_type(ctx, ACCESS_INT); 2700 EA = tcg_temp_new(); 2701 gen_addr_imm_index(ctx, EA, 0x0F); 2702 2703 /* Note that the low part is always in RD+1, even in LE mode. */ 2704 lo = cpu_gpr[rd + 1]; 2705 hi = cpu_gpr[rd]; 2706 2707 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2708 if (HAVE_ATOMIC128) { 2709 TCGv_i32 oi = tcg_temp_new_i32(); 2710 if (ctx->le_mode) { 2711 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2712 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2713 } else { 2714 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2715 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 2716 } 2717 tcg_temp_free_i32(oi); 2718 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2719 } else { 2720 /* Restart with exclusive lock. */ 2721 gen_helper_exit_atomic(cpu_env); 2722 ctx->base.is_jmp = DISAS_NORETURN; 2723 } 2724 } else if (ctx->le_mode) { 2725 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2726 gen_addr_add(ctx, EA, EA, 8); 2727 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2728 } else { 2729 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2730 gen_addr_add(ctx, EA, EA, 8); 2731 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2732 } 2733 tcg_temp_free(EA); 2734 } 2735 #endif 2736 2737 /*** Integer store ***/ 2738 #define GEN_ST(name, stop, opc, type) \ 2739 static void glue(gen_, name)(DisasContext *ctx) \ 2740 { \ 2741 TCGv EA; \ 2742 gen_set_access_type(ctx, ACCESS_INT); \ 2743 EA = tcg_temp_new(); \ 2744 gen_addr_imm_index(ctx, EA, 0); \ 2745 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2746 tcg_temp_free(EA); \ 2747 } 2748 2749 #define GEN_STU(name, stop, opc, type) \ 2750 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2751 { \ 2752 TCGv EA; \ 2753 if (unlikely(rA(ctx->opcode) == 0)) { \ 2754 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2755 return; \ 2756 } \ 2757 gen_set_access_type(ctx, ACCESS_INT); \ 2758 EA = tcg_temp_new(); \ 2759 if (type == PPC_64B) \ 2760 gen_addr_imm_index(ctx, EA, 0x03); \ 2761 else \ 2762 gen_addr_imm_index(ctx, EA, 0); \ 2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2764 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2765 tcg_temp_free(EA); \ 2766 } 2767 2768 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2769 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2770 { \ 2771 TCGv EA; \ 2772 if (unlikely(rA(ctx->opcode) == 0)) { \ 2773 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2774 return; \ 2775 } \ 2776 gen_set_access_type(ctx, ACCESS_INT); \ 2777 EA = tcg_temp_new(); \ 2778 gen_addr_reg_index(ctx, EA); \ 2779 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2781 tcg_temp_free(EA); \ 2782 } 2783 2784 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2785 static void glue(gen_, name##x)(DisasContext *ctx) \ 2786 { \ 2787 TCGv EA; \ 2788 chk; \ 2789 gen_set_access_type(ctx, ACCESS_INT); \ 2790 EA = tcg_temp_new(); \ 2791 gen_addr_reg_index(ctx, EA); \ 2792 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2793 tcg_temp_free(EA); \ 2794 } 2795 #define GEN_STX(name, stop, opc2, opc3, type) \ 2796 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2797 2798 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2799 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2800 2801 #define GEN_STS(name, stop, op, type) \ 2802 GEN_ST(name, stop, op | 0x20, type); \ 2803 GEN_STU(name, stop, op | 0x21, type); \ 2804 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2805 GEN_STX(name, stop, 0x17, op | 0x00, type) 2806 2807 /* stb stbu stbux stbx */ 2808 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2809 /* sth sthu sthux sthx */ 2810 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2811 /* stw stwu stwux stwx */ 2812 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2813 2814 #define GEN_STEPX(name, stop, opc2, opc3) \ 2815 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2816 { \ 2817 TCGv EA; \ 2818 CHK_SV; \ 2819 gen_set_access_type(ctx, ACCESS_INT); \ 2820 EA = tcg_temp_new(); \ 2821 gen_addr_reg_index(ctx, EA); \ 2822 tcg_gen_qemu_st_tl( \ 2823 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2824 tcg_temp_free(EA); \ 2825 } 2826 2827 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2828 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2829 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2830 #if defined(TARGET_PPC64) 2831 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 2832 #endif 2833 2834 #if defined(TARGET_PPC64) 2835 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2836 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2837 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2838 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2839 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2840 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2841 2842 static void gen_std(DisasContext *ctx) 2843 { 2844 int rs; 2845 TCGv EA; 2846 2847 rs = rS(ctx->opcode); 2848 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2849 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2850 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2851 TCGv hi, lo; 2852 2853 if (!(ctx->insns_flags & PPC_64BX)) { 2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2855 } 2856 2857 if (!legal_in_user_mode && ctx->pr) { 2858 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2859 return; 2860 } 2861 2862 if (!le_is_supported && ctx->le_mode) { 2863 gen_align_no_le(ctx); 2864 return; 2865 } 2866 2867 if (unlikely(rs & 1)) { 2868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2869 return; 2870 } 2871 gen_set_access_type(ctx, ACCESS_INT); 2872 EA = tcg_temp_new(); 2873 gen_addr_imm_index(ctx, EA, 0x03); 2874 2875 /* Note that the low part is always in RS+1, even in LE mode. */ 2876 lo = cpu_gpr[rs + 1]; 2877 hi = cpu_gpr[rs]; 2878 2879 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2880 if (HAVE_ATOMIC128) { 2881 TCGv_i32 oi = tcg_temp_new_i32(); 2882 if (ctx->le_mode) { 2883 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2884 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2885 } else { 2886 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2887 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2888 } 2889 tcg_temp_free_i32(oi); 2890 } else { 2891 /* Restart with exclusive lock. */ 2892 gen_helper_exit_atomic(cpu_env); 2893 ctx->base.is_jmp = DISAS_NORETURN; 2894 } 2895 } else if (ctx->le_mode) { 2896 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2897 gen_addr_add(ctx, EA, EA, 8); 2898 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2899 } else { 2900 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2901 gen_addr_add(ctx, EA, EA, 8); 2902 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2903 } 2904 tcg_temp_free(EA); 2905 } else { 2906 /* std / stdu */ 2907 if (Rc(ctx->opcode)) { 2908 if (unlikely(rA(ctx->opcode) == 0)) { 2909 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2910 return; 2911 } 2912 } 2913 gen_set_access_type(ctx, ACCESS_INT); 2914 EA = tcg_temp_new(); 2915 gen_addr_imm_index(ctx, EA, 0x03); 2916 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2917 if (Rc(ctx->opcode)) { 2918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2919 } 2920 tcg_temp_free(EA); 2921 } 2922 } 2923 #endif 2924 /*** Integer load and store with byte reverse ***/ 2925 2926 /* lhbrx */ 2927 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2928 2929 /* lwbrx */ 2930 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2931 2932 #if defined(TARGET_PPC64) 2933 /* ldbrx */ 2934 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2935 /* stdbrx */ 2936 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2937 #endif /* TARGET_PPC64 */ 2938 2939 /* sthbrx */ 2940 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2941 /* stwbrx */ 2942 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2943 2944 /*** Integer load and store multiple ***/ 2945 2946 /* lmw */ 2947 static void gen_lmw(DisasContext *ctx) 2948 { 2949 TCGv t0; 2950 TCGv_i32 t1; 2951 2952 if (ctx->le_mode) { 2953 gen_align_no_le(ctx); 2954 return; 2955 } 2956 gen_set_access_type(ctx, ACCESS_INT); 2957 t0 = tcg_temp_new(); 2958 t1 = tcg_const_i32(rD(ctx->opcode)); 2959 gen_addr_imm_index(ctx, t0, 0); 2960 gen_helper_lmw(cpu_env, t0, t1); 2961 tcg_temp_free(t0); 2962 tcg_temp_free_i32(t1); 2963 } 2964 2965 /* stmw */ 2966 static void gen_stmw(DisasContext *ctx) 2967 { 2968 TCGv t0; 2969 TCGv_i32 t1; 2970 2971 if (ctx->le_mode) { 2972 gen_align_no_le(ctx); 2973 return; 2974 } 2975 gen_set_access_type(ctx, ACCESS_INT); 2976 t0 = tcg_temp_new(); 2977 t1 = tcg_const_i32(rS(ctx->opcode)); 2978 gen_addr_imm_index(ctx, t0, 0); 2979 gen_helper_stmw(cpu_env, t0, t1); 2980 tcg_temp_free(t0); 2981 tcg_temp_free_i32(t1); 2982 } 2983 2984 /*** Integer load and store strings ***/ 2985 2986 /* lswi */ 2987 /* 2988 * PowerPC32 specification says we must generate an exception if rA is 2989 * in the range of registers to be loaded. In an other hand, IBM says 2990 * this is valid, but rA won't be loaded. For now, I'll follow the 2991 * spec... 2992 */ 2993 static void gen_lswi(DisasContext *ctx) 2994 { 2995 TCGv t0; 2996 TCGv_i32 t1, t2; 2997 int nb = NB(ctx->opcode); 2998 int start = rD(ctx->opcode); 2999 int ra = rA(ctx->opcode); 3000 int nr; 3001 3002 if (ctx->le_mode) { 3003 gen_align_no_le(ctx); 3004 return; 3005 } 3006 if (nb == 0) { 3007 nb = 32; 3008 } 3009 nr = DIV_ROUND_UP(nb, 4); 3010 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3011 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3012 return; 3013 } 3014 gen_set_access_type(ctx, ACCESS_INT); 3015 t0 = tcg_temp_new(); 3016 gen_addr_register(ctx, t0); 3017 t1 = tcg_const_i32(nb); 3018 t2 = tcg_const_i32(start); 3019 gen_helper_lsw(cpu_env, t0, t1, t2); 3020 tcg_temp_free(t0); 3021 tcg_temp_free_i32(t1); 3022 tcg_temp_free_i32(t2); 3023 } 3024 3025 /* lswx */ 3026 static void gen_lswx(DisasContext *ctx) 3027 { 3028 TCGv t0; 3029 TCGv_i32 t1, t2, t3; 3030 3031 if (ctx->le_mode) { 3032 gen_align_no_le(ctx); 3033 return; 3034 } 3035 gen_set_access_type(ctx, ACCESS_INT); 3036 t0 = tcg_temp_new(); 3037 gen_addr_reg_index(ctx, t0); 3038 t1 = tcg_const_i32(rD(ctx->opcode)); 3039 t2 = tcg_const_i32(rA(ctx->opcode)); 3040 t3 = tcg_const_i32(rB(ctx->opcode)); 3041 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3042 tcg_temp_free(t0); 3043 tcg_temp_free_i32(t1); 3044 tcg_temp_free_i32(t2); 3045 tcg_temp_free_i32(t3); 3046 } 3047 3048 /* stswi */ 3049 static void gen_stswi(DisasContext *ctx) 3050 { 3051 TCGv t0; 3052 TCGv_i32 t1, t2; 3053 int nb = NB(ctx->opcode); 3054 3055 if (ctx->le_mode) { 3056 gen_align_no_le(ctx); 3057 return; 3058 } 3059 gen_set_access_type(ctx, ACCESS_INT); 3060 t0 = tcg_temp_new(); 3061 gen_addr_register(ctx, t0); 3062 if (nb == 0) { 3063 nb = 32; 3064 } 3065 t1 = tcg_const_i32(nb); 3066 t2 = tcg_const_i32(rS(ctx->opcode)); 3067 gen_helper_stsw(cpu_env, t0, t1, t2); 3068 tcg_temp_free(t0); 3069 tcg_temp_free_i32(t1); 3070 tcg_temp_free_i32(t2); 3071 } 3072 3073 /* stswx */ 3074 static void gen_stswx(DisasContext *ctx) 3075 { 3076 TCGv t0; 3077 TCGv_i32 t1, t2; 3078 3079 if (ctx->le_mode) { 3080 gen_align_no_le(ctx); 3081 return; 3082 } 3083 gen_set_access_type(ctx, ACCESS_INT); 3084 t0 = tcg_temp_new(); 3085 gen_addr_reg_index(ctx, t0); 3086 t1 = tcg_temp_new_i32(); 3087 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3088 tcg_gen_andi_i32(t1, t1, 0x7F); 3089 t2 = tcg_const_i32(rS(ctx->opcode)); 3090 gen_helper_stsw(cpu_env, t0, t1, t2); 3091 tcg_temp_free(t0); 3092 tcg_temp_free_i32(t1); 3093 tcg_temp_free_i32(t2); 3094 } 3095 3096 /*** Memory synchronisation ***/ 3097 /* eieio */ 3098 static void gen_eieio(DisasContext *ctx) 3099 { 3100 TCGBar bar = TCG_MO_LD_ST; 3101 3102 /* 3103 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3104 * tell the CPU it is a store-forwarding barrier. 3105 */ 3106 if (ctx->opcode & 0x2000000) { 3107 /* 3108 * ISA says that "Reserved fields in instructions are ignored 3109 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3110 * as this is not an instruction software should be using, 3111 * complain to the user. 3112 */ 3113 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3114 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3115 TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3116 } else { 3117 bar = TCG_MO_ST_LD; 3118 } 3119 } 3120 3121 tcg_gen_mb(bar | TCG_BAR_SC); 3122 } 3123 3124 #if !defined(CONFIG_USER_ONLY) 3125 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3126 { 3127 TCGv_i32 t; 3128 TCGLabel *l; 3129 3130 if (!ctx->lazy_tlb_flush) { 3131 return; 3132 } 3133 l = gen_new_label(); 3134 t = tcg_temp_new_i32(); 3135 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3136 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3137 if (global) { 3138 gen_helper_check_tlb_flush_global(cpu_env); 3139 } else { 3140 gen_helper_check_tlb_flush_local(cpu_env); 3141 } 3142 gen_set_label(l); 3143 tcg_temp_free_i32(t); 3144 } 3145 #else 3146 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3147 #endif 3148 3149 /* isync */ 3150 static void gen_isync(DisasContext *ctx) 3151 { 3152 /* 3153 * We need to check for a pending TLB flush. This can only happen in 3154 * kernel mode however so check MSR_PR 3155 */ 3156 if (!ctx->pr) { 3157 gen_check_tlb_flush(ctx, false); 3158 } 3159 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3160 gen_stop_exception(ctx); 3161 } 3162 3163 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3164 3165 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3166 { 3167 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3168 TCGv t0 = tcg_temp_new(); 3169 3170 gen_set_access_type(ctx, ACCESS_RES); 3171 gen_addr_reg_index(ctx, t0); 3172 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3173 tcg_gen_mov_tl(cpu_reserve, t0); 3174 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3175 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 3176 tcg_temp_free(t0); 3177 } 3178 3179 #define LARX(name, memop) \ 3180 static void gen_##name(DisasContext *ctx) \ 3181 { \ 3182 gen_load_locked(ctx, memop); \ 3183 } 3184 3185 /* lwarx */ 3186 LARX(lbarx, DEF_MEMOP(MO_UB)) 3187 LARX(lharx, DEF_MEMOP(MO_UW)) 3188 LARX(lwarx, DEF_MEMOP(MO_UL)) 3189 3190 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3191 TCGv EA, TCGCond cond, int addend) 3192 { 3193 TCGv t = tcg_temp_new(); 3194 TCGv t2 = tcg_temp_new(); 3195 TCGv u = tcg_temp_new(); 3196 3197 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3198 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3199 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3200 tcg_gen_addi_tl(u, t, addend); 3201 3202 /* E.g. for fetch and increment bounded... */ 3203 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3204 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3205 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3206 3207 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3208 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3209 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3210 3211 tcg_temp_free(t); 3212 tcg_temp_free(t2); 3213 tcg_temp_free(u); 3214 } 3215 3216 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3217 { 3218 uint32_t gpr_FC = FC(ctx->opcode); 3219 TCGv EA = tcg_temp_new(); 3220 int rt = rD(ctx->opcode); 3221 bool need_serial; 3222 TCGv src, dst; 3223 3224 gen_addr_register(ctx, EA); 3225 dst = cpu_gpr[rt]; 3226 src = cpu_gpr[(rt + 1) & 31]; 3227 3228 need_serial = false; 3229 memop |= MO_ALIGN; 3230 switch (gpr_FC) { 3231 case 0: /* Fetch and add */ 3232 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3233 break; 3234 case 1: /* Fetch and xor */ 3235 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3236 break; 3237 case 2: /* Fetch and or */ 3238 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3239 break; 3240 case 3: /* Fetch and 'and' */ 3241 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3242 break; 3243 case 4: /* Fetch and max unsigned */ 3244 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3245 break; 3246 case 5: /* Fetch and max signed */ 3247 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3248 break; 3249 case 6: /* Fetch and min unsigned */ 3250 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3251 break; 3252 case 7: /* Fetch and min signed */ 3253 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3254 break; 3255 case 8: /* Swap */ 3256 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3257 break; 3258 3259 case 16: /* Compare and swap not equal */ 3260 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3261 need_serial = true; 3262 } else { 3263 TCGv t0 = tcg_temp_new(); 3264 TCGv t1 = tcg_temp_new(); 3265 3266 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3267 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3268 tcg_gen_mov_tl(t1, src); 3269 } else { 3270 tcg_gen_ext32u_tl(t1, src); 3271 } 3272 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3273 cpu_gpr[(rt + 2) & 31], t0); 3274 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3275 tcg_gen_mov_tl(dst, t0); 3276 3277 tcg_temp_free(t0); 3278 tcg_temp_free(t1); 3279 } 3280 break; 3281 3282 case 24: /* Fetch and increment bounded */ 3283 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3284 need_serial = true; 3285 } else { 3286 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3287 } 3288 break; 3289 case 25: /* Fetch and increment equal */ 3290 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3291 need_serial = true; 3292 } else { 3293 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3294 } 3295 break; 3296 case 28: /* Fetch and decrement bounded */ 3297 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3298 need_serial = true; 3299 } else { 3300 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3301 } 3302 break; 3303 3304 default: 3305 /* invoke data storage error handler */ 3306 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3307 } 3308 tcg_temp_free(EA); 3309 3310 if (need_serial) { 3311 /* Restart with exclusive lock. */ 3312 gen_helper_exit_atomic(cpu_env); 3313 ctx->base.is_jmp = DISAS_NORETURN; 3314 } 3315 } 3316 3317 static void gen_lwat(DisasContext *ctx) 3318 { 3319 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3320 } 3321 3322 #ifdef TARGET_PPC64 3323 static void gen_ldat(DisasContext *ctx) 3324 { 3325 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 3326 } 3327 #endif 3328 3329 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3330 { 3331 uint32_t gpr_FC = FC(ctx->opcode); 3332 TCGv EA = tcg_temp_new(); 3333 TCGv src, discard; 3334 3335 gen_addr_register(ctx, EA); 3336 src = cpu_gpr[rD(ctx->opcode)]; 3337 discard = tcg_temp_new(); 3338 3339 memop |= MO_ALIGN; 3340 switch (gpr_FC) { 3341 case 0: /* add and Store */ 3342 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3343 break; 3344 case 1: /* xor and Store */ 3345 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3346 break; 3347 case 2: /* Or and Store */ 3348 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3349 break; 3350 case 3: /* 'and' and Store */ 3351 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3352 break; 3353 case 4: /* Store max unsigned */ 3354 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3355 break; 3356 case 5: /* Store max signed */ 3357 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3358 break; 3359 case 6: /* Store min unsigned */ 3360 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3361 break; 3362 case 7: /* Store min signed */ 3363 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3364 break; 3365 case 24: /* Store twin */ 3366 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3367 /* Restart with exclusive lock. */ 3368 gen_helper_exit_atomic(cpu_env); 3369 ctx->base.is_jmp = DISAS_NORETURN; 3370 } else { 3371 TCGv t = tcg_temp_new(); 3372 TCGv t2 = tcg_temp_new(); 3373 TCGv s = tcg_temp_new(); 3374 TCGv s2 = tcg_temp_new(); 3375 TCGv ea_plus_s = tcg_temp_new(); 3376 3377 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3378 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3379 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3380 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3381 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3382 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3383 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3384 3385 tcg_temp_free(ea_plus_s); 3386 tcg_temp_free(s2); 3387 tcg_temp_free(s); 3388 tcg_temp_free(t2); 3389 tcg_temp_free(t); 3390 } 3391 break; 3392 default: 3393 /* invoke data storage error handler */ 3394 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3395 } 3396 tcg_temp_free(discard); 3397 tcg_temp_free(EA); 3398 } 3399 3400 static void gen_stwat(DisasContext *ctx) 3401 { 3402 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3403 } 3404 3405 #ifdef TARGET_PPC64 3406 static void gen_stdat(DisasContext *ctx) 3407 { 3408 gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 3409 } 3410 #endif 3411 3412 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3413 { 3414 TCGLabel *l1 = gen_new_label(); 3415 TCGLabel *l2 = gen_new_label(); 3416 TCGv t0 = tcg_temp_new(); 3417 int reg = rS(ctx->opcode); 3418 3419 gen_set_access_type(ctx, ACCESS_RES); 3420 gen_addr_reg_index(ctx, t0); 3421 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3422 tcg_temp_free(t0); 3423 3424 t0 = tcg_temp_new(); 3425 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3426 cpu_gpr[reg], ctx->mem_idx, 3427 DEF_MEMOP(memop) | MO_ALIGN); 3428 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3429 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3430 tcg_gen_or_tl(t0, t0, cpu_so); 3431 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3432 tcg_temp_free(t0); 3433 tcg_gen_br(l2); 3434 3435 gen_set_label(l1); 3436 3437 /* 3438 * Address mismatch implies failure. But we still need to provide 3439 * the memory barrier semantics of the instruction. 3440 */ 3441 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3442 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3443 3444 gen_set_label(l2); 3445 tcg_gen_movi_tl(cpu_reserve, -1); 3446 } 3447 3448 #define STCX(name, memop) \ 3449 static void gen_##name(DisasContext *ctx) \ 3450 { \ 3451 gen_conditional_store(ctx, memop); \ 3452 } 3453 3454 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3455 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3456 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3457 3458 #if defined(TARGET_PPC64) 3459 /* ldarx */ 3460 LARX(ldarx, DEF_MEMOP(MO_Q)) 3461 /* stdcx. */ 3462 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3463 3464 /* lqarx */ 3465 static void gen_lqarx(DisasContext *ctx) 3466 { 3467 int rd = rD(ctx->opcode); 3468 TCGv EA, hi, lo; 3469 3470 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3471 (rd == rB(ctx->opcode)))) { 3472 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3473 return; 3474 } 3475 3476 gen_set_access_type(ctx, ACCESS_RES); 3477 EA = tcg_temp_new(); 3478 gen_addr_reg_index(ctx, EA); 3479 3480 /* Note that the low part is always in RD+1, even in LE mode. */ 3481 lo = cpu_gpr[rd + 1]; 3482 hi = cpu_gpr[rd]; 3483 3484 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3485 if (HAVE_ATOMIC128) { 3486 TCGv_i32 oi = tcg_temp_new_i32(); 3487 if (ctx->le_mode) { 3488 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 3489 ctx->mem_idx)); 3490 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3491 } else { 3492 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 3493 ctx->mem_idx)); 3494 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3495 } 3496 tcg_temp_free_i32(oi); 3497 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3498 } else { 3499 /* Restart with exclusive lock. */ 3500 gen_helper_exit_atomic(cpu_env); 3501 ctx->base.is_jmp = DISAS_NORETURN; 3502 tcg_temp_free(EA); 3503 return; 3504 } 3505 } else if (ctx->le_mode) { 3506 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3507 tcg_gen_mov_tl(cpu_reserve, EA); 3508 gen_addr_add(ctx, EA, EA, 8); 3509 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3510 } else { 3511 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 3512 tcg_gen_mov_tl(cpu_reserve, EA); 3513 gen_addr_add(ctx, EA, EA, 8); 3514 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3515 } 3516 tcg_temp_free(EA); 3517 3518 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3519 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3520 } 3521 3522 /* stqcx. */ 3523 static void gen_stqcx_(DisasContext *ctx) 3524 { 3525 int rs = rS(ctx->opcode); 3526 TCGv EA, hi, lo; 3527 3528 if (unlikely(rs & 1)) { 3529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3530 return; 3531 } 3532 3533 gen_set_access_type(ctx, ACCESS_RES); 3534 EA = tcg_temp_new(); 3535 gen_addr_reg_index(ctx, EA); 3536 3537 /* Note that the low part is always in RS+1, even in LE mode. */ 3538 lo = cpu_gpr[rs + 1]; 3539 hi = cpu_gpr[rs]; 3540 3541 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3542 if (HAVE_CMPXCHG128) { 3543 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 3544 if (ctx->le_mode) { 3545 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3546 EA, lo, hi, oi); 3547 } else { 3548 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3549 EA, lo, hi, oi); 3550 } 3551 tcg_temp_free_i32(oi); 3552 } else { 3553 /* Restart with exclusive lock. */ 3554 gen_helper_exit_atomic(cpu_env); 3555 ctx->base.is_jmp = DISAS_NORETURN; 3556 } 3557 tcg_temp_free(EA); 3558 } else { 3559 TCGLabel *lab_fail = gen_new_label(); 3560 TCGLabel *lab_over = gen_new_label(); 3561 TCGv_i64 t0 = tcg_temp_new_i64(); 3562 TCGv_i64 t1 = tcg_temp_new_i64(); 3563 3564 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 3565 tcg_temp_free(EA); 3566 3567 gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 3568 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3569 ? offsetof(CPUPPCState, reserve_val2) 3570 : offsetof(CPUPPCState, reserve_val))); 3571 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3572 3573 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3574 gen_qemu_ld64_i64(ctx, t0, t0); 3575 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3576 ? offsetof(CPUPPCState, reserve_val) 3577 : offsetof(CPUPPCState, reserve_val2))); 3578 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3579 3580 /* Success */ 3581 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 3582 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3583 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 3584 3585 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3586 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3587 tcg_gen_br(lab_over); 3588 3589 gen_set_label(lab_fail); 3590 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3591 3592 gen_set_label(lab_over); 3593 tcg_gen_movi_tl(cpu_reserve, -1); 3594 tcg_temp_free_i64(t0); 3595 tcg_temp_free_i64(t1); 3596 } 3597 } 3598 #endif /* defined(TARGET_PPC64) */ 3599 3600 /* sync */ 3601 static void gen_sync(DisasContext *ctx) 3602 { 3603 uint32_t l = (ctx->opcode >> 21) & 3; 3604 3605 /* 3606 * We may need to check for a pending TLB flush. 3607 * 3608 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3609 * 3610 * Additionally, this can only happen in kernel mode however so 3611 * check MSR_PR as well. 3612 */ 3613 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3614 gen_check_tlb_flush(ctx, true); 3615 } 3616 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3617 } 3618 3619 /* wait */ 3620 static void gen_wait(DisasContext *ctx) 3621 { 3622 TCGv_i32 t0 = tcg_const_i32(1); 3623 tcg_gen_st_i32(t0, cpu_env, 3624 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3625 tcg_temp_free_i32(t0); 3626 /* Stop translation, as the CPU is supposed to sleep from now */ 3627 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3628 } 3629 3630 #if defined(TARGET_PPC64) 3631 static void gen_doze(DisasContext *ctx) 3632 { 3633 #if defined(CONFIG_USER_ONLY) 3634 GEN_PRIV; 3635 #else 3636 TCGv_i32 t; 3637 3638 CHK_HV; 3639 t = tcg_const_i32(PPC_PM_DOZE); 3640 gen_helper_pminsn(cpu_env, t); 3641 tcg_temp_free_i32(t); 3642 /* Stop translation, as the CPU is supposed to sleep from now */ 3643 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3644 #endif /* defined(CONFIG_USER_ONLY) */ 3645 } 3646 3647 static void gen_nap(DisasContext *ctx) 3648 { 3649 #if defined(CONFIG_USER_ONLY) 3650 GEN_PRIV; 3651 #else 3652 TCGv_i32 t; 3653 3654 CHK_HV; 3655 t = tcg_const_i32(PPC_PM_NAP); 3656 gen_helper_pminsn(cpu_env, t); 3657 tcg_temp_free_i32(t); 3658 /* Stop translation, as the CPU is supposed to sleep from now */ 3659 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3660 #endif /* defined(CONFIG_USER_ONLY) */ 3661 } 3662 3663 static void gen_stop(DisasContext *ctx) 3664 { 3665 #if defined(CONFIG_USER_ONLY) 3666 GEN_PRIV; 3667 #else 3668 TCGv_i32 t; 3669 3670 CHK_HV; 3671 t = tcg_const_i32(PPC_PM_STOP); 3672 gen_helper_pminsn(cpu_env, t); 3673 tcg_temp_free_i32(t); 3674 /* Stop translation, as the CPU is supposed to sleep from now */ 3675 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3676 #endif /* defined(CONFIG_USER_ONLY) */ 3677 } 3678 3679 static void gen_sleep(DisasContext *ctx) 3680 { 3681 #if defined(CONFIG_USER_ONLY) 3682 GEN_PRIV; 3683 #else 3684 TCGv_i32 t; 3685 3686 CHK_HV; 3687 t = tcg_const_i32(PPC_PM_SLEEP); 3688 gen_helper_pminsn(cpu_env, t); 3689 tcg_temp_free_i32(t); 3690 /* Stop translation, as the CPU is supposed to sleep from now */ 3691 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3692 #endif /* defined(CONFIG_USER_ONLY) */ 3693 } 3694 3695 static void gen_rvwinkle(DisasContext *ctx) 3696 { 3697 #if defined(CONFIG_USER_ONLY) 3698 GEN_PRIV; 3699 #else 3700 TCGv_i32 t; 3701 3702 CHK_HV; 3703 t = tcg_const_i32(PPC_PM_RVWINKLE); 3704 gen_helper_pminsn(cpu_env, t); 3705 tcg_temp_free_i32(t); 3706 /* Stop translation, as the CPU is supposed to sleep from now */ 3707 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3708 #endif /* defined(CONFIG_USER_ONLY) */ 3709 } 3710 #endif /* #if defined(TARGET_PPC64) */ 3711 3712 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3713 { 3714 #if defined(TARGET_PPC64) 3715 if (ctx->has_cfar) { 3716 tcg_gen_movi_tl(cpu_cfar, nip); 3717 } 3718 #endif 3719 } 3720 3721 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3722 { 3723 if (unlikely(ctx->singlestep_enabled)) { 3724 return false; 3725 } 3726 3727 #ifndef CONFIG_USER_ONLY 3728 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3729 #else 3730 return true; 3731 #endif 3732 } 3733 3734 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3735 { 3736 int sse = ctx->singlestep_enabled; 3737 if (unlikely(sse)) { 3738 if (sse & GDBSTUB_SINGLE_STEP) { 3739 gen_debug_exception(ctx); 3740 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3741 uint32_t excp = gen_prep_dbgex(ctx); 3742 gen_exception(ctx, excp); 3743 } 3744 tcg_gen_exit_tb(NULL, 0); 3745 } else { 3746 tcg_gen_lookup_and_goto_ptr(); 3747 } 3748 } 3749 3750 /*** Branch ***/ 3751 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3752 { 3753 if (NARROW_MODE(ctx)) { 3754 dest = (uint32_t) dest; 3755 } 3756 if (use_goto_tb(ctx, dest)) { 3757 tcg_gen_goto_tb(n); 3758 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3759 tcg_gen_exit_tb(ctx->base.tb, n); 3760 } else { 3761 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3762 gen_lookup_and_goto_ptr(ctx); 3763 } 3764 } 3765 3766 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3767 { 3768 if (NARROW_MODE(ctx)) { 3769 nip = (uint32_t)nip; 3770 } 3771 tcg_gen_movi_tl(cpu_lr, nip); 3772 } 3773 3774 /* b ba bl bla */ 3775 static void gen_b(DisasContext *ctx) 3776 { 3777 target_ulong li, target; 3778 3779 ctx->exception = POWERPC_EXCP_BRANCH; 3780 /* sign extend LI */ 3781 li = LI(ctx->opcode); 3782 li = (li ^ 0x02000000) - 0x02000000; 3783 if (likely(AA(ctx->opcode) == 0)) { 3784 target = ctx->base.pc_next + li - 4; 3785 } else { 3786 target = li; 3787 } 3788 if (LK(ctx->opcode)) { 3789 gen_setlr(ctx, ctx->base.pc_next); 3790 } 3791 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3792 gen_goto_tb(ctx, 0, target); 3793 } 3794 3795 #define BCOND_IM 0 3796 #define BCOND_LR 1 3797 #define BCOND_CTR 2 3798 #define BCOND_TAR 3 3799 3800 static void gen_bcond(DisasContext *ctx, int type) 3801 { 3802 uint32_t bo = BO(ctx->opcode); 3803 TCGLabel *l1; 3804 TCGv target; 3805 ctx->exception = POWERPC_EXCP_BRANCH; 3806 3807 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3808 target = tcg_temp_local_new(); 3809 if (type == BCOND_CTR) { 3810 tcg_gen_mov_tl(target, cpu_ctr); 3811 } else if (type == BCOND_TAR) { 3812 gen_load_spr(target, SPR_TAR); 3813 } else { 3814 tcg_gen_mov_tl(target, cpu_lr); 3815 } 3816 } else { 3817 target = NULL; 3818 } 3819 if (LK(ctx->opcode)) { 3820 gen_setlr(ctx, ctx->base.pc_next); 3821 } 3822 l1 = gen_new_label(); 3823 if ((bo & 0x4) == 0) { 3824 /* Decrement and test CTR */ 3825 TCGv temp = tcg_temp_new(); 3826 3827 if (type == BCOND_CTR) { 3828 /* 3829 * All ISAs up to v3 describe this form of bcctr as invalid but 3830 * some processors, ie. 64-bit server processors compliant with 3831 * arch 2.x, do implement a "test and decrement" logic instead, 3832 * as described in their respective UMs. This logic involves CTR 3833 * to act as both the branch target and a counter, which makes 3834 * it basically useless and thus never used in real code. 3835 * 3836 * This form was hence chosen to trigger extra micro-architectural 3837 * side-effect on real HW needed for the Spectre v2 workaround. 3838 * It is up to guests that implement such workaround, ie. linux, to 3839 * use this form in a way it just triggers the side-effect without 3840 * doing anything else harmful. 3841 */ 3842 if (unlikely(!is_book3s_arch2x(ctx))) { 3843 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3844 tcg_temp_free(temp); 3845 tcg_temp_free(target); 3846 return; 3847 } 3848 3849 if (NARROW_MODE(ctx)) { 3850 tcg_gen_ext32u_tl(temp, cpu_ctr); 3851 } else { 3852 tcg_gen_mov_tl(temp, cpu_ctr); 3853 } 3854 if (bo & 0x2) { 3855 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3856 } else { 3857 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3858 } 3859 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3860 } else { 3861 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3862 if (NARROW_MODE(ctx)) { 3863 tcg_gen_ext32u_tl(temp, cpu_ctr); 3864 } else { 3865 tcg_gen_mov_tl(temp, cpu_ctr); 3866 } 3867 if (bo & 0x2) { 3868 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3869 } else { 3870 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3871 } 3872 } 3873 tcg_temp_free(temp); 3874 } 3875 if ((bo & 0x10) == 0) { 3876 /* Test CR */ 3877 uint32_t bi = BI(ctx->opcode); 3878 uint32_t mask = 0x08 >> (bi & 0x03); 3879 TCGv_i32 temp = tcg_temp_new_i32(); 3880 3881 if (bo & 0x8) { 3882 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3883 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3884 } else { 3885 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3886 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3887 } 3888 tcg_temp_free_i32(temp); 3889 } 3890 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3891 if (type == BCOND_IM) { 3892 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3893 if (likely(AA(ctx->opcode) == 0)) { 3894 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3895 } else { 3896 gen_goto_tb(ctx, 0, li); 3897 } 3898 } else { 3899 if (NARROW_MODE(ctx)) { 3900 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3901 } else { 3902 tcg_gen_andi_tl(cpu_nip, target, ~3); 3903 } 3904 gen_lookup_and_goto_ptr(ctx); 3905 tcg_temp_free(target); 3906 } 3907 if ((bo & 0x14) != 0x14) { 3908 /* fallthrough case */ 3909 gen_set_label(l1); 3910 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3911 } 3912 } 3913 3914 static void gen_bc(DisasContext *ctx) 3915 { 3916 gen_bcond(ctx, BCOND_IM); 3917 } 3918 3919 static void gen_bcctr(DisasContext *ctx) 3920 { 3921 gen_bcond(ctx, BCOND_CTR); 3922 } 3923 3924 static void gen_bclr(DisasContext *ctx) 3925 { 3926 gen_bcond(ctx, BCOND_LR); 3927 } 3928 3929 static void gen_bctar(DisasContext *ctx) 3930 { 3931 gen_bcond(ctx, BCOND_TAR); 3932 } 3933 3934 /*** Condition register logical ***/ 3935 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3936 static void glue(gen_, name)(DisasContext *ctx) \ 3937 { \ 3938 uint8_t bitmask; \ 3939 int sh; \ 3940 TCGv_i32 t0, t1; \ 3941 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3942 t0 = tcg_temp_new_i32(); \ 3943 if (sh > 0) \ 3944 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3945 else if (sh < 0) \ 3946 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3947 else \ 3948 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3949 t1 = tcg_temp_new_i32(); \ 3950 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3951 if (sh > 0) \ 3952 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3953 else if (sh < 0) \ 3954 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3955 else \ 3956 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3957 tcg_op(t0, t0, t1); \ 3958 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3959 tcg_gen_andi_i32(t0, t0, bitmask); \ 3960 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3961 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3962 tcg_temp_free_i32(t0); \ 3963 tcg_temp_free_i32(t1); \ 3964 } 3965 3966 /* crand */ 3967 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3968 /* crandc */ 3969 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3970 /* creqv */ 3971 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3972 /* crnand */ 3973 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3974 /* crnor */ 3975 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3976 /* cror */ 3977 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3978 /* crorc */ 3979 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3980 /* crxor */ 3981 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3982 3983 /* mcrf */ 3984 static void gen_mcrf(DisasContext *ctx) 3985 { 3986 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3987 } 3988 3989 /*** System linkage ***/ 3990 3991 /* rfi (supervisor only) */ 3992 static void gen_rfi(DisasContext *ctx) 3993 { 3994 #if defined(CONFIG_USER_ONLY) 3995 GEN_PRIV; 3996 #else 3997 /* 3998 * This instruction doesn't exist anymore on 64-bit server 3999 * processors compliant with arch 2.x 4000 */ 4001 if (is_book3s_arch2x(ctx)) { 4002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4003 return; 4004 } 4005 /* Restore CPU state */ 4006 CHK_SV; 4007 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4008 gen_io_start(); 4009 } 4010 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4011 gen_helper_rfi(cpu_env); 4012 gen_sync_exception(ctx); 4013 #endif 4014 } 4015 4016 #if defined(TARGET_PPC64) 4017 static void gen_rfid(DisasContext *ctx) 4018 { 4019 #if defined(CONFIG_USER_ONLY) 4020 GEN_PRIV; 4021 #else 4022 /* Restore CPU state */ 4023 CHK_SV; 4024 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4025 gen_io_start(); 4026 } 4027 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4028 gen_helper_rfid(cpu_env); 4029 gen_sync_exception(ctx); 4030 #endif 4031 } 4032 4033 static void gen_hrfid(DisasContext *ctx) 4034 { 4035 #if defined(CONFIG_USER_ONLY) 4036 GEN_PRIV; 4037 #else 4038 /* Restore CPU state */ 4039 CHK_HV; 4040 gen_helper_hrfid(cpu_env); 4041 gen_sync_exception(ctx); 4042 #endif 4043 } 4044 #endif 4045 4046 /* sc */ 4047 #if defined(CONFIG_USER_ONLY) 4048 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4049 #else 4050 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4051 #endif 4052 static void gen_sc(DisasContext *ctx) 4053 { 4054 uint32_t lev; 4055 4056 lev = (ctx->opcode >> 5) & 0x7F; 4057 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4058 } 4059 4060 /*** Trap ***/ 4061 4062 /* Check for unconditional traps (always or never) */ 4063 static bool check_unconditional_trap(DisasContext *ctx) 4064 { 4065 /* Trap never */ 4066 if (TO(ctx->opcode) == 0) { 4067 return true; 4068 } 4069 /* Trap always */ 4070 if (TO(ctx->opcode) == 31) { 4071 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4072 return true; 4073 } 4074 return false; 4075 } 4076 4077 /* tw */ 4078 static void gen_tw(DisasContext *ctx) 4079 { 4080 TCGv_i32 t0; 4081 4082 if (check_unconditional_trap(ctx)) { 4083 return; 4084 } 4085 t0 = tcg_const_i32(TO(ctx->opcode)); 4086 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4087 t0); 4088 tcg_temp_free_i32(t0); 4089 } 4090 4091 /* twi */ 4092 static void gen_twi(DisasContext *ctx) 4093 { 4094 TCGv t0; 4095 TCGv_i32 t1; 4096 4097 if (check_unconditional_trap(ctx)) { 4098 return; 4099 } 4100 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4101 t1 = tcg_const_i32(TO(ctx->opcode)); 4102 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4103 tcg_temp_free(t0); 4104 tcg_temp_free_i32(t1); 4105 } 4106 4107 #if defined(TARGET_PPC64) 4108 /* td */ 4109 static void gen_td(DisasContext *ctx) 4110 { 4111 TCGv_i32 t0; 4112 4113 if (check_unconditional_trap(ctx)) { 4114 return; 4115 } 4116 t0 = tcg_const_i32(TO(ctx->opcode)); 4117 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4118 t0); 4119 tcg_temp_free_i32(t0); 4120 } 4121 4122 /* tdi */ 4123 static void gen_tdi(DisasContext *ctx) 4124 { 4125 TCGv t0; 4126 TCGv_i32 t1; 4127 4128 if (check_unconditional_trap(ctx)) { 4129 return; 4130 } 4131 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4132 t1 = tcg_const_i32(TO(ctx->opcode)); 4133 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4134 tcg_temp_free(t0); 4135 tcg_temp_free_i32(t1); 4136 } 4137 #endif 4138 4139 /*** Processor control ***/ 4140 4141 static void gen_read_xer(DisasContext *ctx, TCGv dst) 4142 { 4143 TCGv t0 = tcg_temp_new(); 4144 TCGv t1 = tcg_temp_new(); 4145 TCGv t2 = tcg_temp_new(); 4146 tcg_gen_mov_tl(dst, cpu_xer); 4147 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4148 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4149 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4150 tcg_gen_or_tl(t0, t0, t1); 4151 tcg_gen_or_tl(dst, dst, t2); 4152 tcg_gen_or_tl(dst, dst, t0); 4153 if (is_isa300(ctx)) { 4154 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4155 tcg_gen_or_tl(dst, dst, t0); 4156 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4157 tcg_gen_or_tl(dst, dst, t0); 4158 } 4159 tcg_temp_free(t0); 4160 tcg_temp_free(t1); 4161 tcg_temp_free(t2); 4162 } 4163 4164 static void gen_write_xer(TCGv src) 4165 { 4166 /* Write all flags, while reading back check for isa300 */ 4167 tcg_gen_andi_tl(cpu_xer, src, 4168 ~((1u << XER_SO) | 4169 (1u << XER_OV) | (1u << XER_OV32) | 4170 (1u << XER_CA) | (1u << XER_CA32))); 4171 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4172 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 4173 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 4174 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 4175 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4176 } 4177 4178 /* mcrxr */ 4179 static void gen_mcrxr(DisasContext *ctx) 4180 { 4181 TCGv_i32 t0 = tcg_temp_new_i32(); 4182 TCGv_i32 t1 = tcg_temp_new_i32(); 4183 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4184 4185 tcg_gen_trunc_tl_i32(t0, cpu_so); 4186 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4187 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4188 tcg_gen_shli_i32(t0, t0, 3); 4189 tcg_gen_shli_i32(t1, t1, 2); 4190 tcg_gen_shli_i32(dst, dst, 1); 4191 tcg_gen_or_i32(dst, dst, t0); 4192 tcg_gen_or_i32(dst, dst, t1); 4193 tcg_temp_free_i32(t0); 4194 tcg_temp_free_i32(t1); 4195 4196 tcg_gen_movi_tl(cpu_so, 0); 4197 tcg_gen_movi_tl(cpu_ov, 0); 4198 tcg_gen_movi_tl(cpu_ca, 0); 4199 } 4200 4201 #ifdef TARGET_PPC64 4202 /* mcrxrx */ 4203 static void gen_mcrxrx(DisasContext *ctx) 4204 { 4205 TCGv t0 = tcg_temp_new(); 4206 TCGv t1 = tcg_temp_new(); 4207 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4208 4209 /* copy OV and OV32 */ 4210 tcg_gen_shli_tl(t0, cpu_ov, 1); 4211 tcg_gen_or_tl(t0, t0, cpu_ov32); 4212 tcg_gen_shli_tl(t0, t0, 2); 4213 /* copy CA and CA32 */ 4214 tcg_gen_shli_tl(t1, cpu_ca, 1); 4215 tcg_gen_or_tl(t1, t1, cpu_ca32); 4216 tcg_gen_or_tl(t0, t0, t1); 4217 tcg_gen_trunc_tl_i32(dst, t0); 4218 tcg_temp_free(t0); 4219 tcg_temp_free(t1); 4220 } 4221 #endif 4222 4223 /* mfcr mfocrf */ 4224 static void gen_mfcr(DisasContext *ctx) 4225 { 4226 uint32_t crm, crn; 4227 4228 if (likely(ctx->opcode & 0x00100000)) { 4229 crm = CRM(ctx->opcode); 4230 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4231 crn = ctz32(crm); 4232 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4233 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4234 cpu_gpr[rD(ctx->opcode)], crn * 4); 4235 } 4236 } else { 4237 TCGv_i32 t0 = tcg_temp_new_i32(); 4238 tcg_gen_mov_i32(t0, cpu_crf[0]); 4239 tcg_gen_shli_i32(t0, t0, 4); 4240 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4241 tcg_gen_shli_i32(t0, t0, 4); 4242 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4243 tcg_gen_shli_i32(t0, t0, 4); 4244 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4245 tcg_gen_shli_i32(t0, t0, 4); 4246 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4247 tcg_gen_shli_i32(t0, t0, 4); 4248 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4249 tcg_gen_shli_i32(t0, t0, 4); 4250 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4251 tcg_gen_shli_i32(t0, t0, 4); 4252 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4253 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4254 tcg_temp_free_i32(t0); 4255 } 4256 } 4257 4258 /* mfmsr */ 4259 static void gen_mfmsr(DisasContext *ctx) 4260 { 4261 CHK_SV; 4262 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4263 } 4264 4265 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4266 { 4267 #if 0 4268 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4269 printf("ERROR: try to access SPR %d !\n", sprn); 4270 #endif 4271 } 4272 #define SPR_NOACCESS (&spr_noaccess) 4273 4274 /* mfspr */ 4275 static inline void gen_op_mfspr(DisasContext *ctx) 4276 { 4277 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4278 uint32_t sprn = SPR(ctx->opcode); 4279 4280 #if defined(CONFIG_USER_ONLY) 4281 read_cb = ctx->spr_cb[sprn].uea_read; 4282 #else 4283 if (ctx->pr) { 4284 read_cb = ctx->spr_cb[sprn].uea_read; 4285 } else if (ctx->hv) { 4286 read_cb = ctx->spr_cb[sprn].hea_read; 4287 } else { 4288 read_cb = ctx->spr_cb[sprn].oea_read; 4289 } 4290 #endif 4291 if (likely(read_cb != NULL)) { 4292 if (likely(read_cb != SPR_NOACCESS)) { 4293 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4294 } else { 4295 /* Privilege exception */ 4296 /* 4297 * This is a hack to avoid warnings when running Linux: 4298 * this OS breaks the PowerPC virtualisation model, 4299 * allowing userland application to read the PVR 4300 */ 4301 if (sprn != SPR_PVR) { 4302 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4303 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4304 ctx->base.pc_next - 4); 4305 } 4306 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4307 } 4308 } else { 4309 /* ISA 2.07 defines these as no-ops */ 4310 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4311 (sprn >= 808 && sprn <= 811)) { 4312 /* This is a nop */ 4313 return; 4314 } 4315 /* Not defined */ 4316 qemu_log_mask(LOG_GUEST_ERROR, 4317 "Trying to read invalid spr %d (0x%03x) at " 4318 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4319 4320 /* 4321 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4322 * generate a priv, a hv emu or a no-op 4323 */ 4324 if (sprn & 0x10) { 4325 if (ctx->pr) { 4326 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4327 } 4328 } else { 4329 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4330 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4331 } 4332 } 4333 } 4334 } 4335 4336 static void gen_mfspr(DisasContext *ctx) 4337 { 4338 gen_op_mfspr(ctx); 4339 } 4340 4341 /* mftb */ 4342 static void gen_mftb(DisasContext *ctx) 4343 { 4344 gen_op_mfspr(ctx); 4345 } 4346 4347 /* mtcrf mtocrf*/ 4348 static void gen_mtcrf(DisasContext *ctx) 4349 { 4350 uint32_t crm, crn; 4351 4352 crm = CRM(ctx->opcode); 4353 if (likely((ctx->opcode & 0x00100000))) { 4354 if (crm && ((crm & (crm - 1)) == 0)) { 4355 TCGv_i32 temp = tcg_temp_new_i32(); 4356 crn = ctz32(crm); 4357 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4358 tcg_gen_shri_i32(temp, temp, crn * 4); 4359 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4360 tcg_temp_free_i32(temp); 4361 } 4362 } else { 4363 TCGv_i32 temp = tcg_temp_new_i32(); 4364 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4365 for (crn = 0 ; crn < 8 ; crn++) { 4366 if (crm & (1 << crn)) { 4367 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4368 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4369 } 4370 } 4371 tcg_temp_free_i32(temp); 4372 } 4373 } 4374 4375 /* mtmsr */ 4376 #if defined(TARGET_PPC64) 4377 static void gen_mtmsrd(DisasContext *ctx) 4378 { 4379 CHK_SV; 4380 4381 #if !defined(CONFIG_USER_ONLY) 4382 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4383 gen_io_start(); 4384 } 4385 if (ctx->opcode & 0x00010000) { 4386 /* L=1 form only updates EE and RI */ 4387 TCGv t0 = tcg_temp_new(); 4388 TCGv t1 = tcg_temp_new(); 4389 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4390 (1 << MSR_RI) | (1 << MSR_EE)); 4391 tcg_gen_andi_tl(t1, cpu_msr, 4392 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4393 tcg_gen_or_tl(t1, t1, t0); 4394 4395 gen_helper_store_msr(cpu_env, t1); 4396 tcg_temp_free(t0); 4397 tcg_temp_free(t1); 4398 4399 } else { 4400 /* 4401 * XXX: we need to update nip before the store if we enter 4402 * power saving mode, we will exit the loop directly from 4403 * ppc_store_msr 4404 */ 4405 gen_update_nip(ctx, ctx->base.pc_next); 4406 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4407 } 4408 /* Must stop the translation as machine state (may have) changed */ 4409 gen_stop_exception(ctx); 4410 #endif /* !defined(CONFIG_USER_ONLY) */ 4411 } 4412 #endif /* defined(TARGET_PPC64) */ 4413 4414 static void gen_mtmsr(DisasContext *ctx) 4415 { 4416 CHK_SV; 4417 4418 #if !defined(CONFIG_USER_ONLY) 4419 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4420 gen_io_start(); 4421 } 4422 if (ctx->opcode & 0x00010000) { 4423 /* L=1 form only updates EE and RI */ 4424 TCGv t0 = tcg_temp_new(); 4425 TCGv t1 = tcg_temp_new(); 4426 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4427 (1 << MSR_RI) | (1 << MSR_EE)); 4428 tcg_gen_andi_tl(t1, cpu_msr, 4429 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4430 tcg_gen_or_tl(t1, t1, t0); 4431 4432 gen_helper_store_msr(cpu_env, t1); 4433 tcg_temp_free(t0); 4434 tcg_temp_free(t1); 4435 4436 } else { 4437 TCGv msr = tcg_temp_new(); 4438 4439 /* 4440 * XXX: we need to update nip before the store if we enter 4441 * power saving mode, we will exit the loop directly from 4442 * ppc_store_msr 4443 */ 4444 gen_update_nip(ctx, ctx->base.pc_next); 4445 #if defined(TARGET_PPC64) 4446 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4447 #else 4448 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4449 #endif 4450 gen_helper_store_msr(cpu_env, msr); 4451 tcg_temp_free(msr); 4452 } 4453 /* Must stop the translation as machine state (may have) changed */ 4454 gen_stop_exception(ctx); 4455 #endif 4456 } 4457 4458 /* mtspr */ 4459 static void gen_mtspr(DisasContext *ctx) 4460 { 4461 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4462 uint32_t sprn = SPR(ctx->opcode); 4463 4464 #if defined(CONFIG_USER_ONLY) 4465 write_cb = ctx->spr_cb[sprn].uea_write; 4466 #else 4467 if (ctx->pr) { 4468 write_cb = ctx->spr_cb[sprn].uea_write; 4469 } else if (ctx->hv) { 4470 write_cb = ctx->spr_cb[sprn].hea_write; 4471 } else { 4472 write_cb = ctx->spr_cb[sprn].oea_write; 4473 } 4474 #endif 4475 if (likely(write_cb != NULL)) { 4476 if (likely(write_cb != SPR_NOACCESS)) { 4477 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4478 } else { 4479 /* Privilege exception */ 4480 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4481 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4482 ctx->base.pc_next - 4); 4483 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4484 } 4485 } else { 4486 /* ISA 2.07 defines these as no-ops */ 4487 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4488 (sprn >= 808 && sprn <= 811)) { 4489 /* This is a nop */ 4490 return; 4491 } 4492 4493 /* Not defined */ 4494 qemu_log_mask(LOG_GUEST_ERROR, 4495 "Trying to write invalid spr %d (0x%03x) at " 4496 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4497 4498 4499 /* 4500 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4501 * generate a priv, a hv emu or a no-op 4502 */ 4503 if (sprn & 0x10) { 4504 if (ctx->pr) { 4505 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4506 } 4507 } else { 4508 if (ctx->pr || sprn == 0) { 4509 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4510 } 4511 } 4512 } 4513 } 4514 4515 #if defined(TARGET_PPC64) 4516 /* setb */ 4517 static void gen_setb(DisasContext *ctx) 4518 { 4519 TCGv_i32 t0 = tcg_temp_new_i32(); 4520 TCGv_i32 t8 = tcg_temp_new_i32(); 4521 TCGv_i32 tm1 = tcg_temp_new_i32(); 4522 int crf = crfS(ctx->opcode); 4523 4524 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4525 tcg_gen_movi_i32(t8, 8); 4526 tcg_gen_movi_i32(tm1, -1); 4527 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4528 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4529 4530 tcg_temp_free_i32(t0); 4531 tcg_temp_free_i32(t8); 4532 tcg_temp_free_i32(tm1); 4533 } 4534 #endif 4535 4536 /*** Cache management ***/ 4537 4538 /* dcbf */ 4539 static void gen_dcbf(DisasContext *ctx) 4540 { 4541 /* XXX: specification says this is treated as a load by the MMU */ 4542 TCGv t0; 4543 gen_set_access_type(ctx, ACCESS_CACHE); 4544 t0 = tcg_temp_new(); 4545 gen_addr_reg_index(ctx, t0); 4546 gen_qemu_ld8u(ctx, t0, t0); 4547 tcg_temp_free(t0); 4548 } 4549 4550 /* dcbfep (external PID dcbf) */ 4551 static void gen_dcbfep(DisasContext *ctx) 4552 { 4553 /* XXX: specification says this is treated as a load by the MMU */ 4554 TCGv t0; 4555 CHK_SV; 4556 gen_set_access_type(ctx, ACCESS_CACHE); 4557 t0 = tcg_temp_new(); 4558 gen_addr_reg_index(ctx, t0); 4559 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4560 tcg_temp_free(t0); 4561 } 4562 4563 /* dcbi (Supervisor only) */ 4564 static void gen_dcbi(DisasContext *ctx) 4565 { 4566 #if defined(CONFIG_USER_ONLY) 4567 GEN_PRIV; 4568 #else 4569 TCGv EA, val; 4570 4571 CHK_SV; 4572 EA = tcg_temp_new(); 4573 gen_set_access_type(ctx, ACCESS_CACHE); 4574 gen_addr_reg_index(ctx, EA); 4575 val = tcg_temp_new(); 4576 /* XXX: specification says this should be treated as a store by the MMU */ 4577 gen_qemu_ld8u(ctx, val, EA); 4578 gen_qemu_st8(ctx, val, EA); 4579 tcg_temp_free(val); 4580 tcg_temp_free(EA); 4581 #endif /* defined(CONFIG_USER_ONLY) */ 4582 } 4583 4584 /* dcdst */ 4585 static void gen_dcbst(DisasContext *ctx) 4586 { 4587 /* XXX: specification say this is treated as a load by the MMU */ 4588 TCGv t0; 4589 gen_set_access_type(ctx, ACCESS_CACHE); 4590 t0 = tcg_temp_new(); 4591 gen_addr_reg_index(ctx, t0); 4592 gen_qemu_ld8u(ctx, t0, t0); 4593 tcg_temp_free(t0); 4594 } 4595 4596 /* dcbstep (dcbstep External PID version) */ 4597 static void gen_dcbstep(DisasContext *ctx) 4598 { 4599 /* XXX: specification say this is treated as a load by the MMU */ 4600 TCGv t0; 4601 gen_set_access_type(ctx, ACCESS_CACHE); 4602 t0 = tcg_temp_new(); 4603 gen_addr_reg_index(ctx, t0); 4604 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4605 tcg_temp_free(t0); 4606 } 4607 4608 /* dcbt */ 4609 static void gen_dcbt(DisasContext *ctx) 4610 { 4611 /* 4612 * interpreted as no-op 4613 * XXX: specification say this is treated as a load by the MMU but 4614 * does not generate any exception 4615 */ 4616 } 4617 4618 /* dcbtep */ 4619 static void gen_dcbtep(DisasContext *ctx) 4620 { 4621 /* 4622 * interpreted as no-op 4623 * XXX: specification say this is treated as a load by the MMU but 4624 * does not generate any exception 4625 */ 4626 } 4627 4628 /* dcbtst */ 4629 static void gen_dcbtst(DisasContext *ctx) 4630 { 4631 /* 4632 * interpreted as no-op 4633 * XXX: specification say this is treated as a load by the MMU but 4634 * does not generate any exception 4635 */ 4636 } 4637 4638 /* dcbtstep */ 4639 static void gen_dcbtstep(DisasContext *ctx) 4640 { 4641 /* 4642 * interpreted as no-op 4643 * XXX: specification say this is treated as a load by the MMU but 4644 * does not generate any exception 4645 */ 4646 } 4647 4648 /* dcbtls */ 4649 static void gen_dcbtls(DisasContext *ctx) 4650 { 4651 /* Always fails locking the cache */ 4652 TCGv t0 = tcg_temp_new(); 4653 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4654 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4655 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4656 tcg_temp_free(t0); 4657 } 4658 4659 /* dcbz */ 4660 static void gen_dcbz(DisasContext *ctx) 4661 { 4662 TCGv tcgv_addr; 4663 TCGv_i32 tcgv_op; 4664 4665 gen_set_access_type(ctx, ACCESS_CACHE); 4666 tcgv_addr = tcg_temp_new(); 4667 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4668 gen_addr_reg_index(ctx, tcgv_addr); 4669 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4670 tcg_temp_free(tcgv_addr); 4671 tcg_temp_free_i32(tcgv_op); 4672 } 4673 4674 /* dcbzep */ 4675 static void gen_dcbzep(DisasContext *ctx) 4676 { 4677 TCGv tcgv_addr; 4678 TCGv_i32 tcgv_op; 4679 4680 gen_set_access_type(ctx, ACCESS_CACHE); 4681 tcgv_addr = tcg_temp_new(); 4682 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4683 gen_addr_reg_index(ctx, tcgv_addr); 4684 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 4685 tcg_temp_free(tcgv_addr); 4686 tcg_temp_free_i32(tcgv_op); 4687 } 4688 4689 /* dst / dstt */ 4690 static void gen_dst(DisasContext *ctx) 4691 { 4692 if (rA(ctx->opcode) == 0) { 4693 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4694 } else { 4695 /* interpreted as no-op */ 4696 } 4697 } 4698 4699 /* dstst /dststt */ 4700 static void gen_dstst(DisasContext *ctx) 4701 { 4702 if (rA(ctx->opcode) == 0) { 4703 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4704 } else { 4705 /* interpreted as no-op */ 4706 } 4707 4708 } 4709 4710 /* dss / dssall */ 4711 static void gen_dss(DisasContext *ctx) 4712 { 4713 /* interpreted as no-op */ 4714 } 4715 4716 /* icbi */ 4717 static void gen_icbi(DisasContext *ctx) 4718 { 4719 TCGv t0; 4720 gen_set_access_type(ctx, ACCESS_CACHE); 4721 t0 = tcg_temp_new(); 4722 gen_addr_reg_index(ctx, t0); 4723 gen_helper_icbi(cpu_env, t0); 4724 tcg_temp_free(t0); 4725 } 4726 4727 /* icbiep */ 4728 static void gen_icbiep(DisasContext *ctx) 4729 { 4730 TCGv t0; 4731 gen_set_access_type(ctx, ACCESS_CACHE); 4732 t0 = tcg_temp_new(); 4733 gen_addr_reg_index(ctx, t0); 4734 gen_helper_icbiep(cpu_env, t0); 4735 tcg_temp_free(t0); 4736 } 4737 4738 /* Optional: */ 4739 /* dcba */ 4740 static void gen_dcba(DisasContext *ctx) 4741 { 4742 /* 4743 * interpreted as no-op 4744 * XXX: specification say this is treated as a store by the MMU 4745 * but does not generate any exception 4746 */ 4747 } 4748 4749 /*** Segment register manipulation ***/ 4750 /* Supervisor only: */ 4751 4752 /* mfsr */ 4753 static void gen_mfsr(DisasContext *ctx) 4754 { 4755 #if defined(CONFIG_USER_ONLY) 4756 GEN_PRIV; 4757 #else 4758 TCGv t0; 4759 4760 CHK_SV; 4761 t0 = tcg_const_tl(SR(ctx->opcode)); 4762 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4763 tcg_temp_free(t0); 4764 #endif /* defined(CONFIG_USER_ONLY) */ 4765 } 4766 4767 /* mfsrin */ 4768 static void gen_mfsrin(DisasContext *ctx) 4769 { 4770 #if defined(CONFIG_USER_ONLY) 4771 GEN_PRIV; 4772 #else 4773 TCGv t0; 4774 4775 CHK_SV; 4776 t0 = tcg_temp_new(); 4777 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4778 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4779 tcg_temp_free(t0); 4780 #endif /* defined(CONFIG_USER_ONLY) */ 4781 } 4782 4783 /* mtsr */ 4784 static void gen_mtsr(DisasContext *ctx) 4785 { 4786 #if defined(CONFIG_USER_ONLY) 4787 GEN_PRIV; 4788 #else 4789 TCGv t0; 4790 4791 CHK_SV; 4792 t0 = tcg_const_tl(SR(ctx->opcode)); 4793 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4794 tcg_temp_free(t0); 4795 #endif /* defined(CONFIG_USER_ONLY) */ 4796 } 4797 4798 /* mtsrin */ 4799 static void gen_mtsrin(DisasContext *ctx) 4800 { 4801 #if defined(CONFIG_USER_ONLY) 4802 GEN_PRIV; 4803 #else 4804 TCGv t0; 4805 CHK_SV; 4806 4807 t0 = tcg_temp_new(); 4808 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4809 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4810 tcg_temp_free(t0); 4811 #endif /* defined(CONFIG_USER_ONLY) */ 4812 } 4813 4814 #if defined(TARGET_PPC64) 4815 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4816 4817 /* mfsr */ 4818 static void gen_mfsr_64b(DisasContext *ctx) 4819 { 4820 #if defined(CONFIG_USER_ONLY) 4821 GEN_PRIV; 4822 #else 4823 TCGv t0; 4824 4825 CHK_SV; 4826 t0 = tcg_const_tl(SR(ctx->opcode)); 4827 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4828 tcg_temp_free(t0); 4829 #endif /* defined(CONFIG_USER_ONLY) */ 4830 } 4831 4832 /* mfsrin */ 4833 static void gen_mfsrin_64b(DisasContext *ctx) 4834 { 4835 #if defined(CONFIG_USER_ONLY) 4836 GEN_PRIV; 4837 #else 4838 TCGv t0; 4839 4840 CHK_SV; 4841 t0 = tcg_temp_new(); 4842 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4843 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4844 tcg_temp_free(t0); 4845 #endif /* defined(CONFIG_USER_ONLY) */ 4846 } 4847 4848 /* mtsr */ 4849 static void gen_mtsr_64b(DisasContext *ctx) 4850 { 4851 #if defined(CONFIG_USER_ONLY) 4852 GEN_PRIV; 4853 #else 4854 TCGv t0; 4855 4856 CHK_SV; 4857 t0 = tcg_const_tl(SR(ctx->opcode)); 4858 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4859 tcg_temp_free(t0); 4860 #endif /* defined(CONFIG_USER_ONLY) */ 4861 } 4862 4863 /* mtsrin */ 4864 static void gen_mtsrin_64b(DisasContext *ctx) 4865 { 4866 #if defined(CONFIG_USER_ONLY) 4867 GEN_PRIV; 4868 #else 4869 TCGv t0; 4870 4871 CHK_SV; 4872 t0 = tcg_temp_new(); 4873 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4874 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4875 tcg_temp_free(t0); 4876 #endif /* defined(CONFIG_USER_ONLY) */ 4877 } 4878 4879 /* slbmte */ 4880 static void gen_slbmte(DisasContext *ctx) 4881 { 4882 #if defined(CONFIG_USER_ONLY) 4883 GEN_PRIV; 4884 #else 4885 CHK_SV; 4886 4887 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4888 cpu_gpr[rS(ctx->opcode)]); 4889 #endif /* defined(CONFIG_USER_ONLY) */ 4890 } 4891 4892 static void gen_slbmfee(DisasContext *ctx) 4893 { 4894 #if defined(CONFIG_USER_ONLY) 4895 GEN_PRIV; 4896 #else 4897 CHK_SV; 4898 4899 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4900 cpu_gpr[rB(ctx->opcode)]); 4901 #endif /* defined(CONFIG_USER_ONLY) */ 4902 } 4903 4904 static void gen_slbmfev(DisasContext *ctx) 4905 { 4906 #if defined(CONFIG_USER_ONLY) 4907 GEN_PRIV; 4908 #else 4909 CHK_SV; 4910 4911 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4912 cpu_gpr[rB(ctx->opcode)]); 4913 #endif /* defined(CONFIG_USER_ONLY) */ 4914 } 4915 4916 static void gen_slbfee_(DisasContext *ctx) 4917 { 4918 #if defined(CONFIG_USER_ONLY) 4919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4920 #else 4921 TCGLabel *l1, *l2; 4922 4923 if (unlikely(ctx->pr)) { 4924 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4925 return; 4926 } 4927 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4928 cpu_gpr[rB(ctx->opcode)]); 4929 l1 = gen_new_label(); 4930 l2 = gen_new_label(); 4931 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4932 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4933 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4934 tcg_gen_br(l2); 4935 gen_set_label(l1); 4936 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4937 gen_set_label(l2); 4938 #endif 4939 } 4940 #endif /* defined(TARGET_PPC64) */ 4941 4942 /*** Lookaside buffer management ***/ 4943 /* Optional & supervisor only: */ 4944 4945 /* tlbia */ 4946 static void gen_tlbia(DisasContext *ctx) 4947 { 4948 #if defined(CONFIG_USER_ONLY) 4949 GEN_PRIV; 4950 #else 4951 CHK_HV; 4952 4953 gen_helper_tlbia(cpu_env); 4954 #endif /* defined(CONFIG_USER_ONLY) */ 4955 } 4956 4957 /* tlbiel */ 4958 static void gen_tlbiel(DisasContext *ctx) 4959 { 4960 #if defined(CONFIG_USER_ONLY) 4961 GEN_PRIV; 4962 #else 4963 CHK_SV; 4964 4965 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4966 #endif /* defined(CONFIG_USER_ONLY) */ 4967 } 4968 4969 /* tlbie */ 4970 static void gen_tlbie(DisasContext *ctx) 4971 { 4972 #if defined(CONFIG_USER_ONLY) 4973 GEN_PRIV; 4974 #else 4975 TCGv_i32 t1; 4976 4977 if (ctx->gtse) { 4978 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4979 } else { 4980 CHK_HV; /* Else hypervisor privileged */ 4981 } 4982 4983 if (NARROW_MODE(ctx)) { 4984 TCGv t0 = tcg_temp_new(); 4985 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4986 gen_helper_tlbie(cpu_env, t0); 4987 tcg_temp_free(t0); 4988 } else { 4989 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4990 } 4991 t1 = tcg_temp_new_i32(); 4992 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4993 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4994 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4995 tcg_temp_free_i32(t1); 4996 #endif /* defined(CONFIG_USER_ONLY) */ 4997 } 4998 4999 /* tlbsync */ 5000 static void gen_tlbsync(DisasContext *ctx) 5001 { 5002 #if defined(CONFIG_USER_ONLY) 5003 GEN_PRIV; 5004 #else 5005 5006 if (ctx->gtse) { 5007 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 5008 } else { 5009 CHK_HV; /* Else hypervisor privileged */ 5010 } 5011 5012 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5013 if (ctx->insns_flags & PPC_BOOKE) { 5014 gen_check_tlb_flush(ctx, true); 5015 } 5016 #endif /* defined(CONFIG_USER_ONLY) */ 5017 } 5018 5019 #if defined(TARGET_PPC64) 5020 /* slbia */ 5021 static void gen_slbia(DisasContext *ctx) 5022 { 5023 #if defined(CONFIG_USER_ONLY) 5024 GEN_PRIV; 5025 #else 5026 uint32_t ih = (ctx->opcode >> 21) & 0x7; 5027 TCGv_i32 t0 = tcg_const_i32(ih); 5028 5029 CHK_SV; 5030 5031 gen_helper_slbia(cpu_env, t0); 5032 tcg_temp_free_i32(t0); 5033 #endif /* defined(CONFIG_USER_ONLY) */ 5034 } 5035 5036 /* slbie */ 5037 static void gen_slbie(DisasContext *ctx) 5038 { 5039 #if defined(CONFIG_USER_ONLY) 5040 GEN_PRIV; 5041 #else 5042 CHK_SV; 5043 5044 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5045 #endif /* defined(CONFIG_USER_ONLY) */ 5046 } 5047 5048 /* slbieg */ 5049 static void gen_slbieg(DisasContext *ctx) 5050 { 5051 #if defined(CONFIG_USER_ONLY) 5052 GEN_PRIV; 5053 #else 5054 CHK_SV; 5055 5056 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5057 #endif /* defined(CONFIG_USER_ONLY) */ 5058 } 5059 5060 /* slbsync */ 5061 static void gen_slbsync(DisasContext *ctx) 5062 { 5063 #if defined(CONFIG_USER_ONLY) 5064 GEN_PRIV; 5065 #else 5066 CHK_SV; 5067 gen_check_tlb_flush(ctx, true); 5068 #endif /* defined(CONFIG_USER_ONLY) */ 5069 } 5070 5071 #endif /* defined(TARGET_PPC64) */ 5072 5073 /*** External control ***/ 5074 /* Optional: */ 5075 5076 /* eciwx */ 5077 static void gen_eciwx(DisasContext *ctx) 5078 { 5079 TCGv t0; 5080 /* Should check EAR[E] ! */ 5081 gen_set_access_type(ctx, ACCESS_EXT); 5082 t0 = tcg_temp_new(); 5083 gen_addr_reg_index(ctx, t0); 5084 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5085 DEF_MEMOP(MO_UL | MO_ALIGN)); 5086 tcg_temp_free(t0); 5087 } 5088 5089 /* ecowx */ 5090 static void gen_ecowx(DisasContext *ctx) 5091 { 5092 TCGv t0; 5093 /* Should check EAR[E] ! */ 5094 gen_set_access_type(ctx, ACCESS_EXT); 5095 t0 = tcg_temp_new(); 5096 gen_addr_reg_index(ctx, t0); 5097 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5098 DEF_MEMOP(MO_UL | MO_ALIGN)); 5099 tcg_temp_free(t0); 5100 } 5101 5102 /* PowerPC 601 specific instructions */ 5103 5104 /* abs - abs. */ 5105 static void gen_abs(DisasContext *ctx) 5106 { 5107 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5108 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5109 5110 tcg_gen_abs_tl(d, a); 5111 if (unlikely(Rc(ctx->opcode) != 0)) { 5112 gen_set_Rc0(ctx, d); 5113 } 5114 } 5115 5116 /* abso - abso. */ 5117 static void gen_abso(DisasContext *ctx) 5118 { 5119 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5120 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5121 5122 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5123 tcg_gen_abs_tl(d, a); 5124 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5125 if (unlikely(Rc(ctx->opcode) != 0)) { 5126 gen_set_Rc0(ctx, d); 5127 } 5128 } 5129 5130 /* clcs */ 5131 static void gen_clcs(DisasContext *ctx) 5132 { 5133 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5134 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5135 tcg_temp_free_i32(t0); 5136 /* Rc=1 sets CR0 to an undefined state */ 5137 } 5138 5139 /* div - div. */ 5140 static void gen_div(DisasContext *ctx) 5141 { 5142 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5143 cpu_gpr[rB(ctx->opcode)]); 5144 if (unlikely(Rc(ctx->opcode) != 0)) { 5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5146 } 5147 } 5148 5149 /* divo - divo. */ 5150 static void gen_divo(DisasContext *ctx) 5151 { 5152 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5153 cpu_gpr[rB(ctx->opcode)]); 5154 if (unlikely(Rc(ctx->opcode) != 0)) { 5155 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5156 } 5157 } 5158 5159 /* divs - divs. */ 5160 static void gen_divs(DisasContext *ctx) 5161 { 5162 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5163 cpu_gpr[rB(ctx->opcode)]); 5164 if (unlikely(Rc(ctx->opcode) != 0)) { 5165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5166 } 5167 } 5168 5169 /* divso - divso. */ 5170 static void gen_divso(DisasContext *ctx) 5171 { 5172 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5174 if (unlikely(Rc(ctx->opcode) != 0)) { 5175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5176 } 5177 } 5178 5179 /* doz - doz. */ 5180 static void gen_doz(DisasContext *ctx) 5181 { 5182 TCGLabel *l1 = gen_new_label(); 5183 TCGLabel *l2 = gen_new_label(); 5184 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5185 cpu_gpr[rA(ctx->opcode)], l1); 5186 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5187 cpu_gpr[rA(ctx->opcode)]); 5188 tcg_gen_br(l2); 5189 gen_set_label(l1); 5190 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5191 gen_set_label(l2); 5192 if (unlikely(Rc(ctx->opcode) != 0)) { 5193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5194 } 5195 } 5196 5197 /* dozo - dozo. */ 5198 static void gen_dozo(DisasContext *ctx) 5199 { 5200 TCGLabel *l1 = gen_new_label(); 5201 TCGLabel *l2 = gen_new_label(); 5202 TCGv t0 = tcg_temp_new(); 5203 TCGv t1 = tcg_temp_new(); 5204 TCGv t2 = tcg_temp_new(); 5205 /* Start with XER OV disabled, the most likely case */ 5206 tcg_gen_movi_tl(cpu_ov, 0); 5207 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5208 cpu_gpr[rA(ctx->opcode)], l1); 5209 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5210 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5211 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5212 tcg_gen_andc_tl(t1, t1, t2); 5213 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5214 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5215 tcg_gen_movi_tl(cpu_ov, 1); 5216 tcg_gen_movi_tl(cpu_so, 1); 5217 tcg_gen_br(l2); 5218 gen_set_label(l1); 5219 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5220 gen_set_label(l2); 5221 tcg_temp_free(t0); 5222 tcg_temp_free(t1); 5223 tcg_temp_free(t2); 5224 if (unlikely(Rc(ctx->opcode) != 0)) { 5225 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5226 } 5227 } 5228 5229 /* dozi */ 5230 static void gen_dozi(DisasContext *ctx) 5231 { 5232 target_long simm = SIMM(ctx->opcode); 5233 TCGLabel *l1 = gen_new_label(); 5234 TCGLabel *l2 = gen_new_label(); 5235 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5236 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5237 tcg_gen_br(l2); 5238 gen_set_label(l1); 5239 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5240 gen_set_label(l2); 5241 if (unlikely(Rc(ctx->opcode) != 0)) { 5242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5243 } 5244 } 5245 5246 /* lscbx - lscbx. */ 5247 static void gen_lscbx(DisasContext *ctx) 5248 { 5249 TCGv t0 = tcg_temp_new(); 5250 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5251 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5252 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5253 5254 gen_addr_reg_index(ctx, t0); 5255 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5256 tcg_temp_free_i32(t1); 5257 tcg_temp_free_i32(t2); 5258 tcg_temp_free_i32(t3); 5259 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5260 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5261 if (unlikely(Rc(ctx->opcode) != 0)) { 5262 gen_set_Rc0(ctx, t0); 5263 } 5264 tcg_temp_free(t0); 5265 } 5266 5267 /* maskg - maskg. */ 5268 static void gen_maskg(DisasContext *ctx) 5269 { 5270 TCGLabel *l1 = gen_new_label(); 5271 TCGv t0 = tcg_temp_new(); 5272 TCGv t1 = tcg_temp_new(); 5273 TCGv t2 = tcg_temp_new(); 5274 TCGv t3 = tcg_temp_new(); 5275 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5276 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5277 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5278 tcg_gen_addi_tl(t2, t0, 1); 5279 tcg_gen_shr_tl(t2, t3, t2); 5280 tcg_gen_shr_tl(t3, t3, t1); 5281 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5282 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5283 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5284 gen_set_label(l1); 5285 tcg_temp_free(t0); 5286 tcg_temp_free(t1); 5287 tcg_temp_free(t2); 5288 tcg_temp_free(t3); 5289 if (unlikely(Rc(ctx->opcode) != 0)) { 5290 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5291 } 5292 } 5293 5294 /* maskir - maskir. */ 5295 static void gen_maskir(DisasContext *ctx) 5296 { 5297 TCGv t0 = tcg_temp_new(); 5298 TCGv t1 = tcg_temp_new(); 5299 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5300 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5301 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5302 tcg_temp_free(t0); 5303 tcg_temp_free(t1); 5304 if (unlikely(Rc(ctx->opcode) != 0)) { 5305 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5306 } 5307 } 5308 5309 /* mul - mul. */ 5310 static void gen_mul(DisasContext *ctx) 5311 { 5312 TCGv_i64 t0 = tcg_temp_new_i64(); 5313 TCGv_i64 t1 = tcg_temp_new_i64(); 5314 TCGv t2 = tcg_temp_new(); 5315 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5316 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5317 tcg_gen_mul_i64(t0, t0, t1); 5318 tcg_gen_trunc_i64_tl(t2, t0); 5319 gen_store_spr(SPR_MQ, t2); 5320 tcg_gen_shri_i64(t1, t0, 32); 5321 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5322 tcg_temp_free_i64(t0); 5323 tcg_temp_free_i64(t1); 5324 tcg_temp_free(t2); 5325 if (unlikely(Rc(ctx->opcode) != 0)) { 5326 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5327 } 5328 } 5329 5330 /* mulo - mulo. */ 5331 static void gen_mulo(DisasContext *ctx) 5332 { 5333 TCGLabel *l1 = gen_new_label(); 5334 TCGv_i64 t0 = tcg_temp_new_i64(); 5335 TCGv_i64 t1 = tcg_temp_new_i64(); 5336 TCGv t2 = tcg_temp_new(); 5337 /* Start with XER OV disabled, the most likely case */ 5338 tcg_gen_movi_tl(cpu_ov, 0); 5339 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5340 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5341 tcg_gen_mul_i64(t0, t0, t1); 5342 tcg_gen_trunc_i64_tl(t2, t0); 5343 gen_store_spr(SPR_MQ, t2); 5344 tcg_gen_shri_i64(t1, t0, 32); 5345 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5346 tcg_gen_ext32s_i64(t1, t0); 5347 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5348 tcg_gen_movi_tl(cpu_ov, 1); 5349 tcg_gen_movi_tl(cpu_so, 1); 5350 gen_set_label(l1); 5351 tcg_temp_free_i64(t0); 5352 tcg_temp_free_i64(t1); 5353 tcg_temp_free(t2); 5354 if (unlikely(Rc(ctx->opcode) != 0)) { 5355 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5356 } 5357 } 5358 5359 /* nabs - nabs. */ 5360 static void gen_nabs(DisasContext *ctx) 5361 { 5362 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5363 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5364 5365 tcg_gen_abs_tl(d, a); 5366 tcg_gen_neg_tl(d, d); 5367 if (unlikely(Rc(ctx->opcode) != 0)) { 5368 gen_set_Rc0(ctx, d); 5369 } 5370 } 5371 5372 /* nabso - nabso. */ 5373 static void gen_nabso(DisasContext *ctx) 5374 { 5375 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5376 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5377 5378 tcg_gen_abs_tl(d, a); 5379 tcg_gen_neg_tl(d, d); 5380 /* nabs never overflows */ 5381 tcg_gen_movi_tl(cpu_ov, 0); 5382 if (unlikely(Rc(ctx->opcode) != 0)) { 5383 gen_set_Rc0(ctx, d); 5384 } 5385 } 5386 5387 /* rlmi - rlmi. */ 5388 static void gen_rlmi(DisasContext *ctx) 5389 { 5390 uint32_t mb = MB(ctx->opcode); 5391 uint32_t me = ME(ctx->opcode); 5392 TCGv t0 = tcg_temp_new(); 5393 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5394 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5395 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5396 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5397 ~MASK(mb, me)); 5398 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5399 tcg_temp_free(t0); 5400 if (unlikely(Rc(ctx->opcode) != 0)) { 5401 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5402 } 5403 } 5404 5405 /* rrib - rrib. */ 5406 static void gen_rrib(DisasContext *ctx) 5407 { 5408 TCGv t0 = tcg_temp_new(); 5409 TCGv t1 = tcg_temp_new(); 5410 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5411 tcg_gen_movi_tl(t1, 0x80000000); 5412 tcg_gen_shr_tl(t1, t1, t0); 5413 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5414 tcg_gen_and_tl(t0, t0, t1); 5415 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5416 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5417 tcg_temp_free(t0); 5418 tcg_temp_free(t1); 5419 if (unlikely(Rc(ctx->opcode) != 0)) { 5420 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5421 } 5422 } 5423 5424 /* sle - sle. */ 5425 static void gen_sle(DisasContext *ctx) 5426 { 5427 TCGv t0 = tcg_temp_new(); 5428 TCGv t1 = tcg_temp_new(); 5429 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5430 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5431 tcg_gen_subfi_tl(t1, 32, t1); 5432 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5433 tcg_gen_or_tl(t1, t0, t1); 5434 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5435 gen_store_spr(SPR_MQ, t1); 5436 tcg_temp_free(t0); 5437 tcg_temp_free(t1); 5438 if (unlikely(Rc(ctx->opcode) != 0)) { 5439 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5440 } 5441 } 5442 5443 /* sleq - sleq. */ 5444 static void gen_sleq(DisasContext *ctx) 5445 { 5446 TCGv t0 = tcg_temp_new(); 5447 TCGv t1 = tcg_temp_new(); 5448 TCGv t2 = tcg_temp_new(); 5449 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5450 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5451 tcg_gen_shl_tl(t2, t2, t0); 5452 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5453 gen_load_spr(t1, SPR_MQ); 5454 gen_store_spr(SPR_MQ, t0); 5455 tcg_gen_and_tl(t0, t0, t2); 5456 tcg_gen_andc_tl(t1, t1, t2); 5457 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5458 tcg_temp_free(t0); 5459 tcg_temp_free(t1); 5460 tcg_temp_free(t2); 5461 if (unlikely(Rc(ctx->opcode) != 0)) { 5462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5463 } 5464 } 5465 5466 /* sliq - sliq. */ 5467 static void gen_sliq(DisasContext *ctx) 5468 { 5469 int sh = SH(ctx->opcode); 5470 TCGv t0 = tcg_temp_new(); 5471 TCGv t1 = tcg_temp_new(); 5472 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5473 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5474 tcg_gen_or_tl(t1, t0, t1); 5475 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5476 gen_store_spr(SPR_MQ, t1); 5477 tcg_temp_free(t0); 5478 tcg_temp_free(t1); 5479 if (unlikely(Rc(ctx->opcode) != 0)) { 5480 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5481 } 5482 } 5483 5484 /* slliq - slliq. */ 5485 static void gen_slliq(DisasContext *ctx) 5486 { 5487 int sh = SH(ctx->opcode); 5488 TCGv t0 = tcg_temp_new(); 5489 TCGv t1 = tcg_temp_new(); 5490 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5491 gen_load_spr(t1, SPR_MQ); 5492 gen_store_spr(SPR_MQ, t0); 5493 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5494 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5495 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5496 tcg_temp_free(t0); 5497 tcg_temp_free(t1); 5498 if (unlikely(Rc(ctx->opcode) != 0)) { 5499 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5500 } 5501 } 5502 5503 /* sllq - sllq. */ 5504 static void gen_sllq(DisasContext *ctx) 5505 { 5506 TCGLabel *l1 = gen_new_label(); 5507 TCGLabel *l2 = gen_new_label(); 5508 TCGv t0 = tcg_temp_local_new(); 5509 TCGv t1 = tcg_temp_local_new(); 5510 TCGv t2 = tcg_temp_local_new(); 5511 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5512 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5513 tcg_gen_shl_tl(t1, t1, t2); 5514 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5515 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5516 gen_load_spr(t0, SPR_MQ); 5517 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5518 tcg_gen_br(l2); 5519 gen_set_label(l1); 5520 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5521 gen_load_spr(t2, SPR_MQ); 5522 tcg_gen_andc_tl(t1, t2, t1); 5523 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5524 gen_set_label(l2); 5525 tcg_temp_free(t0); 5526 tcg_temp_free(t1); 5527 tcg_temp_free(t2); 5528 if (unlikely(Rc(ctx->opcode) != 0)) { 5529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5530 } 5531 } 5532 5533 /* slq - slq. */ 5534 static void gen_slq(DisasContext *ctx) 5535 { 5536 TCGLabel *l1 = gen_new_label(); 5537 TCGv t0 = tcg_temp_new(); 5538 TCGv t1 = tcg_temp_new(); 5539 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5540 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5541 tcg_gen_subfi_tl(t1, 32, t1); 5542 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5543 tcg_gen_or_tl(t1, t0, t1); 5544 gen_store_spr(SPR_MQ, t1); 5545 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5547 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5548 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5549 gen_set_label(l1); 5550 tcg_temp_free(t0); 5551 tcg_temp_free(t1); 5552 if (unlikely(Rc(ctx->opcode) != 0)) { 5553 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5554 } 5555 } 5556 5557 /* sraiq - sraiq. */ 5558 static void gen_sraiq(DisasContext *ctx) 5559 { 5560 int sh = SH(ctx->opcode); 5561 TCGLabel *l1 = gen_new_label(); 5562 TCGv t0 = tcg_temp_new(); 5563 TCGv t1 = tcg_temp_new(); 5564 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5565 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5566 tcg_gen_or_tl(t0, t0, t1); 5567 gen_store_spr(SPR_MQ, t0); 5568 tcg_gen_movi_tl(cpu_ca, 0); 5569 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5570 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5571 tcg_gen_movi_tl(cpu_ca, 1); 5572 gen_set_label(l1); 5573 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5574 tcg_temp_free(t0); 5575 tcg_temp_free(t1); 5576 if (unlikely(Rc(ctx->opcode) != 0)) { 5577 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5578 } 5579 } 5580 5581 /* sraq - sraq. */ 5582 static void gen_sraq(DisasContext *ctx) 5583 { 5584 TCGLabel *l1 = gen_new_label(); 5585 TCGLabel *l2 = gen_new_label(); 5586 TCGv t0 = tcg_temp_new(); 5587 TCGv t1 = tcg_temp_local_new(); 5588 TCGv t2 = tcg_temp_local_new(); 5589 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5590 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5591 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5592 tcg_gen_subfi_tl(t2, 32, t2); 5593 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5594 tcg_gen_or_tl(t0, t0, t2); 5595 gen_store_spr(SPR_MQ, t0); 5596 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5597 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5598 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5599 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5600 gen_set_label(l1); 5601 tcg_temp_free(t0); 5602 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5603 tcg_gen_movi_tl(cpu_ca, 0); 5604 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5605 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5606 tcg_gen_movi_tl(cpu_ca, 1); 5607 gen_set_label(l2); 5608 tcg_temp_free(t1); 5609 tcg_temp_free(t2); 5610 if (unlikely(Rc(ctx->opcode) != 0)) { 5611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5612 } 5613 } 5614 5615 /* sre - sre. */ 5616 static void gen_sre(DisasContext *ctx) 5617 { 5618 TCGv t0 = tcg_temp_new(); 5619 TCGv t1 = tcg_temp_new(); 5620 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5621 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5622 tcg_gen_subfi_tl(t1, 32, t1); 5623 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5624 tcg_gen_or_tl(t1, t0, t1); 5625 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5626 gen_store_spr(SPR_MQ, t1); 5627 tcg_temp_free(t0); 5628 tcg_temp_free(t1); 5629 if (unlikely(Rc(ctx->opcode) != 0)) { 5630 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5631 } 5632 } 5633 5634 /* srea - srea. */ 5635 static void gen_srea(DisasContext *ctx) 5636 { 5637 TCGv t0 = tcg_temp_new(); 5638 TCGv t1 = tcg_temp_new(); 5639 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5640 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5641 gen_store_spr(SPR_MQ, t0); 5642 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5643 tcg_temp_free(t0); 5644 tcg_temp_free(t1); 5645 if (unlikely(Rc(ctx->opcode) != 0)) { 5646 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5647 } 5648 } 5649 5650 /* sreq */ 5651 static void gen_sreq(DisasContext *ctx) 5652 { 5653 TCGv t0 = tcg_temp_new(); 5654 TCGv t1 = tcg_temp_new(); 5655 TCGv t2 = tcg_temp_new(); 5656 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5657 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5658 tcg_gen_shr_tl(t1, t1, t0); 5659 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5660 gen_load_spr(t2, SPR_MQ); 5661 gen_store_spr(SPR_MQ, t0); 5662 tcg_gen_and_tl(t0, t0, t1); 5663 tcg_gen_andc_tl(t2, t2, t1); 5664 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5665 tcg_temp_free(t0); 5666 tcg_temp_free(t1); 5667 tcg_temp_free(t2); 5668 if (unlikely(Rc(ctx->opcode) != 0)) { 5669 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5670 } 5671 } 5672 5673 /* sriq */ 5674 static void gen_sriq(DisasContext *ctx) 5675 { 5676 int sh = SH(ctx->opcode); 5677 TCGv t0 = tcg_temp_new(); 5678 TCGv t1 = tcg_temp_new(); 5679 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5680 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5681 tcg_gen_or_tl(t1, t0, t1); 5682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5683 gen_store_spr(SPR_MQ, t1); 5684 tcg_temp_free(t0); 5685 tcg_temp_free(t1); 5686 if (unlikely(Rc(ctx->opcode) != 0)) { 5687 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5688 } 5689 } 5690 5691 /* srliq */ 5692 static void gen_srliq(DisasContext *ctx) 5693 { 5694 int sh = SH(ctx->opcode); 5695 TCGv t0 = tcg_temp_new(); 5696 TCGv t1 = tcg_temp_new(); 5697 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5698 gen_load_spr(t1, SPR_MQ); 5699 gen_store_spr(SPR_MQ, t0); 5700 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5701 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5702 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5703 tcg_temp_free(t0); 5704 tcg_temp_free(t1); 5705 if (unlikely(Rc(ctx->opcode) != 0)) { 5706 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5707 } 5708 } 5709 5710 /* srlq */ 5711 static void gen_srlq(DisasContext *ctx) 5712 { 5713 TCGLabel *l1 = gen_new_label(); 5714 TCGLabel *l2 = gen_new_label(); 5715 TCGv t0 = tcg_temp_local_new(); 5716 TCGv t1 = tcg_temp_local_new(); 5717 TCGv t2 = tcg_temp_local_new(); 5718 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5719 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5720 tcg_gen_shr_tl(t2, t1, t2); 5721 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5722 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5723 gen_load_spr(t0, SPR_MQ); 5724 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5725 tcg_gen_br(l2); 5726 gen_set_label(l1); 5727 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5728 tcg_gen_and_tl(t0, t0, t2); 5729 gen_load_spr(t1, SPR_MQ); 5730 tcg_gen_andc_tl(t1, t1, t2); 5731 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5732 gen_set_label(l2); 5733 tcg_temp_free(t0); 5734 tcg_temp_free(t1); 5735 tcg_temp_free(t2); 5736 if (unlikely(Rc(ctx->opcode) != 0)) { 5737 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5738 } 5739 } 5740 5741 /* srq */ 5742 static void gen_srq(DisasContext *ctx) 5743 { 5744 TCGLabel *l1 = gen_new_label(); 5745 TCGv t0 = tcg_temp_new(); 5746 TCGv t1 = tcg_temp_new(); 5747 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5748 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5749 tcg_gen_subfi_tl(t1, 32, t1); 5750 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5751 tcg_gen_or_tl(t1, t0, t1); 5752 gen_store_spr(SPR_MQ, t1); 5753 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5754 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5755 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5756 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5757 gen_set_label(l1); 5758 tcg_temp_free(t0); 5759 tcg_temp_free(t1); 5760 if (unlikely(Rc(ctx->opcode) != 0)) { 5761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5762 } 5763 } 5764 5765 /* PowerPC 602 specific instructions */ 5766 5767 /* dsa */ 5768 static void gen_dsa(DisasContext *ctx) 5769 { 5770 /* XXX: TODO */ 5771 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5772 } 5773 5774 /* esa */ 5775 static void gen_esa(DisasContext *ctx) 5776 { 5777 /* XXX: TODO */ 5778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5779 } 5780 5781 /* mfrom */ 5782 static void gen_mfrom(DisasContext *ctx) 5783 { 5784 #if defined(CONFIG_USER_ONLY) 5785 GEN_PRIV; 5786 #else 5787 CHK_SV; 5788 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5789 #endif /* defined(CONFIG_USER_ONLY) */ 5790 } 5791 5792 /* 602 - 603 - G2 TLB management */ 5793 5794 /* tlbld */ 5795 static void gen_tlbld_6xx(DisasContext *ctx) 5796 { 5797 #if defined(CONFIG_USER_ONLY) 5798 GEN_PRIV; 5799 #else 5800 CHK_SV; 5801 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5802 #endif /* defined(CONFIG_USER_ONLY) */ 5803 } 5804 5805 /* tlbli */ 5806 static void gen_tlbli_6xx(DisasContext *ctx) 5807 { 5808 #if defined(CONFIG_USER_ONLY) 5809 GEN_PRIV; 5810 #else 5811 CHK_SV; 5812 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5813 #endif /* defined(CONFIG_USER_ONLY) */ 5814 } 5815 5816 /* 74xx TLB management */ 5817 5818 /* tlbld */ 5819 static void gen_tlbld_74xx(DisasContext *ctx) 5820 { 5821 #if defined(CONFIG_USER_ONLY) 5822 GEN_PRIV; 5823 #else 5824 CHK_SV; 5825 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5826 #endif /* defined(CONFIG_USER_ONLY) */ 5827 } 5828 5829 /* tlbli */ 5830 static void gen_tlbli_74xx(DisasContext *ctx) 5831 { 5832 #if defined(CONFIG_USER_ONLY) 5833 GEN_PRIV; 5834 #else 5835 CHK_SV; 5836 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5837 #endif /* defined(CONFIG_USER_ONLY) */ 5838 } 5839 5840 /* POWER instructions not in PowerPC 601 */ 5841 5842 /* clf */ 5843 static void gen_clf(DisasContext *ctx) 5844 { 5845 /* Cache line flush: implemented as no-op */ 5846 } 5847 5848 /* cli */ 5849 static void gen_cli(DisasContext *ctx) 5850 { 5851 #if defined(CONFIG_USER_ONLY) 5852 GEN_PRIV; 5853 #else 5854 /* Cache line invalidate: privileged and treated as no-op */ 5855 CHK_SV; 5856 #endif /* defined(CONFIG_USER_ONLY) */ 5857 } 5858 5859 /* dclst */ 5860 static void gen_dclst(DisasContext *ctx) 5861 { 5862 /* Data cache line store: treated as no-op */ 5863 } 5864 5865 static void gen_mfsri(DisasContext *ctx) 5866 { 5867 #if defined(CONFIG_USER_ONLY) 5868 GEN_PRIV; 5869 #else 5870 int ra = rA(ctx->opcode); 5871 int rd = rD(ctx->opcode); 5872 TCGv t0; 5873 5874 CHK_SV; 5875 t0 = tcg_temp_new(); 5876 gen_addr_reg_index(ctx, t0); 5877 tcg_gen_extract_tl(t0, t0, 28, 4); 5878 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5879 tcg_temp_free(t0); 5880 if (ra != 0 && ra != rd) { 5881 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5882 } 5883 #endif /* defined(CONFIG_USER_ONLY) */ 5884 } 5885 5886 static void gen_rac(DisasContext *ctx) 5887 { 5888 #if defined(CONFIG_USER_ONLY) 5889 GEN_PRIV; 5890 #else 5891 TCGv t0; 5892 5893 CHK_SV; 5894 t0 = tcg_temp_new(); 5895 gen_addr_reg_index(ctx, t0); 5896 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5897 tcg_temp_free(t0); 5898 #endif /* defined(CONFIG_USER_ONLY) */ 5899 } 5900 5901 static void gen_rfsvc(DisasContext *ctx) 5902 { 5903 #if defined(CONFIG_USER_ONLY) 5904 GEN_PRIV; 5905 #else 5906 CHK_SV; 5907 5908 gen_helper_rfsvc(cpu_env); 5909 gen_sync_exception(ctx); 5910 #endif /* defined(CONFIG_USER_ONLY) */ 5911 } 5912 5913 /* svc is not implemented for now */ 5914 5915 /* BookE specific instructions */ 5916 5917 /* XXX: not implemented on 440 ? */ 5918 static void gen_mfapidi(DisasContext *ctx) 5919 { 5920 /* XXX: TODO */ 5921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5922 } 5923 5924 /* XXX: not implemented on 440 ? */ 5925 static void gen_tlbiva(DisasContext *ctx) 5926 { 5927 #if defined(CONFIG_USER_ONLY) 5928 GEN_PRIV; 5929 #else 5930 TCGv t0; 5931 5932 CHK_SV; 5933 t0 = tcg_temp_new(); 5934 gen_addr_reg_index(ctx, t0); 5935 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5936 tcg_temp_free(t0); 5937 #endif /* defined(CONFIG_USER_ONLY) */ 5938 } 5939 5940 /* All 405 MAC instructions are translated here */ 5941 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5942 int ra, int rb, int rt, int Rc) 5943 { 5944 TCGv t0, t1; 5945 5946 t0 = tcg_temp_local_new(); 5947 t1 = tcg_temp_local_new(); 5948 5949 switch (opc3 & 0x0D) { 5950 case 0x05: 5951 /* macchw - macchw. - macchwo - macchwo. */ 5952 /* macchws - macchws. - macchwso - macchwso. */ 5953 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5954 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5955 /* mulchw - mulchw. */ 5956 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5957 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5958 tcg_gen_ext16s_tl(t1, t1); 5959 break; 5960 case 0x04: 5961 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5962 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5963 /* mulchwu - mulchwu. */ 5964 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5965 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5966 tcg_gen_ext16u_tl(t1, t1); 5967 break; 5968 case 0x01: 5969 /* machhw - machhw. - machhwo - machhwo. */ 5970 /* machhws - machhws. - machhwso - machhwso. */ 5971 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5972 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5973 /* mulhhw - mulhhw. */ 5974 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5975 tcg_gen_ext16s_tl(t0, t0); 5976 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5977 tcg_gen_ext16s_tl(t1, t1); 5978 break; 5979 case 0x00: 5980 /* machhwu - machhwu. - machhwuo - machhwuo. */ 5981 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5982 /* mulhhwu - mulhhwu. */ 5983 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5984 tcg_gen_ext16u_tl(t0, t0); 5985 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5986 tcg_gen_ext16u_tl(t1, t1); 5987 break; 5988 case 0x0D: 5989 /* maclhw - maclhw. - maclhwo - maclhwo. */ 5990 /* maclhws - maclhws. - maclhwso - maclhwso. */ 5991 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5992 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5993 /* mullhw - mullhw. */ 5994 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5995 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5996 break; 5997 case 0x0C: 5998 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5999 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6000 /* mullhwu - mullhwu. */ 6001 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6002 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6003 break; 6004 } 6005 if (opc2 & 0x04) { 6006 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6007 tcg_gen_mul_tl(t1, t0, t1); 6008 if (opc2 & 0x02) { 6009 /* nmultiply-and-accumulate (0x0E) */ 6010 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6011 } else { 6012 /* multiply-and-accumulate (0x0C) */ 6013 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6014 } 6015 6016 if (opc3 & 0x12) { 6017 /* Check overflow and/or saturate */ 6018 TCGLabel *l1 = gen_new_label(); 6019 6020 if (opc3 & 0x10) { 6021 /* Start with XER OV disabled, the most likely case */ 6022 tcg_gen_movi_tl(cpu_ov, 0); 6023 } 6024 if (opc3 & 0x01) { 6025 /* Signed */ 6026 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6027 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6028 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6029 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6030 if (opc3 & 0x02) { 6031 /* Saturate */ 6032 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6033 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6034 } 6035 } else { 6036 /* Unsigned */ 6037 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6038 if (opc3 & 0x02) { 6039 /* Saturate */ 6040 tcg_gen_movi_tl(t0, UINT32_MAX); 6041 } 6042 } 6043 if (opc3 & 0x10) { 6044 /* Check overflow */ 6045 tcg_gen_movi_tl(cpu_ov, 1); 6046 tcg_gen_movi_tl(cpu_so, 1); 6047 } 6048 gen_set_label(l1); 6049 tcg_gen_mov_tl(cpu_gpr[rt], t0); 6050 } 6051 } else { 6052 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6053 } 6054 tcg_temp_free(t0); 6055 tcg_temp_free(t1); 6056 if (unlikely(Rc) != 0) { 6057 /* Update Rc0 */ 6058 gen_set_Rc0(ctx, cpu_gpr[rt]); 6059 } 6060 } 6061 6062 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6063 static void glue(gen_, name)(DisasContext *ctx) \ 6064 { \ 6065 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6066 rD(ctx->opcode), Rc(ctx->opcode)); \ 6067 } 6068 6069 /* macchw - macchw. */ 6070 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6071 /* macchwo - macchwo. */ 6072 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6073 /* macchws - macchws. */ 6074 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6075 /* macchwso - macchwso. */ 6076 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6077 /* macchwsu - macchwsu. */ 6078 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6079 /* macchwsuo - macchwsuo. */ 6080 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6081 /* macchwu - macchwu. */ 6082 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6083 /* macchwuo - macchwuo. */ 6084 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6085 /* machhw - machhw. */ 6086 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6087 /* machhwo - machhwo. */ 6088 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6089 /* machhws - machhws. */ 6090 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6091 /* machhwso - machhwso. */ 6092 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6093 /* machhwsu - machhwsu. */ 6094 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6095 /* machhwsuo - machhwsuo. */ 6096 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6097 /* machhwu - machhwu. */ 6098 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6099 /* machhwuo - machhwuo. */ 6100 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6101 /* maclhw - maclhw. */ 6102 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6103 /* maclhwo - maclhwo. */ 6104 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6105 /* maclhws - maclhws. */ 6106 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6107 /* maclhwso - maclhwso. */ 6108 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6109 /* maclhwu - maclhwu. */ 6110 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6111 /* maclhwuo - maclhwuo. */ 6112 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6113 /* maclhwsu - maclhwsu. */ 6114 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6115 /* maclhwsuo - maclhwsuo. */ 6116 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6117 /* nmacchw - nmacchw. */ 6118 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6119 /* nmacchwo - nmacchwo. */ 6120 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6121 /* nmacchws - nmacchws. */ 6122 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6123 /* nmacchwso - nmacchwso. */ 6124 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6125 /* nmachhw - nmachhw. */ 6126 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6127 /* nmachhwo - nmachhwo. */ 6128 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6129 /* nmachhws - nmachhws. */ 6130 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6131 /* nmachhwso - nmachhwso. */ 6132 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6133 /* nmaclhw - nmaclhw. */ 6134 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6135 /* nmaclhwo - nmaclhwo. */ 6136 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6137 /* nmaclhws - nmaclhws. */ 6138 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6139 /* nmaclhwso - nmaclhwso. */ 6140 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6141 6142 /* mulchw - mulchw. */ 6143 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6144 /* mulchwu - mulchwu. */ 6145 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6146 /* mulhhw - mulhhw. */ 6147 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6148 /* mulhhwu - mulhhwu. */ 6149 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6150 /* mullhw - mullhw. */ 6151 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6152 /* mullhwu - mullhwu. */ 6153 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6154 6155 /* mfdcr */ 6156 static void gen_mfdcr(DisasContext *ctx) 6157 { 6158 #if defined(CONFIG_USER_ONLY) 6159 GEN_PRIV; 6160 #else 6161 TCGv dcrn; 6162 6163 CHK_SV; 6164 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6165 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6166 tcg_temp_free(dcrn); 6167 #endif /* defined(CONFIG_USER_ONLY) */ 6168 } 6169 6170 /* mtdcr */ 6171 static void gen_mtdcr(DisasContext *ctx) 6172 { 6173 #if defined(CONFIG_USER_ONLY) 6174 GEN_PRIV; 6175 #else 6176 TCGv dcrn; 6177 6178 CHK_SV; 6179 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6180 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6181 tcg_temp_free(dcrn); 6182 #endif /* defined(CONFIG_USER_ONLY) */ 6183 } 6184 6185 /* mfdcrx */ 6186 /* XXX: not implemented on 440 ? */ 6187 static void gen_mfdcrx(DisasContext *ctx) 6188 { 6189 #if defined(CONFIG_USER_ONLY) 6190 GEN_PRIV; 6191 #else 6192 CHK_SV; 6193 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6194 cpu_gpr[rA(ctx->opcode)]); 6195 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6196 #endif /* defined(CONFIG_USER_ONLY) */ 6197 } 6198 6199 /* mtdcrx */ 6200 /* XXX: not implemented on 440 ? */ 6201 static void gen_mtdcrx(DisasContext *ctx) 6202 { 6203 #if defined(CONFIG_USER_ONLY) 6204 GEN_PRIV; 6205 #else 6206 CHK_SV; 6207 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6208 cpu_gpr[rS(ctx->opcode)]); 6209 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6210 #endif /* defined(CONFIG_USER_ONLY) */ 6211 } 6212 6213 /* mfdcrux (PPC 460) : user-mode access to DCR */ 6214 static void gen_mfdcrux(DisasContext *ctx) 6215 { 6216 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6217 cpu_gpr[rA(ctx->opcode)]); 6218 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6219 } 6220 6221 /* mtdcrux (PPC 460) : user-mode access to DCR */ 6222 static void gen_mtdcrux(DisasContext *ctx) 6223 { 6224 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6225 cpu_gpr[rS(ctx->opcode)]); 6226 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6227 } 6228 6229 /* dccci */ 6230 static void gen_dccci(DisasContext *ctx) 6231 { 6232 CHK_SV; 6233 /* interpreted as no-op */ 6234 } 6235 6236 /* dcread */ 6237 static void gen_dcread(DisasContext *ctx) 6238 { 6239 #if defined(CONFIG_USER_ONLY) 6240 GEN_PRIV; 6241 #else 6242 TCGv EA, val; 6243 6244 CHK_SV; 6245 gen_set_access_type(ctx, ACCESS_CACHE); 6246 EA = tcg_temp_new(); 6247 gen_addr_reg_index(ctx, EA); 6248 val = tcg_temp_new(); 6249 gen_qemu_ld32u(ctx, val, EA); 6250 tcg_temp_free(val); 6251 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6252 tcg_temp_free(EA); 6253 #endif /* defined(CONFIG_USER_ONLY) */ 6254 } 6255 6256 /* icbt */ 6257 static void gen_icbt_40x(DisasContext *ctx) 6258 { 6259 /* 6260 * interpreted as no-op 6261 * XXX: specification say this is treated as a load by the MMU but 6262 * does not generate any exception 6263 */ 6264 } 6265 6266 /* iccci */ 6267 static void gen_iccci(DisasContext *ctx) 6268 { 6269 CHK_SV; 6270 /* interpreted as no-op */ 6271 } 6272 6273 /* icread */ 6274 static void gen_icread(DisasContext *ctx) 6275 { 6276 CHK_SV; 6277 /* interpreted as no-op */ 6278 } 6279 6280 /* rfci (supervisor only) */ 6281 static void gen_rfci_40x(DisasContext *ctx) 6282 { 6283 #if defined(CONFIG_USER_ONLY) 6284 GEN_PRIV; 6285 #else 6286 CHK_SV; 6287 /* Restore CPU state */ 6288 gen_helper_40x_rfci(cpu_env); 6289 gen_sync_exception(ctx); 6290 #endif /* defined(CONFIG_USER_ONLY) */ 6291 } 6292 6293 static void gen_rfci(DisasContext *ctx) 6294 { 6295 #if defined(CONFIG_USER_ONLY) 6296 GEN_PRIV; 6297 #else 6298 CHK_SV; 6299 /* Restore CPU state */ 6300 gen_helper_rfci(cpu_env); 6301 gen_sync_exception(ctx); 6302 #endif /* defined(CONFIG_USER_ONLY) */ 6303 } 6304 6305 /* BookE specific */ 6306 6307 /* XXX: not implemented on 440 ? */ 6308 static void gen_rfdi(DisasContext *ctx) 6309 { 6310 #if defined(CONFIG_USER_ONLY) 6311 GEN_PRIV; 6312 #else 6313 CHK_SV; 6314 /* Restore CPU state */ 6315 gen_helper_rfdi(cpu_env); 6316 gen_sync_exception(ctx); 6317 #endif /* defined(CONFIG_USER_ONLY) */ 6318 } 6319 6320 /* XXX: not implemented on 440 ? */ 6321 static void gen_rfmci(DisasContext *ctx) 6322 { 6323 #if defined(CONFIG_USER_ONLY) 6324 GEN_PRIV; 6325 #else 6326 CHK_SV; 6327 /* Restore CPU state */ 6328 gen_helper_rfmci(cpu_env); 6329 gen_sync_exception(ctx); 6330 #endif /* defined(CONFIG_USER_ONLY) */ 6331 } 6332 6333 /* TLB management - PowerPC 405 implementation */ 6334 6335 /* tlbre */ 6336 static void gen_tlbre_40x(DisasContext *ctx) 6337 { 6338 #if defined(CONFIG_USER_ONLY) 6339 GEN_PRIV; 6340 #else 6341 CHK_SV; 6342 switch (rB(ctx->opcode)) { 6343 case 0: 6344 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6345 cpu_gpr[rA(ctx->opcode)]); 6346 break; 6347 case 1: 6348 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6349 cpu_gpr[rA(ctx->opcode)]); 6350 break; 6351 default: 6352 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6353 break; 6354 } 6355 #endif /* defined(CONFIG_USER_ONLY) */ 6356 } 6357 6358 /* tlbsx - tlbsx. */ 6359 static void gen_tlbsx_40x(DisasContext *ctx) 6360 { 6361 #if defined(CONFIG_USER_ONLY) 6362 GEN_PRIV; 6363 #else 6364 TCGv t0; 6365 6366 CHK_SV; 6367 t0 = tcg_temp_new(); 6368 gen_addr_reg_index(ctx, t0); 6369 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6370 tcg_temp_free(t0); 6371 if (Rc(ctx->opcode)) { 6372 TCGLabel *l1 = gen_new_label(); 6373 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6374 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6375 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6376 gen_set_label(l1); 6377 } 6378 #endif /* defined(CONFIG_USER_ONLY) */ 6379 } 6380 6381 /* tlbwe */ 6382 static void gen_tlbwe_40x(DisasContext *ctx) 6383 { 6384 #if defined(CONFIG_USER_ONLY) 6385 GEN_PRIV; 6386 #else 6387 CHK_SV; 6388 6389 switch (rB(ctx->opcode)) { 6390 case 0: 6391 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6392 cpu_gpr[rS(ctx->opcode)]); 6393 break; 6394 case 1: 6395 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6396 cpu_gpr[rS(ctx->opcode)]); 6397 break; 6398 default: 6399 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6400 break; 6401 } 6402 #endif /* defined(CONFIG_USER_ONLY) */ 6403 } 6404 6405 /* TLB management - PowerPC 440 implementation */ 6406 6407 /* tlbre */ 6408 static void gen_tlbre_440(DisasContext *ctx) 6409 { 6410 #if defined(CONFIG_USER_ONLY) 6411 GEN_PRIV; 6412 #else 6413 CHK_SV; 6414 6415 switch (rB(ctx->opcode)) { 6416 case 0: 6417 case 1: 6418 case 2: 6419 { 6420 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6421 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6422 t0, cpu_gpr[rA(ctx->opcode)]); 6423 tcg_temp_free_i32(t0); 6424 } 6425 break; 6426 default: 6427 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6428 break; 6429 } 6430 #endif /* defined(CONFIG_USER_ONLY) */ 6431 } 6432 6433 /* tlbsx - tlbsx. */ 6434 static void gen_tlbsx_440(DisasContext *ctx) 6435 { 6436 #if defined(CONFIG_USER_ONLY) 6437 GEN_PRIV; 6438 #else 6439 TCGv t0; 6440 6441 CHK_SV; 6442 t0 = tcg_temp_new(); 6443 gen_addr_reg_index(ctx, t0); 6444 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6445 tcg_temp_free(t0); 6446 if (Rc(ctx->opcode)) { 6447 TCGLabel *l1 = gen_new_label(); 6448 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6449 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6450 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6451 gen_set_label(l1); 6452 } 6453 #endif /* defined(CONFIG_USER_ONLY) */ 6454 } 6455 6456 /* tlbwe */ 6457 static void gen_tlbwe_440(DisasContext *ctx) 6458 { 6459 #if defined(CONFIG_USER_ONLY) 6460 GEN_PRIV; 6461 #else 6462 CHK_SV; 6463 switch (rB(ctx->opcode)) { 6464 case 0: 6465 case 1: 6466 case 2: 6467 { 6468 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6469 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6470 cpu_gpr[rS(ctx->opcode)]); 6471 tcg_temp_free_i32(t0); 6472 } 6473 break; 6474 default: 6475 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6476 break; 6477 } 6478 #endif /* defined(CONFIG_USER_ONLY) */ 6479 } 6480 6481 /* TLB management - PowerPC BookE 2.06 implementation */ 6482 6483 /* tlbre */ 6484 static void gen_tlbre_booke206(DisasContext *ctx) 6485 { 6486 #if defined(CONFIG_USER_ONLY) 6487 GEN_PRIV; 6488 #else 6489 CHK_SV; 6490 gen_helper_booke206_tlbre(cpu_env); 6491 #endif /* defined(CONFIG_USER_ONLY) */ 6492 } 6493 6494 /* tlbsx - tlbsx. */ 6495 static void gen_tlbsx_booke206(DisasContext *ctx) 6496 { 6497 #if defined(CONFIG_USER_ONLY) 6498 GEN_PRIV; 6499 #else 6500 TCGv t0; 6501 6502 CHK_SV; 6503 if (rA(ctx->opcode)) { 6504 t0 = tcg_temp_new(); 6505 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6506 } else { 6507 t0 = tcg_const_tl(0); 6508 } 6509 6510 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6511 gen_helper_booke206_tlbsx(cpu_env, t0); 6512 tcg_temp_free(t0); 6513 #endif /* defined(CONFIG_USER_ONLY) */ 6514 } 6515 6516 /* tlbwe */ 6517 static void gen_tlbwe_booke206(DisasContext *ctx) 6518 { 6519 #if defined(CONFIG_USER_ONLY) 6520 GEN_PRIV; 6521 #else 6522 CHK_SV; 6523 gen_helper_booke206_tlbwe(cpu_env); 6524 #endif /* defined(CONFIG_USER_ONLY) */ 6525 } 6526 6527 static void gen_tlbivax_booke206(DisasContext *ctx) 6528 { 6529 #if defined(CONFIG_USER_ONLY) 6530 GEN_PRIV; 6531 #else 6532 TCGv t0; 6533 6534 CHK_SV; 6535 t0 = tcg_temp_new(); 6536 gen_addr_reg_index(ctx, t0); 6537 gen_helper_booke206_tlbivax(cpu_env, t0); 6538 tcg_temp_free(t0); 6539 #endif /* defined(CONFIG_USER_ONLY) */ 6540 } 6541 6542 static void gen_tlbilx_booke206(DisasContext *ctx) 6543 { 6544 #if defined(CONFIG_USER_ONLY) 6545 GEN_PRIV; 6546 #else 6547 TCGv t0; 6548 6549 CHK_SV; 6550 t0 = tcg_temp_new(); 6551 gen_addr_reg_index(ctx, t0); 6552 6553 switch ((ctx->opcode >> 21) & 0x3) { 6554 case 0: 6555 gen_helper_booke206_tlbilx0(cpu_env, t0); 6556 break; 6557 case 1: 6558 gen_helper_booke206_tlbilx1(cpu_env, t0); 6559 break; 6560 case 3: 6561 gen_helper_booke206_tlbilx3(cpu_env, t0); 6562 break; 6563 default: 6564 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6565 break; 6566 } 6567 6568 tcg_temp_free(t0); 6569 #endif /* defined(CONFIG_USER_ONLY) */ 6570 } 6571 6572 6573 /* wrtee */ 6574 static void gen_wrtee(DisasContext *ctx) 6575 { 6576 #if defined(CONFIG_USER_ONLY) 6577 GEN_PRIV; 6578 #else 6579 TCGv t0; 6580 6581 CHK_SV; 6582 t0 = tcg_temp_new(); 6583 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6584 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6585 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6586 tcg_temp_free(t0); 6587 /* 6588 * Stop translation to have a chance to raise an exception if we 6589 * just set msr_ee to 1 6590 */ 6591 gen_stop_exception(ctx); 6592 #endif /* defined(CONFIG_USER_ONLY) */ 6593 } 6594 6595 /* wrteei */ 6596 static void gen_wrteei(DisasContext *ctx) 6597 { 6598 #if defined(CONFIG_USER_ONLY) 6599 GEN_PRIV; 6600 #else 6601 CHK_SV; 6602 if (ctx->opcode & 0x00008000) { 6603 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6604 /* Stop translation to have a chance to raise an exception */ 6605 gen_stop_exception(ctx); 6606 } else { 6607 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6608 } 6609 #endif /* defined(CONFIG_USER_ONLY) */ 6610 } 6611 6612 /* PowerPC 440 specific instructions */ 6613 6614 /* dlmzb */ 6615 static void gen_dlmzb(DisasContext *ctx) 6616 { 6617 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6618 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6619 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6620 tcg_temp_free_i32(t0); 6621 } 6622 6623 /* mbar replaces eieio on 440 */ 6624 static void gen_mbar(DisasContext *ctx) 6625 { 6626 /* interpreted as no-op */ 6627 } 6628 6629 /* msync replaces sync on 440 */ 6630 static void gen_msync_4xx(DisasContext *ctx) 6631 { 6632 /* Only e500 seems to treat reserved bits as invalid */ 6633 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6634 (ctx->opcode & 0x03FFF801)) { 6635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6636 } 6637 /* otherwise interpreted as no-op */ 6638 } 6639 6640 /* icbt */ 6641 static void gen_icbt_440(DisasContext *ctx) 6642 { 6643 /* 6644 * interpreted as no-op 6645 * XXX: specification say this is treated as a load by the MMU but 6646 * does not generate any exception 6647 */ 6648 } 6649 6650 /* Embedded.Processor Control */ 6651 6652 static void gen_msgclr(DisasContext *ctx) 6653 { 6654 #if defined(CONFIG_USER_ONLY) 6655 GEN_PRIV; 6656 #else 6657 CHK_HV; 6658 if (is_book3s_arch2x(ctx)) { 6659 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6660 } else { 6661 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6662 } 6663 #endif /* defined(CONFIG_USER_ONLY) */ 6664 } 6665 6666 static void gen_msgsnd(DisasContext *ctx) 6667 { 6668 #if defined(CONFIG_USER_ONLY) 6669 GEN_PRIV; 6670 #else 6671 CHK_HV; 6672 if (is_book3s_arch2x(ctx)) { 6673 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6674 } else { 6675 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6676 } 6677 #endif /* defined(CONFIG_USER_ONLY) */ 6678 } 6679 6680 #if defined(TARGET_PPC64) 6681 static void gen_msgclrp(DisasContext *ctx) 6682 { 6683 #if defined(CONFIG_USER_ONLY) 6684 GEN_PRIV; 6685 #else 6686 CHK_SV; 6687 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6688 #endif /* defined(CONFIG_USER_ONLY) */ 6689 } 6690 6691 static void gen_msgsndp(DisasContext *ctx) 6692 { 6693 #if defined(CONFIG_USER_ONLY) 6694 GEN_PRIV; 6695 #else 6696 CHK_SV; 6697 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6698 #endif /* defined(CONFIG_USER_ONLY) */ 6699 } 6700 #endif 6701 6702 static void gen_msgsync(DisasContext *ctx) 6703 { 6704 #if defined(CONFIG_USER_ONLY) 6705 GEN_PRIV; 6706 #else 6707 CHK_HV; 6708 #endif /* defined(CONFIG_USER_ONLY) */ 6709 /* interpreted as no-op */ 6710 } 6711 6712 #if defined(TARGET_PPC64) 6713 static void gen_maddld(DisasContext *ctx) 6714 { 6715 TCGv_i64 t1 = tcg_temp_new_i64(); 6716 6717 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6718 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6719 tcg_temp_free_i64(t1); 6720 } 6721 6722 /* maddhd maddhdu */ 6723 static void gen_maddhd_maddhdu(DisasContext *ctx) 6724 { 6725 TCGv_i64 lo = tcg_temp_new_i64(); 6726 TCGv_i64 hi = tcg_temp_new_i64(); 6727 TCGv_i64 t1 = tcg_temp_new_i64(); 6728 6729 if (Rc(ctx->opcode)) { 6730 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6731 cpu_gpr[rB(ctx->opcode)]); 6732 tcg_gen_movi_i64(t1, 0); 6733 } else { 6734 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6735 cpu_gpr[rB(ctx->opcode)]); 6736 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6737 } 6738 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6739 cpu_gpr[rC(ctx->opcode)], t1); 6740 tcg_temp_free_i64(lo); 6741 tcg_temp_free_i64(hi); 6742 tcg_temp_free_i64(t1); 6743 } 6744 #endif /* defined(TARGET_PPC64) */ 6745 6746 static void gen_tbegin(DisasContext *ctx) 6747 { 6748 if (unlikely(!ctx->tm_enabled)) { 6749 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6750 return; 6751 } 6752 gen_helper_tbegin(cpu_env); 6753 } 6754 6755 #define GEN_TM_NOOP(name) \ 6756 static inline void gen_##name(DisasContext *ctx) \ 6757 { \ 6758 if (unlikely(!ctx->tm_enabled)) { \ 6759 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6760 return; \ 6761 } \ 6762 /* \ 6763 * Because tbegin always fails in QEMU, these user \ 6764 * space instructions all have a simple implementation: \ 6765 * \ 6766 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6767 * = 0b0 || 0b00 || 0b0 \ 6768 */ \ 6769 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6770 } 6771 6772 GEN_TM_NOOP(tend); 6773 GEN_TM_NOOP(tabort); 6774 GEN_TM_NOOP(tabortwc); 6775 GEN_TM_NOOP(tabortwci); 6776 GEN_TM_NOOP(tabortdc); 6777 GEN_TM_NOOP(tabortdci); 6778 GEN_TM_NOOP(tsr); 6779 6780 static inline void gen_cp_abort(DisasContext *ctx) 6781 { 6782 /* Do Nothing */ 6783 } 6784 6785 #define GEN_CP_PASTE_NOOP(name) \ 6786 static inline void gen_##name(DisasContext *ctx) \ 6787 { \ 6788 /* \ 6789 * Generate invalid exception until we have an \ 6790 * implementation of the copy paste facility \ 6791 */ \ 6792 gen_invalid(ctx); \ 6793 } 6794 6795 GEN_CP_PASTE_NOOP(copy) 6796 GEN_CP_PASTE_NOOP(paste) 6797 6798 static void gen_tcheck(DisasContext *ctx) 6799 { 6800 if (unlikely(!ctx->tm_enabled)) { 6801 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6802 return; 6803 } 6804 /* 6805 * Because tbegin always fails, the tcheck implementation is 6806 * simple: 6807 * 6808 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6809 * = 0b1 || 0b00 || 0b0 6810 */ 6811 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6812 } 6813 6814 #if defined(CONFIG_USER_ONLY) 6815 #define GEN_TM_PRIV_NOOP(name) \ 6816 static inline void gen_##name(DisasContext *ctx) \ 6817 { \ 6818 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6819 } 6820 6821 #else 6822 6823 #define GEN_TM_PRIV_NOOP(name) \ 6824 static inline void gen_##name(DisasContext *ctx) \ 6825 { \ 6826 CHK_SV; \ 6827 if (unlikely(!ctx->tm_enabled)) { \ 6828 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6829 return; \ 6830 } \ 6831 /* \ 6832 * Because tbegin always fails, the implementation is \ 6833 * simple: \ 6834 * \ 6835 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6836 * = 0b0 || 0b00 | 0b0 \ 6837 */ \ 6838 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6839 } 6840 6841 #endif 6842 6843 GEN_TM_PRIV_NOOP(treclaim); 6844 GEN_TM_PRIV_NOOP(trechkpt); 6845 6846 static inline void get_fpr(TCGv_i64 dst, int regno) 6847 { 6848 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6849 } 6850 6851 static inline void set_fpr(int regno, TCGv_i64 src) 6852 { 6853 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6854 } 6855 6856 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6857 { 6858 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6859 } 6860 6861 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6862 { 6863 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6864 } 6865 6866 #include "translate/fp-impl.inc.c" 6867 6868 #include "translate/vmx-impl.inc.c" 6869 6870 #include "translate/vsx-impl.inc.c" 6871 6872 #include "translate/dfp-impl.inc.c" 6873 6874 #include "translate/spe-impl.inc.c" 6875 6876 /* Handles lfdp, lxsd, lxssp */ 6877 static void gen_dform39(DisasContext *ctx) 6878 { 6879 switch (ctx->opcode & 0x3) { 6880 case 0: /* lfdp */ 6881 if (ctx->insns_flags2 & PPC2_ISA205) { 6882 return gen_lfdp(ctx); 6883 } 6884 break; 6885 case 2: /* lxsd */ 6886 if (ctx->insns_flags2 & PPC2_ISA300) { 6887 return gen_lxsd(ctx); 6888 } 6889 break; 6890 case 3: /* lxssp */ 6891 if (ctx->insns_flags2 & PPC2_ISA300) { 6892 return gen_lxssp(ctx); 6893 } 6894 break; 6895 } 6896 return gen_invalid(ctx); 6897 } 6898 6899 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6900 static void gen_dform3D(DisasContext *ctx) 6901 { 6902 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6903 switch (ctx->opcode & 0x7) { 6904 case 1: /* lxv */ 6905 if (ctx->insns_flags2 & PPC2_ISA300) { 6906 return gen_lxv(ctx); 6907 } 6908 break; 6909 case 5: /* stxv */ 6910 if (ctx->insns_flags2 & PPC2_ISA300) { 6911 return gen_stxv(ctx); 6912 } 6913 break; 6914 } 6915 } else { /* DS-FORM */ 6916 switch (ctx->opcode & 0x3) { 6917 case 0: /* stfdp */ 6918 if (ctx->insns_flags2 & PPC2_ISA205) { 6919 return gen_stfdp(ctx); 6920 } 6921 break; 6922 case 2: /* stxsd */ 6923 if (ctx->insns_flags2 & PPC2_ISA300) { 6924 return gen_stxsd(ctx); 6925 } 6926 break; 6927 case 3: /* stxssp */ 6928 if (ctx->insns_flags2 & PPC2_ISA300) { 6929 return gen_stxssp(ctx); 6930 } 6931 break; 6932 } 6933 } 6934 return gen_invalid(ctx); 6935 } 6936 6937 static opcode_t opcodes[] = { 6938 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6939 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6940 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6941 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6942 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6943 #if defined(TARGET_PPC64) 6944 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6945 #endif 6946 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6947 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6948 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6949 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6950 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6951 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6952 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6953 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6954 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6955 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6956 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6957 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6958 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6959 #if defined(TARGET_PPC64) 6960 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6961 #endif 6962 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6963 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6964 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6965 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6966 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6967 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6968 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 6969 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6970 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6971 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6972 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6973 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6974 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6975 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6976 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6977 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6978 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6979 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6980 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6981 #if defined(TARGET_PPC64) 6982 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6983 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6984 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6985 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6986 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6987 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6988 #endif 6989 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6990 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6991 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6992 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6993 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6994 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6995 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6996 #if defined(TARGET_PPC64) 6997 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6998 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6999 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7000 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7001 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7002 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7003 PPC_NONE, PPC2_ISA300), 7004 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7005 PPC_NONE, PPC2_ISA300), 7006 #endif 7007 #if defined(TARGET_PPC64) 7008 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7009 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7010 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7011 #endif 7012 /* handles lfdp, lxsd, lxssp */ 7013 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7014 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7015 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7016 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7017 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7018 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7019 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7020 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7021 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7022 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7023 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7024 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7025 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7026 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7027 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7028 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7029 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7030 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7031 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7032 #if defined(TARGET_PPC64) 7033 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7034 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7035 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7036 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7037 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7038 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7039 #endif 7040 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7041 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7042 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7043 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7044 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7045 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7046 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7047 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7048 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7049 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7050 #if defined(TARGET_PPC64) 7051 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7052 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7053 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7054 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7055 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7056 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7057 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7058 #endif 7059 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 7060 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7061 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7062 #if defined(TARGET_PPC64) 7063 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7064 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7065 #endif 7066 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7067 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7068 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7069 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7070 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7071 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7072 #if defined(TARGET_PPC64) 7073 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7074 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7075 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7076 #endif 7077 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7078 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7079 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 7080 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7081 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7082 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 7083 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7084 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 7085 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7086 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 7087 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7088 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7089 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 7090 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7091 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 7092 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7093 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7094 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 7095 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7096 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7097 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7098 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7099 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7100 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7101 #if defined(TARGET_PPC64) 7102 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7103 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7104 PPC_SEGMENT_64B), 7105 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7106 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7107 PPC_SEGMENT_64B), 7108 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7109 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7110 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7111 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7112 #endif 7113 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7114 /* 7115 * XXX Those instructions will need to be handled differently for 7116 * different ISA versions 7117 */ 7118 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7119 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7120 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7121 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7122 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7123 #if defined(TARGET_PPC64) 7124 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7125 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7126 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 7127 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7128 #endif 7129 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7130 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7131 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7132 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7133 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7134 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7135 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7136 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7137 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7138 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7139 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7140 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7141 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7142 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7143 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7144 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7145 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7146 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7147 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7148 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7149 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7150 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7151 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7152 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7153 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7154 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7155 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7156 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7157 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7158 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7159 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7160 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7161 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7162 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7163 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7164 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7165 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7166 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7167 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7168 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7169 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7170 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7171 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7172 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7173 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7174 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7175 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7176 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7177 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7178 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7179 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7180 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7181 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7182 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7183 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7184 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7185 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7186 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7187 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7188 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7189 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7190 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7191 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7192 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7193 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7194 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7195 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7196 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7197 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7198 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7199 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7200 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7201 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7202 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7203 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7204 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7205 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7206 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7207 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7208 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7209 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7210 PPC_NONE, PPC2_BOOKE206), 7211 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7212 PPC_NONE, PPC2_BOOKE206), 7213 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7214 PPC_NONE, PPC2_BOOKE206), 7215 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7216 PPC_NONE, PPC2_BOOKE206), 7217 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7218 PPC_NONE, PPC2_BOOKE206), 7219 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7220 PPC_NONE, PPC2_PRCNTL), 7221 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7222 PPC_NONE, PPC2_PRCNTL), 7223 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 7224 PPC_NONE, PPC2_PRCNTL), 7225 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7226 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7227 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7228 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7229 PPC_BOOKE, PPC2_BOOKE206), 7230 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7231 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7232 PPC_BOOKE, PPC2_BOOKE206), 7233 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 7234 PPC_440_SPEC), 7235 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7236 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7237 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7238 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7239 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7240 #if defined(TARGET_PPC64) 7241 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7242 PPC2_ISA300), 7243 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7244 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 7245 PPC_NONE, PPC2_ISA207S), 7246 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 7247 PPC_NONE, PPC2_ISA207S), 7248 #endif 7249 7250 #undef GEN_INT_ARITH_ADD 7251 #undef GEN_INT_ARITH_ADD_CONST 7252 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7253 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7254 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7255 add_ca, compute_ca, compute_ov) \ 7256 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7257 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7258 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7259 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7260 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7261 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7262 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7263 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7264 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 7265 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7266 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7267 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7268 7269 #undef GEN_INT_ARITH_DIVW 7270 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7271 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7272 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7273 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7274 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7275 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7276 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7277 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7278 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7279 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7280 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7281 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7282 7283 #if defined(TARGET_PPC64) 7284 #undef GEN_INT_ARITH_DIVD 7285 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7286 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7287 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7288 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7289 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7290 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7291 7292 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7293 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7294 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7295 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7296 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7297 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7298 7299 #undef GEN_INT_ARITH_MUL_HELPER 7300 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7301 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7302 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7303 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7304 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7305 #endif 7306 7307 #undef GEN_INT_ARITH_SUBF 7308 #undef GEN_INT_ARITH_SUBF_CONST 7309 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7310 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7311 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7312 add_ca, compute_ca, compute_ov) \ 7313 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7314 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7315 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7316 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7317 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7318 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7319 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7320 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7321 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7322 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7323 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7324 7325 #undef GEN_LOGICAL1 7326 #undef GEN_LOGICAL2 7327 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7328 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7329 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7330 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7331 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7332 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7333 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7334 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7335 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7336 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7337 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7338 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7339 #if defined(TARGET_PPC64) 7340 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7341 #endif 7342 7343 #if defined(TARGET_PPC64) 7344 #undef GEN_PPC64_R2 7345 #undef GEN_PPC64_R4 7346 #define GEN_PPC64_R2(name, opc1, opc2) \ 7347 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7348 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7349 PPC_64B) 7350 #define GEN_PPC64_R4(name, opc1, opc2) \ 7351 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7352 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7353 PPC_64B), \ 7354 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7355 PPC_64B), \ 7356 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7357 PPC_64B) 7358 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7359 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7360 GEN_PPC64_R4(rldic, 0x1E, 0x04), 7361 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7362 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7363 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7364 #endif 7365 7366 #undef GEN_LD 7367 #undef GEN_LDU 7368 #undef GEN_LDUX 7369 #undef GEN_LDX_E 7370 #undef GEN_LDS 7371 #define GEN_LD(name, ldop, opc, type) \ 7372 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7373 #define GEN_LDU(name, ldop, opc, type) \ 7374 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7375 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7376 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7377 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7378 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7379 #define GEN_LDS(name, ldop, op, type) \ 7380 GEN_LD(name, ldop, op | 0x20, type) \ 7381 GEN_LDU(name, ldop, op | 0x21, type) \ 7382 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7383 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7384 7385 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7386 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7387 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7388 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7389 #if defined(TARGET_PPC64) 7390 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7391 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7392 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7393 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7394 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7395 7396 /* HV/P7 and later only */ 7397 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7398 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7399 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7400 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7401 #endif 7402 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7403 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7404 7405 /* External PID based load */ 7406 #undef GEN_LDEPX 7407 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 7408 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7409 0x00000001, PPC_NONE, PPC2_BOOKE206), 7410 7411 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 7412 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 7413 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 7414 #if defined(TARGET_PPC64) 7415 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 7416 #endif 7417 7418 #undef GEN_ST 7419 #undef GEN_STU 7420 #undef GEN_STUX 7421 #undef GEN_STX_E 7422 #undef GEN_STS 7423 #define GEN_ST(name, stop, opc, type) \ 7424 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7425 #define GEN_STU(name, stop, opc, type) \ 7426 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7427 #define GEN_STUX(name, stop, opc2, opc3, type) \ 7428 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7429 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 7430 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7431 #define GEN_STS(name, stop, op, type) \ 7432 GEN_ST(name, stop, op | 0x20, type) \ 7433 GEN_STU(name, stop, op | 0x21, type) \ 7434 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7435 GEN_STX(name, stop, 0x17, op | 0x00, type) 7436 7437 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7438 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7439 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7440 #if defined(TARGET_PPC64) 7441 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7442 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7443 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7444 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7445 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7446 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7447 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7448 #endif 7449 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7450 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7451 7452 #undef GEN_STEPX 7453 #define GEN_STEPX(name, ldop, opc2, opc3) \ 7454 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7455 0x00000001, PPC_NONE, PPC2_BOOKE206), 7456 7457 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 7458 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 7459 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 7460 #if defined(TARGET_PPC64) 7461 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 7462 #endif 7463 7464 #undef GEN_CRLOGIC 7465 #define GEN_CRLOGIC(name, tcg_op, opc) \ 7466 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7467 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7468 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7469 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7470 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7471 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7472 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7473 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7474 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7475 7476 #undef GEN_MAC_HANDLER 7477 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7478 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7479 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7480 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7481 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7482 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7483 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7484 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7485 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7486 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7487 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7488 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7489 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7490 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7491 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7492 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7493 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7494 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7495 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7496 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7497 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7498 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7499 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7500 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7501 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7502 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7503 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7504 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7505 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7506 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7507 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7508 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7509 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7510 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7511 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7512 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7513 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7514 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7515 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7516 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7517 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7518 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7519 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7520 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7521 7522 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7523 PPC_NONE, PPC2_TM), 7524 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7525 PPC_NONE, PPC2_TM), 7526 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7527 PPC_NONE, PPC2_TM), 7528 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7529 PPC_NONE, PPC2_TM), 7530 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7531 PPC_NONE, PPC2_TM), 7532 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7533 PPC_NONE, PPC2_TM), 7534 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7535 PPC_NONE, PPC2_TM), 7536 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7537 PPC_NONE, PPC2_TM), 7538 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7539 PPC_NONE, PPC2_TM), 7540 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7541 PPC_NONE, PPC2_TM), 7542 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7543 PPC_NONE, PPC2_TM), 7544 7545 #include "translate/fp-ops.inc.c" 7546 7547 #include "translate/vmx-ops.inc.c" 7548 7549 #include "translate/vsx-ops.inc.c" 7550 7551 #include "translate/dfp-ops.inc.c" 7552 7553 #include "translate/spe-ops.inc.c" 7554 }; 7555 7556 #include "helper_regs.h" 7557 #include "translate_init.inc.c" 7558 7559 /*****************************************************************************/ 7560 /* Misc PowerPC helpers */ 7561 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7562 { 7563 #define RGPL 4 7564 #define RFPL 4 7565 7566 PowerPCCPU *cpu = POWERPC_CPU(cs); 7567 CPUPPCState *env = &cpu->env; 7568 int i; 7569 7570 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7571 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7572 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7573 cs->cpu_index); 7574 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7575 TARGET_FMT_lx " iidx %d didx %d\n", 7576 env->msr, env->spr[SPR_HID0], 7577 env->hflags, env->immu_idx, env->dmmu_idx); 7578 #if !defined(NO_TIMER_DUMP) 7579 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7580 #if !defined(CONFIG_USER_ONLY) 7581 " DECR " TARGET_FMT_lu 7582 #endif 7583 "\n", 7584 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7585 #if !defined(CONFIG_USER_ONLY) 7586 , cpu_ppc_load_decr(env) 7587 #endif 7588 ); 7589 #endif 7590 for (i = 0; i < 32; i++) { 7591 if ((i & (RGPL - 1)) == 0) { 7592 qemu_fprintf(f, "GPR%02d", i); 7593 } 7594 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7595 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7596 qemu_fprintf(f, "\n"); 7597 } 7598 } 7599 qemu_fprintf(f, "CR "); 7600 for (i = 0; i < 8; i++) 7601 qemu_fprintf(f, "%01x", env->crf[i]); 7602 qemu_fprintf(f, " ["); 7603 for (i = 0; i < 8; i++) { 7604 char a = '-'; 7605 if (env->crf[i] & 0x08) { 7606 a = 'L'; 7607 } else if (env->crf[i] & 0x04) { 7608 a = 'G'; 7609 } else if (env->crf[i] & 0x02) { 7610 a = 'E'; 7611 } 7612 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7613 } 7614 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7615 env->reserve_addr); 7616 7617 if (flags & CPU_DUMP_FPU) { 7618 for (i = 0; i < 32; i++) { 7619 if ((i & (RFPL - 1)) == 0) { 7620 qemu_fprintf(f, "FPR%02d", i); 7621 } 7622 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7623 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7624 qemu_fprintf(f, "\n"); 7625 } 7626 } 7627 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7628 } 7629 7630 #if !defined(CONFIG_USER_ONLY) 7631 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7632 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7633 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7634 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7635 7636 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7637 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7638 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7639 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7640 7641 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7642 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7643 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7644 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7645 7646 #if defined(TARGET_PPC64) 7647 if (env->excp_model == POWERPC_EXCP_POWER7 || 7648 env->excp_model == POWERPC_EXCP_POWER8 || 7649 env->excp_model == POWERPC_EXCP_POWER9) { 7650 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7651 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7652 } 7653 #endif 7654 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7655 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7656 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7657 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7658 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7659 7660 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7661 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7662 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7663 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7664 7665 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7666 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7667 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7668 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7669 7670 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7671 " EPR " TARGET_FMT_lx "\n", 7672 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7673 env->spr[SPR_BOOKE_EPR]); 7674 7675 /* FSL-specific */ 7676 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7677 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7678 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7679 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7680 7681 /* 7682 * IVORs are left out as they are large and do not change often -- 7683 * they can be read with "p $ivor0", "p $ivor1", etc. 7684 */ 7685 } 7686 7687 #if defined(TARGET_PPC64) 7688 if (env->flags & POWERPC_FLAG_CFAR) { 7689 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7690 } 7691 #endif 7692 7693 if (env->spr_cb[SPR_LPCR].name) { 7694 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7695 } 7696 7697 switch (env->mmu_model) { 7698 case POWERPC_MMU_32B: 7699 case POWERPC_MMU_601: 7700 case POWERPC_MMU_SOFT_6xx: 7701 case POWERPC_MMU_SOFT_74xx: 7702 #if defined(TARGET_PPC64) 7703 case POWERPC_MMU_64B: 7704 case POWERPC_MMU_2_03: 7705 case POWERPC_MMU_2_06: 7706 case POWERPC_MMU_2_07: 7707 case POWERPC_MMU_3_00: 7708 #endif 7709 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7710 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7711 } 7712 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7713 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7714 } 7715 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7716 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7717 break; 7718 case POWERPC_MMU_BOOKE206: 7719 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7720 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7721 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7722 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7723 7724 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7725 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7726 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7727 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7728 7729 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7730 " TLB1CFG " TARGET_FMT_lx "\n", 7731 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7732 env->spr[SPR_BOOKE_TLB1CFG]); 7733 break; 7734 default: 7735 break; 7736 } 7737 #endif 7738 7739 #undef RGPL 7740 #undef RFPL 7741 } 7742 7743 void ppc_cpu_dump_statistics(CPUState *cs, int flags) 7744 { 7745 #if defined(DO_PPC_STATISTICS) 7746 PowerPCCPU *cpu = POWERPC_CPU(cs); 7747 opc_handler_t **t1, **t2, **t3, *handler; 7748 int op1, op2, op3; 7749 7750 t1 = cpu->env.opcodes; 7751 for (op1 = 0; op1 < 64; op1++) { 7752 handler = t1[op1]; 7753 if (is_indirect_opcode(handler)) { 7754 t2 = ind_table(handler); 7755 for (op2 = 0; op2 < 32; op2++) { 7756 handler = t2[op2]; 7757 if (is_indirect_opcode(handler)) { 7758 t3 = ind_table(handler); 7759 for (op3 = 0; op3 < 32; op3++) { 7760 handler = t3[op3]; 7761 if (handler->count == 0) { 7762 continue; 7763 } 7764 qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 7765 "%016" PRIx64 " %" PRId64 "\n", 7766 op1, op2, op3, op1, (op3 << 5) | op2, 7767 handler->oname, 7768 handler->count, handler->count); 7769 } 7770 } else { 7771 if (handler->count == 0) { 7772 continue; 7773 } 7774 qemu_printf("%02x %02x (%02x %04d) %16s: " 7775 "%016" PRIx64 " %" PRId64 "\n", 7776 op1, op2, op1, op2, handler->oname, 7777 handler->count, handler->count); 7778 } 7779 } 7780 } else { 7781 if (handler->count == 0) { 7782 continue; 7783 } 7784 qemu_printf("%02x (%02x ) %16s: %016" PRIx64 7785 " %" PRId64 "\n", 7786 op1, op1, handler->oname, 7787 handler->count, handler->count); 7788 } 7789 } 7790 #endif 7791 } 7792 7793 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7794 { 7795 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7796 CPUPPCState *env = cs->env_ptr; 7797 int bound; 7798 7799 ctx->exception = POWERPC_EXCP_NONE; 7800 ctx->spr_cb = env->spr_cb; 7801 ctx->pr = msr_pr; 7802 ctx->mem_idx = env->dmmu_idx; 7803 ctx->dr = msr_dr; 7804 #if !defined(CONFIG_USER_ONLY) 7805 ctx->hv = msr_hv || !env->has_hv_mode; 7806 #endif 7807 ctx->insns_flags = env->insns_flags; 7808 ctx->insns_flags2 = env->insns_flags2; 7809 ctx->access_type = -1; 7810 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7811 ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7812 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7813 ctx->flags = env->flags; 7814 #if defined(TARGET_PPC64) 7815 ctx->sf_mode = msr_is_64bit(env, env->msr); 7816 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7817 #endif 7818 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7819 || env->mmu_model == POWERPC_MMU_601 7820 || (env->mmu_model & POWERPC_MMU_64B); 7821 7822 ctx->fpu_enabled = !!msr_fp; 7823 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { 7824 ctx->spe_enabled = !!msr_spe; 7825 } else { 7826 ctx->spe_enabled = false; 7827 } 7828 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { 7829 ctx->altivec_enabled = !!msr_vr; 7830 } else { 7831 ctx->altivec_enabled = false; 7832 } 7833 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7834 ctx->vsx_enabled = !!msr_vsx; 7835 } else { 7836 ctx->vsx_enabled = false; 7837 } 7838 #if defined(TARGET_PPC64) 7839 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7840 ctx->tm_enabled = !!msr_tm; 7841 } else { 7842 ctx->tm_enabled = false; 7843 } 7844 #endif 7845 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7846 if ((env->flags & POWERPC_FLAG_SE) && msr_se) { 7847 ctx->singlestep_enabled = CPU_SINGLE_STEP; 7848 } else { 7849 ctx->singlestep_enabled = 0; 7850 } 7851 if ((env->flags & POWERPC_FLAG_BE) && msr_be) { 7852 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7853 } 7854 if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 7855 ctx->singlestep_enabled = 0; 7856 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 7857 if (dbcr0 & DBCR0_ICMP) { 7858 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7859 } 7860 if (dbcr0 & DBCR0_BRT) { 7861 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7862 } 7863 7864 } 7865 if (unlikely(ctx->base.singlestep_enabled)) { 7866 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7867 } 7868 #if defined(DO_SINGLE_STEP) && 0 7869 /* Single step trace mode */ 7870 msr_se = 1; 7871 #endif 7872 7873 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7874 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7875 } 7876 7877 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7878 { 7879 } 7880 7881 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7882 { 7883 tcg_gen_insn_start(dcbase->pc_next); 7884 } 7885 7886 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7887 const CPUBreakpoint *bp) 7888 { 7889 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7890 7891 gen_debug_exception(ctx); 7892 dcbase->is_jmp = DISAS_NORETURN; 7893 /* 7894 * The address covered by the breakpoint must be included in 7895 * [tb->pc, tb->pc + tb->size) in order to for it to be properly 7896 * cleared -- thus we increment the PC here so that the logic 7897 * setting tb->size below does the right thing. 7898 */ 7899 ctx->base.pc_next += 4; 7900 return true; 7901 } 7902 7903 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7904 { 7905 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7906 PowerPCCPU *cpu = POWERPC_CPU(cs); 7907 CPUPPCState *env = cs->env_ptr; 7908 opc_handler_t **table, *handler; 7909 7910 LOG_DISAS("----------------\n"); 7911 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7912 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7913 7914 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 7915 need_byteswap(ctx)); 7916 7917 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7918 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7919 opc3(ctx->opcode), opc4(ctx->opcode), 7920 ctx->le_mode ? "little" : "big"); 7921 ctx->base.pc_next += 4; 7922 table = cpu->opcodes; 7923 handler = table[opc1(ctx->opcode)]; 7924 if (is_indirect_opcode(handler)) { 7925 table = ind_table(handler); 7926 handler = table[opc2(ctx->opcode)]; 7927 if (is_indirect_opcode(handler)) { 7928 table = ind_table(handler); 7929 handler = table[opc3(ctx->opcode)]; 7930 if (is_indirect_opcode(handler)) { 7931 table = ind_table(handler); 7932 handler = table[opc4(ctx->opcode)]; 7933 } 7934 } 7935 } 7936 /* Is opcode *REALLY* valid ? */ 7937 if (unlikely(handler->handler == &gen_invalid)) { 7938 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7939 "%02x - %02x - %02x - %02x (%08x) " 7940 TARGET_FMT_lx " %d\n", 7941 opc1(ctx->opcode), opc2(ctx->opcode), 7942 opc3(ctx->opcode), opc4(ctx->opcode), 7943 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7944 } else { 7945 uint32_t inval; 7946 7947 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7948 && Rc(ctx->opcode))) { 7949 inval = handler->inval2; 7950 } else { 7951 inval = handler->inval1; 7952 } 7953 7954 if (unlikely((ctx->opcode & inval) != 0)) { 7955 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7956 "%02x - %02x - %02x - %02x (%08x) " 7957 TARGET_FMT_lx "\n", ctx->opcode & inval, 7958 opc1(ctx->opcode), opc2(ctx->opcode), 7959 opc3(ctx->opcode), opc4(ctx->opcode), 7960 ctx->opcode, ctx->base.pc_next - 4); 7961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7962 ctx->base.is_jmp = DISAS_NORETURN; 7963 return; 7964 } 7965 } 7966 (*(handler->handler))(ctx); 7967 #if defined(DO_PPC_STATISTICS) 7968 handler->count++; 7969 #endif 7970 /* Check trace mode exceptions */ 7971 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7972 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7973 ctx->exception != POWERPC_SYSCALL && 7974 ctx->exception != POWERPC_EXCP_TRAP && 7975 ctx->exception != POWERPC_EXCP_BRANCH)) { 7976 uint32_t excp = gen_prep_dbgex(ctx); 7977 gen_exception_nip(ctx, excp, ctx->base.pc_next); 7978 } 7979 7980 if (tcg_check_temp_count()) { 7981 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7982 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7983 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7984 } 7985 7986 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7987 DISAS_NEXT : DISAS_NORETURN; 7988 } 7989 7990 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7991 { 7992 DisasContext *ctx = container_of(dcbase, DisasContext, base); 7993 7994 if (ctx->exception == POWERPC_EXCP_NONE) { 7995 gen_goto_tb(ctx, 0, ctx->base.pc_next); 7996 } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7997 if (unlikely(ctx->base.singlestep_enabled)) { 7998 gen_debug_exception(ctx); 7999 } 8000 /* Generate the return instruction */ 8001 tcg_gen_exit_tb(NULL, 0); 8002 } 8003 } 8004 8005 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8006 { 8007 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8008 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8009 } 8010 8011 static const TranslatorOps ppc_tr_ops = { 8012 .init_disas_context = ppc_tr_init_disas_context, 8013 .tb_start = ppc_tr_tb_start, 8014 .insn_start = ppc_tr_insn_start, 8015 .breakpoint_check = ppc_tr_breakpoint_check, 8016 .translate_insn = ppc_tr_translate_insn, 8017 .tb_stop = ppc_tr_tb_stop, 8018 .disas_log = ppc_tr_disas_log, 8019 }; 8020 8021 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8022 { 8023 DisasContext ctx; 8024 8025 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8026 } 8027 8028 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8029 target_ulong *data) 8030 { 8031 env->nip = data[0]; 8032 } 8033