1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "exec/exec-all.h" 25 #include "tcg/tcg-op.h" 26 #include "tcg/tcg-op-gvec.h" 27 #include "qemu/host-utils.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "exec/translator.h" 33 #include "exec/log.h" 34 #include "qemu/atomic128.h" 35 #include "spr_common.h" 36 #include "power8-pmu.h" 37 38 #include "qemu/qemu-print.h" 39 #include "qapi/error.h" 40 41 #define HELPER_H "helper.h" 42 #include "exec/helper-info.c.inc" 43 #undef HELPER_H 44 45 #define CPU_SINGLE_STEP 0x1 46 #define CPU_BRANCH_STEP 0x2 47 48 /* Include definitions for instructions classes and implementations flags */ 49 /* #define PPC_DEBUG_DISAS */ 50 51 #ifdef PPC_DEBUG_DISAS 52 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 53 #else 54 # define LOG_DISAS(...) do { } while (0) 55 #endif 56 /*****************************************************************************/ 57 /* Code translation helpers */ 58 59 /* global register indexes */ 60 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 61 + 10 * 4 + 22 * 5 /* SPE GPRh */ 62 + 8 * 5 /* CRF */]; 63 static TCGv cpu_gpr[32]; 64 static TCGv cpu_gprh[32]; 65 static TCGv_i32 cpu_crf[8]; 66 static TCGv cpu_nip; 67 static TCGv cpu_msr; 68 static TCGv cpu_ctr; 69 static TCGv cpu_lr; 70 #if defined(TARGET_PPC64) 71 static TCGv cpu_cfar; 72 #endif 73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 74 static TCGv cpu_reserve; 75 static TCGv cpu_reserve_length; 76 static TCGv cpu_reserve_val; 77 #if defined(TARGET_PPC64) 78 static TCGv cpu_reserve_val2; 79 #endif 80 static TCGv cpu_fpscr; 81 static TCGv_i32 cpu_access_type; 82 83 void ppc_translate_init(void) 84 { 85 int i; 86 char *p; 87 size_t cpu_reg_names_size; 88 89 p = cpu_reg_names; 90 cpu_reg_names_size = sizeof(cpu_reg_names); 91 92 for (i = 0; i < 8; i++) { 93 snprintf(p, cpu_reg_names_size, "crf%d", i); 94 cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, 95 offsetof(CPUPPCState, crf[i]), p); 96 p += 5; 97 cpu_reg_names_size -= 5; 98 } 99 100 for (i = 0; i < 32; i++) { 101 snprintf(p, cpu_reg_names_size, "r%d", i); 102 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 103 offsetof(CPUPPCState, gpr[i]), p); 104 p += (i < 10) ? 3 : 4; 105 cpu_reg_names_size -= (i < 10) ? 3 : 4; 106 snprintf(p, cpu_reg_names_size, "r%dH", i); 107 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 108 offsetof(CPUPPCState, gprh[i]), p); 109 p += (i < 10) ? 4 : 5; 110 cpu_reg_names_size -= (i < 10) ? 4 : 5; 111 } 112 113 cpu_nip = tcg_global_mem_new(tcg_env, 114 offsetof(CPUPPCState, nip), "nip"); 115 116 cpu_msr = tcg_global_mem_new(tcg_env, 117 offsetof(CPUPPCState, msr), "msr"); 118 119 cpu_ctr = tcg_global_mem_new(tcg_env, 120 offsetof(CPUPPCState, ctr), "ctr"); 121 122 cpu_lr = tcg_global_mem_new(tcg_env, 123 offsetof(CPUPPCState, lr), "lr"); 124 125 #if defined(TARGET_PPC64) 126 cpu_cfar = tcg_global_mem_new(tcg_env, 127 offsetof(CPUPPCState, cfar), "cfar"); 128 #endif 129 130 cpu_xer = tcg_global_mem_new(tcg_env, 131 offsetof(CPUPPCState, xer), "xer"); 132 cpu_so = tcg_global_mem_new(tcg_env, 133 offsetof(CPUPPCState, so), "SO"); 134 cpu_ov = tcg_global_mem_new(tcg_env, 135 offsetof(CPUPPCState, ov), "OV"); 136 cpu_ca = tcg_global_mem_new(tcg_env, 137 offsetof(CPUPPCState, ca), "CA"); 138 cpu_ov32 = tcg_global_mem_new(tcg_env, 139 offsetof(CPUPPCState, ov32), "OV32"); 140 cpu_ca32 = tcg_global_mem_new(tcg_env, 141 offsetof(CPUPPCState, ca32), "CA32"); 142 143 cpu_reserve = tcg_global_mem_new(tcg_env, 144 offsetof(CPUPPCState, reserve_addr), 145 "reserve_addr"); 146 cpu_reserve_length = tcg_global_mem_new(tcg_env, 147 offsetof(CPUPPCState, 148 reserve_length), 149 "reserve_length"); 150 cpu_reserve_val = tcg_global_mem_new(tcg_env, 151 offsetof(CPUPPCState, reserve_val), 152 "reserve_val"); 153 #if defined(TARGET_PPC64) 154 cpu_reserve_val2 = tcg_global_mem_new(tcg_env, 155 offsetof(CPUPPCState, reserve_val2), 156 "reserve_val2"); 157 #endif 158 159 cpu_fpscr = tcg_global_mem_new(tcg_env, 160 offsetof(CPUPPCState, fpscr), "fpscr"); 161 162 cpu_access_type = tcg_global_mem_new_i32(tcg_env, 163 offsetof(CPUPPCState, access_type), 164 "access_type"); 165 } 166 167 /* internal defines */ 168 struct DisasContext { 169 DisasContextBase base; 170 target_ulong cia; /* current instruction address */ 171 uint32_t opcode; 172 /* Routine used to access memory */ 173 bool pr, hv, dr, le_mode; 174 bool lazy_tlb_flush; 175 bool need_access_type; 176 int mem_idx; 177 int access_type; 178 /* Translation flags */ 179 MemOp default_tcg_memop_mask; 180 #if defined(TARGET_PPC64) 181 powerpc_excp_t excp_model; 182 bool sf_mode; 183 bool has_cfar; 184 bool has_bhrb; 185 #endif 186 bool fpu_enabled; 187 bool altivec_enabled; 188 bool vsx_enabled; 189 bool spe_enabled; 190 bool tm_enabled; 191 bool gtse; 192 bool hr; 193 bool mmcr0_pmcc0; 194 bool mmcr0_pmcc1; 195 bool mmcr0_pmcjce; 196 bool pmc_other; 197 bool pmu_insn_cnt; 198 bool bhrb_enable; 199 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 200 int singlestep_enabled; 201 uint32_t flags; 202 uint64_t insns_flags; 203 uint64_t insns_flags2; 204 }; 205 206 #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 207 #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 208 #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 209 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 210 211 /* Return true iff byteswap is needed in a scalar memop */ 212 static inline bool need_byteswap(const DisasContext *ctx) 213 { 214 #if TARGET_BIG_ENDIAN 215 return ctx->le_mode; 216 #else 217 return !ctx->le_mode; 218 #endif 219 } 220 221 /* True when active word size < size of target_long. */ 222 #ifdef TARGET_PPC64 223 # define NARROW_MODE(C) (!(C)->sf_mode) 224 #else 225 # define NARROW_MODE(C) 0 226 #endif 227 228 struct opc_handler_t { 229 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 230 uint32_t inval1; 231 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 232 uint32_t inval2; 233 /* instruction type */ 234 uint64_t type; 235 /* extended instruction type */ 236 uint64_t type2; 237 /* handler */ 238 void (*handler)(DisasContext *ctx); 239 }; 240 241 static inline bool gen_serialize(DisasContext *ctx) 242 { 243 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 244 /* Restart with exclusive lock. */ 245 gen_helper_exit_atomic(tcg_env); 246 ctx->base.is_jmp = DISAS_NORETURN; 247 return false; 248 } 249 return true; 250 } 251 252 #if !defined(CONFIG_USER_ONLY) 253 #if defined(TARGET_PPC64) 254 static inline bool gen_serialize_core(DisasContext *ctx) 255 { 256 if (ctx->flags & POWERPC_FLAG_SMT) { 257 return gen_serialize(ctx); 258 } 259 return true; 260 } 261 #endif 262 263 static inline bool gen_serialize_core_lpar(DisasContext *ctx) 264 { 265 #if defined(TARGET_PPC64) 266 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 267 return gen_serialize(ctx); 268 } 269 #endif 270 return true; 271 } 272 #endif 273 274 /* SPR load/store helpers */ 275 static inline void gen_load_spr(TCGv t, int reg) 276 { 277 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 278 } 279 280 static inline void gen_store_spr(int reg, TCGv t) 281 { 282 tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); 283 } 284 285 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 286 { 287 if (ctx->need_access_type && ctx->access_type != access_type) { 288 tcg_gen_movi_i32(cpu_access_type, access_type); 289 ctx->access_type = access_type; 290 } 291 } 292 293 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 294 { 295 if (NARROW_MODE(ctx)) { 296 nip = (uint32_t)nip; 297 } 298 tcg_gen_movi_tl(cpu_nip, nip); 299 } 300 301 static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp, 302 uint32_t error, target_ulong nip) 303 { 304 TCGv_i32 t0, t1; 305 306 gen_update_nip(ctx, nip); 307 t0 = tcg_constant_i32(excp); 308 t1 = tcg_constant_i32(error); 309 gen_helper_raise_exception_err(tcg_env, t0, t1); 310 ctx->base.is_jmp = DISAS_NORETURN; 311 } 312 313 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, 314 uint32_t error) 315 { 316 /* 317 * These are all synchronous exceptions, we set the PC back to the 318 * faulting instruction 319 */ 320 gen_exception_err_nip(ctx, excp, error, ctx->cia); 321 } 322 323 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 324 target_ulong nip) 325 { 326 TCGv_i32 t0; 327 328 gen_update_nip(ctx, nip); 329 t0 = tcg_constant_i32(excp); 330 gen_helper_raise_exception(tcg_env, t0); 331 ctx->base.is_jmp = DISAS_NORETURN; 332 } 333 334 static inline void gen_exception(DisasContext *ctx, uint32_t excp) 335 { 336 /* 337 * These are all synchronous exceptions, we set the PC back to the 338 * faulting instruction 339 */ 340 gen_exception_nip(ctx, excp, ctx->cia); 341 } 342 343 #if !defined(CONFIG_USER_ONLY) 344 static void gen_ppc_maybe_interrupt(DisasContext *ctx) 345 { 346 translator_io_start(&ctx->base); 347 gen_helper_ppc_maybe_interrupt(tcg_env); 348 } 349 #endif 350 351 /* 352 * Tells the caller what is the appropriate exception to generate and prepares 353 * SPR registers for this exception. 354 * 355 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 356 * POWERPC_EXCP_DEBUG (on BookE). 357 */ 358 static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 359 { 360 #if !defined(CONFIG_USER_ONLY) 361 if (ctx->flags & POWERPC_FLAG_DE) { 362 target_ulong dbsr = 0; 363 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 364 dbsr = DBCR0_ICMP; 365 } else { 366 /* Must have been branch */ 367 dbsr = DBCR0_BRT; 368 } 369 TCGv t0 = tcg_temp_new(); 370 gen_load_spr(t0, SPR_BOOKE_DBSR); 371 tcg_gen_ori_tl(t0, t0, dbsr); 372 gen_store_spr(SPR_BOOKE_DBSR, t0); 373 gen_helper_raise_exception(tcg_env, 374 tcg_constant_i32(POWERPC_EXCP_DEBUG)); 375 ctx->base.is_jmp = DISAS_NORETURN; 376 } else { 377 if (!rfi_type) { /* BookS does not single step rfi type instructions */ 378 TCGv t0 = tcg_temp_new(); 379 tcg_gen_movi_tl(t0, ctx->cia); 380 gen_helper_book3s_trace(tcg_env, t0); 381 ctx->base.is_jmp = DISAS_NORETURN; 382 } 383 } 384 #endif 385 } 386 387 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 388 { 389 /* Will be converted to program check if needed */ 390 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 391 } 392 393 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 394 { 395 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 396 } 397 398 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 399 { 400 /* Will be converted to program check if needed */ 401 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 402 } 403 404 /*****************************************************************************/ 405 /* SPR READ/WRITE CALLBACKS */ 406 407 void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 408 { 409 #if 0 410 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 411 printf("ERROR: try to access SPR %d !\n", sprn); 412 #endif 413 } 414 415 /* #define PPC_DUMP_SPR_ACCESSES */ 416 417 /* 418 * Generic callbacks: 419 * do nothing but store/retrieve spr value 420 */ 421 static void spr_load_dump_spr(int sprn) 422 { 423 #ifdef PPC_DUMP_SPR_ACCESSES 424 TCGv_i32 t0 = tcg_constant_i32(sprn); 425 gen_helper_load_dump_spr(tcg_env, t0); 426 #endif 427 } 428 429 void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 430 { 431 gen_load_spr(cpu_gpr[gprn], sprn); 432 spr_load_dump_spr(sprn); 433 } 434 435 static void spr_store_dump_spr(int sprn) 436 { 437 #ifdef PPC_DUMP_SPR_ACCESSES 438 TCGv_i32 t0 = tcg_constant_i32(sprn); 439 gen_helper_store_dump_spr(tcg_env, t0); 440 #endif 441 } 442 443 void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 444 { 445 gen_store_spr(sprn, cpu_gpr[gprn]); 446 spr_store_dump_spr(sprn); 447 } 448 449 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 450 { 451 #ifdef TARGET_PPC64 452 TCGv t0 = tcg_temp_new(); 453 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 454 gen_store_spr(sprn, t0); 455 spr_store_dump_spr(sprn); 456 #else 457 spr_write_generic(ctx, sprn, gprn); 458 #endif 459 } 460 461 void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 462 { 463 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 464 spr_write_generic(ctx, sprn, gprn); 465 return; 466 } 467 468 if (!gen_serialize(ctx)) { 469 return; 470 } 471 472 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), 473 cpu_gpr[gprn]); 474 spr_store_dump_spr(sprn); 475 } 476 477 void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) 478 { 479 TCGv t0; 480 481 if (!(ctx->flags & POWERPC_FLAG_SMT)) { 482 spr_write_generic32(ctx, sprn, gprn); 483 return; 484 } 485 486 if (!gen_serialize(ctx)) { 487 return; 488 } 489 490 t0 = tcg_temp_new(); 491 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 492 gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0); 493 spr_store_dump_spr(sprn); 494 } 495 496 void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn) 497 { 498 if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 499 spr_core_write_generic(ctx, sprn, gprn); 500 } else { 501 spr_write_generic(ctx, sprn, gprn); 502 } 503 } 504 505 static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 506 { 507 /* This does not implement >1 thread */ 508 TCGv t0 = tcg_temp_new(); 509 TCGv t1 = tcg_temp_new(); 510 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 511 tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 512 tcg_gen_or_tl(t1, t1, t0); 513 gen_store_spr(sprn, t1); 514 } 515 516 void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 517 { 518 if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 519 /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 520 spr_write_CTRL_ST(ctx, sprn, gprn); 521 goto out; 522 } 523 524 if (!gen_serialize(ctx)) { 525 return; 526 } 527 528 gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), 529 cpu_gpr[gprn]); 530 out: 531 spr_store_dump_spr(sprn); 532 533 /* 534 * SPR_CTRL writes must force a new translation block, 535 * allowing the PMU to calculate the run latch events with 536 * more accuracy. 537 */ 538 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 539 } 540 541 #if !defined(CONFIG_USER_ONLY) 542 void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 543 { 544 TCGv t0 = tcg_temp_new(); 545 TCGv t1 = tcg_temp_new(); 546 gen_load_spr(t0, sprn); 547 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 548 tcg_gen_and_tl(t0, t0, t1); 549 gen_store_spr(sprn, t0); 550 } 551 552 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 553 { 554 } 555 556 #endif 557 558 /* SPR common to all PowerPC */ 559 /* XER */ 560 void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 561 { 562 TCGv dst = cpu_gpr[gprn]; 563 TCGv t0 = tcg_temp_new(); 564 TCGv t1 = tcg_temp_new(); 565 TCGv t2 = tcg_temp_new(); 566 tcg_gen_mov_tl(dst, cpu_xer); 567 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 568 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 569 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 570 tcg_gen_or_tl(t0, t0, t1); 571 tcg_gen_or_tl(dst, dst, t2); 572 tcg_gen_or_tl(dst, dst, t0); 573 if (is_isa300(ctx)) { 574 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 575 tcg_gen_or_tl(dst, dst, t0); 576 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 577 tcg_gen_or_tl(dst, dst, t0); 578 } 579 } 580 581 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 582 { 583 TCGv src = cpu_gpr[gprn]; 584 /* Write all flags, while reading back check for isa300 */ 585 tcg_gen_andi_tl(cpu_xer, src, 586 ~((1u << XER_SO) | 587 (1u << XER_OV) | (1u << XER_OV32) | 588 (1u << XER_CA) | (1u << XER_CA32))); 589 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 590 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 591 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 592 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 593 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 594 } 595 596 /* LR */ 597 void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 598 { 599 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 600 } 601 602 void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 603 { 604 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 605 } 606 607 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 608 /* Debug facilities */ 609 /* CFAR */ 610 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 611 { 612 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 613 } 614 615 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 616 { 617 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 618 } 619 620 /* Breakpoint */ 621 void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 622 { 623 translator_io_start(&ctx->base); 624 gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); 625 } 626 627 /* Watchpoint */ 628 void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) 629 { 630 translator_io_start(&ctx->base); 631 gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); 632 } 633 634 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) 635 { 636 translator_io_start(&ctx->base); 637 gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); 638 } 639 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 640 641 /* CTR */ 642 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 643 { 644 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 645 } 646 647 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 648 { 649 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 650 } 651 652 /* User read access to SPR */ 653 /* USPRx */ 654 /* UMMCRx */ 655 /* UPMCx */ 656 /* USIA */ 657 /* UDECR */ 658 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 659 { 660 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 661 } 662 663 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 664 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 665 { 666 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 667 } 668 #endif 669 670 /* SPR common to all non-embedded PowerPC */ 671 /* DECR */ 672 #if !defined(CONFIG_USER_ONLY) 673 void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 674 { 675 translator_io_start(&ctx->base); 676 gen_helper_load_decr(cpu_gpr[gprn], tcg_env); 677 } 678 679 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 680 { 681 translator_io_start(&ctx->base); 682 gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); 683 } 684 #endif 685 686 /* SPR common to all non-embedded PowerPC, except 601 */ 687 /* Time base */ 688 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 689 { 690 translator_io_start(&ctx->base); 691 gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); 692 } 693 694 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 695 { 696 translator_io_start(&ctx->base); 697 gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); 698 } 699 700 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 701 { 702 gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); 703 } 704 705 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 706 { 707 gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); 708 } 709 710 #if !defined(CONFIG_USER_ONLY) 711 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 712 { 713 if (!gen_serialize_core_lpar(ctx)) { 714 return; 715 } 716 717 translator_io_start(&ctx->base); 718 gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); 719 } 720 721 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 722 { 723 if (!gen_serialize_core_lpar(ctx)) { 724 return; 725 } 726 727 translator_io_start(&ctx->base); 728 gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); 729 } 730 731 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 732 { 733 gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); 734 } 735 736 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 737 { 738 gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); 739 } 740 741 #if defined(TARGET_PPC64) 742 void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 743 { 744 translator_io_start(&ctx->base); 745 gen_helper_load_purr(cpu_gpr[gprn], tcg_env); 746 } 747 748 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 749 { 750 if (!gen_serialize_core_lpar(ctx)) { 751 return; 752 } 753 translator_io_start(&ctx->base); 754 gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); 755 } 756 757 /* HDECR */ 758 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 759 { 760 translator_io_start(&ctx->base); 761 gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); 762 } 763 764 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 765 { 766 if (!gen_serialize_core_lpar(ctx)) { 767 return; 768 } 769 translator_io_start(&ctx->base); 770 gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); 771 } 772 773 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 774 { 775 translator_io_start(&ctx->base); 776 gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); 777 } 778 779 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 780 { 781 if (!gen_serialize_core_lpar(ctx)) { 782 return; 783 } 784 translator_io_start(&ctx->base); 785 gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); 786 } 787 788 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 789 { 790 if (!gen_serialize_core_lpar(ctx)) { 791 return; 792 } 793 translator_io_start(&ctx->base); 794 gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); 795 } 796 797 #endif 798 #endif 799 800 #if !defined(CONFIG_USER_ONLY) 801 /* IBAT0U...IBAT0U */ 802 /* IBAT0L...IBAT7L */ 803 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 804 { 805 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 806 offsetof(CPUPPCState, 807 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 808 } 809 810 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 811 { 812 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 813 offsetof(CPUPPCState, 814 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 815 } 816 817 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 818 { 819 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 820 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 821 } 822 823 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 824 { 825 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 826 gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); 827 } 828 829 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 830 { 831 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 832 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 833 } 834 835 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 836 { 837 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 838 gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); 839 } 840 841 /* DBAT0U...DBAT7U */ 842 /* DBAT0L...DBAT7L */ 843 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 844 { 845 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 846 offsetof(CPUPPCState, 847 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 848 } 849 850 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 851 { 852 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, 853 offsetof(CPUPPCState, 854 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 855 } 856 857 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 858 { 859 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 860 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 861 } 862 863 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 864 { 865 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 866 gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); 867 } 868 869 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 870 { 871 TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 872 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 873 } 874 875 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 876 { 877 TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 878 gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); 879 } 880 881 /* SDR1 */ 882 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 883 { 884 gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); 885 } 886 887 #if defined(TARGET_PPC64) 888 /* 64 bits PowerPC specific SPRs */ 889 /* PIDR */ 890 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 891 { 892 gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); 893 } 894 895 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 896 { 897 gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); 898 } 899 900 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 901 { 902 tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix)); 903 } 904 905 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 906 { 907 TCGv t0 = tcg_temp_new(); 908 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 909 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 910 } 911 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 912 { 913 if (!gen_serialize_core(ctx)) { 914 return; 915 } 916 917 gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); 918 } 919 920 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 921 { 922 gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); 923 } 924 925 /* DPDES */ 926 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 927 { 928 if (!gen_serialize_core_lpar(ctx)) { 929 return; 930 } 931 932 gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); 933 } 934 935 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 936 { 937 if (!gen_serialize_core_lpar(ctx)) { 938 return; 939 } 940 941 gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); 942 } 943 #endif 944 #endif 945 946 /* PowerPC 40x specific registers */ 947 #if !defined(CONFIG_USER_ONLY) 948 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 949 { 950 translator_io_start(&ctx->base); 951 gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); 952 } 953 954 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 955 { 956 translator_io_start(&ctx->base); 957 gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); 958 } 959 960 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 961 { 962 translator_io_start(&ctx->base); 963 gen_store_spr(sprn, cpu_gpr[gprn]); 964 gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); 965 /* We must stop translation as we may have rebooted */ 966 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 967 } 968 969 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 970 { 971 translator_io_start(&ctx->base); 972 gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); 973 } 974 975 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 976 { 977 translator_io_start(&ctx->base); 978 gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); 979 } 980 981 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 982 { 983 translator_io_start(&ctx->base); 984 gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); 985 } 986 987 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 988 { 989 TCGv t0 = tcg_temp_new(); 990 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 991 gen_helper_store_40x_pid(tcg_env, t0); 992 } 993 994 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 995 { 996 translator_io_start(&ctx->base); 997 gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); 998 } 999 1000 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 1001 { 1002 translator_io_start(&ctx->base); 1003 gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); 1004 } 1005 #endif 1006 1007 /* PIR */ 1008 #if !defined(CONFIG_USER_ONLY) 1009 void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 1010 { 1011 TCGv t0 = tcg_temp_new(); 1012 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 1013 gen_store_spr(SPR_PIR, t0); 1014 } 1015 #endif 1016 1017 /* SPE specific registers */ 1018 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 1019 { 1020 TCGv_i32 t0 = tcg_temp_new_i32(); 1021 tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1022 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 1023 } 1024 1025 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 1026 { 1027 TCGv_i32 t0 = tcg_temp_new_i32(); 1028 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 1029 tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); 1030 } 1031 1032 #if !defined(CONFIG_USER_ONLY) 1033 /* Callback used to write the exception vector base */ 1034 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 1035 { 1036 TCGv t0 = tcg_temp_new(); 1037 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); 1038 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1039 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); 1040 gen_store_spr(sprn, t0); 1041 } 1042 1043 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 1044 { 1045 int sprn_offs; 1046 1047 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 1048 sprn_offs = sprn - SPR_BOOKE_IVOR0; 1049 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 1050 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 1051 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 1052 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 1053 } else { 1054 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 1055 " vector 0x%03x\n", sprn); 1056 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1057 return; 1058 } 1059 1060 TCGv t0 = tcg_temp_new(); 1061 tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); 1062 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1063 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 1064 gen_store_spr(sprn, t0); 1065 } 1066 #endif 1067 1068 #ifdef TARGET_PPC64 1069 #ifndef CONFIG_USER_ONLY 1070 void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1071 { 1072 TCGv t0 = tcg_temp_new(); 1073 TCGv t1 = tcg_temp_new(); 1074 TCGv t2 = tcg_temp_new(); 1075 1076 /* 1077 * Note, the HV=1 PR=0 case is handled earlier by simply using 1078 * spr_write_generic for HV mode in the SPR table 1079 */ 1080 1081 /* Build insertion mask into t1 based on context */ 1082 if (ctx->pr) { 1083 gen_load_spr(t1, SPR_UAMOR); 1084 } else { 1085 gen_load_spr(t1, SPR_AMOR); 1086 } 1087 1088 /* Mask new bits into t2 */ 1089 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1090 1091 /* Load AMR and clear new bits in t0 */ 1092 gen_load_spr(t0, SPR_AMR); 1093 tcg_gen_andc_tl(t0, t0, t1); 1094 1095 /* Or'in new bits and write it out */ 1096 tcg_gen_or_tl(t0, t0, t2); 1097 gen_store_spr(SPR_AMR, t0); 1098 spr_store_dump_spr(SPR_AMR); 1099 } 1100 1101 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1102 { 1103 TCGv t0 = tcg_temp_new(); 1104 TCGv t1 = tcg_temp_new(); 1105 TCGv t2 = tcg_temp_new(); 1106 1107 /* 1108 * Note, the HV=1 case is handled earlier by simply using 1109 * spr_write_generic for HV mode in the SPR table 1110 */ 1111 1112 /* Build insertion mask into t1 based on context */ 1113 gen_load_spr(t1, SPR_AMOR); 1114 1115 /* Mask new bits into t2 */ 1116 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1117 1118 /* Load AMR and clear new bits in t0 */ 1119 gen_load_spr(t0, SPR_UAMOR); 1120 tcg_gen_andc_tl(t0, t0, t1); 1121 1122 /* Or'in new bits and write it out */ 1123 tcg_gen_or_tl(t0, t0, t2); 1124 gen_store_spr(SPR_UAMOR, t0); 1125 spr_store_dump_spr(SPR_UAMOR); 1126 } 1127 1128 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1129 { 1130 TCGv t0 = tcg_temp_new(); 1131 TCGv t1 = tcg_temp_new(); 1132 TCGv t2 = tcg_temp_new(); 1133 1134 /* 1135 * Note, the HV=1 case is handled earlier by simply using 1136 * spr_write_generic for HV mode in the SPR table 1137 */ 1138 1139 /* Build insertion mask into t1 based on context */ 1140 gen_load_spr(t1, SPR_AMOR); 1141 1142 /* Mask new bits into t2 */ 1143 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1144 1145 /* Load AMR and clear new bits in t0 */ 1146 gen_load_spr(t0, SPR_IAMR); 1147 tcg_gen_andc_tl(t0, t0, t1); 1148 1149 /* Or'in new bits and write it out */ 1150 tcg_gen_or_tl(t0, t0, t2); 1151 gen_store_spr(SPR_IAMR, t0); 1152 spr_store_dump_spr(SPR_IAMR); 1153 } 1154 #endif 1155 #endif 1156 1157 #ifndef CONFIG_USER_ONLY 1158 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1159 { 1160 gen_helper_fixup_thrm(tcg_env); 1161 gen_load_spr(cpu_gpr[gprn], sprn); 1162 spr_load_dump_spr(sprn); 1163 } 1164 #endif /* !CONFIG_USER_ONLY */ 1165 1166 #if !defined(CONFIG_USER_ONLY) 1167 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1168 { 1169 TCGv t0 = tcg_temp_new(); 1170 1171 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1172 gen_store_spr(sprn, t0); 1173 } 1174 1175 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1176 { 1177 TCGv t0 = tcg_temp_new(); 1178 1179 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1180 gen_store_spr(sprn, t0); 1181 } 1182 1183 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1184 { 1185 TCGv t0 = tcg_temp_new(); 1186 1187 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1188 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1189 gen_store_spr(sprn, t0); 1190 } 1191 1192 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1193 { 1194 gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); 1195 } 1196 1197 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1198 { 1199 TCGv_i32 t0 = tcg_constant_i32(sprn); 1200 gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); 1201 } 1202 1203 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1204 { 1205 gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); 1206 } 1207 1208 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1209 { 1210 gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); 1211 } 1212 1213 #endif 1214 1215 #if !defined(CONFIG_USER_ONLY) 1216 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1217 { 1218 TCGv val = tcg_temp_new(); 1219 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1220 gen_store_spr(SPR_BOOKE_MAS3, val); 1221 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1222 gen_store_spr(SPR_BOOKE_MAS7, val); 1223 } 1224 1225 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1226 { 1227 TCGv mas7 = tcg_temp_new(); 1228 TCGv mas3 = tcg_temp_new(); 1229 gen_load_spr(mas7, SPR_BOOKE_MAS7); 1230 tcg_gen_shli_tl(mas7, mas7, 32); 1231 gen_load_spr(mas3, SPR_BOOKE_MAS3); 1232 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1233 } 1234 1235 #endif 1236 1237 #ifdef TARGET_PPC64 1238 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1239 int bit, int sprn, int cause) 1240 { 1241 TCGv_i32 t1 = tcg_constant_i32(bit); 1242 TCGv_i32 t2 = tcg_constant_i32(sprn); 1243 TCGv_i32 t3 = tcg_constant_i32(cause); 1244 1245 gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); 1246 } 1247 1248 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1249 int bit, int sprn, int cause) 1250 { 1251 TCGv_i32 t1 = tcg_constant_i32(bit); 1252 TCGv_i32 t2 = tcg_constant_i32(sprn); 1253 TCGv_i32 t3 = tcg_constant_i32(cause); 1254 1255 gen_helper_msr_facility_check(tcg_env, t1, t2, t3); 1256 } 1257 1258 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1259 { 1260 TCGv spr_up = tcg_temp_new(); 1261 TCGv spr = tcg_temp_new(); 1262 1263 gen_load_spr(spr, sprn - 1); 1264 tcg_gen_shri_tl(spr_up, spr, 32); 1265 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1266 } 1267 1268 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1269 { 1270 TCGv spr = tcg_temp_new(); 1271 1272 gen_load_spr(spr, sprn - 1); 1273 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1274 gen_store_spr(sprn - 1, spr); 1275 } 1276 1277 #if !defined(CONFIG_USER_ONLY) 1278 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1279 { 1280 TCGv hmer = tcg_temp_new(); 1281 1282 gen_load_spr(hmer, sprn); 1283 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1284 gen_store_spr(sprn, hmer); 1285 spr_store_dump_spr(sprn); 1286 } 1287 1288 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1289 { 1290 /* Reading TFMR can cause it to be updated, so serialize threads here too */ 1291 if (!gen_serialize_core(ctx)) { 1292 return; 1293 } 1294 gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); 1295 } 1296 1297 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1298 { 1299 if (!gen_serialize_core(ctx)) { 1300 return; 1301 } 1302 gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); 1303 } 1304 1305 void spr_write_sprc(DisasContext *ctx, int sprn, int gprn) 1306 { 1307 gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]); 1308 } 1309 1310 void spr_read_sprd(DisasContext *ctx, int gprn, int sprn) 1311 { 1312 gen_helper_load_sprd(cpu_gpr[gprn], tcg_env); 1313 } 1314 1315 void spr_write_sprd(DisasContext *ctx, int sprn, int gprn) 1316 { 1317 if (!gen_serialize_core(ctx)) { 1318 return; 1319 } 1320 gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]); 1321 } 1322 1323 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1324 { 1325 translator_io_start(&ctx->base); 1326 gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); 1327 } 1328 #endif /* !defined(CONFIG_USER_ONLY) */ 1329 1330 void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1331 { 1332 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1333 spr_read_generic(ctx, gprn, sprn); 1334 } 1335 1336 void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1337 { 1338 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1339 spr_write_generic(ctx, sprn, gprn); 1340 } 1341 1342 void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1343 { 1344 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1345 spr_read_generic(ctx, gprn, sprn); 1346 } 1347 1348 void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1349 { 1350 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1351 spr_write_generic(ctx, sprn, gprn); 1352 } 1353 1354 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1355 { 1356 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1357 spr_read_prev_upper32(ctx, gprn, sprn); 1358 } 1359 1360 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1361 { 1362 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1363 spr_write_prev_upper32(ctx, sprn, gprn); 1364 } 1365 1366 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1367 { 1368 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1369 spr_read_generic(ctx, gprn, sprn); 1370 } 1371 1372 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1373 { 1374 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1375 spr_write_generic(ctx, sprn, gprn); 1376 } 1377 1378 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1379 { 1380 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1381 spr_read_prev_upper32(ctx, gprn, sprn); 1382 } 1383 1384 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1385 { 1386 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1387 spr_write_prev_upper32(ctx, sprn, gprn); 1388 } 1389 1390 void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1391 { 1392 TCGv t0 = tcg_temp_new(); 1393 1394 /* 1395 * Access to the (H)DEXCR in problem state is done using separated 1396 * SPR indexes which are 16 below the SPR indexes which have full 1397 * access to the (H)DEXCR in privileged state. Problem state can 1398 * only read bits 32:63, bits 0:31 return 0. 1399 * 1400 * See section 9.3.1-9.3.2 of PowerISA v3.1B 1401 */ 1402 1403 gen_load_spr(t0, sprn + 16); 1404 tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1405 } 1406 1407 /* The PPR32 SPR accesses the upper 32-bits of PPR */ 1408 void spr_read_ppr32(DisasContext *ctx, int gprn, int sprn) 1409 { 1410 gen_load_spr(cpu_gpr[gprn], SPR_PPR); 1411 tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32); 1412 spr_load_dump_spr(SPR_PPR); 1413 } 1414 1415 void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) 1416 { 1417 TCGv t0 = tcg_temp_new(); 1418 1419 /* 1420 * Don't clobber the low 32-bits of the PPR. These are all reserved bits 1421 * but TCG does implement them, so it would be surprising to zero them 1422 * here. "Priority nops" are similarly careful not to clobber reserved 1423 * bits. 1424 */ 1425 gen_load_spr(t0, SPR_PPR); 1426 tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32); 1427 gen_store_spr(SPR_PPR, t0); 1428 spr_store_dump_spr(SPR_PPR); 1429 } 1430 #endif 1431 1432 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1433 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1434 1435 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1436 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1437 1438 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1439 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1440 1441 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1442 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1443 1444 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1445 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1446 1447 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1448 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1449 1450 typedef struct opcode_t { 1451 unsigned char opc1, opc2, opc3, opc4; 1452 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1453 unsigned char pad[4]; 1454 #endif 1455 opc_handler_t handler; 1456 const char *oname; 1457 } opcode_t; 1458 1459 static void gen_priv_opc(DisasContext *ctx) 1460 { 1461 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 1462 } 1463 1464 /* Helpers for priv. check */ 1465 #define GEN_PRIV(CTX) \ 1466 do { \ 1467 gen_priv_opc(CTX); return; \ 1468 } while (0) 1469 1470 #if defined(CONFIG_USER_ONLY) 1471 #define CHK_HV(CTX) GEN_PRIV(CTX) 1472 #define CHK_SV(CTX) GEN_PRIV(CTX) 1473 #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1474 #else 1475 #define CHK_HV(CTX) \ 1476 do { \ 1477 if (unlikely(ctx->pr || !ctx->hv)) {\ 1478 GEN_PRIV(CTX); \ 1479 } \ 1480 } while (0) 1481 #define CHK_SV(CTX) \ 1482 do { \ 1483 if (unlikely(ctx->pr)) { \ 1484 GEN_PRIV(CTX); \ 1485 } \ 1486 } while (0) 1487 #define CHK_HVRM(CTX) \ 1488 do { \ 1489 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1490 GEN_PRIV(CTX); \ 1491 } \ 1492 } while (0) 1493 #endif 1494 1495 #define CHK_NONE(CTX) 1496 1497 /*****************************************************************************/ 1498 /* PowerPC instructions table */ 1499 1500 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1501 { \ 1502 .opc1 = op1, \ 1503 .opc2 = op2, \ 1504 .opc3 = op3, \ 1505 .opc4 = 0xff, \ 1506 .handler = { \ 1507 .inval1 = invl, \ 1508 .type = _typ, \ 1509 .type2 = _typ2, \ 1510 .handler = &gen_##name, \ 1511 }, \ 1512 .oname = stringify(name), \ 1513 } 1514 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1515 { \ 1516 .opc1 = op1, \ 1517 .opc2 = op2, \ 1518 .opc3 = op3, \ 1519 .opc4 = 0xff, \ 1520 .handler = { \ 1521 .inval1 = invl1, \ 1522 .inval2 = invl2, \ 1523 .type = _typ, \ 1524 .type2 = _typ2, \ 1525 .handler = &gen_##name, \ 1526 }, \ 1527 .oname = stringify(name), \ 1528 } 1529 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1530 { \ 1531 .opc1 = op1, \ 1532 .opc2 = op2, \ 1533 .opc3 = op3, \ 1534 .opc4 = 0xff, \ 1535 .handler = { \ 1536 .inval1 = invl, \ 1537 .type = _typ, \ 1538 .type2 = _typ2, \ 1539 .handler = &gen_##name, \ 1540 }, \ 1541 .oname = onam, \ 1542 } 1543 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1544 { \ 1545 .opc1 = op1, \ 1546 .opc2 = op2, \ 1547 .opc3 = op3, \ 1548 .opc4 = op4, \ 1549 .handler = { \ 1550 .inval1 = invl, \ 1551 .type = _typ, \ 1552 .type2 = _typ2, \ 1553 .handler = &gen_##name, \ 1554 }, \ 1555 .oname = stringify(name), \ 1556 } 1557 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1558 { \ 1559 .opc1 = op1, \ 1560 .opc2 = op2, \ 1561 .opc3 = op3, \ 1562 .opc4 = op4, \ 1563 .handler = { \ 1564 .inval1 = invl, \ 1565 .type = _typ, \ 1566 .type2 = _typ2, \ 1567 .handler = &gen_##name, \ 1568 }, \ 1569 .oname = onam, \ 1570 } 1571 1572 /* Invalid instruction */ 1573 static void gen_invalid(DisasContext *ctx) 1574 { 1575 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1576 } 1577 1578 static opc_handler_t invalid_handler = { 1579 .inval1 = 0xFFFFFFFF, 1580 .inval2 = 0xFFFFFFFF, 1581 .type = PPC_NONE, 1582 .type2 = PPC_NONE, 1583 .handler = gen_invalid, 1584 }; 1585 1586 /*** Integer comparison ***/ 1587 1588 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1589 { 1590 TCGv t0 = tcg_temp_new(); 1591 TCGv t1 = tcg_temp_new(); 1592 TCGv_i32 t = tcg_temp_new_i32(); 1593 1594 tcg_gen_movi_tl(t0, CRF_EQ); 1595 tcg_gen_movi_tl(t1, CRF_LT); 1596 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1597 t0, arg0, arg1, t1, t0); 1598 tcg_gen_movi_tl(t1, CRF_GT); 1599 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1600 t0, arg0, arg1, t1, t0); 1601 1602 tcg_gen_trunc_tl_i32(t, t0); 1603 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1604 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1605 } 1606 1607 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1608 { 1609 TCGv t0 = tcg_constant_tl(arg1); 1610 gen_op_cmp(arg0, t0, s, crf); 1611 } 1612 1613 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1614 { 1615 TCGv t0, t1; 1616 t0 = tcg_temp_new(); 1617 t1 = tcg_temp_new(); 1618 if (s) { 1619 tcg_gen_ext32s_tl(t0, arg0); 1620 tcg_gen_ext32s_tl(t1, arg1); 1621 } else { 1622 tcg_gen_ext32u_tl(t0, arg0); 1623 tcg_gen_ext32u_tl(t1, arg1); 1624 } 1625 gen_op_cmp(t0, t1, s, crf); 1626 } 1627 1628 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1629 { 1630 TCGv t0 = tcg_constant_tl(arg1); 1631 gen_op_cmp32(arg0, t0, s, crf); 1632 } 1633 1634 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1635 { 1636 if (NARROW_MODE(ctx)) { 1637 gen_op_cmpi32(reg, 0, 1, 0); 1638 } else { 1639 gen_op_cmpi(reg, 0, 1, 0); 1640 } 1641 } 1642 1643 /*** Integer arithmetic ***/ 1644 1645 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1646 TCGv arg1, TCGv arg2, int sub) 1647 { 1648 TCGv t0 = tcg_temp_new(); 1649 1650 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1651 tcg_gen_xor_tl(t0, arg1, arg2); 1652 if (sub) { 1653 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1654 } else { 1655 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1656 } 1657 if (NARROW_MODE(ctx)) { 1658 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1659 if (is_isa300(ctx)) { 1660 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1661 } 1662 } else { 1663 if (is_isa300(ctx)) { 1664 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1665 } 1666 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1667 } 1668 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1669 } 1670 1671 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 1672 TCGv res, TCGv arg0, TCGv arg1, 1673 TCGv ca32, int sub) 1674 { 1675 TCGv t0; 1676 1677 if (!is_isa300(ctx)) { 1678 return; 1679 } 1680 1681 t0 = tcg_temp_new(); 1682 if (sub) { 1683 tcg_gen_eqv_tl(t0, arg0, arg1); 1684 } else { 1685 tcg_gen_xor_tl(t0, arg0, arg1); 1686 } 1687 tcg_gen_xor_tl(t0, t0, res); 1688 tcg_gen_extract_tl(ca32, t0, 32, 1); 1689 } 1690 1691 /* Common add function */ 1692 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 1693 TCGv arg2, TCGv ca, TCGv ca32, 1694 bool add_ca, bool compute_ca, 1695 bool compute_ov, bool compute_rc0) 1696 { 1697 TCGv t0 = ret; 1698 1699 if (compute_ca || compute_ov) { 1700 t0 = tcg_temp_new(); 1701 } 1702 1703 if (compute_ca) { 1704 if (NARROW_MODE(ctx)) { 1705 /* 1706 * Caution: a non-obvious corner case of the spec is that 1707 * we must produce the *entire* 64-bit addition, but 1708 * produce the carry into bit 32. 1709 */ 1710 TCGv t1 = tcg_temp_new(); 1711 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1712 tcg_gen_add_tl(t0, arg1, arg2); 1713 if (add_ca) { 1714 tcg_gen_add_tl(t0, t0, ca); 1715 } 1716 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1717 tcg_gen_extract_tl(ca, ca, 32, 1); 1718 if (is_isa300(ctx)) { 1719 tcg_gen_mov_tl(ca32, ca); 1720 } 1721 } else { 1722 TCGv zero = tcg_constant_tl(0); 1723 if (add_ca) { 1724 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 1725 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1726 } else { 1727 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1728 } 1729 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1730 } 1731 } else { 1732 tcg_gen_add_tl(t0, arg1, arg2); 1733 if (add_ca) { 1734 tcg_gen_add_tl(t0, t0, ca); 1735 } 1736 } 1737 1738 if (compute_ov) { 1739 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1740 } 1741 if (unlikely(compute_rc0)) { 1742 gen_set_Rc0(ctx, t0); 1743 } 1744 1745 if (t0 != ret) { 1746 tcg_gen_mov_tl(ret, t0); 1747 } 1748 } 1749 1750 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, 1751 TCGv arg1, TCGv arg2, bool sign, 1752 bool compute_ov, bool compute_rc0) 1753 { 1754 TCGv_i32 t0 = tcg_temp_new_i32(); 1755 TCGv_i32 t1 = tcg_temp_new_i32(); 1756 TCGv_i32 t2 = tcg_temp_new_i32(); 1757 TCGv_i32 t3 = tcg_temp_new_i32(); 1758 1759 tcg_gen_trunc_tl_i32(t0, arg1); 1760 tcg_gen_trunc_tl_i32(t1, arg2); 1761 if (sign) { 1762 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1763 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1764 tcg_gen_and_i32(t2, t2, t3); 1765 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1766 tcg_gen_or_i32(t2, t2, t3); 1767 tcg_gen_movi_i32(t3, 0); 1768 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1769 tcg_gen_div_i32(t3, t0, t1); 1770 tcg_gen_extu_i32_tl(ret, t3); 1771 } else { 1772 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1773 tcg_gen_movi_i32(t3, 0); 1774 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1775 tcg_gen_divu_i32(t3, t0, t1); 1776 tcg_gen_extu_i32_tl(ret, t3); 1777 } 1778 if (compute_ov) { 1779 tcg_gen_extu_i32_tl(cpu_ov, t2); 1780 if (is_isa300(ctx)) { 1781 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1782 } 1783 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1784 } 1785 1786 if (unlikely(compute_rc0)) { 1787 gen_set_Rc0(ctx, ret); 1788 } 1789 } 1790 1791 #if defined(TARGET_PPC64) 1792 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, 1793 TCGv arg1, TCGv arg2, bool sign, 1794 bool compute_ov, bool compute_rc0) 1795 { 1796 TCGv_i64 t0 = tcg_temp_new_i64(); 1797 TCGv_i64 t1 = tcg_temp_new_i64(); 1798 TCGv_i64 t2 = tcg_temp_new_i64(); 1799 TCGv_i64 t3 = tcg_temp_new_i64(); 1800 1801 tcg_gen_mov_i64(t0, arg1); 1802 tcg_gen_mov_i64(t1, arg2); 1803 if (sign) { 1804 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1805 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1806 tcg_gen_and_i64(t2, t2, t3); 1807 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1808 tcg_gen_or_i64(t2, t2, t3); 1809 tcg_gen_movi_i64(t3, 0); 1810 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1811 tcg_gen_div_i64(ret, t0, t1); 1812 } else { 1813 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1814 tcg_gen_movi_i64(t3, 0); 1815 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1816 tcg_gen_divu_i64(ret, t0, t1); 1817 } 1818 if (compute_ov) { 1819 tcg_gen_mov_tl(cpu_ov, t2); 1820 if (is_isa300(ctx)) { 1821 tcg_gen_mov_tl(cpu_ov32, t2); 1822 } 1823 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1824 } 1825 1826 if (unlikely(compute_rc0)) { 1827 gen_set_Rc0(ctx, ret); 1828 } 1829 } 1830 #endif 1831 1832 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1833 TCGv arg2, int sign) 1834 { 1835 TCGv_i32 t0 = tcg_temp_new_i32(); 1836 TCGv_i32 t1 = tcg_temp_new_i32(); 1837 1838 tcg_gen_trunc_tl_i32(t0, arg1); 1839 tcg_gen_trunc_tl_i32(t1, arg2); 1840 if (sign) { 1841 TCGv_i32 t2 = tcg_temp_new_i32(); 1842 TCGv_i32 t3 = tcg_temp_new_i32(); 1843 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1844 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1845 tcg_gen_and_i32(t2, t2, t3); 1846 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1847 tcg_gen_or_i32(t2, t2, t3); 1848 tcg_gen_movi_i32(t3, 0); 1849 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1850 tcg_gen_rem_i32(t3, t0, t1); 1851 tcg_gen_ext_i32_tl(ret, t3); 1852 } else { 1853 TCGv_i32 t2 = tcg_constant_i32(1); 1854 TCGv_i32 t3 = tcg_constant_i32(0); 1855 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1856 tcg_gen_remu_i32(t0, t0, t1); 1857 tcg_gen_extu_i32_tl(ret, t0); 1858 } 1859 } 1860 1861 #if defined(TARGET_PPC64) 1862 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1863 TCGv arg2, int sign) 1864 { 1865 TCGv_i64 t0 = tcg_temp_new_i64(); 1866 TCGv_i64 t1 = tcg_temp_new_i64(); 1867 1868 tcg_gen_mov_i64(t0, arg1); 1869 tcg_gen_mov_i64(t1, arg2); 1870 if (sign) { 1871 TCGv_i64 t2 = tcg_temp_new_i64(); 1872 TCGv_i64 t3 = tcg_temp_new_i64(); 1873 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1874 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1875 tcg_gen_and_i64(t2, t2, t3); 1876 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1877 tcg_gen_or_i64(t2, t2, t3); 1878 tcg_gen_movi_i64(t3, 0); 1879 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1880 tcg_gen_rem_i64(ret, t0, t1); 1881 } else { 1882 TCGv_i64 t2 = tcg_constant_i64(1); 1883 TCGv_i64 t3 = tcg_constant_i64(0); 1884 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1885 tcg_gen_remu_i64(ret, t0, t1); 1886 } 1887 } 1888 #endif 1889 1890 /* Common subf function */ 1891 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1892 TCGv arg2, bool add_ca, bool compute_ca, 1893 bool compute_ov, bool compute_rc0) 1894 { 1895 TCGv t0 = ret; 1896 1897 if (compute_ca || compute_ov) { 1898 t0 = tcg_temp_new(); 1899 } 1900 1901 if (compute_ca) { 1902 /* dest = ~arg1 + arg2 [+ ca]. */ 1903 if (NARROW_MODE(ctx)) { 1904 /* 1905 * Caution: a non-obvious corner case of the spec is that 1906 * we must produce the *entire* 64-bit addition, but 1907 * produce the carry into bit 32. 1908 */ 1909 TCGv inv1 = tcg_temp_new(); 1910 TCGv t1 = tcg_temp_new(); 1911 tcg_gen_not_tl(inv1, arg1); 1912 if (add_ca) { 1913 tcg_gen_add_tl(t0, arg2, cpu_ca); 1914 } else { 1915 tcg_gen_addi_tl(t0, arg2, 1); 1916 } 1917 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1918 tcg_gen_add_tl(t0, t0, inv1); 1919 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1920 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1921 if (is_isa300(ctx)) { 1922 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1923 } 1924 } else if (add_ca) { 1925 TCGv zero, inv1 = tcg_temp_new(); 1926 tcg_gen_not_tl(inv1, arg1); 1927 zero = tcg_constant_tl(0); 1928 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1929 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1930 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1931 } else { 1932 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1933 tcg_gen_sub_tl(t0, arg2, arg1); 1934 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1935 } 1936 } else if (add_ca) { 1937 /* 1938 * Since we're ignoring carry-out, we can simplify the 1939 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1940 */ 1941 tcg_gen_sub_tl(t0, arg2, arg1); 1942 tcg_gen_add_tl(t0, t0, cpu_ca); 1943 tcg_gen_subi_tl(t0, t0, 1); 1944 } else { 1945 tcg_gen_sub_tl(t0, arg2, arg1); 1946 } 1947 1948 if (compute_ov) { 1949 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1950 } 1951 if (unlikely(compute_rc0)) { 1952 gen_set_Rc0(ctx, t0); 1953 } 1954 1955 if (t0 != ret) { 1956 tcg_gen_mov_tl(ret, t0); 1957 } 1958 } 1959 1960 /*** Integer logical ***/ 1961 1962 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1963 static void gen_pause(DisasContext *ctx) 1964 { 1965 TCGv_i32 t0 = tcg_constant_i32(0); 1966 tcg_gen_st_i32(t0, tcg_env, 1967 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1968 1969 /* Stop translation, this gives other CPUs a chance to run */ 1970 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1971 } 1972 #endif /* defined(TARGET_PPC64) */ 1973 1974 /*** Integer rotate ***/ 1975 1976 /* rlwimi & rlwimi. */ 1977 static void gen_rlwimi(DisasContext *ctx) 1978 { 1979 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1980 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1981 uint32_t sh = SH(ctx->opcode); 1982 uint32_t mb = MB(ctx->opcode); 1983 uint32_t me = ME(ctx->opcode); 1984 1985 if (sh == (31 - me) && mb <= me) { 1986 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1987 } else { 1988 target_ulong mask; 1989 bool mask_in_32b = true; 1990 TCGv t1; 1991 1992 #if defined(TARGET_PPC64) 1993 mb += 32; 1994 me += 32; 1995 #endif 1996 mask = MASK(mb, me); 1997 1998 #if defined(TARGET_PPC64) 1999 if (mask > 0xffffffffu) { 2000 mask_in_32b = false; 2001 } 2002 #endif 2003 t1 = tcg_temp_new(); 2004 if (mask_in_32b) { 2005 TCGv_i32 t0 = tcg_temp_new_i32(); 2006 tcg_gen_trunc_tl_i32(t0, t_rs); 2007 tcg_gen_rotli_i32(t0, t0, sh); 2008 tcg_gen_extu_i32_tl(t1, t0); 2009 } else { 2010 #if defined(TARGET_PPC64) 2011 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2012 tcg_gen_rotli_i64(t1, t1, sh); 2013 #else 2014 g_assert_not_reached(); 2015 #endif 2016 } 2017 2018 tcg_gen_andi_tl(t1, t1, mask); 2019 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2020 tcg_gen_or_tl(t_ra, t_ra, t1); 2021 } 2022 if (unlikely(Rc(ctx->opcode) != 0)) { 2023 gen_set_Rc0(ctx, t_ra); 2024 } 2025 } 2026 2027 /* rlwinm & rlwinm. */ 2028 static void gen_rlwinm(DisasContext *ctx) 2029 { 2030 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2031 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2032 int sh = SH(ctx->opcode); 2033 int mb = MB(ctx->opcode); 2034 int me = ME(ctx->opcode); 2035 int len = me - mb + 1; 2036 int rsh = (32 - sh) & 31; 2037 2038 if (sh != 0 && len > 0 && me == (31 - sh)) { 2039 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2040 } else if (me == 31 && rsh + len <= 32) { 2041 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2042 } else { 2043 target_ulong mask; 2044 bool mask_in_32b = true; 2045 #if defined(TARGET_PPC64) 2046 mb += 32; 2047 me += 32; 2048 #endif 2049 mask = MASK(mb, me); 2050 #if defined(TARGET_PPC64) 2051 if (mask > 0xffffffffu) { 2052 mask_in_32b = false; 2053 } 2054 #endif 2055 if (mask_in_32b) { 2056 if (sh == 0) { 2057 tcg_gen_andi_tl(t_ra, t_rs, mask); 2058 } else { 2059 TCGv_i32 t0 = tcg_temp_new_i32(); 2060 tcg_gen_trunc_tl_i32(t0, t_rs); 2061 tcg_gen_rotli_i32(t0, t0, sh); 2062 tcg_gen_andi_i32(t0, t0, mask); 2063 tcg_gen_extu_i32_tl(t_ra, t0); 2064 } 2065 } else { 2066 #if defined(TARGET_PPC64) 2067 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2068 tcg_gen_rotli_i64(t_ra, t_ra, sh); 2069 tcg_gen_andi_i64(t_ra, t_ra, mask); 2070 #else 2071 g_assert_not_reached(); 2072 #endif 2073 } 2074 } 2075 if (unlikely(Rc(ctx->opcode) != 0)) { 2076 gen_set_Rc0(ctx, t_ra); 2077 } 2078 } 2079 2080 /* rlwnm & rlwnm. */ 2081 static void gen_rlwnm(DisasContext *ctx) 2082 { 2083 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2084 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2085 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2086 uint32_t mb = MB(ctx->opcode); 2087 uint32_t me = ME(ctx->opcode); 2088 target_ulong mask; 2089 bool mask_in_32b = true; 2090 2091 #if defined(TARGET_PPC64) 2092 mb += 32; 2093 me += 32; 2094 #endif 2095 mask = MASK(mb, me); 2096 2097 #if defined(TARGET_PPC64) 2098 if (mask > 0xffffffffu) { 2099 mask_in_32b = false; 2100 } 2101 #endif 2102 if (mask_in_32b) { 2103 TCGv_i32 t0 = tcg_temp_new_i32(); 2104 TCGv_i32 t1 = tcg_temp_new_i32(); 2105 tcg_gen_trunc_tl_i32(t0, t_rb); 2106 tcg_gen_trunc_tl_i32(t1, t_rs); 2107 tcg_gen_andi_i32(t0, t0, 0x1f); 2108 tcg_gen_rotl_i32(t1, t1, t0); 2109 tcg_gen_extu_i32_tl(t_ra, t1); 2110 } else { 2111 #if defined(TARGET_PPC64) 2112 TCGv_i64 t0 = tcg_temp_new_i64(); 2113 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2114 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2115 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2116 #else 2117 g_assert_not_reached(); 2118 #endif 2119 } 2120 2121 tcg_gen_andi_tl(t_ra, t_ra, mask); 2122 2123 if (unlikely(Rc(ctx->opcode) != 0)) { 2124 gen_set_Rc0(ctx, t_ra); 2125 } 2126 } 2127 2128 #if defined(TARGET_PPC64) 2129 #define GEN_PPC64_R2(name, opc1, opc2) \ 2130 static void glue(gen_, name##0)(DisasContext *ctx) \ 2131 { \ 2132 gen_##name(ctx, 0); \ 2133 } \ 2134 \ 2135 static void glue(gen_, name##1)(DisasContext *ctx) \ 2136 { \ 2137 gen_##name(ctx, 1); \ 2138 } 2139 #define GEN_PPC64_R4(name, opc1, opc2) \ 2140 static void glue(gen_, name##0)(DisasContext *ctx) \ 2141 { \ 2142 gen_##name(ctx, 0, 0); \ 2143 } \ 2144 \ 2145 static void glue(gen_, name##1)(DisasContext *ctx) \ 2146 { \ 2147 gen_##name(ctx, 0, 1); \ 2148 } \ 2149 \ 2150 static void glue(gen_, name##2)(DisasContext *ctx) \ 2151 { \ 2152 gen_##name(ctx, 1, 0); \ 2153 } \ 2154 \ 2155 static void glue(gen_, name##3)(DisasContext *ctx) \ 2156 { \ 2157 gen_##name(ctx, 1, 1); \ 2158 } 2159 2160 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2161 { 2162 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2163 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2164 int len = me - mb + 1; 2165 int rsh = (64 - sh) & 63; 2166 2167 if (sh != 0 && len > 0 && me == (63 - sh)) { 2168 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2169 } else if (me == 63 && rsh + len <= 64) { 2170 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2171 } else { 2172 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2173 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2174 } 2175 if (unlikely(Rc(ctx->opcode) != 0)) { 2176 gen_set_Rc0(ctx, t_ra); 2177 } 2178 } 2179 2180 /* rldicl - rldicl. */ 2181 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2182 { 2183 uint32_t sh, mb; 2184 2185 sh = SH(ctx->opcode) | (shn << 5); 2186 mb = MB(ctx->opcode) | (mbn << 5); 2187 gen_rldinm(ctx, mb, 63, sh); 2188 } 2189 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2190 2191 /* rldicr - rldicr. */ 2192 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2193 { 2194 uint32_t sh, me; 2195 2196 sh = SH(ctx->opcode) | (shn << 5); 2197 me = MB(ctx->opcode) | (men << 5); 2198 gen_rldinm(ctx, 0, me, sh); 2199 } 2200 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2201 2202 /* rldic - rldic. */ 2203 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2204 { 2205 uint32_t sh, mb; 2206 2207 sh = SH(ctx->opcode) | (shn << 5); 2208 mb = MB(ctx->opcode) | (mbn << 5); 2209 gen_rldinm(ctx, mb, 63 - sh, sh); 2210 } 2211 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2212 2213 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2214 { 2215 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2216 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2217 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2218 TCGv t0; 2219 2220 t0 = tcg_temp_new(); 2221 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2222 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2223 2224 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2225 if (unlikely(Rc(ctx->opcode) != 0)) { 2226 gen_set_Rc0(ctx, t_ra); 2227 } 2228 } 2229 2230 /* rldcl - rldcl. */ 2231 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2232 { 2233 uint32_t mb; 2234 2235 mb = MB(ctx->opcode) | (mbn << 5); 2236 gen_rldnm(ctx, mb, 63); 2237 } 2238 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2239 2240 /* rldcr - rldcr. */ 2241 static inline void gen_rldcr(DisasContext *ctx, int men) 2242 { 2243 uint32_t me; 2244 2245 me = MB(ctx->opcode) | (men << 5); 2246 gen_rldnm(ctx, 0, me); 2247 } 2248 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2249 2250 /* rldimi - rldimi. */ 2251 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2252 { 2253 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2254 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2255 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2256 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2257 uint32_t me = 63 - sh; 2258 2259 if (mb <= me) { 2260 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2261 } else { 2262 target_ulong mask = MASK(mb, me); 2263 TCGv t1 = tcg_temp_new(); 2264 2265 tcg_gen_rotli_tl(t1, t_rs, sh); 2266 tcg_gen_andi_tl(t1, t1, mask); 2267 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2268 tcg_gen_or_tl(t_ra, t_ra, t1); 2269 } 2270 if (unlikely(Rc(ctx->opcode) != 0)) { 2271 gen_set_Rc0(ctx, t_ra); 2272 } 2273 } 2274 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2275 #endif 2276 2277 /*** Integer shift ***/ 2278 2279 /* slw & slw. */ 2280 static void gen_slw(DisasContext *ctx) 2281 { 2282 TCGv t0, t1; 2283 2284 t0 = tcg_temp_new(); 2285 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2286 #if defined(TARGET_PPC64) 2287 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2288 tcg_gen_sari_tl(t0, t0, 0x3f); 2289 #else 2290 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2291 tcg_gen_sari_tl(t0, t0, 0x1f); 2292 #endif 2293 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2294 t1 = tcg_temp_new(); 2295 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2296 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2297 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2298 if (unlikely(Rc(ctx->opcode) != 0)) { 2299 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2300 } 2301 } 2302 2303 /* sraw & sraw. */ 2304 static void gen_sraw(DisasContext *ctx) 2305 { 2306 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, 2307 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2308 if (unlikely(Rc(ctx->opcode) != 0)) { 2309 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2310 } 2311 } 2312 2313 /* srawi & srawi. */ 2314 static void gen_srawi(DisasContext *ctx) 2315 { 2316 int sh = SH(ctx->opcode); 2317 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2318 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2319 if (sh == 0) { 2320 tcg_gen_ext32s_tl(dst, src); 2321 tcg_gen_movi_tl(cpu_ca, 0); 2322 if (is_isa300(ctx)) { 2323 tcg_gen_movi_tl(cpu_ca32, 0); 2324 } 2325 } else { 2326 TCGv t0; 2327 tcg_gen_ext32s_tl(dst, src); 2328 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2329 t0 = tcg_temp_new(); 2330 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2331 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2332 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2333 if (is_isa300(ctx)) { 2334 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2335 } 2336 tcg_gen_sari_tl(dst, dst, sh); 2337 } 2338 if (unlikely(Rc(ctx->opcode) != 0)) { 2339 gen_set_Rc0(ctx, dst); 2340 } 2341 } 2342 2343 /* srw & srw. */ 2344 static void gen_srw(DisasContext *ctx) 2345 { 2346 TCGv t0, t1; 2347 2348 t0 = tcg_temp_new(); 2349 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2350 #if defined(TARGET_PPC64) 2351 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2352 tcg_gen_sari_tl(t0, t0, 0x3f); 2353 #else 2354 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2355 tcg_gen_sari_tl(t0, t0, 0x1f); 2356 #endif 2357 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2358 tcg_gen_ext32u_tl(t0, t0); 2359 t1 = tcg_temp_new(); 2360 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2361 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2362 if (unlikely(Rc(ctx->opcode) != 0)) { 2363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2364 } 2365 } 2366 2367 #if defined(TARGET_PPC64) 2368 /* sld & sld. */ 2369 static void gen_sld(DisasContext *ctx) 2370 { 2371 TCGv t0, t1; 2372 2373 t0 = tcg_temp_new(); 2374 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2375 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2376 tcg_gen_sari_tl(t0, t0, 0x3f); 2377 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2378 t1 = tcg_temp_new(); 2379 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2380 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2381 if (unlikely(Rc(ctx->opcode) != 0)) { 2382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2383 } 2384 } 2385 2386 /* srad & srad. */ 2387 static void gen_srad(DisasContext *ctx) 2388 { 2389 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, 2390 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2391 if (unlikely(Rc(ctx->opcode) != 0)) { 2392 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2393 } 2394 } 2395 /* sradi & sradi. */ 2396 static inline void gen_sradi(DisasContext *ctx, int n) 2397 { 2398 int sh = SH(ctx->opcode) + (n << 5); 2399 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2400 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2401 if (sh == 0) { 2402 tcg_gen_mov_tl(dst, src); 2403 tcg_gen_movi_tl(cpu_ca, 0); 2404 if (is_isa300(ctx)) { 2405 tcg_gen_movi_tl(cpu_ca32, 0); 2406 } 2407 } else { 2408 TCGv t0; 2409 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2410 t0 = tcg_temp_new(); 2411 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2412 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2413 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2414 if (is_isa300(ctx)) { 2415 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2416 } 2417 tcg_gen_sari_tl(dst, src, sh); 2418 } 2419 if (unlikely(Rc(ctx->opcode) != 0)) { 2420 gen_set_Rc0(ctx, dst); 2421 } 2422 } 2423 2424 static void gen_sradi0(DisasContext *ctx) 2425 { 2426 gen_sradi(ctx, 0); 2427 } 2428 2429 static void gen_sradi1(DisasContext *ctx) 2430 { 2431 gen_sradi(ctx, 1); 2432 } 2433 2434 /* extswsli & extswsli. */ 2435 static inline void gen_extswsli(DisasContext *ctx, int n) 2436 { 2437 int sh = SH(ctx->opcode) + (n << 5); 2438 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2439 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2440 2441 tcg_gen_ext32s_tl(dst, src); 2442 tcg_gen_shli_tl(dst, dst, sh); 2443 if (unlikely(Rc(ctx->opcode) != 0)) { 2444 gen_set_Rc0(ctx, dst); 2445 } 2446 } 2447 2448 static void gen_extswsli0(DisasContext *ctx) 2449 { 2450 gen_extswsli(ctx, 0); 2451 } 2452 2453 static void gen_extswsli1(DisasContext *ctx) 2454 { 2455 gen_extswsli(ctx, 1); 2456 } 2457 2458 /* srd & srd. */ 2459 static void gen_srd(DisasContext *ctx) 2460 { 2461 TCGv t0, t1; 2462 2463 t0 = tcg_temp_new(); 2464 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2465 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2466 tcg_gen_sari_tl(t0, t0, 0x3f); 2467 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2468 t1 = tcg_temp_new(); 2469 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2470 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2471 if (unlikely(Rc(ctx->opcode) != 0)) { 2472 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2473 } 2474 } 2475 #endif 2476 2477 /*** Addressing modes ***/ 2478 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2479 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2480 target_long maskl) 2481 { 2482 target_long simm = SIMM(ctx->opcode); 2483 2484 simm &= ~maskl; 2485 if (rA(ctx->opcode) == 0) { 2486 if (NARROW_MODE(ctx)) { 2487 simm = (uint32_t)simm; 2488 } 2489 tcg_gen_movi_tl(EA, simm); 2490 } else if (likely(simm != 0)) { 2491 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2492 if (NARROW_MODE(ctx)) { 2493 tcg_gen_ext32u_tl(EA, EA); 2494 } 2495 } else { 2496 if (NARROW_MODE(ctx)) { 2497 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2498 } else { 2499 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2500 } 2501 } 2502 } 2503 2504 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2505 { 2506 if (rA(ctx->opcode) == 0) { 2507 if (NARROW_MODE(ctx)) { 2508 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2509 } else { 2510 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2511 } 2512 } else { 2513 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2514 if (NARROW_MODE(ctx)) { 2515 tcg_gen_ext32u_tl(EA, EA); 2516 } 2517 } 2518 } 2519 2520 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2521 { 2522 if (rA(ctx->opcode) == 0) { 2523 tcg_gen_movi_tl(EA, 0); 2524 } else if (NARROW_MODE(ctx)) { 2525 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2526 } else { 2527 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2528 } 2529 } 2530 2531 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2532 target_long val) 2533 { 2534 tcg_gen_addi_tl(ret, arg1, val); 2535 if (NARROW_MODE(ctx)) { 2536 tcg_gen_ext32u_tl(ret, ret); 2537 } 2538 } 2539 2540 static inline void gen_align_no_le(DisasContext *ctx) 2541 { 2542 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2543 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2544 } 2545 2546 /* EA <- {(ra == 0) ? 0 : GPR[ra]} + displ */ 2547 static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 2548 { 2549 TCGv ea = tcg_temp_new(); 2550 if (ra) { 2551 tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 2552 } else { 2553 tcg_gen_mov_tl(ea, displ); 2554 } 2555 if (NARROW_MODE(ctx)) { 2556 tcg_gen_ext32u_tl(ea, ea); 2557 } 2558 return ea; 2559 } 2560 2561 #if defined(TARGET_PPC64) 2562 /* EA <- (ra == 0) ? 0 : GPR[ra] */ 2563 static TCGv do_ea_calc_ra(DisasContext *ctx, int ra) 2564 { 2565 TCGv EA = tcg_temp_new(); 2566 if (!ra) { 2567 tcg_gen_movi_tl(EA, 0); 2568 } else if (NARROW_MODE(ctx)) { 2569 tcg_gen_ext32u_tl(EA, cpu_gpr[ra]); 2570 } else { 2571 tcg_gen_mov_tl(EA, cpu_gpr[ra]); 2572 } 2573 return EA; 2574 } 2575 #endif 2576 2577 /*** Integer load ***/ 2578 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2579 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2580 2581 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2582 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2583 TCGv val, \ 2584 TCGv addr) \ 2585 { \ 2586 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2587 } 2588 2589 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2590 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2591 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2592 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2593 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2594 2595 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2596 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2597 2598 #define GEN_QEMU_LOAD_64(ldop, op) \ 2599 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2600 TCGv_i64 val, \ 2601 TCGv addr) \ 2602 { \ 2603 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2604 } 2605 2606 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2607 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2608 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2609 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2610 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 2611 2612 #if defined(TARGET_PPC64) 2613 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 2614 #endif 2615 2616 #define GEN_QEMU_STORE_TL(stop, op) \ 2617 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2618 TCGv val, \ 2619 TCGv addr) \ 2620 { \ 2621 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2622 } 2623 2624 #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 2625 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2626 #endif 2627 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2628 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2629 2630 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2631 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2632 2633 #define GEN_QEMU_STORE_64(stop, op) \ 2634 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2635 TCGv_i64 val, \ 2636 TCGv addr) \ 2637 { \ 2638 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2639 } 2640 2641 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2642 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2643 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2644 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 2645 2646 #if defined(TARGET_PPC64) 2647 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 2648 #endif 2649 2650 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2651 static void glue(gen_, name##x)(DisasContext *ctx) \ 2652 { \ 2653 TCGv EA; \ 2654 chk(ctx); \ 2655 gen_set_access_type(ctx, ACCESS_INT); \ 2656 EA = tcg_temp_new(); \ 2657 gen_addr_reg_index(ctx, EA); \ 2658 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2659 } 2660 2661 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2662 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2663 2664 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2665 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2666 2667 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2668 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2669 { \ 2670 TCGv EA; \ 2671 CHK_SV(ctx); \ 2672 gen_set_access_type(ctx, ACCESS_INT); \ 2673 EA = tcg_temp_new(); \ 2674 gen_addr_reg_index(ctx, EA); \ 2675 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2676 } 2677 2678 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2679 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2680 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2681 #if defined(TARGET_PPC64) 2682 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 2683 #endif 2684 2685 #if defined(TARGET_PPC64) 2686 /* CI load/store variants */ 2687 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2688 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2689 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2690 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2691 #endif 2692 2693 /*** Integer store ***/ 2694 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2695 static void glue(gen_, name##x)(DisasContext *ctx) \ 2696 { \ 2697 TCGv EA; \ 2698 chk(ctx); \ 2699 gen_set_access_type(ctx, ACCESS_INT); \ 2700 EA = tcg_temp_new(); \ 2701 gen_addr_reg_index(ctx, EA); \ 2702 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2703 } 2704 #define GEN_STX(name, stop, opc2, opc3, type) \ 2705 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2706 2707 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2708 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2709 2710 #define GEN_STEPX(name, stop, opc2, opc3) \ 2711 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2712 { \ 2713 TCGv EA; \ 2714 CHK_SV(ctx); \ 2715 gen_set_access_type(ctx, ACCESS_INT); \ 2716 EA = tcg_temp_new(); \ 2717 gen_addr_reg_index(ctx, EA); \ 2718 tcg_gen_qemu_st_tl( \ 2719 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2720 } 2721 2722 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2723 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2724 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2725 #if defined(TARGET_PPC64) 2726 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 2727 #endif 2728 2729 #if defined(TARGET_PPC64) 2730 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2731 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2732 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2733 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2734 #endif 2735 /*** Integer load and store with byte reverse ***/ 2736 2737 /* lhbrx */ 2738 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2739 2740 /* lwbrx */ 2741 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2742 2743 #if defined(TARGET_PPC64) 2744 /* ldbrx */ 2745 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2746 /* stdbrx */ 2747 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2748 #endif /* TARGET_PPC64 */ 2749 2750 /* sthbrx */ 2751 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2752 /* stwbrx */ 2753 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2754 2755 /*** Integer load and store multiple ***/ 2756 2757 /* lmw */ 2758 static void gen_lmw(DisasContext *ctx) 2759 { 2760 TCGv t0; 2761 TCGv_i32 t1; 2762 2763 if (ctx->le_mode) { 2764 gen_align_no_le(ctx); 2765 return; 2766 } 2767 gen_set_access_type(ctx, ACCESS_INT); 2768 t0 = tcg_temp_new(); 2769 t1 = tcg_constant_i32(rD(ctx->opcode)); 2770 gen_addr_imm_index(ctx, t0, 0); 2771 gen_helper_lmw(tcg_env, t0, t1); 2772 } 2773 2774 /* stmw */ 2775 static void gen_stmw(DisasContext *ctx) 2776 { 2777 TCGv t0; 2778 TCGv_i32 t1; 2779 2780 if (ctx->le_mode) { 2781 gen_align_no_le(ctx); 2782 return; 2783 } 2784 gen_set_access_type(ctx, ACCESS_INT); 2785 t0 = tcg_temp_new(); 2786 t1 = tcg_constant_i32(rS(ctx->opcode)); 2787 gen_addr_imm_index(ctx, t0, 0); 2788 gen_helper_stmw(tcg_env, t0, t1); 2789 } 2790 2791 /*** Integer load and store strings ***/ 2792 2793 /* lswi */ 2794 /* 2795 * PowerPC32 specification says we must generate an exception if rA is 2796 * in the range of registers to be loaded. In an other hand, IBM says 2797 * this is valid, but rA won't be loaded. For now, I'll follow the 2798 * spec... 2799 */ 2800 static void gen_lswi(DisasContext *ctx) 2801 { 2802 TCGv t0; 2803 TCGv_i32 t1, t2; 2804 int nb = NB(ctx->opcode); 2805 int start = rD(ctx->opcode); 2806 int ra = rA(ctx->opcode); 2807 int nr; 2808 2809 if (ctx->le_mode) { 2810 gen_align_no_le(ctx); 2811 return; 2812 } 2813 if (nb == 0) { 2814 nb = 32; 2815 } 2816 nr = DIV_ROUND_UP(nb, 4); 2817 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2818 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2819 return; 2820 } 2821 gen_set_access_type(ctx, ACCESS_INT); 2822 t0 = tcg_temp_new(); 2823 gen_addr_register(ctx, t0); 2824 t1 = tcg_constant_i32(nb); 2825 t2 = tcg_constant_i32(start); 2826 gen_helper_lsw(tcg_env, t0, t1, t2); 2827 } 2828 2829 /* lswx */ 2830 static void gen_lswx(DisasContext *ctx) 2831 { 2832 TCGv t0; 2833 TCGv_i32 t1, t2, t3; 2834 2835 if (ctx->le_mode) { 2836 gen_align_no_le(ctx); 2837 return; 2838 } 2839 gen_set_access_type(ctx, ACCESS_INT); 2840 t0 = tcg_temp_new(); 2841 gen_addr_reg_index(ctx, t0); 2842 t1 = tcg_constant_i32(rD(ctx->opcode)); 2843 t2 = tcg_constant_i32(rA(ctx->opcode)); 2844 t3 = tcg_constant_i32(rB(ctx->opcode)); 2845 gen_helper_lswx(tcg_env, t0, t1, t2, t3); 2846 } 2847 2848 /* stswi */ 2849 static void gen_stswi(DisasContext *ctx) 2850 { 2851 TCGv t0; 2852 TCGv_i32 t1, t2; 2853 int nb = NB(ctx->opcode); 2854 2855 if (ctx->le_mode) { 2856 gen_align_no_le(ctx); 2857 return; 2858 } 2859 gen_set_access_type(ctx, ACCESS_INT); 2860 t0 = tcg_temp_new(); 2861 gen_addr_register(ctx, t0); 2862 if (nb == 0) { 2863 nb = 32; 2864 } 2865 t1 = tcg_constant_i32(nb); 2866 t2 = tcg_constant_i32(rS(ctx->opcode)); 2867 gen_helper_stsw(tcg_env, t0, t1, t2); 2868 } 2869 2870 /* stswx */ 2871 static void gen_stswx(DisasContext *ctx) 2872 { 2873 TCGv t0; 2874 TCGv_i32 t1, t2; 2875 2876 if (ctx->le_mode) { 2877 gen_align_no_le(ctx); 2878 return; 2879 } 2880 gen_set_access_type(ctx, ACCESS_INT); 2881 t0 = tcg_temp_new(); 2882 gen_addr_reg_index(ctx, t0); 2883 t1 = tcg_temp_new_i32(); 2884 tcg_gen_trunc_tl_i32(t1, cpu_xer); 2885 tcg_gen_andi_i32(t1, t1, 0x7F); 2886 t2 = tcg_constant_i32(rS(ctx->opcode)); 2887 gen_helper_stsw(tcg_env, t0, t1, t2); 2888 } 2889 2890 #if !defined(CONFIG_USER_ONLY) 2891 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2892 { 2893 TCGv_i32 t; 2894 TCGLabel *l; 2895 2896 if (!ctx->lazy_tlb_flush) { 2897 return; 2898 } 2899 l = gen_new_label(); 2900 t = tcg_temp_new_i32(); 2901 tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); 2902 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 2903 if (global) { 2904 gen_helper_check_tlb_flush_global(tcg_env); 2905 } else { 2906 gen_helper_check_tlb_flush_local(tcg_env); 2907 } 2908 gen_set_label(l); 2909 if (global) { 2910 /* 2911 * Global TLB flush uses async-work which must run before the 2912 * next instruction, so this must be the last in the TB. 2913 */ 2914 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2915 } 2916 } 2917 #else 2918 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 2919 #endif 2920 2921 /* isync */ 2922 static void gen_isync(DisasContext *ctx) 2923 { 2924 /* 2925 * We need to check for a pending TLB flush. This can only happen in 2926 * kernel mode however so check MSR_PR 2927 */ 2928 if (!ctx->pr) { 2929 gen_check_tlb_flush(ctx, false); 2930 } 2931 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2932 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 2933 } 2934 2935 static void gen_load_locked(DisasContext *ctx, MemOp memop) 2936 { 2937 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 2938 TCGv t0 = tcg_temp_new(); 2939 2940 gen_set_access_type(ctx, ACCESS_RES); 2941 gen_addr_reg_index(ctx, t0); 2942 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); 2943 tcg_gen_mov_tl(cpu_reserve, t0); 2944 tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 2945 tcg_gen_mov_tl(cpu_reserve_val, gpr); 2946 } 2947 2948 #define LARX(name, memop) \ 2949 static void gen_##name(DisasContext *ctx) \ 2950 { \ 2951 gen_load_locked(ctx, memop); \ 2952 } 2953 2954 /* lwarx */ 2955 LARX(lbarx, MO_UB) 2956 LARX(lharx, MO_UW) 2957 LARX(lwarx, MO_UL) 2958 2959 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 2960 TCGv EA, TCGCond cond, int addend) 2961 { 2962 TCGv t = tcg_temp_new(); 2963 TCGv t2 = tcg_temp_new(); 2964 TCGv u = tcg_temp_new(); 2965 2966 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 2967 tcg_gen_addi_tl(t2, EA, memop_size(memop)); 2968 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 2969 tcg_gen_addi_tl(u, t, addend); 2970 2971 /* E.g. for fetch and increment bounded... */ 2972 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 2973 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 2974 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 2975 2976 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 2977 tcg_gen_movi_tl(u, 1 << (memop_size(memop) * 8 - 1)); 2978 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 2979 } 2980 2981 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 2982 { 2983 uint32_t gpr_FC = FC(ctx->opcode); 2984 TCGv EA = tcg_temp_new(); 2985 int rt = rD(ctx->opcode); 2986 bool need_serial; 2987 TCGv src, dst; 2988 2989 gen_addr_register(ctx, EA); 2990 dst = cpu_gpr[rt]; 2991 src = cpu_gpr[(rt + 1) & 31]; 2992 2993 need_serial = false; 2994 memop |= MO_ALIGN; 2995 switch (gpr_FC) { 2996 case 0: /* Fetch and add */ 2997 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 2998 break; 2999 case 1: /* Fetch and xor */ 3000 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3001 break; 3002 case 2: /* Fetch and or */ 3003 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3004 break; 3005 case 3: /* Fetch and 'and' */ 3006 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3007 break; 3008 case 4: /* Fetch and max unsigned */ 3009 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3010 break; 3011 case 5: /* Fetch and max signed */ 3012 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3013 break; 3014 case 6: /* Fetch and min unsigned */ 3015 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3016 break; 3017 case 7: /* Fetch and min signed */ 3018 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3019 break; 3020 case 8: /* Swap */ 3021 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3022 break; 3023 3024 case 16: /* Compare and swap not equal */ 3025 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3026 need_serial = true; 3027 } else { 3028 TCGv t0 = tcg_temp_new(); 3029 TCGv t1 = tcg_temp_new(); 3030 3031 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3032 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3033 tcg_gen_mov_tl(t1, src); 3034 } else { 3035 tcg_gen_ext32u_tl(t1, src); 3036 } 3037 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3038 cpu_gpr[(rt + 2) & 31], t0); 3039 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3040 tcg_gen_mov_tl(dst, t0); 3041 } 3042 break; 3043 3044 case 24: /* Fetch and increment bounded */ 3045 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3046 need_serial = true; 3047 } else { 3048 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3049 } 3050 break; 3051 case 25: /* Fetch and increment equal */ 3052 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3053 need_serial = true; 3054 } else { 3055 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3056 } 3057 break; 3058 case 28: /* Fetch and decrement bounded */ 3059 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3060 need_serial = true; 3061 } else { 3062 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3063 } 3064 break; 3065 3066 default: 3067 /* invoke data storage error handler */ 3068 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3069 } 3070 3071 if (need_serial) { 3072 /* Restart with exclusive lock. */ 3073 gen_helper_exit_atomic(tcg_env); 3074 ctx->base.is_jmp = DISAS_NORETURN; 3075 } 3076 } 3077 3078 static void gen_lwat(DisasContext *ctx) 3079 { 3080 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3081 } 3082 3083 #ifdef TARGET_PPC64 3084 static void gen_ldat(DisasContext *ctx) 3085 { 3086 gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 3087 } 3088 #endif 3089 3090 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3091 { 3092 uint32_t gpr_FC = FC(ctx->opcode); 3093 TCGv EA = tcg_temp_new(); 3094 TCGv src, discard; 3095 3096 gen_addr_register(ctx, EA); 3097 src = cpu_gpr[rD(ctx->opcode)]; 3098 discard = tcg_temp_new(); 3099 3100 memop |= MO_ALIGN; 3101 switch (gpr_FC) { 3102 case 0: /* add and Store */ 3103 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3104 break; 3105 case 1: /* xor and Store */ 3106 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3107 break; 3108 case 2: /* Or and Store */ 3109 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3110 break; 3111 case 3: /* 'and' and Store */ 3112 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3113 break; 3114 case 4: /* Store max unsigned */ 3115 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3116 break; 3117 case 5: /* Store max signed */ 3118 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3119 break; 3120 case 6: /* Store min unsigned */ 3121 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3122 break; 3123 case 7: /* Store min signed */ 3124 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3125 break; 3126 case 24: /* Store twin */ 3127 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3128 /* Restart with exclusive lock. */ 3129 gen_helper_exit_atomic(tcg_env); 3130 ctx->base.is_jmp = DISAS_NORETURN; 3131 } else { 3132 TCGv t = tcg_temp_new(); 3133 TCGv t2 = tcg_temp_new(); 3134 TCGv s = tcg_temp_new(); 3135 TCGv s2 = tcg_temp_new(); 3136 TCGv ea_plus_s = tcg_temp_new(); 3137 3138 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3139 tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); 3140 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3141 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3142 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3143 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3144 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3145 } 3146 break; 3147 default: 3148 /* invoke data storage error handler */ 3149 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3150 } 3151 } 3152 3153 static void gen_stwat(DisasContext *ctx) 3154 { 3155 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3156 } 3157 3158 #ifdef TARGET_PPC64 3159 static void gen_stdat(DisasContext *ctx) 3160 { 3161 gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 3162 } 3163 #endif 3164 3165 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3166 { 3167 TCGLabel *lfail; 3168 TCGv EA; 3169 TCGv cr0; 3170 TCGv t0; 3171 int rs = rS(ctx->opcode); 3172 3173 lfail = gen_new_label(); 3174 EA = tcg_temp_new(); 3175 cr0 = tcg_temp_new(); 3176 t0 = tcg_temp_new(); 3177 3178 tcg_gen_mov_tl(cr0, cpu_so); 3179 gen_set_access_type(ctx, ACCESS_RES); 3180 gen_addr_reg_index(ctx, EA); 3181 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3182 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 3183 3184 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3185 cpu_gpr[rs], ctx->mem_idx, 3186 DEF_MEMOP(memop) | MO_ALIGN); 3187 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3188 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3189 tcg_gen_or_tl(cr0, cr0, t0); 3190 3191 gen_set_label(lfail); 3192 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3193 tcg_gen_movi_tl(cpu_reserve, -1); 3194 } 3195 3196 #define STCX(name, memop) \ 3197 static void gen_##name(DisasContext *ctx) \ 3198 { \ 3199 gen_conditional_store(ctx, memop); \ 3200 } 3201 3202 STCX(stbcx_, MO_UB) 3203 STCX(sthcx_, MO_UW) 3204 STCX(stwcx_, MO_UL) 3205 3206 #if defined(TARGET_PPC64) 3207 /* ldarx */ 3208 LARX(ldarx, MO_UQ) 3209 /* stdcx. */ 3210 STCX(stdcx_, MO_UQ) 3211 3212 /* lqarx */ 3213 static void gen_lqarx(DisasContext *ctx) 3214 { 3215 int rd = rD(ctx->opcode); 3216 TCGv EA, hi, lo; 3217 TCGv_i128 t16; 3218 3219 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3220 (rd == rB(ctx->opcode)))) { 3221 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3222 return; 3223 } 3224 3225 gen_set_access_type(ctx, ACCESS_RES); 3226 EA = tcg_temp_new(); 3227 gen_addr_reg_index(ctx, EA); 3228 3229 /* Note that the low part is always in RD+1, even in LE mode. */ 3230 lo = cpu_gpr[rd + 1]; 3231 hi = cpu_gpr[rd]; 3232 3233 t16 = tcg_temp_new_i128(); 3234 tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 3235 tcg_gen_extr_i128_i64(lo, hi, t16); 3236 3237 tcg_gen_mov_tl(cpu_reserve, EA); 3238 tcg_gen_movi_tl(cpu_reserve_length, 16); 3239 tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); 3240 tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); 3241 } 3242 3243 /* stqcx. */ 3244 static void gen_stqcx_(DisasContext *ctx) 3245 { 3246 TCGLabel *lfail; 3247 TCGv EA, t0, t1; 3248 TCGv cr0; 3249 TCGv_i128 cmp, val; 3250 int rs = rS(ctx->opcode); 3251 3252 if (unlikely(rs & 1)) { 3253 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3254 return; 3255 } 3256 3257 lfail = gen_new_label(); 3258 EA = tcg_temp_new(); 3259 cr0 = tcg_temp_new(); 3260 3261 tcg_gen_mov_tl(cr0, cpu_so); 3262 gen_set_access_type(ctx, ACCESS_RES); 3263 gen_addr_reg_index(ctx, EA); 3264 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 3265 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 3266 3267 cmp = tcg_temp_new_i128(); 3268 val = tcg_temp_new_i128(); 3269 3270 tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 3271 3272 /* Note that the low part is always in RS+1, even in LE mode. */ 3273 tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 3274 3275 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3276 DEF_MEMOP(MO_128 | MO_ALIGN)); 3277 3278 t0 = tcg_temp_new(); 3279 t1 = tcg_temp_new(); 3280 tcg_gen_extr_i128_i64(t1, t0, val); 3281 3282 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3283 tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3284 tcg_gen_or_tl(t0, t0, t1); 3285 3286 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3287 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3288 tcg_gen_or_tl(cr0, cr0, t0); 3289 3290 gen_set_label(lfail); 3291 tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3292 tcg_gen_movi_tl(cpu_reserve, -1); 3293 } 3294 #endif /* defined(TARGET_PPC64) */ 3295 3296 /* wait */ 3297 static void gen_wait(DisasContext *ctx) 3298 { 3299 uint32_t wc; 3300 3301 if (ctx->insns_flags & PPC_WAIT) { 3302 /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 3303 3304 if (ctx->insns_flags2 & PPC2_PM_ISA206) { 3305 /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 3306 wc = WC(ctx->opcode); 3307 } else { 3308 wc = 0; 3309 } 3310 3311 } else if (ctx->insns_flags2 & PPC2_ISA300) { 3312 /* v3.0 defines a new 'wait' encoding. */ 3313 wc = WC(ctx->opcode); 3314 if (ctx->insns_flags2 & PPC2_ISA310) { 3315 uint32_t pl = PL(ctx->opcode); 3316 3317 /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 3318 if (wc == 3) { 3319 gen_invalid(ctx); 3320 return; 3321 } 3322 3323 /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 3324 if (pl > 0 && wc != 2) { 3325 gen_invalid(ctx); 3326 return; 3327 } 3328 3329 } else { /* ISA300 */ 3330 /* WC 1-3 are reserved */ 3331 if (wc > 0) { 3332 gen_invalid(ctx); 3333 return; 3334 } 3335 } 3336 3337 } else { 3338 warn_report("wait instruction decoded with wrong ISA flags."); 3339 gen_invalid(ctx); 3340 return; 3341 } 3342 3343 /* 3344 * wait without WC field or with WC=0 waits for an exception / interrupt 3345 * to occur. 3346 */ 3347 if (wc == 0) { 3348 TCGv_i32 t0 = tcg_constant_i32(1); 3349 tcg_gen_st_i32(t0, tcg_env, 3350 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3351 /* Stop translation, as the CPU is supposed to sleep from now */ 3352 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3353 } 3354 3355 /* 3356 * Other wait types must not just wait until an exception occurs because 3357 * ignoring their other wake-up conditions could cause a hang. 3358 * 3359 * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 3360 * no-ops. 3361 * 3362 * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 3363 * 3364 * wc=2 waits for an implementation-specific condition, such could be 3365 * always true, so it can be implemented as a no-op. 3366 * 3367 * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 3368 * 3369 * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 3370 * Reservation-loss may have implementation-specific conditions, so it 3371 * can be implemented as a no-op. 3372 * 3373 * wc=2 waits for an exception or an amount of time to pass. This 3374 * amount is implementation-specific so it can be implemented as a 3375 * no-op. 3376 * 3377 * ISA v3.1 allows for execution to resume "in the rare case of 3378 * an implementation-dependent event", so in any case software must 3379 * not depend on the architected resumption condition to become 3380 * true, so no-op implementations should be architecturally correct 3381 * (if suboptimal). 3382 */ 3383 } 3384 3385 #if defined(TARGET_PPC64) 3386 static void gen_doze(DisasContext *ctx) 3387 { 3388 #if defined(CONFIG_USER_ONLY) 3389 GEN_PRIV(ctx); 3390 #else 3391 TCGv_i32 t; 3392 3393 CHK_HV(ctx); 3394 translator_io_start(&ctx->base); 3395 t = tcg_constant_i32(PPC_PM_DOZE); 3396 gen_helper_pminsn(tcg_env, t); 3397 /* Stop translation, as the CPU is supposed to sleep from now */ 3398 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3399 #endif /* defined(CONFIG_USER_ONLY) */ 3400 } 3401 3402 static void gen_nap(DisasContext *ctx) 3403 { 3404 #if defined(CONFIG_USER_ONLY) 3405 GEN_PRIV(ctx); 3406 #else 3407 TCGv_i32 t; 3408 3409 CHK_HV(ctx); 3410 translator_io_start(&ctx->base); 3411 t = tcg_constant_i32(PPC_PM_NAP); 3412 gen_helper_pminsn(tcg_env, t); 3413 /* Stop translation, as the CPU is supposed to sleep from now */ 3414 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3415 #endif /* defined(CONFIG_USER_ONLY) */ 3416 } 3417 3418 static void gen_stop(DisasContext *ctx) 3419 { 3420 #if defined(CONFIG_USER_ONLY) 3421 GEN_PRIV(ctx); 3422 #else 3423 TCGv_i32 t; 3424 3425 CHK_HV(ctx); 3426 translator_io_start(&ctx->base); 3427 t = tcg_constant_i32(PPC_PM_STOP); 3428 gen_helper_pminsn(tcg_env, t); 3429 /* Stop translation, as the CPU is supposed to sleep from now */ 3430 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3431 #endif /* defined(CONFIG_USER_ONLY) */ 3432 } 3433 3434 static void gen_sleep(DisasContext *ctx) 3435 { 3436 #if defined(CONFIG_USER_ONLY) 3437 GEN_PRIV(ctx); 3438 #else 3439 TCGv_i32 t; 3440 3441 CHK_HV(ctx); 3442 translator_io_start(&ctx->base); 3443 t = tcg_constant_i32(PPC_PM_SLEEP); 3444 gen_helper_pminsn(tcg_env, t); 3445 /* Stop translation, as the CPU is supposed to sleep from now */ 3446 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3447 #endif /* defined(CONFIG_USER_ONLY) */ 3448 } 3449 3450 static void gen_rvwinkle(DisasContext *ctx) 3451 { 3452 #if defined(CONFIG_USER_ONLY) 3453 GEN_PRIV(ctx); 3454 #else 3455 TCGv_i32 t; 3456 3457 CHK_HV(ctx); 3458 translator_io_start(&ctx->base); 3459 t = tcg_constant_i32(PPC_PM_RVWINKLE); 3460 gen_helper_pminsn(tcg_env, t); 3461 /* Stop translation, as the CPU is supposed to sleep from now */ 3462 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3463 #endif /* defined(CONFIG_USER_ONLY) */ 3464 } 3465 3466 static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, TCGv value) 3467 { 3468 TCGv_ptr tmp = tcg_temp_new_ptr(); 3469 3470 /* add base and offset to get address of bhrb entry */ 3471 tcg_gen_add_ptr(tmp, base, (TCGv_ptr)offset); 3472 3473 /* store value into bhrb at bhrb_offset */ 3474 tcg_gen_st_i64(value, tmp, 0); 3475 3476 /* add 8 to current bhrb_offset */ 3477 tcg_gen_addi_tl(offset, offset, 8); 3478 3479 /* apply offset mask */ 3480 tcg_gen_and_tl(offset, offset, mask); 3481 3482 return offset; 3483 } 3484 #endif /* #if defined(TARGET_PPC64) */ 3485 3486 static inline void gen_update_branch_history(DisasContext *ctx, 3487 target_ulong nip, 3488 TCGv target, 3489 target_long inst_type) 3490 { 3491 #if defined(TARGET_PPC64) 3492 TCGv_ptr base; 3493 TCGv tmp; 3494 TCGv offset; 3495 TCGv mask; 3496 TCGLabel *no_update; 3497 3498 if (ctx->has_cfar) { 3499 tcg_gen_movi_tl(cpu_cfar, nip); 3500 } 3501 3502 if (!ctx->has_bhrb || 3503 !ctx->bhrb_enable || 3504 inst_type == BHRB_TYPE_NORECORD) { 3505 return; 3506 } 3507 3508 tmp = tcg_temp_new(); 3509 no_update = gen_new_label(); 3510 3511 /* check for bhrb filtering */ 3512 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter)); 3513 tcg_gen_andi_tl(tmp, tmp, inst_type); 3514 tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update); 3515 3516 base = tcg_temp_new_ptr(); 3517 offset = tcg_temp_new(); 3518 mask = tcg_temp_new(); 3519 3520 /* load bhrb base address */ 3521 tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base)); 3522 3523 /* load current bhrb_offset */ 3524 tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3525 3526 /* load a BHRB offset mask */ 3527 tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask)); 3528 3529 offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip)); 3530 3531 /* Also record the target address for XL-Form branches */ 3532 if (inst_type & BHRB_TYPE_XL_FORM) { 3533 3534 /* Set the 'T' bit for target entries */ 3535 tcg_gen_ori_tl(tmp, target, 0x2); 3536 3537 offset = gen_write_bhrb(base, offset, mask, tmp); 3538 } 3539 3540 /* save updated bhrb_offset for next time */ 3541 tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); 3542 3543 gen_set_label(no_update); 3544 #endif 3545 } 3546 3547 #if defined(TARGET_PPC64) 3548 static void pmu_count_insns(DisasContext *ctx) 3549 { 3550 /* 3551 * Do not bother calling the helper if the PMU isn't counting 3552 * instructions. 3553 */ 3554 if (!ctx->pmu_insn_cnt) { 3555 return; 3556 } 3557 3558 #if !defined(CONFIG_USER_ONLY) 3559 TCGLabel *l; 3560 TCGv t0; 3561 3562 /* 3563 * The PMU insns_inc() helper stops the internal PMU timer if a 3564 * counter overflows happens. In that case, if the guest is 3565 * running with icount and we do not handle it beforehand, 3566 * the helper can trigger a 'bad icount read'. 3567 */ 3568 translator_io_start(&ctx->base); 3569 3570 /* Avoid helper calls when only PMC5-6 are enabled. */ 3571 if (!ctx->pmc_other) { 3572 l = gen_new_label(); 3573 t0 = tcg_temp_new(); 3574 3575 gen_load_spr(t0, SPR_POWER_PMC5); 3576 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3577 gen_store_spr(SPR_POWER_PMC5, t0); 3578 /* Check for overflow, if it's enabled */ 3579 if (ctx->mmcr0_pmcjce) { 3580 tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 3581 gen_helper_handle_pmc5_overflow(tcg_env); 3582 } 3583 3584 gen_set_label(l); 3585 } else { 3586 gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); 3587 } 3588 #else 3589 /* 3590 * User mode can read (but not write) PMC5 and start/stop 3591 * the PMU via MMCR0_FC. In this case just increment 3592 * PMC5 with base.num_insns. 3593 */ 3594 TCGv t0 = tcg_temp_new(); 3595 3596 gen_load_spr(t0, SPR_POWER_PMC5); 3597 tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 3598 gen_store_spr(SPR_POWER_PMC5, t0); 3599 #endif /* #if !defined(CONFIG_USER_ONLY) */ 3600 } 3601 #else 3602 static void pmu_count_insns(DisasContext *ctx) 3603 { 3604 return; 3605 } 3606 #endif /* #if defined(TARGET_PPC64) */ 3607 3608 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3609 { 3610 if (unlikely(ctx->singlestep_enabled)) { 3611 return false; 3612 } 3613 return translator_use_goto_tb(&ctx->base, dest); 3614 } 3615 3616 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3617 { 3618 if (unlikely(ctx->singlestep_enabled)) { 3619 gen_debug_exception(ctx, false); 3620 } else { 3621 /* 3622 * tcg_gen_lookup_and_goto_ptr will exit the TB if 3623 * CF_NO_GOTO_PTR is set. Count insns now. 3624 */ 3625 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 3626 pmu_count_insns(ctx); 3627 } 3628 3629 tcg_gen_lookup_and_goto_ptr(); 3630 } 3631 } 3632 3633 /*** Branch ***/ 3634 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3635 { 3636 if (NARROW_MODE(ctx)) { 3637 dest = (uint32_t) dest; 3638 } 3639 if (use_goto_tb(ctx, dest)) { 3640 pmu_count_insns(ctx); 3641 tcg_gen_goto_tb(n); 3642 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3643 tcg_gen_exit_tb(ctx->base.tb, n); 3644 } else { 3645 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3646 gen_lookup_and_goto_ptr(ctx); 3647 } 3648 } 3649 3650 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3651 { 3652 if (NARROW_MODE(ctx)) { 3653 nip = (uint32_t)nip; 3654 } 3655 tcg_gen_movi_tl(cpu_lr, nip); 3656 } 3657 3658 /* b ba bl bla */ 3659 static void gen_b(DisasContext *ctx) 3660 { 3661 target_ulong li, target; 3662 3663 /* sign extend LI */ 3664 li = LI(ctx->opcode); 3665 li = (li ^ 0x02000000) - 0x02000000; 3666 if (likely(AA(ctx->opcode) == 0)) { 3667 target = ctx->cia + li; 3668 } else { 3669 target = li; 3670 } 3671 if (LK(ctx->opcode)) { 3672 gen_setlr(ctx, ctx->base.pc_next); 3673 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); 3674 } else { 3675 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); 3676 } 3677 gen_goto_tb(ctx, 0, target); 3678 ctx->base.is_jmp = DISAS_NORETURN; 3679 } 3680 3681 #define BCOND_IM 0 3682 #define BCOND_LR 1 3683 #define BCOND_CTR 2 3684 #define BCOND_TAR 3 3685 3686 static void gen_bcond(DisasContext *ctx, int type) 3687 { 3688 uint32_t bo = BO(ctx->opcode); 3689 TCGLabel *l1; 3690 TCGv target; 3691 target_long bhrb_type = BHRB_TYPE_OTHER; 3692 3693 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3694 target = tcg_temp_new(); 3695 if (type == BCOND_CTR) { 3696 tcg_gen_mov_tl(target, cpu_ctr); 3697 } else if (type == BCOND_TAR) { 3698 gen_load_spr(target, SPR_TAR); 3699 } else { 3700 tcg_gen_mov_tl(target, cpu_lr); 3701 } 3702 if (!LK(ctx->opcode)) { 3703 bhrb_type |= BHRB_TYPE_INDIRECT; 3704 } 3705 bhrb_type |= BHRB_TYPE_XL_FORM; 3706 } else { 3707 target = NULL; 3708 } 3709 if (LK(ctx->opcode)) { 3710 gen_setlr(ctx, ctx->base.pc_next); 3711 bhrb_type |= BHRB_TYPE_CALL; 3712 } 3713 l1 = gen_new_label(); 3714 if ((bo & 0x4) == 0) { 3715 /* Decrement and test CTR */ 3716 TCGv temp = tcg_temp_new(); 3717 3718 if (type == BCOND_CTR) { 3719 /* 3720 * All ISAs up to v3 describe this form of bcctr as invalid but 3721 * some processors, ie. 64-bit server processors compliant with 3722 * arch 2.x, do implement a "test and decrement" logic instead, 3723 * as described in their respective UMs. This logic involves CTR 3724 * to act as both the branch target and a counter, which makes 3725 * it basically useless and thus never used in real code. 3726 * 3727 * This form was hence chosen to trigger extra micro-architectural 3728 * side-effect on real HW needed for the Spectre v2 workaround. 3729 * It is up to guests that implement such workaround, ie. linux, to 3730 * use this form in a way it just triggers the side-effect without 3731 * doing anything else harmful. 3732 */ 3733 if (unlikely(!is_book3s_arch2x(ctx))) { 3734 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3735 return; 3736 } 3737 3738 if (NARROW_MODE(ctx)) { 3739 tcg_gen_ext32u_tl(temp, cpu_ctr); 3740 } else { 3741 tcg_gen_mov_tl(temp, cpu_ctr); 3742 } 3743 if (bo & 0x2) { 3744 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3745 } else { 3746 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3747 } 3748 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3749 } else { 3750 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3751 if (NARROW_MODE(ctx)) { 3752 tcg_gen_ext32u_tl(temp, cpu_ctr); 3753 } else { 3754 tcg_gen_mov_tl(temp, cpu_ctr); 3755 } 3756 if (bo & 0x2) { 3757 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3758 } else { 3759 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3760 } 3761 } 3762 bhrb_type |= BHRB_TYPE_COND; 3763 } 3764 if ((bo & 0x10) == 0) { 3765 /* Test CR */ 3766 uint32_t bi = BI(ctx->opcode); 3767 uint32_t mask = 0x08 >> (bi & 0x03); 3768 TCGv_i32 temp = tcg_temp_new_i32(); 3769 3770 if (bo & 0x8) { 3771 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3772 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3773 } else { 3774 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3775 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3776 } 3777 bhrb_type |= BHRB_TYPE_COND; 3778 } 3779 3780 gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); 3781 3782 if (type == BCOND_IM) { 3783 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3784 if (likely(AA(ctx->opcode) == 0)) { 3785 gen_goto_tb(ctx, 0, ctx->cia + li); 3786 } else { 3787 gen_goto_tb(ctx, 0, li); 3788 } 3789 } else { 3790 if (NARROW_MODE(ctx)) { 3791 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3792 } else { 3793 tcg_gen_andi_tl(cpu_nip, target, ~3); 3794 } 3795 gen_lookup_and_goto_ptr(ctx); 3796 } 3797 if ((bo & 0x14) != 0x14) { 3798 /* fallthrough case */ 3799 gen_set_label(l1); 3800 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3801 } 3802 ctx->base.is_jmp = DISAS_NORETURN; 3803 } 3804 3805 static void gen_bc(DisasContext *ctx) 3806 { 3807 gen_bcond(ctx, BCOND_IM); 3808 } 3809 3810 static void gen_bcctr(DisasContext *ctx) 3811 { 3812 gen_bcond(ctx, BCOND_CTR); 3813 } 3814 3815 static void gen_bclr(DisasContext *ctx) 3816 { 3817 gen_bcond(ctx, BCOND_LR); 3818 } 3819 3820 static void gen_bctar(DisasContext *ctx) 3821 { 3822 gen_bcond(ctx, BCOND_TAR); 3823 } 3824 3825 /*** Condition register logical ***/ 3826 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3827 static void glue(gen_, name)(DisasContext *ctx) \ 3828 { \ 3829 uint8_t bitmask; \ 3830 int sh; \ 3831 TCGv_i32 t0, t1; \ 3832 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3833 t0 = tcg_temp_new_i32(); \ 3834 if (sh > 0) \ 3835 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3836 else if (sh < 0) \ 3837 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3838 else \ 3839 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3840 t1 = tcg_temp_new_i32(); \ 3841 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3842 if (sh > 0) \ 3843 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3844 else if (sh < 0) \ 3845 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3846 else \ 3847 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3848 tcg_op(t0, t0, t1); \ 3849 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3850 tcg_gen_andi_i32(t0, t0, bitmask); \ 3851 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3852 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3853 } 3854 3855 /* crand */ 3856 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3857 /* crandc */ 3858 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3859 /* creqv */ 3860 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3861 /* crnand */ 3862 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3863 /* crnor */ 3864 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3865 /* cror */ 3866 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3867 /* crorc */ 3868 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3869 /* crxor */ 3870 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3871 3872 /* mcrf */ 3873 static void gen_mcrf(DisasContext *ctx) 3874 { 3875 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3876 } 3877 3878 /*** System linkage ***/ 3879 3880 /* rfi (supervisor only) */ 3881 static void gen_rfi(DisasContext *ctx) 3882 { 3883 #if defined(CONFIG_USER_ONLY) 3884 GEN_PRIV(ctx); 3885 #else 3886 /* 3887 * This instruction doesn't exist anymore on 64-bit server 3888 * processors compliant with arch 2.x 3889 */ 3890 if (is_book3s_arch2x(ctx)) { 3891 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3892 return; 3893 } 3894 /* Restore CPU state */ 3895 CHK_SV(ctx); 3896 translator_io_start(&ctx->base); 3897 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3898 gen_helper_rfi(tcg_env); 3899 ctx->base.is_jmp = DISAS_EXIT; 3900 #endif 3901 } 3902 3903 #if defined(TARGET_PPC64) 3904 static void gen_rfid(DisasContext *ctx) 3905 { 3906 #if defined(CONFIG_USER_ONLY) 3907 GEN_PRIV(ctx); 3908 #else 3909 /* Restore CPU state */ 3910 CHK_SV(ctx); 3911 translator_io_start(&ctx->base); 3912 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3913 gen_helper_rfid(tcg_env); 3914 ctx->base.is_jmp = DISAS_EXIT; 3915 #endif 3916 } 3917 3918 #if !defined(CONFIG_USER_ONLY) 3919 static void gen_rfscv(DisasContext *ctx) 3920 { 3921 #if defined(CONFIG_USER_ONLY) 3922 GEN_PRIV(ctx); 3923 #else 3924 /* Restore CPU state */ 3925 CHK_SV(ctx); 3926 translator_io_start(&ctx->base); 3927 gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); 3928 gen_helper_rfscv(tcg_env); 3929 ctx->base.is_jmp = DISAS_EXIT; 3930 #endif 3931 } 3932 #endif 3933 3934 static void gen_hrfid(DisasContext *ctx) 3935 { 3936 #if defined(CONFIG_USER_ONLY) 3937 GEN_PRIV(ctx); 3938 #else 3939 /* Restore CPU state */ 3940 CHK_HV(ctx); 3941 translator_io_start(&ctx->base); 3942 gen_helper_hrfid(tcg_env); 3943 ctx->base.is_jmp = DISAS_EXIT; 3944 #endif 3945 } 3946 #endif 3947 3948 /* sc */ 3949 #if defined(CONFIG_USER_ONLY) 3950 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3951 #else 3952 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3953 #endif 3954 static void gen_sc(DisasContext *ctx) 3955 { 3956 uint32_t lev; 3957 3958 /* 3959 * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 3960 * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 3961 * for Ultravisor which TCG does not support, so just ignore the top 6. 3962 */ 3963 lev = (ctx->opcode >> 5) & 0x1; 3964 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3965 } 3966 3967 #if defined(TARGET_PPC64) 3968 #if !defined(CONFIG_USER_ONLY) 3969 static void gen_scv(DisasContext *ctx) 3970 { 3971 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 3972 3973 /* Set the PC back to the faulting instruction. */ 3974 gen_update_nip(ctx, ctx->cia); 3975 gen_helper_scv(tcg_env, tcg_constant_i32(lev)); 3976 3977 ctx->base.is_jmp = DISAS_NORETURN; 3978 } 3979 #endif 3980 #endif 3981 3982 /*** Trap ***/ 3983 3984 /* Check for unconditional traps (always or never) */ 3985 static bool check_unconditional_trap(DisasContext *ctx, int to) 3986 { 3987 /* Trap never */ 3988 if (to == 0) { 3989 return true; 3990 } 3991 /* Trap always */ 3992 if (to == 31) { 3993 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3994 return true; 3995 } 3996 return false; 3997 } 3998 3999 /*** Processor control ***/ 4000 4001 /* mcrxr */ 4002 static void gen_mcrxr(DisasContext *ctx) 4003 { 4004 TCGv_i32 t0 = tcg_temp_new_i32(); 4005 TCGv_i32 t1 = tcg_temp_new_i32(); 4006 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4007 4008 tcg_gen_trunc_tl_i32(t0, cpu_so); 4009 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4010 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4011 tcg_gen_shli_i32(t0, t0, 3); 4012 tcg_gen_shli_i32(t1, t1, 2); 4013 tcg_gen_shli_i32(dst, dst, 1); 4014 tcg_gen_or_i32(dst, dst, t0); 4015 tcg_gen_or_i32(dst, dst, t1); 4016 4017 tcg_gen_movi_tl(cpu_so, 0); 4018 tcg_gen_movi_tl(cpu_ov, 0); 4019 tcg_gen_movi_tl(cpu_ca, 0); 4020 } 4021 4022 #ifdef TARGET_PPC64 4023 /* mcrxrx */ 4024 static void gen_mcrxrx(DisasContext *ctx) 4025 { 4026 TCGv t0 = tcg_temp_new(); 4027 TCGv t1 = tcg_temp_new(); 4028 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4029 4030 /* copy OV and OV32 */ 4031 tcg_gen_shli_tl(t0, cpu_ov, 1); 4032 tcg_gen_or_tl(t0, t0, cpu_ov32); 4033 tcg_gen_shli_tl(t0, t0, 2); 4034 /* copy CA and CA32 */ 4035 tcg_gen_shli_tl(t1, cpu_ca, 1); 4036 tcg_gen_or_tl(t1, t1, cpu_ca32); 4037 tcg_gen_or_tl(t0, t0, t1); 4038 tcg_gen_trunc_tl_i32(dst, t0); 4039 } 4040 #endif 4041 4042 /* mfcr mfocrf */ 4043 static void gen_mfcr(DisasContext *ctx) 4044 { 4045 uint32_t crm, crn; 4046 4047 if (likely(ctx->opcode & 0x00100000)) { 4048 crm = CRM(ctx->opcode); 4049 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4050 crn = ctz32(crm); 4051 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4052 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4053 cpu_gpr[rD(ctx->opcode)], crn * 4); 4054 } 4055 } else { 4056 TCGv_i32 t0 = tcg_temp_new_i32(); 4057 tcg_gen_mov_i32(t0, cpu_crf[0]); 4058 tcg_gen_shli_i32(t0, t0, 4); 4059 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4060 tcg_gen_shli_i32(t0, t0, 4); 4061 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4062 tcg_gen_shli_i32(t0, t0, 4); 4063 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4064 tcg_gen_shli_i32(t0, t0, 4); 4065 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4066 tcg_gen_shli_i32(t0, t0, 4); 4067 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4068 tcg_gen_shli_i32(t0, t0, 4); 4069 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4070 tcg_gen_shli_i32(t0, t0, 4); 4071 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4072 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4073 } 4074 } 4075 4076 /* mfmsr */ 4077 static void gen_mfmsr(DisasContext *ctx) 4078 { 4079 CHK_SV(ctx); 4080 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4081 } 4082 4083 /* mfspr */ 4084 static inline void gen_op_mfspr(DisasContext *ctx) 4085 { 4086 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4087 uint32_t sprn = SPR(ctx->opcode); 4088 4089 #if defined(CONFIG_USER_ONLY) 4090 read_cb = ctx->spr_cb[sprn].uea_read; 4091 #else 4092 if (ctx->pr) { 4093 read_cb = ctx->spr_cb[sprn].uea_read; 4094 } else if (ctx->hv) { 4095 read_cb = ctx->spr_cb[sprn].hea_read; 4096 } else { 4097 read_cb = ctx->spr_cb[sprn].oea_read; 4098 } 4099 #endif 4100 if (likely(read_cb != NULL)) { 4101 if (likely(read_cb != SPR_NOACCESS)) { 4102 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4103 } else { 4104 /* Privilege exception */ 4105 /* 4106 * This is a hack to avoid warnings when running Linux: 4107 * this OS breaks the PowerPC virtualisation model, 4108 * allowing userland application to read the PVR 4109 */ 4110 if (sprn != SPR_PVR) { 4111 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4112 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4113 ctx->cia); 4114 } 4115 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4116 } 4117 } else { 4118 /* ISA 2.07 defines these as no-ops */ 4119 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4120 (sprn >= 808 && sprn <= 811)) { 4121 /* This is a nop */ 4122 return; 4123 } 4124 /* Not defined */ 4125 qemu_log_mask(LOG_GUEST_ERROR, 4126 "Trying to read invalid spr %d (0x%03x) at " 4127 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4128 4129 /* 4130 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4131 * generate a priv, a hv emu or a no-op 4132 */ 4133 if (sprn & 0x10) { 4134 if (ctx->pr) { 4135 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4136 } 4137 } else { 4138 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4139 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4140 } 4141 } 4142 } 4143 } 4144 4145 static void gen_mfspr(DisasContext *ctx) 4146 { 4147 gen_op_mfspr(ctx); 4148 } 4149 4150 /* mftb */ 4151 static void gen_mftb(DisasContext *ctx) 4152 { 4153 gen_op_mfspr(ctx); 4154 } 4155 4156 /* mtcrf mtocrf*/ 4157 static void gen_mtcrf(DisasContext *ctx) 4158 { 4159 uint32_t crm, crn; 4160 4161 crm = CRM(ctx->opcode); 4162 if (likely((ctx->opcode & 0x00100000))) { 4163 if (crm && ((crm & (crm - 1)) == 0)) { 4164 TCGv_i32 temp = tcg_temp_new_i32(); 4165 crn = ctz32(crm); 4166 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4167 tcg_gen_shri_i32(temp, temp, crn * 4); 4168 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4169 } 4170 } else { 4171 TCGv_i32 temp = tcg_temp_new_i32(); 4172 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4173 for (crn = 0 ; crn < 8 ; crn++) { 4174 if (crm & (1 << crn)) { 4175 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4176 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4177 } 4178 } 4179 } 4180 } 4181 4182 /* mtmsr */ 4183 #if defined(TARGET_PPC64) 4184 static void gen_mtmsrd(DisasContext *ctx) 4185 { 4186 if (unlikely(!is_book3s_arch2x(ctx))) { 4187 gen_invalid(ctx); 4188 return; 4189 } 4190 4191 CHK_SV(ctx); 4192 4193 #if !defined(CONFIG_USER_ONLY) 4194 TCGv t0, t1; 4195 target_ulong mask; 4196 4197 t0 = tcg_temp_new(); 4198 t1 = tcg_temp_new(); 4199 4200 translator_io_start(&ctx->base); 4201 4202 if (ctx->opcode & 0x00010000) { 4203 /* L=1 form only updates EE and RI */ 4204 mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4205 } else { 4206 /* mtmsrd does not alter HV, S, ME, or LE */ 4207 mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 4208 (1ULL << MSR_HV)); 4209 /* 4210 * XXX: we need to update nip before the store if we enter 4211 * power saving mode, we will exit the loop directly from 4212 * ppc_store_msr 4213 */ 4214 gen_update_nip(ctx, ctx->base.pc_next); 4215 } 4216 4217 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4218 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4219 tcg_gen_or_tl(t0, t0, t1); 4220 4221 gen_helper_store_msr(tcg_env, t0); 4222 4223 /* Must stop the translation as machine state (may have) changed */ 4224 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4225 #endif /* !defined(CONFIG_USER_ONLY) */ 4226 } 4227 #endif /* defined(TARGET_PPC64) */ 4228 4229 static void gen_mtmsr(DisasContext *ctx) 4230 { 4231 CHK_SV(ctx); 4232 4233 #if !defined(CONFIG_USER_ONLY) 4234 TCGv t0, t1; 4235 target_ulong mask = 0xFFFFFFFF; 4236 4237 t0 = tcg_temp_new(); 4238 t1 = tcg_temp_new(); 4239 4240 translator_io_start(&ctx->base); 4241 if (ctx->opcode & 0x00010000) { 4242 /* L=1 form only updates EE and RI */ 4243 mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4244 } else { 4245 /* mtmsr does not alter S, ME, or LE */ 4246 mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4247 4248 /* 4249 * XXX: we need to update nip before the store if we enter 4250 * power saving mode, we will exit the loop directly from 4251 * ppc_store_msr 4252 */ 4253 gen_update_nip(ctx, ctx->base.pc_next); 4254 } 4255 4256 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 4257 tcg_gen_andi_tl(t1, cpu_msr, ~mask); 4258 tcg_gen_or_tl(t0, t0, t1); 4259 4260 gen_helper_store_msr(tcg_env, t0); 4261 4262 /* Must stop the translation as machine state (may have) changed */ 4263 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4264 #endif 4265 } 4266 4267 /* mtspr */ 4268 static void gen_mtspr(DisasContext *ctx) 4269 { 4270 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4271 uint32_t sprn = SPR(ctx->opcode); 4272 4273 #if defined(CONFIG_USER_ONLY) 4274 write_cb = ctx->spr_cb[sprn].uea_write; 4275 #else 4276 if (ctx->pr) { 4277 write_cb = ctx->spr_cb[sprn].uea_write; 4278 } else if (ctx->hv) { 4279 write_cb = ctx->spr_cb[sprn].hea_write; 4280 } else { 4281 write_cb = ctx->spr_cb[sprn].oea_write; 4282 } 4283 #endif 4284 if (likely(write_cb != NULL)) { 4285 if (likely(write_cb != SPR_NOACCESS)) { 4286 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4287 } else { 4288 /* Privilege exception */ 4289 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4290 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4291 ctx->cia); 4292 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4293 } 4294 } else { 4295 /* ISA 2.07 defines these as no-ops */ 4296 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4297 (sprn >= 808 && sprn <= 811)) { 4298 /* This is a nop */ 4299 return; 4300 } 4301 4302 /* Not defined */ 4303 qemu_log_mask(LOG_GUEST_ERROR, 4304 "Trying to write invalid spr %d (0x%03x) at " 4305 TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4306 4307 4308 /* 4309 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4310 * generate a priv, a hv emu or a no-op 4311 */ 4312 if (sprn & 0x10) { 4313 if (ctx->pr) { 4314 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4315 } 4316 } else { 4317 if (ctx->pr || sprn == 0) { 4318 gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4319 } 4320 } 4321 } 4322 } 4323 4324 #if defined(TARGET_PPC64) 4325 /* setb */ 4326 static void gen_setb(DisasContext *ctx) 4327 { 4328 TCGv_i32 t0 = tcg_temp_new_i32(); 4329 TCGv_i32 t8 = tcg_constant_i32(8); 4330 TCGv_i32 tm1 = tcg_constant_i32(-1); 4331 int crf = crfS(ctx->opcode); 4332 4333 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4334 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4335 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4336 } 4337 #endif 4338 4339 /*** Cache management ***/ 4340 4341 /* dcbf */ 4342 static void gen_dcbf(DisasContext *ctx) 4343 { 4344 /* XXX: specification says this is treated as a load by the MMU */ 4345 TCGv t0; 4346 gen_set_access_type(ctx, ACCESS_CACHE); 4347 t0 = tcg_temp_new(); 4348 gen_addr_reg_index(ctx, t0); 4349 gen_qemu_ld8u(ctx, t0, t0); 4350 } 4351 4352 /* dcbfep (external PID dcbf) */ 4353 static void gen_dcbfep(DisasContext *ctx) 4354 { 4355 /* XXX: specification says this is treated as a load by the MMU */ 4356 TCGv t0; 4357 CHK_SV(ctx); 4358 gen_set_access_type(ctx, ACCESS_CACHE); 4359 t0 = tcg_temp_new(); 4360 gen_addr_reg_index(ctx, t0); 4361 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4362 } 4363 4364 /* dcbi (Supervisor only) */ 4365 static void gen_dcbi(DisasContext *ctx) 4366 { 4367 #if defined(CONFIG_USER_ONLY) 4368 GEN_PRIV(ctx); 4369 #else 4370 TCGv EA, val; 4371 4372 CHK_SV(ctx); 4373 EA = tcg_temp_new(); 4374 gen_set_access_type(ctx, ACCESS_CACHE); 4375 gen_addr_reg_index(ctx, EA); 4376 val = tcg_temp_new(); 4377 /* XXX: specification says this should be treated as a store by the MMU */ 4378 gen_qemu_ld8u(ctx, val, EA); 4379 gen_qemu_st8(ctx, val, EA); 4380 #endif /* defined(CONFIG_USER_ONLY) */ 4381 } 4382 4383 /* dcdst */ 4384 static void gen_dcbst(DisasContext *ctx) 4385 { 4386 /* XXX: specification say this is treated as a load by the MMU */ 4387 TCGv t0; 4388 gen_set_access_type(ctx, ACCESS_CACHE); 4389 t0 = tcg_temp_new(); 4390 gen_addr_reg_index(ctx, t0); 4391 gen_qemu_ld8u(ctx, t0, t0); 4392 } 4393 4394 /* dcbstep (dcbstep External PID version) */ 4395 static void gen_dcbstep(DisasContext *ctx) 4396 { 4397 /* XXX: specification say this is treated as a load by the MMU */ 4398 TCGv t0; 4399 gen_set_access_type(ctx, ACCESS_CACHE); 4400 t0 = tcg_temp_new(); 4401 gen_addr_reg_index(ctx, t0); 4402 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4403 } 4404 4405 /* dcbt */ 4406 static void gen_dcbt(DisasContext *ctx) 4407 { 4408 /* 4409 * interpreted as no-op 4410 * XXX: specification say this is treated as a load by the MMU but 4411 * does not generate any exception 4412 */ 4413 } 4414 4415 /* dcbtep */ 4416 static void gen_dcbtep(DisasContext *ctx) 4417 { 4418 /* 4419 * interpreted as no-op 4420 * XXX: specification say this is treated as a load by the MMU but 4421 * does not generate any exception 4422 */ 4423 } 4424 4425 /* dcbtst */ 4426 static void gen_dcbtst(DisasContext *ctx) 4427 { 4428 /* 4429 * interpreted as no-op 4430 * XXX: specification say this is treated as a load by the MMU but 4431 * does not generate any exception 4432 */ 4433 } 4434 4435 /* dcbtstep */ 4436 static void gen_dcbtstep(DisasContext *ctx) 4437 { 4438 /* 4439 * interpreted as no-op 4440 * XXX: specification say this is treated as a load by the MMU but 4441 * does not generate any exception 4442 */ 4443 } 4444 4445 /* dcbtls */ 4446 static void gen_dcbtls(DisasContext *ctx) 4447 { 4448 /* Always fails locking the cache */ 4449 TCGv t0 = tcg_temp_new(); 4450 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4451 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4452 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4453 } 4454 4455 /* dcblc */ 4456 static void gen_dcblc(DisasContext *ctx) 4457 { 4458 /* 4459 * interpreted as no-op 4460 */ 4461 } 4462 4463 /* dcbz */ 4464 static void gen_dcbz(DisasContext *ctx) 4465 { 4466 TCGv tcgv_addr = tcg_temp_new(); 4467 4468 gen_set_access_type(ctx, ACCESS_CACHE); 4469 gen_addr_reg_index(ctx, tcgv_addr); 4470 4471 #ifdef TARGET_PPC64 4472 if (ctx->excp_model == POWERPC_EXCP_970 && !(ctx->opcode & 0x00200000)) { 4473 gen_helper_dcbzl(tcg_env, tcgv_addr); 4474 return; 4475 } 4476 #endif 4477 4478 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx)); 4479 } 4480 4481 /* dcbzep */ 4482 static void gen_dcbzep(DisasContext *ctx) 4483 { 4484 TCGv tcgv_addr = tcg_temp_new(); 4485 4486 gen_set_access_type(ctx, ACCESS_CACHE); 4487 gen_addr_reg_index(ctx, tcgv_addr); 4488 gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STORE)); 4489 } 4490 4491 /* dst / dstt */ 4492 static void gen_dst(DisasContext *ctx) 4493 { 4494 if (rA(ctx->opcode) == 0) { 4495 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4496 } else { 4497 /* interpreted as no-op */ 4498 } 4499 } 4500 4501 /* dstst /dststt */ 4502 static void gen_dstst(DisasContext *ctx) 4503 { 4504 if (rA(ctx->opcode) == 0) { 4505 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4506 } else { 4507 /* interpreted as no-op */ 4508 } 4509 4510 } 4511 4512 /* dss / dssall */ 4513 static void gen_dss(DisasContext *ctx) 4514 { 4515 /* interpreted as no-op */ 4516 } 4517 4518 /* icbi */ 4519 static void gen_icbi(DisasContext *ctx) 4520 { 4521 TCGv t0; 4522 gen_set_access_type(ctx, ACCESS_CACHE); 4523 t0 = tcg_temp_new(); 4524 gen_addr_reg_index(ctx, t0); 4525 gen_helper_icbi(tcg_env, t0); 4526 } 4527 4528 /* icbiep */ 4529 static void gen_icbiep(DisasContext *ctx) 4530 { 4531 TCGv t0; 4532 gen_set_access_type(ctx, ACCESS_CACHE); 4533 t0 = tcg_temp_new(); 4534 gen_addr_reg_index(ctx, t0); 4535 gen_helper_icbiep(tcg_env, t0); 4536 } 4537 4538 /* Optional: */ 4539 /* dcba */ 4540 static void gen_dcba(DisasContext *ctx) 4541 { 4542 /* 4543 * interpreted as no-op 4544 * XXX: specification say this is treated as a store by the MMU 4545 * but does not generate any exception 4546 */ 4547 } 4548 4549 /*** Segment register manipulation ***/ 4550 /* Supervisor only: */ 4551 4552 /* mfsr */ 4553 static void gen_mfsr(DisasContext *ctx) 4554 { 4555 #if defined(CONFIG_USER_ONLY) 4556 GEN_PRIV(ctx); 4557 #else 4558 TCGv t0; 4559 4560 CHK_SV(ctx); 4561 t0 = tcg_constant_tl(SR(ctx->opcode)); 4562 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4563 #endif /* defined(CONFIG_USER_ONLY) */ 4564 } 4565 4566 /* mfsrin */ 4567 static void gen_mfsrin(DisasContext *ctx) 4568 { 4569 #if defined(CONFIG_USER_ONLY) 4570 GEN_PRIV(ctx); 4571 #else 4572 TCGv t0; 4573 4574 CHK_SV(ctx); 4575 t0 = tcg_temp_new(); 4576 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4577 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4578 #endif /* defined(CONFIG_USER_ONLY) */ 4579 } 4580 4581 /* mtsr */ 4582 static void gen_mtsr(DisasContext *ctx) 4583 { 4584 #if defined(CONFIG_USER_ONLY) 4585 GEN_PRIV(ctx); 4586 #else 4587 TCGv t0; 4588 4589 CHK_SV(ctx); 4590 t0 = tcg_constant_tl(SR(ctx->opcode)); 4591 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4592 #endif /* defined(CONFIG_USER_ONLY) */ 4593 } 4594 4595 /* mtsrin */ 4596 static void gen_mtsrin(DisasContext *ctx) 4597 { 4598 #if defined(CONFIG_USER_ONLY) 4599 GEN_PRIV(ctx); 4600 #else 4601 TCGv t0; 4602 CHK_SV(ctx); 4603 4604 t0 = tcg_temp_new(); 4605 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4606 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); 4607 #endif /* defined(CONFIG_USER_ONLY) */ 4608 } 4609 4610 #if defined(TARGET_PPC64) 4611 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4612 4613 /* mfsr */ 4614 static void gen_mfsr_64b(DisasContext *ctx) 4615 { 4616 #if defined(CONFIG_USER_ONLY) 4617 GEN_PRIV(ctx); 4618 #else 4619 TCGv t0; 4620 4621 CHK_SV(ctx); 4622 t0 = tcg_constant_tl(SR(ctx->opcode)); 4623 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4624 #endif /* defined(CONFIG_USER_ONLY) */ 4625 } 4626 4627 /* mfsrin */ 4628 static void gen_mfsrin_64b(DisasContext *ctx) 4629 { 4630 #if defined(CONFIG_USER_ONLY) 4631 GEN_PRIV(ctx); 4632 #else 4633 TCGv t0; 4634 4635 CHK_SV(ctx); 4636 t0 = tcg_temp_new(); 4637 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4638 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 4639 #endif /* defined(CONFIG_USER_ONLY) */ 4640 } 4641 4642 /* mtsr */ 4643 static void gen_mtsr_64b(DisasContext *ctx) 4644 { 4645 #if defined(CONFIG_USER_ONLY) 4646 GEN_PRIV(ctx); 4647 #else 4648 TCGv t0; 4649 4650 CHK_SV(ctx); 4651 t0 = tcg_constant_tl(SR(ctx->opcode)); 4652 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4653 #endif /* defined(CONFIG_USER_ONLY) */ 4654 } 4655 4656 /* mtsrin */ 4657 static void gen_mtsrin_64b(DisasContext *ctx) 4658 { 4659 #if defined(CONFIG_USER_ONLY) 4660 GEN_PRIV(ctx); 4661 #else 4662 TCGv t0; 4663 4664 CHK_SV(ctx); 4665 t0 = tcg_temp_new(); 4666 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4667 gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); 4668 #endif /* defined(CONFIG_USER_ONLY) */ 4669 } 4670 4671 #endif /* defined(TARGET_PPC64) */ 4672 4673 /*** Lookaside buffer management ***/ 4674 /* Optional & supervisor only: */ 4675 4676 /* tlbia */ 4677 static void gen_tlbia(DisasContext *ctx) 4678 { 4679 #if defined(CONFIG_USER_ONLY) 4680 GEN_PRIV(ctx); 4681 #else 4682 CHK_HV(ctx); 4683 4684 gen_helper_tlbia(tcg_env); 4685 #endif /* defined(CONFIG_USER_ONLY) */ 4686 } 4687 4688 /* tlbsync */ 4689 static void gen_tlbsync(DisasContext *ctx) 4690 { 4691 #if defined(CONFIG_USER_ONLY) 4692 GEN_PRIV(ctx); 4693 #else 4694 4695 if (ctx->gtse) { 4696 CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 4697 } else { 4698 CHK_HV(ctx); /* Else hypervisor privileged */ 4699 } 4700 4701 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4702 if (ctx->insns_flags & PPC_BOOKE) { 4703 gen_check_tlb_flush(ctx, true); 4704 } 4705 #endif /* defined(CONFIG_USER_ONLY) */ 4706 } 4707 4708 /*** External control ***/ 4709 /* Optional: */ 4710 4711 /* eciwx */ 4712 static void gen_eciwx(DisasContext *ctx) 4713 { 4714 TCGv t0; 4715 /* Should check EAR[E] ! */ 4716 gen_set_access_type(ctx, ACCESS_EXT); 4717 t0 = tcg_temp_new(); 4718 gen_addr_reg_index(ctx, t0); 4719 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4720 DEF_MEMOP(MO_UL | MO_ALIGN)); 4721 } 4722 4723 /* ecowx */ 4724 static void gen_ecowx(DisasContext *ctx) 4725 { 4726 TCGv t0; 4727 /* Should check EAR[E] ! */ 4728 gen_set_access_type(ctx, ACCESS_EXT); 4729 t0 = tcg_temp_new(); 4730 gen_addr_reg_index(ctx, t0); 4731 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4732 DEF_MEMOP(MO_UL | MO_ALIGN)); 4733 } 4734 4735 /* 602 - 603 - G2 TLB management */ 4736 4737 /* tlbld */ 4738 static void gen_tlbld_6xx(DisasContext *ctx) 4739 { 4740 #if defined(CONFIG_USER_ONLY) 4741 GEN_PRIV(ctx); 4742 #else 4743 CHK_SV(ctx); 4744 gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4745 #endif /* defined(CONFIG_USER_ONLY) */ 4746 } 4747 4748 /* tlbli */ 4749 static void gen_tlbli_6xx(DisasContext *ctx) 4750 { 4751 #if defined(CONFIG_USER_ONLY) 4752 GEN_PRIV(ctx); 4753 #else 4754 CHK_SV(ctx); 4755 gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4756 #endif /* defined(CONFIG_USER_ONLY) */ 4757 } 4758 4759 /* BookE specific instructions */ 4760 4761 /* XXX: not implemented on 440 ? */ 4762 static void gen_mfapidi(DisasContext *ctx) 4763 { 4764 /* XXX: TODO */ 4765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4766 } 4767 4768 /* XXX: not implemented on 440 ? */ 4769 static void gen_tlbiva(DisasContext *ctx) 4770 { 4771 #if defined(CONFIG_USER_ONLY) 4772 GEN_PRIV(ctx); 4773 #else 4774 TCGv t0; 4775 4776 CHK_SV(ctx); 4777 t0 = tcg_temp_new(); 4778 gen_addr_reg_index(ctx, t0); 4779 gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); 4780 #endif /* defined(CONFIG_USER_ONLY) */ 4781 } 4782 4783 /* All 405 MAC instructions are translated here */ 4784 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 4785 int ra, int rb, int rt, int Rc) 4786 { 4787 TCGv t0, t1; 4788 4789 t0 = tcg_temp_new(); 4790 t1 = tcg_temp_new(); 4791 4792 switch (opc3 & 0x0D) { 4793 case 0x05: 4794 /* macchw - macchw. - macchwo - macchwo. */ 4795 /* macchws - macchws. - macchwso - macchwso. */ 4796 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 4797 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 4798 /* mulchw - mulchw. */ 4799 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4800 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4801 tcg_gen_ext16s_tl(t1, t1); 4802 break; 4803 case 0x04: 4804 /* macchwu - macchwu. - macchwuo - macchwuo. */ 4805 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 4806 /* mulchwu - mulchwu. */ 4807 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4808 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4809 tcg_gen_ext16u_tl(t1, t1); 4810 break; 4811 case 0x01: 4812 /* machhw - machhw. - machhwo - machhwo. */ 4813 /* machhws - machhws. - machhwso - machhwso. */ 4814 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 4815 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 4816 /* mulhhw - mulhhw. */ 4817 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 4818 tcg_gen_ext16s_tl(t0, t0); 4819 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 4820 tcg_gen_ext16s_tl(t1, t1); 4821 break; 4822 case 0x00: 4823 /* machhwu - machhwu. - machhwuo - machhwuo. */ 4824 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 4825 /* mulhhwu - mulhhwu. */ 4826 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 4827 tcg_gen_ext16u_tl(t0, t0); 4828 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 4829 tcg_gen_ext16u_tl(t1, t1); 4830 break; 4831 case 0x0D: 4832 /* maclhw - maclhw. - maclhwo - maclhwo. */ 4833 /* maclhws - maclhws. - maclhwso - maclhwso. */ 4834 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 4835 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 4836 /* mullhw - mullhw. */ 4837 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 4838 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 4839 break; 4840 case 0x0C: 4841 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 4842 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 4843 /* mullhwu - mullhwu. */ 4844 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 4845 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 4846 break; 4847 } 4848 if (opc2 & 0x04) { 4849 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 4850 tcg_gen_mul_tl(t1, t0, t1); 4851 if (opc2 & 0x02) { 4852 /* nmultiply-and-accumulate (0x0E) */ 4853 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 4854 } else { 4855 /* multiply-and-accumulate (0x0C) */ 4856 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 4857 } 4858 4859 if (opc3 & 0x12) { 4860 /* Check overflow and/or saturate */ 4861 TCGLabel *l1 = gen_new_label(); 4862 4863 if (opc3 & 0x10) { 4864 /* Start with XER OV disabled, the most likely case */ 4865 tcg_gen_movi_tl(cpu_ov, 0); 4866 } 4867 if (opc3 & 0x01) { 4868 /* Signed */ 4869 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 4870 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 4871 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 4872 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 4873 if (opc3 & 0x02) { 4874 /* Saturate */ 4875 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 4876 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 4877 } 4878 } else { 4879 /* Unsigned */ 4880 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4881 if (opc3 & 0x02) { 4882 /* Saturate */ 4883 tcg_gen_movi_tl(t0, UINT32_MAX); 4884 } 4885 } 4886 if (opc3 & 0x10) { 4887 /* Check overflow */ 4888 tcg_gen_movi_tl(cpu_ov, 1); 4889 tcg_gen_movi_tl(cpu_so, 1); 4890 } 4891 gen_set_label(l1); 4892 tcg_gen_mov_tl(cpu_gpr[rt], t0); 4893 } 4894 } else { 4895 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 4896 } 4897 if (unlikely(Rc) != 0) { 4898 /* Update Rc0 */ 4899 gen_set_Rc0(ctx, cpu_gpr[rt]); 4900 } 4901 } 4902 4903 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 4904 static void glue(gen_, name)(DisasContext *ctx) \ 4905 { \ 4906 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 4907 rD(ctx->opcode), Rc(ctx->opcode)); \ 4908 } 4909 4910 /* macchw - macchw. */ 4911 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 4912 /* macchwo - macchwo. */ 4913 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 4914 /* macchws - macchws. */ 4915 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 4916 /* macchwso - macchwso. */ 4917 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 4918 /* macchwsu - macchwsu. */ 4919 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 4920 /* macchwsuo - macchwsuo. */ 4921 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 4922 /* macchwu - macchwu. */ 4923 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 4924 /* macchwuo - macchwuo. */ 4925 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 4926 /* machhw - machhw. */ 4927 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 4928 /* machhwo - machhwo. */ 4929 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 4930 /* machhws - machhws. */ 4931 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 4932 /* machhwso - machhwso. */ 4933 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 4934 /* machhwsu - machhwsu. */ 4935 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 4936 /* machhwsuo - machhwsuo. */ 4937 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 4938 /* machhwu - machhwu. */ 4939 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 4940 /* machhwuo - machhwuo. */ 4941 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 4942 /* maclhw - maclhw. */ 4943 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 4944 /* maclhwo - maclhwo. */ 4945 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 4946 /* maclhws - maclhws. */ 4947 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 4948 /* maclhwso - maclhwso. */ 4949 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 4950 /* maclhwu - maclhwu. */ 4951 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 4952 /* maclhwuo - maclhwuo. */ 4953 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 4954 /* maclhwsu - maclhwsu. */ 4955 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 4956 /* maclhwsuo - maclhwsuo. */ 4957 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 4958 /* nmacchw - nmacchw. */ 4959 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 4960 /* nmacchwo - nmacchwo. */ 4961 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 4962 /* nmacchws - nmacchws. */ 4963 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 4964 /* nmacchwso - nmacchwso. */ 4965 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 4966 /* nmachhw - nmachhw. */ 4967 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 4968 /* nmachhwo - nmachhwo. */ 4969 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 4970 /* nmachhws - nmachhws. */ 4971 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 4972 /* nmachhwso - nmachhwso. */ 4973 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 4974 /* nmaclhw - nmaclhw. */ 4975 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 4976 /* nmaclhwo - nmaclhwo. */ 4977 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 4978 /* nmaclhws - nmaclhws. */ 4979 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 4980 /* nmaclhwso - nmaclhwso. */ 4981 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 4982 4983 /* mulchw - mulchw. */ 4984 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 4985 /* mulchwu - mulchwu. */ 4986 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 4987 /* mulhhw - mulhhw. */ 4988 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 4989 /* mulhhwu - mulhhwu. */ 4990 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 4991 /* mullhw - mullhw. */ 4992 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 4993 /* mullhwu - mullhwu. */ 4994 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 4995 4996 /* mfdcr */ 4997 static void gen_mfdcr(DisasContext *ctx) 4998 { 4999 #if defined(CONFIG_USER_ONLY) 5000 GEN_PRIV(ctx); 5001 #else 5002 TCGv dcrn; 5003 5004 CHK_SV(ctx); 5005 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5006 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); 5007 #endif /* defined(CONFIG_USER_ONLY) */ 5008 } 5009 5010 /* mtdcr */ 5011 static void gen_mtdcr(DisasContext *ctx) 5012 { 5013 #if defined(CONFIG_USER_ONLY) 5014 GEN_PRIV(ctx); 5015 #else 5016 TCGv dcrn; 5017 5018 CHK_SV(ctx); 5019 dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5020 gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5021 #endif /* defined(CONFIG_USER_ONLY) */ 5022 } 5023 5024 /* mfdcrx */ 5025 /* XXX: not implemented on 440 ? */ 5026 static void gen_mfdcrx(DisasContext *ctx) 5027 { 5028 #if defined(CONFIG_USER_ONLY) 5029 GEN_PRIV(ctx); 5030 #else 5031 CHK_SV(ctx); 5032 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, 5033 cpu_gpr[rA(ctx->opcode)]); 5034 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5035 #endif /* defined(CONFIG_USER_ONLY) */ 5036 } 5037 5038 /* mtdcrx */ 5039 /* XXX: not implemented on 440 ? */ 5040 static void gen_mtdcrx(DisasContext *ctx) 5041 { 5042 #if defined(CONFIG_USER_ONLY) 5043 GEN_PRIV(ctx); 5044 #else 5045 CHK_SV(ctx); 5046 gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], 5047 cpu_gpr[rS(ctx->opcode)]); 5048 /* Note: Rc update flag set leads to undefined state of Rc0 */ 5049 #endif /* defined(CONFIG_USER_ONLY) */ 5050 } 5051 5052 /* dccci */ 5053 static void gen_dccci(DisasContext *ctx) 5054 { 5055 CHK_SV(ctx); 5056 /* interpreted as no-op */ 5057 } 5058 5059 /* dcread */ 5060 static void gen_dcread(DisasContext *ctx) 5061 { 5062 #if defined(CONFIG_USER_ONLY) 5063 GEN_PRIV(ctx); 5064 #else 5065 TCGv EA, val; 5066 5067 CHK_SV(ctx); 5068 gen_set_access_type(ctx, ACCESS_CACHE); 5069 EA = tcg_temp_new(); 5070 gen_addr_reg_index(ctx, EA); 5071 val = tcg_temp_new(); 5072 gen_qemu_ld32u(ctx, val, EA); 5073 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5074 #endif /* defined(CONFIG_USER_ONLY) */ 5075 } 5076 5077 /* icbt */ 5078 static void gen_icbt_40x(DisasContext *ctx) 5079 { 5080 /* 5081 * interpreted as no-op 5082 * XXX: specification say this is treated as a load by the MMU but 5083 * does not generate any exception 5084 */ 5085 } 5086 5087 /* iccci */ 5088 static void gen_iccci(DisasContext *ctx) 5089 { 5090 CHK_SV(ctx); 5091 /* interpreted as no-op */ 5092 } 5093 5094 /* icread */ 5095 static void gen_icread(DisasContext *ctx) 5096 { 5097 CHK_SV(ctx); 5098 /* interpreted as no-op */ 5099 } 5100 5101 /* rfci (supervisor only) */ 5102 static void gen_rfci_40x(DisasContext *ctx) 5103 { 5104 #if defined(CONFIG_USER_ONLY) 5105 GEN_PRIV(ctx); 5106 #else 5107 CHK_SV(ctx); 5108 /* Restore CPU state */ 5109 gen_helper_40x_rfci(tcg_env); 5110 ctx->base.is_jmp = DISAS_EXIT; 5111 #endif /* defined(CONFIG_USER_ONLY) */ 5112 } 5113 5114 static void gen_rfci(DisasContext *ctx) 5115 { 5116 #if defined(CONFIG_USER_ONLY) 5117 GEN_PRIV(ctx); 5118 #else 5119 CHK_SV(ctx); 5120 /* Restore CPU state */ 5121 gen_helper_rfci(tcg_env); 5122 ctx->base.is_jmp = DISAS_EXIT; 5123 #endif /* defined(CONFIG_USER_ONLY) */ 5124 } 5125 5126 /* BookE specific */ 5127 5128 /* XXX: not implemented on 440 ? */ 5129 static void gen_rfdi(DisasContext *ctx) 5130 { 5131 #if defined(CONFIG_USER_ONLY) 5132 GEN_PRIV(ctx); 5133 #else 5134 CHK_SV(ctx); 5135 /* Restore CPU state */ 5136 gen_helper_rfdi(tcg_env); 5137 ctx->base.is_jmp = DISAS_EXIT; 5138 #endif /* defined(CONFIG_USER_ONLY) */ 5139 } 5140 5141 /* XXX: not implemented on 440 ? */ 5142 static void gen_rfmci(DisasContext *ctx) 5143 { 5144 #if defined(CONFIG_USER_ONLY) 5145 GEN_PRIV(ctx); 5146 #else 5147 CHK_SV(ctx); 5148 /* Restore CPU state */ 5149 gen_helper_rfmci(tcg_env); 5150 ctx->base.is_jmp = DISAS_EXIT; 5151 #endif /* defined(CONFIG_USER_ONLY) */ 5152 } 5153 5154 /* TLB management - PowerPC 405 implementation */ 5155 5156 /* tlbre */ 5157 static void gen_tlbre_40x(DisasContext *ctx) 5158 { 5159 #if defined(CONFIG_USER_ONLY) 5160 GEN_PRIV(ctx); 5161 #else 5162 CHK_SV(ctx); 5163 switch (rB(ctx->opcode)) { 5164 case 0: 5165 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, 5166 cpu_gpr[rA(ctx->opcode)]); 5167 break; 5168 case 1: 5169 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, 5170 cpu_gpr[rA(ctx->opcode)]); 5171 break; 5172 default: 5173 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5174 break; 5175 } 5176 #endif /* defined(CONFIG_USER_ONLY) */ 5177 } 5178 5179 /* tlbsx - tlbsx. */ 5180 static void gen_tlbsx_40x(DisasContext *ctx) 5181 { 5182 #if defined(CONFIG_USER_ONLY) 5183 GEN_PRIV(ctx); 5184 #else 5185 TCGv t0; 5186 5187 CHK_SV(ctx); 5188 t0 = tcg_temp_new(); 5189 gen_addr_reg_index(ctx, t0); 5190 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5191 if (Rc(ctx->opcode)) { 5192 TCGLabel *l1 = gen_new_label(); 5193 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5194 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5195 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5196 gen_set_label(l1); 5197 } 5198 #endif /* defined(CONFIG_USER_ONLY) */ 5199 } 5200 5201 /* tlbwe */ 5202 static void gen_tlbwe_40x(DisasContext *ctx) 5203 { 5204 #if defined(CONFIG_USER_ONLY) 5205 GEN_PRIV(ctx); 5206 #else 5207 CHK_SV(ctx); 5208 5209 switch (rB(ctx->opcode)) { 5210 case 0: 5211 gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], 5212 cpu_gpr[rS(ctx->opcode)]); 5213 break; 5214 case 1: 5215 gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], 5216 cpu_gpr[rS(ctx->opcode)]); 5217 break; 5218 default: 5219 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5220 break; 5221 } 5222 #endif /* defined(CONFIG_USER_ONLY) */ 5223 } 5224 5225 /* TLB management - PowerPC 440 implementation */ 5226 5227 /* tlbre */ 5228 static void gen_tlbre_440(DisasContext *ctx) 5229 { 5230 #if defined(CONFIG_USER_ONLY) 5231 GEN_PRIV(ctx); 5232 #else 5233 CHK_SV(ctx); 5234 5235 switch (rB(ctx->opcode)) { 5236 case 0: 5237 case 1: 5238 case 2: 5239 { 5240 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5241 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, 5242 t0, cpu_gpr[rA(ctx->opcode)]); 5243 } 5244 break; 5245 default: 5246 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5247 break; 5248 } 5249 #endif /* defined(CONFIG_USER_ONLY) */ 5250 } 5251 5252 /* tlbsx - tlbsx. */ 5253 static void gen_tlbsx_440(DisasContext *ctx) 5254 { 5255 #if defined(CONFIG_USER_ONLY) 5256 GEN_PRIV(ctx); 5257 #else 5258 TCGv t0; 5259 5260 CHK_SV(ctx); 5261 t0 = tcg_temp_new(); 5262 gen_addr_reg_index(ctx, t0); 5263 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); 5264 if (Rc(ctx->opcode)) { 5265 TCGLabel *l1 = gen_new_label(); 5266 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5267 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5268 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5269 gen_set_label(l1); 5270 } 5271 #endif /* defined(CONFIG_USER_ONLY) */ 5272 } 5273 5274 /* tlbwe */ 5275 static void gen_tlbwe_440(DisasContext *ctx) 5276 { 5277 #if defined(CONFIG_USER_ONLY) 5278 GEN_PRIV(ctx); 5279 #else 5280 CHK_SV(ctx); 5281 switch (rB(ctx->opcode)) { 5282 case 0: 5283 case 1: 5284 case 2: 5285 { 5286 TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5287 gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], 5288 cpu_gpr[rS(ctx->opcode)]); 5289 } 5290 break; 5291 default: 5292 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5293 break; 5294 } 5295 #endif /* defined(CONFIG_USER_ONLY) */ 5296 } 5297 5298 /* TLB management - PowerPC BookE 2.06 implementation */ 5299 5300 /* tlbre */ 5301 static void gen_tlbre_booke206(DisasContext *ctx) 5302 { 5303 #if defined(CONFIG_USER_ONLY) 5304 GEN_PRIV(ctx); 5305 #else 5306 CHK_SV(ctx); 5307 gen_helper_booke206_tlbre(tcg_env); 5308 #endif /* defined(CONFIG_USER_ONLY) */ 5309 } 5310 5311 /* tlbsx - tlbsx. */ 5312 static void gen_tlbsx_booke206(DisasContext *ctx) 5313 { 5314 #if defined(CONFIG_USER_ONLY) 5315 GEN_PRIV(ctx); 5316 #else 5317 TCGv t0; 5318 5319 CHK_SV(ctx); 5320 if (rA(ctx->opcode)) { 5321 t0 = tcg_temp_new(); 5322 tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5323 } else { 5324 t0 = cpu_gpr[rB(ctx->opcode)]; 5325 } 5326 gen_helper_booke206_tlbsx(tcg_env, t0); 5327 #endif /* defined(CONFIG_USER_ONLY) */ 5328 } 5329 5330 /* tlbwe */ 5331 static void gen_tlbwe_booke206(DisasContext *ctx) 5332 { 5333 #if defined(CONFIG_USER_ONLY) 5334 GEN_PRIV(ctx); 5335 #else 5336 CHK_SV(ctx); 5337 gen_helper_booke206_tlbwe(tcg_env); 5338 #endif /* defined(CONFIG_USER_ONLY) */ 5339 } 5340 5341 static void gen_tlbivax_booke206(DisasContext *ctx) 5342 { 5343 #if defined(CONFIG_USER_ONLY) 5344 GEN_PRIV(ctx); 5345 #else 5346 TCGv t0; 5347 5348 CHK_SV(ctx); 5349 t0 = tcg_temp_new(); 5350 gen_addr_reg_index(ctx, t0); 5351 gen_helper_booke206_tlbivax(tcg_env, t0); 5352 #endif /* defined(CONFIG_USER_ONLY) */ 5353 } 5354 5355 static void gen_tlbilx_booke206(DisasContext *ctx) 5356 { 5357 #if defined(CONFIG_USER_ONLY) 5358 GEN_PRIV(ctx); 5359 #else 5360 TCGv t0; 5361 5362 CHK_SV(ctx); 5363 t0 = tcg_temp_new(); 5364 gen_addr_reg_index(ctx, t0); 5365 5366 switch ((ctx->opcode >> 21) & 0x3) { 5367 case 0: 5368 gen_helper_booke206_tlbilx0(tcg_env, t0); 5369 break; 5370 case 1: 5371 gen_helper_booke206_tlbilx1(tcg_env, t0); 5372 break; 5373 case 3: 5374 gen_helper_booke206_tlbilx3(tcg_env, t0); 5375 break; 5376 default: 5377 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5378 break; 5379 } 5380 #endif /* defined(CONFIG_USER_ONLY) */ 5381 } 5382 5383 /* wrtee */ 5384 static void gen_wrtee(DisasContext *ctx) 5385 { 5386 #if defined(CONFIG_USER_ONLY) 5387 GEN_PRIV(ctx); 5388 #else 5389 TCGv t0; 5390 5391 CHK_SV(ctx); 5392 t0 = tcg_temp_new(); 5393 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5394 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5395 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 5396 gen_ppc_maybe_interrupt(ctx); 5397 /* 5398 * Stop translation to have a chance to raise an exception if we 5399 * just set msr_ee to 1 5400 */ 5401 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5402 #endif /* defined(CONFIG_USER_ONLY) */ 5403 } 5404 5405 /* wrteei */ 5406 static void gen_wrteei(DisasContext *ctx) 5407 { 5408 #if defined(CONFIG_USER_ONLY) 5409 GEN_PRIV(ctx); 5410 #else 5411 CHK_SV(ctx); 5412 if (ctx->opcode & 0x00008000) { 5413 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 5414 gen_ppc_maybe_interrupt(ctx); 5415 /* Stop translation to have a chance to raise an exception */ 5416 ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5417 } else { 5418 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5419 } 5420 #endif /* defined(CONFIG_USER_ONLY) */ 5421 } 5422 5423 /* PowerPC 440 specific instructions */ 5424 5425 /* dlmzb */ 5426 static void gen_dlmzb(DisasContext *ctx) 5427 { 5428 TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 5429 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, 5430 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 5431 } 5432 5433 /* icbt */ 5434 static void gen_icbt_440(DisasContext *ctx) 5435 { 5436 /* 5437 * interpreted as no-op 5438 * XXX: specification say this is treated as a load by the MMU but 5439 * does not generate any exception 5440 */ 5441 } 5442 5443 static void gen_tbegin(DisasContext *ctx) 5444 { 5445 if (unlikely(!ctx->tm_enabled)) { 5446 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5447 return; 5448 } 5449 gen_helper_tbegin(tcg_env); 5450 } 5451 5452 #define GEN_TM_NOOP(name) \ 5453 static inline void gen_##name(DisasContext *ctx) \ 5454 { \ 5455 if (unlikely(!ctx->tm_enabled)) { \ 5456 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5457 return; \ 5458 } \ 5459 /* \ 5460 * Because tbegin always fails in QEMU, these user \ 5461 * space instructions all have a simple implementation: \ 5462 * \ 5463 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5464 * = 0b0 || 0b00 || 0b0 \ 5465 */ \ 5466 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5467 } 5468 5469 GEN_TM_NOOP(tend); 5470 GEN_TM_NOOP(tabort); 5471 GEN_TM_NOOP(tabortwc); 5472 GEN_TM_NOOP(tabortwci); 5473 GEN_TM_NOOP(tabortdc); 5474 GEN_TM_NOOP(tabortdci); 5475 GEN_TM_NOOP(tsr); 5476 5477 static inline void gen_cp_abort(DisasContext *ctx) 5478 { 5479 /* Do Nothing */ 5480 } 5481 5482 #define GEN_CP_PASTE_NOOP(name) \ 5483 static inline void gen_##name(DisasContext *ctx) \ 5484 { \ 5485 /* \ 5486 * Generate invalid exception until we have an \ 5487 * implementation of the copy paste facility \ 5488 */ \ 5489 gen_invalid(ctx); \ 5490 } 5491 5492 GEN_CP_PASTE_NOOP(copy) 5493 GEN_CP_PASTE_NOOP(paste) 5494 5495 static void gen_tcheck(DisasContext *ctx) 5496 { 5497 if (unlikely(!ctx->tm_enabled)) { 5498 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 5499 return; 5500 } 5501 /* 5502 * Because tbegin always fails, the tcheck implementation is 5503 * simple: 5504 * 5505 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 5506 * = 0b1 || 0b00 || 0b0 5507 */ 5508 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 5509 } 5510 5511 #if defined(CONFIG_USER_ONLY) 5512 #define GEN_TM_PRIV_NOOP(name) \ 5513 static inline void gen_##name(DisasContext *ctx) \ 5514 { \ 5515 gen_priv_opc(ctx); \ 5516 } 5517 5518 #else 5519 5520 #define GEN_TM_PRIV_NOOP(name) \ 5521 static inline void gen_##name(DisasContext *ctx) \ 5522 { \ 5523 CHK_SV(ctx); \ 5524 if (unlikely(!ctx->tm_enabled)) { \ 5525 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 5526 return; \ 5527 } \ 5528 /* \ 5529 * Because tbegin always fails, the implementation is \ 5530 * simple: \ 5531 * \ 5532 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 5533 * = 0b0 || 0b00 | 0b0 \ 5534 */ \ 5535 tcg_gen_movi_i32(cpu_crf[0], 0); \ 5536 } 5537 5538 #endif 5539 5540 GEN_TM_PRIV_NOOP(treclaim); 5541 GEN_TM_PRIV_NOOP(trechkpt); 5542 5543 static inline void get_fpr(TCGv_i64 dst, int regno) 5544 { 5545 tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); 5546 } 5547 5548 static inline void set_fpr(int regno, TCGv_i64 src) 5549 { 5550 tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); 5551 /* 5552 * Before PowerISA v3.1 the result of doubleword 1 of the VSR 5553 * corresponding to the target FPR was undefined. However, 5554 * most (if not all) real hardware were setting the result to 0. 5555 * Starting at ISA v3.1, the result for doubleword 1 is now defined 5556 * to be 0. 5557 */ 5558 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false)); 5559 } 5560 5561 /* 5562 * Helpers for decodetree used by !function for decoding arguments. 5563 */ 5564 static int times_2(DisasContext *ctx, int x) 5565 { 5566 return x * 2; 5567 } 5568 5569 static int times_4(DisasContext *ctx, int x) 5570 { 5571 return x * 4; 5572 } 5573 5574 static int times_16(DisasContext *ctx, int x) 5575 { 5576 return x * 16; 5577 } 5578 5579 static int64_t dw_compose_ea(DisasContext *ctx, int x) 5580 { 5581 return deposit64(0xfffffffffffffe00, 3, 6, x); 5582 } 5583 5584 /* 5585 * Helpers for trans_* functions to check for specific insns flags. 5586 * Use token pasting to ensure that we use the proper flag with the 5587 * proper variable. 5588 */ 5589 #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 5590 do { \ 5591 if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 5592 return false; \ 5593 } \ 5594 } while (0) 5595 5596 #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 5597 do { \ 5598 if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 5599 return false; \ 5600 } \ 5601 } while (0) 5602 5603 /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 5604 #if TARGET_LONG_BITS == 32 5605 # define REQUIRE_64BIT(CTX) return false 5606 #else 5607 # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 5608 #endif 5609 5610 #define REQUIRE_VECTOR(CTX) \ 5611 do { \ 5612 if (unlikely(!(CTX)->altivec_enabled)) { \ 5613 gen_exception((CTX), POWERPC_EXCP_VPU); \ 5614 return true; \ 5615 } \ 5616 } while (0) 5617 5618 #define REQUIRE_VSX(CTX) \ 5619 do { \ 5620 if (unlikely(!(CTX)->vsx_enabled)) { \ 5621 gen_exception((CTX), POWERPC_EXCP_VSXU); \ 5622 return true; \ 5623 } \ 5624 } while (0) 5625 5626 #define REQUIRE_FPU(ctx) \ 5627 do { \ 5628 if (unlikely(!(ctx)->fpu_enabled)) { \ 5629 gen_exception((ctx), POWERPC_EXCP_FPU); \ 5630 return true; \ 5631 } \ 5632 } while (0) 5633 5634 #if !defined(CONFIG_USER_ONLY) 5635 #define REQUIRE_SV(CTX) \ 5636 do { \ 5637 if (unlikely((CTX)->pr)) { \ 5638 gen_priv_opc(CTX); \ 5639 return true; \ 5640 } \ 5641 } while (0) 5642 5643 #define REQUIRE_HV(CTX) \ 5644 do { \ 5645 if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 5646 gen_priv_opc(CTX); \ 5647 return true; \ 5648 } \ 5649 } while (0) 5650 #else 5651 #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5652 #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 5653 #endif 5654 5655 /* 5656 * Helpers for implementing sets of trans_* functions. 5657 * Defer the implementation of NAME to FUNC, with optional extra arguments. 5658 */ 5659 #define TRANS(NAME, FUNC, ...) \ 5660 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5661 { return FUNC(ctx, a, __VA_ARGS__); } 5662 #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 5663 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5664 { \ 5665 REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 5666 return FUNC(ctx, a, __VA_ARGS__); \ 5667 } 5668 #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5669 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5670 { \ 5671 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5672 return FUNC(ctx, a, __VA_ARGS__); \ 5673 } 5674 5675 #define TRANS64(NAME, FUNC, ...) \ 5676 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5677 { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 5678 #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 5679 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 5680 { \ 5681 REQUIRE_64BIT(ctx); \ 5682 REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 5683 return FUNC(ctx, a, __VA_ARGS__); \ 5684 } 5685 5686 /* TODO: More TRANS* helpers for extra insn_flags checks. */ 5687 5688 5689 #include "decode-insn32.c.inc" 5690 #include "decode-insn64.c.inc" 5691 #include "power8-pmu-regs.c.inc" 5692 5693 /* 5694 * Incorporate CIA into the constant when R=1. 5695 * Validate that when R=1, RA=0. 5696 */ 5697 static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 5698 { 5699 d->rt = a->rt; 5700 d->ra = a->ra; 5701 d->si = a->si; 5702 if (a->r) { 5703 if (unlikely(a->ra != 0)) { 5704 gen_invalid(ctx); 5705 return false; 5706 } 5707 d->si += ctx->cia; 5708 } 5709 return true; 5710 } 5711 5712 #include "translate/fixedpoint-impl.c.inc" 5713 5714 #include "translate/fp-impl.c.inc" 5715 5716 #include "translate/vmx-impl.c.inc" 5717 5718 #include "translate/vsx-impl.c.inc" 5719 5720 #include "translate/dfp-impl.c.inc" 5721 5722 #include "translate/spe-impl.c.inc" 5723 5724 #include "translate/branch-impl.c.inc" 5725 5726 #include "translate/processor-ctrl-impl.c.inc" 5727 5728 #include "translate/storage-ctrl-impl.c.inc" 5729 5730 #include "translate/misc-impl.c.inc" 5731 5732 #include "translate/bhrb-impl.c.inc" 5733 5734 /* Handles lfdp */ 5735 static void gen_dform39(DisasContext *ctx) 5736 { 5737 if ((ctx->opcode & 0x3) == 0) { 5738 if (ctx->insns_flags2 & PPC2_ISA205) { 5739 return gen_lfdp(ctx); 5740 } 5741 } 5742 return gen_invalid(ctx); 5743 } 5744 5745 /* Handles stfdp */ 5746 static void gen_dform3D(DisasContext *ctx) 5747 { 5748 if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 5749 /* stfdp */ 5750 if (ctx->insns_flags2 & PPC2_ISA205) { 5751 return gen_stfdp(ctx); 5752 } 5753 } 5754 return gen_invalid(ctx); 5755 } 5756 5757 #if defined(TARGET_PPC64) 5758 /* brd */ 5759 static void gen_brd(DisasContext *ctx) 5760 { 5761 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5762 } 5763 5764 /* brw */ 5765 static void gen_brw(DisasContext *ctx) 5766 { 5767 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 5768 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 5769 5770 } 5771 5772 /* brh */ 5773 static void gen_brh(DisasContext *ctx) 5774 { 5775 TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 5776 TCGv_i64 t1 = tcg_temp_new_i64(); 5777 TCGv_i64 t2 = tcg_temp_new_i64(); 5778 5779 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 5780 tcg_gen_and_i64(t2, t1, mask); 5781 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 5782 tcg_gen_shli_i64(t1, t1, 8); 5783 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 5784 } 5785 #endif 5786 5787 static opcode_t opcodes[] = { 5788 #if defined(TARGET_PPC64) 5789 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 5790 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 5791 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 5792 #endif 5793 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 5794 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 5795 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5796 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 5797 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5798 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5799 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5800 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 5801 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 5802 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 5803 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 5804 #if defined(TARGET_PPC64) 5805 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 5806 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 5807 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 5808 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 5809 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 5810 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 5811 PPC_NONE, PPC2_ISA300), 5812 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 5813 PPC_NONE, PPC2_ISA300), 5814 #endif 5815 /* handles lfdp, lxsd, lxssp */ 5816 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5817 /* handles stfdp, stxsd, stxssp */ 5818 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 5819 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5820 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 5821 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 5822 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 5823 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 5824 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 5825 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 5826 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5827 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5828 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 5829 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 5830 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 5831 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5832 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 5833 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 5834 #if defined(TARGET_PPC64) 5835 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 5836 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 5837 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 5838 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 5839 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 5840 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 5841 #endif 5842 /* ISA v3.0 changed the extended opcode from 62 to 30 */ 5843 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 5844 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 5845 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5846 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 5847 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 5848 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 5849 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 5850 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 5851 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 5852 #if defined(TARGET_PPC64) 5853 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 5854 #if !defined(CONFIG_USER_ONLY) 5855 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5856 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5857 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 5858 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 5859 #endif 5860 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 5861 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5862 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5863 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5864 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 5865 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 5866 #endif 5867 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 5868 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 5869 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 5870 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 5871 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 5872 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 5873 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 5874 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 5875 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 5876 #if defined(TARGET_PPC64) 5877 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 5878 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 5879 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 5880 #endif 5881 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 5882 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 5883 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 5884 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5885 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 5886 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 5887 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5888 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 5889 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5890 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 5891 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 5892 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5893 GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 5894 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 5895 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 5896 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 5897 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 5898 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 5899 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 5900 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 5901 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 5902 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 5903 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 5904 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 5905 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 5906 #if defined(TARGET_PPC64) 5907 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 5908 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 5909 PPC_SEGMENT_64B), 5910 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 5911 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 5912 PPC_SEGMENT_64B), 5913 #endif 5914 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 5915 /* 5916 * XXX Those instructions will need to be handled differently for 5917 * different ISA versions 5918 */ 5919 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 5920 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 5921 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 5922 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 5923 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 5924 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 5925 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 5926 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 5927 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 5928 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 5929 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 5930 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 5931 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 5932 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 5933 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 5934 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 5935 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 5936 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 5937 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 5938 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 5939 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 5940 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 5941 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 5942 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 5943 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 5944 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 5945 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 5946 PPC_NONE, PPC2_BOOKE206), 5947 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 5948 PPC_NONE, PPC2_BOOKE206), 5949 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 5950 PPC_NONE, PPC2_BOOKE206), 5951 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 5952 PPC_NONE, PPC2_BOOKE206), 5953 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 5954 PPC_NONE, PPC2_BOOKE206), 5955 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 5956 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 5957 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 5958 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 5959 PPC_BOOKE, PPC2_BOOKE206), 5960 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 5961 PPC_440_SPEC), 5962 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 5963 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 5964 5965 #if defined(TARGET_PPC64) 5966 #undef GEN_PPC64_R2 5967 #undef GEN_PPC64_R4 5968 #define GEN_PPC64_R2(name, opc1, opc2) \ 5969 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 5970 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 5971 PPC_64B) 5972 #define GEN_PPC64_R4(name, opc1, opc2) \ 5973 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 5974 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 5975 PPC_64B), \ 5976 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 5977 PPC_64B), \ 5978 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 5979 PPC_64B) 5980 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 5981 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 5982 GEN_PPC64_R4(rldic, 0x1E, 0x04), 5983 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 5984 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 5985 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 5986 #endif 5987 5988 #undef GEN_LDX_E 5989 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 5990 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 5991 5992 #if defined(TARGET_PPC64) 5993 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 5994 5995 /* HV/P7 and later only */ 5996 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 5997 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 5998 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 5999 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6000 #endif 6001 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6002 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6003 6004 /* External PID based load */ 6005 #undef GEN_LDEPX 6006 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 6007 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6008 0x00000001, PPC_NONE, PPC2_BOOKE206), 6009 6010 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 6011 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 6012 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 6013 #if defined(TARGET_PPC64) 6014 GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 6015 #endif 6016 6017 #undef GEN_STX_E 6018 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6019 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6020 6021 #if defined(TARGET_PPC64) 6022 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6023 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6024 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6025 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6026 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6027 #endif 6028 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6029 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6030 6031 #undef GEN_STEPX 6032 #define GEN_STEPX(name, ldop, opc2, opc3) \ 6033 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 6034 0x00000001, PPC_NONE, PPC2_BOOKE206), 6035 6036 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 6037 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 6038 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 6039 #if defined(TARGET_PPC64) 6040 GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 6041 #endif 6042 6043 #undef GEN_CRLOGIC 6044 #define GEN_CRLOGIC(name, tcg_op, opc) \ 6045 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6046 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6047 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6048 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6049 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6050 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6051 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6052 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6053 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6054 6055 #undef GEN_MAC_HANDLER 6056 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6057 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6058 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6059 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6060 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6061 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6062 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6063 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6064 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6065 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6066 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6067 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6068 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6069 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6070 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6071 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6072 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6073 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6074 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6075 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6076 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6077 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6078 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6079 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6080 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6081 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6082 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6083 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6084 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6085 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6086 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6087 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6088 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6089 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6090 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6091 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6092 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6093 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6094 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6095 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6096 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6097 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6098 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6099 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6100 6101 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6102 PPC_NONE, PPC2_TM), 6103 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6104 PPC_NONE, PPC2_TM), 6105 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6106 PPC_NONE, PPC2_TM), 6107 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6108 PPC_NONE, PPC2_TM), 6109 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6110 PPC_NONE, PPC2_TM), 6111 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6112 PPC_NONE, PPC2_TM), 6113 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6114 PPC_NONE, PPC2_TM), 6115 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6116 PPC_NONE, PPC2_TM), 6117 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6118 PPC_NONE, PPC2_TM), 6119 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6120 PPC_NONE, PPC2_TM), 6121 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6122 PPC_NONE, PPC2_TM), 6123 6124 #include "translate/fp-ops.c.inc" 6125 6126 #include "translate/vmx-ops.c.inc" 6127 6128 #include "translate/vsx-ops.c.inc" 6129 6130 #include "translate/spe-ops.c.inc" 6131 }; 6132 6133 /*****************************************************************************/ 6134 /* Opcode types */ 6135 enum { 6136 PPC_DIRECT = 0, /* Opcode routine */ 6137 PPC_INDIRECT = 1, /* Indirect opcode table */ 6138 }; 6139 6140 #define PPC_OPCODE_MASK 0x3 6141 6142 static inline int is_indirect_opcode(void *handler) 6143 { 6144 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 6145 } 6146 6147 static inline opc_handler_t **ind_table(void *handler) 6148 { 6149 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 6150 } 6151 6152 /* Instruction table creation */ 6153 /* Opcodes tables creation */ 6154 static void fill_new_table(opc_handler_t **table, int len) 6155 { 6156 int i; 6157 6158 for (i = 0; i < len; i++) { 6159 table[i] = &invalid_handler; 6160 } 6161 } 6162 6163 static int create_new_table(opc_handler_t **table, unsigned char idx) 6164 { 6165 opc_handler_t **tmp; 6166 6167 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 6168 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 6169 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 6170 6171 return 0; 6172 } 6173 6174 static int insert_in_table(opc_handler_t **table, unsigned char idx, 6175 opc_handler_t *handler) 6176 { 6177 if (table[idx] != &invalid_handler) { 6178 return -1; 6179 } 6180 table[idx] = handler; 6181 6182 return 0; 6183 } 6184 6185 static int register_direct_insn(opc_handler_t **ppc_opcodes, 6186 unsigned char idx, opc_handler_t *handler) 6187 { 6188 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 6189 printf("*** ERROR: opcode %02x already assigned in main " 6190 "opcode table\n", idx); 6191 return -1; 6192 } 6193 6194 return 0; 6195 } 6196 6197 static int register_ind_in_table(opc_handler_t **table, 6198 unsigned char idx1, unsigned char idx2, 6199 opc_handler_t *handler) 6200 { 6201 if (table[idx1] == &invalid_handler) { 6202 if (create_new_table(table, idx1) < 0) { 6203 printf("*** ERROR: unable to create indirect table " 6204 "idx=%02x\n", idx1); 6205 return -1; 6206 } 6207 } else { 6208 if (!is_indirect_opcode(table[idx1])) { 6209 printf("*** ERROR: idx %02x already assigned to a direct " 6210 "opcode\n", idx1); 6211 return -1; 6212 } 6213 } 6214 if (handler != NULL && 6215 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 6216 printf("*** ERROR: opcode %02x already assigned in " 6217 "opcode table %02x\n", idx2, idx1); 6218 return -1; 6219 } 6220 6221 return 0; 6222 } 6223 6224 static int register_ind_insn(opc_handler_t **ppc_opcodes, 6225 unsigned char idx1, unsigned char idx2, 6226 opc_handler_t *handler) 6227 { 6228 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 6229 } 6230 6231 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 6232 unsigned char idx1, unsigned char idx2, 6233 unsigned char idx3, opc_handler_t *handler) 6234 { 6235 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6236 printf("*** ERROR: unable to join indirect table idx " 6237 "[%02x-%02x]\n", idx1, idx2); 6238 return -1; 6239 } 6240 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 6241 handler) < 0) { 6242 printf("*** ERROR: unable to insert opcode " 6243 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6244 return -1; 6245 } 6246 6247 return 0; 6248 } 6249 6250 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 6251 unsigned char idx1, unsigned char idx2, 6252 unsigned char idx3, unsigned char idx4, 6253 opc_handler_t *handler) 6254 { 6255 opc_handler_t **table; 6256 6257 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 6258 printf("*** ERROR: unable to join indirect table idx " 6259 "[%02x-%02x]\n", idx1, idx2); 6260 return -1; 6261 } 6262 table = ind_table(ppc_opcodes[idx1]); 6263 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 6264 printf("*** ERROR: unable to join 2nd-level indirect table idx " 6265 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 6266 return -1; 6267 } 6268 table = ind_table(table[idx2]); 6269 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 6270 printf("*** ERROR: unable to insert opcode " 6271 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 6272 return -1; 6273 } 6274 return 0; 6275 } 6276 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 6277 { 6278 if (insn->opc2 != 0xFF) { 6279 if (insn->opc3 != 0xFF) { 6280 if (insn->opc4 != 0xFF) { 6281 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6282 insn->opc3, insn->opc4, 6283 &insn->handler) < 0) { 6284 return -1; 6285 } 6286 } else { 6287 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 6288 insn->opc3, &insn->handler) < 0) { 6289 return -1; 6290 } 6291 } 6292 } else { 6293 if (register_ind_insn(ppc_opcodes, insn->opc1, 6294 insn->opc2, &insn->handler) < 0) { 6295 return -1; 6296 } 6297 } 6298 } else { 6299 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 6300 return -1; 6301 } 6302 } 6303 6304 return 0; 6305 } 6306 6307 static int test_opcode_table(opc_handler_t **table, int len) 6308 { 6309 int i, count, tmp; 6310 6311 for (i = 0, count = 0; i < len; i++) { 6312 /* Consistency fixup */ 6313 if (table[i] == NULL) { 6314 table[i] = &invalid_handler; 6315 } 6316 if (table[i] != &invalid_handler) { 6317 if (is_indirect_opcode(table[i])) { 6318 tmp = test_opcode_table(ind_table(table[i]), 6319 PPC_CPU_INDIRECT_OPCODES_LEN); 6320 if (tmp == 0) { 6321 g_free(table[i]); 6322 table[i] = &invalid_handler; 6323 } else { 6324 count++; 6325 } 6326 } else { 6327 count++; 6328 } 6329 } 6330 } 6331 6332 return count; 6333 } 6334 6335 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 6336 { 6337 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 6338 printf("*** WARNING: no opcode defined !\n"); 6339 } 6340 } 6341 6342 /*****************************************************************************/ 6343 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 6344 { 6345 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6346 opcode_t *opc; 6347 6348 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 6349 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 6350 if (((opc->handler.type & pcc->insns_flags) != 0) || 6351 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 6352 if (register_insn(cpu->opcodes, opc) < 0) { 6353 error_setg(errp, "ERROR initializing PowerPC instruction " 6354 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 6355 opc->opc3); 6356 return; 6357 } 6358 } 6359 } 6360 fix_opcode_tables(cpu->opcodes); 6361 fflush(stdout); 6362 fflush(stderr); 6363 } 6364 6365 void destroy_ppc_opcodes(PowerPCCPU *cpu) 6366 { 6367 opc_handler_t **table, **table_2; 6368 int i, j, k; 6369 6370 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 6371 if (cpu->opcodes[i] == &invalid_handler) { 6372 continue; 6373 } 6374 if (is_indirect_opcode(cpu->opcodes[i])) { 6375 table = ind_table(cpu->opcodes[i]); 6376 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 6377 if (table[j] == &invalid_handler) { 6378 continue; 6379 } 6380 if (is_indirect_opcode(table[j])) { 6381 table_2 = ind_table(table[j]); 6382 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 6383 if (table_2[k] != &invalid_handler && 6384 is_indirect_opcode(table_2[k])) { 6385 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 6386 ~PPC_INDIRECT)); 6387 } 6388 } 6389 g_free((opc_handler_t *)((uintptr_t)table[j] & 6390 ~PPC_INDIRECT)); 6391 } 6392 } 6393 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 6394 ~PPC_INDIRECT)); 6395 } 6396 } 6397 } 6398 6399 int ppc_fixup_cpu(PowerPCCPU *cpu) 6400 { 6401 CPUPPCState *env = &cpu->env; 6402 6403 /* 6404 * TCG doesn't (yet) emulate some groups of instructions that are 6405 * implemented on some otherwise supported CPUs (e.g. VSX and 6406 * decimal floating point instructions on POWER7). We remove 6407 * unsupported instruction groups from the cpu state's instruction 6408 * masks and hope the guest can cope. For at least the pseries 6409 * machine, the unavailability of these instructions can be 6410 * advertised to the guest via the device tree. 6411 */ 6412 if ((env->insns_flags & ~PPC_TCG_INSNS) 6413 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 6414 warn_report("Disabling some instructions which are not " 6415 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 6416 env->insns_flags & ~PPC_TCG_INSNS, 6417 env->insns_flags2 & ~PPC_TCG_INSNS2); 6418 } 6419 env->insns_flags &= PPC_TCG_INSNS; 6420 env->insns_flags2 &= PPC_TCG_INSNS2; 6421 return 0; 6422 } 6423 6424 static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 6425 { 6426 opc_handler_t **table, *handler; 6427 uint32_t inval; 6428 6429 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 6430 insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6431 ctx->le_mode ? "little" : "big"); 6432 6433 table = cpu->opcodes; 6434 handler = table[opc1(insn)]; 6435 if (is_indirect_opcode(handler)) { 6436 table = ind_table(handler); 6437 handler = table[opc2(insn)]; 6438 if (is_indirect_opcode(handler)) { 6439 table = ind_table(handler); 6440 handler = table[opc3(insn)]; 6441 if (is_indirect_opcode(handler)) { 6442 table = ind_table(handler); 6443 handler = table[opc4(insn)]; 6444 } 6445 } 6446 } 6447 6448 /* Is opcode *REALLY* valid ? */ 6449 if (unlikely(handler->handler == &gen_invalid)) { 6450 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 6451 "%02x - %02x - %02x - %02x (%08x) " 6452 TARGET_FMT_lx "\n", 6453 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6454 insn, ctx->cia); 6455 return false; 6456 } 6457 6458 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 6459 && Rc(insn))) { 6460 inval = handler->inval2; 6461 } else { 6462 inval = handler->inval1; 6463 } 6464 6465 if (unlikely((insn & inval) != 0)) { 6466 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 6467 "%02x - %02x - %02x - %02x (%08x) " 6468 TARGET_FMT_lx "\n", insn & inval, 6469 opc1(insn), opc2(insn), opc3(insn), opc4(insn), 6470 insn, ctx->cia); 6471 return false; 6472 } 6473 6474 handler->handler(ctx); 6475 return true; 6476 } 6477 6478 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 6479 { 6480 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6481 CPUPPCState *env = cpu_env(cs); 6482 uint32_t hflags = ctx->base.tb->flags; 6483 6484 ctx->spr_cb = env->spr_cb; 6485 ctx->pr = (hflags >> HFLAGS_PR) & 1; 6486 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 6487 ctx->dr = (hflags >> HFLAGS_DR) & 1; 6488 ctx->hv = (hflags >> HFLAGS_HV) & 1; 6489 ctx->insns_flags = env->insns_flags; 6490 ctx->insns_flags2 = env->insns_flags2; 6491 ctx->access_type = -1; 6492 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 6493 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 6494 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 6495 ctx->flags = env->flags; 6496 #if defined(TARGET_PPC64) 6497 ctx->excp_model = env->excp_model; 6498 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 6499 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 6500 ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB); 6501 #endif 6502 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 6503 || env->mmu_model & POWERPC_MMU_64; 6504 6505 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 6506 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 6507 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 6508 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 6509 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 6510 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 6511 ctx->hr = (hflags >> HFLAGS_HR) & 1; 6512 ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 6513 ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 6514 ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 6515 ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 6516 ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 6517 ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1; 6518 6519 ctx->singlestep_enabled = 0; 6520 if ((hflags >> HFLAGS_SE) & 1) { 6521 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 6522 ctx->base.max_insns = 1; 6523 } 6524 if ((hflags >> HFLAGS_BE) & 1) { 6525 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 6526 } 6527 } 6528 6529 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 6530 { 6531 } 6532 6533 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 6534 { 6535 tcg_gen_insn_start(dcbase->pc_next); 6536 } 6537 6538 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 6539 { 6540 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 6541 return opc1(insn) == 1; 6542 } 6543 6544 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 6545 { 6546 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6547 PowerPCCPU *cpu = POWERPC_CPU(cs); 6548 CPUPPCState *env = cpu_env(cs); 6549 target_ulong pc; 6550 uint32_t insn; 6551 bool ok; 6552 6553 LOG_DISAS("----------------\n"); 6554 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 6555 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 6556 6557 ctx->cia = pc = ctx->base.pc_next; 6558 insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 6559 ctx->base.pc_next = pc += 4; 6560 6561 if (!is_prefix_insn(ctx, insn)) { 6562 ctx->opcode = insn; 6563 ok = (decode_insn32(ctx, insn) || 6564 decode_legacy(cpu, ctx, insn)); 6565 } else if ((pc & 63) == 0) { 6566 /* 6567 * Power v3.1, section 1.9 Exceptions: 6568 * attempt to execute a prefixed instruction that crosses a 6569 * 64-byte address boundary (system alignment error). 6570 */ 6571 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 6572 ok = true; 6573 } else { 6574 uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 6575 need_byteswap(ctx)); 6576 ctx->base.pc_next = pc += 4; 6577 ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 6578 } 6579 if (!ok) { 6580 gen_invalid(ctx); 6581 } 6582 6583 /* End the TB when crossing a page boundary. */ 6584 if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 6585 ctx->base.is_jmp = DISAS_TOO_MANY; 6586 } 6587 } 6588 6589 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 6590 { 6591 DisasContext *ctx = container_of(dcbase, DisasContext, base); 6592 DisasJumpType is_jmp = ctx->base.is_jmp; 6593 target_ulong nip = ctx->base.pc_next; 6594 6595 if (is_jmp == DISAS_NORETURN) { 6596 /* We have already exited the TB. */ 6597 return; 6598 } 6599 6600 /* Honor single stepping. */ 6601 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 6602 bool rfi_type = false; 6603 6604 switch (is_jmp) { 6605 case DISAS_TOO_MANY: 6606 case DISAS_EXIT_UPDATE: 6607 case DISAS_CHAIN_UPDATE: 6608 gen_update_nip(ctx, nip); 6609 break; 6610 case DISAS_EXIT: 6611 case DISAS_CHAIN: 6612 /* 6613 * This is a heuristic, to put it kindly. The rfi class of 6614 * instructions are among the few outside branches that change 6615 * NIP without taking an interrupt. Single step trace interrupts 6616 * do not fire on completion of these instructions. 6617 */ 6618 rfi_type = true; 6619 break; 6620 default: 6621 g_assert_not_reached(); 6622 } 6623 6624 gen_debug_exception(ctx, rfi_type); 6625 return; 6626 } 6627 6628 switch (is_jmp) { 6629 case DISAS_TOO_MANY: 6630 if (use_goto_tb(ctx, nip)) { 6631 pmu_count_insns(ctx); 6632 tcg_gen_goto_tb(0); 6633 gen_update_nip(ctx, nip); 6634 tcg_gen_exit_tb(ctx->base.tb, 0); 6635 break; 6636 } 6637 /* fall through */ 6638 case DISAS_CHAIN_UPDATE: 6639 gen_update_nip(ctx, nip); 6640 /* fall through */ 6641 case DISAS_CHAIN: 6642 /* 6643 * tcg_gen_lookup_and_goto_ptr will exit the TB if 6644 * CF_NO_GOTO_PTR is set. Count insns now. 6645 */ 6646 if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 6647 pmu_count_insns(ctx); 6648 } 6649 6650 tcg_gen_lookup_and_goto_ptr(); 6651 break; 6652 6653 case DISAS_EXIT_UPDATE: 6654 gen_update_nip(ctx, nip); 6655 /* fall through */ 6656 case DISAS_EXIT: 6657 pmu_count_insns(ctx); 6658 tcg_gen_exit_tb(NULL, 0); 6659 break; 6660 6661 default: 6662 g_assert_not_reached(); 6663 } 6664 } 6665 6666 static const TranslatorOps ppc_tr_ops = { 6667 .init_disas_context = ppc_tr_init_disas_context, 6668 .tb_start = ppc_tr_tb_start, 6669 .insn_start = ppc_tr_insn_start, 6670 .translate_insn = ppc_tr_translate_insn, 6671 .tb_stop = ppc_tr_tb_stop, 6672 }; 6673 6674 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 6675 vaddr pc, void *host_pc) 6676 { 6677 DisasContext ctx; 6678 6679 translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 6680 } 6681