1 /* 2 * PowerPC emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/helper-proto.h" 22 #include "exec/exec-all.h" 23 #include "qemu/log.h" 24 #include "qemu/main-loop.h" 25 26 /*****************************************************************************/ 27 /* SPR accesses */ 28 29 target_ulong helper_load_tbl(CPUPPCState *env) 30 { 31 return (target_ulong)cpu_ppc_load_tbl(env); 32 } 33 34 target_ulong helper_load_tbu(CPUPPCState *env) 35 { 36 return cpu_ppc_load_tbu(env); 37 } 38 39 target_ulong helper_load_atbl(CPUPPCState *env) 40 { 41 return (target_ulong)cpu_ppc_load_atbl(env); 42 } 43 44 target_ulong helper_load_atbu(CPUPPCState *env) 45 { 46 return cpu_ppc_load_atbu(env); 47 } 48 49 target_ulong helper_load_vtb(CPUPPCState *env) 50 { 51 return cpu_ppc_load_vtb(env); 52 } 53 54 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 55 target_ulong helper_load_purr(CPUPPCState *env) 56 { 57 return (target_ulong)cpu_ppc_load_purr(env); 58 } 59 60 void helper_store_purr(CPUPPCState *env, target_ulong val) 61 { 62 cpu_ppc_store_purr(env, val); 63 } 64 #endif 65 66 target_ulong helper_load_601_rtcl(CPUPPCState *env) 67 { 68 return cpu_ppc601_load_rtcl(env); 69 } 70 71 target_ulong helper_load_601_rtcu(CPUPPCState *env) 72 { 73 return cpu_ppc601_load_rtcu(env); 74 } 75 76 #if !defined(CONFIG_USER_ONLY) 77 void helper_store_tbl(CPUPPCState *env, target_ulong val) 78 { 79 cpu_ppc_store_tbl(env, val); 80 } 81 82 void helper_store_tbu(CPUPPCState *env, target_ulong val) 83 { 84 cpu_ppc_store_tbu(env, val); 85 } 86 87 void helper_store_atbl(CPUPPCState *env, target_ulong val) 88 { 89 cpu_ppc_store_atbl(env, val); 90 } 91 92 void helper_store_atbu(CPUPPCState *env, target_ulong val) 93 { 94 cpu_ppc_store_atbu(env, val); 95 } 96 97 void helper_store_601_rtcl(CPUPPCState *env, target_ulong val) 98 { 99 cpu_ppc601_store_rtcl(env, val); 100 } 101 102 void helper_store_601_rtcu(CPUPPCState *env, target_ulong val) 103 { 104 cpu_ppc601_store_rtcu(env, val); 105 } 106 107 target_ulong helper_load_decr(CPUPPCState *env) 108 { 109 return cpu_ppc_load_decr(env); 110 } 111 112 void helper_store_decr(CPUPPCState *env, target_ulong val) 113 { 114 cpu_ppc_store_decr(env, val); 115 } 116 117 target_ulong helper_load_hdecr(CPUPPCState *env) 118 { 119 return cpu_ppc_load_hdecr(env); 120 } 121 122 void helper_store_hdecr(CPUPPCState *env, target_ulong val) 123 { 124 cpu_ppc_store_hdecr(env, val); 125 } 126 127 void helper_store_vtb(CPUPPCState *env, target_ulong val) 128 { 129 cpu_ppc_store_vtb(env, val); 130 } 131 132 void helper_store_tbu40(CPUPPCState *env, target_ulong val) 133 { 134 cpu_ppc_store_tbu40(env, val); 135 } 136 137 target_ulong helper_load_40x_pit(CPUPPCState *env) 138 { 139 return load_40x_pit(env); 140 } 141 142 void helper_store_40x_pit(CPUPPCState *env, target_ulong val) 143 { 144 store_40x_pit(env, val); 145 } 146 147 void helper_store_40x_tcr(CPUPPCState *env, target_ulong val) 148 { 149 store_40x_tcr(env, val); 150 } 151 152 void helper_store_40x_tsr(CPUPPCState *env, target_ulong val) 153 { 154 store_40x_tsr(env, val); 155 } 156 157 void helper_store_booke_tcr(CPUPPCState *env, target_ulong val) 158 { 159 store_booke_tcr(env, val); 160 } 161 162 void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) 163 { 164 store_booke_tsr(env, val); 165 } 166 #endif 167 168 /*****************************************************************************/ 169 /* Embedded PowerPC specific helpers */ 170 171 /* XXX: to be improved to check access rights when in user-mode */ 172 target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) 173 { 174 uint32_t val = 0; 175 176 if (unlikely(env->dcr_env == NULL)) { 177 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); 178 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 179 POWERPC_EXCP_INVAL | 180 POWERPC_EXCP_INVAL_INVAL, GETPC()); 181 } else { 182 int ret; 183 184 qemu_mutex_lock_iothread(); 185 ret = ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val); 186 qemu_mutex_unlock_iothread(); 187 if (unlikely(ret != 0)) { 188 qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", 189 (uint32_t)dcrn, (uint32_t)dcrn); 190 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 191 POWERPC_EXCP_INVAL | 192 POWERPC_EXCP_PRIV_REG, GETPC()); 193 } 194 } 195 return val; 196 } 197 198 void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) 199 { 200 if (unlikely(env->dcr_env == NULL)) { 201 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); 202 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 203 POWERPC_EXCP_INVAL | 204 POWERPC_EXCP_INVAL_INVAL, GETPC()); 205 } else { 206 int ret; 207 qemu_mutex_lock_iothread(); 208 ret = ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val); 209 qemu_mutex_unlock_iothread(); 210 if (unlikely(ret != 0)) { 211 qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", 212 (uint32_t)dcrn, (uint32_t)dcrn); 213 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 214 POWERPC_EXCP_INVAL | 215 POWERPC_EXCP_PRIV_REG, GETPC()); 216 } 217 } 218 } 219