1 /* 2 * QEMU PPC (monitor definitions) 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "monitor/monitor.h" 28 #include "qemu/ctype.h" 29 #include "monitor/hmp-target.h" 30 #include "monitor/hmp.h" 31 #include "qapi/qapi-commands-machine-target.h" 32 #include "cpu-models.h" 33 #include "cpu-qom.h" 34 35 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md, 36 int val) 37 { 38 CPUArchState *env = mon_get_cpu_env(mon); 39 unsigned int u; 40 int i; 41 42 u = 0; 43 for (i = 0; i < 8; i++) { 44 u |= env->crf[i] << (32 - (4 * (i + 1))); 45 } 46 47 return u; 48 } 49 50 static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md, 51 int val) 52 { 53 CPUArchState *env = mon_get_cpu_env(mon); 54 return cpu_read_xer(env); 55 } 56 57 static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md, 58 int val) 59 { 60 CPUArchState *env = mon_get_cpu_env(mon); 61 if (!env->tb_env) { 62 return 0; 63 } 64 return cpu_ppc_load_decr(env); 65 } 66 67 static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md, 68 int val) 69 { 70 CPUArchState *env = mon_get_cpu_env(mon); 71 if (!env->tb_env) { 72 return 0; 73 } 74 return cpu_ppc_load_tbu(env); 75 } 76 77 static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md, 78 int val) 79 { 80 CPUArchState *env = mon_get_cpu_env(mon); 81 if (!env->tb_env) { 82 return 0; 83 } 84 return cpu_ppc_load_tbl(env); 85 } 86 87 void hmp_info_tlb(Monitor *mon, const QDict *qdict) 88 { 89 CPUArchState *env1 = mon_get_cpu_env(mon); 90 91 if (!env1) { 92 monitor_printf(mon, "No CPU available\n"); 93 return; 94 } 95 dump_mmu(env1); 96 } 97 98 const MonitorDef monitor_defs[] = { 99 { "fpscr", offsetof(CPUPPCState, fpscr) }, 100 /* Next instruction pointer */ 101 { "nip|pc", offsetof(CPUPPCState, nip) }, 102 { "lr", offsetof(CPUPPCState, lr) }, 103 { "ctr", offsetof(CPUPPCState, ctr) }, 104 { "decr", 0, &monitor_get_decr, }, 105 { "ccr|cr", 0, &monitor_get_ccr, }, 106 /* Machine state register */ 107 { "xer", 0, &monitor_get_xer }, 108 { "msr", offsetof(CPUPPCState, msr) }, 109 { "tbu", 0, &monitor_get_tbu, }, 110 { "tbl", 0, &monitor_get_tbl, }, 111 { NULL }, 112 }; 113 114 const MonitorDef *target_monitor_defs(void) 115 { 116 return monitor_defs; 117 } 118 119 static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum) 120 { 121 int regnum; 122 char *endptr = NULL; 123 124 if (!*numstr) { 125 return false; 126 } 127 128 regnum = strtoul(numstr, &endptr, 10); 129 if (*endptr || (regnum >= maxnum)) { 130 return false; 131 } 132 *pregnum = regnum; 133 134 return true; 135 } 136 137 int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) 138 { 139 int i, regnum; 140 PowerPCCPU *cpu = POWERPC_CPU(cs); 141 CPUPPCState *env = &cpu->env; 142 143 /* General purpose registers */ 144 if ((qemu_tolower(name[0]) == 'r') && 145 ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) { 146 *pval = env->gpr[regnum]; 147 return 0; 148 } 149 150 /* Floating point registers */ 151 if ((qemu_tolower(name[0]) == 'f') && 152 ppc_cpu_get_reg_num(name + 1, 32, ®num)) { 153 *pval = *cpu_fpr_ptr(env, regnum); 154 return 0; 155 } 156 157 /* Special purpose registers */ 158 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { 159 ppc_spr_t *spr = &env->spr_cb[i]; 160 161 if (spr->name && (strcasecmp(name, spr->name) == 0)) { 162 *pval = env->spr[i]; 163 return 0; 164 } 165 } 166 167 /* Segment registers */ 168 #if !defined(CONFIG_USER_ONLY) 169 if ((strncasecmp(name, "sr", 2) == 0) && 170 ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) { 171 *pval = env->sr[regnum]; 172 return 0; 173 } 174 #endif 175 176 return -EINVAL; 177 } 178 179 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 180 { 181 ObjectClass *oc = data; 182 CpuDefinitionInfoList **first = user_data; 183 const char *typename; 184 CpuDefinitionInfo *info; 185 186 typename = object_class_get_name(oc); 187 info = g_malloc0(sizeof(*info)); 188 info->name = g_strndup(typename, 189 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 190 191 QAPI_LIST_PREPEND(*first, info); 192 } 193 194 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 195 { 196 CpuDefinitionInfoList *cpu_list = NULL; 197 GSList *list; 198 int i; 199 200 list = object_class_get_list(TYPE_POWERPC_CPU, false); 201 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 202 g_slist_free(list); 203 204 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 205 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 206 ObjectClass *oc; 207 CpuDefinitionInfo *info; 208 209 oc = ppc_cpu_class_by_name(alias->model); 210 if (oc == NULL) { 211 continue; 212 } 213 214 info = g_malloc0(sizeof(*info)); 215 info->name = g_strdup(alias->alias); 216 info->q_typename = g_strdup(object_class_get_name(oc)); 217 218 QAPI_LIST_PREPEND(cpu_list, info); 219 } 220 221 return cpu_list; 222 } 223