xref: /openbmc/qemu/target/ppc/mmu-radix64.h (revision 795c40b8)
1 #ifndef MMU_RADIX64_H
2 #define MMU_RADIX64_H
3 
4 #ifndef CONFIG_USER_ONLY
5 
6 /* Radix Quadrants */
7 #define R_EADDR_MASK            0x3FFFFFFFFFFFFFFF
8 #define R_EADDR_QUADRANT        0xC000000000000000
9 #define R_EADDR_QUADRANT0       0x0000000000000000
10 #define R_EADDR_QUADRANT1       0x4000000000000000
11 #define R_EADDR_QUADRANT2       0x8000000000000000
12 #define R_EADDR_QUADRANT3       0xC000000000000000
13 
14 /* Radix Partition Table Entry Fields */
15 #define PATBE1_R_PRTB           0x0FFFFFFFFFFFF000
16 #define PATBE1_R_PRTS           0x000000000000001F
17 
18 /* Radix Process Table Entry Fields */
19 #define PRTBE_R_GET_RTS(rts) \
20     ((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31)
21 #define PRTBE_R_RPDB            0x0FFFFFFFFFFFFF00
22 #define PRTBE_R_RPDS            0x000000000000001F
23 
24 /* Radix Page Directory/Table Entry Fields */
25 #define R_PTE_VALID             0x8000000000000000
26 #define R_PTE_LEAF              0x4000000000000000
27 #define R_PTE_SW0               0x2000000000000000
28 #define R_PTE_RPN               0x01FFFFFFFFFFF000
29 #define R_PTE_SW1               0x0000000000000E00
30 #define R_GET_SW(sw)            (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7))
31 #define R_PTE_R                 0x0000000000000100
32 #define R_PTE_C                 0x0000000000000080
33 #define R_PTE_ATT               0x0000000000000030
34 #define R_PTE_ATT_NORMAL        0x0000000000000000
35 #define R_PTE_ATT_SAO           0x0000000000000010
36 #define R_PTE_ATT_NI_IO         0x0000000000000020
37 #define R_PTE_ATT_TOLERANT_IO   0x0000000000000030
38 #define R_PTE_EAA_PRIV          0x0000000000000008
39 #define R_PTE_EAA_R             0x0000000000000004
40 #define R_PTE_EAA_RW            0x0000000000000002
41 #define R_PTE_EAA_X             0x0000000000000001
42 #define R_PDE_NLB               PRTBE_R_RPDB
43 #define R_PDE_NLS               PRTBE_R_RPDS
44 
45 #ifdef TARGET_PPC64
46 
47 int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
48                                  int mmu_idx);
49 
50 static inline int ppc_radix64_get_prot_eaa(uint64_t pte)
51 {
52     return (pte & R_PTE_EAA_R ? PAGE_READ : 0) |
53            (pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) |
54            (pte & R_PTE_EAA_X ? PAGE_EXEC : 0);
55 }
56 
57 static inline int ppc_radix64_get_prot_amr(PowerPCCPU *cpu)
58 {
59     CPUPPCState *env = &cpu->env;
60     int amr = env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR63:62 */
61     int iamr = env->spr[SPR_IAMR] >> 62; /* We only care about key0 IAMR63:62 */
62 
63     return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set */
64            (amr & 0x1 ? 0 : PAGE_READ) |
65            (iamr & 0x1 ? 0 : PAGE_EXEC);
66 }
67 
68 #endif /* TARGET_PPC64 */
69 
70 #endif /* CONFIG_USER_ONLY */
71 
72 #endif /* MMU_RADIX64_H */
73