1 #ifndef MMU_HASH64_H 2 #define MMU_HASH64_H 3 4 #ifndef CONFIG_USER_ONLY 5 6 #ifdef TARGET_PPC64 7 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu); 8 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, 9 target_ulong esid, target_ulong vsid); 10 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); 11 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, 12 int mmu_idx); 13 void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 14 uint64_t pte0, uint64_t pte1); 15 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, 16 target_ulong pte_index, 17 target_ulong pte0, target_ulong pte1); 18 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, 19 uint64_t pte0, uint64_t pte1); 20 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); 21 void ppc_hash64_init(PowerPCCPU *cpu); 22 void ppc_hash64_finalize(PowerPCCPU *cpu); 23 void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, 24 bool (*cb)(void *, uint32_t, uint32_t), 25 void *opaque); 26 #endif 27 28 /* 29 * SLB definitions 30 */ 31 32 /* Bits in the SLB ESID word */ 33 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL 34 #define SLB_ESID_V 0x0000000008000000ULL /* valid */ 35 36 /* Bits in the SLB VSID word */ 37 #define SLB_VSID_SHIFT 12 38 #define SLB_VSID_SHIFT_1T 24 39 #define SLB_VSID_SSIZE_SHIFT 62 40 #define SLB_VSID_B 0xc000000000000000ULL 41 #define SLB_VSID_B_256M 0x0000000000000000ULL 42 #define SLB_VSID_B_1T 0x4000000000000000ULL 43 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL 44 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T) 45 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID) 46 #define SLB_VSID_KS 0x0000000000000800ULL 47 #define SLB_VSID_KP 0x0000000000000400ULL 48 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */ 49 #define SLB_VSID_L 0x0000000000000100ULL 50 #define SLB_VSID_C 0x0000000000000080ULL /* class */ 51 #define SLB_VSID_LP 0x0000000000000030ULL 52 #define SLB_VSID_ATTR 0x0000000000000FFFULL 53 #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) 54 #define SLB_VSID_4K 0x0000000000000000ULL 55 #define SLB_VSID_64K 0x0000000000000110ULL 56 #define SLB_VSID_16M 0x0000000000000100ULL 57 #define SLB_VSID_16G 0x0000000000000120ULL 58 59 /* 60 * Hash page table definitions 61 */ 62 63 #define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL 64 #define SDR_64_HTABSIZE 0x000000000000001FULL 65 66 #define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL 67 #define HPTES_PER_GROUP 8 68 #define HASH_PTE_SIZE_64 16 69 #define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP) 70 71 #define HPTE64_V_SSIZE SLB_VSID_B 72 #define HPTE64_V_SSIZE_256M SLB_VSID_B_256M 73 #define HPTE64_V_SSIZE_1T SLB_VSID_B_1T 74 #define HPTE64_V_SSIZE_SHIFT 62 75 #define HPTE64_V_AVPN_SHIFT 7 76 #define HPTE64_V_AVPN 0x3fffffffffffff80ULL 77 #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT) 78 #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL)) 79 #define HPTE64_V_BOLTED 0x0000000000000010ULL 80 #define HPTE64_V_LARGE 0x0000000000000004ULL 81 #define HPTE64_V_SECONDARY 0x0000000000000002ULL 82 #define HPTE64_V_VALID 0x0000000000000001ULL 83 84 #define HPTE64_R_PP0 0x8000000000000000ULL 85 #define HPTE64_R_TS 0x4000000000000000ULL 86 #define HPTE64_R_KEY_HI 0x3000000000000000ULL 87 #define HPTE64_R_RPN_SHIFT 12 88 #define HPTE64_R_RPN 0x0ffffffffffff000ULL 89 #define HPTE64_R_FLAGS 0x00000000000003ffULL 90 #define HPTE64_R_PP 0x0000000000000003ULL 91 #define HPTE64_R_N 0x0000000000000004ULL 92 #define HPTE64_R_G 0x0000000000000008ULL 93 #define HPTE64_R_M 0x0000000000000010ULL 94 #define HPTE64_R_I 0x0000000000000020ULL 95 #define HPTE64_R_W 0x0000000000000040ULL 96 #define HPTE64_R_WIMG 0x0000000000000078ULL 97 #define HPTE64_R_C 0x0000000000000080ULL 98 #define HPTE64_R_R 0x0000000000000100ULL 99 #define HPTE64_R_KEY_LO 0x0000000000000e00ULL 100 #define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \ 101 (((x) & HPTE64_R_KEY_LO) >> 9)) 102 103 #define HPTE64_V_1TB_SEG 0x4000000000000000ULL 104 #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL 105 106 /* Format changes for ARCH v3 */ 107 #define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL 108 #define HPTE64_R_3_0_SSIZE_SHIFT 58 109 #define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT) 110 111 struct ppc_hash_pte64 { 112 uint64_t pte0, pte1; 113 }; 114 115 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, 116 hwaddr ptex, int n); 117 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, 118 hwaddr ptex, int n); 119 120 static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu, 121 const ppc_hash_pte64_t *hptes, int i) 122 { 123 return ldq_p(&(hptes[i].pte0)); 124 } 125 126 static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu, 127 const ppc_hash_pte64_t *hptes, int i) 128 { 129 return ldq_p(&(hptes[i].pte1)); 130 } 131 132 /* 133 * MMU Options 134 */ 135 136 struct PPCHash64PageSize { 137 uint32_t page_shift; /* Page shift (or 0) */ 138 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */ 139 }; 140 typedef struct PPCHash64PageSize PPCHash64PageSize; 141 142 struct PPCHash64SegmentPageSizes { 143 uint32_t page_shift; /* Base page shift of segment (or 0) */ 144 uint32_t slb_enc; /* SLB encoding for BookS */ 145 PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ]; 146 }; 147 148 struct PPCHash64Options { 149 #define PPC_HASH64_1TSEG 0x00001 150 #define PPC_HASH64_AMR 0x00002 151 #define PPC_HASH64_CI_LARGEPAGE 0x00004 152 unsigned flags; 153 unsigned slb_size; 154 PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; 155 }; 156 157 extern const PPCHash64Options ppc_hash64_opts_basic; 158 extern const PPCHash64Options ppc_hash64_opts_POWER7; 159 160 static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature) 161 { 162 return !!(cpu->hash64_opts->flags & feature); 163 } 164 165 #endif /* CONFIG_USER_ONLY */ 166 167 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) 168 static inline void ppc_hash64_init(PowerPCCPU *cpu) 169 { 170 } 171 static inline void ppc_hash64_finalize(PowerPCCPU *cpu) 172 { 173 } 174 #endif 175 176 #endif /* MMU_HASH64_H */ 177