xref: /openbmc/qemu/target/ppc/misc_helper.c (revision 86e372ad)
1 /*
2  * Miscellaneous PowerPC emulation helpers for QEMU.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "qemu/error-report.h"
26 #include "qemu/main-loop.h"
27 #include "mmu-book3s-v3.h"
28 #include "hw/ppc/ppc.h"
29 
30 #include "helper_regs.h"
31 
32 /*****************************************************************************/
33 /* SPR accesses */
34 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
35 {
36     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
37              env->spr[sprn]);
38 }
39 
40 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
41 {
42     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
43              env->spr[sprn]);
44 }
45 
46 void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
47                                    target_ulong val)
48 {
49     CPUState *cs = env_cpu(env);
50     CPUState *ccs;
51     uint32_t nr_threads = cs->nr_threads;
52 
53     if (nr_threads == 1) {
54         env->spr[sprn] = val;
55         return;
56     }
57 
58     THREAD_SIBLING_FOREACH(cs, ccs) {
59         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
60         cenv->spr[sprn] = val;
61     }
62 }
63 
64 void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn,
65                            target_ulong val)
66 {
67     CPUState *cs = env_cpu(env);
68     CPUState *ccs;
69     uint32_t run = val & 1;
70     uint32_t ts, ts_mask;
71 
72     assert(sprn == SPR_CTRL);
73 
74     env->spr[sprn] &= ~1U;
75     env->spr[sprn] |= run;
76 
77     ts_mask = ~(1U << (8 + env->spr[SPR_TIR]));
78     ts = run << (8 + env->spr[SPR_TIR]);
79 
80     THREAD_SIBLING_FOREACH(cs, ccs) {
81         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
82 
83         cenv->spr[sprn] &= ts_mask;
84         cenv->spr[sprn] |= ts;
85     }
86 }
87 
88 
89 #ifdef TARGET_PPC64
90 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
91                                   const char *caller, uint32_t cause,
92                                   uintptr_t raddr)
93 {
94     qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
95                   bit, caller);
96 
97     env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
98 
99     raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
100 }
101 
102 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
103                                uint32_t sprn, uint32_t cause,
104                                uintptr_t raddr)
105 {
106     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
107 
108     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
109     cause &= FSCR_IC_MASK;
110     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
111 
112     raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
113 }
114 #endif
115 
116 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
117                                  const char *caller, uint32_t cause)
118 {
119 #ifdef TARGET_PPC64
120     if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
121                                      !(env->spr[SPR_HFSCR] & (1UL << bit))) {
122         raise_hv_fu_exception(env, bit, caller, cause, GETPC());
123     }
124 #endif
125 }
126 
127 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
128                                 uint32_t sprn, uint32_t cause)
129 {
130 #ifdef TARGET_PPC64
131     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
132         /* Facility is enabled, continue */
133         return;
134     }
135     raise_fu_exception(env, bit, sprn, cause, GETPC());
136 #endif
137 }
138 
139 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
140                                uint32_t sprn, uint32_t cause)
141 {
142 #ifdef TARGET_PPC64
143     if (env->msr & (1ULL << bit)) {
144         /* Facility is enabled, continue */
145         return;
146     }
147     raise_fu_exception(env, bit, sprn, cause, GETPC());
148 #endif
149 }
150 
151 #if !defined(CONFIG_USER_ONLY)
152 
153 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
154 {
155     if (env->spr[SPR_SDR1] != val) {
156         ppc_store_sdr1(env, val);
157         tlb_flush(env_cpu(env));
158     }
159 }
160 
161 #if defined(TARGET_PPC64)
162 void helper_store_ptcr(CPUPPCState *env, target_ulong val)
163 {
164     if (env->spr[SPR_PTCR] != val) {
165         PowerPCCPU *cpu = env_archcpu(env);
166         target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
167         target_ulong patbsize = val & PTCR_PATS;
168 
169         qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val);
170 
171         assert(!cpu->vhyp);
172         assert(env->mmu_model & POWERPC_MMU_3_00);
173 
174         if (val & ~ptcr_mask) {
175             error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
176                          val & ~ptcr_mask);
177             val &= ptcr_mask;
178         }
179 
180         if (patbsize > 24) {
181             error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
182                          " stored in PTCR", patbsize);
183             return;
184         }
185 
186         env->spr[SPR_PTCR] = val;
187         tlb_flush(env_cpu(env));
188     }
189 }
190 
191 void helper_store_pcr(CPUPPCState *env, target_ulong value)
192 {
193     PowerPCCPU *cpu = env_archcpu(env);
194     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
195 
196     env->spr[SPR_PCR] = value & pcc->pcr_mask;
197 }
198 
199 void helper_store_ciabr(CPUPPCState *env, target_ulong value)
200 {
201     ppc_store_ciabr(env, value);
202 }
203 
204 void helper_store_dawr0(CPUPPCState *env, target_ulong value)
205 {
206     ppc_store_dawr0(env, value);
207 }
208 
209 void helper_store_dawrx0(CPUPPCState *env, target_ulong value)
210 {
211     ppc_store_dawrx0(env, value);
212 }
213 
214 /*
215  * DPDES register is shared. Each bit reflects the state of the
216  * doorbell interrupt of a thread of the same core.
217  */
218 target_ulong helper_load_dpdes(CPUPPCState *env)
219 {
220     CPUState *cs = env_cpu(env);
221     CPUState *ccs;
222     uint32_t nr_threads = cs->nr_threads;
223     target_ulong dpdes = 0;
224 
225     helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
226 
227     if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
228         nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
229     }
230 
231     if (nr_threads == 1) {
232         if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
233             dpdes = 1;
234         }
235         return dpdes;
236     }
237 
238     bql_lock();
239     THREAD_SIBLING_FOREACH(cs, ccs) {
240         PowerPCCPU *ccpu = POWERPC_CPU(ccs);
241         CPUPPCState *cenv = &ccpu->env;
242         uint32_t thread_id = ppc_cpu_tir(ccpu);
243 
244         if (cenv->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
245             dpdes |= (0x1 << thread_id);
246         }
247     }
248     bql_unlock();
249 
250     return dpdes;
251 }
252 
253 void helper_store_dpdes(CPUPPCState *env, target_ulong val)
254 {
255     PowerPCCPU *cpu = env_archcpu(env);
256     CPUState *cs = env_cpu(env);
257     CPUState *ccs;
258     uint32_t nr_threads = cs->nr_threads;
259 
260     helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
261 
262     if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
263         nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
264     }
265 
266     if (val & ~(nr_threads - 1)) {
267         qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
268                       TARGET_FMT_lx"\n", val);
269         val &= (nr_threads - 1); /* Ignore the invalid bits */
270     }
271 
272     if (nr_threads == 1) {
273         ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
274         return;
275     }
276 
277     /* Does iothread need to be locked for walking CPU list? */
278     bql_lock();
279     THREAD_SIBLING_FOREACH(cs, ccs) {
280         PowerPCCPU *ccpu = POWERPC_CPU(ccs);
281         uint32_t thread_id = ppc_cpu_tir(ccpu);
282 
283         ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id));
284     }
285     bql_unlock();
286 }
287 #endif /* defined(TARGET_PPC64) */
288 
289 void helper_store_pidr(CPUPPCState *env, target_ulong val)
290 {
291     env->spr[SPR_BOOKS_PID] = (uint32_t)val;
292     tlb_flush(env_cpu(env));
293 }
294 
295 void helper_store_lpidr(CPUPPCState *env, target_ulong val)
296 {
297     env->spr[SPR_LPIDR] = (uint32_t)val;
298 
299     /*
300      * We need to flush the TLB on LPID changes as we only tag HV vs
301      * guest in TCG TLB. Also the quadrants means the HV will
302      * potentially access and cache entries for the current LPID as
303      * well.
304      */
305     tlb_flush(env_cpu(env));
306 }
307 
308 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
309 {
310     /* Bits 26 & 27 affect single-stepping. */
311     hreg_compute_hflags(env);
312     /* Bits 28 & 29 affect reset or shutdown. */
313     store_40x_dbcr0(env, val);
314 }
315 
316 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
317 {
318     store_40x_sler(env, val);
319 }
320 #endif
321 
322 /*****************************************************************************/
323 /* Special registers manipulation */
324 
325 /*
326  * This code is lifted from MacOnLinux. It is called whenever THRM1,2
327  * or 3 is read an fixes up the values in such a way that will make
328  * MacOS not hang. These registers exist on some 75x and 74xx
329  * processors.
330  */
331 void helper_fixup_thrm(CPUPPCState *env)
332 {
333     target_ulong v, t;
334     int i;
335 
336 #define THRM1_TIN       (1 << 31)
337 #define THRM1_TIV       (1 << 30)
338 #define THRM1_THRES(x)  (((x) & 0x7f) << 23)
339 #define THRM1_TID       (1 << 2)
340 #define THRM1_TIE       (1 << 1)
341 #define THRM1_V         (1 << 0)
342 #define THRM3_E         (1 << 0)
343 
344     if (!(env->spr[SPR_THRM3] & THRM3_E)) {
345         return;
346     }
347 
348     /* Note: Thermal interrupts are unimplemented */
349     for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
350         v = env->spr[i];
351         if (!(v & THRM1_V)) {
352             continue;
353         }
354         v |= THRM1_TIV;
355         v &= ~THRM1_TIN;
356         t = v & THRM1_THRES(127);
357         if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
358             v |= THRM1_TIN;
359         }
360         if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
361             v |= THRM1_TIN;
362         }
363         env->spr[i] = v;
364     }
365 }
366