1 /* 2 * Miscellaneous PowerPC emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/exec-all.h" 22 #include "exec/helper-proto.h" 23 #include "qemu/error-report.h" 24 25 #include "helper_regs.h" 26 27 /*****************************************************************************/ 28 /* SPR accesses */ 29 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) 30 { 31 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, 32 env->spr[sprn]); 33 } 34 35 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) 36 { 37 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, 38 env->spr[sprn]); 39 } 40 41 #ifdef TARGET_PPC64 42 static void raise_fu_exception(CPUPPCState *env, uint32_t bit, 43 uint32_t sprn, uint32_t cause, 44 uintptr_t raddr) 45 { 46 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit); 47 48 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 49 cause &= FSCR_IC_MASK; 50 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; 51 52 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); 53 } 54 #endif 55 56 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, 57 uint32_t sprn, uint32_t cause) 58 { 59 #ifdef TARGET_PPC64 60 if (env->spr[SPR_FSCR] & (1ULL << bit)) { 61 /* Facility is enabled, continue */ 62 return; 63 } 64 raise_fu_exception(env, bit, sprn, cause, GETPC()); 65 #endif 66 } 67 68 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, 69 uint32_t sprn, uint32_t cause) 70 { 71 #ifdef TARGET_PPC64 72 if (env->msr & (1ULL << bit)) { 73 /* Facility is enabled, continue */ 74 return; 75 } 76 raise_fu_exception(env, bit, sprn, cause, GETPC()); 77 #endif 78 } 79 80 #if !defined(CONFIG_USER_ONLY) 81 82 void helper_store_sdr1(CPUPPCState *env, target_ulong val) 83 { 84 PowerPCCPU *cpu = ppc_env_get_cpu(env); 85 86 if (env->spr[SPR_SDR1] != val) { 87 ppc_store_sdr1(env, val); 88 tlb_flush(CPU(cpu)); 89 } 90 } 91 92 #if defined(TARGET_PPC64) 93 void helper_store_ptcr(CPUPPCState *env, target_ulong val) 94 { 95 PowerPCCPU *cpu = ppc_env_get_cpu(env); 96 97 if (env->spr[SPR_PTCR] != val) { 98 ppc_store_ptcr(env, val); 99 tlb_flush(CPU(cpu)); 100 } 101 } 102 103 void helper_store_pcr(CPUPPCState *env, target_ulong value) 104 { 105 PowerPCCPU *cpu = ppc_env_get_cpu(env); 106 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 107 108 env->spr[SPR_PCR] = value & pcc->pcr_mask; 109 } 110 #endif /* defined(TARGET_PPC64) */ 111 112 void helper_store_pidr(CPUPPCState *env, target_ulong val) 113 { 114 PowerPCCPU *cpu = ppc_env_get_cpu(env); 115 116 env->spr[SPR_BOOKS_PID] = val; 117 tlb_flush(CPU(cpu)); 118 } 119 120 void helper_store_lpidr(CPUPPCState *env, target_ulong val) 121 { 122 PowerPCCPU *cpu = ppc_env_get_cpu(env); 123 124 env->spr[SPR_LPIDR] = val; 125 126 /* 127 * We need to flush the TLB on LPID changes as we only tag HV vs 128 * guest in TCG TLB. Also the quadrants means the HV will 129 * potentially access and cache entries for the current LPID as 130 * well. 131 */ 132 tlb_flush(CPU(cpu)); 133 } 134 135 void helper_store_hid0_601(CPUPPCState *env, target_ulong val) 136 { 137 target_ulong hid0; 138 139 hid0 = env->spr[SPR_HID0]; 140 if ((val ^ hid0) & 0x00000008) { 141 /* Change current endianness */ 142 env->hflags &= ~(1 << MSR_LE); 143 env->hflags_nmsr &= ~(1 << MSR_LE); 144 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); 145 env->hflags |= env->hflags_nmsr; 146 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, 147 val & 0x8 ? 'l' : 'b', env->hflags); 148 } 149 env->spr[SPR_HID0] = (uint32_t)val; 150 } 151 152 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) 153 { 154 PowerPCCPU *cpu = ppc_env_get_cpu(env); 155 156 if (likely(env->pb[num] != value)) { 157 env->pb[num] = value; 158 /* Should be optimized */ 159 tlb_flush(CPU(cpu)); 160 } 161 } 162 163 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) 164 { 165 store_40x_dbcr0(env, val); 166 } 167 168 void helper_store_40x_sler(CPUPPCState *env, target_ulong val) 169 { 170 store_40x_sler(env, val); 171 } 172 #endif 173 /*****************************************************************************/ 174 /* PowerPC 601 specific instructions (POWER bridge) */ 175 176 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg) 177 { 178 switch (arg) { 179 case 0x0CUL: 180 /* Instruction cache line size */ 181 return env->icache_line_size; 182 break; 183 case 0x0DUL: 184 /* Data cache line size */ 185 return env->dcache_line_size; 186 break; 187 case 0x0EUL: 188 /* Minimum cache line size */ 189 return (env->icache_line_size < env->dcache_line_size) ? 190 env->icache_line_size : env->dcache_line_size; 191 break; 192 case 0x0FUL: 193 /* Maximum cache line size */ 194 return (env->icache_line_size > env->dcache_line_size) ? 195 env->icache_line_size : env->dcache_line_size; 196 break; 197 default: 198 /* Undefined */ 199 return 0; 200 break; 201 } 202 } 203 204 /*****************************************************************************/ 205 /* Special registers manipulation */ 206 207 /* GDBstub can read and write MSR... */ 208 void ppc_store_msr(CPUPPCState *env, target_ulong value) 209 { 210 hreg_store_msr(env, value, 0); 211 } 212 213 /* This code is lifted from MacOnLinux. It is called whenever 214 * THRM1,2 or 3 is read an fixes up the values in such a way 215 * that will make MacOS not hang. These registers exist on some 216 * 75x and 74xx processors. 217 */ 218 void helper_fixup_thrm(CPUPPCState *env) 219 { 220 target_ulong v, t; 221 int i; 222 223 #define THRM1_TIN (1 << 31) 224 #define THRM1_TIV (1 << 30) 225 #define THRM1_THRES(x) (((x) & 0x7f) << 23) 226 #define THRM1_TID (1 << 2) 227 #define THRM1_TIE (1 << 1) 228 #define THRM1_V (1 << 0) 229 #define THRM3_E (1 << 0) 230 231 if (!(env->spr[SPR_THRM3] & THRM3_E)) { 232 return; 233 } 234 235 /* Note: Thermal interrupts are unimplemented */ 236 for (i = SPR_THRM1; i <= SPR_THRM2; i++) { 237 v = env->spr[i]; 238 if (!(v & THRM1_V)) { 239 continue; 240 } 241 v |= THRM1_TIV; 242 v &= ~THRM1_TIN; 243 t = v & THRM1_THRES(127); 244 if ((v & THRM1_TID) && t < THRM1_THRES(24)) { 245 v |= THRM1_TIN; 246 } 247 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) { 248 v |= THRM1_TIN; 249 } 250 env->spr[i] = v; 251 } 252 } 253