1 /* 2 * Miscellaneous PowerPC emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "qemu/error-report.h" 25 #include "qemu/main-loop.h" 26 #include "mmu-book3s-v3.h" 27 28 #include "helper_regs.h" 29 30 /*****************************************************************************/ 31 /* SPR accesses */ 32 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) 33 { 34 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, 35 env->spr[sprn]); 36 } 37 38 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) 39 { 40 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, 41 env->spr[sprn]); 42 } 43 44 #ifdef TARGET_PPC64 45 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, 46 const char *caller, uint32_t cause, 47 uintptr_t raddr) 48 { 49 qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n", 50 bit, caller); 51 52 env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 53 54 raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); 55 } 56 57 static void raise_fu_exception(CPUPPCState *env, uint32_t bit, 58 uint32_t sprn, uint32_t cause, 59 uintptr_t raddr) 60 { 61 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit); 62 63 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 64 cause &= FSCR_IC_MASK; 65 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; 66 67 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); 68 } 69 #endif 70 71 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, 72 const char *caller, uint32_t cause) 73 { 74 #ifdef TARGET_PPC64 75 if ((env->msr_mask & MSR_HVB) && !msr_hv && 76 !(env->spr[SPR_HFSCR] & (1UL << bit))) { 77 raise_hv_fu_exception(env, bit, caller, cause, GETPC()); 78 } 79 #endif 80 } 81 82 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, 83 uint32_t sprn, uint32_t cause) 84 { 85 #ifdef TARGET_PPC64 86 if (env->spr[SPR_FSCR] & (1ULL << bit)) { 87 /* Facility is enabled, continue */ 88 return; 89 } 90 raise_fu_exception(env, bit, sprn, cause, GETPC()); 91 #endif 92 } 93 94 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, 95 uint32_t sprn, uint32_t cause) 96 { 97 #ifdef TARGET_PPC64 98 if (env->msr & (1ULL << bit)) { 99 /* Facility is enabled, continue */ 100 return; 101 } 102 raise_fu_exception(env, bit, sprn, cause, GETPC()); 103 #endif 104 } 105 106 #if !defined(CONFIG_USER_ONLY) 107 108 void helper_store_sdr1(CPUPPCState *env, target_ulong val) 109 { 110 if (env->spr[SPR_SDR1] != val) { 111 ppc_store_sdr1(env, val); 112 tlb_flush(env_cpu(env)); 113 } 114 } 115 116 #if defined(TARGET_PPC64) 117 void helper_store_ptcr(CPUPPCState *env, target_ulong val) 118 { 119 if (env->spr[SPR_PTCR] != val) { 120 PowerPCCPU *cpu = env_archcpu(env); 121 target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS; 122 target_ulong patbsize = val & PTCR_PATS; 123 124 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val); 125 126 assert(!cpu->vhyp); 127 assert(env->mmu_model & POWERPC_MMU_3_00); 128 129 if (val & ~ptcr_mask) { 130 error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR", 131 val & ~ptcr_mask); 132 val &= ptcr_mask; 133 } 134 135 if (patbsize > 24) { 136 error_report("Invalid Partition Table size 0x" TARGET_FMT_lx 137 " stored in PTCR", patbsize); 138 return; 139 } 140 141 env->spr[SPR_PTCR] = val; 142 tlb_flush(env_cpu(env)); 143 } 144 } 145 146 void helper_store_pcr(CPUPPCState *env, target_ulong value) 147 { 148 PowerPCCPU *cpu = env_archcpu(env); 149 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 150 151 env->spr[SPR_PCR] = value & pcc->pcr_mask; 152 } 153 154 /* 155 * DPDES register is shared. Each bit reflects the state of the 156 * doorbell interrupt of a thread of the same core. 157 */ 158 target_ulong helper_load_dpdes(CPUPPCState *env) 159 { 160 target_ulong dpdes = 0; 161 162 helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); 163 164 /* TODO: TCG supports only one thread */ 165 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { 166 dpdes = 1; 167 } 168 169 return dpdes; 170 } 171 172 void helper_store_dpdes(CPUPPCState *env, target_ulong val) 173 { 174 PowerPCCPU *cpu = env_archcpu(env); 175 CPUState *cs = CPU(cpu); 176 177 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); 178 179 /* TODO: TCG supports only one thread */ 180 if (val & ~0x1) { 181 qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " 182 TARGET_FMT_lx"\n", val); 183 return; 184 } 185 186 if (val & 0x1) { 187 env->pending_interrupts |= 1 << PPC_INTERRUPT_DOORBELL; 188 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 189 } else { 190 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); 191 } 192 } 193 #endif /* defined(TARGET_PPC64) */ 194 195 void helper_store_pidr(CPUPPCState *env, target_ulong val) 196 { 197 env->spr[SPR_BOOKS_PID] = val; 198 tlb_flush(env_cpu(env)); 199 } 200 201 void helper_store_lpidr(CPUPPCState *env, target_ulong val) 202 { 203 env->spr[SPR_LPIDR] = val; 204 205 /* 206 * We need to flush the TLB on LPID changes as we only tag HV vs 207 * guest in TCG TLB. Also the quadrants means the HV will 208 * potentially access and cache entries for the current LPID as 209 * well. 210 */ 211 tlb_flush(env_cpu(env)); 212 } 213 214 void helper_store_hid0_601(CPUPPCState *env, target_ulong val) 215 { 216 target_ulong hid0; 217 218 hid0 = env->spr[SPR_HID0]; 219 env->spr[SPR_HID0] = (uint32_t)val; 220 221 if ((val ^ hid0) & 0x00000008) { 222 /* Change current endianness */ 223 hreg_compute_hflags(env); 224 qemu_log("%s: set endianness to %c => %08x\n", __func__, 225 val & 0x8 ? 'l' : 'b', env->hflags); 226 } 227 } 228 229 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) 230 { 231 if (likely(env->pb[num] != value)) { 232 env->pb[num] = value; 233 /* Should be optimized */ 234 tlb_flush(env_cpu(env)); 235 } 236 } 237 238 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) 239 { 240 /* Bits 26 & 27 affect single-stepping. */ 241 hreg_compute_hflags(env); 242 /* Bits 28 & 29 affect reset or shutdown. */ 243 store_40x_dbcr0(env, val); 244 } 245 246 void helper_store_40x_sler(CPUPPCState *env, target_ulong val) 247 { 248 store_40x_sler(env, val); 249 } 250 #endif 251 /*****************************************************************************/ 252 /* PowerPC 601 specific instructions (POWER bridge) */ 253 254 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg) 255 { 256 switch (arg) { 257 case 0x0CUL: 258 /* Instruction cache line size */ 259 return env->icache_line_size; 260 case 0x0DUL: 261 /* Data cache line size */ 262 return env->dcache_line_size; 263 case 0x0EUL: 264 /* Minimum cache line size */ 265 return (env->icache_line_size < env->dcache_line_size) ? 266 env->icache_line_size : env->dcache_line_size; 267 case 0x0FUL: 268 /* Maximum cache line size */ 269 return (env->icache_line_size > env->dcache_line_size) ? 270 env->icache_line_size : env->dcache_line_size; 271 default: 272 /* Undefined */ 273 return 0; 274 } 275 } 276 277 /*****************************************************************************/ 278 /* Special registers manipulation */ 279 280 /* 281 * This code is lifted from MacOnLinux. It is called whenever THRM1,2 282 * or 3 is read an fixes up the values in such a way that will make 283 * MacOS not hang. These registers exist on some 75x and 74xx 284 * processors. 285 */ 286 void helper_fixup_thrm(CPUPPCState *env) 287 { 288 target_ulong v, t; 289 int i; 290 291 #define THRM1_TIN (1 << 31) 292 #define THRM1_TIV (1 << 30) 293 #define THRM1_THRES(x) (((x) & 0x7f) << 23) 294 #define THRM1_TID (1 << 2) 295 #define THRM1_TIE (1 << 1) 296 #define THRM1_V (1 << 0) 297 #define THRM3_E (1 << 0) 298 299 if (!(env->spr[SPR_THRM3] & THRM3_E)) { 300 return; 301 } 302 303 /* Note: Thermal interrupts are unimplemented */ 304 for (i = SPR_THRM1; i <= SPR_THRM2; i++) { 305 v = env->spr[i]; 306 if (!(v & THRM1_V)) { 307 continue; 308 } 309 v |= THRM1_TIV; 310 v &= ~THRM1_TIN; 311 t = v & THRM1_THRES(127); 312 if ((v & THRM1_TID) && t < THRM1_THRES(24)) { 313 v |= THRM1_TIN; 314 } 315 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) { 316 v |= THRM1_TIN; 317 } 318 env->spr[i] = v; 319 } 320 } 321