1 /* 2 * Miscellaneous PowerPC emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "qemu/error-report.h" 26 #include "qemu/main-loop.h" 27 #include "mmu-book3s-v3.h" 28 #include "hw/ppc/ppc.h" 29 30 #include "helper_regs.h" 31 32 /*****************************************************************************/ 33 /* SPR accesses */ 34 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) 35 { 36 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, 37 env->spr[sprn]); 38 } 39 40 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) 41 { 42 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, 43 env->spr[sprn]); 44 } 45 46 void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn, 47 target_ulong val) 48 { 49 CPUState *cs = env_cpu(env); 50 CPUState *ccs; 51 uint32_t nr_threads = cs->nr_threads; 52 uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1); 53 54 assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]); 55 56 if (nr_threads == 1) { 57 env->spr[sprn] = val; 58 return; 59 } 60 61 THREAD_SIBLING_FOREACH(cs, ccs) { 62 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; 63 cenv->spr[sprn] = val; 64 } 65 } 66 67 void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn, 68 target_ulong val) 69 { 70 CPUState *cs = env_cpu(env); 71 CPUState *ccs; 72 uint32_t run = val & 1; 73 uint32_t ts, ts_mask; 74 75 assert(sprn == SPR_CTRL); 76 77 env->spr[sprn] &= ~1U; 78 env->spr[sprn] |= run; 79 80 ts_mask = ~(1U << (8 + env->spr[SPR_TIR])); 81 ts = run << (8 + env->spr[SPR_TIR]); 82 83 THREAD_SIBLING_FOREACH(cs, ccs) { 84 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; 85 86 cenv->spr[sprn] &= ts_mask; 87 cenv->spr[sprn] |= ts; 88 } 89 } 90 91 92 #ifdef TARGET_PPC64 93 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit, 94 const char *caller, uint32_t cause, 95 uintptr_t raddr) 96 { 97 qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n", 98 bit, caller); 99 100 env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 101 102 raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); 103 } 104 105 static void raise_fu_exception(CPUPPCState *env, uint32_t bit, 106 uint32_t sprn, uint32_t cause, 107 uintptr_t raddr) 108 { 109 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit); 110 111 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); 112 cause &= FSCR_IC_MASK; 113 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; 114 115 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); 116 } 117 #endif 118 119 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, 120 const char *caller, uint32_t cause) 121 { 122 #ifdef TARGET_PPC64 123 if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) && 124 !(env->spr[SPR_HFSCR] & (1UL << bit))) { 125 raise_hv_fu_exception(env, bit, caller, cause, GETPC()); 126 } 127 #endif 128 } 129 130 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, 131 uint32_t sprn, uint32_t cause) 132 { 133 #ifdef TARGET_PPC64 134 if (env->spr[SPR_FSCR] & (1ULL << bit)) { 135 /* Facility is enabled, continue */ 136 return; 137 } 138 raise_fu_exception(env, bit, sprn, cause, GETPC()); 139 #endif 140 } 141 142 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, 143 uint32_t sprn, uint32_t cause) 144 { 145 #ifdef TARGET_PPC64 146 if (env->msr & (1ULL << bit)) { 147 /* Facility is enabled, continue */ 148 return; 149 } 150 raise_fu_exception(env, bit, sprn, cause, GETPC()); 151 #endif 152 } 153 154 #if !defined(CONFIG_USER_ONLY) 155 156 void helper_store_sdr1(CPUPPCState *env, target_ulong val) 157 { 158 if (env->spr[SPR_SDR1] != val) { 159 ppc_store_sdr1(env, val); 160 tlb_flush(env_cpu(env)); 161 } 162 } 163 164 #if defined(TARGET_PPC64) 165 void helper_store_ptcr(CPUPPCState *env, target_ulong val) 166 { 167 if (env->spr[SPR_PTCR] != val) { 168 PowerPCCPU *cpu = env_archcpu(env); 169 target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS; 170 target_ulong patbsize = val & PTCR_PATS; 171 172 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val); 173 174 assert(!cpu->vhyp); 175 assert(env->mmu_model & POWERPC_MMU_3_00); 176 177 if (val & ~ptcr_mask) { 178 error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR", 179 val & ~ptcr_mask); 180 val &= ptcr_mask; 181 } 182 183 if (patbsize > 24) { 184 error_report("Invalid Partition Table size 0x" TARGET_FMT_lx 185 " stored in PTCR", patbsize); 186 return; 187 } 188 189 env->spr[SPR_PTCR] = val; 190 tlb_flush(env_cpu(env)); 191 } 192 } 193 194 void helper_store_pcr(CPUPPCState *env, target_ulong value) 195 { 196 PowerPCCPU *cpu = env_archcpu(env); 197 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 198 199 env->spr[SPR_PCR] = value & pcc->pcr_mask; 200 } 201 202 void helper_store_ciabr(CPUPPCState *env, target_ulong value) 203 { 204 ppc_store_ciabr(env, value); 205 } 206 207 void helper_store_dawr0(CPUPPCState *env, target_ulong value) 208 { 209 ppc_store_dawr0(env, value); 210 } 211 212 void helper_store_dawrx0(CPUPPCState *env, target_ulong value) 213 { 214 ppc_store_dawrx0(env, value); 215 } 216 217 /* 218 * DPDES register is shared. Each bit reflects the state of the 219 * doorbell interrupt of a thread of the same core. 220 */ 221 target_ulong helper_load_dpdes(CPUPPCState *env) 222 { 223 CPUState *cs = env_cpu(env); 224 CPUState *ccs; 225 uint32_t nr_threads = cs->nr_threads; 226 target_ulong dpdes = 0; 227 228 helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP); 229 230 if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { 231 nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ 232 } 233 234 if (nr_threads == 1) { 235 if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { 236 dpdes = 1; 237 } 238 return dpdes; 239 } 240 241 bql_lock(); 242 THREAD_SIBLING_FOREACH(cs, ccs) { 243 PowerPCCPU *ccpu = POWERPC_CPU(ccs); 244 CPUPPCState *cenv = &ccpu->env; 245 uint32_t thread_id = ppc_cpu_tir(ccpu); 246 247 if (cenv->pending_interrupts & PPC_INTERRUPT_DOORBELL) { 248 dpdes |= (0x1 << thread_id); 249 } 250 } 251 bql_unlock(); 252 253 return dpdes; 254 } 255 256 void helper_store_dpdes(CPUPPCState *env, target_ulong val) 257 { 258 PowerPCCPU *cpu = env_archcpu(env); 259 CPUState *cs = env_cpu(env); 260 CPUState *ccs; 261 uint32_t nr_threads = cs->nr_threads; 262 263 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP); 264 265 if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { 266 nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */ 267 } 268 269 if (val & ~(nr_threads - 1)) { 270 qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " 271 TARGET_FMT_lx"\n", val); 272 val &= (nr_threads - 1); /* Ignore the invalid bits */ 273 } 274 275 if (nr_threads == 1) { 276 ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); 277 return; 278 } 279 280 /* Does iothread need to be locked for walking CPU list? */ 281 bql_lock(); 282 THREAD_SIBLING_FOREACH(cs, ccs) { 283 PowerPCCPU *ccpu = POWERPC_CPU(ccs); 284 uint32_t thread_id = ppc_cpu_tir(ccpu); 285 286 ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id)); 287 } 288 bql_unlock(); 289 } 290 #endif /* defined(TARGET_PPC64) */ 291 292 void helper_store_pidr(CPUPPCState *env, target_ulong val) 293 { 294 env->spr[SPR_BOOKS_PID] = (uint32_t)val; 295 tlb_flush(env_cpu(env)); 296 } 297 298 void helper_store_lpidr(CPUPPCState *env, target_ulong val) 299 { 300 env->spr[SPR_LPIDR] = (uint32_t)val; 301 302 /* 303 * We need to flush the TLB on LPID changes as we only tag HV vs 304 * guest in TCG TLB. Also the quadrants means the HV will 305 * potentially access and cache entries for the current LPID as 306 * well. 307 */ 308 tlb_flush(env_cpu(env)); 309 } 310 311 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) 312 { 313 /* Bits 26 & 27 affect single-stepping. */ 314 hreg_compute_hflags(env); 315 /* Bits 28 & 29 affect reset or shutdown. */ 316 store_40x_dbcr0(env, val); 317 } 318 319 void helper_store_40x_sler(CPUPPCState *env, target_ulong val) 320 { 321 store_40x_sler(env, val); 322 } 323 #endif 324 325 /*****************************************************************************/ 326 /* Special registers manipulation */ 327 328 /* 329 * This code is lifted from MacOnLinux. It is called whenever THRM1,2 330 * or 3 is read an fixes up the values in such a way that will make 331 * MacOS not hang. These registers exist on some 75x and 74xx 332 * processors. 333 */ 334 void helper_fixup_thrm(CPUPPCState *env) 335 { 336 target_ulong v, t; 337 int i; 338 339 #define THRM1_TIN (1 << 31) 340 #define THRM1_TIV (1 << 30) 341 #define THRM1_THRES(x) (((x) & 0x7f) << 23) 342 #define THRM1_TID (1 << 2) 343 #define THRM1_TIE (1 << 1) 344 #define THRM1_V (1 << 0) 345 #define THRM3_E (1 << 0) 346 347 if (!(env->spr[SPR_THRM3] & THRM3_E)) { 348 return; 349 } 350 351 /* Note: Thermal interrupts are unimplemented */ 352 for (i = SPR_THRM1; i <= SPR_THRM2; i++) { 353 v = env->spr[i]; 354 if (!(v & THRM1_V)) { 355 continue; 356 } 357 v |= THRM1_TIV; 358 v &= ~THRM1_TIN; 359 t = v & THRM1_THRES(127); 360 if ((v & THRM1_TID) && t < THRM1_THRES(24)) { 361 v |= THRM1_TIN; 362 } 363 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) { 364 v |= THRM1_TIN; 365 } 366 env->spr[i] = v; 367 } 368 } 369