1 /* 2 * PowerPC memory access emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/exec-all.h" 22 #include "qemu/host-utils.h" 23 #include "exec/helper-proto.h" 24 #include "helper_regs.h" 25 #include "exec/cpu_ldst.h" 26 #include "tcg.h" 27 #include "internal.h" 28 #include "qemu/atomic128.h" 29 30 /* #define DEBUG_OP */ 31 32 static inline bool needs_byteswap(const CPUPPCState *env) 33 { 34 #if defined(TARGET_WORDS_BIGENDIAN) 35 return msr_le; 36 #else 37 return !msr_le; 38 #endif 39 } 40 41 /*****************************************************************************/ 42 /* Memory load and stores */ 43 44 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, 45 target_long arg) 46 { 47 #if defined(TARGET_PPC64) 48 if (!msr_is_64bit(env, env->msr)) { 49 return (uint32_t)(addr + arg); 50 } else 51 #endif 52 { 53 return addr + arg; 54 } 55 } 56 57 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 58 { 59 for (; reg < 32; reg++) { 60 if (needs_byteswap(env)) { 61 env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC())); 62 } else { 63 env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC()); 64 } 65 addr = addr_add(env, addr, 4); 66 } 67 } 68 69 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 70 { 71 for (; reg < 32; reg++) { 72 if (needs_byteswap(env)) { 73 cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]), 74 GETPC()); 75 } else { 76 cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC()); 77 } 78 addr = addr_add(env, addr, 4); 79 } 80 } 81 82 static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 83 uint32_t reg, uintptr_t raddr) 84 { 85 int sh; 86 87 for (; nb > 3; nb -= 4) { 88 env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr); 89 reg = (reg + 1) % 32; 90 addr = addr_add(env, addr, 4); 91 } 92 if (unlikely(nb > 0)) { 93 env->gpr[reg] = 0; 94 for (sh = 24; nb > 0; nb--, sh -= 8) { 95 env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh; 96 addr = addr_add(env, addr, 1); 97 } 98 } 99 } 100 101 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) 102 { 103 do_lsw(env, addr, nb, reg, GETPC()); 104 } 105 106 /* 107 * PPC32 specification says we must generate an exception if rA is in 108 * the range of registers to be loaded. In an other hand, IBM says 109 * this is valid, but rA won't be loaded. For now, I'll follow the 110 * spec... 111 */ 112 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, 113 uint32_t ra, uint32_t rb) 114 { 115 if (likely(xer_bc != 0)) { 116 int num_used_regs = DIV_ROUND_UP(xer_bc, 4); 117 if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) || 118 lsw_reg_in_range(reg, num_used_regs, rb))) { 119 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 120 POWERPC_EXCP_INVAL | 121 POWERPC_EXCP_INVAL_LSWX, GETPC()); 122 } else { 123 do_lsw(env, addr, xer_bc, reg, GETPC()); 124 } 125 } 126 } 127 128 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 129 uint32_t reg) 130 { 131 int sh; 132 133 for (; nb > 3; nb -= 4) { 134 cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC()); 135 reg = (reg + 1) % 32; 136 addr = addr_add(env, addr, 4); 137 } 138 if (unlikely(nb > 0)) { 139 for (sh = 24; nb > 0; nb--, sh -= 8) { 140 cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC()); 141 addr = addr_add(env, addr, 1); 142 } 143 } 144 } 145 146 static void dcbz_common(CPUPPCState *env, target_ulong addr, 147 uint32_t opcode, bool epid, uintptr_t retaddr) 148 { 149 target_ulong mask, dcbz_size = env->dcache_line_size; 150 uint32_t i; 151 void *haddr; 152 int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx; 153 154 #if defined(TARGET_PPC64) 155 /* Check for dcbz vs dcbzl on 970 */ 156 if (env->excp_model == POWERPC_EXCP_970 && 157 !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { 158 dcbz_size = 32; 159 } 160 #endif 161 162 /* Align address */ 163 mask = ~(dcbz_size - 1); 164 addr &= mask; 165 166 /* Check reservation */ 167 if ((env->reserve_addr & mask) == (addr & mask)) { 168 env->reserve_addr = (target_ulong)-1ULL; 169 } 170 171 /* Try fast path translate */ 172 haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx); 173 if (haddr) { 174 memset(haddr, 0, dcbz_size); 175 } else { 176 /* Slow path */ 177 for (i = 0; i < dcbz_size; i += 8) { 178 if (epid) { 179 #if !defined(CONFIG_USER_ONLY) 180 /* Does not make sense on USER_ONLY config */ 181 cpu_stq_eps_ra(env, addr + i, 0, retaddr); 182 #endif 183 } else { 184 cpu_stq_data_ra(env, addr + i, 0, retaddr); 185 } 186 } 187 } 188 } 189 190 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode) 191 { 192 dcbz_common(env, addr, opcode, false, GETPC()); 193 } 194 195 void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode) 196 { 197 dcbz_common(env, addr, opcode, true, GETPC()); 198 } 199 200 void helper_icbi(CPUPPCState *env, target_ulong addr) 201 { 202 addr &= ~(env->dcache_line_size - 1); 203 /* 204 * Invalidate one cache line : 205 * PowerPC specification says this is to be treated like a load 206 * (not a fetch) by the MMU. To be sure it will be so, 207 * do the load "by hand". 208 */ 209 cpu_ldl_data_ra(env, addr, GETPC()); 210 } 211 212 void helper_icbiep(CPUPPCState *env, target_ulong addr) 213 { 214 #if !defined(CONFIG_USER_ONLY) 215 /* See comments above */ 216 addr &= ~(env->dcache_line_size - 1); 217 cpu_ldl_epl_ra(env, addr, GETPC()); 218 #endif 219 } 220 221 /* XXX: to be tested */ 222 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, 223 uint32_t ra, uint32_t rb) 224 { 225 int i, c, d; 226 227 d = 24; 228 for (i = 0; i < xer_bc; i++) { 229 c = cpu_ldub_data_ra(env, addr, GETPC()); 230 addr = addr_add(env, addr, 1); 231 /* ra (if not 0) and rb are never modified */ 232 if (likely(reg != rb && (ra == 0 || reg != ra))) { 233 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); 234 } 235 if (unlikely(c == xer_cmp)) { 236 break; 237 } 238 if (likely(d != 0)) { 239 d -= 8; 240 } else { 241 d = 24; 242 reg++; 243 reg = reg & 0x1F; 244 } 245 } 246 return i; 247 } 248 249 #ifdef TARGET_PPC64 250 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, 251 uint32_t opidx) 252 { 253 Int128 ret; 254 255 /* We will have raised EXCP_ATOMIC from the translator. */ 256 assert(HAVE_ATOMIC128); 257 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); 258 env->retxh = int128_gethi(ret); 259 return int128_getlo(ret); 260 } 261 262 uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, 263 uint32_t opidx) 264 { 265 Int128 ret; 266 267 /* We will have raised EXCP_ATOMIC from the translator. */ 268 assert(HAVE_ATOMIC128); 269 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); 270 env->retxh = int128_gethi(ret); 271 return int128_getlo(ret); 272 } 273 274 void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, 275 uint64_t lo, uint64_t hi, uint32_t opidx) 276 { 277 Int128 val; 278 279 /* We will have raised EXCP_ATOMIC from the translator. */ 280 assert(HAVE_ATOMIC128); 281 val = int128_make128(lo, hi); 282 helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); 283 } 284 285 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, 286 uint64_t lo, uint64_t hi, uint32_t opidx) 287 { 288 Int128 val; 289 290 /* We will have raised EXCP_ATOMIC from the translator. */ 291 assert(HAVE_ATOMIC128); 292 val = int128_make128(lo, hi); 293 helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); 294 } 295 296 uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, 297 uint64_t new_lo, uint64_t new_hi, 298 uint32_t opidx) 299 { 300 bool success = false; 301 302 /* We will have raised EXCP_ATOMIC from the translator. */ 303 assert(HAVE_CMPXCHG128); 304 305 if (likely(addr == env->reserve_addr)) { 306 Int128 oldv, cmpv, newv; 307 308 cmpv = int128_make128(env->reserve_val2, env->reserve_val); 309 newv = int128_make128(new_lo, new_hi); 310 oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, 311 opidx, GETPC()); 312 success = int128_eq(oldv, cmpv); 313 } 314 env->reserve_addr = -1; 315 return env->so + success * CRF_EQ_BIT; 316 } 317 318 uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, 319 uint64_t new_lo, uint64_t new_hi, 320 uint32_t opidx) 321 { 322 bool success = false; 323 324 /* We will have raised EXCP_ATOMIC from the translator. */ 325 assert(HAVE_CMPXCHG128); 326 327 if (likely(addr == env->reserve_addr)) { 328 Int128 oldv, cmpv, newv; 329 330 cmpv = int128_make128(env->reserve_val2, env->reserve_val); 331 newv = int128_make128(new_lo, new_hi); 332 oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, 333 opidx, GETPC()); 334 success = int128_eq(oldv, cmpv); 335 } 336 env->reserve_addr = -1; 337 return env->so + success * CRF_EQ_BIT; 338 } 339 #endif 340 341 /*****************************************************************************/ 342 /* Altivec extension helpers */ 343 #if defined(HOST_WORDS_BIGENDIAN) 344 #define HI_IDX 0 345 #define LO_IDX 1 346 #else 347 #define HI_IDX 1 348 #define LO_IDX 0 349 #endif 350 351 /* 352 * We use msr_le to determine index ordering in a vector. However, 353 * byteswapping is not simply controlled by msr_le. We also need to 354 * take into account endianness of the target. This is done for the 355 * little-endian PPC64 user-mode target. 356 */ 357 358 #define LVE(name, access, swap, element) \ 359 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 360 target_ulong addr) \ 361 { \ 362 size_t n_elems = ARRAY_SIZE(r->element); \ 363 int adjust = HI_IDX * (n_elems - 1); \ 364 int sh = sizeof(r->element[0]) >> 1; \ 365 int index = (addr & 0xf) >> sh; \ 366 if (msr_le) { \ 367 index = n_elems - index - 1; \ 368 } \ 369 \ 370 if (needs_byteswap(env)) { \ 371 r->element[LO_IDX ? index : (adjust - index)] = \ 372 swap(access(env, addr, GETPC())); \ 373 } else { \ 374 r->element[LO_IDX ? index : (adjust - index)] = \ 375 access(env, addr, GETPC()); \ 376 } \ 377 } 378 #define I(x) (x) 379 LVE(lvebx, cpu_ldub_data_ra, I, u8) 380 LVE(lvehx, cpu_lduw_data_ra, bswap16, u16) 381 LVE(lvewx, cpu_ldl_data_ra, bswap32, u32) 382 #undef I 383 #undef LVE 384 385 #define STVE(name, access, swap, element) \ 386 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 387 target_ulong addr) \ 388 { \ 389 size_t n_elems = ARRAY_SIZE(r->element); \ 390 int adjust = HI_IDX * (n_elems - 1); \ 391 int sh = sizeof(r->element[0]) >> 1; \ 392 int index = (addr & 0xf) >> sh; \ 393 if (msr_le) { \ 394 index = n_elems - index - 1; \ 395 } \ 396 \ 397 if (needs_byteswap(env)) { \ 398 access(env, addr, swap(r->element[LO_IDX ? index : \ 399 (adjust - index)]), \ 400 GETPC()); \ 401 } else { \ 402 access(env, addr, r->element[LO_IDX ? index : \ 403 (adjust - index)], GETPC()); \ 404 } \ 405 } 406 #define I(x) (x) 407 STVE(stvebx, cpu_stb_data_ra, I, u8) 408 STVE(stvehx, cpu_stw_data_ra, bswap16, u16) 409 STVE(stvewx, cpu_stl_data_ra, bswap32, u32) 410 #undef I 411 #undef LVE 412 413 #ifdef TARGET_PPC64 414 #define GET_NB(rb) ((rb >> 56) & 0xFF) 415 416 #define VSX_LXVL(name, lj) \ 417 void helper_##name(CPUPPCState *env, target_ulong addr, \ 418 ppc_vsr_t *xt, target_ulong rb) \ 419 { \ 420 ppc_vsr_t t; \ 421 uint64_t nb = GET_NB(rb); \ 422 int i; \ 423 \ 424 t.s128 = int128_zero(); \ 425 if (nb) { \ 426 nb = (nb >= 16) ? 16 : nb; \ 427 if (msr_le && !lj) { \ 428 for (i = 16; i > 16 - nb; i--) { \ 429 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \ 430 addr = addr_add(env, addr, 1); \ 431 } \ 432 } else { \ 433 for (i = 0; i < nb; i++) { \ 434 t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \ 435 addr = addr_add(env, addr, 1); \ 436 } \ 437 } \ 438 } \ 439 *xt = t; \ 440 } 441 442 VSX_LXVL(lxvl, 0) 443 VSX_LXVL(lxvll, 1) 444 #undef VSX_LXVL 445 446 #define VSX_STXVL(name, lj) \ 447 void helper_##name(CPUPPCState *env, target_ulong addr, \ 448 ppc_vsr_t *xt, target_ulong rb) \ 449 { \ 450 target_ulong nb = GET_NB(rb); \ 451 int i; \ 452 \ 453 if (!nb) { \ 454 return; \ 455 } \ 456 \ 457 nb = (nb >= 16) ? 16 : nb; \ 458 if (msr_le && !lj) { \ 459 for (i = 16; i > 16 - nb; i--) { \ 460 cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \ 461 addr = addr_add(env, addr, 1); \ 462 } \ 463 } else { \ 464 for (i = 0; i < nb; i++) { \ 465 cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC()); \ 466 addr = addr_add(env, addr, 1); \ 467 } \ 468 } \ 469 } 470 471 VSX_STXVL(stxvl, 0) 472 VSX_STXVL(stxvll, 1) 473 #undef VSX_STXVL 474 #undef GET_NB 475 #endif /* TARGET_PPC64 */ 476 477 #undef HI_IDX 478 #undef LO_IDX 479 480 void helper_tbegin(CPUPPCState *env) 481 { 482 /* 483 * As a degenerate implementation, always fail tbegin. The reason 484 * given is "Nesting overflow". The "persistent" bit is set, 485 * providing a hint to the error handler to not retry. The TFIAR 486 * captures the address of the failure, which is this tbegin 487 * instruction. Instruction execution will continue with the next 488 * instruction in memory, which is precisely what we want. 489 */ 490 491 env->spr[SPR_TEXASR] = 492 (1ULL << TEXASR_FAILURE_PERSISTENT) | 493 (1ULL << TEXASR_NESTING_OVERFLOW) | 494 (msr_hv << TEXASR_PRIVILEGE_HV) | 495 (msr_pr << TEXASR_PRIVILEGE_PR) | 496 (1ULL << TEXASR_FAILURE_SUMMARY) | 497 (1ULL << TEXASR_TFIAR_EXACT); 498 env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr; 499 env->spr[SPR_TFHAR] = env->nip + 4; 500 env->crf[0] = 0xB; /* 0b1010 = transaction failure */ 501 } 502