1 /* 2 * PowerPC memory access emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/exec-all.h" 22 #include "qemu/host-utils.h" 23 #include "exec/helper-proto.h" 24 #include "helper_regs.h" 25 #include "exec/cpu_ldst.h" 26 #include "tcg.h" 27 #include "internal.h" 28 #include "qemu/atomic128.h" 29 30 //#define DEBUG_OP 31 32 static inline bool needs_byteswap(const CPUPPCState *env) 33 { 34 #if defined(TARGET_WORDS_BIGENDIAN) 35 return msr_le; 36 #else 37 return !msr_le; 38 #endif 39 } 40 41 /*****************************************************************************/ 42 /* Memory load and stores */ 43 44 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, 45 target_long arg) 46 { 47 #if defined(TARGET_PPC64) 48 if (!msr_is_64bit(env, env->msr)) { 49 return (uint32_t)(addr + arg); 50 } else 51 #endif 52 { 53 return addr + arg; 54 } 55 } 56 57 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 58 { 59 for (; reg < 32; reg++) { 60 if (needs_byteswap(env)) { 61 env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC())); 62 } else { 63 env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC()); 64 } 65 addr = addr_add(env, addr, 4); 66 } 67 } 68 69 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) 70 { 71 for (; reg < 32; reg++) { 72 if (needs_byteswap(env)) { 73 cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]), 74 GETPC()); 75 } else { 76 cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC()); 77 } 78 addr = addr_add(env, addr, 4); 79 } 80 } 81 82 static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 83 uint32_t reg, uintptr_t raddr) 84 { 85 int sh; 86 87 for (; nb > 3; nb -= 4) { 88 env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr); 89 reg = (reg + 1) % 32; 90 addr = addr_add(env, addr, 4); 91 } 92 if (unlikely(nb > 0)) { 93 env->gpr[reg] = 0; 94 for (sh = 24; nb > 0; nb--, sh -= 8) { 95 env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh; 96 addr = addr_add(env, addr, 1); 97 } 98 } 99 } 100 101 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) 102 { 103 do_lsw(env, addr, nb, reg, GETPC()); 104 } 105 106 /* PPC32 specification says we must generate an exception if 107 * rA is in the range of registers to be loaded. 108 * In an other hand, IBM says this is valid, but rA won't be loaded. 109 * For now, I'll follow the spec... 110 */ 111 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, 112 uint32_t ra, uint32_t rb) 113 { 114 if (likely(xer_bc != 0)) { 115 int num_used_regs = DIV_ROUND_UP(xer_bc, 4); 116 if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) || 117 lsw_reg_in_range(reg, num_used_regs, rb))) { 118 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 119 POWERPC_EXCP_INVAL | 120 POWERPC_EXCP_INVAL_LSWX, GETPC()); 121 } else { 122 do_lsw(env, addr, xer_bc, reg, GETPC()); 123 } 124 } 125 } 126 127 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, 128 uint32_t reg) 129 { 130 int sh; 131 132 for (; nb > 3; nb -= 4) { 133 cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC()); 134 reg = (reg + 1) % 32; 135 addr = addr_add(env, addr, 4); 136 } 137 if (unlikely(nb > 0)) { 138 for (sh = 24; nb > 0; nb--, sh -= 8) { 139 cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC()); 140 addr = addr_add(env, addr, 1); 141 } 142 } 143 } 144 145 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode) 146 { 147 target_ulong mask, dcbz_size = env->dcache_line_size; 148 uint32_t i; 149 void *haddr; 150 151 #if defined(TARGET_PPC64) 152 /* Check for dcbz vs dcbzl on 970 */ 153 if (env->excp_model == POWERPC_EXCP_970 && 154 !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { 155 dcbz_size = 32; 156 } 157 #endif 158 159 /* Align address */ 160 mask = ~(dcbz_size - 1); 161 addr &= mask; 162 163 /* Check reservation */ 164 if ((env->reserve_addr & mask) == (addr & mask)) { 165 env->reserve_addr = (target_ulong)-1ULL; 166 } 167 168 /* Try fast path translate */ 169 haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx); 170 if (haddr) { 171 memset(haddr, 0, dcbz_size); 172 } else { 173 /* Slow path */ 174 for (i = 0; i < dcbz_size; i += 8) { 175 cpu_stq_data_ra(env, addr + i, 0, GETPC()); 176 } 177 } 178 } 179 180 void helper_icbi(CPUPPCState *env, target_ulong addr) 181 { 182 addr &= ~(env->dcache_line_size - 1); 183 /* Invalidate one cache line : 184 * PowerPC specification says this is to be treated like a load 185 * (not a fetch) by the MMU. To be sure it will be so, 186 * do the load "by hand". 187 */ 188 cpu_ldl_data_ra(env, addr, GETPC()); 189 } 190 191 /* XXX: to be tested */ 192 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, 193 uint32_t ra, uint32_t rb) 194 { 195 int i, c, d; 196 197 d = 24; 198 for (i = 0; i < xer_bc; i++) { 199 c = cpu_ldub_data_ra(env, addr, GETPC()); 200 addr = addr_add(env, addr, 1); 201 /* ra (if not 0) and rb are never modified */ 202 if (likely(reg != rb && (ra == 0 || reg != ra))) { 203 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); 204 } 205 if (unlikely(c == xer_cmp)) { 206 break; 207 } 208 if (likely(d != 0)) { 209 d -= 8; 210 } else { 211 d = 24; 212 reg++; 213 reg = reg & 0x1F; 214 } 215 } 216 return i; 217 } 218 219 #ifdef TARGET_PPC64 220 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, 221 uint32_t opidx) 222 { 223 Int128 ret; 224 225 /* We will have raised EXCP_ATOMIC from the translator. */ 226 assert(HAVE_ATOMIC128); 227 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); 228 env->retxh = int128_gethi(ret); 229 return int128_getlo(ret); 230 } 231 232 uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, 233 uint32_t opidx) 234 { 235 Int128 ret; 236 237 /* We will have raised EXCP_ATOMIC from the translator. */ 238 assert(HAVE_ATOMIC128); 239 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); 240 env->retxh = int128_gethi(ret); 241 return int128_getlo(ret); 242 } 243 244 void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, 245 uint64_t lo, uint64_t hi, uint32_t opidx) 246 { 247 Int128 val; 248 249 /* We will have raised EXCP_ATOMIC from the translator. */ 250 assert(HAVE_ATOMIC128); 251 val = int128_make128(lo, hi); 252 helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); 253 } 254 255 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, 256 uint64_t lo, uint64_t hi, uint32_t opidx) 257 { 258 Int128 val; 259 260 /* We will have raised EXCP_ATOMIC from the translator. */ 261 assert(HAVE_ATOMIC128); 262 val = int128_make128(lo, hi); 263 helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); 264 } 265 266 uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, 267 uint64_t new_lo, uint64_t new_hi, 268 uint32_t opidx) 269 { 270 bool success = false; 271 272 /* We will have raised EXCP_ATOMIC from the translator. */ 273 assert(HAVE_CMPXCHG128); 274 275 if (likely(addr == env->reserve_addr)) { 276 Int128 oldv, cmpv, newv; 277 278 cmpv = int128_make128(env->reserve_val2, env->reserve_val); 279 newv = int128_make128(new_lo, new_hi); 280 oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, 281 opidx, GETPC()); 282 success = int128_eq(oldv, cmpv); 283 } 284 env->reserve_addr = -1; 285 return env->so + success * CRF_EQ_BIT; 286 } 287 288 uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, 289 uint64_t new_lo, uint64_t new_hi, 290 uint32_t opidx) 291 { 292 bool success = false; 293 294 /* We will have raised EXCP_ATOMIC from the translator. */ 295 assert(HAVE_CMPXCHG128); 296 297 if (likely(addr == env->reserve_addr)) { 298 Int128 oldv, cmpv, newv; 299 300 cmpv = int128_make128(env->reserve_val2, env->reserve_val); 301 newv = int128_make128(new_lo, new_hi); 302 oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, 303 opidx, GETPC()); 304 success = int128_eq(oldv, cmpv); 305 } 306 env->reserve_addr = -1; 307 return env->so + success * CRF_EQ_BIT; 308 } 309 #endif 310 311 /*****************************************************************************/ 312 /* Altivec extension helpers */ 313 #if defined(HOST_WORDS_BIGENDIAN) 314 #define HI_IDX 0 315 #define LO_IDX 1 316 #else 317 #define HI_IDX 1 318 #define LO_IDX 0 319 #endif 320 321 /* We use msr_le to determine index ordering in a vector. However, 322 byteswapping is not simply controlled by msr_le. We also need to take 323 into account endianness of the target. This is done for the little-endian 324 PPC64 user-mode target. */ 325 326 #define LVE(name, access, swap, element) \ 327 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 328 target_ulong addr) \ 329 { \ 330 size_t n_elems = ARRAY_SIZE(r->element); \ 331 int adjust = HI_IDX*(n_elems - 1); \ 332 int sh = sizeof(r->element[0]) >> 1; \ 333 int index = (addr & 0xf) >> sh; \ 334 if (msr_le) { \ 335 index = n_elems - index - 1; \ 336 } \ 337 \ 338 if (needs_byteswap(env)) { \ 339 r->element[LO_IDX ? index : (adjust - index)] = \ 340 swap(access(env, addr, GETPC())); \ 341 } else { \ 342 r->element[LO_IDX ? index : (adjust - index)] = \ 343 access(env, addr, GETPC()); \ 344 } \ 345 } 346 #define I(x) (x) 347 LVE(lvebx, cpu_ldub_data_ra, I, u8) 348 LVE(lvehx, cpu_lduw_data_ra, bswap16, u16) 349 LVE(lvewx, cpu_ldl_data_ra, bswap32, u32) 350 #undef I 351 #undef LVE 352 353 #define STVE(name, access, swap, element) \ 354 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ 355 target_ulong addr) \ 356 { \ 357 size_t n_elems = ARRAY_SIZE(r->element); \ 358 int adjust = HI_IDX * (n_elems - 1); \ 359 int sh = sizeof(r->element[0]) >> 1; \ 360 int index = (addr & 0xf) >> sh; \ 361 if (msr_le) { \ 362 index = n_elems - index - 1; \ 363 } \ 364 \ 365 if (needs_byteswap(env)) { \ 366 access(env, addr, swap(r->element[LO_IDX ? index : \ 367 (adjust - index)]), \ 368 GETPC()); \ 369 } else { \ 370 access(env, addr, r->element[LO_IDX ? index : \ 371 (adjust - index)], GETPC()); \ 372 } \ 373 } 374 #define I(x) (x) 375 STVE(stvebx, cpu_stb_data_ra, I, u8) 376 STVE(stvehx, cpu_stw_data_ra, bswap16, u16) 377 STVE(stvewx, cpu_stl_data_ra, bswap32, u32) 378 #undef I 379 #undef LVE 380 381 #ifdef TARGET_PPC64 382 #define GET_NB(rb) ((rb >> 56) & 0xFF) 383 384 #define VSX_LXVL(name, lj) \ 385 void helper_##name(CPUPPCState *env, target_ulong addr, \ 386 target_ulong xt_num, target_ulong rb) \ 387 { \ 388 int i; \ 389 ppc_vsr_t xt; \ 390 uint64_t nb = GET_NB(rb); \ 391 \ 392 xt.s128 = int128_zero(); \ 393 if (nb) { \ 394 nb = (nb >= 16) ? 16 : nb; \ 395 if (msr_le && !lj) { \ 396 for (i = 16; i > 16 - nb; i--) { \ 397 xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \ 398 addr = addr_add(env, addr, 1); \ 399 } \ 400 } else { \ 401 for (i = 0; i < nb; i++) { \ 402 xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \ 403 addr = addr_add(env, addr, 1); \ 404 } \ 405 } \ 406 } \ 407 putVSR(xt_num, &xt, env); \ 408 } 409 410 VSX_LXVL(lxvl, 0) 411 VSX_LXVL(lxvll, 1) 412 #undef VSX_LXVL 413 414 #define VSX_STXVL(name, lj) \ 415 void helper_##name(CPUPPCState *env, target_ulong addr, \ 416 target_ulong xt_num, target_ulong rb) \ 417 { \ 418 int i; \ 419 ppc_vsr_t xt; \ 420 target_ulong nb = GET_NB(rb); \ 421 \ 422 if (!nb) { \ 423 return; \ 424 } \ 425 getVSR(xt_num, &xt, env); \ 426 nb = (nb >= 16) ? 16 : nb; \ 427 if (msr_le && !lj) { \ 428 for (i = 16; i > 16 - nb; i--) { \ 429 cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \ 430 addr = addr_add(env, addr, 1); \ 431 } \ 432 } else { \ 433 for (i = 0; i < nb; i++) { \ 434 cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \ 435 addr = addr_add(env, addr, 1); \ 436 } \ 437 } \ 438 } 439 440 VSX_STXVL(stxvl, 0) 441 VSX_STXVL(stxvll, 1) 442 #undef VSX_STXVL 443 #undef GET_NB 444 #endif /* TARGET_PPC64 */ 445 446 #undef HI_IDX 447 #undef LO_IDX 448 449 void helper_tbegin(CPUPPCState *env) 450 { 451 /* As a degenerate implementation, always fail tbegin. The reason 452 * given is "Nesting overflow". The "persistent" bit is set, 453 * providing a hint to the error handler to not retry. The TFIAR 454 * captures the address of the failure, which is this tbegin 455 * instruction. Instruction execution will continue with the 456 * next instruction in memory, which is precisely what we want. 457 */ 458 459 env->spr[SPR_TEXASR] = 460 (1ULL << TEXASR_FAILURE_PERSISTENT) | 461 (1ULL << TEXASR_NESTING_OVERFLOW) | 462 (msr_hv << TEXASR_PRIVILEGE_HV) | 463 (msr_pr << TEXASR_PRIVILEGE_PR) | 464 (1ULL << TEXASR_FAILURE_SUMMARY) | 465 (1ULL << TEXASR_TFIAR_EXACT); 466 env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr; 467 env->spr[SPR_TFHAR] = env->nip + 4; 468 env->crf[0] = 0xB; /* 0b1010 = transaction failure */ 469 } 470