1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 #include "kvm_ppc.h" 13 #include "exec/helper-proto.h" 14 15 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 16 { 17 PowerPCCPU *cpu = opaque; 18 CPUPPCState *env = &cpu->env; 19 unsigned int i, j; 20 target_ulong sdr1; 21 uint32_t fpscr, vscr; 22 #if defined(TARGET_PPC64) 23 int32_t slb_nr; 24 #endif 25 target_ulong xer; 26 27 for (i = 0; i < 32; i++) { 28 qemu_get_betls(f, &env->gpr[i]); 29 } 30 #if !defined(TARGET_PPC64) 31 for (i = 0; i < 32; i++) { 32 qemu_get_betls(f, &env->gprh[i]); 33 } 34 #endif 35 qemu_get_betls(f, &env->lr); 36 qemu_get_betls(f, &env->ctr); 37 for (i = 0; i < 8; i++) { 38 qemu_get_be32s(f, &env->crf[i]); 39 } 40 qemu_get_betls(f, &xer); 41 cpu_write_xer(env, xer); 42 qemu_get_betls(f, &env->reserve_addr); 43 qemu_get_betls(f, &env->msr); 44 for (i = 0; i < 4; i++) { 45 qemu_get_betls(f, &env->tgpr[i]); 46 } 47 for (i = 0; i < 32; i++) { 48 union { 49 float64 d; 50 uint64_t l; 51 } u; 52 u.l = qemu_get_be64(f); 53 *cpu_fpr_ptr(env, i) = u.d; 54 } 55 qemu_get_be32s(f, &fpscr); 56 env->fpscr = fpscr; 57 qemu_get_sbe32s(f, &env->access_type); 58 #if defined(TARGET_PPC64) 59 qemu_get_betls(f, &env->spr[SPR_ASR]); 60 qemu_get_sbe32s(f, &slb_nr); 61 #endif 62 qemu_get_betls(f, &sdr1); 63 for (i = 0; i < 32; i++) { 64 qemu_get_betls(f, &env->sr[i]); 65 } 66 for (i = 0; i < 2; i++) { 67 for (j = 0; j < 8; j++) { 68 qemu_get_betls(f, &env->DBAT[i][j]); 69 } 70 } 71 for (i = 0; i < 2; i++) { 72 for (j = 0; j < 8; j++) { 73 qemu_get_betls(f, &env->IBAT[i][j]); 74 } 75 } 76 qemu_get_sbe32s(f, &env->nb_tlb); 77 qemu_get_sbe32s(f, &env->tlb_per_way); 78 qemu_get_sbe32s(f, &env->nb_ways); 79 qemu_get_sbe32s(f, &env->last_way); 80 qemu_get_sbe32s(f, &env->id_tlbs); 81 qemu_get_sbe32s(f, &env->nb_pids); 82 if (env->tlb.tlb6) { 83 /* XXX assumes 6xx */ 84 for (i = 0; i < env->nb_tlb; i++) { 85 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 86 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 87 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 88 } 89 } 90 for (i = 0; i < 4; i++) { 91 qemu_get_betls(f, &env->pb[i]); 92 } 93 for (i = 0; i < 1024; i++) { 94 qemu_get_betls(f, &env->spr[i]); 95 } 96 if (!cpu->vhyp) { 97 ppc_store_sdr1(env, sdr1); 98 } 99 qemu_get_be32s(f, &vscr); 100 helper_mtvscr(env, vscr); 101 qemu_get_be64s(f, &env->spe_acc); 102 qemu_get_be32s(f, &env->spe_fscr); 103 qemu_get_betls(f, &env->msr_mask); 104 qemu_get_be32s(f, &env->flags); 105 qemu_get_sbe32s(f, &env->error_code); 106 qemu_get_be32s(f, &env->pending_interrupts); 107 qemu_get_be32s(f, &env->irq_input_state); 108 for (i = 0; i < POWERPC_EXCP_NB; i++) { 109 qemu_get_betls(f, &env->excp_vectors[i]); 110 } 111 qemu_get_betls(f, &env->excp_prefix); 112 qemu_get_betls(f, &env->ivor_mask); 113 qemu_get_betls(f, &env->ivpr_mask); 114 qemu_get_betls(f, &env->hreset_vector); 115 qemu_get_betls(f, &env->nip); 116 qemu_get_betls(f, &env->hflags); 117 qemu_get_betls(f, &env->hflags_nmsr); 118 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 119 qemu_get_sbe32(f); /* Discard unused power_mode */ 120 121 /* Recompute mmu indices */ 122 hreg_compute_mem_idx(env); 123 124 return 0; 125 } 126 127 static int get_avr(QEMUFile *f, void *pv, size_t size, 128 const VMStateField *field) 129 { 130 ppc_avr_t *v = pv; 131 132 v->u64[0] = qemu_get_be64(f); 133 v->u64[1] = qemu_get_be64(f); 134 135 return 0; 136 } 137 138 static int put_avr(QEMUFile *f, void *pv, size_t size, 139 const VMStateField *field, QJSON *vmdesc) 140 { 141 ppc_avr_t *v = pv; 142 143 qemu_put_be64(f, v->u64[0]); 144 qemu_put_be64(f, v->u64[1]); 145 return 0; 146 } 147 148 static const VMStateInfo vmstate_info_avr = { 149 .name = "avr", 150 .get = get_avr, 151 .put = put_avr, 152 }; 153 154 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 155 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) 156 157 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 158 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 159 160 static int get_fpr(QEMUFile *f, void *pv, size_t size, 161 const VMStateField *field) 162 { 163 ppc_vsr_t *v = pv; 164 165 v->VsrD(0) = qemu_get_be64(f); 166 167 return 0; 168 } 169 170 static int put_fpr(QEMUFile *f, void *pv, size_t size, 171 const VMStateField *field, QJSON *vmdesc) 172 { 173 ppc_vsr_t *v = pv; 174 175 qemu_put_be64(f, v->VsrD(0)); 176 return 0; 177 } 178 179 static const VMStateInfo vmstate_info_fpr = { 180 .name = "fpr", 181 .get = get_fpr, 182 .put = put_fpr, 183 }; 184 185 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ 186 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) 187 188 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ 189 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) 190 191 static int get_vsr(QEMUFile *f, void *pv, size_t size, 192 const VMStateField *field) 193 { 194 ppc_vsr_t *v = pv; 195 196 v->VsrD(1) = qemu_get_be64(f); 197 198 return 0; 199 } 200 201 static int put_vsr(QEMUFile *f, void *pv, size_t size, 202 const VMStateField *field, QJSON *vmdesc) 203 { 204 ppc_vsr_t *v = pv; 205 206 qemu_put_be64(f, v->VsrD(1)); 207 return 0; 208 } 209 210 static const VMStateInfo vmstate_info_vsr = { 211 .name = "vsr", 212 .get = get_vsr, 213 .put = put_vsr, 214 }; 215 216 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ 217 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) 218 219 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ 220 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) 221 222 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 223 { 224 PowerPCCPU *cpu = opaque; 225 226 return cpu->pre_2_8_migration; 227 } 228 229 #if defined(TARGET_PPC64) 230 static bool cpu_pre_3_0_migration(void *opaque, int version_id) 231 { 232 PowerPCCPU *cpu = opaque; 233 234 return cpu->pre_3_0_migration; 235 } 236 #endif 237 238 static int cpu_pre_save(void *opaque) 239 { 240 PowerPCCPU *cpu = opaque; 241 CPUPPCState *env = &cpu->env; 242 int i; 243 uint64_t insns_compat_mask = 244 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 245 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 246 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 247 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 248 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 249 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 250 | PPC_64B | PPC_64BX | PPC_ALTIVEC 251 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 252 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 253 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 254 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 255 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 256 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 257 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 258 259 env->spr[SPR_LR] = env->lr; 260 env->spr[SPR_CTR] = env->ctr; 261 env->spr[SPR_XER] = cpu_read_xer(env); 262 #if defined(TARGET_PPC64) 263 env->spr[SPR_CFAR] = env->cfar; 264 #endif 265 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 266 267 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 268 env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; 269 env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; 270 env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; 271 env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; 272 } 273 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 274 env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; 275 env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4]; 276 env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4]; 277 env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; 278 } 279 280 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 281 if (cpu->pre_2_8_migration) { 282 /* 283 * Mask out bits that got added to msr_mask since the versions 284 * which stupidly included it in the migration stream. 285 */ 286 target_ulong metamask = 0 287 #if defined(TARGET_PPC64) 288 | (1ULL << MSR_TS0) 289 | (1ULL << MSR_TS1) 290 #endif 291 ; 292 cpu->mig_msr_mask = env->msr_mask & ~metamask; 293 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 294 /* 295 * CPU models supported by old machines all have 296 * PPC_MEM_TLBIE, so we set it unconditionally to allow 297 * backward migration from a POWER9 host to a POWER8 host. 298 */ 299 cpu->mig_insns_flags |= PPC_MEM_TLBIE; 300 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 301 cpu->mig_nb_BATs = env->nb_BATs; 302 } 303 if (cpu->pre_3_0_migration) { 304 if (cpu->hash64_opts) { 305 cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 306 } 307 } 308 309 return 0; 310 } 311 312 /* 313 * Determine if a given PVR is a "close enough" match to the CPU 314 * object. For TCG and KVM PR it would probably be sufficient to 315 * require an exact PVR match. However for KVM HV the user is 316 * restricted to a PVR exactly matching the host CPU. The correct way 317 * to handle this is to put the guest into an architected 318 * compatibility mode. However, to allow a more forgiving transition 319 * and migration from before this was widely done, we allow migration 320 * between sufficiently similar PVRs, as determined by the CPU class's 321 * pvr_match() hook. 322 */ 323 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 324 { 325 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 326 327 if (pvr == pcc->pvr) { 328 return true; 329 } 330 return pcc->pvr_match(pcc, pvr); 331 } 332 333 static int cpu_post_load(void *opaque, int version_id) 334 { 335 PowerPCCPU *cpu = opaque; 336 CPUPPCState *env = &cpu->env; 337 int i; 338 target_ulong msr; 339 340 /* 341 * If we're operating in compat mode, we should be ok as long as 342 * the destination supports the same compatiblity mode. 343 * 344 * Otherwise, however, we require that the destination has exactly 345 * the same CPU model as the source. 346 */ 347 348 #if defined(TARGET_PPC64) 349 if (cpu->compat_pvr) { 350 uint32_t compat_pvr = cpu->compat_pvr; 351 Error *local_err = NULL; 352 353 cpu->compat_pvr = 0; 354 ppc_set_compat(cpu, compat_pvr, &local_err); 355 if (local_err) { 356 error_report_err(local_err); 357 return -1; 358 } 359 } else 360 #endif 361 { 362 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 363 return -1; 364 } 365 } 366 367 /* 368 * If we're running with KVM HV, there is a chance that the guest 369 * is running with KVM HV and its kernel does not have the 370 * capability of dealing with a different PVR other than this 371 * exact host PVR in KVM_SET_SREGS. If that happens, the 372 * guest freezes after migration. 373 * 374 * The function kvmppc_pvr_workaround_required does this verification 375 * by first checking if the kernel has the cap, returning true immediately 376 * if that is the case. Otherwise, it checks if we're running in KVM PR. 377 * If the guest kernel does not have the cap and we're not running KVM-PR 378 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 379 * receive the PVR it expects as a workaround. 380 * 381 */ 382 #if defined(CONFIG_KVM) 383 if (kvmppc_pvr_workaround_required(cpu)) { 384 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 385 } 386 #endif 387 388 env->lr = env->spr[SPR_LR]; 389 env->ctr = env->spr[SPR_CTR]; 390 cpu_write_xer(env, env->spr[SPR_XER]); 391 #if defined(TARGET_PPC64) 392 env->cfar = env->spr[SPR_CFAR]; 393 #endif 394 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 395 396 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 397 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i]; 398 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1]; 399 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i]; 400 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1]; 401 } 402 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 403 env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i]; 404 env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1]; 405 env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i]; 406 env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1]; 407 } 408 409 if (!cpu->vhyp) { 410 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 411 } 412 413 /* 414 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB 415 * before restoring 416 */ 417 msr = env->msr; 418 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); 419 ppc_store_msr(env, msr); 420 421 hreg_compute_mem_idx(env); 422 423 return 0; 424 } 425 426 static bool fpu_needed(void *opaque) 427 { 428 PowerPCCPU *cpu = opaque; 429 430 return cpu->env.insns_flags & PPC_FLOAT; 431 } 432 433 static const VMStateDescription vmstate_fpu = { 434 .name = "cpu/fpu", 435 .version_id = 1, 436 .minimum_version_id = 1, 437 .needed = fpu_needed, 438 .fields = (VMStateField[]) { 439 VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), 440 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 441 VMSTATE_END_OF_LIST() 442 }, 443 }; 444 445 static bool altivec_needed(void *opaque) 446 { 447 PowerPCCPU *cpu = opaque; 448 449 return cpu->env.insns_flags & PPC_ALTIVEC; 450 } 451 452 static int get_vscr(QEMUFile *f, void *opaque, size_t size, 453 const VMStateField *field) 454 { 455 PowerPCCPU *cpu = opaque; 456 helper_mtvscr(&cpu->env, qemu_get_be32(f)); 457 return 0; 458 } 459 460 static int put_vscr(QEMUFile *f, void *opaque, size_t size, 461 const VMStateField *field, QJSON *vmdesc) 462 { 463 PowerPCCPU *cpu = opaque; 464 qemu_put_be32(f, helper_mfvscr(&cpu->env)); 465 return 0; 466 } 467 468 static const VMStateInfo vmstate_vscr = { 469 .name = "cpu/altivec/vscr", 470 .get = get_vscr, 471 .put = put_vscr, 472 }; 473 474 static const VMStateDescription vmstate_altivec = { 475 .name = "cpu/altivec", 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .needed = altivec_needed, 479 .fields = (VMStateField[]) { 480 VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), 481 /* 482 * Save the architecture value of the vscr, not the internally 483 * expanded version. Since this architecture value does not 484 * exist in memory to be stored, this requires a but of hoop 485 * jumping. We want OFFSET=0 so that we effectively pass CPU 486 * to the helper functions. 487 */ 488 { 489 .name = "vscr", 490 .version_id = 0, 491 .size = sizeof(uint32_t), 492 .info = &vmstate_vscr, 493 .flags = VMS_SINGLE, 494 .offset = 0 495 }, 496 VMSTATE_END_OF_LIST() 497 }, 498 }; 499 500 static bool vsx_needed(void *opaque) 501 { 502 PowerPCCPU *cpu = opaque; 503 504 return cpu->env.insns_flags2 & PPC2_VSX; 505 } 506 507 static const VMStateDescription vmstate_vsx = { 508 .name = "cpu/vsx", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .needed = vsx_needed, 512 .fields = (VMStateField[]) { 513 VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), 514 VMSTATE_END_OF_LIST() 515 }, 516 }; 517 518 #ifdef TARGET_PPC64 519 /* Transactional memory state */ 520 static bool tm_needed(void *opaque) 521 { 522 PowerPCCPU *cpu = opaque; 523 CPUPPCState *env = &cpu->env; 524 return msr_ts; 525 } 526 527 static const VMStateDescription vmstate_tm = { 528 .name = "cpu/tm", 529 .version_id = 1, 530 .minimum_version_id = 1, 531 .minimum_version_id_old = 1, 532 .needed = tm_needed, 533 .fields = (VMStateField []) { 534 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 535 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 536 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 537 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 538 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 539 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 540 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 541 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 542 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 543 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 544 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 545 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 546 VMSTATE_END_OF_LIST() 547 }, 548 }; 549 #endif 550 551 static bool sr_needed(void *opaque) 552 { 553 #ifdef TARGET_PPC64 554 PowerPCCPU *cpu = opaque; 555 556 return !(cpu->env.mmu_model & POWERPC_MMU_64); 557 #else 558 return true; 559 #endif 560 } 561 562 static const VMStateDescription vmstate_sr = { 563 .name = "cpu/sr", 564 .version_id = 1, 565 .minimum_version_id = 1, 566 .needed = sr_needed, 567 .fields = (VMStateField[]) { 568 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 569 VMSTATE_END_OF_LIST() 570 }, 571 }; 572 573 #ifdef TARGET_PPC64 574 static int get_slbe(QEMUFile *f, void *pv, size_t size, 575 const VMStateField *field) 576 { 577 ppc_slb_t *v = pv; 578 579 v->esid = qemu_get_be64(f); 580 v->vsid = qemu_get_be64(f); 581 582 return 0; 583 } 584 585 static int put_slbe(QEMUFile *f, void *pv, size_t size, 586 const VMStateField *field, QJSON *vmdesc) 587 { 588 ppc_slb_t *v = pv; 589 590 qemu_put_be64(f, v->esid); 591 qemu_put_be64(f, v->vsid); 592 return 0; 593 } 594 595 static const VMStateInfo vmstate_info_slbe = { 596 .name = "slbe", 597 .get = get_slbe, 598 .put = put_slbe, 599 }; 600 601 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 602 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 603 604 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 605 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 606 607 static bool slb_needed(void *opaque) 608 { 609 PowerPCCPU *cpu = opaque; 610 611 /* We don't support any of the old segment table based 64-bit CPUs */ 612 return cpu->env.mmu_model & POWERPC_MMU_64; 613 } 614 615 static int slb_post_load(void *opaque, int version_id) 616 { 617 PowerPCCPU *cpu = opaque; 618 CPUPPCState *env = &cpu->env; 619 int i; 620 621 /* 622 * We've pulled in the raw esid and vsid values from the migration 623 * stream, but we need to recompute the page size pointers 624 */ 625 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 626 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 627 /* Migration source had bad values in its SLB */ 628 return -1; 629 } 630 } 631 632 return 0; 633 } 634 635 static const VMStateDescription vmstate_slb = { 636 .name = "cpu/slb", 637 .version_id = 1, 638 .minimum_version_id = 1, 639 .needed = slb_needed, 640 .post_load = slb_post_load, 641 .fields = (VMStateField[]) { 642 VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration), 643 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 644 VMSTATE_END_OF_LIST() 645 } 646 }; 647 #endif /* TARGET_PPC64 */ 648 649 static const VMStateDescription vmstate_tlb6xx_entry = { 650 .name = "cpu/tlb6xx_entry", 651 .version_id = 1, 652 .minimum_version_id = 1, 653 .fields = (VMStateField[]) { 654 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 655 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 656 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 657 VMSTATE_END_OF_LIST() 658 }, 659 }; 660 661 static bool tlb6xx_needed(void *opaque) 662 { 663 PowerPCCPU *cpu = opaque; 664 CPUPPCState *env = &cpu->env; 665 666 return env->nb_tlb && (env->tlb_type == TLB_6XX); 667 } 668 669 static const VMStateDescription vmstate_tlb6xx = { 670 .name = "cpu/tlb6xx", 671 .version_id = 1, 672 .minimum_version_id = 1, 673 .needed = tlb6xx_needed, 674 .fields = (VMStateField[]) { 675 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 676 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 677 env.nb_tlb, 678 vmstate_tlb6xx_entry, 679 ppc6xx_tlb_t), 680 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 681 VMSTATE_END_OF_LIST() 682 } 683 }; 684 685 static const VMStateDescription vmstate_tlbemb_entry = { 686 .name = "cpu/tlbemb_entry", 687 .version_id = 1, 688 .minimum_version_id = 1, 689 .fields = (VMStateField[]) { 690 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 691 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 692 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 693 VMSTATE_UINTTL(size, ppcemb_tlb_t), 694 VMSTATE_UINT32(prot, ppcemb_tlb_t), 695 VMSTATE_UINT32(attr, ppcemb_tlb_t), 696 VMSTATE_END_OF_LIST() 697 }, 698 }; 699 700 static bool tlbemb_needed(void *opaque) 701 { 702 PowerPCCPU *cpu = opaque; 703 CPUPPCState *env = &cpu->env; 704 705 return env->nb_tlb && (env->tlb_type == TLB_EMB); 706 } 707 708 static bool pbr403_needed(void *opaque) 709 { 710 PowerPCCPU *cpu = opaque; 711 uint32_t pvr = cpu->env.spr[SPR_PVR]; 712 713 return (pvr & 0xffff0000) == 0x00200000; 714 } 715 716 static const VMStateDescription vmstate_pbr403 = { 717 .name = "cpu/pbr403", 718 .version_id = 1, 719 .minimum_version_id = 1, 720 .needed = pbr403_needed, 721 .fields = (VMStateField[]) { 722 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 723 VMSTATE_END_OF_LIST() 724 }, 725 }; 726 727 static const VMStateDescription vmstate_tlbemb = { 728 .name = "cpu/tlb6xx", 729 .version_id = 1, 730 .minimum_version_id = 1, 731 .needed = tlbemb_needed, 732 .fields = (VMStateField[]) { 733 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 734 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 735 env.nb_tlb, 736 vmstate_tlbemb_entry, 737 ppcemb_tlb_t), 738 /* 403 protection registers */ 739 VMSTATE_END_OF_LIST() 740 }, 741 .subsections = (const VMStateDescription*[]) { 742 &vmstate_pbr403, 743 NULL 744 } 745 }; 746 747 static const VMStateDescription vmstate_tlbmas_entry = { 748 .name = "cpu/tlbmas_entry", 749 .version_id = 1, 750 .minimum_version_id = 1, 751 .fields = (VMStateField[]) { 752 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 753 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 754 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 755 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 756 VMSTATE_END_OF_LIST() 757 }, 758 }; 759 760 static bool tlbmas_needed(void *opaque) 761 { 762 PowerPCCPU *cpu = opaque; 763 CPUPPCState *env = &cpu->env; 764 765 return env->nb_tlb && (env->tlb_type == TLB_MAS); 766 } 767 768 static const VMStateDescription vmstate_tlbmas = { 769 .name = "cpu/tlbmas", 770 .version_id = 1, 771 .minimum_version_id = 1, 772 .needed = tlbmas_needed, 773 .fields = (VMStateField[]) { 774 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 775 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 776 env.nb_tlb, 777 vmstate_tlbmas_entry, 778 ppcmas_tlb_t), 779 VMSTATE_END_OF_LIST() 780 } 781 }; 782 783 static bool compat_needed(void *opaque) 784 { 785 PowerPCCPU *cpu = opaque; 786 787 assert(!(cpu->compat_pvr && !cpu->vhyp)); 788 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 789 } 790 791 static const VMStateDescription vmstate_compat = { 792 .name = "cpu/compat", 793 .version_id = 1, 794 .minimum_version_id = 1, 795 .needed = compat_needed, 796 .fields = (VMStateField[]) { 797 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 798 VMSTATE_END_OF_LIST() 799 } 800 }; 801 802 const VMStateDescription vmstate_ppc_cpu = { 803 .name = "cpu", 804 .version_id = 5, 805 .minimum_version_id = 5, 806 .minimum_version_id_old = 4, 807 .load_state_old = cpu_load_old, 808 .pre_save = cpu_pre_save, 809 .post_load = cpu_post_load, 810 .fields = (VMStateField[]) { 811 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 812 813 /* User mode architected state */ 814 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 815 #if !defined(TARGET_PPC64) 816 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 817 #endif 818 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 819 VMSTATE_UINTTL(env.nip, PowerPCCPU), 820 821 /* SPRs */ 822 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 823 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 824 825 /* Reservation */ 826 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 827 828 /* Supervisor mode architected state */ 829 VMSTATE_UINTTL(env.msr, PowerPCCPU), 830 831 /* Internal state */ 832 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 833 /* FIXME: access_type? */ 834 835 /* Sanity checking */ 836 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 837 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 838 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 839 cpu_pre_2_8_migration), 840 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 841 VMSTATE_END_OF_LIST() 842 }, 843 .subsections = (const VMStateDescription*[]) { 844 &vmstate_fpu, 845 &vmstate_altivec, 846 &vmstate_vsx, 847 &vmstate_sr, 848 #ifdef TARGET_PPC64 849 &vmstate_tm, 850 &vmstate_slb, 851 #endif /* TARGET_PPC64 */ 852 &vmstate_tlb6xx, 853 &vmstate_tlbemb, 854 &vmstate_tlbmas, 855 &vmstate_compat, 856 NULL 857 } 858 }; 859