1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 #include "kvm_ppc.h" 13 14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 15 { 16 PowerPCCPU *cpu = opaque; 17 CPUPPCState *env = &cpu->env; 18 unsigned int i, j; 19 target_ulong sdr1; 20 uint32_t fpscr; 21 target_ulong xer; 22 23 for (i = 0; i < 32; i++) 24 qemu_get_betls(f, &env->gpr[i]); 25 #if !defined(TARGET_PPC64) 26 for (i = 0; i < 32; i++) 27 qemu_get_betls(f, &env->gprh[i]); 28 #endif 29 qemu_get_betls(f, &env->lr); 30 qemu_get_betls(f, &env->ctr); 31 for (i = 0; i < 8; i++) 32 qemu_get_be32s(f, &env->crf[i]); 33 qemu_get_betls(f, &xer); 34 cpu_write_xer(env, xer); 35 qemu_get_betls(f, &env->reserve_addr); 36 qemu_get_betls(f, &env->msr); 37 for (i = 0; i < 4; i++) 38 qemu_get_betls(f, &env->tgpr[i]); 39 for (i = 0; i < 32; i++) { 40 union { 41 float64 d; 42 uint64_t l; 43 } u; 44 u.l = qemu_get_be64(f); 45 env->fpr[i] = u.d; 46 } 47 qemu_get_be32s(f, &fpscr); 48 env->fpscr = fpscr; 49 qemu_get_sbe32s(f, &env->access_type); 50 #if defined(TARGET_PPC64) 51 qemu_get_betls(f, &env->spr[SPR_ASR]); 52 qemu_get_sbe32s(f, &env->slb_nr); 53 #endif 54 qemu_get_betls(f, &sdr1); 55 for (i = 0; i < 32; i++) 56 qemu_get_betls(f, &env->sr[i]); 57 for (i = 0; i < 2; i++) 58 for (j = 0; j < 8; j++) 59 qemu_get_betls(f, &env->DBAT[i][j]); 60 for (i = 0; i < 2; i++) 61 for (j = 0; j < 8; j++) 62 qemu_get_betls(f, &env->IBAT[i][j]); 63 qemu_get_sbe32s(f, &env->nb_tlb); 64 qemu_get_sbe32s(f, &env->tlb_per_way); 65 qemu_get_sbe32s(f, &env->nb_ways); 66 qemu_get_sbe32s(f, &env->last_way); 67 qemu_get_sbe32s(f, &env->id_tlbs); 68 qemu_get_sbe32s(f, &env->nb_pids); 69 if (env->tlb.tlb6) { 70 // XXX assumes 6xx 71 for (i = 0; i < env->nb_tlb; i++) { 72 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 73 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 74 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 75 } 76 } 77 for (i = 0; i < 4; i++) 78 qemu_get_betls(f, &env->pb[i]); 79 for (i = 0; i < 1024; i++) 80 qemu_get_betls(f, &env->spr[i]); 81 if (!cpu->vhyp) { 82 ppc_store_sdr1(env, sdr1); 83 } 84 qemu_get_be32s(f, &env->vscr); 85 qemu_get_be64s(f, &env->spe_acc); 86 qemu_get_be32s(f, &env->spe_fscr); 87 qemu_get_betls(f, &env->msr_mask); 88 qemu_get_be32s(f, &env->flags); 89 qemu_get_sbe32s(f, &env->error_code); 90 qemu_get_be32s(f, &env->pending_interrupts); 91 qemu_get_be32s(f, &env->irq_input_state); 92 for (i = 0; i < POWERPC_EXCP_NB; i++) 93 qemu_get_betls(f, &env->excp_vectors[i]); 94 qemu_get_betls(f, &env->excp_prefix); 95 qemu_get_betls(f, &env->ivor_mask); 96 qemu_get_betls(f, &env->ivpr_mask); 97 qemu_get_betls(f, &env->hreset_vector); 98 qemu_get_betls(f, &env->nip); 99 qemu_get_betls(f, &env->hflags); 100 qemu_get_betls(f, &env->hflags_nmsr); 101 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 102 qemu_get_sbe32(f); /* Discard unused power_mode */ 103 104 /* Recompute mmu indices */ 105 hreg_compute_mem_idx(env); 106 107 return 0; 108 } 109 110 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 111 { 112 ppc_avr_t *v = pv; 113 114 v->u64[0] = qemu_get_be64(f); 115 v->u64[1] = qemu_get_be64(f); 116 117 return 0; 118 } 119 120 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 121 QJSON *vmdesc) 122 { 123 ppc_avr_t *v = pv; 124 125 qemu_put_be64(f, v->u64[0]); 126 qemu_put_be64(f, v->u64[1]); 127 return 0; 128 } 129 130 static const VMStateInfo vmstate_info_avr = { 131 .name = "avr", 132 .get = get_avr, 133 .put = put_avr, 134 }; 135 136 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 137 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 138 139 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 140 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 141 142 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 143 { 144 PowerPCCPU *cpu = opaque; 145 146 return cpu->pre_2_8_migration; 147 } 148 149 static void cpu_pre_save(void *opaque) 150 { 151 PowerPCCPU *cpu = opaque; 152 CPUPPCState *env = &cpu->env; 153 int i; 154 uint64_t insns_compat_mask = 155 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 156 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 157 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 158 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 159 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 160 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 161 | PPC_64B | PPC_64BX | PPC_ALTIVEC 162 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 163 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 164 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 165 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 166 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 167 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 168 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 169 170 env->spr[SPR_LR] = env->lr; 171 env->spr[SPR_CTR] = env->ctr; 172 env->spr[SPR_XER] = cpu_read_xer(env); 173 #if defined(TARGET_PPC64) 174 env->spr[SPR_CFAR] = env->cfar; 175 #endif 176 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 177 178 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 179 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 180 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 181 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 182 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 183 } 184 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 185 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 186 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 187 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 188 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 189 } 190 191 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 192 if (cpu->pre_2_8_migration) { 193 cpu->mig_msr_mask = env->msr_mask; 194 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 195 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 196 cpu->mig_nb_BATs = env->nb_BATs; 197 } 198 } 199 200 /* 201 * Determine if a given PVR is a "close enough" match to the CPU 202 * object. For TCG and KVM PR it would probably be sufficient to 203 * require an exact PVR match. However for KVM HV the user is 204 * restricted to a PVR exactly matching the host CPU. The correct way 205 * to handle this is to put the guest into an architected 206 * compatibility mode. However, to allow a more forgiving transition 207 * and migration from before this was widely done, we allow migration 208 * between sufficiently similar PVRs, as determined by the CPU class's 209 * pvr_match() hook. 210 */ 211 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 212 { 213 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 214 215 if (pvr == pcc->pvr) { 216 return true; 217 } 218 return pcc->pvr_match(pcc, pvr); 219 } 220 221 static int cpu_post_load(void *opaque, int version_id) 222 { 223 PowerPCCPU *cpu = opaque; 224 CPUPPCState *env = &cpu->env; 225 int i; 226 target_ulong msr; 227 228 /* 229 * If we're operating in compat mode, we should be ok as long as 230 * the destination supports the same compatiblity mode. 231 * 232 * Otherwise, however, we require that the destination has exactly 233 * the same CPU model as the source. 234 */ 235 236 #if defined(TARGET_PPC64) 237 if (cpu->compat_pvr) { 238 Error *local_err = NULL; 239 240 ppc_set_compat(cpu, cpu->compat_pvr, &local_err); 241 if (local_err) { 242 error_report_err(local_err); 243 return -1; 244 } 245 } else 246 #endif 247 { 248 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 249 return -1; 250 } 251 } 252 253 /* 254 * If we're running with KVM HV, there is a chance that the guest 255 * is running with KVM HV and its kernel does not have the 256 * capability of dealing with a different PVR other than this 257 * exact host PVR in KVM_SET_SREGS. If that happens, the 258 * guest freezes after migration. 259 * 260 * The function kvmppc_pvr_workaround_required does this verification 261 * by first checking if the kernel has the cap, returning true immediately 262 * if that is the case. Otherwise, it checks if we're running in KVM PR. 263 * If the guest kernel does not have the cap and we're not running KVM-PR 264 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 265 * receive the PVR it expects as a workaround. 266 * 267 */ 268 #if defined(CONFIG_KVM) 269 if (kvmppc_pvr_workaround_required(cpu)) { 270 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 271 } 272 #endif 273 274 env->lr = env->spr[SPR_LR]; 275 env->ctr = env->spr[SPR_CTR]; 276 cpu_write_xer(env, env->spr[SPR_XER]); 277 #if defined(TARGET_PPC64) 278 env->cfar = env->spr[SPR_CFAR]; 279 #endif 280 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 281 282 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 283 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 284 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 285 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 286 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 287 } 288 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 289 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 290 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 291 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 292 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 293 } 294 295 if (!cpu->vhyp) { 296 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 297 } 298 299 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 300 msr = env->msr; 301 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 302 ppc_store_msr(env, msr); 303 304 hreg_compute_mem_idx(env); 305 306 return 0; 307 } 308 309 static bool fpu_needed(void *opaque) 310 { 311 PowerPCCPU *cpu = opaque; 312 313 return (cpu->env.insns_flags & PPC_FLOAT); 314 } 315 316 static const VMStateDescription vmstate_fpu = { 317 .name = "cpu/fpu", 318 .version_id = 1, 319 .minimum_version_id = 1, 320 .needed = fpu_needed, 321 .fields = (VMStateField[]) { 322 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 323 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 324 VMSTATE_END_OF_LIST() 325 }, 326 }; 327 328 static bool altivec_needed(void *opaque) 329 { 330 PowerPCCPU *cpu = opaque; 331 332 return (cpu->env.insns_flags & PPC_ALTIVEC); 333 } 334 335 static const VMStateDescription vmstate_altivec = { 336 .name = "cpu/altivec", 337 .version_id = 1, 338 .minimum_version_id = 1, 339 .needed = altivec_needed, 340 .fields = (VMStateField[]) { 341 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 342 VMSTATE_UINT32(env.vscr, PowerPCCPU), 343 VMSTATE_END_OF_LIST() 344 }, 345 }; 346 347 static bool vsx_needed(void *opaque) 348 { 349 PowerPCCPU *cpu = opaque; 350 351 return (cpu->env.insns_flags2 & PPC2_VSX); 352 } 353 354 static const VMStateDescription vmstate_vsx = { 355 .name = "cpu/vsx", 356 .version_id = 1, 357 .minimum_version_id = 1, 358 .needed = vsx_needed, 359 .fields = (VMStateField[]) { 360 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 361 VMSTATE_END_OF_LIST() 362 }, 363 }; 364 365 #ifdef TARGET_PPC64 366 /* Transactional memory state */ 367 static bool tm_needed(void *opaque) 368 { 369 PowerPCCPU *cpu = opaque; 370 CPUPPCState *env = &cpu->env; 371 return msr_ts; 372 } 373 374 static const VMStateDescription vmstate_tm = { 375 .name = "cpu/tm", 376 .version_id = 1, 377 .minimum_version_id = 1, 378 .minimum_version_id_old = 1, 379 .needed = tm_needed, 380 .fields = (VMStateField []) { 381 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 382 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 383 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 384 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 385 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 386 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 387 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 388 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 389 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 390 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 391 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 392 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 393 VMSTATE_END_OF_LIST() 394 }, 395 }; 396 #endif 397 398 static bool sr_needed(void *opaque) 399 { 400 #ifdef TARGET_PPC64 401 PowerPCCPU *cpu = opaque; 402 403 return !(cpu->env.mmu_model & POWERPC_MMU_64); 404 #else 405 return true; 406 #endif 407 } 408 409 static const VMStateDescription vmstate_sr = { 410 .name = "cpu/sr", 411 .version_id = 1, 412 .minimum_version_id = 1, 413 .needed = sr_needed, 414 .fields = (VMStateField[]) { 415 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 416 VMSTATE_END_OF_LIST() 417 }, 418 }; 419 420 #ifdef TARGET_PPC64 421 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 422 { 423 ppc_slb_t *v = pv; 424 425 v->esid = qemu_get_be64(f); 426 v->vsid = qemu_get_be64(f); 427 428 return 0; 429 } 430 431 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 432 QJSON *vmdesc) 433 { 434 ppc_slb_t *v = pv; 435 436 qemu_put_be64(f, v->esid); 437 qemu_put_be64(f, v->vsid); 438 return 0; 439 } 440 441 static const VMStateInfo vmstate_info_slbe = { 442 .name = "slbe", 443 .get = get_slbe, 444 .put = put_slbe, 445 }; 446 447 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 448 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 449 450 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 451 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 452 453 static bool slb_needed(void *opaque) 454 { 455 PowerPCCPU *cpu = opaque; 456 457 /* We don't support any of the old segment table based 64-bit CPUs */ 458 return (cpu->env.mmu_model & POWERPC_MMU_64); 459 } 460 461 static int slb_post_load(void *opaque, int version_id) 462 { 463 PowerPCCPU *cpu = opaque; 464 CPUPPCState *env = &cpu->env; 465 int i; 466 467 /* We've pulled in the raw esid and vsid values from the migration 468 * stream, but we need to recompute the page size pointers */ 469 for (i = 0; i < env->slb_nr; i++) { 470 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 471 /* Migration source had bad values in its SLB */ 472 return -1; 473 } 474 } 475 476 return 0; 477 } 478 479 static const VMStateDescription vmstate_slb = { 480 .name = "cpu/slb", 481 .version_id = 1, 482 .minimum_version_id = 1, 483 .needed = slb_needed, 484 .post_load = slb_post_load, 485 .fields = (VMStateField[]) { 486 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), 487 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 488 VMSTATE_END_OF_LIST() 489 } 490 }; 491 #endif /* TARGET_PPC64 */ 492 493 static const VMStateDescription vmstate_tlb6xx_entry = { 494 .name = "cpu/tlb6xx_entry", 495 .version_id = 1, 496 .minimum_version_id = 1, 497 .fields = (VMStateField[]) { 498 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 499 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 500 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 501 VMSTATE_END_OF_LIST() 502 }, 503 }; 504 505 static bool tlb6xx_needed(void *opaque) 506 { 507 PowerPCCPU *cpu = opaque; 508 CPUPPCState *env = &cpu->env; 509 510 return env->nb_tlb && (env->tlb_type == TLB_6XX); 511 } 512 513 static const VMStateDescription vmstate_tlb6xx = { 514 .name = "cpu/tlb6xx", 515 .version_id = 1, 516 .minimum_version_id = 1, 517 .needed = tlb6xx_needed, 518 .fields = (VMStateField[]) { 519 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 520 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 521 env.nb_tlb, 522 vmstate_tlb6xx_entry, 523 ppc6xx_tlb_t), 524 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 525 VMSTATE_END_OF_LIST() 526 } 527 }; 528 529 static const VMStateDescription vmstate_tlbemb_entry = { 530 .name = "cpu/tlbemb_entry", 531 .version_id = 1, 532 .minimum_version_id = 1, 533 .fields = (VMStateField[]) { 534 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 535 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 536 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 537 VMSTATE_UINTTL(size, ppcemb_tlb_t), 538 VMSTATE_UINT32(prot, ppcemb_tlb_t), 539 VMSTATE_UINT32(attr, ppcemb_tlb_t), 540 VMSTATE_END_OF_LIST() 541 }, 542 }; 543 544 static bool tlbemb_needed(void *opaque) 545 { 546 PowerPCCPU *cpu = opaque; 547 CPUPPCState *env = &cpu->env; 548 549 return env->nb_tlb && (env->tlb_type == TLB_EMB); 550 } 551 552 static bool pbr403_needed(void *opaque) 553 { 554 PowerPCCPU *cpu = opaque; 555 uint32_t pvr = cpu->env.spr[SPR_PVR]; 556 557 return (pvr & 0xffff0000) == 0x00200000; 558 } 559 560 static const VMStateDescription vmstate_pbr403 = { 561 .name = "cpu/pbr403", 562 .version_id = 1, 563 .minimum_version_id = 1, 564 .needed = pbr403_needed, 565 .fields = (VMStateField[]) { 566 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 567 VMSTATE_END_OF_LIST() 568 }, 569 }; 570 571 static const VMStateDescription vmstate_tlbemb = { 572 .name = "cpu/tlb6xx", 573 .version_id = 1, 574 .minimum_version_id = 1, 575 .needed = tlbemb_needed, 576 .fields = (VMStateField[]) { 577 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 578 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 579 env.nb_tlb, 580 vmstate_tlbemb_entry, 581 ppcemb_tlb_t), 582 /* 403 protection registers */ 583 VMSTATE_END_OF_LIST() 584 }, 585 .subsections = (const VMStateDescription*[]) { 586 &vmstate_pbr403, 587 NULL 588 } 589 }; 590 591 static const VMStateDescription vmstate_tlbmas_entry = { 592 .name = "cpu/tlbmas_entry", 593 .version_id = 1, 594 .minimum_version_id = 1, 595 .fields = (VMStateField[]) { 596 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 597 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 598 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 599 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 600 VMSTATE_END_OF_LIST() 601 }, 602 }; 603 604 static bool tlbmas_needed(void *opaque) 605 { 606 PowerPCCPU *cpu = opaque; 607 CPUPPCState *env = &cpu->env; 608 609 return env->nb_tlb && (env->tlb_type == TLB_MAS); 610 } 611 612 static const VMStateDescription vmstate_tlbmas = { 613 .name = "cpu/tlbmas", 614 .version_id = 1, 615 .minimum_version_id = 1, 616 .needed = tlbmas_needed, 617 .fields = (VMStateField[]) { 618 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 619 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 620 env.nb_tlb, 621 vmstate_tlbmas_entry, 622 ppcmas_tlb_t), 623 VMSTATE_END_OF_LIST() 624 } 625 }; 626 627 static bool compat_needed(void *opaque) 628 { 629 PowerPCCPU *cpu = opaque; 630 631 assert(!(cpu->compat_pvr && !cpu->vhyp)); 632 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 633 } 634 635 static const VMStateDescription vmstate_compat = { 636 .name = "cpu/compat", 637 .version_id = 1, 638 .minimum_version_id = 1, 639 .needed = compat_needed, 640 .fields = (VMStateField[]) { 641 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 642 VMSTATE_END_OF_LIST() 643 } 644 }; 645 646 const VMStateDescription vmstate_ppc_cpu = { 647 .name = "cpu", 648 .version_id = 5, 649 .minimum_version_id = 5, 650 .minimum_version_id_old = 4, 651 .load_state_old = cpu_load_old, 652 .pre_save = cpu_pre_save, 653 .post_load = cpu_post_load, 654 .fields = (VMStateField[]) { 655 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 656 657 /* User mode architected state */ 658 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 659 #if !defined(TARGET_PPC64) 660 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 661 #endif 662 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 663 VMSTATE_UINTTL(env.nip, PowerPCCPU), 664 665 /* SPRs */ 666 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 667 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 668 669 /* Reservation */ 670 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 671 672 /* Supervisor mode architected state */ 673 VMSTATE_UINTTL(env.msr, PowerPCCPU), 674 675 /* Internal state */ 676 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 677 /* FIXME: access_type? */ 678 679 /* Sanity checking */ 680 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 681 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 682 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 683 cpu_pre_2_8_migration), 684 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 685 VMSTATE_END_OF_LIST() 686 }, 687 .subsections = (const VMStateDescription*[]) { 688 &vmstate_fpu, 689 &vmstate_altivec, 690 &vmstate_vsx, 691 &vmstate_sr, 692 #ifdef TARGET_PPC64 693 &vmstate_tm, 694 &vmstate_slb, 695 #endif /* TARGET_PPC64 */ 696 &vmstate_tlb6xx, 697 &vmstate_tlbemb, 698 &vmstate_tlbmas, 699 &vmstate_compat, 700 NULL 701 } 702 }; 703