1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 13 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 14 { 15 PowerPCCPU *cpu = opaque; 16 CPUPPCState *env = &cpu->env; 17 unsigned int i, j; 18 target_ulong sdr1; 19 uint32_t fpscr; 20 target_ulong xer; 21 22 for (i = 0; i < 32; i++) 23 qemu_get_betls(f, &env->gpr[i]); 24 #if !defined(TARGET_PPC64) 25 for (i = 0; i < 32; i++) 26 qemu_get_betls(f, &env->gprh[i]); 27 #endif 28 qemu_get_betls(f, &env->lr); 29 qemu_get_betls(f, &env->ctr); 30 for (i = 0; i < 8; i++) 31 qemu_get_be32s(f, &env->crf[i]); 32 qemu_get_betls(f, &xer); 33 cpu_write_xer(env, xer); 34 qemu_get_betls(f, &env->reserve_addr); 35 qemu_get_betls(f, &env->msr); 36 for (i = 0; i < 4; i++) 37 qemu_get_betls(f, &env->tgpr[i]); 38 for (i = 0; i < 32; i++) { 39 union { 40 float64 d; 41 uint64_t l; 42 } u; 43 u.l = qemu_get_be64(f); 44 env->fpr[i] = u.d; 45 } 46 qemu_get_be32s(f, &fpscr); 47 env->fpscr = fpscr; 48 qemu_get_sbe32s(f, &env->access_type); 49 #if defined(TARGET_PPC64) 50 qemu_get_betls(f, &env->spr[SPR_ASR]); 51 qemu_get_sbe32s(f, &env->slb_nr); 52 #endif 53 qemu_get_betls(f, &sdr1); 54 for (i = 0; i < 32; i++) 55 qemu_get_betls(f, &env->sr[i]); 56 for (i = 0; i < 2; i++) 57 for (j = 0; j < 8; j++) 58 qemu_get_betls(f, &env->DBAT[i][j]); 59 for (i = 0; i < 2; i++) 60 for (j = 0; j < 8; j++) 61 qemu_get_betls(f, &env->IBAT[i][j]); 62 qemu_get_sbe32s(f, &env->nb_tlb); 63 qemu_get_sbe32s(f, &env->tlb_per_way); 64 qemu_get_sbe32s(f, &env->nb_ways); 65 qemu_get_sbe32s(f, &env->last_way); 66 qemu_get_sbe32s(f, &env->id_tlbs); 67 qemu_get_sbe32s(f, &env->nb_pids); 68 if (env->tlb.tlb6) { 69 // XXX assumes 6xx 70 for (i = 0; i < env->nb_tlb; i++) { 71 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 72 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 73 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 74 } 75 } 76 for (i = 0; i < 4; i++) 77 qemu_get_betls(f, &env->pb[i]); 78 for (i = 0; i < 1024; i++) 79 qemu_get_betls(f, &env->spr[i]); 80 if (!cpu->vhyp) { 81 ppc_store_sdr1(env, sdr1); 82 } 83 qemu_get_be32s(f, &env->vscr); 84 qemu_get_be64s(f, &env->spe_acc); 85 qemu_get_be32s(f, &env->spe_fscr); 86 qemu_get_betls(f, &env->msr_mask); 87 qemu_get_be32s(f, &env->flags); 88 qemu_get_sbe32s(f, &env->error_code); 89 qemu_get_be32s(f, &env->pending_interrupts); 90 qemu_get_be32s(f, &env->irq_input_state); 91 for (i = 0; i < POWERPC_EXCP_NB; i++) 92 qemu_get_betls(f, &env->excp_vectors[i]); 93 qemu_get_betls(f, &env->excp_prefix); 94 qemu_get_betls(f, &env->ivor_mask); 95 qemu_get_betls(f, &env->ivpr_mask); 96 qemu_get_betls(f, &env->hreset_vector); 97 qemu_get_betls(f, &env->nip); 98 qemu_get_betls(f, &env->hflags); 99 qemu_get_betls(f, &env->hflags_nmsr); 100 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 101 qemu_get_sbe32(f); /* Discard unused power_mode */ 102 103 /* Recompute mmu indices */ 104 hreg_compute_mem_idx(env); 105 106 return 0; 107 } 108 109 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 110 { 111 ppc_avr_t *v = pv; 112 113 v->u64[0] = qemu_get_be64(f); 114 v->u64[1] = qemu_get_be64(f); 115 116 return 0; 117 } 118 119 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 120 QJSON *vmdesc) 121 { 122 ppc_avr_t *v = pv; 123 124 qemu_put_be64(f, v->u64[0]); 125 qemu_put_be64(f, v->u64[1]); 126 return 0; 127 } 128 129 static const VMStateInfo vmstate_info_avr = { 130 .name = "avr", 131 .get = get_avr, 132 .put = put_avr, 133 }; 134 135 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 136 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 137 138 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 139 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 140 141 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 142 { 143 PowerPCCPU *cpu = opaque; 144 145 return cpu->pre_2_8_migration; 146 } 147 148 static void cpu_pre_save(void *opaque) 149 { 150 PowerPCCPU *cpu = opaque; 151 CPUPPCState *env = &cpu->env; 152 int i; 153 uint64_t insns_compat_mask = 154 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 155 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 156 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 157 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 158 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 159 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 160 | PPC_64B | PPC_64BX | PPC_ALTIVEC 161 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 162 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 163 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 164 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 165 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 166 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 167 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 168 169 env->spr[SPR_LR] = env->lr; 170 env->spr[SPR_CTR] = env->ctr; 171 env->spr[SPR_XER] = cpu_read_xer(env); 172 #if defined(TARGET_PPC64) 173 env->spr[SPR_CFAR] = env->cfar; 174 #endif 175 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 176 177 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 178 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 179 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 180 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 181 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 182 } 183 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 184 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 185 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 186 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 187 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 188 } 189 190 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 191 if (cpu->pre_2_8_migration) { 192 cpu->mig_msr_mask = env->msr_mask; 193 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 194 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 195 cpu->mig_nb_BATs = env->nb_BATs; 196 } 197 } 198 199 /* 200 * Determine if a given PVR is a "close enough" match to the CPU 201 * object. For TCG and KVM PR it would probably be sufficient to 202 * require an exact PVR match. However for KVM HV the user is 203 * restricted to a PVR exactly matching the host CPU. The correct way 204 * to handle this is to put the guest into an architected 205 * compatibility mode. However, to allow a more forgiving transition 206 * and migration from before this was widely done, we allow migration 207 * between sufficiently similar PVRs, as determined by the CPU class's 208 * pvr_match() hook. 209 */ 210 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 211 { 212 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 213 214 if (pvr == pcc->pvr) { 215 return true; 216 } 217 return pcc->pvr_match(pcc, pvr); 218 } 219 220 static int cpu_post_load(void *opaque, int version_id) 221 { 222 PowerPCCPU *cpu = opaque; 223 CPUPPCState *env = &cpu->env; 224 int i; 225 target_ulong msr; 226 227 /* 228 * If we're operating in compat mode, we should be ok as long as 229 * the destination supports the same compatiblity mode. 230 * 231 * Otherwise, however, we require that the destination has exactly 232 * the same CPU model as the source. 233 */ 234 235 #if defined(TARGET_PPC64) 236 if (cpu->compat_pvr) { 237 Error *local_err = NULL; 238 239 ppc_set_compat(cpu, cpu->compat_pvr, &local_err); 240 if (local_err) { 241 error_report_err(local_err); 242 error_free(local_err); 243 return -1; 244 } 245 } else 246 #endif 247 { 248 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 249 return -1; 250 } 251 } 252 253 env->lr = env->spr[SPR_LR]; 254 env->ctr = env->spr[SPR_CTR]; 255 cpu_write_xer(env, env->spr[SPR_XER]); 256 #if defined(TARGET_PPC64) 257 env->cfar = env->spr[SPR_CFAR]; 258 #endif 259 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 260 261 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 262 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 263 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 264 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 265 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 266 } 267 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 268 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 269 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 270 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 271 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 272 } 273 274 if (!cpu->vhyp) { 275 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 276 } 277 278 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 279 msr = env->msr; 280 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 281 ppc_store_msr(env, msr); 282 283 hreg_compute_mem_idx(env); 284 285 return 0; 286 } 287 288 static bool fpu_needed(void *opaque) 289 { 290 PowerPCCPU *cpu = opaque; 291 292 return (cpu->env.insns_flags & PPC_FLOAT); 293 } 294 295 static const VMStateDescription vmstate_fpu = { 296 .name = "cpu/fpu", 297 .version_id = 1, 298 .minimum_version_id = 1, 299 .needed = fpu_needed, 300 .fields = (VMStateField[]) { 301 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 302 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 303 VMSTATE_END_OF_LIST() 304 }, 305 }; 306 307 static bool altivec_needed(void *opaque) 308 { 309 PowerPCCPU *cpu = opaque; 310 311 return (cpu->env.insns_flags & PPC_ALTIVEC); 312 } 313 314 static const VMStateDescription vmstate_altivec = { 315 .name = "cpu/altivec", 316 .version_id = 1, 317 .minimum_version_id = 1, 318 .needed = altivec_needed, 319 .fields = (VMStateField[]) { 320 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 321 VMSTATE_UINT32(env.vscr, PowerPCCPU), 322 VMSTATE_END_OF_LIST() 323 }, 324 }; 325 326 static bool vsx_needed(void *opaque) 327 { 328 PowerPCCPU *cpu = opaque; 329 330 return (cpu->env.insns_flags2 & PPC2_VSX); 331 } 332 333 static const VMStateDescription vmstate_vsx = { 334 .name = "cpu/vsx", 335 .version_id = 1, 336 .minimum_version_id = 1, 337 .needed = vsx_needed, 338 .fields = (VMStateField[]) { 339 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 340 VMSTATE_END_OF_LIST() 341 }, 342 }; 343 344 #ifdef TARGET_PPC64 345 /* Transactional memory state */ 346 static bool tm_needed(void *opaque) 347 { 348 PowerPCCPU *cpu = opaque; 349 CPUPPCState *env = &cpu->env; 350 return msr_ts; 351 } 352 353 static const VMStateDescription vmstate_tm = { 354 .name = "cpu/tm", 355 .version_id = 1, 356 .minimum_version_id = 1, 357 .minimum_version_id_old = 1, 358 .needed = tm_needed, 359 .fields = (VMStateField []) { 360 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 361 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 362 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 363 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 364 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 365 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 366 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 367 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 368 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 369 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 370 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 371 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 372 VMSTATE_END_OF_LIST() 373 }, 374 }; 375 #endif 376 377 static bool sr_needed(void *opaque) 378 { 379 #ifdef TARGET_PPC64 380 PowerPCCPU *cpu = opaque; 381 382 return !(cpu->env.mmu_model & POWERPC_MMU_64); 383 #else 384 return true; 385 #endif 386 } 387 388 static const VMStateDescription vmstate_sr = { 389 .name = "cpu/sr", 390 .version_id = 1, 391 .minimum_version_id = 1, 392 .needed = sr_needed, 393 .fields = (VMStateField[]) { 394 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 395 VMSTATE_END_OF_LIST() 396 }, 397 }; 398 399 #ifdef TARGET_PPC64 400 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 401 { 402 ppc_slb_t *v = pv; 403 404 v->esid = qemu_get_be64(f); 405 v->vsid = qemu_get_be64(f); 406 407 return 0; 408 } 409 410 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 411 QJSON *vmdesc) 412 { 413 ppc_slb_t *v = pv; 414 415 qemu_put_be64(f, v->esid); 416 qemu_put_be64(f, v->vsid); 417 return 0; 418 } 419 420 static const VMStateInfo vmstate_info_slbe = { 421 .name = "slbe", 422 .get = get_slbe, 423 .put = put_slbe, 424 }; 425 426 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 427 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 428 429 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 430 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 431 432 static bool slb_needed(void *opaque) 433 { 434 PowerPCCPU *cpu = opaque; 435 436 /* We don't support any of the old segment table based 64-bit CPUs */ 437 return (cpu->env.mmu_model & POWERPC_MMU_64); 438 } 439 440 static int slb_post_load(void *opaque, int version_id) 441 { 442 PowerPCCPU *cpu = opaque; 443 CPUPPCState *env = &cpu->env; 444 int i; 445 446 /* We've pulled in the raw esid and vsid values from the migration 447 * stream, but we need to recompute the page size pointers */ 448 for (i = 0; i < env->slb_nr; i++) { 449 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 450 /* Migration source had bad values in its SLB */ 451 return -1; 452 } 453 } 454 455 return 0; 456 } 457 458 static const VMStateDescription vmstate_slb = { 459 .name = "cpu/slb", 460 .version_id = 1, 461 .minimum_version_id = 1, 462 .needed = slb_needed, 463 .post_load = slb_post_load, 464 .fields = (VMStateField[]) { 465 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), 466 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 467 VMSTATE_END_OF_LIST() 468 } 469 }; 470 #endif /* TARGET_PPC64 */ 471 472 static const VMStateDescription vmstate_tlb6xx_entry = { 473 .name = "cpu/tlb6xx_entry", 474 .version_id = 1, 475 .minimum_version_id = 1, 476 .fields = (VMStateField[]) { 477 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 478 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 479 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 480 VMSTATE_END_OF_LIST() 481 }, 482 }; 483 484 static bool tlb6xx_needed(void *opaque) 485 { 486 PowerPCCPU *cpu = opaque; 487 CPUPPCState *env = &cpu->env; 488 489 return env->nb_tlb && (env->tlb_type == TLB_6XX); 490 } 491 492 static const VMStateDescription vmstate_tlb6xx = { 493 .name = "cpu/tlb6xx", 494 .version_id = 1, 495 .minimum_version_id = 1, 496 .needed = tlb6xx_needed, 497 .fields = (VMStateField[]) { 498 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 499 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 500 env.nb_tlb, 501 vmstate_tlb6xx_entry, 502 ppc6xx_tlb_t), 503 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 504 VMSTATE_END_OF_LIST() 505 } 506 }; 507 508 static const VMStateDescription vmstate_tlbemb_entry = { 509 .name = "cpu/tlbemb_entry", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .fields = (VMStateField[]) { 513 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 514 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 515 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 516 VMSTATE_UINTTL(size, ppcemb_tlb_t), 517 VMSTATE_UINT32(prot, ppcemb_tlb_t), 518 VMSTATE_UINT32(attr, ppcemb_tlb_t), 519 VMSTATE_END_OF_LIST() 520 }, 521 }; 522 523 static bool tlbemb_needed(void *opaque) 524 { 525 PowerPCCPU *cpu = opaque; 526 CPUPPCState *env = &cpu->env; 527 528 return env->nb_tlb && (env->tlb_type == TLB_EMB); 529 } 530 531 static bool pbr403_needed(void *opaque) 532 { 533 PowerPCCPU *cpu = opaque; 534 uint32_t pvr = cpu->env.spr[SPR_PVR]; 535 536 return (pvr & 0xffff0000) == 0x00200000; 537 } 538 539 static const VMStateDescription vmstate_pbr403 = { 540 .name = "cpu/pbr403", 541 .version_id = 1, 542 .minimum_version_id = 1, 543 .needed = pbr403_needed, 544 .fields = (VMStateField[]) { 545 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 546 VMSTATE_END_OF_LIST() 547 }, 548 }; 549 550 static const VMStateDescription vmstate_tlbemb = { 551 .name = "cpu/tlb6xx", 552 .version_id = 1, 553 .minimum_version_id = 1, 554 .needed = tlbemb_needed, 555 .fields = (VMStateField[]) { 556 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 557 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 558 env.nb_tlb, 559 vmstate_tlbemb_entry, 560 ppcemb_tlb_t), 561 /* 403 protection registers */ 562 VMSTATE_END_OF_LIST() 563 }, 564 .subsections = (const VMStateDescription*[]) { 565 &vmstate_pbr403, 566 NULL 567 } 568 }; 569 570 static const VMStateDescription vmstate_tlbmas_entry = { 571 .name = "cpu/tlbmas_entry", 572 .version_id = 1, 573 .minimum_version_id = 1, 574 .fields = (VMStateField[]) { 575 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 576 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 577 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 578 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 579 VMSTATE_END_OF_LIST() 580 }, 581 }; 582 583 static bool tlbmas_needed(void *opaque) 584 { 585 PowerPCCPU *cpu = opaque; 586 CPUPPCState *env = &cpu->env; 587 588 return env->nb_tlb && (env->tlb_type == TLB_MAS); 589 } 590 591 static const VMStateDescription vmstate_tlbmas = { 592 .name = "cpu/tlbmas", 593 .version_id = 1, 594 .minimum_version_id = 1, 595 .needed = tlbmas_needed, 596 .fields = (VMStateField[]) { 597 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 598 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 599 env.nb_tlb, 600 vmstate_tlbmas_entry, 601 ppcmas_tlb_t), 602 VMSTATE_END_OF_LIST() 603 } 604 }; 605 606 static bool compat_needed(void *opaque) 607 { 608 PowerPCCPU *cpu = opaque; 609 610 assert(!(cpu->compat_pvr && !cpu->vhyp)); 611 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 612 } 613 614 static const VMStateDescription vmstate_compat = { 615 .name = "cpu/compat", 616 .version_id = 1, 617 .minimum_version_id = 1, 618 .needed = compat_needed, 619 .fields = (VMStateField[]) { 620 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 621 VMSTATE_END_OF_LIST() 622 } 623 }; 624 625 const VMStateDescription vmstate_ppc_cpu = { 626 .name = "cpu", 627 .version_id = 5, 628 .minimum_version_id = 5, 629 .minimum_version_id_old = 4, 630 .load_state_old = cpu_load_old, 631 .pre_save = cpu_pre_save, 632 .post_load = cpu_post_load, 633 .fields = (VMStateField[]) { 634 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 635 636 /* User mode architected state */ 637 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 638 #if !defined(TARGET_PPC64) 639 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 640 #endif 641 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 642 VMSTATE_UINTTL(env.nip, PowerPCCPU), 643 644 /* SPRs */ 645 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 646 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 647 648 /* Reservation */ 649 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 650 651 /* Supervisor mode architected state */ 652 VMSTATE_UINTTL(env.msr, PowerPCCPU), 653 654 /* Internal state */ 655 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 656 /* FIXME: access_type? */ 657 658 /* Sanity checking */ 659 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 660 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 661 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 662 cpu_pre_2_8_migration), 663 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 664 VMSTATE_END_OF_LIST() 665 }, 666 .subsections = (const VMStateDescription*[]) { 667 &vmstate_fpu, 668 &vmstate_altivec, 669 &vmstate_vsx, 670 &vmstate_sr, 671 #ifdef TARGET_PPC64 672 &vmstate_tm, 673 &vmstate_slb, 674 #endif /* TARGET_PPC64 */ 675 &vmstate_tlb6xx, 676 &vmstate_tlbemb, 677 &vmstate_tlbmas, 678 &vmstate_compat, 679 NULL 680 } 681 }; 682