1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 12 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 13 { 14 PowerPCCPU *cpu = opaque; 15 CPUPPCState *env = &cpu->env; 16 unsigned int i, j; 17 target_ulong sdr1; 18 uint32_t fpscr; 19 target_ulong xer; 20 21 for (i = 0; i < 32; i++) 22 qemu_get_betls(f, &env->gpr[i]); 23 #if !defined(TARGET_PPC64) 24 for (i = 0; i < 32; i++) 25 qemu_get_betls(f, &env->gprh[i]); 26 #endif 27 qemu_get_betls(f, &env->lr); 28 qemu_get_betls(f, &env->ctr); 29 for (i = 0; i < 8; i++) 30 qemu_get_be32s(f, &env->crf[i]); 31 qemu_get_betls(f, &xer); 32 cpu_write_xer(env, xer); 33 qemu_get_betls(f, &env->reserve_addr); 34 qemu_get_betls(f, &env->msr); 35 for (i = 0; i < 4; i++) 36 qemu_get_betls(f, &env->tgpr[i]); 37 for (i = 0; i < 32; i++) { 38 union { 39 float64 d; 40 uint64_t l; 41 } u; 42 u.l = qemu_get_be64(f); 43 env->fpr[i] = u.d; 44 } 45 qemu_get_be32s(f, &fpscr); 46 env->fpscr = fpscr; 47 qemu_get_sbe32s(f, &env->access_type); 48 #if defined(TARGET_PPC64) 49 qemu_get_betls(f, &env->spr[SPR_ASR]); 50 qemu_get_sbe32s(f, &env->slb_nr); 51 #endif 52 qemu_get_betls(f, &sdr1); 53 for (i = 0; i < 32; i++) 54 qemu_get_betls(f, &env->sr[i]); 55 for (i = 0; i < 2; i++) 56 for (j = 0; j < 8; j++) 57 qemu_get_betls(f, &env->DBAT[i][j]); 58 for (i = 0; i < 2; i++) 59 for (j = 0; j < 8; j++) 60 qemu_get_betls(f, &env->IBAT[i][j]); 61 qemu_get_sbe32s(f, &env->nb_tlb); 62 qemu_get_sbe32s(f, &env->tlb_per_way); 63 qemu_get_sbe32s(f, &env->nb_ways); 64 qemu_get_sbe32s(f, &env->last_way); 65 qemu_get_sbe32s(f, &env->id_tlbs); 66 qemu_get_sbe32s(f, &env->nb_pids); 67 if (env->tlb.tlb6) { 68 // XXX assumes 6xx 69 for (i = 0; i < env->nb_tlb; i++) { 70 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 71 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 72 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 73 } 74 } 75 for (i = 0; i < 4; i++) 76 qemu_get_betls(f, &env->pb[i]); 77 for (i = 0; i < 1024; i++) 78 qemu_get_betls(f, &env->spr[i]); 79 if (!env->external_htab) { 80 ppc_store_sdr1(env, sdr1); 81 } 82 qemu_get_be32s(f, &env->vscr); 83 qemu_get_be64s(f, &env->spe_acc); 84 qemu_get_be32s(f, &env->spe_fscr); 85 qemu_get_betls(f, &env->msr_mask); 86 qemu_get_be32s(f, &env->flags); 87 qemu_get_sbe32s(f, &env->error_code); 88 qemu_get_be32s(f, &env->pending_interrupts); 89 qemu_get_be32s(f, &env->irq_input_state); 90 for (i = 0; i < POWERPC_EXCP_NB; i++) 91 qemu_get_betls(f, &env->excp_vectors[i]); 92 qemu_get_betls(f, &env->excp_prefix); 93 qemu_get_betls(f, &env->ivor_mask); 94 qemu_get_betls(f, &env->ivpr_mask); 95 qemu_get_betls(f, &env->hreset_vector); 96 qemu_get_betls(f, &env->nip); 97 qemu_get_betls(f, &env->hflags); 98 qemu_get_betls(f, &env->hflags_nmsr); 99 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 100 qemu_get_sbe32(f); /* Discard unused power_mode */ 101 102 /* Recompute mmu indices */ 103 hreg_compute_mem_idx(env); 104 105 return 0; 106 } 107 108 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 109 { 110 ppc_avr_t *v = pv; 111 112 v->u64[0] = qemu_get_be64(f); 113 v->u64[1] = qemu_get_be64(f); 114 115 return 0; 116 } 117 118 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 119 QJSON *vmdesc) 120 { 121 ppc_avr_t *v = pv; 122 123 qemu_put_be64(f, v->u64[0]); 124 qemu_put_be64(f, v->u64[1]); 125 return 0; 126 } 127 128 static const VMStateInfo vmstate_info_avr = { 129 .name = "avr", 130 .get = get_avr, 131 .put = put_avr, 132 }; 133 134 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 135 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 136 137 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 138 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 139 140 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 141 { 142 PowerPCCPU *cpu = opaque; 143 144 return cpu->pre_2_8_migration; 145 } 146 147 static void cpu_pre_save(void *opaque) 148 { 149 PowerPCCPU *cpu = opaque; 150 CPUPPCState *env = &cpu->env; 151 int i; 152 uint64_t insns_compat_mask = 153 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 154 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 155 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 156 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 157 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 158 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 159 | PPC_64B | PPC_64BX | PPC_ALTIVEC 160 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 161 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 162 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 163 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 164 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 165 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 166 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 167 168 env->spr[SPR_LR] = env->lr; 169 env->spr[SPR_CTR] = env->ctr; 170 env->spr[SPR_XER] = cpu_read_xer(env); 171 #if defined(TARGET_PPC64) 172 env->spr[SPR_CFAR] = env->cfar; 173 #endif 174 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 175 176 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 177 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 178 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 179 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 180 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 181 } 182 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 183 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 184 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 185 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 186 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 187 } 188 189 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 190 if (cpu->pre_2_8_migration) { 191 cpu->mig_msr_mask = env->msr_mask; 192 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 193 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 194 cpu->mig_nb_BATs = env->nb_BATs; 195 } 196 } 197 198 static int cpu_post_load(void *opaque, int version_id) 199 { 200 PowerPCCPU *cpu = opaque; 201 CPUPPCState *env = &cpu->env; 202 int i; 203 target_ulong msr; 204 205 /* 206 * We always ignore the source PVR. The user or management 207 * software has to take care of running QEMU in a compatible mode. 208 */ 209 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 210 env->lr = env->spr[SPR_LR]; 211 env->ctr = env->spr[SPR_CTR]; 212 cpu_write_xer(env, env->spr[SPR_XER]); 213 #if defined(TARGET_PPC64) 214 env->cfar = env->spr[SPR_CFAR]; 215 #endif 216 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 217 218 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 219 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 220 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 221 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 222 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 223 } 224 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 225 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 226 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 227 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 228 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 229 } 230 231 if (!env->external_htab) { 232 /* Restore htab_base and htab_mask variables */ 233 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 234 } 235 236 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 237 msr = env->msr; 238 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 239 ppc_store_msr(env, msr); 240 241 hreg_compute_mem_idx(env); 242 243 return 0; 244 } 245 246 static bool fpu_needed(void *opaque) 247 { 248 PowerPCCPU *cpu = opaque; 249 250 return (cpu->env.insns_flags & PPC_FLOAT); 251 } 252 253 static const VMStateDescription vmstate_fpu = { 254 .name = "cpu/fpu", 255 .version_id = 1, 256 .minimum_version_id = 1, 257 .needed = fpu_needed, 258 .fields = (VMStateField[]) { 259 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 260 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 261 VMSTATE_END_OF_LIST() 262 }, 263 }; 264 265 static bool altivec_needed(void *opaque) 266 { 267 PowerPCCPU *cpu = opaque; 268 269 return (cpu->env.insns_flags & PPC_ALTIVEC); 270 } 271 272 static const VMStateDescription vmstate_altivec = { 273 .name = "cpu/altivec", 274 .version_id = 1, 275 .minimum_version_id = 1, 276 .needed = altivec_needed, 277 .fields = (VMStateField[]) { 278 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 279 VMSTATE_UINT32(env.vscr, PowerPCCPU), 280 VMSTATE_END_OF_LIST() 281 }, 282 }; 283 284 static bool vsx_needed(void *opaque) 285 { 286 PowerPCCPU *cpu = opaque; 287 288 return (cpu->env.insns_flags2 & PPC2_VSX); 289 } 290 291 static const VMStateDescription vmstate_vsx = { 292 .name = "cpu/vsx", 293 .version_id = 1, 294 .minimum_version_id = 1, 295 .needed = vsx_needed, 296 .fields = (VMStateField[]) { 297 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 298 VMSTATE_END_OF_LIST() 299 }, 300 }; 301 302 #ifdef TARGET_PPC64 303 /* Transactional memory state */ 304 static bool tm_needed(void *opaque) 305 { 306 PowerPCCPU *cpu = opaque; 307 CPUPPCState *env = &cpu->env; 308 return msr_ts; 309 } 310 311 static const VMStateDescription vmstate_tm = { 312 .name = "cpu/tm", 313 .version_id = 1, 314 .minimum_version_id = 1, 315 .minimum_version_id_old = 1, 316 .needed = tm_needed, 317 .fields = (VMStateField []) { 318 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 319 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 320 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 321 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 322 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 323 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 324 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 325 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 326 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 327 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 328 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 329 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 330 VMSTATE_END_OF_LIST() 331 }, 332 }; 333 #endif 334 335 static bool sr_needed(void *opaque) 336 { 337 #ifdef TARGET_PPC64 338 PowerPCCPU *cpu = opaque; 339 340 return !(cpu->env.mmu_model & POWERPC_MMU_64); 341 #else 342 return true; 343 #endif 344 } 345 346 static const VMStateDescription vmstate_sr = { 347 .name = "cpu/sr", 348 .version_id = 1, 349 .minimum_version_id = 1, 350 .needed = sr_needed, 351 .fields = (VMStateField[]) { 352 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 353 VMSTATE_END_OF_LIST() 354 }, 355 }; 356 357 #ifdef TARGET_PPC64 358 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 359 { 360 ppc_slb_t *v = pv; 361 362 v->esid = qemu_get_be64(f); 363 v->vsid = qemu_get_be64(f); 364 365 return 0; 366 } 367 368 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 369 QJSON *vmdesc) 370 { 371 ppc_slb_t *v = pv; 372 373 qemu_put_be64(f, v->esid); 374 qemu_put_be64(f, v->vsid); 375 return 0; 376 } 377 378 static const VMStateInfo vmstate_info_slbe = { 379 .name = "slbe", 380 .get = get_slbe, 381 .put = put_slbe, 382 }; 383 384 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 385 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 386 387 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 388 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 389 390 static bool slb_needed(void *opaque) 391 { 392 PowerPCCPU *cpu = opaque; 393 394 /* We don't support any of the old segment table based 64-bit CPUs */ 395 return (cpu->env.mmu_model & POWERPC_MMU_64); 396 } 397 398 static int slb_post_load(void *opaque, int version_id) 399 { 400 PowerPCCPU *cpu = opaque; 401 CPUPPCState *env = &cpu->env; 402 int i; 403 404 /* We've pulled in the raw esid and vsid values from the migration 405 * stream, but we need to recompute the page size pointers */ 406 for (i = 0; i < env->slb_nr; i++) { 407 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 408 /* Migration source had bad values in its SLB */ 409 return -1; 410 } 411 } 412 413 return 0; 414 } 415 416 static const VMStateDescription vmstate_slb = { 417 .name = "cpu/slb", 418 .version_id = 1, 419 .minimum_version_id = 1, 420 .needed = slb_needed, 421 .post_load = slb_post_load, 422 .fields = (VMStateField[]) { 423 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU), 424 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 425 VMSTATE_END_OF_LIST() 426 } 427 }; 428 #endif /* TARGET_PPC64 */ 429 430 static const VMStateDescription vmstate_tlb6xx_entry = { 431 .name = "cpu/tlb6xx_entry", 432 .version_id = 1, 433 .minimum_version_id = 1, 434 .fields = (VMStateField[]) { 435 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 436 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 437 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static bool tlb6xx_needed(void *opaque) 443 { 444 PowerPCCPU *cpu = opaque; 445 CPUPPCState *env = &cpu->env; 446 447 return env->nb_tlb && (env->tlb_type == TLB_6XX); 448 } 449 450 static const VMStateDescription vmstate_tlb6xx = { 451 .name = "cpu/tlb6xx", 452 .version_id = 1, 453 .minimum_version_id = 1, 454 .needed = tlb6xx_needed, 455 .fields = (VMStateField[]) { 456 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 457 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 458 env.nb_tlb, 459 vmstate_tlb6xx_entry, 460 ppc6xx_tlb_t), 461 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 462 VMSTATE_END_OF_LIST() 463 } 464 }; 465 466 static const VMStateDescription vmstate_tlbemb_entry = { 467 .name = "cpu/tlbemb_entry", 468 .version_id = 1, 469 .minimum_version_id = 1, 470 .fields = (VMStateField[]) { 471 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 472 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 473 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 474 VMSTATE_UINTTL(size, ppcemb_tlb_t), 475 VMSTATE_UINT32(prot, ppcemb_tlb_t), 476 VMSTATE_UINT32(attr, ppcemb_tlb_t), 477 VMSTATE_END_OF_LIST() 478 }, 479 }; 480 481 static bool tlbemb_needed(void *opaque) 482 { 483 PowerPCCPU *cpu = opaque; 484 CPUPPCState *env = &cpu->env; 485 486 return env->nb_tlb && (env->tlb_type == TLB_EMB); 487 } 488 489 static bool pbr403_needed(void *opaque) 490 { 491 PowerPCCPU *cpu = opaque; 492 uint32_t pvr = cpu->env.spr[SPR_PVR]; 493 494 return (pvr & 0xffff0000) == 0x00200000; 495 } 496 497 static const VMStateDescription vmstate_pbr403 = { 498 .name = "cpu/pbr403", 499 .version_id = 1, 500 .minimum_version_id = 1, 501 .needed = pbr403_needed, 502 .fields = (VMStateField[]) { 503 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 504 VMSTATE_END_OF_LIST() 505 }, 506 }; 507 508 static const VMStateDescription vmstate_tlbemb = { 509 .name = "cpu/tlb6xx", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .needed = tlbemb_needed, 513 .fields = (VMStateField[]) { 514 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 515 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 516 env.nb_tlb, 517 vmstate_tlbemb_entry, 518 ppcemb_tlb_t), 519 /* 403 protection registers */ 520 VMSTATE_END_OF_LIST() 521 }, 522 .subsections = (const VMStateDescription*[]) { 523 &vmstate_pbr403, 524 NULL 525 } 526 }; 527 528 static const VMStateDescription vmstate_tlbmas_entry = { 529 .name = "cpu/tlbmas_entry", 530 .version_id = 1, 531 .minimum_version_id = 1, 532 .fields = (VMStateField[]) { 533 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 534 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 535 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 536 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 537 VMSTATE_END_OF_LIST() 538 }, 539 }; 540 541 static bool tlbmas_needed(void *opaque) 542 { 543 PowerPCCPU *cpu = opaque; 544 CPUPPCState *env = &cpu->env; 545 546 return env->nb_tlb && (env->tlb_type == TLB_MAS); 547 } 548 549 static const VMStateDescription vmstate_tlbmas = { 550 .name = "cpu/tlbmas", 551 .version_id = 1, 552 .minimum_version_id = 1, 553 .needed = tlbmas_needed, 554 .fields = (VMStateField[]) { 555 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 556 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 557 env.nb_tlb, 558 vmstate_tlbmas_entry, 559 ppcmas_tlb_t), 560 VMSTATE_END_OF_LIST() 561 } 562 }; 563 564 const VMStateDescription vmstate_ppc_cpu = { 565 .name = "cpu", 566 .version_id = 5, 567 .minimum_version_id = 5, 568 .minimum_version_id_old = 4, 569 .load_state_old = cpu_load_old, 570 .pre_save = cpu_pre_save, 571 .post_load = cpu_post_load, 572 .fields = (VMStateField[]) { 573 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 574 575 /* User mode architected state */ 576 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 577 #if !defined(TARGET_PPC64) 578 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 579 #endif 580 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 581 VMSTATE_UINTTL(env.nip, PowerPCCPU), 582 583 /* SPRs */ 584 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 585 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 586 587 /* Reservation */ 588 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 589 590 /* Supervisor mode architected state */ 591 VMSTATE_UINTTL(env.msr, PowerPCCPU), 592 593 /* Internal state */ 594 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 595 /* FIXME: access_type? */ 596 597 /* Sanity checking */ 598 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 599 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 600 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 601 cpu_pre_2_8_migration), 602 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 603 VMSTATE_END_OF_LIST() 604 }, 605 .subsections = (const VMStateDescription*[]) { 606 &vmstate_fpu, 607 &vmstate_altivec, 608 &vmstate_vsx, 609 &vmstate_sr, 610 #ifdef TARGET_PPC64 611 &vmstate_tm, 612 &vmstate_slb, 613 #endif /* TARGET_PPC64 */ 614 &vmstate_tlb6xx, 615 &vmstate_tlbemb, 616 &vmstate_tlbmas, 617 NULL 618 } 619 }; 620