1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 #include "kvm_ppc.h" 13 14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 15 { 16 PowerPCCPU *cpu = opaque; 17 CPUPPCState *env = &cpu->env; 18 unsigned int i, j; 19 target_ulong sdr1; 20 uint32_t fpscr; 21 target_ulong xer; 22 23 for (i = 0; i < 32; i++) 24 qemu_get_betls(f, &env->gpr[i]); 25 #if !defined(TARGET_PPC64) 26 for (i = 0; i < 32; i++) 27 qemu_get_betls(f, &env->gprh[i]); 28 #endif 29 qemu_get_betls(f, &env->lr); 30 qemu_get_betls(f, &env->ctr); 31 for (i = 0; i < 8; i++) 32 qemu_get_be32s(f, &env->crf[i]); 33 qemu_get_betls(f, &xer); 34 cpu_write_xer(env, xer); 35 qemu_get_betls(f, &env->reserve_addr); 36 qemu_get_betls(f, &env->msr); 37 for (i = 0; i < 4; i++) 38 qemu_get_betls(f, &env->tgpr[i]); 39 for (i = 0; i < 32; i++) { 40 union { 41 float64 d; 42 uint64_t l; 43 } u; 44 u.l = qemu_get_be64(f); 45 env->fpr[i] = u.d; 46 } 47 qemu_get_be32s(f, &fpscr); 48 env->fpscr = fpscr; 49 qemu_get_sbe32s(f, &env->access_type); 50 #if defined(TARGET_PPC64) 51 qemu_get_betls(f, &env->spr[SPR_ASR]); 52 qemu_get_sbe32s(f, &env->slb_nr); 53 #endif 54 qemu_get_betls(f, &sdr1); 55 for (i = 0; i < 32; i++) 56 qemu_get_betls(f, &env->sr[i]); 57 for (i = 0; i < 2; i++) 58 for (j = 0; j < 8; j++) 59 qemu_get_betls(f, &env->DBAT[i][j]); 60 for (i = 0; i < 2; i++) 61 for (j = 0; j < 8; j++) 62 qemu_get_betls(f, &env->IBAT[i][j]); 63 qemu_get_sbe32s(f, &env->nb_tlb); 64 qemu_get_sbe32s(f, &env->tlb_per_way); 65 qemu_get_sbe32s(f, &env->nb_ways); 66 qemu_get_sbe32s(f, &env->last_way); 67 qemu_get_sbe32s(f, &env->id_tlbs); 68 qemu_get_sbe32s(f, &env->nb_pids); 69 if (env->tlb.tlb6) { 70 // XXX assumes 6xx 71 for (i = 0; i < env->nb_tlb; i++) { 72 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 73 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 74 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 75 } 76 } 77 for (i = 0; i < 4; i++) 78 qemu_get_betls(f, &env->pb[i]); 79 for (i = 0; i < 1024; i++) 80 qemu_get_betls(f, &env->spr[i]); 81 if (!cpu->vhyp) { 82 ppc_store_sdr1(env, sdr1); 83 } 84 qemu_get_be32s(f, &env->vscr); 85 qemu_get_be64s(f, &env->spe_acc); 86 qemu_get_be32s(f, &env->spe_fscr); 87 qemu_get_betls(f, &env->msr_mask); 88 qemu_get_be32s(f, &env->flags); 89 qemu_get_sbe32s(f, &env->error_code); 90 qemu_get_be32s(f, &env->pending_interrupts); 91 qemu_get_be32s(f, &env->irq_input_state); 92 for (i = 0; i < POWERPC_EXCP_NB; i++) 93 qemu_get_betls(f, &env->excp_vectors[i]); 94 qemu_get_betls(f, &env->excp_prefix); 95 qemu_get_betls(f, &env->ivor_mask); 96 qemu_get_betls(f, &env->ivpr_mask); 97 qemu_get_betls(f, &env->hreset_vector); 98 qemu_get_betls(f, &env->nip); 99 qemu_get_betls(f, &env->hflags); 100 qemu_get_betls(f, &env->hflags_nmsr); 101 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 102 qemu_get_sbe32(f); /* Discard unused power_mode */ 103 104 /* Recompute mmu indices */ 105 hreg_compute_mem_idx(env); 106 107 return 0; 108 } 109 110 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 111 { 112 ppc_avr_t *v = pv; 113 114 v->u64[0] = qemu_get_be64(f); 115 v->u64[1] = qemu_get_be64(f); 116 117 return 0; 118 } 119 120 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 121 QJSON *vmdesc) 122 { 123 ppc_avr_t *v = pv; 124 125 qemu_put_be64(f, v->u64[0]); 126 qemu_put_be64(f, v->u64[1]); 127 return 0; 128 } 129 130 static const VMStateInfo vmstate_info_avr = { 131 .name = "avr", 132 .get = get_avr, 133 .put = put_avr, 134 }; 135 136 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 137 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 138 139 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 140 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 141 142 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 143 { 144 PowerPCCPU *cpu = opaque; 145 146 return cpu->pre_2_8_migration; 147 } 148 149 static int cpu_pre_save(void *opaque) 150 { 151 PowerPCCPU *cpu = opaque; 152 CPUPPCState *env = &cpu->env; 153 int i; 154 uint64_t insns_compat_mask = 155 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 156 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 157 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 158 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 159 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 160 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 161 | PPC_64B | PPC_64BX | PPC_ALTIVEC 162 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 163 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 164 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 165 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 166 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 167 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 168 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 169 170 env->spr[SPR_LR] = env->lr; 171 env->spr[SPR_CTR] = env->ctr; 172 env->spr[SPR_XER] = cpu_read_xer(env); 173 #if defined(TARGET_PPC64) 174 env->spr[SPR_CFAR] = env->cfar; 175 #endif 176 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 177 178 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 179 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 180 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 181 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 182 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 183 } 184 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 185 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 186 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 187 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 188 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 189 } 190 191 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 192 if (cpu->pre_2_8_migration) { 193 cpu->mig_msr_mask = env->msr_mask; 194 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 195 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 196 cpu->mig_nb_BATs = env->nb_BATs; 197 } 198 199 return 0; 200 } 201 202 /* 203 * Determine if a given PVR is a "close enough" match to the CPU 204 * object. For TCG and KVM PR it would probably be sufficient to 205 * require an exact PVR match. However for KVM HV the user is 206 * restricted to a PVR exactly matching the host CPU. The correct way 207 * to handle this is to put the guest into an architected 208 * compatibility mode. However, to allow a more forgiving transition 209 * and migration from before this was widely done, we allow migration 210 * between sufficiently similar PVRs, as determined by the CPU class's 211 * pvr_match() hook. 212 */ 213 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 214 { 215 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 216 217 if (pvr == pcc->pvr) { 218 return true; 219 } 220 return pcc->pvr_match(pcc, pvr); 221 } 222 223 static int cpu_post_load(void *opaque, int version_id) 224 { 225 PowerPCCPU *cpu = opaque; 226 CPUPPCState *env = &cpu->env; 227 int i; 228 target_ulong msr; 229 230 /* 231 * If we're operating in compat mode, we should be ok as long as 232 * the destination supports the same compatiblity mode. 233 * 234 * Otherwise, however, we require that the destination has exactly 235 * the same CPU model as the source. 236 */ 237 238 #if defined(TARGET_PPC64) 239 if (cpu->compat_pvr) { 240 Error *local_err = NULL; 241 242 ppc_set_compat(cpu, cpu->compat_pvr, &local_err); 243 if (local_err) { 244 error_report_err(local_err); 245 return -1; 246 } 247 } else 248 #endif 249 { 250 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 251 return -1; 252 } 253 } 254 255 /* 256 * If we're running with KVM HV, there is a chance that the guest 257 * is running with KVM HV and its kernel does not have the 258 * capability of dealing with a different PVR other than this 259 * exact host PVR in KVM_SET_SREGS. If that happens, the 260 * guest freezes after migration. 261 * 262 * The function kvmppc_pvr_workaround_required does this verification 263 * by first checking if the kernel has the cap, returning true immediately 264 * if that is the case. Otherwise, it checks if we're running in KVM PR. 265 * If the guest kernel does not have the cap and we're not running KVM-PR 266 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 267 * receive the PVR it expects as a workaround. 268 * 269 */ 270 #if defined(CONFIG_KVM) 271 if (kvmppc_pvr_workaround_required(cpu)) { 272 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 273 } 274 #endif 275 276 env->lr = env->spr[SPR_LR]; 277 env->ctr = env->spr[SPR_CTR]; 278 cpu_write_xer(env, env->spr[SPR_XER]); 279 #if defined(TARGET_PPC64) 280 env->cfar = env->spr[SPR_CFAR]; 281 #endif 282 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 283 284 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 285 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 286 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 287 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 288 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 289 } 290 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 291 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 292 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 293 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 294 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 295 } 296 297 if (!cpu->vhyp) { 298 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 299 } 300 301 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 302 msr = env->msr; 303 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 304 ppc_store_msr(env, msr); 305 306 hreg_compute_mem_idx(env); 307 308 return 0; 309 } 310 311 static bool fpu_needed(void *opaque) 312 { 313 PowerPCCPU *cpu = opaque; 314 315 return (cpu->env.insns_flags & PPC_FLOAT); 316 } 317 318 static const VMStateDescription vmstate_fpu = { 319 .name = "cpu/fpu", 320 .version_id = 1, 321 .minimum_version_id = 1, 322 .needed = fpu_needed, 323 .fields = (VMStateField[]) { 324 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 325 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 326 VMSTATE_END_OF_LIST() 327 }, 328 }; 329 330 static bool altivec_needed(void *opaque) 331 { 332 PowerPCCPU *cpu = opaque; 333 334 return (cpu->env.insns_flags & PPC_ALTIVEC); 335 } 336 337 static const VMStateDescription vmstate_altivec = { 338 .name = "cpu/altivec", 339 .version_id = 1, 340 .minimum_version_id = 1, 341 .needed = altivec_needed, 342 .fields = (VMStateField[]) { 343 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 344 VMSTATE_UINT32(env.vscr, PowerPCCPU), 345 VMSTATE_END_OF_LIST() 346 }, 347 }; 348 349 static bool vsx_needed(void *opaque) 350 { 351 PowerPCCPU *cpu = opaque; 352 353 return (cpu->env.insns_flags2 & PPC2_VSX); 354 } 355 356 static const VMStateDescription vmstate_vsx = { 357 .name = "cpu/vsx", 358 .version_id = 1, 359 .minimum_version_id = 1, 360 .needed = vsx_needed, 361 .fields = (VMStateField[]) { 362 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 363 VMSTATE_END_OF_LIST() 364 }, 365 }; 366 367 #ifdef TARGET_PPC64 368 /* Transactional memory state */ 369 static bool tm_needed(void *opaque) 370 { 371 PowerPCCPU *cpu = opaque; 372 CPUPPCState *env = &cpu->env; 373 return msr_ts; 374 } 375 376 static const VMStateDescription vmstate_tm = { 377 .name = "cpu/tm", 378 .version_id = 1, 379 .minimum_version_id = 1, 380 .minimum_version_id_old = 1, 381 .needed = tm_needed, 382 .fields = (VMStateField []) { 383 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 384 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 385 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 386 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 387 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 388 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 389 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 390 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 391 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 392 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 393 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 394 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 395 VMSTATE_END_OF_LIST() 396 }, 397 }; 398 #endif 399 400 static bool sr_needed(void *opaque) 401 { 402 #ifdef TARGET_PPC64 403 PowerPCCPU *cpu = opaque; 404 405 return !(cpu->env.mmu_model & POWERPC_MMU_64); 406 #else 407 return true; 408 #endif 409 } 410 411 static const VMStateDescription vmstate_sr = { 412 .name = "cpu/sr", 413 .version_id = 1, 414 .minimum_version_id = 1, 415 .needed = sr_needed, 416 .fields = (VMStateField[]) { 417 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 418 VMSTATE_END_OF_LIST() 419 }, 420 }; 421 422 #ifdef TARGET_PPC64 423 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 424 { 425 ppc_slb_t *v = pv; 426 427 v->esid = qemu_get_be64(f); 428 v->vsid = qemu_get_be64(f); 429 430 return 0; 431 } 432 433 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 434 QJSON *vmdesc) 435 { 436 ppc_slb_t *v = pv; 437 438 qemu_put_be64(f, v->esid); 439 qemu_put_be64(f, v->vsid); 440 return 0; 441 } 442 443 static const VMStateInfo vmstate_info_slbe = { 444 .name = "slbe", 445 .get = get_slbe, 446 .put = put_slbe, 447 }; 448 449 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 450 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 451 452 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 453 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 454 455 static bool slb_needed(void *opaque) 456 { 457 PowerPCCPU *cpu = opaque; 458 459 /* We don't support any of the old segment table based 64-bit CPUs */ 460 return (cpu->env.mmu_model & POWERPC_MMU_64); 461 } 462 463 static int slb_post_load(void *opaque, int version_id) 464 { 465 PowerPCCPU *cpu = opaque; 466 CPUPPCState *env = &cpu->env; 467 int i; 468 469 /* We've pulled in the raw esid and vsid values from the migration 470 * stream, but we need to recompute the page size pointers */ 471 for (i = 0; i < env->slb_nr; i++) { 472 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 473 /* Migration source had bad values in its SLB */ 474 return -1; 475 } 476 } 477 478 return 0; 479 } 480 481 static const VMStateDescription vmstate_slb = { 482 .name = "cpu/slb", 483 .version_id = 1, 484 .minimum_version_id = 1, 485 .needed = slb_needed, 486 .post_load = slb_post_load, 487 .fields = (VMStateField[]) { 488 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL), 489 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 490 VMSTATE_END_OF_LIST() 491 } 492 }; 493 #endif /* TARGET_PPC64 */ 494 495 static const VMStateDescription vmstate_tlb6xx_entry = { 496 .name = "cpu/tlb6xx_entry", 497 .version_id = 1, 498 .minimum_version_id = 1, 499 .fields = (VMStateField[]) { 500 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 501 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 502 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 503 VMSTATE_END_OF_LIST() 504 }, 505 }; 506 507 static bool tlb6xx_needed(void *opaque) 508 { 509 PowerPCCPU *cpu = opaque; 510 CPUPPCState *env = &cpu->env; 511 512 return env->nb_tlb && (env->tlb_type == TLB_6XX); 513 } 514 515 static const VMStateDescription vmstate_tlb6xx = { 516 .name = "cpu/tlb6xx", 517 .version_id = 1, 518 .minimum_version_id = 1, 519 .needed = tlb6xx_needed, 520 .fields = (VMStateField[]) { 521 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 522 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 523 env.nb_tlb, 524 vmstate_tlb6xx_entry, 525 ppc6xx_tlb_t), 526 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 527 VMSTATE_END_OF_LIST() 528 } 529 }; 530 531 static const VMStateDescription vmstate_tlbemb_entry = { 532 .name = "cpu/tlbemb_entry", 533 .version_id = 1, 534 .minimum_version_id = 1, 535 .fields = (VMStateField[]) { 536 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 537 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 538 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 539 VMSTATE_UINTTL(size, ppcemb_tlb_t), 540 VMSTATE_UINT32(prot, ppcemb_tlb_t), 541 VMSTATE_UINT32(attr, ppcemb_tlb_t), 542 VMSTATE_END_OF_LIST() 543 }, 544 }; 545 546 static bool tlbemb_needed(void *opaque) 547 { 548 PowerPCCPU *cpu = opaque; 549 CPUPPCState *env = &cpu->env; 550 551 return env->nb_tlb && (env->tlb_type == TLB_EMB); 552 } 553 554 static bool pbr403_needed(void *opaque) 555 { 556 PowerPCCPU *cpu = opaque; 557 uint32_t pvr = cpu->env.spr[SPR_PVR]; 558 559 return (pvr & 0xffff0000) == 0x00200000; 560 } 561 562 static const VMStateDescription vmstate_pbr403 = { 563 .name = "cpu/pbr403", 564 .version_id = 1, 565 .minimum_version_id = 1, 566 .needed = pbr403_needed, 567 .fields = (VMStateField[]) { 568 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 569 VMSTATE_END_OF_LIST() 570 }, 571 }; 572 573 static const VMStateDescription vmstate_tlbemb = { 574 .name = "cpu/tlb6xx", 575 .version_id = 1, 576 .minimum_version_id = 1, 577 .needed = tlbemb_needed, 578 .fields = (VMStateField[]) { 579 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 580 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 581 env.nb_tlb, 582 vmstate_tlbemb_entry, 583 ppcemb_tlb_t), 584 /* 403 protection registers */ 585 VMSTATE_END_OF_LIST() 586 }, 587 .subsections = (const VMStateDescription*[]) { 588 &vmstate_pbr403, 589 NULL 590 } 591 }; 592 593 static const VMStateDescription vmstate_tlbmas_entry = { 594 .name = "cpu/tlbmas_entry", 595 .version_id = 1, 596 .minimum_version_id = 1, 597 .fields = (VMStateField[]) { 598 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 599 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 600 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 601 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 602 VMSTATE_END_OF_LIST() 603 }, 604 }; 605 606 static bool tlbmas_needed(void *opaque) 607 { 608 PowerPCCPU *cpu = opaque; 609 CPUPPCState *env = &cpu->env; 610 611 return env->nb_tlb && (env->tlb_type == TLB_MAS); 612 } 613 614 static const VMStateDescription vmstate_tlbmas = { 615 .name = "cpu/tlbmas", 616 .version_id = 1, 617 .minimum_version_id = 1, 618 .needed = tlbmas_needed, 619 .fields = (VMStateField[]) { 620 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 621 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 622 env.nb_tlb, 623 vmstate_tlbmas_entry, 624 ppcmas_tlb_t), 625 VMSTATE_END_OF_LIST() 626 } 627 }; 628 629 static bool compat_needed(void *opaque) 630 { 631 PowerPCCPU *cpu = opaque; 632 633 assert(!(cpu->compat_pvr && !cpu->vhyp)); 634 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 635 } 636 637 static const VMStateDescription vmstate_compat = { 638 .name = "cpu/compat", 639 .version_id = 1, 640 .minimum_version_id = 1, 641 .needed = compat_needed, 642 .fields = (VMStateField[]) { 643 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 644 VMSTATE_END_OF_LIST() 645 } 646 }; 647 648 const VMStateDescription vmstate_ppc_cpu = { 649 .name = "cpu", 650 .version_id = 5, 651 .minimum_version_id = 5, 652 .minimum_version_id_old = 4, 653 .load_state_old = cpu_load_old, 654 .pre_save = cpu_pre_save, 655 .post_load = cpu_post_load, 656 .fields = (VMStateField[]) { 657 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 658 659 /* User mode architected state */ 660 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 661 #if !defined(TARGET_PPC64) 662 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 663 #endif 664 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 665 VMSTATE_UINTTL(env.nip, PowerPCCPU), 666 667 /* SPRs */ 668 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 669 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 670 671 /* Reservation */ 672 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 673 674 /* Supervisor mode architected state */ 675 VMSTATE_UINTTL(env.msr, PowerPCCPU), 676 677 /* Internal state */ 678 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 679 /* FIXME: access_type? */ 680 681 /* Sanity checking */ 682 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 683 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 684 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 685 cpu_pre_2_8_migration), 686 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 687 VMSTATE_END_OF_LIST() 688 }, 689 .subsections = (const VMStateDescription*[]) { 690 &vmstate_fpu, 691 &vmstate_altivec, 692 &vmstate_vsx, 693 &vmstate_sr, 694 #ifdef TARGET_PPC64 695 &vmstate_tm, 696 &vmstate_slb, 697 #endif /* TARGET_PPC64 */ 698 &vmstate_tlb6xx, 699 &vmstate_tlbemb, 700 &vmstate_tlbmas, 701 &vmstate_compat, 702 NULL 703 } 704 }; 705