1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 #include "kvm_ppc.h" 13 14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 15 { 16 PowerPCCPU *cpu = opaque; 17 CPUPPCState *env = &cpu->env; 18 unsigned int i, j; 19 target_ulong sdr1; 20 uint32_t fpscr; 21 #if defined(TARGET_PPC64) 22 int32_t slb_nr; 23 #endif 24 target_ulong xer; 25 26 for (i = 0; i < 32; i++) 27 qemu_get_betls(f, &env->gpr[i]); 28 #if !defined(TARGET_PPC64) 29 for (i = 0; i < 32; i++) 30 qemu_get_betls(f, &env->gprh[i]); 31 #endif 32 qemu_get_betls(f, &env->lr); 33 qemu_get_betls(f, &env->ctr); 34 for (i = 0; i < 8; i++) 35 qemu_get_be32s(f, &env->crf[i]); 36 qemu_get_betls(f, &xer); 37 cpu_write_xer(env, xer); 38 qemu_get_betls(f, &env->reserve_addr); 39 qemu_get_betls(f, &env->msr); 40 for (i = 0; i < 4; i++) 41 qemu_get_betls(f, &env->tgpr[i]); 42 for (i = 0; i < 32; i++) { 43 union { 44 float64 d; 45 uint64_t l; 46 } u; 47 u.l = qemu_get_be64(f); 48 env->fpr[i] = u.d; 49 } 50 qemu_get_be32s(f, &fpscr); 51 env->fpscr = fpscr; 52 qemu_get_sbe32s(f, &env->access_type); 53 #if defined(TARGET_PPC64) 54 qemu_get_betls(f, &env->spr[SPR_ASR]); 55 qemu_get_sbe32s(f, &slb_nr); 56 #endif 57 qemu_get_betls(f, &sdr1); 58 for (i = 0; i < 32; i++) 59 qemu_get_betls(f, &env->sr[i]); 60 for (i = 0; i < 2; i++) 61 for (j = 0; j < 8; j++) 62 qemu_get_betls(f, &env->DBAT[i][j]); 63 for (i = 0; i < 2; i++) 64 for (j = 0; j < 8; j++) 65 qemu_get_betls(f, &env->IBAT[i][j]); 66 qemu_get_sbe32s(f, &env->nb_tlb); 67 qemu_get_sbe32s(f, &env->tlb_per_way); 68 qemu_get_sbe32s(f, &env->nb_ways); 69 qemu_get_sbe32s(f, &env->last_way); 70 qemu_get_sbe32s(f, &env->id_tlbs); 71 qemu_get_sbe32s(f, &env->nb_pids); 72 if (env->tlb.tlb6) { 73 // XXX assumes 6xx 74 for (i = 0; i < env->nb_tlb; i++) { 75 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 76 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 77 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 78 } 79 } 80 for (i = 0; i < 4; i++) 81 qemu_get_betls(f, &env->pb[i]); 82 for (i = 0; i < 1024; i++) 83 qemu_get_betls(f, &env->spr[i]); 84 if (!cpu->vhyp) { 85 ppc_store_sdr1(env, sdr1); 86 } 87 qemu_get_be32s(f, &env->vscr); 88 qemu_get_be64s(f, &env->spe_acc); 89 qemu_get_be32s(f, &env->spe_fscr); 90 qemu_get_betls(f, &env->msr_mask); 91 qemu_get_be32s(f, &env->flags); 92 qemu_get_sbe32s(f, &env->error_code); 93 qemu_get_be32s(f, &env->pending_interrupts); 94 qemu_get_be32s(f, &env->irq_input_state); 95 for (i = 0; i < POWERPC_EXCP_NB; i++) 96 qemu_get_betls(f, &env->excp_vectors[i]); 97 qemu_get_betls(f, &env->excp_prefix); 98 qemu_get_betls(f, &env->ivor_mask); 99 qemu_get_betls(f, &env->ivpr_mask); 100 qemu_get_betls(f, &env->hreset_vector); 101 qemu_get_betls(f, &env->nip); 102 qemu_get_betls(f, &env->hflags); 103 qemu_get_betls(f, &env->hflags_nmsr); 104 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 105 qemu_get_sbe32(f); /* Discard unused power_mode */ 106 107 /* Recompute mmu indices */ 108 hreg_compute_mem_idx(env); 109 110 return 0; 111 } 112 113 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 114 { 115 ppc_avr_t *v = pv; 116 117 v->u64[0] = qemu_get_be64(f); 118 v->u64[1] = qemu_get_be64(f); 119 120 return 0; 121 } 122 123 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 124 QJSON *vmdesc) 125 { 126 ppc_avr_t *v = pv; 127 128 qemu_put_be64(f, v->u64[0]); 129 qemu_put_be64(f, v->u64[1]); 130 return 0; 131 } 132 133 static const VMStateInfo vmstate_info_avr = { 134 .name = "avr", 135 .get = get_avr, 136 .put = put_avr, 137 }; 138 139 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 140 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 141 142 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 143 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 144 145 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 146 { 147 PowerPCCPU *cpu = opaque; 148 149 return cpu->pre_2_8_migration; 150 } 151 152 #if defined(TARGET_PPC64) 153 static bool cpu_pre_3_0_migration(void *opaque, int version_id) 154 { 155 PowerPCCPU *cpu = opaque; 156 157 return cpu->pre_3_0_migration; 158 } 159 #endif 160 161 static int cpu_pre_save(void *opaque) 162 { 163 PowerPCCPU *cpu = opaque; 164 CPUPPCState *env = &cpu->env; 165 int i; 166 uint64_t insns_compat_mask = 167 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 168 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 169 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 170 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 171 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 172 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 173 | PPC_64B | PPC_64BX | PPC_ALTIVEC 174 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 175 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 176 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 177 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 178 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 179 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 180 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 181 182 env->spr[SPR_LR] = env->lr; 183 env->spr[SPR_CTR] = env->ctr; 184 env->spr[SPR_XER] = cpu_read_xer(env); 185 #if defined(TARGET_PPC64) 186 env->spr[SPR_CFAR] = env->cfar; 187 #endif 188 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 189 190 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 191 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 192 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 193 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 194 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 195 } 196 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 197 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 198 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 199 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 200 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 201 } 202 203 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 204 if (cpu->pre_2_8_migration) { 205 /* Mask out bits that got added to msr_mask since the versions 206 * which stupidly included it in the migration stream. */ 207 target_ulong metamask = 0 208 #if defined(TARGET_PPC64) 209 | (1ULL << MSR_TS0) 210 | (1ULL << MSR_TS1) 211 #endif 212 ; 213 cpu->mig_msr_mask = env->msr_mask & ~metamask; 214 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 215 /* CPU models supported by old machines all have PPC_MEM_TLBIE, 216 * so we set it unconditionally to allow backward migration from 217 * a POWER9 host to a POWER8 host. 218 */ 219 cpu->mig_insns_flags |= PPC_MEM_TLBIE; 220 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 221 cpu->mig_nb_BATs = env->nb_BATs; 222 } 223 if (cpu->pre_3_0_migration) { 224 if (cpu->hash64_opts) { 225 cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 226 } 227 } 228 229 return 0; 230 } 231 232 /* 233 * Determine if a given PVR is a "close enough" match to the CPU 234 * object. For TCG and KVM PR it would probably be sufficient to 235 * require an exact PVR match. However for KVM HV the user is 236 * restricted to a PVR exactly matching the host CPU. The correct way 237 * to handle this is to put the guest into an architected 238 * compatibility mode. However, to allow a more forgiving transition 239 * and migration from before this was widely done, we allow migration 240 * between sufficiently similar PVRs, as determined by the CPU class's 241 * pvr_match() hook. 242 */ 243 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 244 { 245 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 246 247 if (pvr == pcc->pvr) { 248 return true; 249 } 250 return pcc->pvr_match(pcc, pvr); 251 } 252 253 static int cpu_post_load(void *opaque, int version_id) 254 { 255 PowerPCCPU *cpu = opaque; 256 CPUPPCState *env = &cpu->env; 257 int i; 258 target_ulong msr; 259 260 /* 261 * If we're operating in compat mode, we should be ok as long as 262 * the destination supports the same compatiblity mode. 263 * 264 * Otherwise, however, we require that the destination has exactly 265 * the same CPU model as the source. 266 */ 267 268 #if defined(TARGET_PPC64) 269 if (cpu->compat_pvr) { 270 uint32_t compat_pvr = cpu->compat_pvr; 271 Error *local_err = NULL; 272 273 cpu->compat_pvr = 0; 274 ppc_set_compat(cpu, compat_pvr, &local_err); 275 if (local_err) { 276 error_report_err(local_err); 277 return -1; 278 } 279 } else 280 #endif 281 { 282 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 283 return -1; 284 } 285 } 286 287 /* 288 * If we're running with KVM HV, there is a chance that the guest 289 * is running with KVM HV and its kernel does not have the 290 * capability of dealing with a different PVR other than this 291 * exact host PVR in KVM_SET_SREGS. If that happens, the 292 * guest freezes after migration. 293 * 294 * The function kvmppc_pvr_workaround_required does this verification 295 * by first checking if the kernel has the cap, returning true immediately 296 * if that is the case. Otherwise, it checks if we're running in KVM PR. 297 * If the guest kernel does not have the cap and we're not running KVM-PR 298 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 299 * receive the PVR it expects as a workaround. 300 * 301 */ 302 #if defined(CONFIG_KVM) 303 if (kvmppc_pvr_workaround_required(cpu)) { 304 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 305 } 306 #endif 307 308 env->lr = env->spr[SPR_LR]; 309 env->ctr = env->spr[SPR_CTR]; 310 cpu_write_xer(env, env->spr[SPR_XER]); 311 #if defined(TARGET_PPC64) 312 env->cfar = env->spr[SPR_CFAR]; 313 #endif 314 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 315 316 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 317 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 318 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 319 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 320 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 321 } 322 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 323 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 324 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 325 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 326 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 327 } 328 329 if (!cpu->vhyp) { 330 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 331 } 332 333 /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ 334 msr = env->msr; 335 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); 336 ppc_store_msr(env, msr); 337 338 hreg_compute_mem_idx(env); 339 340 return 0; 341 } 342 343 static bool fpu_needed(void *opaque) 344 { 345 PowerPCCPU *cpu = opaque; 346 347 return (cpu->env.insns_flags & PPC_FLOAT); 348 } 349 350 static const VMStateDescription vmstate_fpu = { 351 .name = "cpu/fpu", 352 .version_id = 1, 353 .minimum_version_id = 1, 354 .needed = fpu_needed, 355 .fields = (VMStateField[]) { 356 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 357 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 358 VMSTATE_END_OF_LIST() 359 }, 360 }; 361 362 static bool altivec_needed(void *opaque) 363 { 364 PowerPCCPU *cpu = opaque; 365 366 return (cpu->env.insns_flags & PPC_ALTIVEC); 367 } 368 369 static const VMStateDescription vmstate_altivec = { 370 .name = "cpu/altivec", 371 .version_id = 1, 372 .minimum_version_id = 1, 373 .needed = altivec_needed, 374 .fields = (VMStateField[]) { 375 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 376 VMSTATE_UINT32(env.vscr, PowerPCCPU), 377 VMSTATE_END_OF_LIST() 378 }, 379 }; 380 381 static bool vsx_needed(void *opaque) 382 { 383 PowerPCCPU *cpu = opaque; 384 385 return (cpu->env.insns_flags2 & PPC2_VSX); 386 } 387 388 static const VMStateDescription vmstate_vsx = { 389 .name = "cpu/vsx", 390 .version_id = 1, 391 .minimum_version_id = 1, 392 .needed = vsx_needed, 393 .fields = (VMStateField[]) { 394 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 395 VMSTATE_END_OF_LIST() 396 }, 397 }; 398 399 #ifdef TARGET_PPC64 400 /* Transactional memory state */ 401 static bool tm_needed(void *opaque) 402 { 403 PowerPCCPU *cpu = opaque; 404 CPUPPCState *env = &cpu->env; 405 return msr_ts; 406 } 407 408 static const VMStateDescription vmstate_tm = { 409 .name = "cpu/tm", 410 .version_id = 1, 411 .minimum_version_id = 1, 412 .minimum_version_id_old = 1, 413 .needed = tm_needed, 414 .fields = (VMStateField []) { 415 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 416 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 417 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 418 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 419 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 420 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 421 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 422 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 423 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 424 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 425 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 426 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 427 VMSTATE_END_OF_LIST() 428 }, 429 }; 430 #endif 431 432 static bool sr_needed(void *opaque) 433 { 434 #ifdef TARGET_PPC64 435 PowerPCCPU *cpu = opaque; 436 437 return !(cpu->env.mmu_model & POWERPC_MMU_64); 438 #else 439 return true; 440 #endif 441 } 442 443 static const VMStateDescription vmstate_sr = { 444 .name = "cpu/sr", 445 .version_id = 1, 446 .minimum_version_id = 1, 447 .needed = sr_needed, 448 .fields = (VMStateField[]) { 449 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 450 VMSTATE_END_OF_LIST() 451 }, 452 }; 453 454 #ifdef TARGET_PPC64 455 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 456 { 457 ppc_slb_t *v = pv; 458 459 v->esid = qemu_get_be64(f); 460 v->vsid = qemu_get_be64(f); 461 462 return 0; 463 } 464 465 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 466 QJSON *vmdesc) 467 { 468 ppc_slb_t *v = pv; 469 470 qemu_put_be64(f, v->esid); 471 qemu_put_be64(f, v->vsid); 472 return 0; 473 } 474 475 static const VMStateInfo vmstate_info_slbe = { 476 .name = "slbe", 477 .get = get_slbe, 478 .put = put_slbe, 479 }; 480 481 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 482 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 483 484 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 485 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 486 487 static bool slb_needed(void *opaque) 488 { 489 PowerPCCPU *cpu = opaque; 490 491 /* We don't support any of the old segment table based 64-bit CPUs */ 492 return (cpu->env.mmu_model & POWERPC_MMU_64); 493 } 494 495 static int slb_post_load(void *opaque, int version_id) 496 { 497 PowerPCCPU *cpu = opaque; 498 CPUPPCState *env = &cpu->env; 499 int i; 500 501 /* We've pulled in the raw esid and vsid values from the migration 502 * stream, but we need to recompute the page size pointers */ 503 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 504 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 505 /* Migration source had bad values in its SLB */ 506 return -1; 507 } 508 } 509 510 return 0; 511 } 512 513 static const VMStateDescription vmstate_slb = { 514 .name = "cpu/slb", 515 .version_id = 1, 516 .minimum_version_id = 1, 517 .needed = slb_needed, 518 .post_load = slb_post_load, 519 .fields = (VMStateField[]) { 520 VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration), 521 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 522 VMSTATE_END_OF_LIST() 523 } 524 }; 525 #endif /* TARGET_PPC64 */ 526 527 static const VMStateDescription vmstate_tlb6xx_entry = { 528 .name = "cpu/tlb6xx_entry", 529 .version_id = 1, 530 .minimum_version_id = 1, 531 .fields = (VMStateField[]) { 532 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 533 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 534 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 535 VMSTATE_END_OF_LIST() 536 }, 537 }; 538 539 static bool tlb6xx_needed(void *opaque) 540 { 541 PowerPCCPU *cpu = opaque; 542 CPUPPCState *env = &cpu->env; 543 544 return env->nb_tlb && (env->tlb_type == TLB_6XX); 545 } 546 547 static const VMStateDescription vmstate_tlb6xx = { 548 .name = "cpu/tlb6xx", 549 .version_id = 1, 550 .minimum_version_id = 1, 551 .needed = tlb6xx_needed, 552 .fields = (VMStateField[]) { 553 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 554 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 555 env.nb_tlb, 556 vmstate_tlb6xx_entry, 557 ppc6xx_tlb_t), 558 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 559 VMSTATE_END_OF_LIST() 560 } 561 }; 562 563 static const VMStateDescription vmstate_tlbemb_entry = { 564 .name = "cpu/tlbemb_entry", 565 .version_id = 1, 566 .minimum_version_id = 1, 567 .fields = (VMStateField[]) { 568 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 569 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 570 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 571 VMSTATE_UINTTL(size, ppcemb_tlb_t), 572 VMSTATE_UINT32(prot, ppcemb_tlb_t), 573 VMSTATE_UINT32(attr, ppcemb_tlb_t), 574 VMSTATE_END_OF_LIST() 575 }, 576 }; 577 578 static bool tlbemb_needed(void *opaque) 579 { 580 PowerPCCPU *cpu = opaque; 581 CPUPPCState *env = &cpu->env; 582 583 return env->nb_tlb && (env->tlb_type == TLB_EMB); 584 } 585 586 static bool pbr403_needed(void *opaque) 587 { 588 PowerPCCPU *cpu = opaque; 589 uint32_t pvr = cpu->env.spr[SPR_PVR]; 590 591 return (pvr & 0xffff0000) == 0x00200000; 592 } 593 594 static const VMStateDescription vmstate_pbr403 = { 595 .name = "cpu/pbr403", 596 .version_id = 1, 597 .minimum_version_id = 1, 598 .needed = pbr403_needed, 599 .fields = (VMStateField[]) { 600 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 601 VMSTATE_END_OF_LIST() 602 }, 603 }; 604 605 static const VMStateDescription vmstate_tlbemb = { 606 .name = "cpu/tlb6xx", 607 .version_id = 1, 608 .minimum_version_id = 1, 609 .needed = tlbemb_needed, 610 .fields = (VMStateField[]) { 611 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 612 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 613 env.nb_tlb, 614 vmstate_tlbemb_entry, 615 ppcemb_tlb_t), 616 /* 403 protection registers */ 617 VMSTATE_END_OF_LIST() 618 }, 619 .subsections = (const VMStateDescription*[]) { 620 &vmstate_pbr403, 621 NULL 622 } 623 }; 624 625 static const VMStateDescription vmstate_tlbmas_entry = { 626 .name = "cpu/tlbmas_entry", 627 .version_id = 1, 628 .minimum_version_id = 1, 629 .fields = (VMStateField[]) { 630 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 631 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 632 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 633 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 634 VMSTATE_END_OF_LIST() 635 }, 636 }; 637 638 static bool tlbmas_needed(void *opaque) 639 { 640 PowerPCCPU *cpu = opaque; 641 CPUPPCState *env = &cpu->env; 642 643 return env->nb_tlb && (env->tlb_type == TLB_MAS); 644 } 645 646 static const VMStateDescription vmstate_tlbmas = { 647 .name = "cpu/tlbmas", 648 .version_id = 1, 649 .minimum_version_id = 1, 650 .needed = tlbmas_needed, 651 .fields = (VMStateField[]) { 652 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 653 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 654 env.nb_tlb, 655 vmstate_tlbmas_entry, 656 ppcmas_tlb_t), 657 VMSTATE_END_OF_LIST() 658 } 659 }; 660 661 static bool compat_needed(void *opaque) 662 { 663 PowerPCCPU *cpu = opaque; 664 665 assert(!(cpu->compat_pvr && !cpu->vhyp)); 666 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 667 } 668 669 static const VMStateDescription vmstate_compat = { 670 .name = "cpu/compat", 671 .version_id = 1, 672 .minimum_version_id = 1, 673 .needed = compat_needed, 674 .fields = (VMStateField[]) { 675 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 676 VMSTATE_END_OF_LIST() 677 } 678 }; 679 680 const VMStateDescription vmstate_ppc_cpu = { 681 .name = "cpu", 682 .version_id = 5, 683 .minimum_version_id = 5, 684 .minimum_version_id_old = 4, 685 .load_state_old = cpu_load_old, 686 .pre_save = cpu_pre_save, 687 .post_load = cpu_post_load, 688 .fields = (VMStateField[]) { 689 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 690 691 /* User mode architected state */ 692 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 693 #if !defined(TARGET_PPC64) 694 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 695 #endif 696 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 697 VMSTATE_UINTTL(env.nip, PowerPCCPU), 698 699 /* SPRs */ 700 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 701 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 702 703 /* Reservation */ 704 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 705 706 /* Supervisor mode architected state */ 707 VMSTATE_UINTTL(env.msr, PowerPCCPU), 708 709 /* Internal state */ 710 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 711 /* FIXME: access_type? */ 712 713 /* Sanity checking */ 714 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 715 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 716 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 717 cpu_pre_2_8_migration), 718 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 719 VMSTATE_END_OF_LIST() 720 }, 721 .subsections = (const VMStateDescription*[]) { 722 &vmstate_fpu, 723 &vmstate_altivec, 724 &vmstate_vsx, 725 &vmstate_sr, 726 #ifdef TARGET_PPC64 727 &vmstate_tm, 728 &vmstate_slb, 729 #endif /* TARGET_PPC64 */ 730 &vmstate_tlb6xx, 731 &vmstate_tlbemb, 732 &vmstate_tlbmas, 733 &vmstate_compat, 734 NULL 735 } 736 }; 737