1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "exec/exec-all.h" 4 #include "sysemu/kvm.h" 5 #include "sysemu/tcg.h" 6 #include "helper_regs.h" 7 #include "mmu-hash64.h" 8 #include "migration/cpu.h" 9 #include "qapi/error.h" 10 #include "kvm_ppc.h" 11 #include "power8-pmu.h" 12 13 static void post_load_update_msr(CPUPPCState *env) 14 { 15 target_ulong msr = env->msr; 16 17 /* 18 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB 19 * before restoring. Note that this recomputes hflags. 20 */ 21 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); 22 ppc_store_msr(env, msr); 23 } 24 25 static int get_avr(QEMUFile *f, void *pv, size_t size, 26 const VMStateField *field) 27 { 28 ppc_avr_t *v = pv; 29 30 v->u64[0] = qemu_get_be64(f); 31 v->u64[1] = qemu_get_be64(f); 32 33 return 0; 34 } 35 36 static int put_avr(QEMUFile *f, void *pv, size_t size, 37 const VMStateField *field, JSONWriter *vmdesc) 38 { 39 ppc_avr_t *v = pv; 40 41 qemu_put_be64(f, v->u64[0]); 42 qemu_put_be64(f, v->u64[1]); 43 return 0; 44 } 45 46 static const VMStateInfo vmstate_info_avr = { 47 .name = "avr", 48 .get = get_avr, 49 .put = put_avr, 50 }; 51 52 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 53 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) 54 55 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 56 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 57 58 static int get_fpr(QEMUFile *f, void *pv, size_t size, 59 const VMStateField *field) 60 { 61 ppc_vsr_t *v = pv; 62 63 v->VsrD(0) = qemu_get_be64(f); 64 65 return 0; 66 } 67 68 static int put_fpr(QEMUFile *f, void *pv, size_t size, 69 const VMStateField *field, JSONWriter *vmdesc) 70 { 71 ppc_vsr_t *v = pv; 72 73 qemu_put_be64(f, v->VsrD(0)); 74 return 0; 75 } 76 77 static const VMStateInfo vmstate_info_fpr = { 78 .name = "fpr", 79 .get = get_fpr, 80 .put = put_fpr, 81 }; 82 83 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ 84 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) 85 86 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ 87 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) 88 89 static int get_vsr(QEMUFile *f, void *pv, size_t size, 90 const VMStateField *field) 91 { 92 ppc_vsr_t *v = pv; 93 94 v->VsrD(1) = qemu_get_be64(f); 95 96 return 0; 97 } 98 99 static int put_vsr(QEMUFile *f, void *pv, size_t size, 100 const VMStateField *field, JSONWriter *vmdesc) 101 { 102 ppc_vsr_t *v = pv; 103 104 qemu_put_be64(f, v->VsrD(1)); 105 return 0; 106 } 107 108 static const VMStateInfo vmstate_info_vsr = { 109 .name = "vsr", 110 .get = get_vsr, 111 .put = put_vsr, 112 }; 113 114 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ 115 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) 116 117 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ 118 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) 119 120 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 121 { 122 PowerPCCPU *cpu = opaque; 123 124 return cpu->pre_2_8_migration; 125 } 126 127 #if defined(TARGET_PPC64) 128 static bool cpu_pre_3_0_migration(void *opaque, int version_id) 129 { 130 PowerPCCPU *cpu = opaque; 131 132 return cpu->pre_3_0_migration; 133 } 134 #endif 135 136 static int cpu_pre_save(void *opaque) 137 { 138 PowerPCCPU *cpu = opaque; 139 CPUPPCState *env = &cpu->env; 140 int i; 141 uint64_t insns_compat_mask = 142 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 143 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 144 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 145 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 146 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 147 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 148 | PPC_64B | PPC_64BX | PPC_ALTIVEC 149 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 150 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 151 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 152 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 153 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 154 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 155 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM 156 | PPC2_MEM_LWSYNC; 157 158 env->spr[SPR_LR] = env->lr; 159 env->spr[SPR_CTR] = env->ctr; 160 env->spr[SPR_XER] = cpu_read_xer(env); 161 #if defined(TARGET_PPC64) 162 env->spr[SPR_CFAR] = env->cfar; 163 #endif 164 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 165 166 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 167 env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; 168 env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; 169 env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; 170 env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; 171 } 172 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 173 env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; 174 env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4]; 175 env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4]; 176 env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; 177 } 178 179 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 180 if (cpu->pre_2_8_migration) { 181 /* 182 * Mask out bits that got added to msr_mask since the versions 183 * which stupidly included it in the migration stream. 184 */ 185 target_ulong metamask = 0 186 #if defined(TARGET_PPC64) 187 | (1ULL << MSR_TS0) 188 | (1ULL << MSR_TS1) 189 #endif 190 ; 191 cpu->mig_msr_mask = env->msr_mask & ~metamask; 192 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 193 /* 194 * CPU models supported by old machines all have 195 * PPC_MEM_TLBIE, so we set it unconditionally to allow 196 * backward migration from a POWER9 host to a POWER8 host. 197 */ 198 cpu->mig_insns_flags |= PPC_MEM_TLBIE; 199 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 200 cpu->mig_nb_BATs = env->nb_BATs; 201 } 202 if (cpu->pre_3_0_migration) { 203 if (cpu->hash64_opts) { 204 cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 205 } 206 } 207 208 /* Used to retain migration compatibility for pre 6.0 for 601 machines. */ 209 env->hflags_compat_nmsr = 0; 210 211 if (tcg_enabled()) { 212 /* 213 * TCG does not maintain the DECR spr (unlike KVM) so have to save 214 * it here. 215 */ 216 env->spr[SPR_DECR] = cpu_ppc_load_decr(env); 217 } 218 219 return 0; 220 } 221 222 /* 223 * Determine if a given PVR is a "close enough" match to the CPU 224 * object. For TCG and KVM PR it would probably be sufficient to 225 * require an exact PVR match. However for KVM HV the user is 226 * restricted to a PVR exactly matching the host CPU. The correct way 227 * to handle this is to put the guest into an architected 228 * compatibility mode. However, to allow a more forgiving transition 229 * and migration from before this was widely done, we allow migration 230 * between sufficiently similar PVRs, as determined by the CPU class's 231 * pvr_match() hook. 232 */ 233 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 234 { 235 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 236 237 if (pvr == pcc->pvr) { 238 return true; 239 } 240 return pcc->pvr_match(pcc, pvr, true); 241 } 242 243 static int cpu_post_load(void *opaque, int version_id) 244 { 245 PowerPCCPU *cpu = opaque; 246 CPUPPCState *env = &cpu->env; 247 int i; 248 249 /* 250 * If we're operating in compat mode, we should be ok as long as 251 * the destination supports the same compatibility mode. 252 * 253 * Otherwise, however, we require that the destination has exactly 254 * the same CPU model as the source. 255 */ 256 257 #if defined(TARGET_PPC64) 258 if (cpu->compat_pvr) { 259 uint32_t compat_pvr = cpu->compat_pvr; 260 Error *local_err = NULL; 261 int ret; 262 263 cpu->compat_pvr = 0; 264 ret = ppc_set_compat(cpu, compat_pvr, &local_err); 265 if (ret < 0) { 266 error_report_err(local_err); 267 return ret; 268 } 269 } else 270 #endif 271 { 272 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 273 return -EINVAL; 274 } 275 } 276 277 /* 278 * If we're running with KVM HV, there is a chance that the guest 279 * is running with KVM HV and its kernel does not have the 280 * capability of dealing with a different PVR other than this 281 * exact host PVR in KVM_SET_SREGS. If that happens, the 282 * guest freezes after migration. 283 * 284 * The function kvmppc_pvr_workaround_required does this verification 285 * by first checking if the kernel has the cap, returning true immediately 286 * if that is the case. Otherwise, it checks if we're running in KVM PR. 287 * If the guest kernel does not have the cap and we're not running KVM-PR 288 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 289 * receive the PVR it expects as a workaround. 290 * 291 */ 292 if (kvmppc_pvr_workaround_required(cpu)) { 293 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 294 } 295 296 env->lr = env->spr[SPR_LR]; 297 env->ctr = env->spr[SPR_CTR]; 298 cpu_write_xer(env, env->spr[SPR_XER]); 299 #if defined(TARGET_PPC64) 300 env->cfar = env->spr[SPR_CFAR]; 301 #endif 302 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 303 304 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 305 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i]; 306 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1]; 307 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i]; 308 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1]; 309 } 310 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 311 env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i]; 312 env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1]; 313 env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i]; 314 env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1]; 315 } 316 317 if (!cpu->vhyp) { 318 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 319 } 320 321 post_load_update_msr(env); 322 323 if (tcg_enabled()) { 324 /* Re-set breaks based on regs */ 325 #if defined(TARGET_PPC64) 326 ppc_update_ciabr(env); 327 ppc_update_daw0(env); 328 #endif 329 /* 330 * TCG needs to re-start the decrementer timer and/or raise the 331 * interrupt. This works for level-triggered decrementer. Edge 332 * triggered types (including HDEC) would need to carry more state. 333 */ 334 cpu_ppc_store_decr(env, env->spr[SPR_DECR]); 335 pmu_mmcr01_updated(env); 336 } 337 338 return 0; 339 } 340 341 static bool fpu_needed(void *opaque) 342 { 343 PowerPCCPU *cpu = opaque; 344 345 return cpu->env.insns_flags & PPC_FLOAT; 346 } 347 348 static const VMStateDescription vmstate_fpu = { 349 .name = "cpu/fpu", 350 .version_id = 1, 351 .minimum_version_id = 1, 352 .needed = fpu_needed, 353 .fields = (VMStateField[]) { 354 VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), 355 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 356 VMSTATE_END_OF_LIST() 357 }, 358 }; 359 360 static bool altivec_needed(void *opaque) 361 { 362 PowerPCCPU *cpu = opaque; 363 364 return cpu->env.insns_flags & PPC_ALTIVEC; 365 } 366 367 static int get_vscr(QEMUFile *f, void *opaque, size_t size, 368 const VMStateField *field) 369 { 370 PowerPCCPU *cpu = opaque; 371 ppc_store_vscr(&cpu->env, qemu_get_be32(f)); 372 return 0; 373 } 374 375 static int put_vscr(QEMUFile *f, void *opaque, size_t size, 376 const VMStateField *field, JSONWriter *vmdesc) 377 { 378 PowerPCCPU *cpu = opaque; 379 qemu_put_be32(f, ppc_get_vscr(&cpu->env)); 380 return 0; 381 } 382 383 static const VMStateInfo vmstate_vscr = { 384 .name = "cpu/altivec/vscr", 385 .get = get_vscr, 386 .put = put_vscr, 387 }; 388 389 static const VMStateDescription vmstate_altivec = { 390 .name = "cpu/altivec", 391 .version_id = 1, 392 .minimum_version_id = 1, 393 .needed = altivec_needed, 394 .fields = (VMStateField[]) { 395 VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), 396 /* 397 * Save the architecture value of the vscr, not the internally 398 * expanded version. Since this architecture value does not 399 * exist in memory to be stored, this requires a but of hoop 400 * jumping. We want OFFSET=0 so that we effectively pass CPU 401 * to the helper functions. 402 */ 403 { 404 .name = "vscr", 405 .version_id = 0, 406 .size = sizeof(uint32_t), 407 .info = &vmstate_vscr, 408 .flags = VMS_SINGLE, 409 .offset = 0 410 }, 411 VMSTATE_END_OF_LIST() 412 }, 413 }; 414 415 static bool vsx_needed(void *opaque) 416 { 417 PowerPCCPU *cpu = opaque; 418 419 return cpu->env.insns_flags2 & PPC2_VSX; 420 } 421 422 static const VMStateDescription vmstate_vsx = { 423 .name = "cpu/vsx", 424 .version_id = 1, 425 .minimum_version_id = 1, 426 .needed = vsx_needed, 427 .fields = (VMStateField[]) { 428 VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), 429 VMSTATE_END_OF_LIST() 430 }, 431 }; 432 433 #ifdef TARGET_PPC64 434 /* Transactional memory state */ 435 static bool tm_needed(void *opaque) 436 { 437 PowerPCCPU *cpu = opaque; 438 CPUPPCState *env = &cpu->env; 439 return FIELD_EX64(env->msr, MSR, TS); 440 } 441 442 static const VMStateDescription vmstate_tm = { 443 .name = "cpu/tm", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .needed = tm_needed, 447 .fields = (VMStateField []) { 448 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 449 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 450 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 451 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 452 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 453 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 454 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 455 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 456 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 457 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 458 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 459 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 460 VMSTATE_END_OF_LIST() 461 }, 462 }; 463 #endif 464 465 static bool sr_needed(void *opaque) 466 { 467 #ifdef TARGET_PPC64 468 PowerPCCPU *cpu = opaque; 469 470 return !mmu_is_64bit(cpu->env.mmu_model); 471 #else 472 return true; 473 #endif 474 } 475 476 static const VMStateDescription vmstate_sr = { 477 .name = "cpu/sr", 478 .version_id = 1, 479 .minimum_version_id = 1, 480 .needed = sr_needed, 481 .fields = (VMStateField[]) { 482 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 483 VMSTATE_END_OF_LIST() 484 }, 485 }; 486 487 #ifdef TARGET_PPC64 488 static int get_slbe(QEMUFile *f, void *pv, size_t size, 489 const VMStateField *field) 490 { 491 ppc_slb_t *v = pv; 492 493 v->esid = qemu_get_be64(f); 494 v->vsid = qemu_get_be64(f); 495 496 return 0; 497 } 498 499 static int put_slbe(QEMUFile *f, void *pv, size_t size, 500 const VMStateField *field, JSONWriter *vmdesc) 501 { 502 ppc_slb_t *v = pv; 503 504 qemu_put_be64(f, v->esid); 505 qemu_put_be64(f, v->vsid); 506 return 0; 507 } 508 509 static const VMStateInfo vmstate_info_slbe = { 510 .name = "slbe", 511 .get = get_slbe, 512 .put = put_slbe, 513 }; 514 515 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 516 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 517 518 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 519 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 520 521 static bool slb_needed(void *opaque) 522 { 523 PowerPCCPU *cpu = opaque; 524 525 /* We don't support any of the old segment table based 64-bit CPUs */ 526 return mmu_is_64bit(cpu->env.mmu_model); 527 } 528 529 static int slb_post_load(void *opaque, int version_id) 530 { 531 PowerPCCPU *cpu = opaque; 532 CPUPPCState *env = &cpu->env; 533 int i; 534 535 /* 536 * We've pulled in the raw esid and vsid values from the migration 537 * stream, but we need to recompute the page size pointers 538 */ 539 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 540 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 541 /* Migration source had bad values in its SLB */ 542 return -1; 543 } 544 } 545 546 return 0; 547 } 548 549 static const VMStateDescription vmstate_slb = { 550 .name = "cpu/slb", 551 .version_id = 1, 552 .minimum_version_id = 1, 553 .needed = slb_needed, 554 .post_load = slb_post_load, 555 .fields = (VMStateField[]) { 556 VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration), 557 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 558 VMSTATE_END_OF_LIST() 559 } 560 }; 561 #endif /* TARGET_PPC64 */ 562 563 static const VMStateDescription vmstate_tlb6xx_entry = { 564 .name = "cpu/tlb6xx_entry", 565 .version_id = 1, 566 .minimum_version_id = 1, 567 .fields = (VMStateField[]) { 568 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 569 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 570 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 571 VMSTATE_END_OF_LIST() 572 }, 573 }; 574 575 static bool tlb6xx_needed(void *opaque) 576 { 577 PowerPCCPU *cpu = opaque; 578 CPUPPCState *env = &cpu->env; 579 580 return env->nb_tlb && (env->tlb_type == TLB_6XX); 581 } 582 583 static const VMStateDescription vmstate_tlb6xx = { 584 .name = "cpu/tlb6xx", 585 .version_id = 1, 586 .minimum_version_id = 1, 587 .needed = tlb6xx_needed, 588 .fields = (VMStateField[]) { 589 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 590 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 591 env.nb_tlb, 592 vmstate_tlb6xx_entry, 593 ppc6xx_tlb_t), 594 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 595 VMSTATE_END_OF_LIST() 596 } 597 }; 598 599 static const VMStateDescription vmstate_tlbemb_entry = { 600 .name = "cpu/tlbemb_entry", 601 .version_id = 1, 602 .minimum_version_id = 1, 603 .fields = (VMStateField[]) { 604 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 605 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 606 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 607 VMSTATE_UINTTL(size, ppcemb_tlb_t), 608 VMSTATE_UINT32(prot, ppcemb_tlb_t), 609 VMSTATE_UINT32(attr, ppcemb_tlb_t), 610 VMSTATE_END_OF_LIST() 611 }, 612 }; 613 614 static bool tlbemb_needed(void *opaque) 615 { 616 PowerPCCPU *cpu = opaque; 617 CPUPPCState *env = &cpu->env; 618 619 return env->nb_tlb && (env->tlb_type == TLB_EMB); 620 } 621 622 static const VMStateDescription vmstate_tlbemb = { 623 .name = "cpu/tlb6xx", 624 .version_id = 1, 625 .minimum_version_id = 1, 626 .needed = tlbemb_needed, 627 .fields = (VMStateField[]) { 628 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 629 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 630 env.nb_tlb, 631 vmstate_tlbemb_entry, 632 ppcemb_tlb_t), 633 VMSTATE_END_OF_LIST() 634 }, 635 }; 636 637 static const VMStateDescription vmstate_tlbmas_entry = { 638 .name = "cpu/tlbmas_entry", 639 .version_id = 1, 640 .minimum_version_id = 1, 641 .fields = (VMStateField[]) { 642 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 643 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 644 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 645 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 646 VMSTATE_END_OF_LIST() 647 }, 648 }; 649 650 static bool tlbmas_needed(void *opaque) 651 { 652 PowerPCCPU *cpu = opaque; 653 CPUPPCState *env = &cpu->env; 654 655 return env->nb_tlb && (env->tlb_type == TLB_MAS); 656 } 657 658 static const VMStateDescription vmstate_tlbmas = { 659 .name = "cpu/tlbmas", 660 .version_id = 1, 661 .minimum_version_id = 1, 662 .needed = tlbmas_needed, 663 .fields = (VMStateField[]) { 664 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 665 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 666 env.nb_tlb, 667 vmstate_tlbmas_entry, 668 ppcmas_tlb_t), 669 VMSTATE_END_OF_LIST() 670 } 671 }; 672 673 static bool compat_needed(void *opaque) 674 { 675 PowerPCCPU *cpu = opaque; 676 677 assert(!(cpu->compat_pvr && !cpu->vhyp)); 678 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 679 } 680 681 static const VMStateDescription vmstate_compat = { 682 .name = "cpu/compat", 683 .version_id = 1, 684 .minimum_version_id = 1, 685 .needed = compat_needed, 686 .fields = (VMStateField[]) { 687 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 688 VMSTATE_END_OF_LIST() 689 } 690 }; 691 692 const VMStateDescription vmstate_ppc_cpu = { 693 .name = "cpu", 694 .version_id = 5, 695 .minimum_version_id = 5, 696 .pre_save = cpu_pre_save, 697 .post_load = cpu_post_load, 698 .fields = (VMStateField[]) { 699 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 700 701 /* User mode architected state */ 702 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 703 #if !defined(TARGET_PPC64) 704 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 705 #endif 706 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 707 VMSTATE_UINTTL(env.nip, PowerPCCPU), 708 709 /* SPRs */ 710 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 711 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 712 713 /* Reservation */ 714 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 715 716 /* Supervisor mode architected state */ 717 VMSTATE_UINTTL(env.msr, PowerPCCPU), 718 719 /* Backward compatible internal state */ 720 VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), 721 722 /* Sanity checking */ 723 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 724 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 725 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 726 cpu_pre_2_8_migration), 727 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 728 VMSTATE_END_OF_LIST() 729 }, 730 .subsections = (const VMStateDescription*[]) { 731 &vmstate_fpu, 732 &vmstate_altivec, 733 &vmstate_vsx, 734 &vmstate_sr, 735 #ifdef TARGET_PPC64 736 &vmstate_tm, 737 &vmstate_slb, 738 #endif /* TARGET_PPC64 */ 739 &vmstate_tlb6xx, 740 &vmstate_tlbemb, 741 &vmstate_tlbmas, 742 &vmstate_compat, 743 NULL 744 } 745 }; 746