1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu-common.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "cpu.h" 28 #include "cpu-models.h" 29 #include "qemu/timer.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/hw_accel.h" 32 #include "kvm_ppc.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/device_tree.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/sysbus.h" 38 #include "hw/ppc/spapr.h" 39 #include "hw/ppc/spapr_cpu_core.h" 40 #include "hw/hw.h" 41 #include "hw/ppc/ppc.h" 42 #include "migration/qemu-file-types.h" 43 #include "sysemu/watchdog.h" 44 #include "trace.h" 45 #include "exec/gdbstub.h" 46 #include "exec/memattrs.h" 47 #include "exec/ram_addr.h" 48 #include "sysemu/hostmem.h" 49 #include "qemu/cutils.h" 50 #include "qemu/main-loop.h" 51 #include "qemu/mmap-alloc.h" 52 #include "elf.h" 53 #include "sysemu/kvm_int.h" 54 55 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 56 57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 58 KVM_CAP_LAST_INFO 59 }; 60 61 static int cap_interrupt_unset; 62 static int cap_interrupt_level; 63 static int cap_segstate; 64 static int cap_booke_sregs; 65 static int cap_ppc_smt; 66 static int cap_ppc_smt_possible; 67 static int cap_spapr_tce; 68 static int cap_spapr_tce_64; 69 static int cap_spapr_multitce; 70 static int cap_spapr_vfio; 71 static int cap_hior; 72 static int cap_one_reg; 73 static int cap_epr; 74 static int cap_ppc_watchdog; 75 static int cap_papr; 76 static int cap_htab_fd; 77 static int cap_fixup_hcalls; 78 static int cap_htm; /* Hardware transactional memory support */ 79 static int cap_mmu_radix; 80 static int cap_mmu_hash_v3; 81 static int cap_xive; 82 static int cap_resize_hpt; 83 static int cap_ppc_pvr_compat; 84 static int cap_ppc_safe_cache; 85 static int cap_ppc_safe_bounds_check; 86 static int cap_ppc_safe_indirect_branch; 87 static int cap_ppc_count_cache_flush_assist; 88 static int cap_ppc_nested_kvm_hv; 89 static int cap_large_decr; 90 91 static uint32_t debug_inst_opcode; 92 93 /* 94 * XXX We have a race condition where we actually have a level triggered 95 * interrupt, but the infrastructure can't expose that yet, so the guest 96 * takes but ignores it, goes to sleep and never gets notified that there's 97 * still an interrupt pending. 98 * 99 * As a quick workaround, let's just wake up again 20 ms after we injected 100 * an interrupt. That way we can assure that we're always reinjecting 101 * interrupts in case the guest swallowed them. 102 */ 103 static QEMUTimer *idle_timer; 104 105 static void kvm_kick_cpu(void *opaque) 106 { 107 PowerPCCPU *cpu = opaque; 108 109 qemu_cpu_kick(CPU(cpu)); 110 } 111 112 /* 113 * Check whether we are running with KVM-PR (instead of KVM-HV). This 114 * should only be used for fallback tests - generally we should use 115 * explicit capabilities for the features we want, rather than 116 * assuming what is/isn't available depending on the KVM variant. 117 */ 118 static bool kvmppc_is_pr(KVMState *ks) 119 { 120 /* Assume KVM-PR if the GET_PVINFO capability is available */ 121 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 122 } 123 124 static int kvm_ppc_register_host_cpu_type(MachineState *ms); 125 static void kvmppc_get_cpu_characteristics(KVMState *s); 126 static int kvmppc_get_dec_bits(void); 127 128 int kvm_arch_init(MachineState *ms, KVMState *s) 129 { 130 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 131 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); 132 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 133 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 134 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 135 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 136 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 137 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 138 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 139 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 140 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 141 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 142 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 143 /* 144 * Note: we don't set cap_papr here, because this capability is 145 * only activated after this by kvmppc_set_papr() 146 */ 147 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 148 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 149 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 150 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 151 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 152 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 153 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 154 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 155 kvmppc_get_cpu_characteristics(s); 156 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 157 cap_large_decr = kvmppc_get_dec_bits(); 158 /* 159 * Note: setting it to false because there is not such capability 160 * in KVM at this moment. 161 * 162 * TODO: call kvm_vm_check_extension() with the right capability 163 * after the kernel starts implementing it. 164 */ 165 cap_ppc_pvr_compat = false; 166 167 if (!cap_interrupt_level) { 168 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " 169 "VM to stall at times!\n"); 170 } 171 172 kvm_ppc_register_host_cpu_type(ms); 173 174 return 0; 175 } 176 177 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s) 178 { 179 return 0; 180 } 181 182 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 183 { 184 CPUPPCState *cenv = &cpu->env; 185 CPUState *cs = CPU(cpu); 186 struct kvm_sregs sregs; 187 int ret; 188 189 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 190 /* 191 * What we're really trying to say is "if we're on BookE, we 192 * use the native PVR for now". This is the only sane way to 193 * check it though, so we potentially confuse users that they 194 * can run BookE guests on BookS. Let's hope nobody dares 195 * enough :) 196 */ 197 return 0; 198 } else { 199 if (!cap_segstate) { 200 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 201 return -ENOSYS; 202 } 203 } 204 205 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 206 if (ret) { 207 return ret; 208 } 209 210 sregs.pvr = cenv->spr[SPR_PVR]; 211 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 212 } 213 214 /* Set up a shared TLB array with KVM */ 215 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 216 { 217 CPUPPCState *env = &cpu->env; 218 CPUState *cs = CPU(cpu); 219 struct kvm_book3e_206_tlb_params params = {}; 220 struct kvm_config_tlb cfg = {}; 221 unsigned int entries = 0; 222 int ret, i; 223 224 if (!kvm_enabled() || 225 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 226 return 0; 227 } 228 229 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 230 231 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 232 params.tlb_sizes[i] = booke206_tlb_size(env, i); 233 params.tlb_ways[i] = booke206_tlb_ways(env, i); 234 entries += params.tlb_sizes[i]; 235 } 236 237 assert(entries == env->nb_tlb); 238 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 239 240 env->tlb_dirty = true; 241 242 cfg.array = (uintptr_t)env->tlb.tlbm; 243 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 244 cfg.params = (uintptr_t)¶ms; 245 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 246 247 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 248 if (ret < 0) { 249 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 250 __func__, strerror(-ret)); 251 return ret; 252 } 253 254 env->kvm_sw_tlb = true; 255 return 0; 256 } 257 258 259 #if defined(TARGET_PPC64) 260 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 261 { 262 int ret; 263 264 assert(kvm_state != NULL); 265 266 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 267 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 268 error_append_hint(errp, "Consider switching to a newer KVM\n"); 269 return; 270 } 271 272 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 273 if (ret == 0) { 274 return; 275 } 276 277 error_setg_errno(errp, -ret, 278 "KVM failed to provide the MMU features it supports"); 279 } 280 281 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 282 { 283 KVMState *s = KVM_STATE(current_machine->accelerator); 284 struct ppc_radix_page_info *radix_page_info; 285 struct kvm_ppc_rmmu_info rmmu_info; 286 int i; 287 288 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 289 return NULL; 290 } 291 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 292 return NULL; 293 } 294 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 295 radix_page_info->count = 0; 296 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 297 if (rmmu_info.ap_encodings[i]) { 298 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 299 radix_page_info->count++; 300 } 301 } 302 return radix_page_info; 303 } 304 305 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 306 bool radix, bool gtse, 307 uint64_t proc_tbl) 308 { 309 CPUState *cs = CPU(cpu); 310 int ret; 311 uint64_t flags = 0; 312 struct kvm_ppc_mmuv3_cfg cfg = { 313 .process_table = proc_tbl, 314 }; 315 316 if (radix) { 317 flags |= KVM_PPC_MMUV3_RADIX; 318 } 319 if (gtse) { 320 flags |= KVM_PPC_MMUV3_GTSE; 321 } 322 cfg.flags = flags; 323 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 324 switch (ret) { 325 case 0: 326 return H_SUCCESS; 327 case -EINVAL: 328 return H_PARAMETER; 329 case -ENODEV: 330 return H_NOT_AVAILABLE; 331 default: 332 return H_HARDWARE; 333 } 334 } 335 336 bool kvmppc_hpt_needs_host_contiguous_pages(void) 337 { 338 static struct kvm_ppc_smmu_info smmu_info; 339 340 if (!kvm_enabled()) { 341 return false; 342 } 343 344 kvm_get_smmu_info(&smmu_info, &error_fatal); 345 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 346 } 347 348 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 349 { 350 struct kvm_ppc_smmu_info smmu_info; 351 int iq, ik, jq, jk; 352 Error *local_err = NULL; 353 354 /* For now, we only have anything to check on hash64 MMUs */ 355 if (!cpu->hash64_opts || !kvm_enabled()) { 356 return; 357 } 358 359 kvm_get_smmu_info(&smmu_info, &local_err); 360 if (local_err) { 361 error_propagate(errp, local_err); 362 return; 363 } 364 365 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 366 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 367 error_setg(errp, 368 "KVM does not support 1TiB segments which guest expects"); 369 return; 370 } 371 372 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 373 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 374 smmu_info.slb_size, cpu->hash64_opts->slb_size); 375 return; 376 } 377 378 /* 379 * Verify that every pagesize supported by the cpu model is 380 * supported by KVM with the same encodings 381 */ 382 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 383 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 384 struct kvm_ppc_one_seg_page_size *ksps; 385 386 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 387 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 388 break; 389 } 390 } 391 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 392 error_setg(errp, "KVM doesn't support for base page shift %u", 393 qsps->page_shift); 394 return; 395 } 396 397 ksps = &smmu_info.sps[ik]; 398 if (ksps->slb_enc != qsps->slb_enc) { 399 error_setg(errp, 400 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 401 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 402 return; 403 } 404 405 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 406 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 407 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 408 break; 409 } 410 } 411 412 if (jk >= ARRAY_SIZE(ksps->enc)) { 413 error_setg(errp, "KVM doesn't support page shift %u/%u", 414 qsps->enc[jq].page_shift, qsps->page_shift); 415 return; 416 } 417 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 418 error_setg(errp, 419 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 420 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 421 qsps->page_shift, qsps->enc[jq].pte_enc); 422 return; 423 } 424 } 425 } 426 427 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 428 /* 429 * Mostly what guest pagesizes we can use are related to the 430 * host pages used to map guest RAM, which is handled in the 431 * platform code. Cache-Inhibited largepages (64k) however are 432 * used for I/O, so if they're mapped to the host at all it 433 * will be a normal mapping, not a special hugepage one used 434 * for RAM. 435 */ 436 if (getpagesize() < 0x10000) { 437 error_setg(errp, 438 "KVM can't supply 64kiB CI pages, which guest expects"); 439 } 440 } 441 } 442 #endif /* !defined (TARGET_PPC64) */ 443 444 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 445 { 446 return POWERPC_CPU(cpu)->vcpu_id; 447 } 448 449 /* 450 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 451 * only 1 watchpoint, so array size of 4 is sufficient for now. 452 */ 453 #define MAX_HW_BKPTS 4 454 455 static struct HWBreakpoint { 456 target_ulong addr; 457 int type; 458 } hw_debug_points[MAX_HW_BKPTS]; 459 460 static CPUWatchpoint hw_watchpoint; 461 462 /* Default there is no breakpoint and watchpoint supported */ 463 static int max_hw_breakpoint; 464 static int max_hw_watchpoint; 465 static int nb_hw_breakpoint; 466 static int nb_hw_watchpoint; 467 468 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 469 { 470 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 471 max_hw_breakpoint = 2; 472 max_hw_watchpoint = 2; 473 } 474 475 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 476 fprintf(stderr, "Error initializing h/w breakpoints\n"); 477 return; 478 } 479 } 480 481 int kvm_arch_init_vcpu(CPUState *cs) 482 { 483 PowerPCCPU *cpu = POWERPC_CPU(cs); 484 CPUPPCState *cenv = &cpu->env; 485 int ret; 486 487 /* Synchronize sregs with kvm */ 488 ret = kvm_arch_sync_sregs(cpu); 489 if (ret) { 490 if (ret == -EINVAL) { 491 error_report("Register sync failed... If you're using kvm-hv.ko," 492 " only \"-cpu host\" is possible"); 493 } 494 return ret; 495 } 496 497 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu); 498 499 switch (cenv->mmu_model) { 500 case POWERPC_MMU_BOOKE206: 501 /* This target supports access to KVM's guest TLB */ 502 ret = kvm_booke206_tlb_init(cpu); 503 break; 504 case POWERPC_MMU_2_07: 505 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 506 /* 507 * KVM-HV has transactional memory on POWER8 also without 508 * the KVM_CAP_PPC_HTM extension, so enable it here 509 * instead as long as it's availble to userspace on the 510 * host. 511 */ 512 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 513 cap_htm = true; 514 } 515 } 516 break; 517 default: 518 break; 519 } 520 521 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 522 kvmppc_hw_debug_points_init(cenv); 523 524 return ret; 525 } 526 527 int kvm_arch_destroy_vcpu(CPUState *cs) 528 { 529 return 0; 530 } 531 532 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 533 { 534 CPUPPCState *env = &cpu->env; 535 CPUState *cs = CPU(cpu); 536 struct kvm_dirty_tlb dirty_tlb; 537 unsigned char *bitmap; 538 int ret; 539 540 if (!env->kvm_sw_tlb) { 541 return; 542 } 543 544 bitmap = g_malloc((env->nb_tlb + 7) / 8); 545 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 546 547 dirty_tlb.bitmap = (uintptr_t)bitmap; 548 dirty_tlb.num_dirty = env->nb_tlb; 549 550 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 551 if (ret) { 552 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 553 __func__, strerror(-ret)); 554 } 555 556 g_free(bitmap); 557 } 558 559 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 560 { 561 PowerPCCPU *cpu = POWERPC_CPU(cs); 562 CPUPPCState *env = &cpu->env; 563 union { 564 uint32_t u32; 565 uint64_t u64; 566 } val; 567 struct kvm_one_reg reg = { 568 .id = id, 569 .addr = (uintptr_t) &val, 570 }; 571 int ret; 572 573 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 574 if (ret != 0) { 575 trace_kvm_failed_spr_get(spr, strerror(errno)); 576 } else { 577 switch (id & KVM_REG_SIZE_MASK) { 578 case KVM_REG_SIZE_U32: 579 env->spr[spr] = val.u32; 580 break; 581 582 case KVM_REG_SIZE_U64: 583 env->spr[spr] = val.u64; 584 break; 585 586 default: 587 /* Don't handle this size yet */ 588 abort(); 589 } 590 } 591 } 592 593 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 594 { 595 PowerPCCPU *cpu = POWERPC_CPU(cs); 596 CPUPPCState *env = &cpu->env; 597 union { 598 uint32_t u32; 599 uint64_t u64; 600 } val; 601 struct kvm_one_reg reg = { 602 .id = id, 603 .addr = (uintptr_t) &val, 604 }; 605 int ret; 606 607 switch (id & KVM_REG_SIZE_MASK) { 608 case KVM_REG_SIZE_U32: 609 val.u32 = env->spr[spr]; 610 break; 611 612 case KVM_REG_SIZE_U64: 613 val.u64 = env->spr[spr]; 614 break; 615 616 default: 617 /* Don't handle this size yet */ 618 abort(); 619 } 620 621 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 622 if (ret != 0) { 623 trace_kvm_failed_spr_set(spr, strerror(errno)); 624 } 625 } 626 627 static int kvm_put_fp(CPUState *cs) 628 { 629 PowerPCCPU *cpu = POWERPC_CPU(cs); 630 CPUPPCState *env = &cpu->env; 631 struct kvm_one_reg reg; 632 int i; 633 int ret; 634 635 if (env->insns_flags & PPC_FLOAT) { 636 uint64_t fpscr = env->fpscr; 637 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 638 639 reg.id = KVM_REG_PPC_FPSCR; 640 reg.addr = (uintptr_t)&fpscr; 641 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 642 if (ret < 0) { 643 trace_kvm_failed_fpscr_set(strerror(errno)); 644 return ret; 645 } 646 647 for (i = 0; i < 32; i++) { 648 uint64_t vsr[2]; 649 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 650 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 651 652 #ifdef HOST_WORDS_BIGENDIAN 653 vsr[0] = float64_val(*fpr); 654 vsr[1] = *vsrl; 655 #else 656 vsr[0] = *vsrl; 657 vsr[1] = float64_val(*fpr); 658 #endif 659 reg.addr = (uintptr_t) &vsr; 660 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 661 662 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 663 if (ret < 0) { 664 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 665 strerror(errno)); 666 return ret; 667 } 668 } 669 } 670 671 if (env->insns_flags & PPC_ALTIVEC) { 672 reg.id = KVM_REG_PPC_VSCR; 673 reg.addr = (uintptr_t)&env->vscr; 674 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 675 if (ret < 0) { 676 trace_kvm_failed_vscr_set(strerror(errno)); 677 return ret; 678 } 679 680 for (i = 0; i < 32; i++) { 681 reg.id = KVM_REG_PPC_VR(i); 682 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 683 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 684 if (ret < 0) { 685 trace_kvm_failed_vr_set(i, strerror(errno)); 686 return ret; 687 } 688 } 689 } 690 691 return 0; 692 } 693 694 static int kvm_get_fp(CPUState *cs) 695 { 696 PowerPCCPU *cpu = POWERPC_CPU(cs); 697 CPUPPCState *env = &cpu->env; 698 struct kvm_one_reg reg; 699 int i; 700 int ret; 701 702 if (env->insns_flags & PPC_FLOAT) { 703 uint64_t fpscr; 704 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 705 706 reg.id = KVM_REG_PPC_FPSCR; 707 reg.addr = (uintptr_t)&fpscr; 708 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 709 if (ret < 0) { 710 trace_kvm_failed_fpscr_get(strerror(errno)); 711 return ret; 712 } else { 713 env->fpscr = fpscr; 714 } 715 716 for (i = 0; i < 32; i++) { 717 uint64_t vsr[2]; 718 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 719 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 720 721 reg.addr = (uintptr_t) &vsr; 722 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 723 724 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 725 if (ret < 0) { 726 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 727 strerror(errno)); 728 return ret; 729 } else { 730 #ifdef HOST_WORDS_BIGENDIAN 731 *fpr = vsr[0]; 732 if (vsx) { 733 *vsrl = vsr[1]; 734 } 735 #else 736 *fpr = vsr[1]; 737 if (vsx) { 738 *vsrl = vsr[0]; 739 } 740 #endif 741 } 742 } 743 } 744 745 if (env->insns_flags & PPC_ALTIVEC) { 746 reg.id = KVM_REG_PPC_VSCR; 747 reg.addr = (uintptr_t)&env->vscr; 748 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 749 if (ret < 0) { 750 trace_kvm_failed_vscr_get(strerror(errno)); 751 return ret; 752 } 753 754 for (i = 0; i < 32; i++) { 755 reg.id = KVM_REG_PPC_VR(i); 756 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 757 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 758 if (ret < 0) { 759 trace_kvm_failed_vr_get(i, strerror(errno)); 760 return ret; 761 } 762 } 763 } 764 765 return 0; 766 } 767 768 #if defined(TARGET_PPC64) 769 static int kvm_get_vpa(CPUState *cs) 770 { 771 PowerPCCPU *cpu = POWERPC_CPU(cs); 772 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 773 struct kvm_one_reg reg; 774 int ret; 775 776 reg.id = KVM_REG_PPC_VPA_ADDR; 777 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 778 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 779 if (ret < 0) { 780 trace_kvm_failed_vpa_addr_get(strerror(errno)); 781 return ret; 782 } 783 784 assert((uintptr_t)&spapr_cpu->slb_shadow_size 785 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 786 reg.id = KVM_REG_PPC_VPA_SLB; 787 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 788 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 789 if (ret < 0) { 790 trace_kvm_failed_slb_get(strerror(errno)); 791 return ret; 792 } 793 794 assert((uintptr_t)&spapr_cpu->dtl_size 795 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 796 reg.id = KVM_REG_PPC_VPA_DTL; 797 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 798 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 799 if (ret < 0) { 800 trace_kvm_failed_dtl_get(strerror(errno)); 801 return ret; 802 } 803 804 return 0; 805 } 806 807 static int kvm_put_vpa(CPUState *cs) 808 { 809 PowerPCCPU *cpu = POWERPC_CPU(cs); 810 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 811 struct kvm_one_reg reg; 812 int ret; 813 814 /* 815 * SLB shadow or DTL can't be registered unless a master VPA is 816 * registered. That means when restoring state, if a VPA *is* 817 * registered, we need to set that up first. If not, we need to 818 * deregister the others before deregistering the master VPA 819 */ 820 assert(spapr_cpu->vpa_addr 821 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 822 823 if (spapr_cpu->vpa_addr) { 824 reg.id = KVM_REG_PPC_VPA_ADDR; 825 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 826 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 827 if (ret < 0) { 828 trace_kvm_failed_vpa_addr_set(strerror(errno)); 829 return ret; 830 } 831 } 832 833 assert((uintptr_t)&spapr_cpu->slb_shadow_size 834 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 835 reg.id = KVM_REG_PPC_VPA_SLB; 836 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 837 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 838 if (ret < 0) { 839 trace_kvm_failed_slb_set(strerror(errno)); 840 return ret; 841 } 842 843 assert((uintptr_t)&spapr_cpu->dtl_size 844 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 845 reg.id = KVM_REG_PPC_VPA_DTL; 846 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 847 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 848 if (ret < 0) { 849 trace_kvm_failed_dtl_set(strerror(errno)); 850 return ret; 851 } 852 853 if (!spapr_cpu->vpa_addr) { 854 reg.id = KVM_REG_PPC_VPA_ADDR; 855 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 856 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 857 if (ret < 0) { 858 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 859 return ret; 860 } 861 } 862 863 return 0; 864 } 865 #endif /* TARGET_PPC64 */ 866 867 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 868 { 869 CPUPPCState *env = &cpu->env; 870 struct kvm_sregs sregs; 871 int i; 872 873 sregs.pvr = env->spr[SPR_PVR]; 874 875 if (cpu->vhyp) { 876 PPCVirtualHypervisorClass *vhc = 877 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 878 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 879 } else { 880 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 881 } 882 883 /* Sync SLB */ 884 #ifdef TARGET_PPC64 885 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 886 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 887 if (env->slb[i].esid & SLB_ESID_V) { 888 sregs.u.s.ppc64.slb[i].slbe |= i; 889 } 890 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 891 } 892 #endif 893 894 /* Sync SRs */ 895 for (i = 0; i < 16; i++) { 896 sregs.u.s.ppc32.sr[i] = env->sr[i]; 897 } 898 899 /* Sync BATs */ 900 for (i = 0; i < 8; i++) { 901 /* Beware. We have to swap upper and lower bits here */ 902 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 903 | env->DBAT[1][i]; 904 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 905 | env->IBAT[1][i]; 906 } 907 908 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 909 } 910 911 int kvm_arch_put_registers(CPUState *cs, int level) 912 { 913 PowerPCCPU *cpu = POWERPC_CPU(cs); 914 CPUPPCState *env = &cpu->env; 915 struct kvm_regs regs; 916 int ret; 917 int i; 918 919 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 920 if (ret < 0) { 921 return ret; 922 } 923 924 regs.ctr = env->ctr; 925 regs.lr = env->lr; 926 regs.xer = cpu_read_xer(env); 927 regs.msr = env->msr; 928 regs.pc = env->nip; 929 930 regs.srr0 = env->spr[SPR_SRR0]; 931 regs.srr1 = env->spr[SPR_SRR1]; 932 933 regs.sprg0 = env->spr[SPR_SPRG0]; 934 regs.sprg1 = env->spr[SPR_SPRG1]; 935 regs.sprg2 = env->spr[SPR_SPRG2]; 936 regs.sprg3 = env->spr[SPR_SPRG3]; 937 regs.sprg4 = env->spr[SPR_SPRG4]; 938 regs.sprg5 = env->spr[SPR_SPRG5]; 939 regs.sprg6 = env->spr[SPR_SPRG6]; 940 regs.sprg7 = env->spr[SPR_SPRG7]; 941 942 regs.pid = env->spr[SPR_BOOKE_PID]; 943 944 for (i = 0; i < 32; i++) { 945 regs.gpr[i] = env->gpr[i]; 946 } 947 948 regs.cr = 0; 949 for (i = 0; i < 8; i++) { 950 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); 951 } 952 953 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 954 if (ret < 0) { 955 return ret; 956 } 957 958 kvm_put_fp(cs); 959 960 if (env->tlb_dirty) { 961 kvm_sw_tlb_put(cpu); 962 env->tlb_dirty = false; 963 } 964 965 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 966 ret = kvmppc_put_books_sregs(cpu); 967 if (ret < 0) { 968 return ret; 969 } 970 } 971 972 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 973 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 974 } 975 976 if (cap_one_reg) { 977 int i; 978 979 /* 980 * We deliberately ignore errors here, for kernels which have 981 * the ONE_REG calls, but don't support the specific 982 * registers, there's a reasonable chance things will still 983 * work, at least until we try to migrate. 984 */ 985 for (i = 0; i < 1024; i++) { 986 uint64_t id = env->spr_cb[i].one_reg_id; 987 988 if (id != 0) { 989 kvm_put_one_spr(cs, id, i); 990 } 991 } 992 993 #ifdef TARGET_PPC64 994 if (msr_ts) { 995 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 997 } 998 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1000 } 1001 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1002 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1003 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1004 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1005 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1006 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1007 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1008 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1009 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1010 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1011 } 1012 1013 if (cap_papr) { 1014 if (kvm_put_vpa(cs) < 0) { 1015 trace_kvm_failed_put_vpa(); 1016 } 1017 } 1018 1019 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1020 #endif /* TARGET_PPC64 */ 1021 } 1022 1023 return ret; 1024 } 1025 1026 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1027 { 1028 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1029 } 1030 1031 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1032 { 1033 CPUPPCState *env = &cpu->env; 1034 struct kvm_sregs sregs; 1035 int ret; 1036 1037 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1038 if (ret < 0) { 1039 return ret; 1040 } 1041 1042 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1043 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1044 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1045 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1046 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1047 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1048 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1049 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1050 env->spr[SPR_DECR] = sregs.u.e.dec; 1051 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1052 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1053 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1054 } 1055 1056 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1057 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1058 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1059 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1060 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1061 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1062 } 1063 1064 if (sregs.u.e.features & KVM_SREGS_E_64) { 1065 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1066 } 1067 1068 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1069 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1070 } 1071 1072 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1073 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1074 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1075 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1076 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1077 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1078 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1079 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1080 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1081 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1082 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1083 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1084 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1085 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1086 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1087 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1088 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1089 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1090 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1091 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1092 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1093 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1094 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1095 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1096 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1097 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1098 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1099 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1100 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1101 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1102 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1103 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1104 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1105 1106 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1107 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1108 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1109 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1110 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1111 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1112 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1113 } 1114 1115 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1116 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1117 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1118 } 1119 1120 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1121 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1122 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1123 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1124 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1125 } 1126 } 1127 1128 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1129 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1130 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1131 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1132 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1133 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1134 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1135 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1136 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1137 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1138 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1139 } 1140 1141 if (sregs.u.e.features & KVM_SREGS_EXP) { 1142 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1143 } 1144 1145 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1146 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1147 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1148 } 1149 1150 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1151 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1152 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1153 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1154 1155 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1156 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1157 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1158 } 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1165 { 1166 CPUPPCState *env = &cpu->env; 1167 struct kvm_sregs sregs; 1168 int ret; 1169 int i; 1170 1171 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1172 if (ret < 0) { 1173 return ret; 1174 } 1175 1176 if (!cpu->vhyp) { 1177 ppc_store_sdr1(env, sregs.u.s.sdr1); 1178 } 1179 1180 /* Sync SLB */ 1181 #ifdef TARGET_PPC64 1182 /* 1183 * The packed SLB array we get from KVM_GET_SREGS only contains 1184 * information about valid entries. So we flush our internal copy 1185 * to get rid of stale ones, then put all valid SLB entries back 1186 * in. 1187 */ 1188 memset(env->slb, 0, sizeof(env->slb)); 1189 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1190 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1191 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1192 /* 1193 * Only restore valid entries 1194 */ 1195 if (rb & SLB_ESID_V) { 1196 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1197 } 1198 } 1199 #endif 1200 1201 /* Sync SRs */ 1202 for (i = 0; i < 16; i++) { 1203 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1204 } 1205 1206 /* Sync BATs */ 1207 for (i = 0; i < 8; i++) { 1208 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1209 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1210 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1211 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1212 } 1213 1214 return 0; 1215 } 1216 1217 int kvm_arch_get_registers(CPUState *cs) 1218 { 1219 PowerPCCPU *cpu = POWERPC_CPU(cs); 1220 CPUPPCState *env = &cpu->env; 1221 struct kvm_regs regs; 1222 uint32_t cr; 1223 int i, ret; 1224 1225 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1226 if (ret < 0) { 1227 return ret; 1228 } 1229 1230 cr = regs.cr; 1231 for (i = 7; i >= 0; i--) { 1232 env->crf[i] = cr & 15; 1233 cr >>= 4; 1234 } 1235 1236 env->ctr = regs.ctr; 1237 env->lr = regs.lr; 1238 cpu_write_xer(env, regs.xer); 1239 env->msr = regs.msr; 1240 env->nip = regs.pc; 1241 1242 env->spr[SPR_SRR0] = regs.srr0; 1243 env->spr[SPR_SRR1] = regs.srr1; 1244 1245 env->spr[SPR_SPRG0] = regs.sprg0; 1246 env->spr[SPR_SPRG1] = regs.sprg1; 1247 env->spr[SPR_SPRG2] = regs.sprg2; 1248 env->spr[SPR_SPRG3] = regs.sprg3; 1249 env->spr[SPR_SPRG4] = regs.sprg4; 1250 env->spr[SPR_SPRG5] = regs.sprg5; 1251 env->spr[SPR_SPRG6] = regs.sprg6; 1252 env->spr[SPR_SPRG7] = regs.sprg7; 1253 1254 env->spr[SPR_BOOKE_PID] = regs.pid; 1255 1256 for (i = 0; i < 32; i++) { 1257 env->gpr[i] = regs.gpr[i]; 1258 } 1259 1260 kvm_get_fp(cs); 1261 1262 if (cap_booke_sregs) { 1263 ret = kvmppc_get_booke_sregs(cpu); 1264 if (ret < 0) { 1265 return ret; 1266 } 1267 } 1268 1269 if (cap_segstate) { 1270 ret = kvmppc_get_books_sregs(cpu); 1271 if (ret < 0) { 1272 return ret; 1273 } 1274 } 1275 1276 if (cap_hior) { 1277 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1278 } 1279 1280 if (cap_one_reg) { 1281 int i; 1282 1283 /* 1284 * We deliberately ignore errors here, for kernels which have 1285 * the ONE_REG calls, but don't support the specific 1286 * registers, there's a reasonable chance things will still 1287 * work, at least until we try to migrate. 1288 */ 1289 for (i = 0; i < 1024; i++) { 1290 uint64_t id = env->spr_cb[i].one_reg_id; 1291 1292 if (id != 0) { 1293 kvm_get_one_spr(cs, id, i); 1294 } 1295 } 1296 1297 #ifdef TARGET_PPC64 1298 if (msr_ts) { 1299 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1301 } 1302 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1303 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1304 } 1305 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1306 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1307 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1308 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1309 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1310 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1311 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1312 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1313 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1314 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1315 } 1316 1317 if (cap_papr) { 1318 if (kvm_get_vpa(cs) < 0) { 1319 trace_kvm_failed_get_vpa(); 1320 } 1321 } 1322 1323 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1324 #endif 1325 } 1326 1327 return 0; 1328 } 1329 1330 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1331 { 1332 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1333 1334 if (irq != PPC_INTERRUPT_EXT) { 1335 return 0; 1336 } 1337 1338 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { 1339 return 0; 1340 } 1341 1342 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1343 1344 return 0; 1345 } 1346 1347 #if defined(TARGET_PPC64) 1348 #define PPC_INPUT_INT PPC970_INPUT_INT 1349 #else 1350 #define PPC_INPUT_INT PPC6xx_INPUT_INT 1351 #endif 1352 1353 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1354 { 1355 PowerPCCPU *cpu = POWERPC_CPU(cs); 1356 CPUPPCState *env = &cpu->env; 1357 int r; 1358 unsigned irq; 1359 1360 qemu_mutex_lock_iothread(); 1361 1362 /* 1363 * PowerPC QEMU tracks the various core input pins (interrupt, 1364 * critical interrupt, reset, etc) in PPC-specific 1365 * env->irq_input_state. 1366 */ 1367 if (!cap_interrupt_level && 1368 run->ready_for_interrupt_injection && 1369 (cs->interrupt_request & CPU_INTERRUPT_HARD) && 1370 (env->irq_input_state & (1 << PPC_INPUT_INT))) 1371 { 1372 /* 1373 * For now KVM disregards the 'irq' argument. However, in the 1374 * future KVM could cache it in-kernel to avoid a heavyweight 1375 * exit when reading the UIC. 1376 */ 1377 irq = KVM_INTERRUPT_SET; 1378 1379 trace_kvm_injected_interrupt(irq); 1380 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); 1381 if (r < 0) { 1382 printf("cpu %d fail inject %x\n", cs->cpu_index, irq); 1383 } 1384 1385 /* Always wake up soon in case the interrupt was level based */ 1386 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1387 (NANOSECONDS_PER_SECOND / 50)); 1388 } 1389 1390 /* 1391 * We don't know if there are more interrupts pending after 1392 * this. However, the guest will return to userspace in the course 1393 * of handling this one anyways, so we will get a chance to 1394 * deliver the rest. 1395 */ 1396 1397 qemu_mutex_unlock_iothread(); 1398 } 1399 1400 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1401 { 1402 return MEMTXATTRS_UNSPECIFIED; 1403 } 1404 1405 int kvm_arch_process_async_events(CPUState *cs) 1406 { 1407 return cs->halted; 1408 } 1409 1410 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1411 { 1412 CPUState *cs = CPU(cpu); 1413 CPUPPCState *env = &cpu->env; 1414 1415 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { 1416 cs->halted = 1; 1417 cs->exception_index = EXCP_HLT; 1418 } 1419 1420 return 0; 1421 } 1422 1423 /* map dcr access to existing qemu dcr emulation */ 1424 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1425 uint32_t dcrn, uint32_t *data) 1426 { 1427 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1428 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1435 uint32_t dcrn, uint32_t data) 1436 { 1437 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1438 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1439 } 1440 1441 return 0; 1442 } 1443 1444 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1445 { 1446 /* Mixed endian case is not handled */ 1447 uint32_t sc = debug_inst_opcode; 1448 1449 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1450 sizeof(sc), 0) || 1451 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1452 return -EINVAL; 1453 } 1454 1455 return 0; 1456 } 1457 1458 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1459 { 1460 uint32_t sc; 1461 1462 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1463 sc != debug_inst_opcode || 1464 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1465 sizeof(sc), 1)) { 1466 return -EINVAL; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static int find_hw_breakpoint(target_ulong addr, int type) 1473 { 1474 int n; 1475 1476 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1477 <= ARRAY_SIZE(hw_debug_points)); 1478 1479 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1480 if (hw_debug_points[n].addr == addr && 1481 hw_debug_points[n].type == type) { 1482 return n; 1483 } 1484 } 1485 1486 return -1; 1487 } 1488 1489 static int find_hw_watchpoint(target_ulong addr, int *flag) 1490 { 1491 int n; 1492 1493 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1494 if (n >= 0) { 1495 *flag = BP_MEM_ACCESS; 1496 return n; 1497 } 1498 1499 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1500 if (n >= 0) { 1501 *flag = BP_MEM_WRITE; 1502 return n; 1503 } 1504 1505 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1506 if (n >= 0) { 1507 *flag = BP_MEM_READ; 1508 return n; 1509 } 1510 1511 return -1; 1512 } 1513 1514 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1515 target_ulong len, int type) 1516 { 1517 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1518 return -ENOBUFS; 1519 } 1520 1521 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1522 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1523 1524 switch (type) { 1525 case GDB_BREAKPOINT_HW: 1526 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1527 return -ENOBUFS; 1528 } 1529 1530 if (find_hw_breakpoint(addr, type) >= 0) { 1531 return -EEXIST; 1532 } 1533 1534 nb_hw_breakpoint++; 1535 break; 1536 1537 case GDB_WATCHPOINT_WRITE: 1538 case GDB_WATCHPOINT_READ: 1539 case GDB_WATCHPOINT_ACCESS: 1540 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1541 return -ENOBUFS; 1542 } 1543 1544 if (find_hw_breakpoint(addr, type) >= 0) { 1545 return -EEXIST; 1546 } 1547 1548 nb_hw_watchpoint++; 1549 break; 1550 1551 default: 1552 return -ENOSYS; 1553 } 1554 1555 return 0; 1556 } 1557 1558 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1559 target_ulong len, int type) 1560 { 1561 int n; 1562 1563 n = find_hw_breakpoint(addr, type); 1564 if (n < 0) { 1565 return -ENOENT; 1566 } 1567 1568 switch (type) { 1569 case GDB_BREAKPOINT_HW: 1570 nb_hw_breakpoint--; 1571 break; 1572 1573 case GDB_WATCHPOINT_WRITE: 1574 case GDB_WATCHPOINT_READ: 1575 case GDB_WATCHPOINT_ACCESS: 1576 nb_hw_watchpoint--; 1577 break; 1578 1579 default: 1580 return -ENOSYS; 1581 } 1582 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1583 1584 return 0; 1585 } 1586 1587 void kvm_arch_remove_all_hw_breakpoints(void) 1588 { 1589 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1590 } 1591 1592 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1593 { 1594 int n; 1595 1596 /* Software Breakpoint updates */ 1597 if (kvm_sw_breakpoints_active(cs)) { 1598 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1599 } 1600 1601 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1602 <= ARRAY_SIZE(hw_debug_points)); 1603 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1604 1605 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1606 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1607 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1608 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1609 switch (hw_debug_points[n].type) { 1610 case GDB_BREAKPOINT_HW: 1611 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1612 break; 1613 case GDB_WATCHPOINT_WRITE: 1614 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1615 break; 1616 case GDB_WATCHPOINT_READ: 1617 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1618 break; 1619 case GDB_WATCHPOINT_ACCESS: 1620 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1621 KVMPPC_DEBUG_WATCH_READ; 1622 break; 1623 default: 1624 cpu_abort(cs, "Unsupported breakpoint type\n"); 1625 } 1626 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1627 } 1628 } 1629 } 1630 1631 static int kvm_handle_hw_breakpoint(CPUState *cs, 1632 struct kvm_debug_exit_arch *arch_info) 1633 { 1634 int handle = 0; 1635 int n; 1636 int flag = 0; 1637 1638 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1639 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1640 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1641 if (n >= 0) { 1642 handle = 1; 1643 } 1644 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1645 KVMPPC_DEBUG_WATCH_WRITE)) { 1646 n = find_hw_watchpoint(arch_info->address, &flag); 1647 if (n >= 0) { 1648 handle = 1; 1649 cs->watchpoint_hit = &hw_watchpoint; 1650 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1651 hw_watchpoint.flags = flag; 1652 } 1653 } 1654 } 1655 return handle; 1656 } 1657 1658 static int kvm_handle_singlestep(void) 1659 { 1660 return 1; 1661 } 1662 1663 static int kvm_handle_sw_breakpoint(void) 1664 { 1665 return 1; 1666 } 1667 1668 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1669 { 1670 CPUState *cs = CPU(cpu); 1671 CPUPPCState *env = &cpu->env; 1672 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1673 1674 if (cs->singlestep_enabled) { 1675 return kvm_handle_singlestep(); 1676 } 1677 1678 if (arch_info->status) { 1679 return kvm_handle_hw_breakpoint(cs, arch_info); 1680 } 1681 1682 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1683 return kvm_handle_sw_breakpoint(); 1684 } 1685 1686 /* 1687 * QEMU is not able to handle debug exception, so inject 1688 * program exception to guest; 1689 * Yes program exception NOT debug exception !! 1690 * When QEMU is using debug resources then debug exception must 1691 * be always set. To achieve this we set MSR_DE and also set 1692 * MSRP_DEP so guest cannot change MSR_DE. 1693 * When emulating debug resource for guest we want guest 1694 * to control MSR_DE (enable/disable debug interrupt on need). 1695 * Supporting both configurations are NOT possible. 1696 * So the result is that we cannot share debug resources 1697 * between QEMU and Guest on BOOKE architecture. 1698 * In the current design QEMU gets the priority over guest, 1699 * this means that if QEMU is using debug resources then guest 1700 * cannot use them; 1701 * For software breakpoint QEMU uses a privileged instruction; 1702 * So there cannot be any reason that we are here for guest 1703 * set debug exception, only possibility is guest executed a 1704 * privileged / illegal instruction and that's why we are 1705 * injecting a program interrupt. 1706 */ 1707 cpu_synchronize_state(cs); 1708 /* 1709 * env->nip is PC, so increment this by 4 to use 1710 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1711 */ 1712 env->nip += 4; 1713 cs->exception_index = POWERPC_EXCP_PROGRAM; 1714 env->error_code = POWERPC_EXCP_INVAL; 1715 ppc_cpu_do_interrupt(cs); 1716 1717 return 0; 1718 } 1719 1720 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1721 { 1722 PowerPCCPU *cpu = POWERPC_CPU(cs); 1723 CPUPPCState *env = &cpu->env; 1724 int ret; 1725 1726 qemu_mutex_lock_iothread(); 1727 1728 switch (run->exit_reason) { 1729 case KVM_EXIT_DCR: 1730 if (run->dcr.is_write) { 1731 trace_kvm_handle_dcr_write(); 1732 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1733 } else { 1734 trace_kvm_handle_dcr_read(); 1735 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1736 } 1737 break; 1738 case KVM_EXIT_HLT: 1739 trace_kvm_handle_halt(); 1740 ret = kvmppc_handle_halt(cpu); 1741 break; 1742 #if defined(TARGET_PPC64) 1743 case KVM_EXIT_PAPR_HCALL: 1744 trace_kvm_handle_papr_hcall(); 1745 run->papr_hcall.ret = spapr_hypercall(cpu, 1746 run->papr_hcall.nr, 1747 run->papr_hcall.args); 1748 ret = 0; 1749 break; 1750 #endif 1751 case KVM_EXIT_EPR: 1752 trace_kvm_handle_epr(); 1753 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1754 ret = 0; 1755 break; 1756 case KVM_EXIT_WATCHDOG: 1757 trace_kvm_handle_watchdog_expiry(); 1758 watchdog_perform_action(); 1759 ret = 0; 1760 break; 1761 1762 case KVM_EXIT_DEBUG: 1763 trace_kvm_handle_debug_exception(); 1764 if (kvm_handle_debug(cpu, run)) { 1765 ret = EXCP_DEBUG; 1766 break; 1767 } 1768 /* re-enter, this exception was guest-internal */ 1769 ret = 0; 1770 break; 1771 1772 default: 1773 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1774 ret = -1; 1775 break; 1776 } 1777 1778 qemu_mutex_unlock_iothread(); 1779 return ret; 1780 } 1781 1782 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1783 { 1784 CPUState *cs = CPU(cpu); 1785 uint32_t bits = tsr_bits; 1786 struct kvm_one_reg reg = { 1787 .id = KVM_REG_PPC_OR_TSR, 1788 .addr = (uintptr_t) &bits, 1789 }; 1790 1791 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1792 } 1793 1794 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1795 { 1796 1797 CPUState *cs = CPU(cpu); 1798 uint32_t bits = tsr_bits; 1799 struct kvm_one_reg reg = { 1800 .id = KVM_REG_PPC_CLEAR_TSR, 1801 .addr = (uintptr_t) &bits, 1802 }; 1803 1804 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1805 } 1806 1807 int kvmppc_set_tcr(PowerPCCPU *cpu) 1808 { 1809 CPUState *cs = CPU(cpu); 1810 CPUPPCState *env = &cpu->env; 1811 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1812 1813 struct kvm_one_reg reg = { 1814 .id = KVM_REG_PPC_TCR, 1815 .addr = (uintptr_t) &tcr, 1816 }; 1817 1818 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1819 } 1820 1821 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1822 { 1823 CPUState *cs = CPU(cpu); 1824 int ret; 1825 1826 if (!kvm_enabled()) { 1827 return -1; 1828 } 1829 1830 if (!cap_ppc_watchdog) { 1831 printf("warning: KVM does not support watchdog"); 1832 return -1; 1833 } 1834 1835 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1836 if (ret < 0) { 1837 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1838 __func__, strerror(-ret)); 1839 return ret; 1840 } 1841 1842 return ret; 1843 } 1844 1845 static int read_cpuinfo(const char *field, char *value, int len) 1846 { 1847 FILE *f; 1848 int ret = -1; 1849 int field_len = strlen(field); 1850 char line[512]; 1851 1852 f = fopen("/proc/cpuinfo", "r"); 1853 if (!f) { 1854 return -1; 1855 } 1856 1857 do { 1858 if (!fgets(line, sizeof(line), f)) { 1859 break; 1860 } 1861 if (!strncmp(line, field, field_len)) { 1862 pstrcpy(value, len, line); 1863 ret = 0; 1864 break; 1865 } 1866 } while (*line); 1867 1868 fclose(f); 1869 1870 return ret; 1871 } 1872 1873 uint32_t kvmppc_get_tbfreq(void) 1874 { 1875 char line[512]; 1876 char *ns; 1877 uint32_t retval = NANOSECONDS_PER_SECOND; 1878 1879 if (read_cpuinfo("timebase", line, sizeof(line))) { 1880 return retval; 1881 } 1882 1883 ns = strchr(line, ':'); 1884 if (!ns) { 1885 return retval; 1886 } 1887 1888 ns++; 1889 1890 return atoi(ns); 1891 } 1892 1893 bool kvmppc_get_host_serial(char **value) 1894 { 1895 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1896 NULL); 1897 } 1898 1899 bool kvmppc_get_host_model(char **value) 1900 { 1901 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1902 } 1903 1904 /* Try to find a device tree node for a CPU with clock-frequency property */ 1905 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1906 { 1907 struct dirent *dirp; 1908 DIR *dp; 1909 1910 dp = opendir(PROC_DEVTREE_CPU); 1911 if (!dp) { 1912 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1913 return -1; 1914 } 1915 1916 buf[0] = '\0'; 1917 while ((dirp = readdir(dp)) != NULL) { 1918 FILE *f; 1919 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1920 dirp->d_name); 1921 f = fopen(buf, "r"); 1922 if (f) { 1923 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1924 fclose(f); 1925 break; 1926 } 1927 buf[0] = '\0'; 1928 } 1929 closedir(dp); 1930 if (buf[0] == '\0') { 1931 printf("Unknown host!\n"); 1932 return -1; 1933 } 1934 1935 return 0; 1936 } 1937 1938 static uint64_t kvmppc_read_int_dt(const char *filename) 1939 { 1940 union { 1941 uint32_t v32; 1942 uint64_t v64; 1943 } u; 1944 FILE *f; 1945 int len; 1946 1947 f = fopen(filename, "rb"); 1948 if (!f) { 1949 return -1; 1950 } 1951 1952 len = fread(&u, 1, sizeof(u), f); 1953 fclose(f); 1954 switch (len) { 1955 case 4: 1956 /* property is a 32-bit quantity */ 1957 return be32_to_cpu(u.v32); 1958 case 8: 1959 return be64_to_cpu(u.v64); 1960 } 1961 1962 return 0; 1963 } 1964 1965 /* 1966 * Read a CPU node property from the host device tree that's a single 1967 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1968 * (can't find or open the property, or doesn't understand the format) 1969 */ 1970 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1971 { 1972 char buf[PATH_MAX], *tmp; 1973 uint64_t val; 1974 1975 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1976 return -1; 1977 } 1978 1979 tmp = g_strdup_printf("%s/%s", buf, propname); 1980 val = kvmppc_read_int_dt(tmp); 1981 g_free(tmp); 1982 1983 return val; 1984 } 1985 1986 uint64_t kvmppc_get_clockfreq(void) 1987 { 1988 return kvmppc_read_int_cpu_dt("clock-frequency"); 1989 } 1990 1991 static int kvmppc_get_dec_bits(void) 1992 { 1993 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1994 1995 if (nr_bits > 0) { 1996 return nr_bits; 1997 } 1998 return 0; 1999 } 2000 2001 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 2002 { 2003 CPUState *cs = env_cpu(env); 2004 2005 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 2006 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 2007 return 0; 2008 } 2009 2010 return 1; 2011 } 2012 2013 int kvmppc_get_hasidle(CPUPPCState *env) 2014 { 2015 struct kvm_ppc_pvinfo pvinfo; 2016 2017 if (!kvmppc_get_pvinfo(env, &pvinfo) && 2018 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 2019 return 1; 2020 } 2021 2022 return 0; 2023 } 2024 2025 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 2026 { 2027 uint32_t *hc = (uint32_t *)buf; 2028 struct kvm_ppc_pvinfo pvinfo; 2029 2030 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 2031 memcpy(buf, pvinfo.hcall, buf_len); 2032 return 0; 2033 } 2034 2035 /* 2036 * Fallback to always fail hypercalls regardless of endianness: 2037 * 2038 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 2039 * li r3, -1 2040 * b .+8 (becomes nop in wrong endian) 2041 * bswap32(li r3, -1) 2042 */ 2043 2044 hc[0] = cpu_to_be32(0x08000048); 2045 hc[1] = cpu_to_be32(0x3860ffff); 2046 hc[2] = cpu_to_be32(0x48000008); 2047 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2048 2049 return 1; 2050 } 2051 2052 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2053 { 2054 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2055 } 2056 2057 void kvmppc_enable_logical_ci_hcalls(void) 2058 { 2059 /* 2060 * FIXME: it would be nice if we could detect the cases where 2061 * we're using a device which requires the in kernel 2062 * implementation of these hcalls, but the kernel lacks them and 2063 * produce a warning. 2064 */ 2065 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2066 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2067 } 2068 2069 void kvmppc_enable_set_mode_hcall(void) 2070 { 2071 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2072 } 2073 2074 void kvmppc_enable_clear_ref_mod_hcalls(void) 2075 { 2076 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2077 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2078 } 2079 2080 void kvmppc_enable_h_page_init(void) 2081 { 2082 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2083 } 2084 2085 void kvmppc_set_papr(PowerPCCPU *cpu) 2086 { 2087 CPUState *cs = CPU(cpu); 2088 int ret; 2089 2090 if (!kvm_enabled()) { 2091 return; 2092 } 2093 2094 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2095 if (ret) { 2096 error_report("This vCPU type or KVM version does not support PAPR"); 2097 exit(1); 2098 } 2099 2100 /* 2101 * Update the capability flag so we sync the right information 2102 * with kvm 2103 */ 2104 cap_papr = 1; 2105 } 2106 2107 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2108 { 2109 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2110 } 2111 2112 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2113 { 2114 CPUState *cs = CPU(cpu); 2115 int ret; 2116 2117 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2118 if (ret && mpic_proxy) { 2119 error_report("This KVM version does not support EPR"); 2120 exit(1); 2121 } 2122 } 2123 2124 int kvmppc_smt_threads(void) 2125 { 2126 return cap_ppc_smt ? cap_ppc_smt : 1; 2127 } 2128 2129 int kvmppc_set_smt_threads(int smt) 2130 { 2131 int ret; 2132 2133 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2134 if (!ret) { 2135 cap_ppc_smt = smt; 2136 } 2137 return ret; 2138 } 2139 2140 void kvmppc_hint_smt_possible(Error **errp) 2141 { 2142 int i; 2143 GString *g; 2144 char *s; 2145 2146 assert(kvm_enabled()); 2147 if (cap_ppc_smt_possible) { 2148 g = g_string_new("Available VSMT modes:"); 2149 for (i = 63; i >= 0; i--) { 2150 if ((1UL << i) & cap_ppc_smt_possible) { 2151 g_string_append_printf(g, " %lu", (1UL << i)); 2152 } 2153 } 2154 s = g_string_free(g, false); 2155 error_append_hint(errp, "%s.\n", s); 2156 g_free(s); 2157 } else { 2158 error_append_hint(errp, 2159 "This KVM seems to be too old to support VSMT.\n"); 2160 } 2161 } 2162 2163 2164 #ifdef TARGET_PPC64 2165 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) 2166 { 2167 struct kvm_ppc_smmu_info info; 2168 long rampagesize, best_page_shift; 2169 int i; 2170 2171 /* 2172 * Find the largest hardware supported page size that's less than 2173 * or equal to the (logical) backing page size of guest RAM 2174 */ 2175 kvm_get_smmu_info(&info, &error_fatal); 2176 rampagesize = qemu_minrampagesize(); 2177 best_page_shift = 0; 2178 2179 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2180 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2181 2182 if (!sps->page_shift) { 2183 continue; 2184 } 2185 2186 if ((sps->page_shift > best_page_shift) 2187 && ((1UL << sps->page_shift) <= rampagesize)) { 2188 best_page_shift = sps->page_shift; 2189 } 2190 } 2191 2192 return MIN(current_size, 2193 1ULL << (best_page_shift + hash_shift - 7)); 2194 } 2195 #endif 2196 2197 bool kvmppc_spapr_use_multitce(void) 2198 { 2199 return cap_spapr_multitce; 2200 } 2201 2202 int kvmppc_spapr_enable_inkernel_multitce(void) 2203 { 2204 int ret; 2205 2206 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2207 H_PUT_TCE_INDIRECT, 1); 2208 if (!ret) { 2209 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2210 H_STUFF_TCE, 1); 2211 } 2212 2213 return ret; 2214 } 2215 2216 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2217 uint64_t bus_offset, uint32_t nb_table, 2218 int *pfd, bool need_vfio) 2219 { 2220 long len; 2221 int fd; 2222 void *table; 2223 2224 /* 2225 * Must set fd to -1 so we don't try to munmap when called for 2226 * destroying the table, which the upper layers -will- do 2227 */ 2228 *pfd = -1; 2229 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2230 return NULL; 2231 } 2232 2233 if (cap_spapr_tce_64) { 2234 struct kvm_create_spapr_tce_64 args = { 2235 .liobn = liobn, 2236 .page_shift = page_shift, 2237 .offset = bus_offset >> page_shift, 2238 .size = nb_table, 2239 .flags = 0 2240 }; 2241 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2242 if (fd < 0) { 2243 fprintf(stderr, 2244 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2245 liobn); 2246 return NULL; 2247 } 2248 } else if (cap_spapr_tce) { 2249 uint64_t window_size = (uint64_t) nb_table << page_shift; 2250 struct kvm_create_spapr_tce args = { 2251 .liobn = liobn, 2252 .window_size = window_size, 2253 }; 2254 if ((window_size != args.window_size) || bus_offset) { 2255 return NULL; 2256 } 2257 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2258 if (fd < 0) { 2259 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2260 liobn); 2261 return NULL; 2262 } 2263 } else { 2264 return NULL; 2265 } 2266 2267 len = nb_table * sizeof(uint64_t); 2268 /* FIXME: round this up to page size */ 2269 2270 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2271 if (table == MAP_FAILED) { 2272 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2273 liobn); 2274 close(fd); 2275 return NULL; 2276 } 2277 2278 *pfd = fd; 2279 return table; 2280 } 2281 2282 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2283 { 2284 long len; 2285 2286 if (fd < 0) { 2287 return -1; 2288 } 2289 2290 len = nb_table * sizeof(uint64_t); 2291 if ((munmap(table, len) < 0) || 2292 (close(fd) < 0)) { 2293 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2294 strerror(errno)); 2295 /* Leak the table */ 2296 } 2297 2298 return 0; 2299 } 2300 2301 int kvmppc_reset_htab(int shift_hint) 2302 { 2303 uint32_t shift = shift_hint; 2304 2305 if (!kvm_enabled()) { 2306 /* Full emulation, tell caller to allocate htab itself */ 2307 return 0; 2308 } 2309 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2310 int ret; 2311 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2312 if (ret == -ENOTTY) { 2313 /* 2314 * At least some versions of PR KVM advertise the 2315 * capability, but don't implement the ioctl(). Oops. 2316 * Return 0 so that we allocate the htab in qemu, as is 2317 * correct for PR. 2318 */ 2319 return 0; 2320 } else if (ret < 0) { 2321 return ret; 2322 } 2323 return shift; 2324 } 2325 2326 /* 2327 * We have a kernel that predates the htab reset calls. For PR 2328 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2329 * this era, it has allocated a 16MB fixed size hash table 2330 * already. 2331 */ 2332 if (kvmppc_is_pr(kvm_state)) { 2333 /* PR - tell caller to allocate htab */ 2334 return 0; 2335 } else { 2336 /* HV - assume 16MB kernel allocated htab */ 2337 return 24; 2338 } 2339 } 2340 2341 static inline uint32_t mfpvr(void) 2342 { 2343 uint32_t pvr; 2344 2345 asm ("mfpvr %0" 2346 : "=r"(pvr)); 2347 return pvr; 2348 } 2349 2350 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2351 { 2352 if (on) { 2353 *word |= flags; 2354 } else { 2355 *word &= ~flags; 2356 } 2357 } 2358 2359 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2360 { 2361 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2362 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2363 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2364 2365 /* Now fix up the class with information we can query from the host */ 2366 pcc->pvr = mfpvr(); 2367 2368 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2369 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2370 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2371 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2372 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2373 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2374 2375 if (dcache_size != -1) { 2376 pcc->l1_dcache_size = dcache_size; 2377 } 2378 2379 if (icache_size != -1) { 2380 pcc->l1_icache_size = icache_size; 2381 } 2382 2383 #if defined(TARGET_PPC64) 2384 pcc->radix_page_info = kvm_get_radix_page_info(); 2385 2386 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2387 /* 2388 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2389 * compliant. More importantly, advertising ISA 3.00 2390 * architected mode may prevent guests from activating 2391 * necessary DD1 workarounds. 2392 */ 2393 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2394 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2395 } 2396 #endif /* defined(TARGET_PPC64) */ 2397 } 2398 2399 bool kvmppc_has_cap_epr(void) 2400 { 2401 return cap_epr; 2402 } 2403 2404 bool kvmppc_has_cap_fixup_hcalls(void) 2405 { 2406 return cap_fixup_hcalls; 2407 } 2408 2409 bool kvmppc_has_cap_htm(void) 2410 { 2411 return cap_htm; 2412 } 2413 2414 bool kvmppc_has_cap_mmu_radix(void) 2415 { 2416 return cap_mmu_radix; 2417 } 2418 2419 bool kvmppc_has_cap_mmu_hash_v3(void) 2420 { 2421 return cap_mmu_hash_v3; 2422 } 2423 2424 static bool kvmppc_power8_host(void) 2425 { 2426 bool ret = false; 2427 #ifdef TARGET_PPC64 2428 { 2429 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2430 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2431 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2432 (base_pvr == CPU_POWERPC_POWER8_BASE); 2433 } 2434 #endif /* TARGET_PPC64 */ 2435 return ret; 2436 } 2437 2438 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2439 { 2440 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2441 2442 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2443 return 2; 2444 } else if ((!l1d_thread_priv_req || 2445 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2446 (c.character & c.character_mask 2447 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2448 return 1; 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2455 { 2456 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2457 return 2; 2458 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2459 return 1; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2466 { 2467 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2468 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2469 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2470 return SPAPR_CAP_FIXED_NA; 2471 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2472 return SPAPR_CAP_WORKAROUND; 2473 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2474 return SPAPR_CAP_FIXED_CCD; 2475 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2476 return SPAPR_CAP_FIXED_IBS; 2477 } 2478 2479 return 0; 2480 } 2481 2482 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2483 { 2484 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2485 return 1; 2486 } 2487 return 0; 2488 } 2489 2490 bool kvmppc_has_cap_xive(void) 2491 { 2492 return cap_xive; 2493 } 2494 2495 static void kvmppc_get_cpu_characteristics(KVMState *s) 2496 { 2497 struct kvm_ppc_cpu_char c; 2498 int ret; 2499 2500 /* Assume broken */ 2501 cap_ppc_safe_cache = 0; 2502 cap_ppc_safe_bounds_check = 0; 2503 cap_ppc_safe_indirect_branch = 0; 2504 2505 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2506 if (!ret) { 2507 return; 2508 } 2509 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2510 if (ret < 0) { 2511 return; 2512 } 2513 2514 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2515 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2516 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2517 cap_ppc_count_cache_flush_assist = 2518 parse_cap_ppc_count_cache_flush_assist(c); 2519 } 2520 2521 int kvmppc_get_cap_safe_cache(void) 2522 { 2523 return cap_ppc_safe_cache; 2524 } 2525 2526 int kvmppc_get_cap_safe_bounds_check(void) 2527 { 2528 return cap_ppc_safe_bounds_check; 2529 } 2530 2531 int kvmppc_get_cap_safe_indirect_branch(void) 2532 { 2533 return cap_ppc_safe_indirect_branch; 2534 } 2535 2536 int kvmppc_get_cap_count_cache_flush_assist(void) 2537 { 2538 return cap_ppc_count_cache_flush_assist; 2539 } 2540 2541 bool kvmppc_has_cap_nested_kvm_hv(void) 2542 { 2543 return !!cap_ppc_nested_kvm_hv; 2544 } 2545 2546 int kvmppc_set_cap_nested_kvm_hv(int enable) 2547 { 2548 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2549 } 2550 2551 bool kvmppc_has_cap_spapr_vfio(void) 2552 { 2553 return cap_spapr_vfio; 2554 } 2555 2556 int kvmppc_get_cap_large_decr(void) 2557 { 2558 return cap_large_decr; 2559 } 2560 2561 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2562 { 2563 CPUState *cs = CPU(cpu); 2564 uint64_t lpcr; 2565 2566 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2567 /* Do we need to modify the LPCR? */ 2568 if (!!(lpcr & LPCR_LD) != !!enable) { 2569 if (enable) { 2570 lpcr |= LPCR_LD; 2571 } else { 2572 lpcr &= ~LPCR_LD; 2573 } 2574 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2575 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2576 2577 if (!!(lpcr & LPCR_LD) != !!enable) { 2578 return -1; 2579 } 2580 } 2581 2582 return 0; 2583 } 2584 2585 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2586 { 2587 uint32_t host_pvr = mfpvr(); 2588 PowerPCCPUClass *pvr_pcc; 2589 2590 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2591 if (pvr_pcc == NULL) { 2592 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2593 } 2594 2595 return pvr_pcc; 2596 } 2597 2598 static int kvm_ppc_register_host_cpu_type(MachineState *ms) 2599 { 2600 TypeInfo type_info = { 2601 .name = TYPE_HOST_POWERPC_CPU, 2602 .class_init = kvmppc_host_cpu_class_init, 2603 }; 2604 MachineClass *mc = MACHINE_GET_CLASS(ms); 2605 PowerPCCPUClass *pvr_pcc; 2606 ObjectClass *oc; 2607 DeviceClass *dc; 2608 int i; 2609 2610 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2611 if (pvr_pcc == NULL) { 2612 return -1; 2613 } 2614 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2615 type_register(&type_info); 2616 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) { 2617 /* override TCG default cpu type with 'host' cpu model */ 2618 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2619 } 2620 2621 oc = object_class_by_name(type_info.name); 2622 g_assert(oc); 2623 2624 /* 2625 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2626 * we want "POWER8" to be a "family" alias that points to the current 2627 * host CPU type, too) 2628 */ 2629 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2630 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2631 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2632 char *suffix; 2633 2634 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2635 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2636 if (suffix) { 2637 *suffix = 0; 2638 } 2639 break; 2640 } 2641 } 2642 2643 return 0; 2644 } 2645 2646 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2647 { 2648 struct kvm_rtas_token_args args = { 2649 .token = token, 2650 }; 2651 2652 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2653 return -ENOENT; 2654 } 2655 2656 strncpy(args.name, function, sizeof(args.name) - 1); 2657 2658 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2659 } 2660 2661 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2662 { 2663 struct kvm_get_htab_fd s = { 2664 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2665 .start_index = index, 2666 }; 2667 int ret; 2668 2669 if (!cap_htab_fd) { 2670 error_setg(errp, "KVM version doesn't support %s the HPT", 2671 write ? "writing" : "reading"); 2672 return -ENOTSUP; 2673 } 2674 2675 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2676 if (ret < 0) { 2677 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2678 write ? "writing" : "reading", write ? "to" : "from", 2679 strerror(errno)); 2680 return -errno; 2681 } 2682 2683 return ret; 2684 } 2685 2686 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2687 { 2688 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2689 uint8_t buf[bufsize]; 2690 ssize_t rc; 2691 2692 do { 2693 rc = read(fd, buf, bufsize); 2694 if (rc < 0) { 2695 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2696 strerror(errno)); 2697 return rc; 2698 } else if (rc) { 2699 uint8_t *buffer = buf; 2700 ssize_t n = rc; 2701 while (n) { 2702 struct kvm_get_htab_header *head = 2703 (struct kvm_get_htab_header *) buffer; 2704 size_t chunksize = sizeof(*head) + 2705 HASH_PTE_SIZE_64 * head->n_valid; 2706 2707 qemu_put_be32(f, head->index); 2708 qemu_put_be16(f, head->n_valid); 2709 qemu_put_be16(f, head->n_invalid); 2710 qemu_put_buffer(f, (void *)(head + 1), 2711 HASH_PTE_SIZE_64 * head->n_valid); 2712 2713 buffer += chunksize; 2714 n -= chunksize; 2715 } 2716 } 2717 } while ((rc != 0) 2718 && ((max_ns < 0) || 2719 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2720 2721 return (rc == 0) ? 1 : 0; 2722 } 2723 2724 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2725 uint16_t n_valid, uint16_t n_invalid) 2726 { 2727 struct kvm_get_htab_header *buf; 2728 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2729 ssize_t rc; 2730 2731 buf = alloca(chunksize); 2732 buf->index = index; 2733 buf->n_valid = n_valid; 2734 buf->n_invalid = n_invalid; 2735 2736 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2737 2738 rc = write(fd, buf, chunksize); 2739 if (rc < 0) { 2740 fprintf(stderr, "Error writing KVM hash table: %s\n", 2741 strerror(errno)); 2742 return rc; 2743 } 2744 if (rc != chunksize) { 2745 /* We should never get a short write on a single chunk */ 2746 fprintf(stderr, "Short write, restoring KVM hash table\n"); 2747 return -1; 2748 } 2749 return 0; 2750 } 2751 2752 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2753 { 2754 return true; 2755 } 2756 2757 void kvm_arch_init_irq_routing(KVMState *s) 2758 { 2759 } 2760 2761 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2762 { 2763 int fd, rc; 2764 int i; 2765 2766 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2767 2768 i = 0; 2769 while (i < n) { 2770 struct kvm_get_htab_header *hdr; 2771 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2772 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2773 2774 rc = read(fd, buf, sizeof(buf)); 2775 if (rc < 0) { 2776 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2777 } 2778 2779 hdr = (struct kvm_get_htab_header *)buf; 2780 while ((i < n) && ((char *)hdr < (buf + rc))) { 2781 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2782 2783 if (hdr->index != (ptex + i)) { 2784 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2785 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2786 } 2787 2788 if (n - i < valid) { 2789 valid = n - i; 2790 } 2791 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2792 i += valid; 2793 2794 if ((n - i) < invalid) { 2795 invalid = n - i; 2796 } 2797 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2798 i += invalid; 2799 2800 hdr = (struct kvm_get_htab_header *) 2801 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2802 } 2803 } 2804 2805 close(fd); 2806 } 2807 2808 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2809 { 2810 int fd, rc; 2811 struct { 2812 struct kvm_get_htab_header hdr; 2813 uint64_t pte0; 2814 uint64_t pte1; 2815 } buf; 2816 2817 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2818 2819 buf.hdr.n_valid = 1; 2820 buf.hdr.n_invalid = 0; 2821 buf.hdr.index = ptex; 2822 buf.pte0 = cpu_to_be64(pte0); 2823 buf.pte1 = cpu_to_be64(pte1); 2824 2825 rc = write(fd, &buf, sizeof(buf)); 2826 if (rc != sizeof(buf)) { 2827 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2828 } 2829 close(fd); 2830 } 2831 2832 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2833 uint64_t address, uint32_t data, PCIDevice *dev) 2834 { 2835 return 0; 2836 } 2837 2838 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2839 int vector, PCIDevice *dev) 2840 { 2841 return 0; 2842 } 2843 2844 int kvm_arch_release_virq_post(int virq) 2845 { 2846 return 0; 2847 } 2848 2849 int kvm_arch_msi_data_to_gsi(uint32_t data) 2850 { 2851 return data & 0xffff; 2852 } 2853 2854 int kvmppc_enable_hwrng(void) 2855 { 2856 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2857 return -1; 2858 } 2859 2860 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2861 } 2862 2863 void kvmppc_check_papr_resize_hpt(Error **errp) 2864 { 2865 if (!kvm_enabled()) { 2866 return; /* No KVM, we're good */ 2867 } 2868 2869 if (cap_resize_hpt) { 2870 return; /* Kernel has explicit support, we're good */ 2871 } 2872 2873 /* Otherwise fallback on looking for PR KVM */ 2874 if (kvmppc_is_pr(kvm_state)) { 2875 return; 2876 } 2877 2878 error_setg(errp, 2879 "Hash page table resizing not available with this KVM version"); 2880 } 2881 2882 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2883 { 2884 CPUState *cs = CPU(cpu); 2885 struct kvm_ppc_resize_hpt rhpt = { 2886 .flags = flags, 2887 .shift = shift, 2888 }; 2889 2890 if (!cap_resize_hpt) { 2891 return -ENOSYS; 2892 } 2893 2894 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2895 } 2896 2897 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2898 { 2899 CPUState *cs = CPU(cpu); 2900 struct kvm_ppc_resize_hpt rhpt = { 2901 .flags = flags, 2902 .shift = shift, 2903 }; 2904 2905 if (!cap_resize_hpt) { 2906 return -ENOSYS; 2907 } 2908 2909 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2910 } 2911 2912 /* 2913 * This is a helper function to detect a post migration scenario 2914 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2915 * the guest kernel can't handle a PVR value other than the actual host 2916 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2917 * 2918 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2919 * (so, we're HV), return true. The workaround itself is done in 2920 * cpu_post_load. 2921 * 2922 * The order here is important: we'll only check for KVM PR as a 2923 * fallback if the guest kernel can't handle the situation itself. 2924 * We need to avoid as much as possible querying the running KVM type 2925 * in QEMU level. 2926 */ 2927 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2928 { 2929 CPUState *cs = CPU(cpu); 2930 2931 if (!kvm_enabled()) { 2932 return false; 2933 } 2934 2935 if (cap_ppc_pvr_compat) { 2936 return false; 2937 } 2938 2939 return !kvmppc_is_pr(cs->kvm_state); 2940 } 2941 2942 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2943 { 2944 CPUState *cs = CPU(cpu); 2945 2946 if (kvm_enabled()) { 2947 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2948 } 2949 } 2950 2951 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2952 { 2953 CPUState *cs = CPU(cpu); 2954 2955 if (kvm_enabled()) { 2956 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2957 } 2958 } 2959