1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu-common.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "cpu.h" 28 #include "cpu-models.h" 29 #include "qemu/timer.h" 30 #include "sysemu/hw_accel.h" 31 #include "kvm_ppc.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/device_tree.h" 34 #include "mmu-hash64.h" 35 36 #include "hw/sysbus.h" 37 #include "hw/ppc/spapr.h" 38 #include "hw/ppc/spapr_cpu_core.h" 39 #include "hw/hw.h" 40 #include "hw/ppc/ppc.h" 41 #include "migration/qemu-file-types.h" 42 #include "sysemu/watchdog.h" 43 #include "trace.h" 44 #include "exec/gdbstub.h" 45 #include "exec/memattrs.h" 46 #include "exec/ram_addr.h" 47 #include "sysemu/hostmem.h" 48 #include "qemu/cutils.h" 49 #include "qemu/main-loop.h" 50 #include "qemu/mmap-alloc.h" 51 #include "elf.h" 52 #include "sysemu/kvm_int.h" 53 54 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 55 56 #define DEBUG_RETURN_GUEST 0 57 #define DEBUG_RETURN_GDB 1 58 59 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 60 KVM_CAP_LAST_INFO 61 }; 62 63 static int cap_interrupt_unset; 64 static int cap_segstate; 65 static int cap_booke_sregs; 66 static int cap_ppc_smt; 67 static int cap_ppc_smt_possible; 68 static int cap_spapr_tce; 69 static int cap_spapr_tce_64; 70 static int cap_spapr_multitce; 71 static int cap_spapr_vfio; 72 static int cap_hior; 73 static int cap_one_reg; 74 static int cap_epr; 75 static int cap_ppc_watchdog; 76 static int cap_papr; 77 static int cap_htab_fd; 78 static int cap_fixup_hcalls; 79 static int cap_htm; /* Hardware transactional memory support */ 80 static int cap_mmu_radix; 81 static int cap_mmu_hash_v3; 82 static int cap_xive; 83 static int cap_resize_hpt; 84 static int cap_ppc_pvr_compat; 85 static int cap_ppc_safe_cache; 86 static int cap_ppc_safe_bounds_check; 87 static int cap_ppc_safe_indirect_branch; 88 static int cap_ppc_count_cache_flush_assist; 89 static int cap_ppc_nested_kvm_hv; 90 static int cap_large_decr; 91 92 static uint32_t debug_inst_opcode; 93 94 /* 95 * Check whether we are running with KVM-PR (instead of KVM-HV). This 96 * should only be used for fallback tests - generally we should use 97 * explicit capabilities for the features we want, rather than 98 * assuming what is/isn't available depending on the KVM variant. 99 */ 100 static bool kvmppc_is_pr(KVMState *ks) 101 { 102 /* Assume KVM-PR if the GET_PVINFO capability is available */ 103 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 104 } 105 106 static int kvm_ppc_register_host_cpu_type(void); 107 static void kvmppc_get_cpu_characteristics(KVMState *s); 108 static int kvmppc_get_dec_bits(void); 109 110 int kvm_arch_init(MachineState *ms, KVMState *s) 111 { 112 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 113 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 114 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 115 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 116 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 117 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 118 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 119 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 120 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 121 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 122 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 123 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 124 /* 125 * Note: we don't set cap_papr here, because this capability is 126 * only activated after this by kvmppc_set_papr() 127 */ 128 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 129 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 130 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 131 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 132 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 133 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 134 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 135 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 136 kvmppc_get_cpu_characteristics(s); 137 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 138 cap_large_decr = kvmppc_get_dec_bits(); 139 /* 140 * Note: setting it to false because there is not such capability 141 * in KVM at this moment. 142 * 143 * TODO: call kvm_vm_check_extension() with the right capability 144 * after the kernel starts implementing it. 145 */ 146 cap_ppc_pvr_compat = false; 147 148 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 149 error_report("KVM: Host kernel doesn't have level irq capability"); 150 exit(1); 151 } 152 153 kvm_ppc_register_host_cpu_type(); 154 155 return 0; 156 } 157 158 int kvm_arch_irqchip_create(KVMState *s) 159 { 160 return 0; 161 } 162 163 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 164 { 165 CPUPPCState *cenv = &cpu->env; 166 CPUState *cs = CPU(cpu); 167 struct kvm_sregs sregs; 168 int ret; 169 170 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 171 /* 172 * What we're really trying to say is "if we're on BookE, we 173 * use the native PVR for now". This is the only sane way to 174 * check it though, so we potentially confuse users that they 175 * can run BookE guests on BookS. Let's hope nobody dares 176 * enough :) 177 */ 178 return 0; 179 } else { 180 if (!cap_segstate) { 181 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 182 return -ENOSYS; 183 } 184 } 185 186 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 187 if (ret) { 188 return ret; 189 } 190 191 sregs.pvr = cenv->spr[SPR_PVR]; 192 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 193 } 194 195 /* Set up a shared TLB array with KVM */ 196 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 197 { 198 CPUPPCState *env = &cpu->env; 199 CPUState *cs = CPU(cpu); 200 struct kvm_book3e_206_tlb_params params = {}; 201 struct kvm_config_tlb cfg = {}; 202 unsigned int entries = 0; 203 int ret, i; 204 205 if (!kvm_enabled() || 206 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 207 return 0; 208 } 209 210 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 211 212 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 213 params.tlb_sizes[i] = booke206_tlb_size(env, i); 214 params.tlb_ways[i] = booke206_tlb_ways(env, i); 215 entries += params.tlb_sizes[i]; 216 } 217 218 assert(entries == env->nb_tlb); 219 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 220 221 env->tlb_dirty = true; 222 223 cfg.array = (uintptr_t)env->tlb.tlbm; 224 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 225 cfg.params = (uintptr_t)¶ms; 226 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 227 228 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 229 if (ret < 0) { 230 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 231 __func__, strerror(-ret)); 232 return ret; 233 } 234 235 env->kvm_sw_tlb = true; 236 return 0; 237 } 238 239 240 #if defined(TARGET_PPC64) 241 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 242 { 243 int ret; 244 245 assert(kvm_state != NULL); 246 247 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 248 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 249 error_append_hint(errp, "Consider switching to a newer KVM\n"); 250 return; 251 } 252 253 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 254 if (ret == 0) { 255 return; 256 } 257 258 error_setg_errno(errp, -ret, 259 "KVM failed to provide the MMU features it supports"); 260 } 261 262 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 263 { 264 KVMState *s = KVM_STATE(current_accel()); 265 struct ppc_radix_page_info *radix_page_info; 266 struct kvm_ppc_rmmu_info rmmu_info; 267 int i; 268 269 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 270 return NULL; 271 } 272 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 273 return NULL; 274 } 275 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 276 radix_page_info->count = 0; 277 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 278 if (rmmu_info.ap_encodings[i]) { 279 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 280 radix_page_info->count++; 281 } 282 } 283 return radix_page_info; 284 } 285 286 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 287 bool radix, bool gtse, 288 uint64_t proc_tbl) 289 { 290 CPUState *cs = CPU(cpu); 291 int ret; 292 uint64_t flags = 0; 293 struct kvm_ppc_mmuv3_cfg cfg = { 294 .process_table = proc_tbl, 295 }; 296 297 if (radix) { 298 flags |= KVM_PPC_MMUV3_RADIX; 299 } 300 if (gtse) { 301 flags |= KVM_PPC_MMUV3_GTSE; 302 } 303 cfg.flags = flags; 304 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 305 switch (ret) { 306 case 0: 307 return H_SUCCESS; 308 case -EINVAL: 309 return H_PARAMETER; 310 case -ENODEV: 311 return H_NOT_AVAILABLE; 312 default: 313 return H_HARDWARE; 314 } 315 } 316 317 bool kvmppc_hpt_needs_host_contiguous_pages(void) 318 { 319 static struct kvm_ppc_smmu_info smmu_info; 320 321 if (!kvm_enabled()) { 322 return false; 323 } 324 325 kvm_get_smmu_info(&smmu_info, &error_fatal); 326 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 327 } 328 329 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 330 { 331 struct kvm_ppc_smmu_info smmu_info; 332 int iq, ik, jq, jk; 333 Error *local_err = NULL; 334 335 /* For now, we only have anything to check on hash64 MMUs */ 336 if (!cpu->hash64_opts || !kvm_enabled()) { 337 return; 338 } 339 340 kvm_get_smmu_info(&smmu_info, &local_err); 341 if (local_err) { 342 error_propagate(errp, local_err); 343 return; 344 } 345 346 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 347 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 348 error_setg(errp, 349 "KVM does not support 1TiB segments which guest expects"); 350 return; 351 } 352 353 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 354 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 355 smmu_info.slb_size, cpu->hash64_opts->slb_size); 356 return; 357 } 358 359 /* 360 * Verify that every pagesize supported by the cpu model is 361 * supported by KVM with the same encodings 362 */ 363 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 364 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 365 struct kvm_ppc_one_seg_page_size *ksps; 366 367 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 368 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 369 break; 370 } 371 } 372 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 373 error_setg(errp, "KVM doesn't support for base page shift %u", 374 qsps->page_shift); 375 return; 376 } 377 378 ksps = &smmu_info.sps[ik]; 379 if (ksps->slb_enc != qsps->slb_enc) { 380 error_setg(errp, 381 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 382 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 383 return; 384 } 385 386 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 387 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 388 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 389 break; 390 } 391 } 392 393 if (jk >= ARRAY_SIZE(ksps->enc)) { 394 error_setg(errp, "KVM doesn't support page shift %u/%u", 395 qsps->enc[jq].page_shift, qsps->page_shift); 396 return; 397 } 398 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 399 error_setg(errp, 400 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 401 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 402 qsps->page_shift, qsps->enc[jq].pte_enc); 403 return; 404 } 405 } 406 } 407 408 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 409 /* 410 * Mostly what guest pagesizes we can use are related to the 411 * host pages used to map guest RAM, which is handled in the 412 * platform code. Cache-Inhibited largepages (64k) however are 413 * used for I/O, so if they're mapped to the host at all it 414 * will be a normal mapping, not a special hugepage one used 415 * for RAM. 416 */ 417 if (qemu_real_host_page_size < 0x10000) { 418 error_setg(errp, 419 "KVM can't supply 64kiB CI pages, which guest expects"); 420 } 421 } 422 } 423 #endif /* !defined (TARGET_PPC64) */ 424 425 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 426 { 427 return POWERPC_CPU(cpu)->vcpu_id; 428 } 429 430 /* 431 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 432 * only 1 watchpoint, so array size of 4 is sufficient for now. 433 */ 434 #define MAX_HW_BKPTS 4 435 436 static struct HWBreakpoint { 437 target_ulong addr; 438 int type; 439 } hw_debug_points[MAX_HW_BKPTS]; 440 441 static CPUWatchpoint hw_watchpoint; 442 443 /* Default there is no breakpoint and watchpoint supported */ 444 static int max_hw_breakpoint; 445 static int max_hw_watchpoint; 446 static int nb_hw_breakpoint; 447 static int nb_hw_watchpoint; 448 449 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 450 { 451 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 452 max_hw_breakpoint = 2; 453 max_hw_watchpoint = 2; 454 } 455 456 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 457 fprintf(stderr, "Error initializing h/w breakpoints\n"); 458 return; 459 } 460 } 461 462 int kvm_arch_init_vcpu(CPUState *cs) 463 { 464 PowerPCCPU *cpu = POWERPC_CPU(cs); 465 CPUPPCState *cenv = &cpu->env; 466 int ret; 467 468 /* Synchronize sregs with kvm */ 469 ret = kvm_arch_sync_sregs(cpu); 470 if (ret) { 471 if (ret == -EINVAL) { 472 error_report("Register sync failed... If you're using kvm-hv.ko," 473 " only \"-cpu host\" is possible"); 474 } 475 return ret; 476 } 477 478 switch (cenv->mmu_model) { 479 case POWERPC_MMU_BOOKE206: 480 /* This target supports access to KVM's guest TLB */ 481 ret = kvm_booke206_tlb_init(cpu); 482 break; 483 case POWERPC_MMU_2_07: 484 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 485 /* 486 * KVM-HV has transactional memory on POWER8 also without 487 * the KVM_CAP_PPC_HTM extension, so enable it here 488 * instead as long as it's availble to userspace on the 489 * host. 490 */ 491 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 492 cap_htm = true; 493 } 494 } 495 break; 496 default: 497 break; 498 } 499 500 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 501 kvmppc_hw_debug_points_init(cenv); 502 503 return ret; 504 } 505 506 int kvm_arch_destroy_vcpu(CPUState *cs) 507 { 508 return 0; 509 } 510 511 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 512 { 513 CPUPPCState *env = &cpu->env; 514 CPUState *cs = CPU(cpu); 515 struct kvm_dirty_tlb dirty_tlb; 516 unsigned char *bitmap; 517 int ret; 518 519 if (!env->kvm_sw_tlb) { 520 return; 521 } 522 523 bitmap = g_malloc((env->nb_tlb + 7) / 8); 524 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 525 526 dirty_tlb.bitmap = (uintptr_t)bitmap; 527 dirty_tlb.num_dirty = env->nb_tlb; 528 529 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 530 if (ret) { 531 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 532 __func__, strerror(-ret)); 533 } 534 535 g_free(bitmap); 536 } 537 538 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 539 { 540 PowerPCCPU *cpu = POWERPC_CPU(cs); 541 CPUPPCState *env = &cpu->env; 542 union { 543 uint32_t u32; 544 uint64_t u64; 545 } val; 546 struct kvm_one_reg reg = { 547 .id = id, 548 .addr = (uintptr_t) &val, 549 }; 550 int ret; 551 552 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 553 if (ret != 0) { 554 trace_kvm_failed_spr_get(spr, strerror(errno)); 555 } else { 556 switch (id & KVM_REG_SIZE_MASK) { 557 case KVM_REG_SIZE_U32: 558 env->spr[spr] = val.u32; 559 break; 560 561 case KVM_REG_SIZE_U64: 562 env->spr[spr] = val.u64; 563 break; 564 565 default: 566 /* Don't handle this size yet */ 567 abort(); 568 } 569 } 570 } 571 572 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 573 { 574 PowerPCCPU *cpu = POWERPC_CPU(cs); 575 CPUPPCState *env = &cpu->env; 576 union { 577 uint32_t u32; 578 uint64_t u64; 579 } val; 580 struct kvm_one_reg reg = { 581 .id = id, 582 .addr = (uintptr_t) &val, 583 }; 584 int ret; 585 586 switch (id & KVM_REG_SIZE_MASK) { 587 case KVM_REG_SIZE_U32: 588 val.u32 = env->spr[spr]; 589 break; 590 591 case KVM_REG_SIZE_U64: 592 val.u64 = env->spr[spr]; 593 break; 594 595 default: 596 /* Don't handle this size yet */ 597 abort(); 598 } 599 600 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 601 if (ret != 0) { 602 trace_kvm_failed_spr_set(spr, strerror(errno)); 603 } 604 } 605 606 static int kvm_put_fp(CPUState *cs) 607 { 608 PowerPCCPU *cpu = POWERPC_CPU(cs); 609 CPUPPCState *env = &cpu->env; 610 struct kvm_one_reg reg; 611 int i; 612 int ret; 613 614 if (env->insns_flags & PPC_FLOAT) { 615 uint64_t fpscr = env->fpscr; 616 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 617 618 reg.id = KVM_REG_PPC_FPSCR; 619 reg.addr = (uintptr_t)&fpscr; 620 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 621 if (ret < 0) { 622 trace_kvm_failed_fpscr_set(strerror(errno)); 623 return ret; 624 } 625 626 for (i = 0; i < 32; i++) { 627 uint64_t vsr[2]; 628 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 629 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 630 631 #ifdef HOST_WORDS_BIGENDIAN 632 vsr[0] = float64_val(*fpr); 633 vsr[1] = *vsrl; 634 #else 635 vsr[0] = *vsrl; 636 vsr[1] = float64_val(*fpr); 637 #endif 638 reg.addr = (uintptr_t) &vsr; 639 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 640 641 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 642 if (ret < 0) { 643 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 644 strerror(errno)); 645 return ret; 646 } 647 } 648 } 649 650 if (env->insns_flags & PPC_ALTIVEC) { 651 reg.id = KVM_REG_PPC_VSCR; 652 reg.addr = (uintptr_t)&env->vscr; 653 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 654 if (ret < 0) { 655 trace_kvm_failed_vscr_set(strerror(errno)); 656 return ret; 657 } 658 659 for (i = 0; i < 32; i++) { 660 reg.id = KVM_REG_PPC_VR(i); 661 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 662 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 663 if (ret < 0) { 664 trace_kvm_failed_vr_set(i, strerror(errno)); 665 return ret; 666 } 667 } 668 } 669 670 return 0; 671 } 672 673 static int kvm_get_fp(CPUState *cs) 674 { 675 PowerPCCPU *cpu = POWERPC_CPU(cs); 676 CPUPPCState *env = &cpu->env; 677 struct kvm_one_reg reg; 678 int i; 679 int ret; 680 681 if (env->insns_flags & PPC_FLOAT) { 682 uint64_t fpscr; 683 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 684 685 reg.id = KVM_REG_PPC_FPSCR; 686 reg.addr = (uintptr_t)&fpscr; 687 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 688 if (ret < 0) { 689 trace_kvm_failed_fpscr_get(strerror(errno)); 690 return ret; 691 } else { 692 env->fpscr = fpscr; 693 } 694 695 for (i = 0; i < 32; i++) { 696 uint64_t vsr[2]; 697 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 698 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 699 700 reg.addr = (uintptr_t) &vsr; 701 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 702 703 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 704 if (ret < 0) { 705 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 706 strerror(errno)); 707 return ret; 708 } else { 709 #ifdef HOST_WORDS_BIGENDIAN 710 *fpr = vsr[0]; 711 if (vsx) { 712 *vsrl = vsr[1]; 713 } 714 #else 715 *fpr = vsr[1]; 716 if (vsx) { 717 *vsrl = vsr[0]; 718 } 719 #endif 720 } 721 } 722 } 723 724 if (env->insns_flags & PPC_ALTIVEC) { 725 reg.id = KVM_REG_PPC_VSCR; 726 reg.addr = (uintptr_t)&env->vscr; 727 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 728 if (ret < 0) { 729 trace_kvm_failed_vscr_get(strerror(errno)); 730 return ret; 731 } 732 733 for (i = 0; i < 32; i++) { 734 reg.id = KVM_REG_PPC_VR(i); 735 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 736 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 737 if (ret < 0) { 738 trace_kvm_failed_vr_get(i, strerror(errno)); 739 return ret; 740 } 741 } 742 } 743 744 return 0; 745 } 746 747 #if defined(TARGET_PPC64) 748 static int kvm_get_vpa(CPUState *cs) 749 { 750 PowerPCCPU *cpu = POWERPC_CPU(cs); 751 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 752 struct kvm_one_reg reg; 753 int ret; 754 755 reg.id = KVM_REG_PPC_VPA_ADDR; 756 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 757 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 758 if (ret < 0) { 759 trace_kvm_failed_vpa_addr_get(strerror(errno)); 760 return ret; 761 } 762 763 assert((uintptr_t)&spapr_cpu->slb_shadow_size 764 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 765 reg.id = KVM_REG_PPC_VPA_SLB; 766 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 767 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 768 if (ret < 0) { 769 trace_kvm_failed_slb_get(strerror(errno)); 770 return ret; 771 } 772 773 assert((uintptr_t)&spapr_cpu->dtl_size 774 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 775 reg.id = KVM_REG_PPC_VPA_DTL; 776 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 778 if (ret < 0) { 779 trace_kvm_failed_dtl_get(strerror(errno)); 780 return ret; 781 } 782 783 return 0; 784 } 785 786 static int kvm_put_vpa(CPUState *cs) 787 { 788 PowerPCCPU *cpu = POWERPC_CPU(cs); 789 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 790 struct kvm_one_reg reg; 791 int ret; 792 793 /* 794 * SLB shadow or DTL can't be registered unless a master VPA is 795 * registered. That means when restoring state, if a VPA *is* 796 * registered, we need to set that up first. If not, we need to 797 * deregister the others before deregistering the master VPA 798 */ 799 assert(spapr_cpu->vpa_addr 800 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 801 802 if (spapr_cpu->vpa_addr) { 803 reg.id = KVM_REG_PPC_VPA_ADDR; 804 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 805 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 806 if (ret < 0) { 807 trace_kvm_failed_vpa_addr_set(strerror(errno)); 808 return ret; 809 } 810 } 811 812 assert((uintptr_t)&spapr_cpu->slb_shadow_size 813 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 814 reg.id = KVM_REG_PPC_VPA_SLB; 815 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 816 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 817 if (ret < 0) { 818 trace_kvm_failed_slb_set(strerror(errno)); 819 return ret; 820 } 821 822 assert((uintptr_t)&spapr_cpu->dtl_size 823 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 824 reg.id = KVM_REG_PPC_VPA_DTL; 825 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 826 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 827 if (ret < 0) { 828 trace_kvm_failed_dtl_set(strerror(errno)); 829 return ret; 830 } 831 832 if (!spapr_cpu->vpa_addr) { 833 reg.id = KVM_REG_PPC_VPA_ADDR; 834 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 835 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 836 if (ret < 0) { 837 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 838 return ret; 839 } 840 } 841 842 return 0; 843 } 844 #endif /* TARGET_PPC64 */ 845 846 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 847 { 848 CPUPPCState *env = &cpu->env; 849 struct kvm_sregs sregs; 850 int i; 851 852 sregs.pvr = env->spr[SPR_PVR]; 853 854 if (cpu->vhyp) { 855 PPCVirtualHypervisorClass *vhc = 856 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 857 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 858 } else { 859 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 860 } 861 862 /* Sync SLB */ 863 #ifdef TARGET_PPC64 864 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 865 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 866 if (env->slb[i].esid & SLB_ESID_V) { 867 sregs.u.s.ppc64.slb[i].slbe |= i; 868 } 869 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 870 } 871 #endif 872 873 /* Sync SRs */ 874 for (i = 0; i < 16; i++) { 875 sregs.u.s.ppc32.sr[i] = env->sr[i]; 876 } 877 878 /* Sync BATs */ 879 for (i = 0; i < 8; i++) { 880 /* Beware. We have to swap upper and lower bits here */ 881 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 882 | env->DBAT[1][i]; 883 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 884 | env->IBAT[1][i]; 885 } 886 887 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 888 } 889 890 int kvm_arch_put_registers(CPUState *cs, int level) 891 { 892 PowerPCCPU *cpu = POWERPC_CPU(cs); 893 CPUPPCState *env = &cpu->env; 894 struct kvm_regs regs; 895 int ret; 896 int i; 897 898 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 899 if (ret < 0) { 900 return ret; 901 } 902 903 regs.ctr = env->ctr; 904 regs.lr = env->lr; 905 regs.xer = cpu_read_xer(env); 906 regs.msr = env->msr; 907 regs.pc = env->nip; 908 909 regs.srr0 = env->spr[SPR_SRR0]; 910 regs.srr1 = env->spr[SPR_SRR1]; 911 912 regs.sprg0 = env->spr[SPR_SPRG0]; 913 regs.sprg1 = env->spr[SPR_SPRG1]; 914 regs.sprg2 = env->spr[SPR_SPRG2]; 915 regs.sprg3 = env->spr[SPR_SPRG3]; 916 regs.sprg4 = env->spr[SPR_SPRG4]; 917 regs.sprg5 = env->spr[SPR_SPRG5]; 918 regs.sprg6 = env->spr[SPR_SPRG6]; 919 regs.sprg7 = env->spr[SPR_SPRG7]; 920 921 regs.pid = env->spr[SPR_BOOKE_PID]; 922 923 for (i = 0; i < 32; i++) { 924 regs.gpr[i] = env->gpr[i]; 925 } 926 927 regs.cr = 0; 928 for (i = 0; i < 8; i++) { 929 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); 930 } 931 932 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 933 if (ret < 0) { 934 return ret; 935 } 936 937 kvm_put_fp(cs); 938 939 if (env->tlb_dirty) { 940 kvm_sw_tlb_put(cpu); 941 env->tlb_dirty = false; 942 } 943 944 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 945 ret = kvmppc_put_books_sregs(cpu); 946 if (ret < 0) { 947 return ret; 948 } 949 } 950 951 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 952 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 953 } 954 955 if (cap_one_reg) { 956 int i; 957 958 /* 959 * We deliberately ignore errors here, for kernels which have 960 * the ONE_REG calls, but don't support the specific 961 * registers, there's a reasonable chance things will still 962 * work, at least until we try to migrate. 963 */ 964 for (i = 0; i < 1024; i++) { 965 uint64_t id = env->spr_cb[i].one_reg_id; 966 967 if (id != 0) { 968 kvm_put_one_spr(cs, id, i); 969 } 970 } 971 972 #ifdef TARGET_PPC64 973 if (msr_ts) { 974 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 975 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 976 } 977 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 979 } 980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 990 } 991 992 if (cap_papr) { 993 if (kvm_put_vpa(cs) < 0) { 994 trace_kvm_failed_put_vpa(); 995 } 996 } 997 998 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 999 1000 if (level > KVM_PUT_RUNTIME_STATE) { 1001 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1002 } 1003 #endif /* TARGET_PPC64 */ 1004 } 1005 1006 return ret; 1007 } 1008 1009 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1010 { 1011 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1012 } 1013 1014 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1015 { 1016 CPUPPCState *env = &cpu->env; 1017 struct kvm_sregs sregs; 1018 int ret; 1019 1020 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1021 if (ret < 0) { 1022 return ret; 1023 } 1024 1025 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1026 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1027 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1028 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1029 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1030 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1031 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1032 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1033 env->spr[SPR_DECR] = sregs.u.e.dec; 1034 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1035 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1036 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1037 } 1038 1039 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1040 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1041 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1042 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1043 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1044 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1045 } 1046 1047 if (sregs.u.e.features & KVM_SREGS_E_64) { 1048 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1049 } 1050 1051 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1052 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1053 } 1054 1055 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1056 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1057 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1058 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1059 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1060 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1061 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1062 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1063 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1064 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1065 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1066 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1067 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1068 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1069 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1070 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1071 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1072 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1073 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1074 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1075 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1076 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1077 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1078 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1079 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1080 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1081 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1082 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1083 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1084 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1085 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1086 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1087 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1088 1089 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1090 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1091 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1092 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1093 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1094 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1095 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1096 } 1097 1098 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1099 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1100 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1101 } 1102 1103 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1104 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1105 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1106 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1107 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1108 } 1109 } 1110 1111 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1112 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1113 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1114 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1115 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1116 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1117 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1118 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1119 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1120 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1121 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1122 } 1123 1124 if (sregs.u.e.features & KVM_SREGS_EXP) { 1125 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1126 } 1127 1128 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1129 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1130 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1131 } 1132 1133 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1134 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1135 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1136 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1137 1138 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1139 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1140 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1141 } 1142 } 1143 1144 return 0; 1145 } 1146 1147 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1148 { 1149 CPUPPCState *env = &cpu->env; 1150 struct kvm_sregs sregs; 1151 int ret; 1152 int i; 1153 1154 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1155 if (ret < 0) { 1156 return ret; 1157 } 1158 1159 if (!cpu->vhyp) { 1160 ppc_store_sdr1(env, sregs.u.s.sdr1); 1161 } 1162 1163 /* Sync SLB */ 1164 #ifdef TARGET_PPC64 1165 /* 1166 * The packed SLB array we get from KVM_GET_SREGS only contains 1167 * information about valid entries. So we flush our internal copy 1168 * to get rid of stale ones, then put all valid SLB entries back 1169 * in. 1170 */ 1171 memset(env->slb, 0, sizeof(env->slb)); 1172 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1173 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1174 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1175 /* 1176 * Only restore valid entries 1177 */ 1178 if (rb & SLB_ESID_V) { 1179 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1180 } 1181 } 1182 #endif 1183 1184 /* Sync SRs */ 1185 for (i = 0; i < 16; i++) { 1186 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1187 } 1188 1189 /* Sync BATs */ 1190 for (i = 0; i < 8; i++) { 1191 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1192 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1193 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1194 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1195 } 1196 1197 return 0; 1198 } 1199 1200 int kvm_arch_get_registers(CPUState *cs) 1201 { 1202 PowerPCCPU *cpu = POWERPC_CPU(cs); 1203 CPUPPCState *env = &cpu->env; 1204 struct kvm_regs regs; 1205 uint32_t cr; 1206 int i, ret; 1207 1208 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1209 if (ret < 0) { 1210 return ret; 1211 } 1212 1213 cr = regs.cr; 1214 for (i = 7; i >= 0; i--) { 1215 env->crf[i] = cr & 15; 1216 cr >>= 4; 1217 } 1218 1219 env->ctr = regs.ctr; 1220 env->lr = regs.lr; 1221 cpu_write_xer(env, regs.xer); 1222 env->msr = regs.msr; 1223 env->nip = regs.pc; 1224 1225 env->spr[SPR_SRR0] = regs.srr0; 1226 env->spr[SPR_SRR1] = regs.srr1; 1227 1228 env->spr[SPR_SPRG0] = regs.sprg0; 1229 env->spr[SPR_SPRG1] = regs.sprg1; 1230 env->spr[SPR_SPRG2] = regs.sprg2; 1231 env->spr[SPR_SPRG3] = regs.sprg3; 1232 env->spr[SPR_SPRG4] = regs.sprg4; 1233 env->spr[SPR_SPRG5] = regs.sprg5; 1234 env->spr[SPR_SPRG6] = regs.sprg6; 1235 env->spr[SPR_SPRG7] = regs.sprg7; 1236 1237 env->spr[SPR_BOOKE_PID] = regs.pid; 1238 1239 for (i = 0; i < 32; i++) { 1240 env->gpr[i] = regs.gpr[i]; 1241 } 1242 1243 kvm_get_fp(cs); 1244 1245 if (cap_booke_sregs) { 1246 ret = kvmppc_get_booke_sregs(cpu); 1247 if (ret < 0) { 1248 return ret; 1249 } 1250 } 1251 1252 if (cap_segstate) { 1253 ret = kvmppc_get_books_sregs(cpu); 1254 if (ret < 0) { 1255 return ret; 1256 } 1257 } 1258 1259 if (cap_hior) { 1260 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1261 } 1262 1263 if (cap_one_reg) { 1264 int i; 1265 1266 /* 1267 * We deliberately ignore errors here, for kernels which have 1268 * the ONE_REG calls, but don't support the specific 1269 * registers, there's a reasonable chance things will still 1270 * work, at least until we try to migrate. 1271 */ 1272 for (i = 0; i < 1024; i++) { 1273 uint64_t id = env->spr_cb[i].one_reg_id; 1274 1275 if (id != 0) { 1276 kvm_get_one_spr(cs, id, i); 1277 } 1278 } 1279 1280 #ifdef TARGET_PPC64 1281 if (msr_ts) { 1282 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1284 } 1285 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1287 } 1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1298 } 1299 1300 if (cap_papr) { 1301 if (kvm_get_vpa(cs) < 0) { 1302 trace_kvm_failed_get_vpa(); 1303 } 1304 } 1305 1306 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1307 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1308 #endif 1309 } 1310 1311 return 0; 1312 } 1313 1314 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1315 { 1316 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1317 1318 if (irq != PPC_INTERRUPT_EXT) { 1319 return 0; 1320 } 1321 1322 if (!kvm_enabled() || !cap_interrupt_unset) { 1323 return 0; 1324 } 1325 1326 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1327 1328 return 0; 1329 } 1330 1331 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1332 { 1333 return; 1334 } 1335 1336 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1337 { 1338 return MEMTXATTRS_UNSPECIFIED; 1339 } 1340 1341 int kvm_arch_process_async_events(CPUState *cs) 1342 { 1343 return cs->halted; 1344 } 1345 1346 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1347 { 1348 CPUState *cs = CPU(cpu); 1349 CPUPPCState *env = &cpu->env; 1350 1351 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { 1352 cs->halted = 1; 1353 cs->exception_index = EXCP_HLT; 1354 } 1355 1356 return 0; 1357 } 1358 1359 /* map dcr access to existing qemu dcr emulation */ 1360 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1361 uint32_t dcrn, uint32_t *data) 1362 { 1363 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1364 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1365 } 1366 1367 return 0; 1368 } 1369 1370 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1371 uint32_t dcrn, uint32_t data) 1372 { 1373 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1374 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1375 } 1376 1377 return 0; 1378 } 1379 1380 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1381 { 1382 /* Mixed endian case is not handled */ 1383 uint32_t sc = debug_inst_opcode; 1384 1385 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1386 sizeof(sc), 0) || 1387 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1388 return -EINVAL; 1389 } 1390 1391 return 0; 1392 } 1393 1394 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1395 { 1396 uint32_t sc; 1397 1398 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1399 sc != debug_inst_opcode || 1400 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1401 sizeof(sc), 1)) { 1402 return -EINVAL; 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int find_hw_breakpoint(target_ulong addr, int type) 1409 { 1410 int n; 1411 1412 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1413 <= ARRAY_SIZE(hw_debug_points)); 1414 1415 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1416 if (hw_debug_points[n].addr == addr && 1417 hw_debug_points[n].type == type) { 1418 return n; 1419 } 1420 } 1421 1422 return -1; 1423 } 1424 1425 static int find_hw_watchpoint(target_ulong addr, int *flag) 1426 { 1427 int n; 1428 1429 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1430 if (n >= 0) { 1431 *flag = BP_MEM_ACCESS; 1432 return n; 1433 } 1434 1435 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1436 if (n >= 0) { 1437 *flag = BP_MEM_WRITE; 1438 return n; 1439 } 1440 1441 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1442 if (n >= 0) { 1443 *flag = BP_MEM_READ; 1444 return n; 1445 } 1446 1447 return -1; 1448 } 1449 1450 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1451 target_ulong len, int type) 1452 { 1453 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1454 return -ENOBUFS; 1455 } 1456 1457 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1458 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1459 1460 switch (type) { 1461 case GDB_BREAKPOINT_HW: 1462 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1463 return -ENOBUFS; 1464 } 1465 1466 if (find_hw_breakpoint(addr, type) >= 0) { 1467 return -EEXIST; 1468 } 1469 1470 nb_hw_breakpoint++; 1471 break; 1472 1473 case GDB_WATCHPOINT_WRITE: 1474 case GDB_WATCHPOINT_READ: 1475 case GDB_WATCHPOINT_ACCESS: 1476 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1477 return -ENOBUFS; 1478 } 1479 1480 if (find_hw_breakpoint(addr, type) >= 0) { 1481 return -EEXIST; 1482 } 1483 1484 nb_hw_watchpoint++; 1485 break; 1486 1487 default: 1488 return -ENOSYS; 1489 } 1490 1491 return 0; 1492 } 1493 1494 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1495 target_ulong len, int type) 1496 { 1497 int n; 1498 1499 n = find_hw_breakpoint(addr, type); 1500 if (n < 0) { 1501 return -ENOENT; 1502 } 1503 1504 switch (type) { 1505 case GDB_BREAKPOINT_HW: 1506 nb_hw_breakpoint--; 1507 break; 1508 1509 case GDB_WATCHPOINT_WRITE: 1510 case GDB_WATCHPOINT_READ: 1511 case GDB_WATCHPOINT_ACCESS: 1512 nb_hw_watchpoint--; 1513 break; 1514 1515 default: 1516 return -ENOSYS; 1517 } 1518 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1519 1520 return 0; 1521 } 1522 1523 void kvm_arch_remove_all_hw_breakpoints(void) 1524 { 1525 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1526 } 1527 1528 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1529 { 1530 int n; 1531 1532 /* Software Breakpoint updates */ 1533 if (kvm_sw_breakpoints_active(cs)) { 1534 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1535 } 1536 1537 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1538 <= ARRAY_SIZE(hw_debug_points)); 1539 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1540 1541 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1542 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1543 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1544 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1545 switch (hw_debug_points[n].type) { 1546 case GDB_BREAKPOINT_HW: 1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1548 break; 1549 case GDB_WATCHPOINT_WRITE: 1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1551 break; 1552 case GDB_WATCHPOINT_READ: 1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1554 break; 1555 case GDB_WATCHPOINT_ACCESS: 1556 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1557 KVMPPC_DEBUG_WATCH_READ; 1558 break; 1559 default: 1560 cpu_abort(cs, "Unsupported breakpoint type\n"); 1561 } 1562 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1563 } 1564 } 1565 } 1566 1567 static int kvm_handle_hw_breakpoint(CPUState *cs, 1568 struct kvm_debug_exit_arch *arch_info) 1569 { 1570 int handle = DEBUG_RETURN_GUEST; 1571 int n; 1572 int flag = 0; 1573 1574 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1575 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1576 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1577 if (n >= 0) { 1578 handle = DEBUG_RETURN_GDB; 1579 } 1580 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1581 KVMPPC_DEBUG_WATCH_WRITE)) { 1582 n = find_hw_watchpoint(arch_info->address, &flag); 1583 if (n >= 0) { 1584 handle = DEBUG_RETURN_GDB; 1585 cs->watchpoint_hit = &hw_watchpoint; 1586 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1587 hw_watchpoint.flags = flag; 1588 } 1589 } 1590 } 1591 return handle; 1592 } 1593 1594 static int kvm_handle_singlestep(void) 1595 { 1596 return DEBUG_RETURN_GDB; 1597 } 1598 1599 static int kvm_handle_sw_breakpoint(void) 1600 { 1601 return DEBUG_RETURN_GDB; 1602 } 1603 1604 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1605 { 1606 CPUState *cs = CPU(cpu); 1607 CPUPPCState *env = &cpu->env; 1608 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1609 1610 if (cs->singlestep_enabled) { 1611 return kvm_handle_singlestep(); 1612 } 1613 1614 if (arch_info->status) { 1615 return kvm_handle_hw_breakpoint(cs, arch_info); 1616 } 1617 1618 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1619 return kvm_handle_sw_breakpoint(); 1620 } 1621 1622 /* 1623 * QEMU is not able to handle debug exception, so inject 1624 * program exception to guest; 1625 * Yes program exception NOT debug exception !! 1626 * When QEMU is using debug resources then debug exception must 1627 * be always set. To achieve this we set MSR_DE and also set 1628 * MSRP_DEP so guest cannot change MSR_DE. 1629 * When emulating debug resource for guest we want guest 1630 * to control MSR_DE (enable/disable debug interrupt on need). 1631 * Supporting both configurations are NOT possible. 1632 * So the result is that we cannot share debug resources 1633 * between QEMU and Guest on BOOKE architecture. 1634 * In the current design QEMU gets the priority over guest, 1635 * this means that if QEMU is using debug resources then guest 1636 * cannot use them; 1637 * For software breakpoint QEMU uses a privileged instruction; 1638 * So there cannot be any reason that we are here for guest 1639 * set debug exception, only possibility is guest executed a 1640 * privileged / illegal instruction and that's why we are 1641 * injecting a program interrupt. 1642 */ 1643 cpu_synchronize_state(cs); 1644 /* 1645 * env->nip is PC, so increment this by 4 to use 1646 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1647 */ 1648 env->nip += 4; 1649 cs->exception_index = POWERPC_EXCP_PROGRAM; 1650 env->error_code = POWERPC_EXCP_INVAL; 1651 ppc_cpu_do_interrupt(cs); 1652 1653 return DEBUG_RETURN_GUEST; 1654 } 1655 1656 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1657 { 1658 PowerPCCPU *cpu = POWERPC_CPU(cs); 1659 CPUPPCState *env = &cpu->env; 1660 int ret; 1661 1662 qemu_mutex_lock_iothread(); 1663 1664 switch (run->exit_reason) { 1665 case KVM_EXIT_DCR: 1666 if (run->dcr.is_write) { 1667 trace_kvm_handle_dcr_write(); 1668 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1669 } else { 1670 trace_kvm_handle_dcr_read(); 1671 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1672 } 1673 break; 1674 case KVM_EXIT_HLT: 1675 trace_kvm_handle_halt(); 1676 ret = kvmppc_handle_halt(cpu); 1677 break; 1678 #if defined(TARGET_PPC64) 1679 case KVM_EXIT_PAPR_HCALL: 1680 trace_kvm_handle_papr_hcall(); 1681 run->papr_hcall.ret = spapr_hypercall(cpu, 1682 run->papr_hcall.nr, 1683 run->papr_hcall.args); 1684 ret = 0; 1685 break; 1686 #endif 1687 case KVM_EXIT_EPR: 1688 trace_kvm_handle_epr(); 1689 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1690 ret = 0; 1691 break; 1692 case KVM_EXIT_WATCHDOG: 1693 trace_kvm_handle_watchdog_expiry(); 1694 watchdog_perform_action(); 1695 ret = 0; 1696 break; 1697 1698 case KVM_EXIT_DEBUG: 1699 trace_kvm_handle_debug_exception(); 1700 if (kvm_handle_debug(cpu, run)) { 1701 ret = EXCP_DEBUG; 1702 break; 1703 } 1704 /* re-enter, this exception was guest-internal */ 1705 ret = 0; 1706 break; 1707 1708 #if defined(TARGET_PPC64) 1709 case KVM_EXIT_NMI: 1710 trace_kvm_handle_nmi_exception(); 1711 ret = kvm_handle_nmi(cpu, run); 1712 break; 1713 #endif 1714 1715 default: 1716 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1717 ret = -1; 1718 break; 1719 } 1720 1721 qemu_mutex_unlock_iothread(); 1722 return ret; 1723 } 1724 1725 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1726 { 1727 CPUState *cs = CPU(cpu); 1728 uint32_t bits = tsr_bits; 1729 struct kvm_one_reg reg = { 1730 .id = KVM_REG_PPC_OR_TSR, 1731 .addr = (uintptr_t) &bits, 1732 }; 1733 1734 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1735 } 1736 1737 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1738 { 1739 1740 CPUState *cs = CPU(cpu); 1741 uint32_t bits = tsr_bits; 1742 struct kvm_one_reg reg = { 1743 .id = KVM_REG_PPC_CLEAR_TSR, 1744 .addr = (uintptr_t) &bits, 1745 }; 1746 1747 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1748 } 1749 1750 int kvmppc_set_tcr(PowerPCCPU *cpu) 1751 { 1752 CPUState *cs = CPU(cpu); 1753 CPUPPCState *env = &cpu->env; 1754 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1755 1756 struct kvm_one_reg reg = { 1757 .id = KVM_REG_PPC_TCR, 1758 .addr = (uintptr_t) &tcr, 1759 }; 1760 1761 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1762 } 1763 1764 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1765 { 1766 CPUState *cs = CPU(cpu); 1767 int ret; 1768 1769 if (!kvm_enabled()) { 1770 return -1; 1771 } 1772 1773 if (!cap_ppc_watchdog) { 1774 printf("warning: KVM does not support watchdog"); 1775 return -1; 1776 } 1777 1778 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1779 if (ret < 0) { 1780 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1781 __func__, strerror(-ret)); 1782 return ret; 1783 } 1784 1785 return ret; 1786 } 1787 1788 static int read_cpuinfo(const char *field, char *value, int len) 1789 { 1790 FILE *f; 1791 int ret = -1; 1792 int field_len = strlen(field); 1793 char line[512]; 1794 1795 f = fopen("/proc/cpuinfo", "r"); 1796 if (!f) { 1797 return -1; 1798 } 1799 1800 do { 1801 if (!fgets(line, sizeof(line), f)) { 1802 break; 1803 } 1804 if (!strncmp(line, field, field_len)) { 1805 pstrcpy(value, len, line); 1806 ret = 0; 1807 break; 1808 } 1809 } while (*line); 1810 1811 fclose(f); 1812 1813 return ret; 1814 } 1815 1816 uint32_t kvmppc_get_tbfreq(void) 1817 { 1818 char line[512]; 1819 char *ns; 1820 uint32_t retval = NANOSECONDS_PER_SECOND; 1821 1822 if (read_cpuinfo("timebase", line, sizeof(line))) { 1823 return retval; 1824 } 1825 1826 ns = strchr(line, ':'); 1827 if (!ns) { 1828 return retval; 1829 } 1830 1831 ns++; 1832 1833 return atoi(ns); 1834 } 1835 1836 bool kvmppc_get_host_serial(char **value) 1837 { 1838 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1839 NULL); 1840 } 1841 1842 bool kvmppc_get_host_model(char **value) 1843 { 1844 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1845 } 1846 1847 /* Try to find a device tree node for a CPU with clock-frequency property */ 1848 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1849 { 1850 struct dirent *dirp; 1851 DIR *dp; 1852 1853 dp = opendir(PROC_DEVTREE_CPU); 1854 if (!dp) { 1855 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1856 return -1; 1857 } 1858 1859 buf[0] = '\0'; 1860 while ((dirp = readdir(dp)) != NULL) { 1861 FILE *f; 1862 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1863 dirp->d_name); 1864 f = fopen(buf, "r"); 1865 if (f) { 1866 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1867 fclose(f); 1868 break; 1869 } 1870 buf[0] = '\0'; 1871 } 1872 closedir(dp); 1873 if (buf[0] == '\0') { 1874 printf("Unknown host!\n"); 1875 return -1; 1876 } 1877 1878 return 0; 1879 } 1880 1881 static uint64_t kvmppc_read_int_dt(const char *filename) 1882 { 1883 union { 1884 uint32_t v32; 1885 uint64_t v64; 1886 } u; 1887 FILE *f; 1888 int len; 1889 1890 f = fopen(filename, "rb"); 1891 if (!f) { 1892 return -1; 1893 } 1894 1895 len = fread(&u, 1, sizeof(u), f); 1896 fclose(f); 1897 switch (len) { 1898 case 4: 1899 /* property is a 32-bit quantity */ 1900 return be32_to_cpu(u.v32); 1901 case 8: 1902 return be64_to_cpu(u.v64); 1903 } 1904 1905 return 0; 1906 } 1907 1908 /* 1909 * Read a CPU node property from the host device tree that's a single 1910 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1911 * (can't find or open the property, or doesn't understand the format) 1912 */ 1913 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1914 { 1915 char buf[PATH_MAX], *tmp; 1916 uint64_t val; 1917 1918 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1919 return -1; 1920 } 1921 1922 tmp = g_strdup_printf("%s/%s", buf, propname); 1923 val = kvmppc_read_int_dt(tmp); 1924 g_free(tmp); 1925 1926 return val; 1927 } 1928 1929 uint64_t kvmppc_get_clockfreq(void) 1930 { 1931 return kvmppc_read_int_cpu_dt("clock-frequency"); 1932 } 1933 1934 static int kvmppc_get_dec_bits(void) 1935 { 1936 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1937 1938 if (nr_bits > 0) { 1939 return nr_bits; 1940 } 1941 return 0; 1942 } 1943 1944 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1945 { 1946 CPUState *cs = env_cpu(env); 1947 1948 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1949 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1950 return 0; 1951 } 1952 1953 return 1; 1954 } 1955 1956 int kvmppc_get_hasidle(CPUPPCState *env) 1957 { 1958 struct kvm_ppc_pvinfo pvinfo; 1959 1960 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1961 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1962 return 1; 1963 } 1964 1965 return 0; 1966 } 1967 1968 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 1969 { 1970 uint32_t *hc = (uint32_t *)buf; 1971 struct kvm_ppc_pvinfo pvinfo; 1972 1973 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 1974 memcpy(buf, pvinfo.hcall, buf_len); 1975 return 0; 1976 } 1977 1978 /* 1979 * Fallback to always fail hypercalls regardless of endianness: 1980 * 1981 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 1982 * li r3, -1 1983 * b .+8 (becomes nop in wrong endian) 1984 * bswap32(li r3, -1) 1985 */ 1986 1987 hc[0] = cpu_to_be32(0x08000048); 1988 hc[1] = cpu_to_be32(0x3860ffff); 1989 hc[2] = cpu_to_be32(0x48000008); 1990 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 1991 1992 return 1; 1993 } 1994 1995 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 1996 { 1997 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 1998 } 1999 2000 void kvmppc_enable_logical_ci_hcalls(void) 2001 { 2002 /* 2003 * FIXME: it would be nice if we could detect the cases where 2004 * we're using a device which requires the in kernel 2005 * implementation of these hcalls, but the kernel lacks them and 2006 * produce a warning. 2007 */ 2008 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2009 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2010 } 2011 2012 void kvmppc_enable_set_mode_hcall(void) 2013 { 2014 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2015 } 2016 2017 void kvmppc_enable_clear_ref_mod_hcalls(void) 2018 { 2019 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2020 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2021 } 2022 2023 void kvmppc_enable_h_page_init(void) 2024 { 2025 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2026 } 2027 2028 void kvmppc_set_papr(PowerPCCPU *cpu) 2029 { 2030 CPUState *cs = CPU(cpu); 2031 int ret; 2032 2033 if (!kvm_enabled()) { 2034 return; 2035 } 2036 2037 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2038 if (ret) { 2039 error_report("This vCPU type or KVM version does not support PAPR"); 2040 exit(1); 2041 } 2042 2043 /* 2044 * Update the capability flag so we sync the right information 2045 * with kvm 2046 */ 2047 cap_papr = 1; 2048 } 2049 2050 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2051 { 2052 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2053 } 2054 2055 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2056 { 2057 CPUState *cs = CPU(cpu); 2058 int ret; 2059 2060 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2061 if (ret && mpic_proxy) { 2062 error_report("This KVM version does not support EPR"); 2063 exit(1); 2064 } 2065 } 2066 2067 int kvmppc_set_fwnmi(void) 2068 { 2069 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 2070 CPUState *cs = CPU(cpu); 2071 2072 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); 2073 } 2074 2075 int kvmppc_smt_threads(void) 2076 { 2077 return cap_ppc_smt ? cap_ppc_smt : 1; 2078 } 2079 2080 int kvmppc_set_smt_threads(int smt) 2081 { 2082 int ret; 2083 2084 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2085 if (!ret) { 2086 cap_ppc_smt = smt; 2087 } 2088 return ret; 2089 } 2090 2091 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2092 { 2093 int i; 2094 GString *g; 2095 char *s; 2096 2097 assert(kvm_enabled()); 2098 if (cap_ppc_smt_possible) { 2099 g = g_string_new("Available VSMT modes:"); 2100 for (i = 63; i >= 0; i--) { 2101 if ((1UL << i) & cap_ppc_smt_possible) { 2102 g_string_append_printf(g, " %lu", (1UL << i)); 2103 } 2104 } 2105 s = g_string_free(g, false); 2106 error_append_hint(errp, "%s.\n", s); 2107 g_free(s); 2108 } else { 2109 error_append_hint(errp, 2110 "This KVM seems to be too old to support VSMT.\n"); 2111 } 2112 } 2113 2114 2115 #ifdef TARGET_PPC64 2116 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) 2117 { 2118 struct kvm_ppc_smmu_info info; 2119 long rampagesize, best_page_shift; 2120 int i; 2121 2122 /* 2123 * Find the largest hardware supported page size that's less than 2124 * or equal to the (logical) backing page size of guest RAM 2125 */ 2126 kvm_get_smmu_info(&info, &error_fatal); 2127 rampagesize = qemu_minrampagesize(); 2128 best_page_shift = 0; 2129 2130 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2131 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2132 2133 if (!sps->page_shift) { 2134 continue; 2135 } 2136 2137 if ((sps->page_shift > best_page_shift) 2138 && ((1UL << sps->page_shift) <= rampagesize)) { 2139 best_page_shift = sps->page_shift; 2140 } 2141 } 2142 2143 return MIN(current_size, 2144 1ULL << (best_page_shift + hash_shift - 7)); 2145 } 2146 #endif 2147 2148 bool kvmppc_spapr_use_multitce(void) 2149 { 2150 return cap_spapr_multitce; 2151 } 2152 2153 int kvmppc_spapr_enable_inkernel_multitce(void) 2154 { 2155 int ret; 2156 2157 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2158 H_PUT_TCE_INDIRECT, 1); 2159 if (!ret) { 2160 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2161 H_STUFF_TCE, 1); 2162 } 2163 2164 return ret; 2165 } 2166 2167 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2168 uint64_t bus_offset, uint32_t nb_table, 2169 int *pfd, bool need_vfio) 2170 { 2171 long len; 2172 int fd; 2173 void *table; 2174 2175 /* 2176 * Must set fd to -1 so we don't try to munmap when called for 2177 * destroying the table, which the upper layers -will- do 2178 */ 2179 *pfd = -1; 2180 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2181 return NULL; 2182 } 2183 2184 if (cap_spapr_tce_64) { 2185 struct kvm_create_spapr_tce_64 args = { 2186 .liobn = liobn, 2187 .page_shift = page_shift, 2188 .offset = bus_offset >> page_shift, 2189 .size = nb_table, 2190 .flags = 0 2191 }; 2192 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2193 if (fd < 0) { 2194 fprintf(stderr, 2195 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2196 liobn); 2197 return NULL; 2198 } 2199 } else if (cap_spapr_tce) { 2200 uint64_t window_size = (uint64_t) nb_table << page_shift; 2201 struct kvm_create_spapr_tce args = { 2202 .liobn = liobn, 2203 .window_size = window_size, 2204 }; 2205 if ((window_size != args.window_size) || bus_offset) { 2206 return NULL; 2207 } 2208 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2209 if (fd < 0) { 2210 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2211 liobn); 2212 return NULL; 2213 } 2214 } else { 2215 return NULL; 2216 } 2217 2218 len = nb_table * sizeof(uint64_t); 2219 /* FIXME: round this up to page size */ 2220 2221 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2222 if (table == MAP_FAILED) { 2223 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2224 liobn); 2225 close(fd); 2226 return NULL; 2227 } 2228 2229 *pfd = fd; 2230 return table; 2231 } 2232 2233 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2234 { 2235 long len; 2236 2237 if (fd < 0) { 2238 return -1; 2239 } 2240 2241 len = nb_table * sizeof(uint64_t); 2242 if ((munmap(table, len) < 0) || 2243 (close(fd) < 0)) { 2244 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2245 strerror(errno)); 2246 /* Leak the table */ 2247 } 2248 2249 return 0; 2250 } 2251 2252 int kvmppc_reset_htab(int shift_hint) 2253 { 2254 uint32_t shift = shift_hint; 2255 2256 if (!kvm_enabled()) { 2257 /* Full emulation, tell caller to allocate htab itself */ 2258 return 0; 2259 } 2260 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2261 int ret; 2262 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2263 if (ret == -ENOTTY) { 2264 /* 2265 * At least some versions of PR KVM advertise the 2266 * capability, but don't implement the ioctl(). Oops. 2267 * Return 0 so that we allocate the htab in qemu, as is 2268 * correct for PR. 2269 */ 2270 return 0; 2271 } else if (ret < 0) { 2272 return ret; 2273 } 2274 return shift; 2275 } 2276 2277 /* 2278 * We have a kernel that predates the htab reset calls. For PR 2279 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2280 * this era, it has allocated a 16MB fixed size hash table 2281 * already. 2282 */ 2283 if (kvmppc_is_pr(kvm_state)) { 2284 /* PR - tell caller to allocate htab */ 2285 return 0; 2286 } else { 2287 /* HV - assume 16MB kernel allocated htab */ 2288 return 24; 2289 } 2290 } 2291 2292 static inline uint32_t mfpvr(void) 2293 { 2294 uint32_t pvr; 2295 2296 asm ("mfpvr %0" 2297 : "=r"(pvr)); 2298 return pvr; 2299 } 2300 2301 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2302 { 2303 if (on) { 2304 *word |= flags; 2305 } else { 2306 *word &= ~flags; 2307 } 2308 } 2309 2310 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2311 { 2312 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2313 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2314 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2315 2316 /* Now fix up the class with information we can query from the host */ 2317 pcc->pvr = mfpvr(); 2318 2319 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2320 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2321 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2322 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2323 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2324 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2325 2326 if (dcache_size != -1) { 2327 pcc->l1_dcache_size = dcache_size; 2328 } 2329 2330 if (icache_size != -1) { 2331 pcc->l1_icache_size = icache_size; 2332 } 2333 2334 #if defined(TARGET_PPC64) 2335 pcc->radix_page_info = kvm_get_radix_page_info(); 2336 2337 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2338 /* 2339 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2340 * compliant. More importantly, advertising ISA 3.00 2341 * architected mode may prevent guests from activating 2342 * necessary DD1 workarounds. 2343 */ 2344 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2345 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2346 } 2347 #endif /* defined(TARGET_PPC64) */ 2348 } 2349 2350 bool kvmppc_has_cap_epr(void) 2351 { 2352 return cap_epr; 2353 } 2354 2355 bool kvmppc_has_cap_fixup_hcalls(void) 2356 { 2357 return cap_fixup_hcalls; 2358 } 2359 2360 bool kvmppc_has_cap_htm(void) 2361 { 2362 return cap_htm; 2363 } 2364 2365 bool kvmppc_has_cap_mmu_radix(void) 2366 { 2367 return cap_mmu_radix; 2368 } 2369 2370 bool kvmppc_has_cap_mmu_hash_v3(void) 2371 { 2372 return cap_mmu_hash_v3; 2373 } 2374 2375 static bool kvmppc_power8_host(void) 2376 { 2377 bool ret = false; 2378 #ifdef TARGET_PPC64 2379 { 2380 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2381 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2382 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2383 (base_pvr == CPU_POWERPC_POWER8_BASE); 2384 } 2385 #endif /* TARGET_PPC64 */ 2386 return ret; 2387 } 2388 2389 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2390 { 2391 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2392 2393 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2394 return 2; 2395 } else if ((!l1d_thread_priv_req || 2396 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2397 (c.character & c.character_mask 2398 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2399 return 1; 2400 } 2401 2402 return 0; 2403 } 2404 2405 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2406 { 2407 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2408 return 2; 2409 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2410 return 1; 2411 } 2412 2413 return 0; 2414 } 2415 2416 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2417 { 2418 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2419 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2420 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2421 return SPAPR_CAP_FIXED_NA; 2422 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2423 return SPAPR_CAP_WORKAROUND; 2424 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2425 return SPAPR_CAP_FIXED_CCD; 2426 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2427 return SPAPR_CAP_FIXED_IBS; 2428 } 2429 2430 return 0; 2431 } 2432 2433 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2434 { 2435 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2436 return 1; 2437 } 2438 return 0; 2439 } 2440 2441 bool kvmppc_has_cap_xive(void) 2442 { 2443 return cap_xive; 2444 } 2445 2446 static void kvmppc_get_cpu_characteristics(KVMState *s) 2447 { 2448 struct kvm_ppc_cpu_char c; 2449 int ret; 2450 2451 /* Assume broken */ 2452 cap_ppc_safe_cache = 0; 2453 cap_ppc_safe_bounds_check = 0; 2454 cap_ppc_safe_indirect_branch = 0; 2455 2456 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2457 if (!ret) { 2458 return; 2459 } 2460 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2461 if (ret < 0) { 2462 return; 2463 } 2464 2465 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2466 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2467 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2468 cap_ppc_count_cache_flush_assist = 2469 parse_cap_ppc_count_cache_flush_assist(c); 2470 } 2471 2472 int kvmppc_get_cap_safe_cache(void) 2473 { 2474 return cap_ppc_safe_cache; 2475 } 2476 2477 int kvmppc_get_cap_safe_bounds_check(void) 2478 { 2479 return cap_ppc_safe_bounds_check; 2480 } 2481 2482 int kvmppc_get_cap_safe_indirect_branch(void) 2483 { 2484 return cap_ppc_safe_indirect_branch; 2485 } 2486 2487 int kvmppc_get_cap_count_cache_flush_assist(void) 2488 { 2489 return cap_ppc_count_cache_flush_assist; 2490 } 2491 2492 bool kvmppc_has_cap_nested_kvm_hv(void) 2493 { 2494 return !!cap_ppc_nested_kvm_hv; 2495 } 2496 2497 int kvmppc_set_cap_nested_kvm_hv(int enable) 2498 { 2499 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2500 } 2501 2502 bool kvmppc_has_cap_spapr_vfio(void) 2503 { 2504 return cap_spapr_vfio; 2505 } 2506 2507 int kvmppc_get_cap_large_decr(void) 2508 { 2509 return cap_large_decr; 2510 } 2511 2512 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2513 { 2514 CPUState *cs = CPU(cpu); 2515 uint64_t lpcr; 2516 2517 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2518 /* Do we need to modify the LPCR? */ 2519 if (!!(lpcr & LPCR_LD) != !!enable) { 2520 if (enable) { 2521 lpcr |= LPCR_LD; 2522 } else { 2523 lpcr &= ~LPCR_LD; 2524 } 2525 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2526 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2527 2528 if (!!(lpcr & LPCR_LD) != !!enable) { 2529 return -1; 2530 } 2531 } 2532 2533 return 0; 2534 } 2535 2536 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2537 { 2538 uint32_t host_pvr = mfpvr(); 2539 PowerPCCPUClass *pvr_pcc; 2540 2541 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2542 if (pvr_pcc == NULL) { 2543 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2544 } 2545 2546 return pvr_pcc; 2547 } 2548 2549 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2550 { 2551 MachineClass *mc = MACHINE_CLASS(oc); 2552 2553 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2554 } 2555 2556 static int kvm_ppc_register_host_cpu_type(void) 2557 { 2558 TypeInfo type_info = { 2559 .name = TYPE_HOST_POWERPC_CPU, 2560 .class_init = kvmppc_host_cpu_class_init, 2561 }; 2562 PowerPCCPUClass *pvr_pcc; 2563 ObjectClass *oc; 2564 DeviceClass *dc; 2565 int i; 2566 2567 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2568 if (pvr_pcc == NULL) { 2569 return -1; 2570 } 2571 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2572 type_register(&type_info); 2573 /* override TCG default cpu type with 'host' cpu model */ 2574 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2575 false, NULL); 2576 2577 oc = object_class_by_name(type_info.name); 2578 g_assert(oc); 2579 2580 /* 2581 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2582 * we want "POWER8" to be a "family" alias that points to the current 2583 * host CPU type, too) 2584 */ 2585 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2586 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2587 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2588 char *suffix; 2589 2590 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2591 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2592 if (suffix) { 2593 *suffix = 0; 2594 } 2595 break; 2596 } 2597 } 2598 2599 return 0; 2600 } 2601 2602 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2603 { 2604 struct kvm_rtas_token_args args = { 2605 .token = token, 2606 }; 2607 2608 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2609 return -ENOENT; 2610 } 2611 2612 strncpy(args.name, function, sizeof(args.name) - 1); 2613 2614 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2615 } 2616 2617 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2618 { 2619 struct kvm_get_htab_fd s = { 2620 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2621 .start_index = index, 2622 }; 2623 int ret; 2624 2625 if (!cap_htab_fd) { 2626 error_setg(errp, "KVM version doesn't support %s the HPT", 2627 write ? "writing" : "reading"); 2628 return -ENOTSUP; 2629 } 2630 2631 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2632 if (ret < 0) { 2633 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2634 write ? "writing" : "reading", write ? "to" : "from", 2635 strerror(errno)); 2636 return -errno; 2637 } 2638 2639 return ret; 2640 } 2641 2642 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2643 { 2644 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2645 uint8_t buf[bufsize]; 2646 ssize_t rc; 2647 2648 do { 2649 rc = read(fd, buf, bufsize); 2650 if (rc < 0) { 2651 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2652 strerror(errno)); 2653 return rc; 2654 } else if (rc) { 2655 uint8_t *buffer = buf; 2656 ssize_t n = rc; 2657 while (n) { 2658 struct kvm_get_htab_header *head = 2659 (struct kvm_get_htab_header *) buffer; 2660 size_t chunksize = sizeof(*head) + 2661 HASH_PTE_SIZE_64 * head->n_valid; 2662 2663 qemu_put_be32(f, head->index); 2664 qemu_put_be16(f, head->n_valid); 2665 qemu_put_be16(f, head->n_invalid); 2666 qemu_put_buffer(f, (void *)(head + 1), 2667 HASH_PTE_SIZE_64 * head->n_valid); 2668 2669 buffer += chunksize; 2670 n -= chunksize; 2671 } 2672 } 2673 } while ((rc != 0) 2674 && ((max_ns < 0) || 2675 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2676 2677 return (rc == 0) ? 1 : 0; 2678 } 2679 2680 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2681 uint16_t n_valid, uint16_t n_invalid) 2682 { 2683 struct kvm_get_htab_header *buf; 2684 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2685 ssize_t rc; 2686 2687 buf = alloca(chunksize); 2688 buf->index = index; 2689 buf->n_valid = n_valid; 2690 buf->n_invalid = n_invalid; 2691 2692 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2693 2694 rc = write(fd, buf, chunksize); 2695 if (rc < 0) { 2696 fprintf(stderr, "Error writing KVM hash table: %s\n", 2697 strerror(errno)); 2698 return rc; 2699 } 2700 if (rc != chunksize) { 2701 /* We should never get a short write on a single chunk */ 2702 fprintf(stderr, "Short write, restoring KVM hash table\n"); 2703 return -1; 2704 } 2705 return 0; 2706 } 2707 2708 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2709 { 2710 return true; 2711 } 2712 2713 void kvm_arch_init_irq_routing(KVMState *s) 2714 { 2715 } 2716 2717 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2718 { 2719 int fd, rc; 2720 int i; 2721 2722 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2723 2724 i = 0; 2725 while (i < n) { 2726 struct kvm_get_htab_header *hdr; 2727 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2728 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2729 2730 rc = read(fd, buf, sizeof(buf)); 2731 if (rc < 0) { 2732 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2733 } 2734 2735 hdr = (struct kvm_get_htab_header *)buf; 2736 while ((i < n) && ((char *)hdr < (buf + rc))) { 2737 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2738 2739 if (hdr->index != (ptex + i)) { 2740 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2741 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2742 } 2743 2744 if (n - i < valid) { 2745 valid = n - i; 2746 } 2747 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2748 i += valid; 2749 2750 if ((n - i) < invalid) { 2751 invalid = n - i; 2752 } 2753 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2754 i += invalid; 2755 2756 hdr = (struct kvm_get_htab_header *) 2757 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2758 } 2759 } 2760 2761 close(fd); 2762 } 2763 2764 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2765 { 2766 int fd, rc; 2767 struct { 2768 struct kvm_get_htab_header hdr; 2769 uint64_t pte0; 2770 uint64_t pte1; 2771 } buf; 2772 2773 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2774 2775 buf.hdr.n_valid = 1; 2776 buf.hdr.n_invalid = 0; 2777 buf.hdr.index = ptex; 2778 buf.pte0 = cpu_to_be64(pte0); 2779 buf.pte1 = cpu_to_be64(pte1); 2780 2781 rc = write(fd, &buf, sizeof(buf)); 2782 if (rc != sizeof(buf)) { 2783 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2784 } 2785 close(fd); 2786 } 2787 2788 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2789 uint64_t address, uint32_t data, PCIDevice *dev) 2790 { 2791 return 0; 2792 } 2793 2794 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2795 int vector, PCIDevice *dev) 2796 { 2797 return 0; 2798 } 2799 2800 int kvm_arch_release_virq_post(int virq) 2801 { 2802 return 0; 2803 } 2804 2805 int kvm_arch_msi_data_to_gsi(uint32_t data) 2806 { 2807 return data & 0xffff; 2808 } 2809 2810 #if defined(TARGET_PPC64) 2811 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) 2812 { 2813 bool recovered = run->flags & KVM_RUN_PPC_NMI_DISP_FULLY_RECOV; 2814 2815 cpu_synchronize_state(CPU(cpu)); 2816 2817 spapr_mce_req_event(cpu, recovered); 2818 2819 return 0; 2820 } 2821 #endif 2822 2823 int kvmppc_enable_hwrng(void) 2824 { 2825 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2826 return -1; 2827 } 2828 2829 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2830 } 2831 2832 void kvmppc_check_papr_resize_hpt(Error **errp) 2833 { 2834 if (!kvm_enabled()) { 2835 return; /* No KVM, we're good */ 2836 } 2837 2838 if (cap_resize_hpt) { 2839 return; /* Kernel has explicit support, we're good */ 2840 } 2841 2842 /* Otherwise fallback on looking for PR KVM */ 2843 if (kvmppc_is_pr(kvm_state)) { 2844 return; 2845 } 2846 2847 error_setg(errp, 2848 "Hash page table resizing not available with this KVM version"); 2849 } 2850 2851 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2852 { 2853 CPUState *cs = CPU(cpu); 2854 struct kvm_ppc_resize_hpt rhpt = { 2855 .flags = flags, 2856 .shift = shift, 2857 }; 2858 2859 if (!cap_resize_hpt) { 2860 return -ENOSYS; 2861 } 2862 2863 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2864 } 2865 2866 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2867 { 2868 CPUState *cs = CPU(cpu); 2869 struct kvm_ppc_resize_hpt rhpt = { 2870 .flags = flags, 2871 .shift = shift, 2872 }; 2873 2874 if (!cap_resize_hpt) { 2875 return -ENOSYS; 2876 } 2877 2878 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2879 } 2880 2881 /* 2882 * This is a helper function to detect a post migration scenario 2883 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2884 * the guest kernel can't handle a PVR value other than the actual host 2885 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2886 * 2887 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2888 * (so, we're HV), return true. The workaround itself is done in 2889 * cpu_post_load. 2890 * 2891 * The order here is important: we'll only check for KVM PR as a 2892 * fallback if the guest kernel can't handle the situation itself. 2893 * We need to avoid as much as possible querying the running KVM type 2894 * in QEMU level. 2895 */ 2896 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2897 { 2898 CPUState *cs = CPU(cpu); 2899 2900 if (!kvm_enabled()) { 2901 return false; 2902 } 2903 2904 if (cap_ppc_pvr_compat) { 2905 return false; 2906 } 2907 2908 return !kvmppc_is_pr(cs->kvm_state); 2909 } 2910 2911 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2912 { 2913 CPUState *cs = CPU(cpu); 2914 2915 if (kvm_enabled()) { 2916 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2917 } 2918 } 2919 2920 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2921 { 2922 CPUState *cs = CPU(cpu); 2923 2924 if (kvm_enabled()) { 2925 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2926 } 2927 } 2928 2929 /* 2930 * Don't set error if KVM_PPC_SVM_OFF ioctl is invoked on kernels 2931 * that don't support this ioctl. 2932 */ 2933 void kvmppc_svm_off(Error **errp) 2934 { 2935 int rc; 2936 2937 if (!kvm_enabled()) { 2938 return; 2939 } 2940 2941 rc = kvm_vm_ioctl(KVM_STATE(current_accel()), KVM_PPC_SVM_OFF); 2942 if (rc && rc != -ENOTTY) { 2943 error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed"); 2944 } 2945 } 2946