1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "cpu.h" 27 #include "cpu-models.h" 28 #include "qemu/timer.h" 29 #include "sysemu/hw_accel.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "mmu-hash64.h" 34 35 #include "hw/ppc/spapr.h" 36 #include "hw/ppc/spapr_cpu_core.h" 37 #include "hw/hw.h" 38 #include "hw/ppc/ppc.h" 39 #include "migration/qemu-file-types.h" 40 #include "sysemu/watchdog.h" 41 #include "trace.h" 42 #include "exec/gdbstub.h" 43 #include "exec/memattrs.h" 44 #include "exec/ram_addr.h" 45 #include "sysemu/hostmem.h" 46 #include "qemu/cutils.h" 47 #include "qemu/main-loop.h" 48 #include "qemu/mmap-alloc.h" 49 #include "elf.h" 50 #include "sysemu/kvm_int.h" 51 52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 53 54 #define DEBUG_RETURN_GUEST 0 55 #define DEBUG_RETURN_GDB 1 56 57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 58 KVM_CAP_LAST_INFO 59 }; 60 61 static int cap_interrupt_unset; 62 static int cap_segstate; 63 static int cap_booke_sregs; 64 static int cap_ppc_smt; 65 static int cap_ppc_smt_possible; 66 static int cap_spapr_tce; 67 static int cap_spapr_tce_64; 68 static int cap_spapr_multitce; 69 static int cap_spapr_vfio; 70 static int cap_hior; 71 static int cap_one_reg; 72 static int cap_epr; 73 static int cap_ppc_watchdog; 74 static int cap_papr; 75 static int cap_htab_fd; 76 static int cap_fixup_hcalls; 77 static int cap_htm; /* Hardware transactional memory support */ 78 static int cap_mmu_radix; 79 static int cap_mmu_hash_v3; 80 static int cap_xive; 81 static int cap_resize_hpt; 82 static int cap_ppc_pvr_compat; 83 static int cap_ppc_safe_cache; 84 static int cap_ppc_safe_bounds_check; 85 static int cap_ppc_safe_indirect_branch; 86 static int cap_ppc_count_cache_flush_assist; 87 static int cap_ppc_nested_kvm_hv; 88 static int cap_large_decr; 89 static int cap_fwnmi; 90 static int cap_rpt_invalidate; 91 static int cap_ail_mode_3; 92 93 static uint32_t debug_inst_opcode; 94 95 /* 96 * Check whether we are running with KVM-PR (instead of KVM-HV). This 97 * should only be used for fallback tests - generally we should use 98 * explicit capabilities for the features we want, rather than 99 * assuming what is/isn't available depending on the KVM variant. 100 */ 101 static bool kvmppc_is_pr(KVMState *ks) 102 { 103 /* Assume KVM-PR if the GET_PVINFO capability is available */ 104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 105 } 106 107 static int kvm_ppc_register_host_cpu_type(void); 108 static void kvmppc_get_cpu_characteristics(KVMState *s); 109 static int kvmppc_get_dec_bits(void); 110 111 int kvm_arch_init(MachineState *ms, KVMState *s) 112 { 113 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 114 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 115 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 116 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 117 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 118 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 119 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 120 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 121 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 122 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 123 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 124 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 125 /* 126 * Note: we don't set cap_papr here, because this capability is 127 * only activated after this by kvmppc_set_papr() 128 */ 129 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 130 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 131 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 132 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 133 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 134 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 135 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 136 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 137 kvmppc_get_cpu_characteristics(s); 138 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 139 cap_large_decr = kvmppc_get_dec_bits(); 140 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI); 141 /* 142 * Note: setting it to false because there is not such capability 143 * in KVM at this moment. 144 * 145 * TODO: call kvm_vm_check_extension() with the right capability 146 * after the kernel starts implementing it. 147 */ 148 cap_ppc_pvr_compat = false; 149 150 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 151 error_report("KVM: Host kernel doesn't have level irq capability"); 152 exit(1); 153 } 154 155 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE); 156 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3); 157 kvm_ppc_register_host_cpu_type(); 158 159 return 0; 160 } 161 162 int kvm_arch_irqchip_create(KVMState *s) 163 { 164 return 0; 165 } 166 167 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 168 { 169 CPUPPCState *cenv = &cpu->env; 170 CPUState *cs = CPU(cpu); 171 struct kvm_sregs sregs; 172 int ret; 173 174 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 175 /* 176 * What we're really trying to say is "if we're on BookE, we 177 * use the native PVR for now". This is the only sane way to 178 * check it though, so we potentially confuse users that they 179 * can run BookE guests on BookS. Let's hope nobody dares 180 * enough :) 181 */ 182 return 0; 183 } else { 184 if (!cap_segstate) { 185 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 186 return -ENOSYS; 187 } 188 } 189 190 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 191 if (ret) { 192 return ret; 193 } 194 195 sregs.pvr = cenv->spr[SPR_PVR]; 196 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 197 } 198 199 /* Set up a shared TLB array with KVM */ 200 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 201 { 202 CPUPPCState *env = &cpu->env; 203 CPUState *cs = CPU(cpu); 204 struct kvm_book3e_206_tlb_params params = {}; 205 struct kvm_config_tlb cfg = {}; 206 unsigned int entries = 0; 207 int ret, i; 208 209 if (!kvm_enabled() || 210 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 211 return 0; 212 } 213 214 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 215 216 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 217 params.tlb_sizes[i] = booke206_tlb_size(env, i); 218 params.tlb_ways[i] = booke206_tlb_ways(env, i); 219 entries += params.tlb_sizes[i]; 220 } 221 222 assert(entries == env->nb_tlb); 223 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 224 225 env->tlb_dirty = true; 226 227 cfg.array = (uintptr_t)env->tlb.tlbm; 228 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 229 cfg.params = (uintptr_t)¶ms; 230 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 231 232 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 233 if (ret < 0) { 234 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 235 __func__, strerror(-ret)); 236 return ret; 237 } 238 239 env->kvm_sw_tlb = true; 240 return 0; 241 } 242 243 244 #if defined(TARGET_PPC64) 245 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 246 { 247 int ret; 248 249 assert(kvm_state != NULL); 250 251 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 252 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 253 error_append_hint(errp, "Consider switching to a newer KVM\n"); 254 return; 255 } 256 257 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 258 if (ret == 0) { 259 return; 260 } 261 262 error_setg_errno(errp, -ret, 263 "KVM failed to provide the MMU features it supports"); 264 } 265 266 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 267 { 268 KVMState *s = KVM_STATE(current_accel()); 269 struct ppc_radix_page_info *radix_page_info; 270 struct kvm_ppc_rmmu_info rmmu_info = { }; 271 int i; 272 273 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 274 return NULL; 275 } 276 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 277 return NULL; 278 } 279 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 280 radix_page_info->count = 0; 281 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 282 if (rmmu_info.ap_encodings[i]) { 283 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 284 radix_page_info->count++; 285 } 286 } 287 return radix_page_info; 288 } 289 290 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 291 bool radix, bool gtse, 292 uint64_t proc_tbl) 293 { 294 CPUState *cs = CPU(cpu); 295 int ret; 296 uint64_t flags = 0; 297 struct kvm_ppc_mmuv3_cfg cfg = { 298 .process_table = proc_tbl, 299 }; 300 301 if (radix) { 302 flags |= KVM_PPC_MMUV3_RADIX; 303 } 304 if (gtse) { 305 flags |= KVM_PPC_MMUV3_GTSE; 306 } 307 cfg.flags = flags; 308 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 309 switch (ret) { 310 case 0: 311 return H_SUCCESS; 312 case -EINVAL: 313 return H_PARAMETER; 314 case -ENODEV: 315 return H_NOT_AVAILABLE; 316 default: 317 return H_HARDWARE; 318 } 319 } 320 321 bool kvmppc_hpt_needs_host_contiguous_pages(void) 322 { 323 static struct kvm_ppc_smmu_info smmu_info; 324 325 if (!kvm_enabled()) { 326 return false; 327 } 328 329 kvm_get_smmu_info(&smmu_info, &error_fatal); 330 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 331 } 332 333 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 334 { 335 struct kvm_ppc_smmu_info smmu_info; 336 int iq, ik, jq, jk; 337 Error *local_err = NULL; 338 339 /* For now, we only have anything to check on hash64 MMUs */ 340 if (!cpu->hash64_opts || !kvm_enabled()) { 341 return; 342 } 343 344 kvm_get_smmu_info(&smmu_info, &local_err); 345 if (local_err) { 346 error_propagate(errp, local_err); 347 return; 348 } 349 350 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 351 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 352 error_setg(errp, 353 "KVM does not support 1TiB segments which guest expects"); 354 return; 355 } 356 357 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 358 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 359 smmu_info.slb_size, cpu->hash64_opts->slb_size); 360 return; 361 } 362 363 /* 364 * Verify that every pagesize supported by the cpu model is 365 * supported by KVM with the same encodings 366 */ 367 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 368 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 369 struct kvm_ppc_one_seg_page_size *ksps; 370 371 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 372 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 373 break; 374 } 375 } 376 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 377 error_setg(errp, "KVM doesn't support for base page shift %u", 378 qsps->page_shift); 379 return; 380 } 381 382 ksps = &smmu_info.sps[ik]; 383 if (ksps->slb_enc != qsps->slb_enc) { 384 error_setg(errp, 385 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 386 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 387 return; 388 } 389 390 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 391 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 392 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 393 break; 394 } 395 } 396 397 if (jk >= ARRAY_SIZE(ksps->enc)) { 398 error_setg(errp, "KVM doesn't support page shift %u/%u", 399 qsps->enc[jq].page_shift, qsps->page_shift); 400 return; 401 } 402 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 403 error_setg(errp, 404 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 405 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 406 qsps->page_shift, qsps->enc[jq].pte_enc); 407 return; 408 } 409 } 410 } 411 412 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 413 /* 414 * Mostly what guest pagesizes we can use are related to the 415 * host pages used to map guest RAM, which is handled in the 416 * platform code. Cache-Inhibited largepages (64k) however are 417 * used for I/O, so if they're mapped to the host at all it 418 * will be a normal mapping, not a special hugepage one used 419 * for RAM. 420 */ 421 if (qemu_real_host_page_size() < 0x10000) { 422 error_setg(errp, 423 "KVM can't supply 64kiB CI pages, which guest expects"); 424 } 425 } 426 } 427 #endif /* !defined (TARGET_PPC64) */ 428 429 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 430 { 431 return POWERPC_CPU(cpu)->vcpu_id; 432 } 433 434 /* 435 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 436 * only 1 watchpoint, so array size of 4 is sufficient for now. 437 */ 438 #define MAX_HW_BKPTS 4 439 440 static struct HWBreakpoint { 441 target_ulong addr; 442 int type; 443 } hw_debug_points[MAX_HW_BKPTS]; 444 445 static CPUWatchpoint hw_watchpoint; 446 447 /* Default there is no breakpoint and watchpoint supported */ 448 static int max_hw_breakpoint; 449 static int max_hw_watchpoint; 450 static int nb_hw_breakpoint; 451 static int nb_hw_watchpoint; 452 453 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 454 { 455 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 456 max_hw_breakpoint = 2; 457 max_hw_watchpoint = 2; 458 } 459 460 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 461 fprintf(stderr, "Error initializing h/w breakpoints\n"); 462 return; 463 } 464 } 465 466 int kvm_arch_init_vcpu(CPUState *cs) 467 { 468 PowerPCCPU *cpu = POWERPC_CPU(cs); 469 CPUPPCState *cenv = &cpu->env; 470 int ret; 471 472 /* Synchronize sregs with kvm */ 473 ret = kvm_arch_sync_sregs(cpu); 474 if (ret) { 475 if (ret == -EINVAL) { 476 error_report("Register sync failed... If you're using kvm-hv.ko," 477 " only \"-cpu host\" is possible"); 478 } 479 return ret; 480 } 481 482 switch (cenv->mmu_model) { 483 case POWERPC_MMU_BOOKE206: 484 /* This target supports access to KVM's guest TLB */ 485 ret = kvm_booke206_tlb_init(cpu); 486 break; 487 case POWERPC_MMU_2_07: 488 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 489 /* 490 * KVM-HV has transactional memory on POWER8 also without 491 * the KVM_CAP_PPC_HTM extension, so enable it here 492 * instead as long as it's available to userspace on the 493 * host. 494 */ 495 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 496 cap_htm = true; 497 } 498 } 499 break; 500 default: 501 break; 502 } 503 504 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 505 kvmppc_hw_debug_points_init(cenv); 506 507 return ret; 508 } 509 510 int kvm_arch_destroy_vcpu(CPUState *cs) 511 { 512 return 0; 513 } 514 515 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 516 { 517 CPUPPCState *env = &cpu->env; 518 CPUState *cs = CPU(cpu); 519 struct kvm_dirty_tlb dirty_tlb; 520 unsigned char *bitmap; 521 int ret; 522 523 if (!env->kvm_sw_tlb) { 524 return; 525 } 526 527 bitmap = g_malloc((env->nb_tlb + 7) / 8); 528 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 529 530 dirty_tlb.bitmap = (uintptr_t)bitmap; 531 dirty_tlb.num_dirty = env->nb_tlb; 532 533 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 534 if (ret) { 535 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 536 __func__, strerror(-ret)); 537 } 538 539 g_free(bitmap); 540 } 541 542 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 543 { 544 PowerPCCPU *cpu = POWERPC_CPU(cs); 545 CPUPPCState *env = &cpu->env; 546 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ 547 union { 548 uint32_t u32; 549 uint64_t u64; 550 } val = { }; 551 struct kvm_one_reg reg = { 552 .id = id, 553 .addr = (uintptr_t) &val, 554 }; 555 int ret; 556 557 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 558 if (ret != 0) { 559 trace_kvm_failed_spr_get(spr, strerror(errno)); 560 } else { 561 switch (id & KVM_REG_SIZE_MASK) { 562 case KVM_REG_SIZE_U32: 563 env->spr[spr] = val.u32; 564 break; 565 566 case KVM_REG_SIZE_U64: 567 env->spr[spr] = val.u64; 568 break; 569 570 default: 571 /* Don't handle this size yet */ 572 abort(); 573 } 574 } 575 } 576 577 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 578 { 579 PowerPCCPU *cpu = POWERPC_CPU(cs); 580 CPUPPCState *env = &cpu->env; 581 union { 582 uint32_t u32; 583 uint64_t u64; 584 } val; 585 struct kvm_one_reg reg = { 586 .id = id, 587 .addr = (uintptr_t) &val, 588 }; 589 int ret; 590 591 switch (id & KVM_REG_SIZE_MASK) { 592 case KVM_REG_SIZE_U32: 593 val.u32 = env->spr[spr]; 594 break; 595 596 case KVM_REG_SIZE_U64: 597 val.u64 = env->spr[spr]; 598 break; 599 600 default: 601 /* Don't handle this size yet */ 602 abort(); 603 } 604 605 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 606 if (ret != 0) { 607 trace_kvm_failed_spr_set(spr, strerror(errno)); 608 } 609 } 610 611 static int kvm_put_fp(CPUState *cs) 612 { 613 PowerPCCPU *cpu = POWERPC_CPU(cs); 614 CPUPPCState *env = &cpu->env; 615 struct kvm_one_reg reg; 616 int i; 617 int ret; 618 619 if (env->insns_flags & PPC_FLOAT) { 620 uint64_t fpscr = env->fpscr; 621 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 622 623 reg.id = KVM_REG_PPC_FPSCR; 624 reg.addr = (uintptr_t)&fpscr; 625 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 626 if (ret < 0) { 627 trace_kvm_failed_fpscr_set(strerror(errno)); 628 return ret; 629 } 630 631 for (i = 0; i < 32; i++) { 632 uint64_t vsr[2]; 633 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 634 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 635 636 #if HOST_BIG_ENDIAN 637 vsr[0] = float64_val(*fpr); 638 vsr[1] = *vsrl; 639 #else 640 vsr[0] = *vsrl; 641 vsr[1] = float64_val(*fpr); 642 #endif 643 reg.addr = (uintptr_t) &vsr; 644 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 645 646 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 647 if (ret < 0) { 648 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 649 strerror(errno)); 650 return ret; 651 } 652 } 653 } 654 655 if (env->insns_flags & PPC_ALTIVEC) { 656 reg.id = KVM_REG_PPC_VSCR; 657 reg.addr = (uintptr_t)&env->vscr; 658 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 659 if (ret < 0) { 660 trace_kvm_failed_vscr_set(strerror(errno)); 661 return ret; 662 } 663 664 for (i = 0; i < 32; i++) { 665 reg.id = KVM_REG_PPC_VR(i); 666 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 667 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 668 if (ret < 0) { 669 trace_kvm_failed_vr_set(i, strerror(errno)); 670 return ret; 671 } 672 } 673 } 674 675 return 0; 676 } 677 678 static int kvm_get_fp(CPUState *cs) 679 { 680 PowerPCCPU *cpu = POWERPC_CPU(cs); 681 CPUPPCState *env = &cpu->env; 682 struct kvm_one_reg reg; 683 int i; 684 int ret; 685 686 if (env->insns_flags & PPC_FLOAT) { 687 uint64_t fpscr; 688 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 689 690 reg.id = KVM_REG_PPC_FPSCR; 691 reg.addr = (uintptr_t)&fpscr; 692 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 693 if (ret < 0) { 694 trace_kvm_failed_fpscr_get(strerror(errno)); 695 return ret; 696 } else { 697 env->fpscr = fpscr; 698 } 699 700 for (i = 0; i < 32; i++) { 701 uint64_t vsr[2]; 702 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 703 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 704 705 reg.addr = (uintptr_t) &vsr; 706 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 707 708 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 709 if (ret < 0) { 710 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 711 strerror(errno)); 712 return ret; 713 } else { 714 #if HOST_BIG_ENDIAN 715 *fpr = vsr[0]; 716 if (vsx) { 717 *vsrl = vsr[1]; 718 } 719 #else 720 *fpr = vsr[1]; 721 if (vsx) { 722 *vsrl = vsr[0]; 723 } 724 #endif 725 } 726 } 727 } 728 729 if (env->insns_flags & PPC_ALTIVEC) { 730 reg.id = KVM_REG_PPC_VSCR; 731 reg.addr = (uintptr_t)&env->vscr; 732 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 733 if (ret < 0) { 734 trace_kvm_failed_vscr_get(strerror(errno)); 735 return ret; 736 } 737 738 for (i = 0; i < 32; i++) { 739 reg.id = KVM_REG_PPC_VR(i); 740 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 741 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 742 if (ret < 0) { 743 trace_kvm_failed_vr_get(i, strerror(errno)); 744 return ret; 745 } 746 } 747 } 748 749 return 0; 750 } 751 752 #if defined(TARGET_PPC64) 753 static int kvm_get_vpa(CPUState *cs) 754 { 755 PowerPCCPU *cpu = POWERPC_CPU(cs); 756 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 757 struct kvm_one_reg reg; 758 int ret; 759 760 reg.id = KVM_REG_PPC_VPA_ADDR; 761 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 762 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 763 if (ret < 0) { 764 trace_kvm_failed_vpa_addr_get(strerror(errno)); 765 return ret; 766 } 767 768 assert((uintptr_t)&spapr_cpu->slb_shadow_size 769 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 770 reg.id = KVM_REG_PPC_VPA_SLB; 771 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 772 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 773 if (ret < 0) { 774 trace_kvm_failed_slb_get(strerror(errno)); 775 return ret; 776 } 777 778 assert((uintptr_t)&spapr_cpu->dtl_size 779 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 780 reg.id = KVM_REG_PPC_VPA_DTL; 781 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 782 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 783 if (ret < 0) { 784 trace_kvm_failed_dtl_get(strerror(errno)); 785 return ret; 786 } 787 788 return 0; 789 } 790 791 static int kvm_put_vpa(CPUState *cs) 792 { 793 PowerPCCPU *cpu = POWERPC_CPU(cs); 794 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 795 struct kvm_one_reg reg; 796 int ret; 797 798 /* 799 * SLB shadow or DTL can't be registered unless a master VPA is 800 * registered. That means when restoring state, if a VPA *is* 801 * registered, we need to set that up first. If not, we need to 802 * deregister the others before deregistering the master VPA 803 */ 804 assert(spapr_cpu->vpa_addr 805 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 806 807 if (spapr_cpu->vpa_addr) { 808 reg.id = KVM_REG_PPC_VPA_ADDR; 809 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 810 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 811 if (ret < 0) { 812 trace_kvm_failed_vpa_addr_set(strerror(errno)); 813 return ret; 814 } 815 } 816 817 assert((uintptr_t)&spapr_cpu->slb_shadow_size 818 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 819 reg.id = KVM_REG_PPC_VPA_SLB; 820 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 821 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 822 if (ret < 0) { 823 trace_kvm_failed_slb_set(strerror(errno)); 824 return ret; 825 } 826 827 assert((uintptr_t)&spapr_cpu->dtl_size 828 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 829 reg.id = KVM_REG_PPC_VPA_DTL; 830 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 831 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 832 if (ret < 0) { 833 trace_kvm_failed_dtl_set(strerror(errno)); 834 return ret; 835 } 836 837 if (!spapr_cpu->vpa_addr) { 838 reg.id = KVM_REG_PPC_VPA_ADDR; 839 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 840 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 841 if (ret < 0) { 842 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 843 return ret; 844 } 845 } 846 847 return 0; 848 } 849 #endif /* TARGET_PPC64 */ 850 851 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 852 { 853 CPUPPCState *env = &cpu->env; 854 struct kvm_sregs sregs = { }; 855 int i; 856 857 sregs.pvr = env->spr[SPR_PVR]; 858 859 if (cpu->vhyp) { 860 PPCVirtualHypervisorClass *vhc = 861 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 862 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 863 } else { 864 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 865 } 866 867 /* Sync SLB */ 868 #ifdef TARGET_PPC64 869 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 870 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 871 if (env->slb[i].esid & SLB_ESID_V) { 872 sregs.u.s.ppc64.slb[i].slbe |= i; 873 } 874 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 875 } 876 #endif 877 878 /* Sync SRs */ 879 for (i = 0; i < 16; i++) { 880 sregs.u.s.ppc32.sr[i] = env->sr[i]; 881 } 882 883 /* Sync BATs */ 884 for (i = 0; i < 8; i++) { 885 /* Beware. We have to swap upper and lower bits here */ 886 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 887 | env->DBAT[1][i]; 888 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 889 | env->IBAT[1][i]; 890 } 891 892 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 893 } 894 895 int kvm_arch_put_registers(CPUState *cs, int level) 896 { 897 PowerPCCPU *cpu = POWERPC_CPU(cs); 898 CPUPPCState *env = &cpu->env; 899 struct kvm_regs regs; 900 int ret; 901 int i; 902 903 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 904 if (ret < 0) { 905 return ret; 906 } 907 908 regs.ctr = env->ctr; 909 regs.lr = env->lr; 910 regs.xer = cpu_read_xer(env); 911 regs.msr = env->msr; 912 regs.pc = env->nip; 913 914 regs.srr0 = env->spr[SPR_SRR0]; 915 regs.srr1 = env->spr[SPR_SRR1]; 916 917 regs.sprg0 = env->spr[SPR_SPRG0]; 918 regs.sprg1 = env->spr[SPR_SPRG1]; 919 regs.sprg2 = env->spr[SPR_SPRG2]; 920 regs.sprg3 = env->spr[SPR_SPRG3]; 921 regs.sprg4 = env->spr[SPR_SPRG4]; 922 regs.sprg5 = env->spr[SPR_SPRG5]; 923 regs.sprg6 = env->spr[SPR_SPRG6]; 924 regs.sprg7 = env->spr[SPR_SPRG7]; 925 926 regs.pid = env->spr[SPR_BOOKE_PID]; 927 928 for (i = 0; i < 32; i++) { 929 regs.gpr[i] = env->gpr[i]; 930 } 931 932 regs.cr = ppc_get_cr(env); 933 934 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 935 if (ret < 0) { 936 return ret; 937 } 938 939 kvm_put_fp(cs); 940 941 if (env->tlb_dirty) { 942 kvm_sw_tlb_put(cpu); 943 env->tlb_dirty = false; 944 } 945 946 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 947 ret = kvmppc_put_books_sregs(cpu); 948 if (ret < 0) { 949 return ret; 950 } 951 } 952 953 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 954 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 955 } 956 957 if (cap_one_reg) { 958 int i; 959 960 /* 961 * We deliberately ignore errors here, for kernels which have 962 * the ONE_REG calls, but don't support the specific 963 * registers, there's a reasonable chance things will still 964 * work, at least until we try to migrate. 965 */ 966 for (i = 0; i < 1024; i++) { 967 uint64_t id = env->spr_cb[i].one_reg_id; 968 969 if (id != 0) { 970 kvm_put_one_spr(cs, id, i); 971 } 972 } 973 974 #ifdef TARGET_PPC64 975 if (FIELD_EX64(env->msr, MSR, TS)) { 976 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 978 } 979 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 981 } 982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 992 } 993 994 if (cap_papr) { 995 if (kvm_put_vpa(cs) < 0) { 996 trace_kvm_failed_put_vpa(); 997 } 998 } 999 1000 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1001 1002 if (level > KVM_PUT_RUNTIME_STATE) { 1003 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1004 } 1005 #endif /* TARGET_PPC64 */ 1006 } 1007 1008 return ret; 1009 } 1010 1011 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1012 { 1013 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1014 } 1015 1016 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1017 { 1018 CPUPPCState *env = &cpu->env; 1019 struct kvm_sregs sregs; 1020 int ret; 1021 1022 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1023 if (ret < 0) { 1024 return ret; 1025 } 1026 1027 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1028 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1029 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1030 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1031 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1032 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1033 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1034 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1035 env->spr[SPR_DECR] = sregs.u.e.dec; 1036 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1037 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1038 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1039 } 1040 1041 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1042 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1043 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1044 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1045 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1046 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1047 } 1048 1049 if (sregs.u.e.features & KVM_SREGS_E_64) { 1050 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1051 } 1052 1053 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1054 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1055 } 1056 1057 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1058 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1059 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1060 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1061 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1062 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1063 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1064 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1065 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1066 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1067 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1068 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1069 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1070 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1071 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1072 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1073 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1074 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1075 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1076 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1077 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1078 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1079 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1080 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1081 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1082 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1083 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1084 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1085 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1086 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1087 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1088 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1089 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1090 1091 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1092 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1093 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1094 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1095 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1096 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1097 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1098 } 1099 1100 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1101 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1102 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1103 } 1104 1105 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1106 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1107 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1108 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1109 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1110 } 1111 } 1112 1113 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1114 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1115 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1116 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1117 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1118 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1119 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1120 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1121 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1122 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1123 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1124 } 1125 1126 if (sregs.u.e.features & KVM_SREGS_EXP) { 1127 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1128 } 1129 1130 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1131 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1132 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1133 } 1134 1135 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1136 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1137 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1138 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1139 1140 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1141 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1142 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1143 } 1144 } 1145 1146 return 0; 1147 } 1148 1149 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1150 { 1151 CPUPPCState *env = &cpu->env; 1152 struct kvm_sregs sregs; 1153 int ret; 1154 int i; 1155 1156 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1157 if (ret < 0) { 1158 return ret; 1159 } 1160 1161 if (!cpu->vhyp) { 1162 ppc_store_sdr1(env, sregs.u.s.sdr1); 1163 } 1164 1165 /* Sync SLB */ 1166 #ifdef TARGET_PPC64 1167 /* 1168 * The packed SLB array we get from KVM_GET_SREGS only contains 1169 * information about valid entries. So we flush our internal copy 1170 * to get rid of stale ones, then put all valid SLB entries back 1171 * in. 1172 */ 1173 memset(env->slb, 0, sizeof(env->slb)); 1174 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1175 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1176 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1177 /* 1178 * Only restore valid entries 1179 */ 1180 if (rb & SLB_ESID_V) { 1181 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1182 } 1183 } 1184 #endif 1185 1186 /* Sync SRs */ 1187 for (i = 0; i < 16; i++) { 1188 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1189 } 1190 1191 /* Sync BATs */ 1192 for (i = 0; i < 8; i++) { 1193 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1194 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1195 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1196 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1197 } 1198 1199 return 0; 1200 } 1201 1202 int kvm_arch_get_registers(CPUState *cs) 1203 { 1204 PowerPCCPU *cpu = POWERPC_CPU(cs); 1205 CPUPPCState *env = &cpu->env; 1206 struct kvm_regs regs; 1207 int i, ret; 1208 1209 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1210 if (ret < 0) { 1211 return ret; 1212 } 1213 1214 ppc_set_cr(env, regs.cr); 1215 env->ctr = regs.ctr; 1216 env->lr = regs.lr; 1217 cpu_write_xer(env, regs.xer); 1218 env->msr = regs.msr; 1219 env->nip = regs.pc; 1220 1221 env->spr[SPR_SRR0] = regs.srr0; 1222 env->spr[SPR_SRR1] = regs.srr1; 1223 1224 env->spr[SPR_SPRG0] = regs.sprg0; 1225 env->spr[SPR_SPRG1] = regs.sprg1; 1226 env->spr[SPR_SPRG2] = regs.sprg2; 1227 env->spr[SPR_SPRG3] = regs.sprg3; 1228 env->spr[SPR_SPRG4] = regs.sprg4; 1229 env->spr[SPR_SPRG5] = regs.sprg5; 1230 env->spr[SPR_SPRG6] = regs.sprg6; 1231 env->spr[SPR_SPRG7] = regs.sprg7; 1232 1233 env->spr[SPR_BOOKE_PID] = regs.pid; 1234 1235 for (i = 0; i < 32; i++) { 1236 env->gpr[i] = regs.gpr[i]; 1237 } 1238 1239 kvm_get_fp(cs); 1240 1241 if (cap_booke_sregs) { 1242 ret = kvmppc_get_booke_sregs(cpu); 1243 if (ret < 0) { 1244 return ret; 1245 } 1246 } 1247 1248 if (cap_segstate) { 1249 ret = kvmppc_get_books_sregs(cpu); 1250 if (ret < 0) { 1251 return ret; 1252 } 1253 } 1254 1255 if (cap_hior) { 1256 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1257 } 1258 1259 if (cap_one_reg) { 1260 int i; 1261 1262 /* 1263 * We deliberately ignore errors here, for kernels which have 1264 * the ONE_REG calls, but don't support the specific 1265 * registers, there's a reasonable chance things will still 1266 * work, at least until we try to migrate. 1267 */ 1268 for (i = 0; i < 1024; i++) { 1269 uint64_t id = env->spr_cb[i].one_reg_id; 1270 1271 if (id != 0) { 1272 kvm_get_one_spr(cs, id, i); 1273 } 1274 } 1275 1276 #ifdef TARGET_PPC64 1277 if (FIELD_EX64(env->msr, MSR, TS)) { 1278 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1279 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1280 } 1281 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1282 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1283 } 1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1294 } 1295 1296 if (cap_papr) { 1297 if (kvm_get_vpa(cs) < 0) { 1298 trace_kvm_failed_get_vpa(); 1299 } 1300 } 1301 1302 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1303 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1304 #endif 1305 } 1306 1307 return 0; 1308 } 1309 1310 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1311 { 1312 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1313 1314 if (irq != PPC_INTERRUPT_EXT) { 1315 return 0; 1316 } 1317 1318 if (!kvm_enabled() || !cap_interrupt_unset) { 1319 return 0; 1320 } 1321 1322 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1323 1324 return 0; 1325 } 1326 1327 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1328 { 1329 return; 1330 } 1331 1332 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1333 { 1334 return MEMTXATTRS_UNSPECIFIED; 1335 } 1336 1337 int kvm_arch_process_async_events(CPUState *cs) 1338 { 1339 return cs->halted; 1340 } 1341 1342 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1343 { 1344 CPUState *cs = CPU(cpu); 1345 CPUPPCState *env = &cpu->env; 1346 1347 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && 1348 FIELD_EX64(env->msr, MSR, EE)) { 1349 cs->halted = 1; 1350 cs->exception_index = EXCP_HLT; 1351 } 1352 1353 return 0; 1354 } 1355 1356 /* map dcr access to existing qemu dcr emulation */ 1357 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1358 uint32_t dcrn, uint32_t *data) 1359 { 1360 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1361 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1368 uint32_t dcrn, uint32_t data) 1369 { 1370 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1371 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1372 } 1373 1374 return 0; 1375 } 1376 1377 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1378 { 1379 /* Mixed endian case is not handled */ 1380 uint32_t sc = debug_inst_opcode; 1381 1382 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1383 sizeof(sc), 0) || 1384 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1385 return -EINVAL; 1386 } 1387 1388 return 0; 1389 } 1390 1391 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1392 { 1393 uint32_t sc; 1394 1395 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1396 sc != debug_inst_opcode || 1397 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1398 sizeof(sc), 1)) { 1399 return -EINVAL; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int find_hw_breakpoint(target_ulong addr, int type) 1406 { 1407 int n; 1408 1409 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1410 <= ARRAY_SIZE(hw_debug_points)); 1411 1412 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1413 if (hw_debug_points[n].addr == addr && 1414 hw_debug_points[n].type == type) { 1415 return n; 1416 } 1417 } 1418 1419 return -1; 1420 } 1421 1422 static int find_hw_watchpoint(target_ulong addr, int *flag) 1423 { 1424 int n; 1425 1426 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1427 if (n >= 0) { 1428 *flag = BP_MEM_ACCESS; 1429 return n; 1430 } 1431 1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1433 if (n >= 0) { 1434 *flag = BP_MEM_WRITE; 1435 return n; 1436 } 1437 1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1439 if (n >= 0) { 1440 *flag = BP_MEM_READ; 1441 return n; 1442 } 1443 1444 return -1; 1445 } 1446 1447 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1448 target_ulong len, int type) 1449 { 1450 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1451 return -ENOBUFS; 1452 } 1453 1454 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1455 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1456 1457 switch (type) { 1458 case GDB_BREAKPOINT_HW: 1459 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1460 return -ENOBUFS; 1461 } 1462 1463 if (find_hw_breakpoint(addr, type) >= 0) { 1464 return -EEXIST; 1465 } 1466 1467 nb_hw_breakpoint++; 1468 break; 1469 1470 case GDB_WATCHPOINT_WRITE: 1471 case GDB_WATCHPOINT_READ: 1472 case GDB_WATCHPOINT_ACCESS: 1473 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1474 return -ENOBUFS; 1475 } 1476 1477 if (find_hw_breakpoint(addr, type) >= 0) { 1478 return -EEXIST; 1479 } 1480 1481 nb_hw_watchpoint++; 1482 break; 1483 1484 default: 1485 return -ENOSYS; 1486 } 1487 1488 return 0; 1489 } 1490 1491 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1492 target_ulong len, int type) 1493 { 1494 int n; 1495 1496 n = find_hw_breakpoint(addr, type); 1497 if (n < 0) { 1498 return -ENOENT; 1499 } 1500 1501 switch (type) { 1502 case GDB_BREAKPOINT_HW: 1503 nb_hw_breakpoint--; 1504 break; 1505 1506 case GDB_WATCHPOINT_WRITE: 1507 case GDB_WATCHPOINT_READ: 1508 case GDB_WATCHPOINT_ACCESS: 1509 nb_hw_watchpoint--; 1510 break; 1511 1512 default: 1513 return -ENOSYS; 1514 } 1515 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1516 1517 return 0; 1518 } 1519 1520 void kvm_arch_remove_all_hw_breakpoints(void) 1521 { 1522 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1523 } 1524 1525 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1526 { 1527 int n; 1528 1529 /* Software Breakpoint updates */ 1530 if (kvm_sw_breakpoints_active(cs)) { 1531 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1532 } 1533 1534 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1535 <= ARRAY_SIZE(hw_debug_points)); 1536 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1537 1538 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1540 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1541 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1542 switch (hw_debug_points[n].type) { 1543 case GDB_BREAKPOINT_HW: 1544 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1545 break; 1546 case GDB_WATCHPOINT_WRITE: 1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1548 break; 1549 case GDB_WATCHPOINT_READ: 1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1551 break; 1552 case GDB_WATCHPOINT_ACCESS: 1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1554 KVMPPC_DEBUG_WATCH_READ; 1555 break; 1556 default: 1557 cpu_abort(cs, "Unsupported breakpoint type\n"); 1558 } 1559 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1560 } 1561 } 1562 } 1563 1564 static int kvm_handle_hw_breakpoint(CPUState *cs, 1565 struct kvm_debug_exit_arch *arch_info) 1566 { 1567 int handle = DEBUG_RETURN_GUEST; 1568 int n; 1569 int flag = 0; 1570 1571 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1572 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1573 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1574 if (n >= 0) { 1575 handle = DEBUG_RETURN_GDB; 1576 } 1577 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1578 KVMPPC_DEBUG_WATCH_WRITE)) { 1579 n = find_hw_watchpoint(arch_info->address, &flag); 1580 if (n >= 0) { 1581 handle = DEBUG_RETURN_GDB; 1582 cs->watchpoint_hit = &hw_watchpoint; 1583 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1584 hw_watchpoint.flags = flag; 1585 } 1586 } 1587 } 1588 return handle; 1589 } 1590 1591 static int kvm_handle_singlestep(void) 1592 { 1593 return DEBUG_RETURN_GDB; 1594 } 1595 1596 static int kvm_handle_sw_breakpoint(void) 1597 { 1598 return DEBUG_RETURN_GDB; 1599 } 1600 1601 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1602 { 1603 CPUState *cs = CPU(cpu); 1604 CPUPPCState *env = &cpu->env; 1605 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1606 1607 if (cs->singlestep_enabled) { 1608 return kvm_handle_singlestep(); 1609 } 1610 1611 if (arch_info->status) { 1612 return kvm_handle_hw_breakpoint(cs, arch_info); 1613 } 1614 1615 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1616 return kvm_handle_sw_breakpoint(); 1617 } 1618 1619 /* 1620 * QEMU is not able to handle debug exception, so inject 1621 * program exception to guest; 1622 * Yes program exception NOT debug exception !! 1623 * When QEMU is using debug resources then debug exception must 1624 * be always set. To achieve this we set MSR_DE and also set 1625 * MSRP_DEP so guest cannot change MSR_DE. 1626 * When emulating debug resource for guest we want guest 1627 * to control MSR_DE (enable/disable debug interrupt on need). 1628 * Supporting both configurations are NOT possible. 1629 * So the result is that we cannot share debug resources 1630 * between QEMU and Guest on BOOKE architecture. 1631 * In the current design QEMU gets the priority over guest, 1632 * this means that if QEMU is using debug resources then guest 1633 * cannot use them; 1634 * For software breakpoint QEMU uses a privileged instruction; 1635 * So there cannot be any reason that we are here for guest 1636 * set debug exception, only possibility is guest executed a 1637 * privileged / illegal instruction and that's why we are 1638 * injecting a program interrupt. 1639 */ 1640 cpu_synchronize_state(cs); 1641 /* 1642 * env->nip is PC, so increment this by 4 to use 1643 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1644 */ 1645 env->nip += 4; 1646 cs->exception_index = POWERPC_EXCP_PROGRAM; 1647 env->error_code = POWERPC_EXCP_INVAL; 1648 ppc_cpu_do_interrupt(cs); 1649 1650 return DEBUG_RETURN_GUEST; 1651 } 1652 1653 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1654 { 1655 PowerPCCPU *cpu = POWERPC_CPU(cs); 1656 CPUPPCState *env = &cpu->env; 1657 int ret; 1658 1659 qemu_mutex_lock_iothread(); 1660 1661 switch (run->exit_reason) { 1662 case KVM_EXIT_DCR: 1663 if (run->dcr.is_write) { 1664 trace_kvm_handle_dcr_write(); 1665 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1666 } else { 1667 trace_kvm_handle_dcr_read(); 1668 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1669 } 1670 break; 1671 case KVM_EXIT_HLT: 1672 trace_kvm_handle_halt(); 1673 ret = kvmppc_handle_halt(cpu); 1674 break; 1675 #if defined(TARGET_PPC64) 1676 case KVM_EXIT_PAPR_HCALL: 1677 trace_kvm_handle_papr_hcall(run->papr_hcall.nr); 1678 run->papr_hcall.ret = spapr_hypercall(cpu, 1679 run->papr_hcall.nr, 1680 run->papr_hcall.args); 1681 ret = 0; 1682 break; 1683 #endif 1684 case KVM_EXIT_EPR: 1685 trace_kvm_handle_epr(); 1686 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1687 ret = 0; 1688 break; 1689 case KVM_EXIT_WATCHDOG: 1690 trace_kvm_handle_watchdog_expiry(); 1691 watchdog_perform_action(); 1692 ret = 0; 1693 break; 1694 1695 case KVM_EXIT_DEBUG: 1696 trace_kvm_handle_debug_exception(); 1697 if (kvm_handle_debug(cpu, run)) { 1698 ret = EXCP_DEBUG; 1699 break; 1700 } 1701 /* re-enter, this exception was guest-internal */ 1702 ret = 0; 1703 break; 1704 1705 #if defined(TARGET_PPC64) 1706 case KVM_EXIT_NMI: 1707 trace_kvm_handle_nmi_exception(); 1708 ret = kvm_handle_nmi(cpu, run); 1709 break; 1710 #endif 1711 1712 default: 1713 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1714 ret = -1; 1715 break; 1716 } 1717 1718 qemu_mutex_unlock_iothread(); 1719 return ret; 1720 } 1721 1722 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1723 { 1724 CPUState *cs = CPU(cpu); 1725 uint32_t bits = tsr_bits; 1726 struct kvm_one_reg reg = { 1727 .id = KVM_REG_PPC_OR_TSR, 1728 .addr = (uintptr_t) &bits, 1729 }; 1730 1731 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1732 } 1733 1734 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1735 { 1736 1737 CPUState *cs = CPU(cpu); 1738 uint32_t bits = tsr_bits; 1739 struct kvm_one_reg reg = { 1740 .id = KVM_REG_PPC_CLEAR_TSR, 1741 .addr = (uintptr_t) &bits, 1742 }; 1743 1744 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1745 } 1746 1747 int kvmppc_set_tcr(PowerPCCPU *cpu) 1748 { 1749 CPUState *cs = CPU(cpu); 1750 CPUPPCState *env = &cpu->env; 1751 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1752 1753 struct kvm_one_reg reg = { 1754 .id = KVM_REG_PPC_TCR, 1755 .addr = (uintptr_t) &tcr, 1756 }; 1757 1758 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1759 } 1760 1761 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1762 { 1763 CPUState *cs = CPU(cpu); 1764 int ret; 1765 1766 if (!kvm_enabled()) { 1767 return -1; 1768 } 1769 1770 if (!cap_ppc_watchdog) { 1771 printf("warning: KVM does not support watchdog"); 1772 return -1; 1773 } 1774 1775 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1776 if (ret < 0) { 1777 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1778 __func__, strerror(-ret)); 1779 return ret; 1780 } 1781 1782 return ret; 1783 } 1784 1785 static int read_cpuinfo(const char *field, char *value, int len) 1786 { 1787 FILE *f; 1788 int ret = -1; 1789 int field_len = strlen(field); 1790 char line[512]; 1791 1792 f = fopen("/proc/cpuinfo", "r"); 1793 if (!f) { 1794 return -1; 1795 } 1796 1797 do { 1798 if (!fgets(line, sizeof(line), f)) { 1799 break; 1800 } 1801 if (!strncmp(line, field, field_len)) { 1802 pstrcpy(value, len, line); 1803 ret = 0; 1804 break; 1805 } 1806 } while (*line); 1807 1808 fclose(f); 1809 1810 return ret; 1811 } 1812 1813 static uint32_t kvmppc_get_tbfreq_procfs(void) 1814 { 1815 char line[512]; 1816 char *ns; 1817 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND; 1818 uint32_t tbfreq_procfs; 1819 1820 if (read_cpuinfo("timebase", line, sizeof(line))) { 1821 return tbfreq_fallback; 1822 } 1823 1824 ns = strchr(line, ':'); 1825 if (!ns) { 1826 return tbfreq_fallback; 1827 } 1828 1829 tbfreq_procfs = atoi(++ns); 1830 1831 /* 0 is certainly not acceptable by the guest, return fallback value */ 1832 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback; 1833 } 1834 1835 uint32_t kvmppc_get_tbfreq(void) 1836 { 1837 static uint32_t cached_tbfreq; 1838 1839 if (!cached_tbfreq) { 1840 cached_tbfreq = kvmppc_get_tbfreq_procfs(); 1841 } 1842 1843 return cached_tbfreq; 1844 } 1845 1846 bool kvmppc_get_host_serial(char **value) 1847 { 1848 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1849 NULL); 1850 } 1851 1852 bool kvmppc_get_host_model(char **value) 1853 { 1854 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1855 } 1856 1857 /* Try to find a device tree node for a CPU with clock-frequency property */ 1858 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1859 { 1860 struct dirent *dirp; 1861 DIR *dp; 1862 1863 dp = opendir(PROC_DEVTREE_CPU); 1864 if (!dp) { 1865 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1866 return -1; 1867 } 1868 1869 buf[0] = '\0'; 1870 while ((dirp = readdir(dp)) != NULL) { 1871 FILE *f; 1872 1873 /* Don't accidentally read from the current and parent directories */ 1874 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) { 1875 continue; 1876 } 1877 1878 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1879 dirp->d_name); 1880 f = fopen(buf, "r"); 1881 if (f) { 1882 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1883 fclose(f); 1884 break; 1885 } 1886 buf[0] = '\0'; 1887 } 1888 closedir(dp); 1889 if (buf[0] == '\0') { 1890 printf("Unknown host!\n"); 1891 return -1; 1892 } 1893 1894 return 0; 1895 } 1896 1897 static uint64_t kvmppc_read_int_dt(const char *filename) 1898 { 1899 union { 1900 uint32_t v32; 1901 uint64_t v64; 1902 } u; 1903 FILE *f; 1904 int len; 1905 1906 f = fopen(filename, "rb"); 1907 if (!f) { 1908 return -1; 1909 } 1910 1911 len = fread(&u, 1, sizeof(u), f); 1912 fclose(f); 1913 switch (len) { 1914 case 4: 1915 /* property is a 32-bit quantity */ 1916 return be32_to_cpu(u.v32); 1917 case 8: 1918 return be64_to_cpu(u.v64); 1919 } 1920 1921 return 0; 1922 } 1923 1924 /* 1925 * Read a CPU node property from the host device tree that's a single 1926 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1927 * (can't find or open the property, or doesn't understand the format) 1928 */ 1929 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1930 { 1931 char buf[PATH_MAX], *tmp; 1932 uint64_t val; 1933 1934 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1935 return -1; 1936 } 1937 1938 tmp = g_strdup_printf("%s/%s", buf, propname); 1939 val = kvmppc_read_int_dt(tmp); 1940 g_free(tmp); 1941 1942 return val; 1943 } 1944 1945 uint64_t kvmppc_get_clockfreq(void) 1946 { 1947 return kvmppc_read_int_cpu_dt("clock-frequency"); 1948 } 1949 1950 static int kvmppc_get_dec_bits(void) 1951 { 1952 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1953 1954 if (nr_bits > 0) { 1955 return nr_bits; 1956 } 1957 return 0; 1958 } 1959 1960 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1961 { 1962 CPUState *cs = env_cpu(env); 1963 1964 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1965 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1966 return 0; 1967 } 1968 1969 return 1; 1970 } 1971 1972 int kvmppc_get_hasidle(CPUPPCState *env) 1973 { 1974 struct kvm_ppc_pvinfo pvinfo; 1975 1976 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1977 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1978 return 1; 1979 } 1980 1981 return 0; 1982 } 1983 1984 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 1985 { 1986 uint32_t *hc = (uint32_t *)buf; 1987 struct kvm_ppc_pvinfo pvinfo; 1988 1989 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 1990 memcpy(buf, pvinfo.hcall, buf_len); 1991 return 0; 1992 } 1993 1994 /* 1995 * Fallback to always fail hypercalls regardless of endianness: 1996 * 1997 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 1998 * li r3, -1 1999 * b .+8 (becomes nop in wrong endian) 2000 * bswap32(li r3, -1) 2001 */ 2002 2003 hc[0] = cpu_to_be32(0x08000048); 2004 hc[1] = cpu_to_be32(0x3860ffff); 2005 hc[2] = cpu_to_be32(0x48000008); 2006 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2007 2008 return 1; 2009 } 2010 2011 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2012 { 2013 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2014 } 2015 2016 void kvmppc_enable_logical_ci_hcalls(void) 2017 { 2018 /* 2019 * FIXME: it would be nice if we could detect the cases where 2020 * we're using a device which requires the in kernel 2021 * implementation of these hcalls, but the kernel lacks them and 2022 * produce a warning. 2023 */ 2024 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2025 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2026 } 2027 2028 void kvmppc_enable_set_mode_hcall(void) 2029 { 2030 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2031 } 2032 2033 void kvmppc_enable_clear_ref_mod_hcalls(void) 2034 { 2035 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2036 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2037 } 2038 2039 void kvmppc_enable_h_page_init(void) 2040 { 2041 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2042 } 2043 2044 void kvmppc_enable_h_rpt_invalidate(void) 2045 { 2046 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE); 2047 } 2048 2049 void kvmppc_set_papr(PowerPCCPU *cpu) 2050 { 2051 CPUState *cs = CPU(cpu); 2052 int ret; 2053 2054 if (!kvm_enabled()) { 2055 return; 2056 } 2057 2058 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2059 if (ret) { 2060 error_report("This vCPU type or KVM version does not support PAPR"); 2061 exit(1); 2062 } 2063 2064 /* 2065 * Update the capability flag so we sync the right information 2066 * with kvm 2067 */ 2068 cap_papr = 1; 2069 } 2070 2071 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2072 { 2073 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2074 } 2075 2076 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2077 { 2078 CPUState *cs = CPU(cpu); 2079 int ret; 2080 2081 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2082 if (ret && mpic_proxy) { 2083 error_report("This KVM version does not support EPR"); 2084 exit(1); 2085 } 2086 } 2087 2088 bool kvmppc_get_fwnmi(void) 2089 { 2090 return cap_fwnmi; 2091 } 2092 2093 int kvmppc_set_fwnmi(PowerPCCPU *cpu) 2094 { 2095 CPUState *cs = CPU(cpu); 2096 2097 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); 2098 } 2099 2100 int kvmppc_smt_threads(void) 2101 { 2102 return cap_ppc_smt ? cap_ppc_smt : 1; 2103 } 2104 2105 int kvmppc_set_smt_threads(int smt) 2106 { 2107 int ret; 2108 2109 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2110 if (!ret) { 2111 cap_ppc_smt = smt; 2112 } 2113 return ret; 2114 } 2115 2116 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2117 { 2118 int i; 2119 GString *g; 2120 char *s; 2121 2122 assert(kvm_enabled()); 2123 if (cap_ppc_smt_possible) { 2124 g = g_string_new("Available VSMT modes:"); 2125 for (i = 63; i >= 0; i--) { 2126 if ((1UL << i) & cap_ppc_smt_possible) { 2127 g_string_append_printf(g, " %lu", (1UL << i)); 2128 } 2129 } 2130 s = g_string_free(g, false); 2131 error_append_hint(errp, "%s.\n", s); 2132 g_free(s); 2133 } else { 2134 error_append_hint(errp, 2135 "This KVM seems to be too old to support VSMT.\n"); 2136 } 2137 } 2138 2139 2140 #ifdef TARGET_PPC64 2141 uint64_t kvmppc_vrma_limit(unsigned int hash_shift) 2142 { 2143 struct kvm_ppc_smmu_info info; 2144 long rampagesize, best_page_shift; 2145 int i; 2146 2147 /* 2148 * Find the largest hardware supported page size that's less than 2149 * or equal to the (logical) backing page size of guest RAM 2150 */ 2151 kvm_get_smmu_info(&info, &error_fatal); 2152 rampagesize = qemu_minrampagesize(); 2153 best_page_shift = 0; 2154 2155 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2156 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2157 2158 if (!sps->page_shift) { 2159 continue; 2160 } 2161 2162 if ((sps->page_shift > best_page_shift) 2163 && ((1UL << sps->page_shift) <= rampagesize)) { 2164 best_page_shift = sps->page_shift; 2165 } 2166 } 2167 2168 return 1ULL << (best_page_shift + hash_shift - 7); 2169 } 2170 #endif 2171 2172 bool kvmppc_spapr_use_multitce(void) 2173 { 2174 return cap_spapr_multitce; 2175 } 2176 2177 int kvmppc_spapr_enable_inkernel_multitce(void) 2178 { 2179 int ret; 2180 2181 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2182 H_PUT_TCE_INDIRECT, 1); 2183 if (!ret) { 2184 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2185 H_STUFF_TCE, 1); 2186 } 2187 2188 return ret; 2189 } 2190 2191 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2192 uint64_t bus_offset, uint32_t nb_table, 2193 int *pfd, bool need_vfio) 2194 { 2195 long len; 2196 int fd; 2197 void *table; 2198 2199 /* 2200 * Must set fd to -1 so we don't try to munmap when called for 2201 * destroying the table, which the upper layers -will- do 2202 */ 2203 *pfd = -1; 2204 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2205 return NULL; 2206 } 2207 2208 if (cap_spapr_tce_64) { 2209 struct kvm_create_spapr_tce_64 args = { 2210 .liobn = liobn, 2211 .page_shift = page_shift, 2212 .offset = bus_offset >> page_shift, 2213 .size = nb_table, 2214 .flags = 0 2215 }; 2216 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2217 if (fd < 0) { 2218 fprintf(stderr, 2219 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2220 liobn); 2221 return NULL; 2222 } 2223 } else if (cap_spapr_tce) { 2224 uint64_t window_size = (uint64_t) nb_table << page_shift; 2225 struct kvm_create_spapr_tce args = { 2226 .liobn = liobn, 2227 .window_size = window_size, 2228 }; 2229 if ((window_size != args.window_size) || bus_offset) { 2230 return NULL; 2231 } 2232 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2233 if (fd < 0) { 2234 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2235 liobn); 2236 return NULL; 2237 } 2238 } else { 2239 return NULL; 2240 } 2241 2242 len = nb_table * sizeof(uint64_t); 2243 /* FIXME: round this up to page size */ 2244 2245 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2246 if (table == MAP_FAILED) { 2247 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2248 liobn); 2249 close(fd); 2250 return NULL; 2251 } 2252 2253 *pfd = fd; 2254 return table; 2255 } 2256 2257 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2258 { 2259 long len; 2260 2261 if (fd < 0) { 2262 return -1; 2263 } 2264 2265 len = nb_table * sizeof(uint64_t); 2266 if ((munmap(table, len) < 0) || 2267 (close(fd) < 0)) { 2268 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2269 strerror(errno)); 2270 /* Leak the table */ 2271 } 2272 2273 return 0; 2274 } 2275 2276 int kvmppc_reset_htab(int shift_hint) 2277 { 2278 uint32_t shift = shift_hint; 2279 2280 if (!kvm_enabled()) { 2281 /* Full emulation, tell caller to allocate htab itself */ 2282 return 0; 2283 } 2284 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2285 int ret; 2286 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2287 if (ret == -ENOTTY) { 2288 /* 2289 * At least some versions of PR KVM advertise the 2290 * capability, but don't implement the ioctl(). Oops. 2291 * Return 0 so that we allocate the htab in qemu, as is 2292 * correct for PR. 2293 */ 2294 return 0; 2295 } else if (ret < 0) { 2296 return ret; 2297 } 2298 return shift; 2299 } 2300 2301 /* 2302 * We have a kernel that predates the htab reset calls. For PR 2303 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2304 * this era, it has allocated a 16MB fixed size hash table 2305 * already. 2306 */ 2307 if (kvmppc_is_pr(kvm_state)) { 2308 /* PR - tell caller to allocate htab */ 2309 return 0; 2310 } else { 2311 /* HV - assume 16MB kernel allocated htab */ 2312 return 24; 2313 } 2314 } 2315 2316 static inline uint32_t mfpvr(void) 2317 { 2318 uint32_t pvr; 2319 2320 asm ("mfpvr %0" 2321 : "=r"(pvr)); 2322 return pvr; 2323 } 2324 2325 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2326 { 2327 if (on) { 2328 *word |= flags; 2329 } else { 2330 *word &= ~flags; 2331 } 2332 } 2333 2334 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2335 { 2336 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2337 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2338 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2339 2340 /* Now fix up the class with information we can query from the host */ 2341 pcc->pvr = mfpvr(); 2342 2343 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2344 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2345 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2346 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2347 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2348 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2349 2350 if (dcache_size != -1) { 2351 pcc->l1_dcache_size = dcache_size; 2352 } 2353 2354 if (icache_size != -1) { 2355 pcc->l1_icache_size = icache_size; 2356 } 2357 2358 #if defined(TARGET_PPC64) 2359 pcc->radix_page_info = kvm_get_radix_page_info(); 2360 2361 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2362 /* 2363 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2364 * compliant. More importantly, advertising ISA 3.00 2365 * architected mode may prevent guests from activating 2366 * necessary DD1 workarounds. 2367 */ 2368 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2369 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2370 } 2371 #endif /* defined(TARGET_PPC64) */ 2372 } 2373 2374 bool kvmppc_has_cap_epr(void) 2375 { 2376 return cap_epr; 2377 } 2378 2379 bool kvmppc_has_cap_fixup_hcalls(void) 2380 { 2381 return cap_fixup_hcalls; 2382 } 2383 2384 bool kvmppc_has_cap_htm(void) 2385 { 2386 return cap_htm; 2387 } 2388 2389 bool kvmppc_has_cap_mmu_radix(void) 2390 { 2391 return cap_mmu_radix; 2392 } 2393 2394 bool kvmppc_has_cap_mmu_hash_v3(void) 2395 { 2396 return cap_mmu_hash_v3; 2397 } 2398 2399 static bool kvmppc_power8_host(void) 2400 { 2401 bool ret = false; 2402 #ifdef TARGET_PPC64 2403 { 2404 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2405 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2406 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2407 (base_pvr == CPU_POWERPC_POWER8_BASE); 2408 } 2409 #endif /* TARGET_PPC64 */ 2410 return ret; 2411 } 2412 2413 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2414 { 2415 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2416 2417 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2418 return 2; 2419 } else if ((!l1d_thread_priv_req || 2420 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2421 (c.character & c.character_mask 2422 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2423 return 1; 2424 } 2425 2426 return 0; 2427 } 2428 2429 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2430 { 2431 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2432 return 2; 2433 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2434 return 1; 2435 } 2436 2437 return 0; 2438 } 2439 2440 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2441 { 2442 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2443 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2444 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2445 return SPAPR_CAP_FIXED_NA; 2446 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2447 return SPAPR_CAP_WORKAROUND; 2448 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2449 return SPAPR_CAP_FIXED_CCD; 2450 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2451 return SPAPR_CAP_FIXED_IBS; 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2458 { 2459 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2460 return 1; 2461 } 2462 return 0; 2463 } 2464 2465 bool kvmppc_has_cap_xive(void) 2466 { 2467 return cap_xive; 2468 } 2469 2470 static void kvmppc_get_cpu_characteristics(KVMState *s) 2471 { 2472 struct kvm_ppc_cpu_char c; 2473 int ret; 2474 2475 /* Assume broken */ 2476 cap_ppc_safe_cache = 0; 2477 cap_ppc_safe_bounds_check = 0; 2478 cap_ppc_safe_indirect_branch = 0; 2479 2480 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2481 if (!ret) { 2482 return; 2483 } 2484 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2485 if (ret < 0) { 2486 return; 2487 } 2488 2489 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2490 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2491 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2492 cap_ppc_count_cache_flush_assist = 2493 parse_cap_ppc_count_cache_flush_assist(c); 2494 } 2495 2496 int kvmppc_get_cap_safe_cache(void) 2497 { 2498 return cap_ppc_safe_cache; 2499 } 2500 2501 int kvmppc_get_cap_safe_bounds_check(void) 2502 { 2503 return cap_ppc_safe_bounds_check; 2504 } 2505 2506 int kvmppc_get_cap_safe_indirect_branch(void) 2507 { 2508 return cap_ppc_safe_indirect_branch; 2509 } 2510 2511 int kvmppc_get_cap_count_cache_flush_assist(void) 2512 { 2513 return cap_ppc_count_cache_flush_assist; 2514 } 2515 2516 bool kvmppc_has_cap_nested_kvm_hv(void) 2517 { 2518 return !!cap_ppc_nested_kvm_hv; 2519 } 2520 2521 int kvmppc_set_cap_nested_kvm_hv(int enable) 2522 { 2523 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2524 } 2525 2526 bool kvmppc_has_cap_spapr_vfio(void) 2527 { 2528 return cap_spapr_vfio; 2529 } 2530 2531 int kvmppc_get_cap_large_decr(void) 2532 { 2533 return cap_large_decr; 2534 } 2535 2536 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2537 { 2538 CPUState *cs = CPU(cpu); 2539 uint64_t lpcr = 0; 2540 2541 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2542 /* Do we need to modify the LPCR? */ 2543 if (!!(lpcr & LPCR_LD) != !!enable) { 2544 if (enable) { 2545 lpcr |= LPCR_LD; 2546 } else { 2547 lpcr &= ~LPCR_LD; 2548 } 2549 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2550 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2551 2552 if (!!(lpcr & LPCR_LD) != !!enable) { 2553 return -1; 2554 } 2555 } 2556 2557 return 0; 2558 } 2559 2560 int kvmppc_has_cap_rpt_invalidate(void) 2561 { 2562 return cap_rpt_invalidate; 2563 } 2564 2565 bool kvmppc_supports_ail_3(void) 2566 { 2567 return cap_ail_mode_3; 2568 } 2569 2570 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2571 { 2572 uint32_t host_pvr = mfpvr(); 2573 PowerPCCPUClass *pvr_pcc; 2574 2575 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2576 if (pvr_pcc == NULL) { 2577 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2578 } 2579 2580 return pvr_pcc; 2581 } 2582 2583 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2584 { 2585 MachineClass *mc = MACHINE_CLASS(oc); 2586 2587 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2588 } 2589 2590 static int kvm_ppc_register_host_cpu_type(void) 2591 { 2592 TypeInfo type_info = { 2593 .name = TYPE_HOST_POWERPC_CPU, 2594 .class_init = kvmppc_host_cpu_class_init, 2595 }; 2596 PowerPCCPUClass *pvr_pcc; 2597 ObjectClass *oc; 2598 DeviceClass *dc; 2599 int i; 2600 2601 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2602 if (pvr_pcc == NULL) { 2603 return -1; 2604 } 2605 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2606 type_register(&type_info); 2607 /* override TCG default cpu type with 'host' cpu model */ 2608 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2609 false, NULL); 2610 2611 oc = object_class_by_name(type_info.name); 2612 g_assert(oc); 2613 2614 /* 2615 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2616 * we want "POWER8" to be a "family" alias that points to the current 2617 * host CPU type, too) 2618 */ 2619 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2620 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2621 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2622 char *suffix; 2623 2624 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2625 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2626 if (suffix) { 2627 *suffix = 0; 2628 } 2629 break; 2630 } 2631 } 2632 2633 return 0; 2634 } 2635 2636 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2637 { 2638 struct kvm_rtas_token_args args = { 2639 .token = token, 2640 }; 2641 2642 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2643 return -ENOENT; 2644 } 2645 2646 strncpy(args.name, function, sizeof(args.name) - 1); 2647 2648 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2649 } 2650 2651 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2652 { 2653 struct kvm_get_htab_fd s = { 2654 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2655 .start_index = index, 2656 }; 2657 int ret; 2658 2659 if (!cap_htab_fd) { 2660 error_setg(errp, "KVM version doesn't support %s the HPT", 2661 write ? "writing" : "reading"); 2662 return -ENOTSUP; 2663 } 2664 2665 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2666 if (ret < 0) { 2667 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2668 write ? "writing" : "reading", write ? "to" : "from", 2669 strerror(errno)); 2670 return -errno; 2671 } 2672 2673 return ret; 2674 } 2675 2676 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2677 { 2678 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2679 uint8_t buf[bufsize]; 2680 ssize_t rc; 2681 2682 do { 2683 rc = read(fd, buf, bufsize); 2684 if (rc < 0) { 2685 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2686 strerror(errno)); 2687 return rc; 2688 } else if (rc) { 2689 uint8_t *buffer = buf; 2690 ssize_t n = rc; 2691 while (n) { 2692 struct kvm_get_htab_header *head = 2693 (struct kvm_get_htab_header *) buffer; 2694 size_t chunksize = sizeof(*head) + 2695 HASH_PTE_SIZE_64 * head->n_valid; 2696 2697 qemu_put_be32(f, head->index); 2698 qemu_put_be16(f, head->n_valid); 2699 qemu_put_be16(f, head->n_invalid); 2700 qemu_put_buffer(f, (void *)(head + 1), 2701 HASH_PTE_SIZE_64 * head->n_valid); 2702 2703 buffer += chunksize; 2704 n -= chunksize; 2705 } 2706 } 2707 } while ((rc != 0) 2708 && ((max_ns < 0) || 2709 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2710 2711 return (rc == 0) ? 1 : 0; 2712 } 2713 2714 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2715 uint16_t n_valid, uint16_t n_invalid, Error **errp) 2716 { 2717 struct kvm_get_htab_header *buf; 2718 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2719 ssize_t rc; 2720 2721 buf = alloca(chunksize); 2722 buf->index = index; 2723 buf->n_valid = n_valid; 2724 buf->n_invalid = n_invalid; 2725 2726 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2727 2728 rc = write(fd, buf, chunksize); 2729 if (rc < 0) { 2730 error_setg_errno(errp, errno, "Error writing the KVM hash table"); 2731 return -errno; 2732 } 2733 if (rc != chunksize) { 2734 /* We should never get a short write on a single chunk */ 2735 error_setg(errp, "Short write while restoring the KVM hash table"); 2736 return -ENOSPC; 2737 } 2738 return 0; 2739 } 2740 2741 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2742 { 2743 return true; 2744 } 2745 2746 void kvm_arch_init_irq_routing(KVMState *s) 2747 { 2748 } 2749 2750 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2751 { 2752 int fd, rc; 2753 int i; 2754 2755 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2756 2757 i = 0; 2758 while (i < n) { 2759 struct kvm_get_htab_header *hdr; 2760 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2761 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2762 2763 rc = read(fd, buf, sizeof(buf)); 2764 if (rc < 0) { 2765 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2766 } 2767 2768 hdr = (struct kvm_get_htab_header *)buf; 2769 while ((i < n) && ((char *)hdr < (buf + rc))) { 2770 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2771 2772 if (hdr->index != (ptex + i)) { 2773 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2774 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2775 } 2776 2777 if (n - i < valid) { 2778 valid = n - i; 2779 } 2780 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2781 i += valid; 2782 2783 if ((n - i) < invalid) { 2784 invalid = n - i; 2785 } 2786 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2787 i += invalid; 2788 2789 hdr = (struct kvm_get_htab_header *) 2790 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2791 } 2792 } 2793 2794 close(fd); 2795 } 2796 2797 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2798 { 2799 int fd, rc; 2800 struct { 2801 struct kvm_get_htab_header hdr; 2802 uint64_t pte0; 2803 uint64_t pte1; 2804 } buf; 2805 2806 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2807 2808 buf.hdr.n_valid = 1; 2809 buf.hdr.n_invalid = 0; 2810 buf.hdr.index = ptex; 2811 buf.pte0 = cpu_to_be64(pte0); 2812 buf.pte1 = cpu_to_be64(pte1); 2813 2814 rc = write(fd, &buf, sizeof(buf)); 2815 if (rc != sizeof(buf)) { 2816 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2817 } 2818 close(fd); 2819 } 2820 2821 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2822 uint64_t address, uint32_t data, PCIDevice *dev) 2823 { 2824 return 0; 2825 } 2826 2827 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2828 int vector, PCIDevice *dev) 2829 { 2830 return 0; 2831 } 2832 2833 int kvm_arch_release_virq_post(int virq) 2834 { 2835 return 0; 2836 } 2837 2838 int kvm_arch_msi_data_to_gsi(uint32_t data) 2839 { 2840 return data & 0xffff; 2841 } 2842 2843 #if defined(TARGET_PPC64) 2844 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) 2845 { 2846 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK; 2847 2848 cpu_synchronize_state(CPU(cpu)); 2849 2850 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV); 2851 2852 return 0; 2853 } 2854 #endif 2855 2856 int kvmppc_enable_hwrng(void) 2857 { 2858 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2859 return -1; 2860 } 2861 2862 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2863 } 2864 2865 void kvmppc_check_papr_resize_hpt(Error **errp) 2866 { 2867 if (!kvm_enabled()) { 2868 return; /* No KVM, we're good */ 2869 } 2870 2871 if (cap_resize_hpt) { 2872 return; /* Kernel has explicit support, we're good */ 2873 } 2874 2875 /* Otherwise fallback on looking for PR KVM */ 2876 if (kvmppc_is_pr(kvm_state)) { 2877 return; 2878 } 2879 2880 error_setg(errp, 2881 "Hash page table resizing not available with this KVM version"); 2882 } 2883 2884 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2885 { 2886 CPUState *cs = CPU(cpu); 2887 struct kvm_ppc_resize_hpt rhpt = { 2888 .flags = flags, 2889 .shift = shift, 2890 }; 2891 2892 if (!cap_resize_hpt) { 2893 return -ENOSYS; 2894 } 2895 2896 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2897 } 2898 2899 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2900 { 2901 CPUState *cs = CPU(cpu); 2902 struct kvm_ppc_resize_hpt rhpt = { 2903 .flags = flags, 2904 .shift = shift, 2905 }; 2906 2907 if (!cap_resize_hpt) { 2908 return -ENOSYS; 2909 } 2910 2911 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2912 } 2913 2914 /* 2915 * This is a helper function to detect a post migration scenario 2916 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2917 * the guest kernel can't handle a PVR value other than the actual host 2918 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2919 * 2920 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2921 * (so, we're HV), return true. The workaround itself is done in 2922 * cpu_post_load. 2923 * 2924 * The order here is important: we'll only check for KVM PR as a 2925 * fallback if the guest kernel can't handle the situation itself. 2926 * We need to avoid as much as possible querying the running KVM type 2927 * in QEMU level. 2928 */ 2929 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2930 { 2931 CPUState *cs = CPU(cpu); 2932 2933 if (!kvm_enabled()) { 2934 return false; 2935 } 2936 2937 if (cap_ppc_pvr_compat) { 2938 return false; 2939 } 2940 2941 return !kvmppc_is_pr(cs->kvm_state); 2942 } 2943 2944 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2945 { 2946 CPUState *cs = CPU(cpu); 2947 2948 if (kvm_enabled()) { 2949 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2950 } 2951 } 2952 2953 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2954 { 2955 CPUState *cs = CPU(cpu); 2956 2957 if (kvm_enabled()) { 2958 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2959 } 2960 } 2961 2962 bool kvm_arch_cpu_check_are_resettable(void) 2963 { 2964 return true; 2965 } 2966 2967 void kvm_arch_accel_class_init(ObjectClass *oc) 2968 { 2969 } 2970