1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu-common.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "cpu.h" 28 #include "cpu-models.h" 29 #include "qemu/timer.h" 30 #include "sysemu/hw_accel.h" 31 #include "kvm_ppc.h" 32 #include "sysemu/cpus.h" 33 #include "sysemu/device_tree.h" 34 #include "mmu-hash64.h" 35 36 #include "hw/sysbus.h" 37 #include "hw/ppc/spapr.h" 38 #include "hw/ppc/spapr_cpu_core.h" 39 #include "hw/hw.h" 40 #include "hw/ppc/ppc.h" 41 #include "migration/qemu-file-types.h" 42 #include "sysemu/watchdog.h" 43 #include "trace.h" 44 #include "exec/gdbstub.h" 45 #include "exec/memattrs.h" 46 #include "exec/ram_addr.h" 47 #include "sysemu/hostmem.h" 48 #include "qemu/cutils.h" 49 #include "qemu/main-loop.h" 50 #include "qemu/mmap-alloc.h" 51 #include "elf.h" 52 #include "sysemu/kvm_int.h" 53 54 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 55 56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 57 KVM_CAP_LAST_INFO 58 }; 59 60 static int cap_interrupt_unset; 61 static int cap_segstate; 62 static int cap_booke_sregs; 63 static int cap_ppc_smt; 64 static int cap_ppc_smt_possible; 65 static int cap_spapr_tce; 66 static int cap_spapr_tce_64; 67 static int cap_spapr_multitce; 68 static int cap_spapr_vfio; 69 static int cap_hior; 70 static int cap_one_reg; 71 static int cap_epr; 72 static int cap_ppc_watchdog; 73 static int cap_papr; 74 static int cap_htab_fd; 75 static int cap_fixup_hcalls; 76 static int cap_htm; /* Hardware transactional memory support */ 77 static int cap_mmu_radix; 78 static int cap_mmu_hash_v3; 79 static int cap_xive; 80 static int cap_resize_hpt; 81 static int cap_ppc_pvr_compat; 82 static int cap_ppc_safe_cache; 83 static int cap_ppc_safe_bounds_check; 84 static int cap_ppc_safe_indirect_branch; 85 static int cap_ppc_count_cache_flush_assist; 86 static int cap_ppc_nested_kvm_hv; 87 static int cap_large_decr; 88 89 static uint32_t debug_inst_opcode; 90 91 /* 92 * Check whether we are running with KVM-PR (instead of KVM-HV). This 93 * should only be used for fallback tests - generally we should use 94 * explicit capabilities for the features we want, rather than 95 * assuming what is/isn't available depending on the KVM variant. 96 */ 97 static bool kvmppc_is_pr(KVMState *ks) 98 { 99 /* Assume KVM-PR if the GET_PVINFO capability is available */ 100 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 101 } 102 103 static int kvm_ppc_register_host_cpu_type(void); 104 static void kvmppc_get_cpu_characteristics(KVMState *s); 105 static int kvmppc_get_dec_bits(void); 106 107 int kvm_arch_init(MachineState *ms, KVMState *s) 108 { 109 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 110 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 111 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 112 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 113 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 114 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 115 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 116 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 117 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 118 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 119 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 120 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 121 /* 122 * Note: we don't set cap_papr here, because this capability is 123 * only activated after this by kvmppc_set_papr() 124 */ 125 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 126 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 127 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 128 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 129 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 130 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 131 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 132 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 133 kvmppc_get_cpu_characteristics(s); 134 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 135 cap_large_decr = kvmppc_get_dec_bits(); 136 /* 137 * Note: setting it to false because there is not such capability 138 * in KVM at this moment. 139 * 140 * TODO: call kvm_vm_check_extension() with the right capability 141 * after the kernel starts implementing it. 142 */ 143 cap_ppc_pvr_compat = false; 144 145 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 146 error_report("KVM: Host kernel doesn't have level irq capability"); 147 exit(1); 148 } 149 150 kvm_ppc_register_host_cpu_type(); 151 152 return 0; 153 } 154 155 int kvm_arch_irqchip_create(KVMState *s) 156 { 157 return 0; 158 } 159 160 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 161 { 162 CPUPPCState *cenv = &cpu->env; 163 CPUState *cs = CPU(cpu); 164 struct kvm_sregs sregs; 165 int ret; 166 167 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 168 /* 169 * What we're really trying to say is "if we're on BookE, we 170 * use the native PVR for now". This is the only sane way to 171 * check it though, so we potentially confuse users that they 172 * can run BookE guests on BookS. Let's hope nobody dares 173 * enough :) 174 */ 175 return 0; 176 } else { 177 if (!cap_segstate) { 178 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 179 return -ENOSYS; 180 } 181 } 182 183 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 184 if (ret) { 185 return ret; 186 } 187 188 sregs.pvr = cenv->spr[SPR_PVR]; 189 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 190 } 191 192 /* Set up a shared TLB array with KVM */ 193 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 194 { 195 CPUPPCState *env = &cpu->env; 196 CPUState *cs = CPU(cpu); 197 struct kvm_book3e_206_tlb_params params = {}; 198 struct kvm_config_tlb cfg = {}; 199 unsigned int entries = 0; 200 int ret, i; 201 202 if (!kvm_enabled() || 203 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 204 return 0; 205 } 206 207 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 208 209 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 210 params.tlb_sizes[i] = booke206_tlb_size(env, i); 211 params.tlb_ways[i] = booke206_tlb_ways(env, i); 212 entries += params.tlb_sizes[i]; 213 } 214 215 assert(entries == env->nb_tlb); 216 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 217 218 env->tlb_dirty = true; 219 220 cfg.array = (uintptr_t)env->tlb.tlbm; 221 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 222 cfg.params = (uintptr_t)¶ms; 223 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 224 225 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 226 if (ret < 0) { 227 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 228 __func__, strerror(-ret)); 229 return ret; 230 } 231 232 env->kvm_sw_tlb = true; 233 return 0; 234 } 235 236 237 #if defined(TARGET_PPC64) 238 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 239 { 240 int ret; 241 242 assert(kvm_state != NULL); 243 244 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 245 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 246 error_append_hint(errp, "Consider switching to a newer KVM\n"); 247 return; 248 } 249 250 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 251 if (ret == 0) { 252 return; 253 } 254 255 error_setg_errno(errp, -ret, 256 "KVM failed to provide the MMU features it supports"); 257 } 258 259 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 260 { 261 KVMState *s = KVM_STATE(current_machine->accelerator); 262 struct ppc_radix_page_info *radix_page_info; 263 struct kvm_ppc_rmmu_info rmmu_info; 264 int i; 265 266 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 267 return NULL; 268 } 269 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 270 return NULL; 271 } 272 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 273 radix_page_info->count = 0; 274 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 275 if (rmmu_info.ap_encodings[i]) { 276 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 277 radix_page_info->count++; 278 } 279 } 280 return radix_page_info; 281 } 282 283 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 284 bool radix, bool gtse, 285 uint64_t proc_tbl) 286 { 287 CPUState *cs = CPU(cpu); 288 int ret; 289 uint64_t flags = 0; 290 struct kvm_ppc_mmuv3_cfg cfg = { 291 .process_table = proc_tbl, 292 }; 293 294 if (radix) { 295 flags |= KVM_PPC_MMUV3_RADIX; 296 } 297 if (gtse) { 298 flags |= KVM_PPC_MMUV3_GTSE; 299 } 300 cfg.flags = flags; 301 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 302 switch (ret) { 303 case 0: 304 return H_SUCCESS; 305 case -EINVAL: 306 return H_PARAMETER; 307 case -ENODEV: 308 return H_NOT_AVAILABLE; 309 default: 310 return H_HARDWARE; 311 } 312 } 313 314 bool kvmppc_hpt_needs_host_contiguous_pages(void) 315 { 316 static struct kvm_ppc_smmu_info smmu_info; 317 318 if (!kvm_enabled()) { 319 return false; 320 } 321 322 kvm_get_smmu_info(&smmu_info, &error_fatal); 323 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 324 } 325 326 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 327 { 328 struct kvm_ppc_smmu_info smmu_info; 329 int iq, ik, jq, jk; 330 Error *local_err = NULL; 331 332 /* For now, we only have anything to check on hash64 MMUs */ 333 if (!cpu->hash64_opts || !kvm_enabled()) { 334 return; 335 } 336 337 kvm_get_smmu_info(&smmu_info, &local_err); 338 if (local_err) { 339 error_propagate(errp, local_err); 340 return; 341 } 342 343 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 344 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 345 error_setg(errp, 346 "KVM does not support 1TiB segments which guest expects"); 347 return; 348 } 349 350 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 351 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 352 smmu_info.slb_size, cpu->hash64_opts->slb_size); 353 return; 354 } 355 356 /* 357 * Verify that every pagesize supported by the cpu model is 358 * supported by KVM with the same encodings 359 */ 360 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 361 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 362 struct kvm_ppc_one_seg_page_size *ksps; 363 364 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 365 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 366 break; 367 } 368 } 369 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 370 error_setg(errp, "KVM doesn't support for base page shift %u", 371 qsps->page_shift); 372 return; 373 } 374 375 ksps = &smmu_info.sps[ik]; 376 if (ksps->slb_enc != qsps->slb_enc) { 377 error_setg(errp, 378 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 379 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 380 return; 381 } 382 383 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 384 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 385 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 386 break; 387 } 388 } 389 390 if (jk >= ARRAY_SIZE(ksps->enc)) { 391 error_setg(errp, "KVM doesn't support page shift %u/%u", 392 qsps->enc[jq].page_shift, qsps->page_shift); 393 return; 394 } 395 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 396 error_setg(errp, 397 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 398 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 399 qsps->page_shift, qsps->enc[jq].pte_enc); 400 return; 401 } 402 } 403 } 404 405 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 406 /* 407 * Mostly what guest pagesizes we can use are related to the 408 * host pages used to map guest RAM, which is handled in the 409 * platform code. Cache-Inhibited largepages (64k) however are 410 * used for I/O, so if they're mapped to the host at all it 411 * will be a normal mapping, not a special hugepage one used 412 * for RAM. 413 */ 414 if (qemu_real_host_page_size < 0x10000) { 415 error_setg(errp, 416 "KVM can't supply 64kiB CI pages, which guest expects"); 417 } 418 } 419 } 420 #endif /* !defined (TARGET_PPC64) */ 421 422 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 423 { 424 return POWERPC_CPU(cpu)->vcpu_id; 425 } 426 427 /* 428 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 429 * only 1 watchpoint, so array size of 4 is sufficient for now. 430 */ 431 #define MAX_HW_BKPTS 4 432 433 static struct HWBreakpoint { 434 target_ulong addr; 435 int type; 436 } hw_debug_points[MAX_HW_BKPTS]; 437 438 static CPUWatchpoint hw_watchpoint; 439 440 /* Default there is no breakpoint and watchpoint supported */ 441 static int max_hw_breakpoint; 442 static int max_hw_watchpoint; 443 static int nb_hw_breakpoint; 444 static int nb_hw_watchpoint; 445 446 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 447 { 448 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 449 max_hw_breakpoint = 2; 450 max_hw_watchpoint = 2; 451 } 452 453 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 454 fprintf(stderr, "Error initializing h/w breakpoints\n"); 455 return; 456 } 457 } 458 459 int kvm_arch_init_vcpu(CPUState *cs) 460 { 461 PowerPCCPU *cpu = POWERPC_CPU(cs); 462 CPUPPCState *cenv = &cpu->env; 463 int ret; 464 465 /* Synchronize sregs with kvm */ 466 ret = kvm_arch_sync_sregs(cpu); 467 if (ret) { 468 if (ret == -EINVAL) { 469 error_report("Register sync failed... If you're using kvm-hv.ko," 470 " only \"-cpu host\" is possible"); 471 } 472 return ret; 473 } 474 475 switch (cenv->mmu_model) { 476 case POWERPC_MMU_BOOKE206: 477 /* This target supports access to KVM's guest TLB */ 478 ret = kvm_booke206_tlb_init(cpu); 479 break; 480 case POWERPC_MMU_2_07: 481 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 482 /* 483 * KVM-HV has transactional memory on POWER8 also without 484 * the KVM_CAP_PPC_HTM extension, so enable it here 485 * instead as long as it's availble to userspace on the 486 * host. 487 */ 488 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 489 cap_htm = true; 490 } 491 } 492 break; 493 default: 494 break; 495 } 496 497 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 498 kvmppc_hw_debug_points_init(cenv); 499 500 return ret; 501 } 502 503 int kvm_arch_destroy_vcpu(CPUState *cs) 504 { 505 return 0; 506 } 507 508 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 509 { 510 CPUPPCState *env = &cpu->env; 511 CPUState *cs = CPU(cpu); 512 struct kvm_dirty_tlb dirty_tlb; 513 unsigned char *bitmap; 514 int ret; 515 516 if (!env->kvm_sw_tlb) { 517 return; 518 } 519 520 bitmap = g_malloc((env->nb_tlb + 7) / 8); 521 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 522 523 dirty_tlb.bitmap = (uintptr_t)bitmap; 524 dirty_tlb.num_dirty = env->nb_tlb; 525 526 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 527 if (ret) { 528 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 529 __func__, strerror(-ret)); 530 } 531 532 g_free(bitmap); 533 } 534 535 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 536 { 537 PowerPCCPU *cpu = POWERPC_CPU(cs); 538 CPUPPCState *env = &cpu->env; 539 union { 540 uint32_t u32; 541 uint64_t u64; 542 } val; 543 struct kvm_one_reg reg = { 544 .id = id, 545 .addr = (uintptr_t) &val, 546 }; 547 int ret; 548 549 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 550 if (ret != 0) { 551 trace_kvm_failed_spr_get(spr, strerror(errno)); 552 } else { 553 switch (id & KVM_REG_SIZE_MASK) { 554 case KVM_REG_SIZE_U32: 555 env->spr[spr] = val.u32; 556 break; 557 558 case KVM_REG_SIZE_U64: 559 env->spr[spr] = val.u64; 560 break; 561 562 default: 563 /* Don't handle this size yet */ 564 abort(); 565 } 566 } 567 } 568 569 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 570 { 571 PowerPCCPU *cpu = POWERPC_CPU(cs); 572 CPUPPCState *env = &cpu->env; 573 union { 574 uint32_t u32; 575 uint64_t u64; 576 } val; 577 struct kvm_one_reg reg = { 578 .id = id, 579 .addr = (uintptr_t) &val, 580 }; 581 int ret; 582 583 switch (id & KVM_REG_SIZE_MASK) { 584 case KVM_REG_SIZE_U32: 585 val.u32 = env->spr[spr]; 586 break; 587 588 case KVM_REG_SIZE_U64: 589 val.u64 = env->spr[spr]; 590 break; 591 592 default: 593 /* Don't handle this size yet */ 594 abort(); 595 } 596 597 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 598 if (ret != 0) { 599 trace_kvm_failed_spr_set(spr, strerror(errno)); 600 } 601 } 602 603 static int kvm_put_fp(CPUState *cs) 604 { 605 PowerPCCPU *cpu = POWERPC_CPU(cs); 606 CPUPPCState *env = &cpu->env; 607 struct kvm_one_reg reg; 608 int i; 609 int ret; 610 611 if (env->insns_flags & PPC_FLOAT) { 612 uint64_t fpscr = env->fpscr; 613 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 614 615 reg.id = KVM_REG_PPC_FPSCR; 616 reg.addr = (uintptr_t)&fpscr; 617 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 618 if (ret < 0) { 619 trace_kvm_failed_fpscr_set(strerror(errno)); 620 return ret; 621 } 622 623 for (i = 0; i < 32; i++) { 624 uint64_t vsr[2]; 625 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 626 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 627 628 #ifdef HOST_WORDS_BIGENDIAN 629 vsr[0] = float64_val(*fpr); 630 vsr[1] = *vsrl; 631 #else 632 vsr[0] = *vsrl; 633 vsr[1] = float64_val(*fpr); 634 #endif 635 reg.addr = (uintptr_t) &vsr; 636 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 637 638 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 639 if (ret < 0) { 640 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 641 strerror(errno)); 642 return ret; 643 } 644 } 645 } 646 647 if (env->insns_flags & PPC_ALTIVEC) { 648 reg.id = KVM_REG_PPC_VSCR; 649 reg.addr = (uintptr_t)&env->vscr; 650 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 651 if (ret < 0) { 652 trace_kvm_failed_vscr_set(strerror(errno)); 653 return ret; 654 } 655 656 for (i = 0; i < 32; i++) { 657 reg.id = KVM_REG_PPC_VR(i); 658 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 659 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 660 if (ret < 0) { 661 trace_kvm_failed_vr_set(i, strerror(errno)); 662 return ret; 663 } 664 } 665 } 666 667 return 0; 668 } 669 670 static int kvm_get_fp(CPUState *cs) 671 { 672 PowerPCCPU *cpu = POWERPC_CPU(cs); 673 CPUPPCState *env = &cpu->env; 674 struct kvm_one_reg reg; 675 int i; 676 int ret; 677 678 if (env->insns_flags & PPC_FLOAT) { 679 uint64_t fpscr; 680 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 681 682 reg.id = KVM_REG_PPC_FPSCR; 683 reg.addr = (uintptr_t)&fpscr; 684 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 685 if (ret < 0) { 686 trace_kvm_failed_fpscr_get(strerror(errno)); 687 return ret; 688 } else { 689 env->fpscr = fpscr; 690 } 691 692 for (i = 0; i < 32; i++) { 693 uint64_t vsr[2]; 694 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 695 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 696 697 reg.addr = (uintptr_t) &vsr; 698 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 699 700 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 701 if (ret < 0) { 702 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 703 strerror(errno)); 704 return ret; 705 } else { 706 #ifdef HOST_WORDS_BIGENDIAN 707 *fpr = vsr[0]; 708 if (vsx) { 709 *vsrl = vsr[1]; 710 } 711 #else 712 *fpr = vsr[1]; 713 if (vsx) { 714 *vsrl = vsr[0]; 715 } 716 #endif 717 } 718 } 719 } 720 721 if (env->insns_flags & PPC_ALTIVEC) { 722 reg.id = KVM_REG_PPC_VSCR; 723 reg.addr = (uintptr_t)&env->vscr; 724 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 725 if (ret < 0) { 726 trace_kvm_failed_vscr_get(strerror(errno)); 727 return ret; 728 } 729 730 for (i = 0; i < 32; i++) { 731 reg.id = KVM_REG_PPC_VR(i); 732 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 733 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 734 if (ret < 0) { 735 trace_kvm_failed_vr_get(i, strerror(errno)); 736 return ret; 737 } 738 } 739 } 740 741 return 0; 742 } 743 744 #if defined(TARGET_PPC64) 745 static int kvm_get_vpa(CPUState *cs) 746 { 747 PowerPCCPU *cpu = POWERPC_CPU(cs); 748 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 749 struct kvm_one_reg reg; 750 int ret; 751 752 reg.id = KVM_REG_PPC_VPA_ADDR; 753 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 754 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 755 if (ret < 0) { 756 trace_kvm_failed_vpa_addr_get(strerror(errno)); 757 return ret; 758 } 759 760 assert((uintptr_t)&spapr_cpu->slb_shadow_size 761 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 762 reg.id = KVM_REG_PPC_VPA_SLB; 763 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 764 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 765 if (ret < 0) { 766 trace_kvm_failed_slb_get(strerror(errno)); 767 return ret; 768 } 769 770 assert((uintptr_t)&spapr_cpu->dtl_size 771 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 772 reg.id = KVM_REG_PPC_VPA_DTL; 773 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 774 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 775 if (ret < 0) { 776 trace_kvm_failed_dtl_get(strerror(errno)); 777 return ret; 778 } 779 780 return 0; 781 } 782 783 static int kvm_put_vpa(CPUState *cs) 784 { 785 PowerPCCPU *cpu = POWERPC_CPU(cs); 786 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 787 struct kvm_one_reg reg; 788 int ret; 789 790 /* 791 * SLB shadow or DTL can't be registered unless a master VPA is 792 * registered. That means when restoring state, if a VPA *is* 793 * registered, we need to set that up first. If not, we need to 794 * deregister the others before deregistering the master VPA 795 */ 796 assert(spapr_cpu->vpa_addr 797 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 798 799 if (spapr_cpu->vpa_addr) { 800 reg.id = KVM_REG_PPC_VPA_ADDR; 801 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 802 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 803 if (ret < 0) { 804 trace_kvm_failed_vpa_addr_set(strerror(errno)); 805 return ret; 806 } 807 } 808 809 assert((uintptr_t)&spapr_cpu->slb_shadow_size 810 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 811 reg.id = KVM_REG_PPC_VPA_SLB; 812 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 813 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 814 if (ret < 0) { 815 trace_kvm_failed_slb_set(strerror(errno)); 816 return ret; 817 } 818 819 assert((uintptr_t)&spapr_cpu->dtl_size 820 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 821 reg.id = KVM_REG_PPC_VPA_DTL; 822 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 823 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 824 if (ret < 0) { 825 trace_kvm_failed_dtl_set(strerror(errno)); 826 return ret; 827 } 828 829 if (!spapr_cpu->vpa_addr) { 830 reg.id = KVM_REG_PPC_VPA_ADDR; 831 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 832 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 833 if (ret < 0) { 834 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 835 return ret; 836 } 837 } 838 839 return 0; 840 } 841 #endif /* TARGET_PPC64 */ 842 843 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 844 { 845 CPUPPCState *env = &cpu->env; 846 struct kvm_sregs sregs; 847 int i; 848 849 sregs.pvr = env->spr[SPR_PVR]; 850 851 if (cpu->vhyp) { 852 PPCVirtualHypervisorClass *vhc = 853 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 854 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 855 } else { 856 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 857 } 858 859 /* Sync SLB */ 860 #ifdef TARGET_PPC64 861 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 862 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 863 if (env->slb[i].esid & SLB_ESID_V) { 864 sregs.u.s.ppc64.slb[i].slbe |= i; 865 } 866 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 867 } 868 #endif 869 870 /* Sync SRs */ 871 for (i = 0; i < 16; i++) { 872 sregs.u.s.ppc32.sr[i] = env->sr[i]; 873 } 874 875 /* Sync BATs */ 876 for (i = 0; i < 8; i++) { 877 /* Beware. We have to swap upper and lower bits here */ 878 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 879 | env->DBAT[1][i]; 880 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 881 | env->IBAT[1][i]; 882 } 883 884 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 885 } 886 887 int kvm_arch_put_registers(CPUState *cs, int level) 888 { 889 PowerPCCPU *cpu = POWERPC_CPU(cs); 890 CPUPPCState *env = &cpu->env; 891 struct kvm_regs regs; 892 int ret; 893 int i; 894 895 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 896 if (ret < 0) { 897 return ret; 898 } 899 900 regs.ctr = env->ctr; 901 regs.lr = env->lr; 902 regs.xer = cpu_read_xer(env); 903 regs.msr = env->msr; 904 regs.pc = env->nip; 905 906 regs.srr0 = env->spr[SPR_SRR0]; 907 regs.srr1 = env->spr[SPR_SRR1]; 908 909 regs.sprg0 = env->spr[SPR_SPRG0]; 910 regs.sprg1 = env->spr[SPR_SPRG1]; 911 regs.sprg2 = env->spr[SPR_SPRG2]; 912 regs.sprg3 = env->spr[SPR_SPRG3]; 913 regs.sprg4 = env->spr[SPR_SPRG4]; 914 regs.sprg5 = env->spr[SPR_SPRG5]; 915 regs.sprg6 = env->spr[SPR_SPRG6]; 916 regs.sprg7 = env->spr[SPR_SPRG7]; 917 918 regs.pid = env->spr[SPR_BOOKE_PID]; 919 920 for (i = 0; i < 32; i++) { 921 regs.gpr[i] = env->gpr[i]; 922 } 923 924 regs.cr = 0; 925 for (i = 0; i < 8; i++) { 926 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); 927 } 928 929 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 930 if (ret < 0) { 931 return ret; 932 } 933 934 kvm_put_fp(cs); 935 936 if (env->tlb_dirty) { 937 kvm_sw_tlb_put(cpu); 938 env->tlb_dirty = false; 939 } 940 941 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 942 ret = kvmppc_put_books_sregs(cpu); 943 if (ret < 0) { 944 return ret; 945 } 946 } 947 948 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 949 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 950 } 951 952 if (cap_one_reg) { 953 int i; 954 955 /* 956 * We deliberately ignore errors here, for kernels which have 957 * the ONE_REG calls, but don't support the specific 958 * registers, there's a reasonable chance things will still 959 * work, at least until we try to migrate. 960 */ 961 for (i = 0; i < 1024; i++) { 962 uint64_t id = env->spr_cb[i].one_reg_id; 963 964 if (id != 0) { 965 kvm_put_one_spr(cs, id, i); 966 } 967 } 968 969 #ifdef TARGET_PPC64 970 if (msr_ts) { 971 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 972 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 973 } 974 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 975 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 976 } 977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 987 } 988 989 if (cap_papr) { 990 if (kvm_put_vpa(cs) < 0) { 991 trace_kvm_failed_put_vpa(); 992 } 993 } 994 995 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 996 997 if (level > KVM_PUT_RUNTIME_STATE) { 998 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 999 } 1000 #endif /* TARGET_PPC64 */ 1001 } 1002 1003 return ret; 1004 } 1005 1006 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1007 { 1008 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1009 } 1010 1011 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1012 { 1013 CPUPPCState *env = &cpu->env; 1014 struct kvm_sregs sregs; 1015 int ret; 1016 1017 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1018 if (ret < 0) { 1019 return ret; 1020 } 1021 1022 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1023 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1024 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1025 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1026 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1027 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1028 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1029 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1030 env->spr[SPR_DECR] = sregs.u.e.dec; 1031 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1032 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1033 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1034 } 1035 1036 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1037 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1038 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1039 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1040 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1041 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1042 } 1043 1044 if (sregs.u.e.features & KVM_SREGS_E_64) { 1045 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1046 } 1047 1048 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1049 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1050 } 1051 1052 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1053 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1054 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1055 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1056 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1057 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1058 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1059 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1060 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1061 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1062 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1063 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1064 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1065 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1066 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1067 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1068 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1069 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1070 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1071 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1072 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1073 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1074 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1075 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1076 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1077 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1078 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1079 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1080 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1081 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1082 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1083 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1084 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1085 1086 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1087 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1088 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1089 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1090 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1091 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1092 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1093 } 1094 1095 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1096 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1097 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1098 } 1099 1100 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1101 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1102 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1103 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1104 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1105 } 1106 } 1107 1108 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1109 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1110 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1111 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1112 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1113 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1114 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1115 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1116 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1117 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1118 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1119 } 1120 1121 if (sregs.u.e.features & KVM_SREGS_EXP) { 1122 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1123 } 1124 1125 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1126 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1127 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1128 } 1129 1130 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1131 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1132 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1133 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1134 1135 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1136 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1137 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1138 } 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1145 { 1146 CPUPPCState *env = &cpu->env; 1147 struct kvm_sregs sregs; 1148 int ret; 1149 int i; 1150 1151 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1152 if (ret < 0) { 1153 return ret; 1154 } 1155 1156 if (!cpu->vhyp) { 1157 ppc_store_sdr1(env, sregs.u.s.sdr1); 1158 } 1159 1160 /* Sync SLB */ 1161 #ifdef TARGET_PPC64 1162 /* 1163 * The packed SLB array we get from KVM_GET_SREGS only contains 1164 * information about valid entries. So we flush our internal copy 1165 * to get rid of stale ones, then put all valid SLB entries back 1166 * in. 1167 */ 1168 memset(env->slb, 0, sizeof(env->slb)); 1169 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1170 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1171 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1172 /* 1173 * Only restore valid entries 1174 */ 1175 if (rb & SLB_ESID_V) { 1176 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1177 } 1178 } 1179 #endif 1180 1181 /* Sync SRs */ 1182 for (i = 0; i < 16; i++) { 1183 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1184 } 1185 1186 /* Sync BATs */ 1187 for (i = 0; i < 8; i++) { 1188 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1189 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1190 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1191 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1192 } 1193 1194 return 0; 1195 } 1196 1197 int kvm_arch_get_registers(CPUState *cs) 1198 { 1199 PowerPCCPU *cpu = POWERPC_CPU(cs); 1200 CPUPPCState *env = &cpu->env; 1201 struct kvm_regs regs; 1202 uint32_t cr; 1203 int i, ret; 1204 1205 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1206 if (ret < 0) { 1207 return ret; 1208 } 1209 1210 cr = regs.cr; 1211 for (i = 7; i >= 0; i--) { 1212 env->crf[i] = cr & 15; 1213 cr >>= 4; 1214 } 1215 1216 env->ctr = regs.ctr; 1217 env->lr = regs.lr; 1218 cpu_write_xer(env, regs.xer); 1219 env->msr = regs.msr; 1220 env->nip = regs.pc; 1221 1222 env->spr[SPR_SRR0] = regs.srr0; 1223 env->spr[SPR_SRR1] = regs.srr1; 1224 1225 env->spr[SPR_SPRG0] = regs.sprg0; 1226 env->spr[SPR_SPRG1] = regs.sprg1; 1227 env->spr[SPR_SPRG2] = regs.sprg2; 1228 env->spr[SPR_SPRG3] = regs.sprg3; 1229 env->spr[SPR_SPRG4] = regs.sprg4; 1230 env->spr[SPR_SPRG5] = regs.sprg5; 1231 env->spr[SPR_SPRG6] = regs.sprg6; 1232 env->spr[SPR_SPRG7] = regs.sprg7; 1233 1234 env->spr[SPR_BOOKE_PID] = regs.pid; 1235 1236 for (i = 0; i < 32; i++) { 1237 env->gpr[i] = regs.gpr[i]; 1238 } 1239 1240 kvm_get_fp(cs); 1241 1242 if (cap_booke_sregs) { 1243 ret = kvmppc_get_booke_sregs(cpu); 1244 if (ret < 0) { 1245 return ret; 1246 } 1247 } 1248 1249 if (cap_segstate) { 1250 ret = kvmppc_get_books_sregs(cpu); 1251 if (ret < 0) { 1252 return ret; 1253 } 1254 } 1255 1256 if (cap_hior) { 1257 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1258 } 1259 1260 if (cap_one_reg) { 1261 int i; 1262 1263 /* 1264 * We deliberately ignore errors here, for kernels which have 1265 * the ONE_REG calls, but don't support the specific 1266 * registers, there's a reasonable chance things will still 1267 * work, at least until we try to migrate. 1268 */ 1269 for (i = 0; i < 1024; i++) { 1270 uint64_t id = env->spr_cb[i].one_reg_id; 1271 1272 if (id != 0) { 1273 kvm_get_one_spr(cs, id, i); 1274 } 1275 } 1276 1277 #ifdef TARGET_PPC64 1278 if (msr_ts) { 1279 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1281 } 1282 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1284 } 1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1295 } 1296 1297 if (cap_papr) { 1298 if (kvm_get_vpa(cs) < 0) { 1299 trace_kvm_failed_get_vpa(); 1300 } 1301 } 1302 1303 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1304 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1305 #endif 1306 } 1307 1308 return 0; 1309 } 1310 1311 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1312 { 1313 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1314 1315 if (irq != PPC_INTERRUPT_EXT) { 1316 return 0; 1317 } 1318 1319 if (!kvm_enabled() || !cap_interrupt_unset) { 1320 return 0; 1321 } 1322 1323 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1324 1325 return 0; 1326 } 1327 1328 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1329 { 1330 return; 1331 } 1332 1333 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1334 { 1335 return MEMTXATTRS_UNSPECIFIED; 1336 } 1337 1338 int kvm_arch_process_async_events(CPUState *cs) 1339 { 1340 return cs->halted; 1341 } 1342 1343 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1344 { 1345 CPUState *cs = CPU(cpu); 1346 CPUPPCState *env = &cpu->env; 1347 1348 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { 1349 cs->halted = 1; 1350 cs->exception_index = EXCP_HLT; 1351 } 1352 1353 return 0; 1354 } 1355 1356 /* map dcr access to existing qemu dcr emulation */ 1357 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1358 uint32_t dcrn, uint32_t *data) 1359 { 1360 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1361 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1368 uint32_t dcrn, uint32_t data) 1369 { 1370 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1371 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1372 } 1373 1374 return 0; 1375 } 1376 1377 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1378 { 1379 /* Mixed endian case is not handled */ 1380 uint32_t sc = debug_inst_opcode; 1381 1382 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1383 sizeof(sc), 0) || 1384 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1385 return -EINVAL; 1386 } 1387 1388 return 0; 1389 } 1390 1391 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1392 { 1393 uint32_t sc; 1394 1395 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1396 sc != debug_inst_opcode || 1397 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1398 sizeof(sc), 1)) { 1399 return -EINVAL; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int find_hw_breakpoint(target_ulong addr, int type) 1406 { 1407 int n; 1408 1409 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1410 <= ARRAY_SIZE(hw_debug_points)); 1411 1412 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1413 if (hw_debug_points[n].addr == addr && 1414 hw_debug_points[n].type == type) { 1415 return n; 1416 } 1417 } 1418 1419 return -1; 1420 } 1421 1422 static int find_hw_watchpoint(target_ulong addr, int *flag) 1423 { 1424 int n; 1425 1426 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1427 if (n >= 0) { 1428 *flag = BP_MEM_ACCESS; 1429 return n; 1430 } 1431 1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1433 if (n >= 0) { 1434 *flag = BP_MEM_WRITE; 1435 return n; 1436 } 1437 1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1439 if (n >= 0) { 1440 *flag = BP_MEM_READ; 1441 return n; 1442 } 1443 1444 return -1; 1445 } 1446 1447 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1448 target_ulong len, int type) 1449 { 1450 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1451 return -ENOBUFS; 1452 } 1453 1454 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1455 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1456 1457 switch (type) { 1458 case GDB_BREAKPOINT_HW: 1459 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1460 return -ENOBUFS; 1461 } 1462 1463 if (find_hw_breakpoint(addr, type) >= 0) { 1464 return -EEXIST; 1465 } 1466 1467 nb_hw_breakpoint++; 1468 break; 1469 1470 case GDB_WATCHPOINT_WRITE: 1471 case GDB_WATCHPOINT_READ: 1472 case GDB_WATCHPOINT_ACCESS: 1473 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1474 return -ENOBUFS; 1475 } 1476 1477 if (find_hw_breakpoint(addr, type) >= 0) { 1478 return -EEXIST; 1479 } 1480 1481 nb_hw_watchpoint++; 1482 break; 1483 1484 default: 1485 return -ENOSYS; 1486 } 1487 1488 return 0; 1489 } 1490 1491 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1492 target_ulong len, int type) 1493 { 1494 int n; 1495 1496 n = find_hw_breakpoint(addr, type); 1497 if (n < 0) { 1498 return -ENOENT; 1499 } 1500 1501 switch (type) { 1502 case GDB_BREAKPOINT_HW: 1503 nb_hw_breakpoint--; 1504 break; 1505 1506 case GDB_WATCHPOINT_WRITE: 1507 case GDB_WATCHPOINT_READ: 1508 case GDB_WATCHPOINT_ACCESS: 1509 nb_hw_watchpoint--; 1510 break; 1511 1512 default: 1513 return -ENOSYS; 1514 } 1515 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1516 1517 return 0; 1518 } 1519 1520 void kvm_arch_remove_all_hw_breakpoints(void) 1521 { 1522 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1523 } 1524 1525 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1526 { 1527 int n; 1528 1529 /* Software Breakpoint updates */ 1530 if (kvm_sw_breakpoints_active(cs)) { 1531 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1532 } 1533 1534 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1535 <= ARRAY_SIZE(hw_debug_points)); 1536 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1537 1538 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1540 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1541 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1542 switch (hw_debug_points[n].type) { 1543 case GDB_BREAKPOINT_HW: 1544 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1545 break; 1546 case GDB_WATCHPOINT_WRITE: 1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1548 break; 1549 case GDB_WATCHPOINT_READ: 1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1551 break; 1552 case GDB_WATCHPOINT_ACCESS: 1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1554 KVMPPC_DEBUG_WATCH_READ; 1555 break; 1556 default: 1557 cpu_abort(cs, "Unsupported breakpoint type\n"); 1558 } 1559 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1560 } 1561 } 1562 } 1563 1564 static int kvm_handle_hw_breakpoint(CPUState *cs, 1565 struct kvm_debug_exit_arch *arch_info) 1566 { 1567 int handle = 0; 1568 int n; 1569 int flag = 0; 1570 1571 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1572 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1573 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1574 if (n >= 0) { 1575 handle = 1; 1576 } 1577 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1578 KVMPPC_DEBUG_WATCH_WRITE)) { 1579 n = find_hw_watchpoint(arch_info->address, &flag); 1580 if (n >= 0) { 1581 handle = 1; 1582 cs->watchpoint_hit = &hw_watchpoint; 1583 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1584 hw_watchpoint.flags = flag; 1585 } 1586 } 1587 } 1588 return handle; 1589 } 1590 1591 static int kvm_handle_singlestep(void) 1592 { 1593 return 1; 1594 } 1595 1596 static int kvm_handle_sw_breakpoint(void) 1597 { 1598 return 1; 1599 } 1600 1601 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1602 { 1603 CPUState *cs = CPU(cpu); 1604 CPUPPCState *env = &cpu->env; 1605 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1606 1607 if (cs->singlestep_enabled) { 1608 return kvm_handle_singlestep(); 1609 } 1610 1611 if (arch_info->status) { 1612 return kvm_handle_hw_breakpoint(cs, arch_info); 1613 } 1614 1615 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1616 return kvm_handle_sw_breakpoint(); 1617 } 1618 1619 /* 1620 * QEMU is not able to handle debug exception, so inject 1621 * program exception to guest; 1622 * Yes program exception NOT debug exception !! 1623 * When QEMU is using debug resources then debug exception must 1624 * be always set. To achieve this we set MSR_DE and also set 1625 * MSRP_DEP so guest cannot change MSR_DE. 1626 * When emulating debug resource for guest we want guest 1627 * to control MSR_DE (enable/disable debug interrupt on need). 1628 * Supporting both configurations are NOT possible. 1629 * So the result is that we cannot share debug resources 1630 * between QEMU and Guest on BOOKE architecture. 1631 * In the current design QEMU gets the priority over guest, 1632 * this means that if QEMU is using debug resources then guest 1633 * cannot use them; 1634 * For software breakpoint QEMU uses a privileged instruction; 1635 * So there cannot be any reason that we are here for guest 1636 * set debug exception, only possibility is guest executed a 1637 * privileged / illegal instruction and that's why we are 1638 * injecting a program interrupt. 1639 */ 1640 cpu_synchronize_state(cs); 1641 /* 1642 * env->nip is PC, so increment this by 4 to use 1643 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1644 */ 1645 env->nip += 4; 1646 cs->exception_index = POWERPC_EXCP_PROGRAM; 1647 env->error_code = POWERPC_EXCP_INVAL; 1648 ppc_cpu_do_interrupt(cs); 1649 1650 return 0; 1651 } 1652 1653 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1654 { 1655 PowerPCCPU *cpu = POWERPC_CPU(cs); 1656 CPUPPCState *env = &cpu->env; 1657 int ret; 1658 1659 qemu_mutex_lock_iothread(); 1660 1661 switch (run->exit_reason) { 1662 case KVM_EXIT_DCR: 1663 if (run->dcr.is_write) { 1664 trace_kvm_handle_dcr_write(); 1665 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1666 } else { 1667 trace_kvm_handle_dcr_read(); 1668 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1669 } 1670 break; 1671 case KVM_EXIT_HLT: 1672 trace_kvm_handle_halt(); 1673 ret = kvmppc_handle_halt(cpu); 1674 break; 1675 #if defined(TARGET_PPC64) 1676 case KVM_EXIT_PAPR_HCALL: 1677 trace_kvm_handle_papr_hcall(); 1678 run->papr_hcall.ret = spapr_hypercall(cpu, 1679 run->papr_hcall.nr, 1680 run->papr_hcall.args); 1681 ret = 0; 1682 break; 1683 #endif 1684 case KVM_EXIT_EPR: 1685 trace_kvm_handle_epr(); 1686 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1687 ret = 0; 1688 break; 1689 case KVM_EXIT_WATCHDOG: 1690 trace_kvm_handle_watchdog_expiry(); 1691 watchdog_perform_action(); 1692 ret = 0; 1693 break; 1694 1695 case KVM_EXIT_DEBUG: 1696 trace_kvm_handle_debug_exception(); 1697 if (kvm_handle_debug(cpu, run)) { 1698 ret = EXCP_DEBUG; 1699 break; 1700 } 1701 /* re-enter, this exception was guest-internal */ 1702 ret = 0; 1703 break; 1704 1705 default: 1706 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1707 ret = -1; 1708 break; 1709 } 1710 1711 qemu_mutex_unlock_iothread(); 1712 return ret; 1713 } 1714 1715 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1716 { 1717 CPUState *cs = CPU(cpu); 1718 uint32_t bits = tsr_bits; 1719 struct kvm_one_reg reg = { 1720 .id = KVM_REG_PPC_OR_TSR, 1721 .addr = (uintptr_t) &bits, 1722 }; 1723 1724 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1725 } 1726 1727 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1728 { 1729 1730 CPUState *cs = CPU(cpu); 1731 uint32_t bits = tsr_bits; 1732 struct kvm_one_reg reg = { 1733 .id = KVM_REG_PPC_CLEAR_TSR, 1734 .addr = (uintptr_t) &bits, 1735 }; 1736 1737 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1738 } 1739 1740 int kvmppc_set_tcr(PowerPCCPU *cpu) 1741 { 1742 CPUState *cs = CPU(cpu); 1743 CPUPPCState *env = &cpu->env; 1744 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1745 1746 struct kvm_one_reg reg = { 1747 .id = KVM_REG_PPC_TCR, 1748 .addr = (uintptr_t) &tcr, 1749 }; 1750 1751 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1752 } 1753 1754 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1755 { 1756 CPUState *cs = CPU(cpu); 1757 int ret; 1758 1759 if (!kvm_enabled()) { 1760 return -1; 1761 } 1762 1763 if (!cap_ppc_watchdog) { 1764 printf("warning: KVM does not support watchdog"); 1765 return -1; 1766 } 1767 1768 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1769 if (ret < 0) { 1770 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1771 __func__, strerror(-ret)); 1772 return ret; 1773 } 1774 1775 return ret; 1776 } 1777 1778 static int read_cpuinfo(const char *field, char *value, int len) 1779 { 1780 FILE *f; 1781 int ret = -1; 1782 int field_len = strlen(field); 1783 char line[512]; 1784 1785 f = fopen("/proc/cpuinfo", "r"); 1786 if (!f) { 1787 return -1; 1788 } 1789 1790 do { 1791 if (!fgets(line, sizeof(line), f)) { 1792 break; 1793 } 1794 if (!strncmp(line, field, field_len)) { 1795 pstrcpy(value, len, line); 1796 ret = 0; 1797 break; 1798 } 1799 } while (*line); 1800 1801 fclose(f); 1802 1803 return ret; 1804 } 1805 1806 uint32_t kvmppc_get_tbfreq(void) 1807 { 1808 char line[512]; 1809 char *ns; 1810 uint32_t retval = NANOSECONDS_PER_SECOND; 1811 1812 if (read_cpuinfo("timebase", line, sizeof(line))) { 1813 return retval; 1814 } 1815 1816 ns = strchr(line, ':'); 1817 if (!ns) { 1818 return retval; 1819 } 1820 1821 ns++; 1822 1823 return atoi(ns); 1824 } 1825 1826 bool kvmppc_get_host_serial(char **value) 1827 { 1828 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1829 NULL); 1830 } 1831 1832 bool kvmppc_get_host_model(char **value) 1833 { 1834 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1835 } 1836 1837 /* Try to find a device tree node for a CPU with clock-frequency property */ 1838 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1839 { 1840 struct dirent *dirp; 1841 DIR *dp; 1842 1843 dp = opendir(PROC_DEVTREE_CPU); 1844 if (!dp) { 1845 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1846 return -1; 1847 } 1848 1849 buf[0] = '\0'; 1850 while ((dirp = readdir(dp)) != NULL) { 1851 FILE *f; 1852 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1853 dirp->d_name); 1854 f = fopen(buf, "r"); 1855 if (f) { 1856 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1857 fclose(f); 1858 break; 1859 } 1860 buf[0] = '\0'; 1861 } 1862 closedir(dp); 1863 if (buf[0] == '\0') { 1864 printf("Unknown host!\n"); 1865 return -1; 1866 } 1867 1868 return 0; 1869 } 1870 1871 static uint64_t kvmppc_read_int_dt(const char *filename) 1872 { 1873 union { 1874 uint32_t v32; 1875 uint64_t v64; 1876 } u; 1877 FILE *f; 1878 int len; 1879 1880 f = fopen(filename, "rb"); 1881 if (!f) { 1882 return -1; 1883 } 1884 1885 len = fread(&u, 1, sizeof(u), f); 1886 fclose(f); 1887 switch (len) { 1888 case 4: 1889 /* property is a 32-bit quantity */ 1890 return be32_to_cpu(u.v32); 1891 case 8: 1892 return be64_to_cpu(u.v64); 1893 } 1894 1895 return 0; 1896 } 1897 1898 /* 1899 * Read a CPU node property from the host device tree that's a single 1900 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1901 * (can't find or open the property, or doesn't understand the format) 1902 */ 1903 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1904 { 1905 char buf[PATH_MAX], *tmp; 1906 uint64_t val; 1907 1908 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1909 return -1; 1910 } 1911 1912 tmp = g_strdup_printf("%s/%s", buf, propname); 1913 val = kvmppc_read_int_dt(tmp); 1914 g_free(tmp); 1915 1916 return val; 1917 } 1918 1919 uint64_t kvmppc_get_clockfreq(void) 1920 { 1921 return kvmppc_read_int_cpu_dt("clock-frequency"); 1922 } 1923 1924 static int kvmppc_get_dec_bits(void) 1925 { 1926 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1927 1928 if (nr_bits > 0) { 1929 return nr_bits; 1930 } 1931 return 0; 1932 } 1933 1934 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1935 { 1936 CPUState *cs = env_cpu(env); 1937 1938 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1939 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1940 return 0; 1941 } 1942 1943 return 1; 1944 } 1945 1946 int kvmppc_get_hasidle(CPUPPCState *env) 1947 { 1948 struct kvm_ppc_pvinfo pvinfo; 1949 1950 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1951 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1952 return 1; 1953 } 1954 1955 return 0; 1956 } 1957 1958 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 1959 { 1960 uint32_t *hc = (uint32_t *)buf; 1961 struct kvm_ppc_pvinfo pvinfo; 1962 1963 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 1964 memcpy(buf, pvinfo.hcall, buf_len); 1965 return 0; 1966 } 1967 1968 /* 1969 * Fallback to always fail hypercalls regardless of endianness: 1970 * 1971 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 1972 * li r3, -1 1973 * b .+8 (becomes nop in wrong endian) 1974 * bswap32(li r3, -1) 1975 */ 1976 1977 hc[0] = cpu_to_be32(0x08000048); 1978 hc[1] = cpu_to_be32(0x3860ffff); 1979 hc[2] = cpu_to_be32(0x48000008); 1980 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 1981 1982 return 1; 1983 } 1984 1985 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 1986 { 1987 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 1988 } 1989 1990 void kvmppc_enable_logical_ci_hcalls(void) 1991 { 1992 /* 1993 * FIXME: it would be nice if we could detect the cases where 1994 * we're using a device which requires the in kernel 1995 * implementation of these hcalls, but the kernel lacks them and 1996 * produce a warning. 1997 */ 1998 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 1999 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2000 } 2001 2002 void kvmppc_enable_set_mode_hcall(void) 2003 { 2004 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2005 } 2006 2007 void kvmppc_enable_clear_ref_mod_hcalls(void) 2008 { 2009 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2010 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2011 } 2012 2013 void kvmppc_enable_h_page_init(void) 2014 { 2015 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2016 } 2017 2018 void kvmppc_set_papr(PowerPCCPU *cpu) 2019 { 2020 CPUState *cs = CPU(cpu); 2021 int ret; 2022 2023 if (!kvm_enabled()) { 2024 return; 2025 } 2026 2027 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2028 if (ret) { 2029 error_report("This vCPU type or KVM version does not support PAPR"); 2030 exit(1); 2031 } 2032 2033 /* 2034 * Update the capability flag so we sync the right information 2035 * with kvm 2036 */ 2037 cap_papr = 1; 2038 } 2039 2040 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2041 { 2042 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2043 } 2044 2045 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2046 { 2047 CPUState *cs = CPU(cpu); 2048 int ret; 2049 2050 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2051 if (ret && mpic_proxy) { 2052 error_report("This KVM version does not support EPR"); 2053 exit(1); 2054 } 2055 } 2056 2057 int kvmppc_smt_threads(void) 2058 { 2059 return cap_ppc_smt ? cap_ppc_smt : 1; 2060 } 2061 2062 int kvmppc_set_smt_threads(int smt) 2063 { 2064 int ret; 2065 2066 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2067 if (!ret) { 2068 cap_ppc_smt = smt; 2069 } 2070 return ret; 2071 } 2072 2073 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2074 { 2075 int i; 2076 GString *g; 2077 char *s; 2078 2079 assert(kvm_enabled()); 2080 if (cap_ppc_smt_possible) { 2081 g = g_string_new("Available VSMT modes:"); 2082 for (i = 63; i >= 0; i--) { 2083 if ((1UL << i) & cap_ppc_smt_possible) { 2084 g_string_append_printf(g, " %lu", (1UL << i)); 2085 } 2086 } 2087 s = g_string_free(g, false); 2088 error_append_hint(errp, "%s.\n", s); 2089 g_free(s); 2090 } else { 2091 error_append_hint(errp, 2092 "This KVM seems to be too old to support VSMT.\n"); 2093 } 2094 } 2095 2096 2097 #ifdef TARGET_PPC64 2098 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) 2099 { 2100 struct kvm_ppc_smmu_info info; 2101 long rampagesize, best_page_shift; 2102 int i; 2103 2104 /* 2105 * Find the largest hardware supported page size that's less than 2106 * or equal to the (logical) backing page size of guest RAM 2107 */ 2108 kvm_get_smmu_info(&info, &error_fatal); 2109 rampagesize = qemu_minrampagesize(); 2110 best_page_shift = 0; 2111 2112 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2113 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2114 2115 if (!sps->page_shift) { 2116 continue; 2117 } 2118 2119 if ((sps->page_shift > best_page_shift) 2120 && ((1UL << sps->page_shift) <= rampagesize)) { 2121 best_page_shift = sps->page_shift; 2122 } 2123 } 2124 2125 return MIN(current_size, 2126 1ULL << (best_page_shift + hash_shift - 7)); 2127 } 2128 #endif 2129 2130 bool kvmppc_spapr_use_multitce(void) 2131 { 2132 return cap_spapr_multitce; 2133 } 2134 2135 int kvmppc_spapr_enable_inkernel_multitce(void) 2136 { 2137 int ret; 2138 2139 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2140 H_PUT_TCE_INDIRECT, 1); 2141 if (!ret) { 2142 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2143 H_STUFF_TCE, 1); 2144 } 2145 2146 return ret; 2147 } 2148 2149 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2150 uint64_t bus_offset, uint32_t nb_table, 2151 int *pfd, bool need_vfio) 2152 { 2153 long len; 2154 int fd; 2155 void *table; 2156 2157 /* 2158 * Must set fd to -1 so we don't try to munmap when called for 2159 * destroying the table, which the upper layers -will- do 2160 */ 2161 *pfd = -1; 2162 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2163 return NULL; 2164 } 2165 2166 if (cap_spapr_tce_64) { 2167 struct kvm_create_spapr_tce_64 args = { 2168 .liobn = liobn, 2169 .page_shift = page_shift, 2170 .offset = bus_offset >> page_shift, 2171 .size = nb_table, 2172 .flags = 0 2173 }; 2174 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2175 if (fd < 0) { 2176 fprintf(stderr, 2177 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2178 liobn); 2179 return NULL; 2180 } 2181 } else if (cap_spapr_tce) { 2182 uint64_t window_size = (uint64_t) nb_table << page_shift; 2183 struct kvm_create_spapr_tce args = { 2184 .liobn = liobn, 2185 .window_size = window_size, 2186 }; 2187 if ((window_size != args.window_size) || bus_offset) { 2188 return NULL; 2189 } 2190 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2191 if (fd < 0) { 2192 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2193 liobn); 2194 return NULL; 2195 } 2196 } else { 2197 return NULL; 2198 } 2199 2200 len = nb_table * sizeof(uint64_t); 2201 /* FIXME: round this up to page size */ 2202 2203 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2204 if (table == MAP_FAILED) { 2205 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2206 liobn); 2207 close(fd); 2208 return NULL; 2209 } 2210 2211 *pfd = fd; 2212 return table; 2213 } 2214 2215 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2216 { 2217 long len; 2218 2219 if (fd < 0) { 2220 return -1; 2221 } 2222 2223 len = nb_table * sizeof(uint64_t); 2224 if ((munmap(table, len) < 0) || 2225 (close(fd) < 0)) { 2226 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2227 strerror(errno)); 2228 /* Leak the table */ 2229 } 2230 2231 return 0; 2232 } 2233 2234 int kvmppc_reset_htab(int shift_hint) 2235 { 2236 uint32_t shift = shift_hint; 2237 2238 if (!kvm_enabled()) { 2239 /* Full emulation, tell caller to allocate htab itself */ 2240 return 0; 2241 } 2242 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2243 int ret; 2244 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2245 if (ret == -ENOTTY) { 2246 /* 2247 * At least some versions of PR KVM advertise the 2248 * capability, but don't implement the ioctl(). Oops. 2249 * Return 0 so that we allocate the htab in qemu, as is 2250 * correct for PR. 2251 */ 2252 return 0; 2253 } else if (ret < 0) { 2254 return ret; 2255 } 2256 return shift; 2257 } 2258 2259 /* 2260 * We have a kernel that predates the htab reset calls. For PR 2261 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2262 * this era, it has allocated a 16MB fixed size hash table 2263 * already. 2264 */ 2265 if (kvmppc_is_pr(kvm_state)) { 2266 /* PR - tell caller to allocate htab */ 2267 return 0; 2268 } else { 2269 /* HV - assume 16MB kernel allocated htab */ 2270 return 24; 2271 } 2272 } 2273 2274 static inline uint32_t mfpvr(void) 2275 { 2276 uint32_t pvr; 2277 2278 asm ("mfpvr %0" 2279 : "=r"(pvr)); 2280 return pvr; 2281 } 2282 2283 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2284 { 2285 if (on) { 2286 *word |= flags; 2287 } else { 2288 *word &= ~flags; 2289 } 2290 } 2291 2292 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2293 { 2294 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2295 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2296 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2297 2298 /* Now fix up the class with information we can query from the host */ 2299 pcc->pvr = mfpvr(); 2300 2301 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2302 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2303 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2304 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2305 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2306 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2307 2308 if (dcache_size != -1) { 2309 pcc->l1_dcache_size = dcache_size; 2310 } 2311 2312 if (icache_size != -1) { 2313 pcc->l1_icache_size = icache_size; 2314 } 2315 2316 #if defined(TARGET_PPC64) 2317 pcc->radix_page_info = kvm_get_radix_page_info(); 2318 2319 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2320 /* 2321 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2322 * compliant. More importantly, advertising ISA 3.00 2323 * architected mode may prevent guests from activating 2324 * necessary DD1 workarounds. 2325 */ 2326 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2327 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2328 } 2329 #endif /* defined(TARGET_PPC64) */ 2330 } 2331 2332 bool kvmppc_has_cap_epr(void) 2333 { 2334 return cap_epr; 2335 } 2336 2337 bool kvmppc_has_cap_fixup_hcalls(void) 2338 { 2339 return cap_fixup_hcalls; 2340 } 2341 2342 bool kvmppc_has_cap_htm(void) 2343 { 2344 return cap_htm; 2345 } 2346 2347 bool kvmppc_has_cap_mmu_radix(void) 2348 { 2349 return cap_mmu_radix; 2350 } 2351 2352 bool kvmppc_has_cap_mmu_hash_v3(void) 2353 { 2354 return cap_mmu_hash_v3; 2355 } 2356 2357 static bool kvmppc_power8_host(void) 2358 { 2359 bool ret = false; 2360 #ifdef TARGET_PPC64 2361 { 2362 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2363 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2364 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2365 (base_pvr == CPU_POWERPC_POWER8_BASE); 2366 } 2367 #endif /* TARGET_PPC64 */ 2368 return ret; 2369 } 2370 2371 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2372 { 2373 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2374 2375 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2376 return 2; 2377 } else if ((!l1d_thread_priv_req || 2378 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2379 (c.character & c.character_mask 2380 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2381 return 1; 2382 } 2383 2384 return 0; 2385 } 2386 2387 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2388 { 2389 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2390 return 2; 2391 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2392 return 1; 2393 } 2394 2395 return 0; 2396 } 2397 2398 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2399 { 2400 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2401 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2402 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2403 return SPAPR_CAP_FIXED_NA; 2404 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2405 return SPAPR_CAP_WORKAROUND; 2406 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2407 return SPAPR_CAP_FIXED_CCD; 2408 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2409 return SPAPR_CAP_FIXED_IBS; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2416 { 2417 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2418 return 1; 2419 } 2420 return 0; 2421 } 2422 2423 bool kvmppc_has_cap_xive(void) 2424 { 2425 return cap_xive; 2426 } 2427 2428 static void kvmppc_get_cpu_characteristics(KVMState *s) 2429 { 2430 struct kvm_ppc_cpu_char c; 2431 int ret; 2432 2433 /* Assume broken */ 2434 cap_ppc_safe_cache = 0; 2435 cap_ppc_safe_bounds_check = 0; 2436 cap_ppc_safe_indirect_branch = 0; 2437 2438 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2439 if (!ret) { 2440 return; 2441 } 2442 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2443 if (ret < 0) { 2444 return; 2445 } 2446 2447 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2448 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2449 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2450 cap_ppc_count_cache_flush_assist = 2451 parse_cap_ppc_count_cache_flush_assist(c); 2452 } 2453 2454 int kvmppc_get_cap_safe_cache(void) 2455 { 2456 return cap_ppc_safe_cache; 2457 } 2458 2459 int kvmppc_get_cap_safe_bounds_check(void) 2460 { 2461 return cap_ppc_safe_bounds_check; 2462 } 2463 2464 int kvmppc_get_cap_safe_indirect_branch(void) 2465 { 2466 return cap_ppc_safe_indirect_branch; 2467 } 2468 2469 int kvmppc_get_cap_count_cache_flush_assist(void) 2470 { 2471 return cap_ppc_count_cache_flush_assist; 2472 } 2473 2474 bool kvmppc_has_cap_nested_kvm_hv(void) 2475 { 2476 return !!cap_ppc_nested_kvm_hv; 2477 } 2478 2479 int kvmppc_set_cap_nested_kvm_hv(int enable) 2480 { 2481 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2482 } 2483 2484 bool kvmppc_has_cap_spapr_vfio(void) 2485 { 2486 return cap_spapr_vfio; 2487 } 2488 2489 int kvmppc_get_cap_large_decr(void) 2490 { 2491 return cap_large_decr; 2492 } 2493 2494 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2495 { 2496 CPUState *cs = CPU(cpu); 2497 uint64_t lpcr; 2498 2499 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2500 /* Do we need to modify the LPCR? */ 2501 if (!!(lpcr & LPCR_LD) != !!enable) { 2502 if (enable) { 2503 lpcr |= LPCR_LD; 2504 } else { 2505 lpcr &= ~LPCR_LD; 2506 } 2507 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2508 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2509 2510 if (!!(lpcr & LPCR_LD) != !!enable) { 2511 return -1; 2512 } 2513 } 2514 2515 return 0; 2516 } 2517 2518 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2519 { 2520 uint32_t host_pvr = mfpvr(); 2521 PowerPCCPUClass *pvr_pcc; 2522 2523 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2524 if (pvr_pcc == NULL) { 2525 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2526 } 2527 2528 return pvr_pcc; 2529 } 2530 2531 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2532 { 2533 MachineClass *mc = MACHINE_CLASS(oc); 2534 2535 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2536 } 2537 2538 static int kvm_ppc_register_host_cpu_type(void) 2539 { 2540 TypeInfo type_info = { 2541 .name = TYPE_HOST_POWERPC_CPU, 2542 .class_init = kvmppc_host_cpu_class_init, 2543 }; 2544 PowerPCCPUClass *pvr_pcc; 2545 ObjectClass *oc; 2546 DeviceClass *dc; 2547 int i; 2548 2549 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2550 if (pvr_pcc == NULL) { 2551 return -1; 2552 } 2553 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2554 type_register(&type_info); 2555 /* override TCG default cpu type with 'host' cpu model */ 2556 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2557 false, NULL); 2558 2559 oc = object_class_by_name(type_info.name); 2560 g_assert(oc); 2561 2562 /* 2563 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2564 * we want "POWER8" to be a "family" alias that points to the current 2565 * host CPU type, too) 2566 */ 2567 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2568 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2569 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2570 char *suffix; 2571 2572 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2573 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2574 if (suffix) { 2575 *suffix = 0; 2576 } 2577 break; 2578 } 2579 } 2580 2581 return 0; 2582 } 2583 2584 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2585 { 2586 struct kvm_rtas_token_args args = { 2587 .token = token, 2588 }; 2589 2590 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2591 return -ENOENT; 2592 } 2593 2594 strncpy(args.name, function, sizeof(args.name) - 1); 2595 2596 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2597 } 2598 2599 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2600 { 2601 struct kvm_get_htab_fd s = { 2602 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2603 .start_index = index, 2604 }; 2605 int ret; 2606 2607 if (!cap_htab_fd) { 2608 error_setg(errp, "KVM version doesn't support %s the HPT", 2609 write ? "writing" : "reading"); 2610 return -ENOTSUP; 2611 } 2612 2613 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2614 if (ret < 0) { 2615 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2616 write ? "writing" : "reading", write ? "to" : "from", 2617 strerror(errno)); 2618 return -errno; 2619 } 2620 2621 return ret; 2622 } 2623 2624 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2625 { 2626 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2627 uint8_t buf[bufsize]; 2628 ssize_t rc; 2629 2630 do { 2631 rc = read(fd, buf, bufsize); 2632 if (rc < 0) { 2633 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2634 strerror(errno)); 2635 return rc; 2636 } else if (rc) { 2637 uint8_t *buffer = buf; 2638 ssize_t n = rc; 2639 while (n) { 2640 struct kvm_get_htab_header *head = 2641 (struct kvm_get_htab_header *) buffer; 2642 size_t chunksize = sizeof(*head) + 2643 HASH_PTE_SIZE_64 * head->n_valid; 2644 2645 qemu_put_be32(f, head->index); 2646 qemu_put_be16(f, head->n_valid); 2647 qemu_put_be16(f, head->n_invalid); 2648 qemu_put_buffer(f, (void *)(head + 1), 2649 HASH_PTE_SIZE_64 * head->n_valid); 2650 2651 buffer += chunksize; 2652 n -= chunksize; 2653 } 2654 } 2655 } while ((rc != 0) 2656 && ((max_ns < 0) || 2657 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2658 2659 return (rc == 0) ? 1 : 0; 2660 } 2661 2662 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2663 uint16_t n_valid, uint16_t n_invalid) 2664 { 2665 struct kvm_get_htab_header *buf; 2666 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2667 ssize_t rc; 2668 2669 buf = alloca(chunksize); 2670 buf->index = index; 2671 buf->n_valid = n_valid; 2672 buf->n_invalid = n_invalid; 2673 2674 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2675 2676 rc = write(fd, buf, chunksize); 2677 if (rc < 0) { 2678 fprintf(stderr, "Error writing KVM hash table: %s\n", 2679 strerror(errno)); 2680 return rc; 2681 } 2682 if (rc != chunksize) { 2683 /* We should never get a short write on a single chunk */ 2684 fprintf(stderr, "Short write, restoring KVM hash table\n"); 2685 return -1; 2686 } 2687 return 0; 2688 } 2689 2690 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2691 { 2692 return true; 2693 } 2694 2695 void kvm_arch_init_irq_routing(KVMState *s) 2696 { 2697 } 2698 2699 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2700 { 2701 int fd, rc; 2702 int i; 2703 2704 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2705 2706 i = 0; 2707 while (i < n) { 2708 struct kvm_get_htab_header *hdr; 2709 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2710 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2711 2712 rc = read(fd, buf, sizeof(buf)); 2713 if (rc < 0) { 2714 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2715 } 2716 2717 hdr = (struct kvm_get_htab_header *)buf; 2718 while ((i < n) && ((char *)hdr < (buf + rc))) { 2719 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2720 2721 if (hdr->index != (ptex + i)) { 2722 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2723 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2724 } 2725 2726 if (n - i < valid) { 2727 valid = n - i; 2728 } 2729 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2730 i += valid; 2731 2732 if ((n - i) < invalid) { 2733 invalid = n - i; 2734 } 2735 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2736 i += invalid; 2737 2738 hdr = (struct kvm_get_htab_header *) 2739 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2740 } 2741 } 2742 2743 close(fd); 2744 } 2745 2746 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2747 { 2748 int fd, rc; 2749 struct { 2750 struct kvm_get_htab_header hdr; 2751 uint64_t pte0; 2752 uint64_t pte1; 2753 } buf; 2754 2755 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2756 2757 buf.hdr.n_valid = 1; 2758 buf.hdr.n_invalid = 0; 2759 buf.hdr.index = ptex; 2760 buf.pte0 = cpu_to_be64(pte0); 2761 buf.pte1 = cpu_to_be64(pte1); 2762 2763 rc = write(fd, &buf, sizeof(buf)); 2764 if (rc != sizeof(buf)) { 2765 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2766 } 2767 close(fd); 2768 } 2769 2770 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2771 uint64_t address, uint32_t data, PCIDevice *dev) 2772 { 2773 return 0; 2774 } 2775 2776 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2777 int vector, PCIDevice *dev) 2778 { 2779 return 0; 2780 } 2781 2782 int kvm_arch_release_virq_post(int virq) 2783 { 2784 return 0; 2785 } 2786 2787 int kvm_arch_msi_data_to_gsi(uint32_t data) 2788 { 2789 return data & 0xffff; 2790 } 2791 2792 int kvmppc_enable_hwrng(void) 2793 { 2794 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2795 return -1; 2796 } 2797 2798 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2799 } 2800 2801 void kvmppc_check_papr_resize_hpt(Error **errp) 2802 { 2803 if (!kvm_enabled()) { 2804 return; /* No KVM, we're good */ 2805 } 2806 2807 if (cap_resize_hpt) { 2808 return; /* Kernel has explicit support, we're good */ 2809 } 2810 2811 /* Otherwise fallback on looking for PR KVM */ 2812 if (kvmppc_is_pr(kvm_state)) { 2813 return; 2814 } 2815 2816 error_setg(errp, 2817 "Hash page table resizing not available with this KVM version"); 2818 } 2819 2820 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2821 { 2822 CPUState *cs = CPU(cpu); 2823 struct kvm_ppc_resize_hpt rhpt = { 2824 .flags = flags, 2825 .shift = shift, 2826 }; 2827 2828 if (!cap_resize_hpt) { 2829 return -ENOSYS; 2830 } 2831 2832 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2833 } 2834 2835 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2836 { 2837 CPUState *cs = CPU(cpu); 2838 struct kvm_ppc_resize_hpt rhpt = { 2839 .flags = flags, 2840 .shift = shift, 2841 }; 2842 2843 if (!cap_resize_hpt) { 2844 return -ENOSYS; 2845 } 2846 2847 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2848 } 2849 2850 /* 2851 * This is a helper function to detect a post migration scenario 2852 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2853 * the guest kernel can't handle a PVR value other than the actual host 2854 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2855 * 2856 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2857 * (so, we're HV), return true. The workaround itself is done in 2858 * cpu_post_load. 2859 * 2860 * The order here is important: we'll only check for KVM PR as a 2861 * fallback if the guest kernel can't handle the situation itself. 2862 * We need to avoid as much as possible querying the running KVM type 2863 * in QEMU level. 2864 */ 2865 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2866 { 2867 CPUState *cs = CPU(cpu); 2868 2869 if (!kvm_enabled()) { 2870 return false; 2871 } 2872 2873 if (cap_ppc_pvr_compat) { 2874 return false; 2875 } 2876 2877 return !kvmppc_is_pr(cs->kvm_state); 2878 } 2879 2880 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2881 { 2882 CPUState *cs = CPU(cpu); 2883 2884 if (kvm_enabled()) { 2885 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2886 } 2887 } 2888 2889 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2890 { 2891 CPUState *cs = CPU(cpu); 2892 2893 if (kvm_enabled()) { 2894 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2895 } 2896 } 2897 2898 /* 2899 * Don't set error if KVM_PPC_SVM_OFF ioctl is invoked on kernels 2900 * that don't support this ioctl. 2901 */ 2902 void kvmppc_svm_off(Error **errp) 2903 { 2904 int rc; 2905 2906 if (!kvm_enabled()) { 2907 return; 2908 } 2909 2910 rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF); 2911 if (rc && rc != -ENOTTY) { 2912 error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed"); 2913 } 2914 } 2915