1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu-common.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "cpu.h" 28 #include "cpu-models.h" 29 #include "qemu/timer.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/hw_accel.h" 32 #include "kvm_ppc.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/device_tree.h" 35 #include "mmu-hash64.h" 36 37 #include "hw/sysbus.h" 38 #include "hw/ppc/spapr.h" 39 #include "hw/ppc/spapr_cpu_core.h" 40 #include "hw/ppc/ppc.h" 41 #include "sysemu/watchdog.h" 42 #include "trace.h" 43 #include "exec/gdbstub.h" 44 #include "exec/memattrs.h" 45 #include "exec/ram_addr.h" 46 #include "sysemu/hostmem.h" 47 #include "qemu/cutils.h" 48 #include "qemu/mmap-alloc.h" 49 #include "elf.h" 50 #include "sysemu/kvm_int.h" 51 52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 53 54 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 55 KVM_CAP_LAST_INFO 56 }; 57 58 static int cap_interrupt_unset; 59 static int cap_interrupt_level; 60 static int cap_segstate; 61 static int cap_booke_sregs; 62 static int cap_ppc_smt; 63 static int cap_ppc_smt_possible; 64 static int cap_spapr_tce; 65 static int cap_spapr_tce_64; 66 static int cap_spapr_multitce; 67 static int cap_spapr_vfio; 68 static int cap_hior; 69 static int cap_one_reg; 70 static int cap_epr; 71 static int cap_ppc_watchdog; 72 static int cap_papr; 73 static int cap_htab_fd; 74 static int cap_fixup_hcalls; 75 static int cap_htm; /* Hardware transactional memory support */ 76 static int cap_mmu_radix; 77 static int cap_mmu_hash_v3; 78 static int cap_resize_hpt; 79 static int cap_ppc_pvr_compat; 80 static int cap_ppc_safe_cache; 81 static int cap_ppc_safe_bounds_check; 82 static int cap_ppc_safe_indirect_branch; 83 static int cap_ppc_count_cache_flush_assist; 84 static int cap_ppc_nested_kvm_hv; 85 static int cap_large_decr; 86 87 static uint32_t debug_inst_opcode; 88 89 /* 90 * XXX We have a race condition where we actually have a level triggered 91 * interrupt, but the infrastructure can't expose that yet, so the guest 92 * takes but ignores it, goes to sleep and never gets notified that there's 93 * still an interrupt pending. 94 * 95 * As a quick workaround, let's just wake up again 20 ms after we injected 96 * an interrupt. That way we can assure that we're always reinjecting 97 * interrupts in case the guest swallowed them. 98 */ 99 static QEMUTimer *idle_timer; 100 101 static void kvm_kick_cpu(void *opaque) 102 { 103 PowerPCCPU *cpu = opaque; 104 105 qemu_cpu_kick(CPU(cpu)); 106 } 107 108 /* 109 * Check whether we are running with KVM-PR (instead of KVM-HV). This 110 * should only be used for fallback tests - generally we should use 111 * explicit capabilities for the features we want, rather than 112 * assuming what is/isn't available depending on the KVM variant. 113 */ 114 static bool kvmppc_is_pr(KVMState *ks) 115 { 116 /* Assume KVM-PR if the GET_PVINFO capability is available */ 117 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 118 } 119 120 static int kvm_ppc_register_host_cpu_type(MachineState *ms); 121 static void kvmppc_get_cpu_characteristics(KVMState *s); 122 static int kvmppc_get_dec_bits(void); 123 124 int kvm_arch_init(MachineState *ms, KVMState *s) 125 { 126 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 127 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); 128 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 129 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 130 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 131 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 132 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 133 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 134 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 135 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 136 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 137 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 138 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 139 /* 140 * Note: we don't set cap_papr here, because this capability is 141 * only activated after this by kvmppc_set_papr() 142 */ 143 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 144 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 145 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 146 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 147 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 148 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 149 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 150 kvmppc_get_cpu_characteristics(s); 151 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 152 cap_large_decr = kvmppc_get_dec_bits(); 153 /* 154 * Note: setting it to false because there is not such capability 155 * in KVM at this moment. 156 * 157 * TODO: call kvm_vm_check_extension() with the right capability 158 * after the kernel starts implementing it. 159 */ 160 cap_ppc_pvr_compat = false; 161 162 if (!cap_interrupt_level) { 163 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " 164 "VM to stall at times!\n"); 165 } 166 167 kvm_ppc_register_host_cpu_type(ms); 168 169 return 0; 170 } 171 172 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s) 173 { 174 return 0; 175 } 176 177 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 178 { 179 CPUPPCState *cenv = &cpu->env; 180 CPUState *cs = CPU(cpu); 181 struct kvm_sregs sregs; 182 int ret; 183 184 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 185 /* 186 * What we're really trying to say is "if we're on BookE, we 187 * use the native PVR for now". This is the only sane way to 188 * check it though, so we potentially confuse users that they 189 * can run BookE guests on BookS. Let's hope nobody dares 190 * enough :) 191 */ 192 return 0; 193 } else { 194 if (!cap_segstate) { 195 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 196 return -ENOSYS; 197 } 198 } 199 200 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 201 if (ret) { 202 return ret; 203 } 204 205 sregs.pvr = cenv->spr[SPR_PVR]; 206 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 207 } 208 209 /* Set up a shared TLB array with KVM */ 210 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 211 { 212 CPUPPCState *env = &cpu->env; 213 CPUState *cs = CPU(cpu); 214 struct kvm_book3e_206_tlb_params params = {}; 215 struct kvm_config_tlb cfg = {}; 216 unsigned int entries = 0; 217 int ret, i; 218 219 if (!kvm_enabled() || 220 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 221 return 0; 222 } 223 224 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 225 226 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 227 params.tlb_sizes[i] = booke206_tlb_size(env, i); 228 params.tlb_ways[i] = booke206_tlb_ways(env, i); 229 entries += params.tlb_sizes[i]; 230 } 231 232 assert(entries == env->nb_tlb); 233 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 234 235 env->tlb_dirty = true; 236 237 cfg.array = (uintptr_t)env->tlb.tlbm; 238 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 239 cfg.params = (uintptr_t)¶ms; 240 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 241 242 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 243 if (ret < 0) { 244 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 245 __func__, strerror(-ret)); 246 return ret; 247 } 248 249 env->kvm_sw_tlb = true; 250 return 0; 251 } 252 253 254 #if defined(TARGET_PPC64) 255 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 256 { 257 int ret; 258 259 assert(kvm_state != NULL); 260 261 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 262 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 263 error_append_hint(errp, "Consider switching to a newer KVM\n"); 264 return; 265 } 266 267 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 268 if (ret == 0) { 269 return; 270 } 271 272 error_setg_errno(errp, -ret, 273 "KVM failed to provide the MMU features it supports"); 274 } 275 276 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 277 { 278 KVMState *s = KVM_STATE(current_machine->accelerator); 279 struct ppc_radix_page_info *radix_page_info; 280 struct kvm_ppc_rmmu_info rmmu_info; 281 int i; 282 283 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 284 return NULL; 285 } 286 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 287 return NULL; 288 } 289 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 290 radix_page_info->count = 0; 291 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 292 if (rmmu_info.ap_encodings[i]) { 293 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 294 radix_page_info->count++; 295 } 296 } 297 return radix_page_info; 298 } 299 300 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 301 bool radix, bool gtse, 302 uint64_t proc_tbl) 303 { 304 CPUState *cs = CPU(cpu); 305 int ret; 306 uint64_t flags = 0; 307 struct kvm_ppc_mmuv3_cfg cfg = { 308 .process_table = proc_tbl, 309 }; 310 311 if (radix) { 312 flags |= KVM_PPC_MMUV3_RADIX; 313 } 314 if (gtse) { 315 flags |= KVM_PPC_MMUV3_GTSE; 316 } 317 cfg.flags = flags; 318 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 319 switch (ret) { 320 case 0: 321 return H_SUCCESS; 322 case -EINVAL: 323 return H_PARAMETER; 324 case -ENODEV: 325 return H_NOT_AVAILABLE; 326 default: 327 return H_HARDWARE; 328 } 329 } 330 331 bool kvmppc_hpt_needs_host_contiguous_pages(void) 332 { 333 static struct kvm_ppc_smmu_info smmu_info; 334 335 if (!kvm_enabled()) { 336 return false; 337 } 338 339 kvm_get_smmu_info(&smmu_info, &error_fatal); 340 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 341 } 342 343 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 344 { 345 struct kvm_ppc_smmu_info smmu_info; 346 int iq, ik, jq, jk; 347 Error *local_err = NULL; 348 349 /* For now, we only have anything to check on hash64 MMUs */ 350 if (!cpu->hash64_opts || !kvm_enabled()) { 351 return; 352 } 353 354 kvm_get_smmu_info(&smmu_info, &local_err); 355 if (local_err) { 356 error_propagate(errp, local_err); 357 return; 358 } 359 360 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 361 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 362 error_setg(errp, 363 "KVM does not support 1TiB segments which guest expects"); 364 return; 365 } 366 367 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 368 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 369 smmu_info.slb_size, cpu->hash64_opts->slb_size); 370 return; 371 } 372 373 /* 374 * Verify that every pagesize supported by the cpu model is 375 * supported by KVM with the same encodings 376 */ 377 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 378 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 379 struct kvm_ppc_one_seg_page_size *ksps; 380 381 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 382 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 383 break; 384 } 385 } 386 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 387 error_setg(errp, "KVM doesn't support for base page shift %u", 388 qsps->page_shift); 389 return; 390 } 391 392 ksps = &smmu_info.sps[ik]; 393 if (ksps->slb_enc != qsps->slb_enc) { 394 error_setg(errp, 395 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 396 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 397 return; 398 } 399 400 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 401 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 402 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 403 break; 404 } 405 } 406 407 if (jk >= ARRAY_SIZE(ksps->enc)) { 408 error_setg(errp, "KVM doesn't support page shift %u/%u", 409 qsps->enc[jq].page_shift, qsps->page_shift); 410 return; 411 } 412 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 413 error_setg(errp, 414 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 415 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 416 qsps->page_shift, qsps->enc[jq].pte_enc); 417 return; 418 } 419 } 420 } 421 422 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 423 /* 424 * Mostly what guest pagesizes we can use are related to the 425 * host pages used to map guest RAM, which is handled in the 426 * platform code. Cache-Inhibited largepages (64k) however are 427 * used for I/O, so if they're mapped to the host at all it 428 * will be a normal mapping, not a special hugepage one used 429 * for RAM. 430 */ 431 if (getpagesize() < 0x10000) { 432 error_setg(errp, 433 "KVM can't supply 64kiB CI pages, which guest expects"); 434 } 435 } 436 } 437 #endif /* !defined (TARGET_PPC64) */ 438 439 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 440 { 441 return POWERPC_CPU(cpu)->vcpu_id; 442 } 443 444 /* 445 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 446 * only 1 watchpoint, so array size of 4 is sufficient for now. 447 */ 448 #define MAX_HW_BKPTS 4 449 450 static struct HWBreakpoint { 451 target_ulong addr; 452 int type; 453 } hw_debug_points[MAX_HW_BKPTS]; 454 455 static CPUWatchpoint hw_watchpoint; 456 457 /* Default there is no breakpoint and watchpoint supported */ 458 static int max_hw_breakpoint; 459 static int max_hw_watchpoint; 460 static int nb_hw_breakpoint; 461 static int nb_hw_watchpoint; 462 463 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 464 { 465 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 466 max_hw_breakpoint = 2; 467 max_hw_watchpoint = 2; 468 } 469 470 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 471 fprintf(stderr, "Error initializing h/w breakpoints\n"); 472 return; 473 } 474 } 475 476 int kvm_arch_init_vcpu(CPUState *cs) 477 { 478 PowerPCCPU *cpu = POWERPC_CPU(cs); 479 CPUPPCState *cenv = &cpu->env; 480 int ret; 481 482 /* Synchronize sregs with kvm */ 483 ret = kvm_arch_sync_sregs(cpu); 484 if (ret) { 485 if (ret == -EINVAL) { 486 error_report("Register sync failed... If you're using kvm-hv.ko," 487 " only \"-cpu host\" is possible"); 488 } 489 return ret; 490 } 491 492 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu); 493 494 switch (cenv->mmu_model) { 495 case POWERPC_MMU_BOOKE206: 496 /* This target supports access to KVM's guest TLB */ 497 ret = kvm_booke206_tlb_init(cpu); 498 break; 499 case POWERPC_MMU_2_07: 500 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 501 /* 502 * KVM-HV has transactional memory on POWER8 also without 503 * the KVM_CAP_PPC_HTM extension, so enable it here 504 * instead as long as it's availble to userspace on the 505 * host. 506 */ 507 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 508 cap_htm = true; 509 } 510 } 511 break; 512 default: 513 break; 514 } 515 516 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 517 kvmppc_hw_debug_points_init(cenv); 518 519 return ret; 520 } 521 522 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 523 { 524 CPUPPCState *env = &cpu->env; 525 CPUState *cs = CPU(cpu); 526 struct kvm_dirty_tlb dirty_tlb; 527 unsigned char *bitmap; 528 int ret; 529 530 if (!env->kvm_sw_tlb) { 531 return; 532 } 533 534 bitmap = g_malloc((env->nb_tlb + 7) / 8); 535 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 536 537 dirty_tlb.bitmap = (uintptr_t)bitmap; 538 dirty_tlb.num_dirty = env->nb_tlb; 539 540 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 541 if (ret) { 542 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 543 __func__, strerror(-ret)); 544 } 545 546 g_free(bitmap); 547 } 548 549 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 550 { 551 PowerPCCPU *cpu = POWERPC_CPU(cs); 552 CPUPPCState *env = &cpu->env; 553 union { 554 uint32_t u32; 555 uint64_t u64; 556 } val; 557 struct kvm_one_reg reg = { 558 .id = id, 559 .addr = (uintptr_t) &val, 560 }; 561 int ret; 562 563 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 564 if (ret != 0) { 565 trace_kvm_failed_spr_get(spr, strerror(errno)); 566 } else { 567 switch (id & KVM_REG_SIZE_MASK) { 568 case KVM_REG_SIZE_U32: 569 env->spr[spr] = val.u32; 570 break; 571 572 case KVM_REG_SIZE_U64: 573 env->spr[spr] = val.u64; 574 break; 575 576 default: 577 /* Don't handle this size yet */ 578 abort(); 579 } 580 } 581 } 582 583 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 584 { 585 PowerPCCPU *cpu = POWERPC_CPU(cs); 586 CPUPPCState *env = &cpu->env; 587 union { 588 uint32_t u32; 589 uint64_t u64; 590 } val; 591 struct kvm_one_reg reg = { 592 .id = id, 593 .addr = (uintptr_t) &val, 594 }; 595 int ret; 596 597 switch (id & KVM_REG_SIZE_MASK) { 598 case KVM_REG_SIZE_U32: 599 val.u32 = env->spr[spr]; 600 break; 601 602 case KVM_REG_SIZE_U64: 603 val.u64 = env->spr[spr]; 604 break; 605 606 default: 607 /* Don't handle this size yet */ 608 abort(); 609 } 610 611 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 612 if (ret != 0) { 613 trace_kvm_failed_spr_set(spr, strerror(errno)); 614 } 615 } 616 617 static int kvm_put_fp(CPUState *cs) 618 { 619 PowerPCCPU *cpu = POWERPC_CPU(cs); 620 CPUPPCState *env = &cpu->env; 621 struct kvm_one_reg reg; 622 int i; 623 int ret; 624 625 if (env->insns_flags & PPC_FLOAT) { 626 uint64_t fpscr = env->fpscr; 627 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 628 629 reg.id = KVM_REG_PPC_FPSCR; 630 reg.addr = (uintptr_t)&fpscr; 631 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 632 if (ret < 0) { 633 trace_kvm_failed_fpscr_set(strerror(errno)); 634 return ret; 635 } 636 637 for (i = 0; i < 32; i++) { 638 uint64_t vsr[2]; 639 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 640 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 641 642 #ifdef HOST_WORDS_BIGENDIAN 643 vsr[0] = float64_val(*fpr); 644 vsr[1] = *vsrl; 645 #else 646 vsr[0] = *vsrl; 647 vsr[1] = float64_val(*fpr); 648 #endif 649 reg.addr = (uintptr_t) &vsr; 650 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 651 652 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 653 if (ret < 0) { 654 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 655 strerror(errno)); 656 return ret; 657 } 658 } 659 } 660 661 if (env->insns_flags & PPC_ALTIVEC) { 662 reg.id = KVM_REG_PPC_VSCR; 663 reg.addr = (uintptr_t)&env->vscr; 664 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 665 if (ret < 0) { 666 trace_kvm_failed_vscr_set(strerror(errno)); 667 return ret; 668 } 669 670 for (i = 0; i < 32; i++) { 671 reg.id = KVM_REG_PPC_VR(i); 672 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 673 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 674 if (ret < 0) { 675 trace_kvm_failed_vr_set(i, strerror(errno)); 676 return ret; 677 } 678 } 679 } 680 681 return 0; 682 } 683 684 static int kvm_get_fp(CPUState *cs) 685 { 686 PowerPCCPU *cpu = POWERPC_CPU(cs); 687 CPUPPCState *env = &cpu->env; 688 struct kvm_one_reg reg; 689 int i; 690 int ret; 691 692 if (env->insns_flags & PPC_FLOAT) { 693 uint64_t fpscr; 694 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 695 696 reg.id = KVM_REG_PPC_FPSCR; 697 reg.addr = (uintptr_t)&fpscr; 698 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 699 if (ret < 0) { 700 trace_kvm_failed_fpscr_get(strerror(errno)); 701 return ret; 702 } else { 703 env->fpscr = fpscr; 704 } 705 706 for (i = 0; i < 32; i++) { 707 uint64_t vsr[2]; 708 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 709 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 710 711 reg.addr = (uintptr_t) &vsr; 712 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 713 714 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 715 if (ret < 0) { 716 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 717 strerror(errno)); 718 return ret; 719 } else { 720 #ifdef HOST_WORDS_BIGENDIAN 721 *fpr = vsr[0]; 722 if (vsx) { 723 *vsrl = vsr[1]; 724 } 725 #else 726 *fpr = vsr[1]; 727 if (vsx) { 728 *vsrl = vsr[0]; 729 } 730 #endif 731 } 732 } 733 } 734 735 if (env->insns_flags & PPC_ALTIVEC) { 736 reg.id = KVM_REG_PPC_VSCR; 737 reg.addr = (uintptr_t)&env->vscr; 738 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 739 if (ret < 0) { 740 trace_kvm_failed_vscr_get(strerror(errno)); 741 return ret; 742 } 743 744 for (i = 0; i < 32; i++) { 745 reg.id = KVM_REG_PPC_VR(i); 746 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 747 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 748 if (ret < 0) { 749 trace_kvm_failed_vr_get(i, strerror(errno)); 750 return ret; 751 } 752 } 753 } 754 755 return 0; 756 } 757 758 #if defined(TARGET_PPC64) 759 static int kvm_get_vpa(CPUState *cs) 760 { 761 PowerPCCPU *cpu = POWERPC_CPU(cs); 762 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 763 struct kvm_one_reg reg; 764 int ret; 765 766 reg.id = KVM_REG_PPC_VPA_ADDR; 767 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 768 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 769 if (ret < 0) { 770 trace_kvm_failed_vpa_addr_get(strerror(errno)); 771 return ret; 772 } 773 774 assert((uintptr_t)&spapr_cpu->slb_shadow_size 775 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 776 reg.id = KVM_REG_PPC_VPA_SLB; 777 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 778 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 779 if (ret < 0) { 780 trace_kvm_failed_slb_get(strerror(errno)); 781 return ret; 782 } 783 784 assert((uintptr_t)&spapr_cpu->dtl_size 785 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 786 reg.id = KVM_REG_PPC_VPA_DTL; 787 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 788 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 789 if (ret < 0) { 790 trace_kvm_failed_dtl_get(strerror(errno)); 791 return ret; 792 } 793 794 return 0; 795 } 796 797 static int kvm_put_vpa(CPUState *cs) 798 { 799 PowerPCCPU *cpu = POWERPC_CPU(cs); 800 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 801 struct kvm_one_reg reg; 802 int ret; 803 804 /* 805 * SLB shadow or DTL can't be registered unless a master VPA is 806 * registered. That means when restoring state, if a VPA *is* 807 * registered, we need to set that up first. If not, we need to 808 * deregister the others before deregistering the master VPA 809 */ 810 assert(spapr_cpu->vpa_addr 811 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 812 813 if (spapr_cpu->vpa_addr) { 814 reg.id = KVM_REG_PPC_VPA_ADDR; 815 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 816 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 817 if (ret < 0) { 818 trace_kvm_failed_vpa_addr_set(strerror(errno)); 819 return ret; 820 } 821 } 822 823 assert((uintptr_t)&spapr_cpu->slb_shadow_size 824 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 825 reg.id = KVM_REG_PPC_VPA_SLB; 826 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 827 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 828 if (ret < 0) { 829 trace_kvm_failed_slb_set(strerror(errno)); 830 return ret; 831 } 832 833 assert((uintptr_t)&spapr_cpu->dtl_size 834 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 835 reg.id = KVM_REG_PPC_VPA_DTL; 836 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 837 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 838 if (ret < 0) { 839 trace_kvm_failed_dtl_set(strerror(errno)); 840 return ret; 841 } 842 843 if (!spapr_cpu->vpa_addr) { 844 reg.id = KVM_REG_PPC_VPA_ADDR; 845 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 846 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 847 if (ret < 0) { 848 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 849 return ret; 850 } 851 } 852 853 return 0; 854 } 855 #endif /* TARGET_PPC64 */ 856 857 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 858 { 859 CPUPPCState *env = &cpu->env; 860 struct kvm_sregs sregs; 861 int i; 862 863 sregs.pvr = env->spr[SPR_PVR]; 864 865 if (cpu->vhyp) { 866 PPCVirtualHypervisorClass *vhc = 867 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 868 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 869 } else { 870 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 871 } 872 873 /* Sync SLB */ 874 #ifdef TARGET_PPC64 875 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 876 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 877 if (env->slb[i].esid & SLB_ESID_V) { 878 sregs.u.s.ppc64.slb[i].slbe |= i; 879 } 880 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 881 } 882 #endif 883 884 /* Sync SRs */ 885 for (i = 0; i < 16; i++) { 886 sregs.u.s.ppc32.sr[i] = env->sr[i]; 887 } 888 889 /* Sync BATs */ 890 for (i = 0; i < 8; i++) { 891 /* Beware. We have to swap upper and lower bits here */ 892 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 893 | env->DBAT[1][i]; 894 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 895 | env->IBAT[1][i]; 896 } 897 898 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 899 } 900 901 int kvm_arch_put_registers(CPUState *cs, int level) 902 { 903 PowerPCCPU *cpu = POWERPC_CPU(cs); 904 CPUPPCState *env = &cpu->env; 905 struct kvm_regs regs; 906 int ret; 907 int i; 908 909 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 910 if (ret < 0) { 911 return ret; 912 } 913 914 regs.ctr = env->ctr; 915 regs.lr = env->lr; 916 regs.xer = cpu_read_xer(env); 917 regs.msr = env->msr; 918 regs.pc = env->nip; 919 920 regs.srr0 = env->spr[SPR_SRR0]; 921 regs.srr1 = env->spr[SPR_SRR1]; 922 923 regs.sprg0 = env->spr[SPR_SPRG0]; 924 regs.sprg1 = env->spr[SPR_SPRG1]; 925 regs.sprg2 = env->spr[SPR_SPRG2]; 926 regs.sprg3 = env->spr[SPR_SPRG3]; 927 regs.sprg4 = env->spr[SPR_SPRG4]; 928 regs.sprg5 = env->spr[SPR_SPRG5]; 929 regs.sprg6 = env->spr[SPR_SPRG6]; 930 regs.sprg7 = env->spr[SPR_SPRG7]; 931 932 regs.pid = env->spr[SPR_BOOKE_PID]; 933 934 for (i = 0; i < 32; i++) { 935 regs.gpr[i] = env->gpr[i]; 936 } 937 938 regs.cr = 0; 939 for (i = 0; i < 8; i++) { 940 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); 941 } 942 943 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 944 if (ret < 0) { 945 return ret; 946 } 947 948 kvm_put_fp(cs); 949 950 if (env->tlb_dirty) { 951 kvm_sw_tlb_put(cpu); 952 env->tlb_dirty = false; 953 } 954 955 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 956 ret = kvmppc_put_books_sregs(cpu); 957 if (ret < 0) { 958 return ret; 959 } 960 } 961 962 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 963 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 964 } 965 966 if (cap_one_reg) { 967 int i; 968 969 /* 970 * We deliberately ignore errors here, for kernels which have 971 * the ONE_REG calls, but don't support the specific 972 * registers, there's a reasonable chance things will still 973 * work, at least until we try to migrate. 974 */ 975 for (i = 0; i < 1024; i++) { 976 uint64_t id = env->spr_cb[i].one_reg_id; 977 978 if (id != 0) { 979 kvm_put_one_spr(cs, id, i); 980 } 981 } 982 983 #ifdef TARGET_PPC64 984 if (msr_ts) { 985 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 987 } 988 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 990 } 991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 997 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 999 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1000 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1001 } 1002 1003 if (cap_papr) { 1004 if (kvm_put_vpa(cs) < 0) { 1005 trace_kvm_failed_put_vpa(); 1006 } 1007 } 1008 1009 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1010 #endif /* TARGET_PPC64 */ 1011 } 1012 1013 return ret; 1014 } 1015 1016 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1017 { 1018 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1019 } 1020 1021 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1022 { 1023 CPUPPCState *env = &cpu->env; 1024 struct kvm_sregs sregs; 1025 int ret; 1026 1027 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1028 if (ret < 0) { 1029 return ret; 1030 } 1031 1032 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1033 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1034 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1035 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1036 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1037 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1038 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1039 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1040 env->spr[SPR_DECR] = sregs.u.e.dec; 1041 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1042 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1043 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1044 } 1045 1046 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1047 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1048 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1049 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1050 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1051 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1052 } 1053 1054 if (sregs.u.e.features & KVM_SREGS_E_64) { 1055 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1056 } 1057 1058 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1059 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1060 } 1061 1062 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1063 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1064 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1065 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1066 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1067 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1068 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1069 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1070 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1071 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1072 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1073 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1074 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1075 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1076 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1077 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1078 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1079 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1080 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1081 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1082 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1083 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1084 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1085 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1086 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1087 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1088 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1089 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1090 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1091 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1092 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1093 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1094 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1095 1096 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1097 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1098 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1099 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1100 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1101 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1102 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1103 } 1104 1105 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1106 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1107 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1108 } 1109 1110 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1111 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1112 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1113 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1114 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1115 } 1116 } 1117 1118 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1119 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1120 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1121 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1122 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1123 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1124 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1125 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1126 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1127 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1128 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1129 } 1130 1131 if (sregs.u.e.features & KVM_SREGS_EXP) { 1132 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1133 } 1134 1135 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1136 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1137 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1138 } 1139 1140 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1141 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1142 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1143 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1144 1145 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1146 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1147 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1148 } 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1155 { 1156 CPUPPCState *env = &cpu->env; 1157 struct kvm_sregs sregs; 1158 int ret; 1159 int i; 1160 1161 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1162 if (ret < 0) { 1163 return ret; 1164 } 1165 1166 if (!cpu->vhyp) { 1167 ppc_store_sdr1(env, sregs.u.s.sdr1); 1168 } 1169 1170 /* Sync SLB */ 1171 #ifdef TARGET_PPC64 1172 /* 1173 * The packed SLB array we get from KVM_GET_SREGS only contains 1174 * information about valid entries. So we flush our internal copy 1175 * to get rid of stale ones, then put all valid SLB entries back 1176 * in. 1177 */ 1178 memset(env->slb, 0, sizeof(env->slb)); 1179 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1180 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1181 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1182 /* 1183 * Only restore valid entries 1184 */ 1185 if (rb & SLB_ESID_V) { 1186 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1187 } 1188 } 1189 #endif 1190 1191 /* Sync SRs */ 1192 for (i = 0; i < 16; i++) { 1193 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1194 } 1195 1196 /* Sync BATs */ 1197 for (i = 0; i < 8; i++) { 1198 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1199 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1200 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1201 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1202 } 1203 1204 return 0; 1205 } 1206 1207 int kvm_arch_get_registers(CPUState *cs) 1208 { 1209 PowerPCCPU *cpu = POWERPC_CPU(cs); 1210 CPUPPCState *env = &cpu->env; 1211 struct kvm_regs regs; 1212 uint32_t cr; 1213 int i, ret; 1214 1215 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1216 if (ret < 0) { 1217 return ret; 1218 } 1219 1220 cr = regs.cr; 1221 for (i = 7; i >= 0; i--) { 1222 env->crf[i] = cr & 15; 1223 cr >>= 4; 1224 } 1225 1226 env->ctr = regs.ctr; 1227 env->lr = regs.lr; 1228 cpu_write_xer(env, regs.xer); 1229 env->msr = regs.msr; 1230 env->nip = regs.pc; 1231 1232 env->spr[SPR_SRR0] = regs.srr0; 1233 env->spr[SPR_SRR1] = regs.srr1; 1234 1235 env->spr[SPR_SPRG0] = regs.sprg0; 1236 env->spr[SPR_SPRG1] = regs.sprg1; 1237 env->spr[SPR_SPRG2] = regs.sprg2; 1238 env->spr[SPR_SPRG3] = regs.sprg3; 1239 env->spr[SPR_SPRG4] = regs.sprg4; 1240 env->spr[SPR_SPRG5] = regs.sprg5; 1241 env->spr[SPR_SPRG6] = regs.sprg6; 1242 env->spr[SPR_SPRG7] = regs.sprg7; 1243 1244 env->spr[SPR_BOOKE_PID] = regs.pid; 1245 1246 for (i = 0; i < 32; i++) { 1247 env->gpr[i] = regs.gpr[i]; 1248 } 1249 1250 kvm_get_fp(cs); 1251 1252 if (cap_booke_sregs) { 1253 ret = kvmppc_get_booke_sregs(cpu); 1254 if (ret < 0) { 1255 return ret; 1256 } 1257 } 1258 1259 if (cap_segstate) { 1260 ret = kvmppc_get_books_sregs(cpu); 1261 if (ret < 0) { 1262 return ret; 1263 } 1264 } 1265 1266 if (cap_hior) { 1267 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1268 } 1269 1270 if (cap_one_reg) { 1271 int i; 1272 1273 /* 1274 * We deliberately ignore errors here, for kernels which have 1275 * the ONE_REG calls, but don't support the specific 1276 * registers, there's a reasonable chance things will still 1277 * work, at least until we try to migrate. 1278 */ 1279 for (i = 0; i < 1024; i++) { 1280 uint64_t id = env->spr_cb[i].one_reg_id; 1281 1282 if (id != 0) { 1283 kvm_get_one_spr(cs, id, i); 1284 } 1285 } 1286 1287 #ifdef TARGET_PPC64 1288 if (msr_ts) { 1289 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1291 } 1292 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1294 } 1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1301 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1302 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1303 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1304 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1305 } 1306 1307 if (cap_papr) { 1308 if (kvm_get_vpa(cs) < 0) { 1309 trace_kvm_failed_get_vpa(); 1310 } 1311 } 1312 1313 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1314 #endif 1315 } 1316 1317 return 0; 1318 } 1319 1320 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1321 { 1322 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1323 1324 if (irq != PPC_INTERRUPT_EXT) { 1325 return 0; 1326 } 1327 1328 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { 1329 return 0; 1330 } 1331 1332 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1333 1334 return 0; 1335 } 1336 1337 #if defined(TARGET_PPC64) 1338 #define PPC_INPUT_INT PPC970_INPUT_INT 1339 #else 1340 #define PPC_INPUT_INT PPC6xx_INPUT_INT 1341 #endif 1342 1343 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1344 { 1345 PowerPCCPU *cpu = POWERPC_CPU(cs); 1346 CPUPPCState *env = &cpu->env; 1347 int r; 1348 unsigned irq; 1349 1350 qemu_mutex_lock_iothread(); 1351 1352 /* 1353 * PowerPC QEMU tracks the various core input pins (interrupt, 1354 * critical interrupt, reset, etc) in PPC-specific 1355 * env->irq_input_state. 1356 */ 1357 if (!cap_interrupt_level && 1358 run->ready_for_interrupt_injection && 1359 (cs->interrupt_request & CPU_INTERRUPT_HARD) && 1360 (env->irq_input_state & (1 << PPC_INPUT_INT))) 1361 { 1362 /* 1363 * For now KVM disregards the 'irq' argument. However, in the 1364 * future KVM could cache it in-kernel to avoid a heavyweight 1365 * exit when reading the UIC. 1366 */ 1367 irq = KVM_INTERRUPT_SET; 1368 1369 trace_kvm_injected_interrupt(irq); 1370 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); 1371 if (r < 0) { 1372 printf("cpu %d fail inject %x\n", cs->cpu_index, irq); 1373 } 1374 1375 /* Always wake up soon in case the interrupt was level based */ 1376 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1377 (NANOSECONDS_PER_SECOND / 50)); 1378 } 1379 1380 /* 1381 * We don't know if there are more interrupts pending after 1382 * this. However, the guest will return to userspace in the course 1383 * of handling this one anyways, so we will get a chance to 1384 * deliver the rest. 1385 */ 1386 1387 qemu_mutex_unlock_iothread(); 1388 } 1389 1390 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1391 { 1392 return MEMTXATTRS_UNSPECIFIED; 1393 } 1394 1395 int kvm_arch_process_async_events(CPUState *cs) 1396 { 1397 return cs->halted; 1398 } 1399 1400 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1401 { 1402 CPUState *cs = CPU(cpu); 1403 CPUPPCState *env = &cpu->env; 1404 1405 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { 1406 cs->halted = 1; 1407 cs->exception_index = EXCP_HLT; 1408 } 1409 1410 return 0; 1411 } 1412 1413 /* map dcr access to existing qemu dcr emulation */ 1414 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1415 uint32_t dcrn, uint32_t *data) 1416 { 1417 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1418 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1425 uint32_t dcrn, uint32_t data) 1426 { 1427 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1428 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1429 } 1430 1431 return 0; 1432 } 1433 1434 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1435 { 1436 /* Mixed endian case is not handled */ 1437 uint32_t sc = debug_inst_opcode; 1438 1439 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1440 sizeof(sc), 0) || 1441 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1442 return -EINVAL; 1443 } 1444 1445 return 0; 1446 } 1447 1448 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1449 { 1450 uint32_t sc; 1451 1452 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1453 sc != debug_inst_opcode || 1454 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1455 sizeof(sc), 1)) { 1456 return -EINVAL; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int find_hw_breakpoint(target_ulong addr, int type) 1463 { 1464 int n; 1465 1466 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1467 <= ARRAY_SIZE(hw_debug_points)); 1468 1469 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1470 if (hw_debug_points[n].addr == addr && 1471 hw_debug_points[n].type == type) { 1472 return n; 1473 } 1474 } 1475 1476 return -1; 1477 } 1478 1479 static int find_hw_watchpoint(target_ulong addr, int *flag) 1480 { 1481 int n; 1482 1483 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1484 if (n >= 0) { 1485 *flag = BP_MEM_ACCESS; 1486 return n; 1487 } 1488 1489 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1490 if (n >= 0) { 1491 *flag = BP_MEM_WRITE; 1492 return n; 1493 } 1494 1495 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1496 if (n >= 0) { 1497 *flag = BP_MEM_READ; 1498 return n; 1499 } 1500 1501 return -1; 1502 } 1503 1504 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1505 target_ulong len, int type) 1506 { 1507 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1508 return -ENOBUFS; 1509 } 1510 1511 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1512 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1513 1514 switch (type) { 1515 case GDB_BREAKPOINT_HW: 1516 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1517 return -ENOBUFS; 1518 } 1519 1520 if (find_hw_breakpoint(addr, type) >= 0) { 1521 return -EEXIST; 1522 } 1523 1524 nb_hw_breakpoint++; 1525 break; 1526 1527 case GDB_WATCHPOINT_WRITE: 1528 case GDB_WATCHPOINT_READ: 1529 case GDB_WATCHPOINT_ACCESS: 1530 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1531 return -ENOBUFS; 1532 } 1533 1534 if (find_hw_breakpoint(addr, type) >= 0) { 1535 return -EEXIST; 1536 } 1537 1538 nb_hw_watchpoint++; 1539 break; 1540 1541 default: 1542 return -ENOSYS; 1543 } 1544 1545 return 0; 1546 } 1547 1548 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1549 target_ulong len, int type) 1550 { 1551 int n; 1552 1553 n = find_hw_breakpoint(addr, type); 1554 if (n < 0) { 1555 return -ENOENT; 1556 } 1557 1558 switch (type) { 1559 case GDB_BREAKPOINT_HW: 1560 nb_hw_breakpoint--; 1561 break; 1562 1563 case GDB_WATCHPOINT_WRITE: 1564 case GDB_WATCHPOINT_READ: 1565 case GDB_WATCHPOINT_ACCESS: 1566 nb_hw_watchpoint--; 1567 break; 1568 1569 default: 1570 return -ENOSYS; 1571 } 1572 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1573 1574 return 0; 1575 } 1576 1577 void kvm_arch_remove_all_hw_breakpoints(void) 1578 { 1579 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1580 } 1581 1582 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1583 { 1584 int n; 1585 1586 /* Software Breakpoint updates */ 1587 if (kvm_sw_breakpoints_active(cs)) { 1588 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1589 } 1590 1591 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1592 <= ARRAY_SIZE(hw_debug_points)); 1593 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1594 1595 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1596 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1597 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1598 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1599 switch (hw_debug_points[n].type) { 1600 case GDB_BREAKPOINT_HW: 1601 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1602 break; 1603 case GDB_WATCHPOINT_WRITE: 1604 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1605 break; 1606 case GDB_WATCHPOINT_READ: 1607 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1608 break; 1609 case GDB_WATCHPOINT_ACCESS: 1610 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1611 KVMPPC_DEBUG_WATCH_READ; 1612 break; 1613 default: 1614 cpu_abort(cs, "Unsupported breakpoint type\n"); 1615 } 1616 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1617 } 1618 } 1619 } 1620 1621 static int kvm_handle_hw_breakpoint(CPUState *cs, 1622 struct kvm_debug_exit_arch *arch_info) 1623 { 1624 int handle = 0; 1625 int n; 1626 int flag = 0; 1627 1628 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1629 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1630 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1631 if (n >= 0) { 1632 handle = 1; 1633 } 1634 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1635 KVMPPC_DEBUG_WATCH_WRITE)) { 1636 n = find_hw_watchpoint(arch_info->address, &flag); 1637 if (n >= 0) { 1638 handle = 1; 1639 cs->watchpoint_hit = &hw_watchpoint; 1640 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1641 hw_watchpoint.flags = flag; 1642 } 1643 } 1644 } 1645 return handle; 1646 } 1647 1648 static int kvm_handle_singlestep(void) 1649 { 1650 return 1; 1651 } 1652 1653 static int kvm_handle_sw_breakpoint(void) 1654 { 1655 return 1; 1656 } 1657 1658 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1659 { 1660 CPUState *cs = CPU(cpu); 1661 CPUPPCState *env = &cpu->env; 1662 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1663 1664 if (cs->singlestep_enabled) { 1665 return kvm_handle_singlestep(); 1666 } 1667 1668 if (arch_info->status) { 1669 return kvm_handle_hw_breakpoint(cs, arch_info); 1670 } 1671 1672 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1673 return kvm_handle_sw_breakpoint(); 1674 } 1675 1676 /* 1677 * QEMU is not able to handle debug exception, so inject 1678 * program exception to guest; 1679 * Yes program exception NOT debug exception !! 1680 * When QEMU is using debug resources then debug exception must 1681 * be always set. To achieve this we set MSR_DE and also set 1682 * MSRP_DEP so guest cannot change MSR_DE. 1683 * When emulating debug resource for guest we want guest 1684 * to control MSR_DE (enable/disable debug interrupt on need). 1685 * Supporting both configurations are NOT possible. 1686 * So the result is that we cannot share debug resources 1687 * between QEMU and Guest on BOOKE architecture. 1688 * In the current design QEMU gets the priority over guest, 1689 * this means that if QEMU is using debug resources then guest 1690 * cannot use them; 1691 * For software breakpoint QEMU uses a privileged instruction; 1692 * So there cannot be any reason that we are here for guest 1693 * set debug exception, only possibility is guest executed a 1694 * privileged / illegal instruction and that's why we are 1695 * injecting a program interrupt. 1696 */ 1697 cpu_synchronize_state(cs); 1698 /* 1699 * env->nip is PC, so increment this by 4 to use 1700 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1701 */ 1702 env->nip += 4; 1703 cs->exception_index = POWERPC_EXCP_PROGRAM; 1704 env->error_code = POWERPC_EXCP_INVAL; 1705 ppc_cpu_do_interrupt(cs); 1706 1707 return 0; 1708 } 1709 1710 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1711 { 1712 PowerPCCPU *cpu = POWERPC_CPU(cs); 1713 CPUPPCState *env = &cpu->env; 1714 int ret; 1715 1716 qemu_mutex_lock_iothread(); 1717 1718 switch (run->exit_reason) { 1719 case KVM_EXIT_DCR: 1720 if (run->dcr.is_write) { 1721 trace_kvm_handle_dcr_write(); 1722 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1723 } else { 1724 trace_kvm_handle_drc_read(); 1725 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1726 } 1727 break; 1728 case KVM_EXIT_HLT: 1729 trace_kvm_handle_halt(); 1730 ret = kvmppc_handle_halt(cpu); 1731 break; 1732 #if defined(TARGET_PPC64) 1733 case KVM_EXIT_PAPR_HCALL: 1734 trace_kvm_handle_papr_hcall(); 1735 run->papr_hcall.ret = spapr_hypercall(cpu, 1736 run->papr_hcall.nr, 1737 run->papr_hcall.args); 1738 ret = 0; 1739 break; 1740 #endif 1741 case KVM_EXIT_EPR: 1742 trace_kvm_handle_epr(); 1743 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1744 ret = 0; 1745 break; 1746 case KVM_EXIT_WATCHDOG: 1747 trace_kvm_handle_watchdog_expiry(); 1748 watchdog_perform_action(); 1749 ret = 0; 1750 break; 1751 1752 case KVM_EXIT_DEBUG: 1753 trace_kvm_handle_debug_exception(); 1754 if (kvm_handle_debug(cpu, run)) { 1755 ret = EXCP_DEBUG; 1756 break; 1757 } 1758 /* re-enter, this exception was guest-internal */ 1759 ret = 0; 1760 break; 1761 1762 default: 1763 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1764 ret = -1; 1765 break; 1766 } 1767 1768 qemu_mutex_unlock_iothread(); 1769 return ret; 1770 } 1771 1772 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1773 { 1774 CPUState *cs = CPU(cpu); 1775 uint32_t bits = tsr_bits; 1776 struct kvm_one_reg reg = { 1777 .id = KVM_REG_PPC_OR_TSR, 1778 .addr = (uintptr_t) &bits, 1779 }; 1780 1781 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1782 } 1783 1784 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1785 { 1786 1787 CPUState *cs = CPU(cpu); 1788 uint32_t bits = tsr_bits; 1789 struct kvm_one_reg reg = { 1790 .id = KVM_REG_PPC_CLEAR_TSR, 1791 .addr = (uintptr_t) &bits, 1792 }; 1793 1794 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1795 } 1796 1797 int kvmppc_set_tcr(PowerPCCPU *cpu) 1798 { 1799 CPUState *cs = CPU(cpu); 1800 CPUPPCState *env = &cpu->env; 1801 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1802 1803 struct kvm_one_reg reg = { 1804 .id = KVM_REG_PPC_TCR, 1805 .addr = (uintptr_t) &tcr, 1806 }; 1807 1808 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1809 } 1810 1811 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1812 { 1813 CPUState *cs = CPU(cpu); 1814 int ret; 1815 1816 if (!kvm_enabled()) { 1817 return -1; 1818 } 1819 1820 if (!cap_ppc_watchdog) { 1821 printf("warning: KVM does not support watchdog"); 1822 return -1; 1823 } 1824 1825 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1826 if (ret < 0) { 1827 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1828 __func__, strerror(-ret)); 1829 return ret; 1830 } 1831 1832 return ret; 1833 } 1834 1835 static int read_cpuinfo(const char *field, char *value, int len) 1836 { 1837 FILE *f; 1838 int ret = -1; 1839 int field_len = strlen(field); 1840 char line[512]; 1841 1842 f = fopen("/proc/cpuinfo", "r"); 1843 if (!f) { 1844 return -1; 1845 } 1846 1847 do { 1848 if (!fgets(line, sizeof(line), f)) { 1849 break; 1850 } 1851 if (!strncmp(line, field, field_len)) { 1852 pstrcpy(value, len, line); 1853 ret = 0; 1854 break; 1855 } 1856 } while (*line); 1857 1858 fclose(f); 1859 1860 return ret; 1861 } 1862 1863 uint32_t kvmppc_get_tbfreq(void) 1864 { 1865 char line[512]; 1866 char *ns; 1867 uint32_t retval = NANOSECONDS_PER_SECOND; 1868 1869 if (read_cpuinfo("timebase", line, sizeof(line))) { 1870 return retval; 1871 } 1872 1873 ns = strchr(line, ':'); 1874 if (!ns) { 1875 return retval; 1876 } 1877 1878 ns++; 1879 1880 return atoi(ns); 1881 } 1882 1883 bool kvmppc_get_host_serial(char **value) 1884 { 1885 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1886 NULL); 1887 } 1888 1889 bool kvmppc_get_host_model(char **value) 1890 { 1891 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1892 } 1893 1894 /* Try to find a device tree node for a CPU with clock-frequency property */ 1895 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1896 { 1897 struct dirent *dirp; 1898 DIR *dp; 1899 1900 dp = opendir(PROC_DEVTREE_CPU); 1901 if (!dp) { 1902 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1903 return -1; 1904 } 1905 1906 buf[0] = '\0'; 1907 while ((dirp = readdir(dp)) != NULL) { 1908 FILE *f; 1909 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1910 dirp->d_name); 1911 f = fopen(buf, "r"); 1912 if (f) { 1913 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1914 fclose(f); 1915 break; 1916 } 1917 buf[0] = '\0'; 1918 } 1919 closedir(dp); 1920 if (buf[0] == '\0') { 1921 printf("Unknown host!\n"); 1922 return -1; 1923 } 1924 1925 return 0; 1926 } 1927 1928 static uint64_t kvmppc_read_int_dt(const char *filename) 1929 { 1930 union { 1931 uint32_t v32; 1932 uint64_t v64; 1933 } u; 1934 FILE *f; 1935 int len; 1936 1937 f = fopen(filename, "rb"); 1938 if (!f) { 1939 return -1; 1940 } 1941 1942 len = fread(&u, 1, sizeof(u), f); 1943 fclose(f); 1944 switch (len) { 1945 case 4: 1946 /* property is a 32-bit quantity */ 1947 return be32_to_cpu(u.v32); 1948 case 8: 1949 return be64_to_cpu(u.v64); 1950 } 1951 1952 return 0; 1953 } 1954 1955 /* 1956 * Read a CPU node property from the host device tree that's a single 1957 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1958 * (can't find or open the property, or doesn't understand the format) 1959 */ 1960 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1961 { 1962 char buf[PATH_MAX], *tmp; 1963 uint64_t val; 1964 1965 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1966 return -1; 1967 } 1968 1969 tmp = g_strdup_printf("%s/%s", buf, propname); 1970 val = kvmppc_read_int_dt(tmp); 1971 g_free(tmp); 1972 1973 return val; 1974 } 1975 1976 uint64_t kvmppc_get_clockfreq(void) 1977 { 1978 return kvmppc_read_int_cpu_dt("clock-frequency"); 1979 } 1980 1981 static int kvmppc_get_dec_bits(void) 1982 { 1983 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1984 1985 if (nr_bits > 0) { 1986 return nr_bits; 1987 } 1988 return 0; 1989 } 1990 1991 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1992 { 1993 PowerPCCPU *cpu = ppc_env_get_cpu(env); 1994 CPUState *cs = CPU(cpu); 1995 1996 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1997 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1998 return 0; 1999 } 2000 2001 return 1; 2002 } 2003 2004 int kvmppc_get_hasidle(CPUPPCState *env) 2005 { 2006 struct kvm_ppc_pvinfo pvinfo; 2007 2008 if (!kvmppc_get_pvinfo(env, &pvinfo) && 2009 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 2010 return 1; 2011 } 2012 2013 return 0; 2014 } 2015 2016 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 2017 { 2018 uint32_t *hc = (uint32_t *)buf; 2019 struct kvm_ppc_pvinfo pvinfo; 2020 2021 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 2022 memcpy(buf, pvinfo.hcall, buf_len); 2023 return 0; 2024 } 2025 2026 /* 2027 * Fallback to always fail hypercalls regardless of endianness: 2028 * 2029 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 2030 * li r3, -1 2031 * b .+8 (becomes nop in wrong endian) 2032 * bswap32(li r3, -1) 2033 */ 2034 2035 hc[0] = cpu_to_be32(0x08000048); 2036 hc[1] = cpu_to_be32(0x3860ffff); 2037 hc[2] = cpu_to_be32(0x48000008); 2038 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2039 2040 return 1; 2041 } 2042 2043 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2044 { 2045 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2046 } 2047 2048 void kvmppc_enable_logical_ci_hcalls(void) 2049 { 2050 /* 2051 * FIXME: it would be nice if we could detect the cases where 2052 * we're using a device which requires the in kernel 2053 * implementation of these hcalls, but the kernel lacks them and 2054 * produce a warning. 2055 */ 2056 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2057 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2058 } 2059 2060 void kvmppc_enable_set_mode_hcall(void) 2061 { 2062 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2063 } 2064 2065 void kvmppc_enable_clear_ref_mod_hcalls(void) 2066 { 2067 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2068 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2069 } 2070 2071 void kvmppc_enable_h_page_init(void) 2072 { 2073 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2074 } 2075 2076 void kvmppc_set_papr(PowerPCCPU *cpu) 2077 { 2078 CPUState *cs = CPU(cpu); 2079 int ret; 2080 2081 if (!kvm_enabled()) { 2082 return; 2083 } 2084 2085 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2086 if (ret) { 2087 error_report("This vCPU type or KVM version does not support PAPR"); 2088 exit(1); 2089 } 2090 2091 /* 2092 * Update the capability flag so we sync the right information 2093 * with kvm 2094 */ 2095 cap_papr = 1; 2096 } 2097 2098 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2099 { 2100 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2101 } 2102 2103 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2104 { 2105 CPUState *cs = CPU(cpu); 2106 int ret; 2107 2108 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2109 if (ret && mpic_proxy) { 2110 error_report("This KVM version does not support EPR"); 2111 exit(1); 2112 } 2113 } 2114 2115 int kvmppc_smt_threads(void) 2116 { 2117 return cap_ppc_smt ? cap_ppc_smt : 1; 2118 } 2119 2120 int kvmppc_set_smt_threads(int smt) 2121 { 2122 int ret; 2123 2124 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2125 if (!ret) { 2126 cap_ppc_smt = smt; 2127 } 2128 return ret; 2129 } 2130 2131 void kvmppc_hint_smt_possible(Error **errp) 2132 { 2133 int i; 2134 GString *g; 2135 char *s; 2136 2137 assert(kvm_enabled()); 2138 if (cap_ppc_smt_possible) { 2139 g = g_string_new("Available VSMT modes:"); 2140 for (i = 63; i >= 0; i--) { 2141 if ((1UL << i) & cap_ppc_smt_possible) { 2142 g_string_append_printf(g, " %lu", (1UL << i)); 2143 } 2144 } 2145 s = g_string_free(g, false); 2146 error_append_hint(errp, "%s.\n", s); 2147 g_free(s); 2148 } else { 2149 error_append_hint(errp, 2150 "This KVM seems to be too old to support VSMT.\n"); 2151 } 2152 } 2153 2154 2155 #ifdef TARGET_PPC64 2156 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) 2157 { 2158 struct kvm_ppc_smmu_info info; 2159 long rampagesize, best_page_shift; 2160 int i; 2161 2162 /* 2163 * Find the largest hardware supported page size that's less than 2164 * or equal to the (logical) backing page size of guest RAM 2165 */ 2166 kvm_get_smmu_info(&info, &error_fatal); 2167 rampagesize = qemu_minrampagesize(); 2168 best_page_shift = 0; 2169 2170 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2171 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2172 2173 if (!sps->page_shift) { 2174 continue; 2175 } 2176 2177 if ((sps->page_shift > best_page_shift) 2178 && ((1UL << sps->page_shift) <= rampagesize)) { 2179 best_page_shift = sps->page_shift; 2180 } 2181 } 2182 2183 return MIN(current_size, 2184 1ULL << (best_page_shift + hash_shift - 7)); 2185 } 2186 #endif 2187 2188 bool kvmppc_spapr_use_multitce(void) 2189 { 2190 return cap_spapr_multitce; 2191 } 2192 2193 int kvmppc_spapr_enable_inkernel_multitce(void) 2194 { 2195 int ret; 2196 2197 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2198 H_PUT_TCE_INDIRECT, 1); 2199 if (!ret) { 2200 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2201 H_STUFF_TCE, 1); 2202 } 2203 2204 return ret; 2205 } 2206 2207 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2208 uint64_t bus_offset, uint32_t nb_table, 2209 int *pfd, bool need_vfio) 2210 { 2211 long len; 2212 int fd; 2213 void *table; 2214 2215 /* 2216 * Must set fd to -1 so we don't try to munmap when called for 2217 * destroying the table, which the upper layers -will- do 2218 */ 2219 *pfd = -1; 2220 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2221 return NULL; 2222 } 2223 2224 if (cap_spapr_tce_64) { 2225 struct kvm_create_spapr_tce_64 args = { 2226 .liobn = liobn, 2227 .page_shift = page_shift, 2228 .offset = bus_offset >> page_shift, 2229 .size = nb_table, 2230 .flags = 0 2231 }; 2232 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2233 if (fd < 0) { 2234 fprintf(stderr, 2235 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2236 liobn); 2237 return NULL; 2238 } 2239 } else if (cap_spapr_tce) { 2240 uint64_t window_size = (uint64_t) nb_table << page_shift; 2241 struct kvm_create_spapr_tce args = { 2242 .liobn = liobn, 2243 .window_size = window_size, 2244 }; 2245 if ((window_size != args.window_size) || bus_offset) { 2246 return NULL; 2247 } 2248 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2249 if (fd < 0) { 2250 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2251 liobn); 2252 return NULL; 2253 } 2254 } else { 2255 return NULL; 2256 } 2257 2258 len = nb_table * sizeof(uint64_t); 2259 /* FIXME: round this up to page size */ 2260 2261 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2262 if (table == MAP_FAILED) { 2263 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2264 liobn); 2265 close(fd); 2266 return NULL; 2267 } 2268 2269 *pfd = fd; 2270 return table; 2271 } 2272 2273 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2274 { 2275 long len; 2276 2277 if (fd < 0) { 2278 return -1; 2279 } 2280 2281 len = nb_table * sizeof(uint64_t); 2282 if ((munmap(table, len) < 0) || 2283 (close(fd) < 0)) { 2284 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2285 strerror(errno)); 2286 /* Leak the table */ 2287 } 2288 2289 return 0; 2290 } 2291 2292 int kvmppc_reset_htab(int shift_hint) 2293 { 2294 uint32_t shift = shift_hint; 2295 2296 if (!kvm_enabled()) { 2297 /* Full emulation, tell caller to allocate htab itself */ 2298 return 0; 2299 } 2300 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2301 int ret; 2302 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2303 if (ret == -ENOTTY) { 2304 /* 2305 * At least some versions of PR KVM advertise the 2306 * capability, but don't implement the ioctl(). Oops. 2307 * Return 0 so that we allocate the htab in qemu, as is 2308 * correct for PR. 2309 */ 2310 return 0; 2311 } else if (ret < 0) { 2312 return ret; 2313 } 2314 return shift; 2315 } 2316 2317 /* 2318 * We have a kernel that predates the htab reset calls. For PR 2319 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2320 * this era, it has allocated a 16MB fixed size hash table 2321 * already. 2322 */ 2323 if (kvmppc_is_pr(kvm_state)) { 2324 /* PR - tell caller to allocate htab */ 2325 return 0; 2326 } else { 2327 /* HV - assume 16MB kernel allocated htab */ 2328 return 24; 2329 } 2330 } 2331 2332 static inline uint32_t mfpvr(void) 2333 { 2334 uint32_t pvr; 2335 2336 asm ("mfpvr %0" 2337 : "=r"(pvr)); 2338 return pvr; 2339 } 2340 2341 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2342 { 2343 if (on) { 2344 *word |= flags; 2345 } else { 2346 *word &= ~flags; 2347 } 2348 } 2349 2350 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2351 { 2352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2353 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2354 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2355 2356 /* Now fix up the class with information we can query from the host */ 2357 pcc->pvr = mfpvr(); 2358 2359 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2360 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2361 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2362 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2363 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2364 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2365 2366 if (dcache_size != -1) { 2367 pcc->l1_dcache_size = dcache_size; 2368 } 2369 2370 if (icache_size != -1) { 2371 pcc->l1_icache_size = icache_size; 2372 } 2373 2374 #if defined(TARGET_PPC64) 2375 pcc->radix_page_info = kvm_get_radix_page_info(); 2376 2377 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2378 /* 2379 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2380 * compliant. More importantly, advertising ISA 3.00 2381 * architected mode may prevent guests from activating 2382 * necessary DD1 workarounds. 2383 */ 2384 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2385 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2386 } 2387 #endif /* defined(TARGET_PPC64) */ 2388 } 2389 2390 bool kvmppc_has_cap_epr(void) 2391 { 2392 return cap_epr; 2393 } 2394 2395 bool kvmppc_has_cap_fixup_hcalls(void) 2396 { 2397 return cap_fixup_hcalls; 2398 } 2399 2400 bool kvmppc_has_cap_htm(void) 2401 { 2402 return cap_htm; 2403 } 2404 2405 bool kvmppc_has_cap_mmu_radix(void) 2406 { 2407 return cap_mmu_radix; 2408 } 2409 2410 bool kvmppc_has_cap_mmu_hash_v3(void) 2411 { 2412 return cap_mmu_hash_v3; 2413 } 2414 2415 static bool kvmppc_power8_host(void) 2416 { 2417 bool ret = false; 2418 #ifdef TARGET_PPC64 2419 { 2420 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2421 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2422 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2423 (base_pvr == CPU_POWERPC_POWER8_BASE); 2424 } 2425 #endif /* TARGET_PPC64 */ 2426 return ret; 2427 } 2428 2429 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2430 { 2431 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2432 2433 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2434 return 2; 2435 } else if ((!l1d_thread_priv_req || 2436 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2437 (c.character & c.character_mask 2438 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2439 return 1; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2446 { 2447 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2448 return 2; 2449 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2450 return 1; 2451 } 2452 2453 return 0; 2454 } 2455 2456 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2457 { 2458 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2459 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2460 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2461 return SPAPR_CAP_FIXED_NA; 2462 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2463 return SPAPR_CAP_WORKAROUND; 2464 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2465 return SPAPR_CAP_FIXED_CCD; 2466 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2467 return SPAPR_CAP_FIXED_IBS; 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2474 { 2475 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2476 return 1; 2477 } 2478 return 0; 2479 } 2480 2481 static void kvmppc_get_cpu_characteristics(KVMState *s) 2482 { 2483 struct kvm_ppc_cpu_char c; 2484 int ret; 2485 2486 /* Assume broken */ 2487 cap_ppc_safe_cache = 0; 2488 cap_ppc_safe_bounds_check = 0; 2489 cap_ppc_safe_indirect_branch = 0; 2490 2491 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2492 if (!ret) { 2493 return; 2494 } 2495 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2496 if (ret < 0) { 2497 return; 2498 } 2499 2500 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2501 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2502 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2503 cap_ppc_count_cache_flush_assist = 2504 parse_cap_ppc_count_cache_flush_assist(c); 2505 } 2506 2507 int kvmppc_get_cap_safe_cache(void) 2508 { 2509 return cap_ppc_safe_cache; 2510 } 2511 2512 int kvmppc_get_cap_safe_bounds_check(void) 2513 { 2514 return cap_ppc_safe_bounds_check; 2515 } 2516 2517 int kvmppc_get_cap_safe_indirect_branch(void) 2518 { 2519 return cap_ppc_safe_indirect_branch; 2520 } 2521 2522 int kvmppc_get_cap_count_cache_flush_assist(void) 2523 { 2524 return cap_ppc_count_cache_flush_assist; 2525 } 2526 2527 bool kvmppc_has_cap_nested_kvm_hv(void) 2528 { 2529 return !!cap_ppc_nested_kvm_hv; 2530 } 2531 2532 int kvmppc_set_cap_nested_kvm_hv(int enable) 2533 { 2534 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2535 } 2536 2537 bool kvmppc_has_cap_spapr_vfio(void) 2538 { 2539 return cap_spapr_vfio; 2540 } 2541 2542 int kvmppc_get_cap_large_decr(void) 2543 { 2544 return cap_large_decr; 2545 } 2546 2547 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2548 { 2549 CPUState *cs = CPU(cpu); 2550 uint64_t lpcr; 2551 2552 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2553 /* Do we need to modify the LPCR? */ 2554 if (!!(lpcr & LPCR_LD) != !!enable) { 2555 if (enable) { 2556 lpcr |= LPCR_LD; 2557 } else { 2558 lpcr &= ~LPCR_LD; 2559 } 2560 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2561 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2562 2563 if (!!(lpcr & LPCR_LD) != !!enable) { 2564 return -1; 2565 } 2566 } 2567 2568 return 0; 2569 } 2570 2571 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2572 { 2573 uint32_t host_pvr = mfpvr(); 2574 PowerPCCPUClass *pvr_pcc; 2575 2576 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2577 if (pvr_pcc == NULL) { 2578 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2579 } 2580 2581 return pvr_pcc; 2582 } 2583 2584 static int kvm_ppc_register_host_cpu_type(MachineState *ms) 2585 { 2586 TypeInfo type_info = { 2587 .name = TYPE_HOST_POWERPC_CPU, 2588 .class_init = kvmppc_host_cpu_class_init, 2589 }; 2590 MachineClass *mc = MACHINE_GET_CLASS(ms); 2591 PowerPCCPUClass *pvr_pcc; 2592 ObjectClass *oc; 2593 DeviceClass *dc; 2594 int i; 2595 2596 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2597 if (pvr_pcc == NULL) { 2598 return -1; 2599 } 2600 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2601 type_register(&type_info); 2602 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) { 2603 /* override TCG default cpu type with 'host' cpu model */ 2604 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2605 } 2606 2607 oc = object_class_by_name(type_info.name); 2608 g_assert(oc); 2609 2610 /* 2611 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2612 * we want "POWER8" to be a "family" alias that points to the current 2613 * host CPU type, too) 2614 */ 2615 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2616 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2617 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2618 char *suffix; 2619 2620 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2621 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2622 if (suffix) { 2623 *suffix = 0; 2624 } 2625 break; 2626 } 2627 } 2628 2629 return 0; 2630 } 2631 2632 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2633 { 2634 struct kvm_rtas_token_args args = { 2635 .token = token, 2636 }; 2637 2638 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2639 return -ENOENT; 2640 } 2641 2642 strncpy(args.name, function, sizeof(args.name)); 2643 2644 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2645 } 2646 2647 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2648 { 2649 struct kvm_get_htab_fd s = { 2650 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2651 .start_index = index, 2652 }; 2653 int ret; 2654 2655 if (!cap_htab_fd) { 2656 error_setg(errp, "KVM version doesn't support %s the HPT", 2657 write ? "writing" : "reading"); 2658 return -ENOTSUP; 2659 } 2660 2661 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2662 if (ret < 0) { 2663 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2664 write ? "writing" : "reading", write ? "to" : "from", 2665 strerror(errno)); 2666 return -errno; 2667 } 2668 2669 return ret; 2670 } 2671 2672 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2673 { 2674 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2675 uint8_t buf[bufsize]; 2676 ssize_t rc; 2677 2678 do { 2679 rc = read(fd, buf, bufsize); 2680 if (rc < 0) { 2681 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2682 strerror(errno)); 2683 return rc; 2684 } else if (rc) { 2685 uint8_t *buffer = buf; 2686 ssize_t n = rc; 2687 while (n) { 2688 struct kvm_get_htab_header *head = 2689 (struct kvm_get_htab_header *) buffer; 2690 size_t chunksize = sizeof(*head) + 2691 HASH_PTE_SIZE_64 * head->n_valid; 2692 2693 qemu_put_be32(f, head->index); 2694 qemu_put_be16(f, head->n_valid); 2695 qemu_put_be16(f, head->n_invalid); 2696 qemu_put_buffer(f, (void *)(head + 1), 2697 HASH_PTE_SIZE_64 * head->n_valid); 2698 2699 buffer += chunksize; 2700 n -= chunksize; 2701 } 2702 } 2703 } while ((rc != 0) 2704 && ((max_ns < 0) || 2705 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2706 2707 return (rc == 0) ? 1 : 0; 2708 } 2709 2710 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2711 uint16_t n_valid, uint16_t n_invalid) 2712 { 2713 struct kvm_get_htab_header *buf; 2714 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2715 ssize_t rc; 2716 2717 buf = alloca(chunksize); 2718 buf->index = index; 2719 buf->n_valid = n_valid; 2720 buf->n_invalid = n_invalid; 2721 2722 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2723 2724 rc = write(fd, buf, chunksize); 2725 if (rc < 0) { 2726 fprintf(stderr, "Error writing KVM hash table: %s\n", 2727 strerror(errno)); 2728 return rc; 2729 } 2730 if (rc != chunksize) { 2731 /* We should never get a short write on a single chunk */ 2732 fprintf(stderr, "Short write, restoring KVM hash table\n"); 2733 return -1; 2734 } 2735 return 0; 2736 } 2737 2738 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2739 { 2740 return true; 2741 } 2742 2743 void kvm_arch_init_irq_routing(KVMState *s) 2744 { 2745 } 2746 2747 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2748 { 2749 int fd, rc; 2750 int i; 2751 2752 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2753 2754 i = 0; 2755 while (i < n) { 2756 struct kvm_get_htab_header *hdr; 2757 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2758 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2759 2760 rc = read(fd, buf, sizeof(buf)); 2761 if (rc < 0) { 2762 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2763 } 2764 2765 hdr = (struct kvm_get_htab_header *)buf; 2766 while ((i < n) && ((char *)hdr < (buf + rc))) { 2767 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2768 2769 if (hdr->index != (ptex + i)) { 2770 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2771 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2772 } 2773 2774 if (n - i < valid) { 2775 valid = n - i; 2776 } 2777 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2778 i += valid; 2779 2780 if ((n - i) < invalid) { 2781 invalid = n - i; 2782 } 2783 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2784 i += invalid; 2785 2786 hdr = (struct kvm_get_htab_header *) 2787 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2788 } 2789 } 2790 2791 close(fd); 2792 } 2793 2794 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2795 { 2796 int fd, rc; 2797 struct { 2798 struct kvm_get_htab_header hdr; 2799 uint64_t pte0; 2800 uint64_t pte1; 2801 } buf; 2802 2803 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2804 2805 buf.hdr.n_valid = 1; 2806 buf.hdr.n_invalid = 0; 2807 buf.hdr.index = ptex; 2808 buf.pte0 = cpu_to_be64(pte0); 2809 buf.pte1 = cpu_to_be64(pte1); 2810 2811 rc = write(fd, &buf, sizeof(buf)); 2812 if (rc != sizeof(buf)) { 2813 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2814 } 2815 close(fd); 2816 } 2817 2818 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2819 uint64_t address, uint32_t data, PCIDevice *dev) 2820 { 2821 return 0; 2822 } 2823 2824 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2825 int vector, PCIDevice *dev) 2826 { 2827 return 0; 2828 } 2829 2830 int kvm_arch_release_virq_post(int virq) 2831 { 2832 return 0; 2833 } 2834 2835 int kvm_arch_msi_data_to_gsi(uint32_t data) 2836 { 2837 return data & 0xffff; 2838 } 2839 2840 int kvmppc_enable_hwrng(void) 2841 { 2842 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2843 return -1; 2844 } 2845 2846 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2847 } 2848 2849 void kvmppc_check_papr_resize_hpt(Error **errp) 2850 { 2851 if (!kvm_enabled()) { 2852 return; /* No KVM, we're good */ 2853 } 2854 2855 if (cap_resize_hpt) { 2856 return; /* Kernel has explicit support, we're good */ 2857 } 2858 2859 /* Otherwise fallback on looking for PR KVM */ 2860 if (kvmppc_is_pr(kvm_state)) { 2861 return; 2862 } 2863 2864 error_setg(errp, 2865 "Hash page table resizing not available with this KVM version"); 2866 } 2867 2868 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2869 { 2870 CPUState *cs = CPU(cpu); 2871 struct kvm_ppc_resize_hpt rhpt = { 2872 .flags = flags, 2873 .shift = shift, 2874 }; 2875 2876 if (!cap_resize_hpt) { 2877 return -ENOSYS; 2878 } 2879 2880 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2881 } 2882 2883 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2884 { 2885 CPUState *cs = CPU(cpu); 2886 struct kvm_ppc_resize_hpt rhpt = { 2887 .flags = flags, 2888 .shift = shift, 2889 }; 2890 2891 if (!cap_resize_hpt) { 2892 return -ENOSYS; 2893 } 2894 2895 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2896 } 2897 2898 /* 2899 * This is a helper function to detect a post migration scenario 2900 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2901 * the guest kernel can't handle a PVR value other than the actual host 2902 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2903 * 2904 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2905 * (so, we're HV), return true. The workaround itself is done in 2906 * cpu_post_load. 2907 * 2908 * The order here is important: we'll only check for KVM PR as a 2909 * fallback if the guest kernel can't handle the situation itself. 2910 * We need to avoid as much as possible querying the running KVM type 2911 * in QEMU level. 2912 */ 2913 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2914 { 2915 CPUState *cs = CPU(cpu); 2916 2917 if (!kvm_enabled()) { 2918 return false; 2919 } 2920 2921 if (cap_ppc_pvr_compat) { 2922 return false; 2923 } 2924 2925 return !kvmppc_is_pr(cs->kvm_state); 2926 } 2927 2928 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2929 { 2930 CPUState *cs = CPU(cpu); 2931 2932 if (kvm_enabled()) { 2933 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2934 } 2935 } 2936