1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "cpu.h" 27 #include "cpu-models.h" 28 #include "qemu/timer.h" 29 #include "sysemu/hw_accel.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "mmu-hash64.h" 34 35 #include "hw/ppc/spapr.h" 36 #include "hw/ppc/spapr_cpu_core.h" 37 #include "hw/hw.h" 38 #include "hw/ppc/ppc.h" 39 #include "migration/qemu-file-types.h" 40 #include "sysemu/watchdog.h" 41 #include "trace.h" 42 #include "exec/gdbstub.h" 43 #include "exec/memattrs.h" 44 #include "exec/ram_addr.h" 45 #include "sysemu/hostmem.h" 46 #include "qemu/cutils.h" 47 #include "qemu/main-loop.h" 48 #include "qemu/mmap-alloc.h" 49 #include "elf.h" 50 #include "sysemu/kvm_int.h" 51 52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 53 54 #define DEBUG_RETURN_GUEST 0 55 #define DEBUG_RETURN_GDB 1 56 57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 58 KVM_CAP_LAST_INFO 59 }; 60 61 static int cap_interrupt_unset; 62 static int cap_segstate; 63 static int cap_booke_sregs; 64 static int cap_ppc_smt; 65 static int cap_ppc_smt_possible; 66 static int cap_spapr_tce; 67 static int cap_spapr_tce_64; 68 static int cap_spapr_multitce; 69 static int cap_spapr_vfio; 70 static int cap_hior; 71 static int cap_one_reg; 72 static int cap_epr; 73 static int cap_ppc_watchdog; 74 static int cap_papr; 75 static int cap_htab_fd; 76 static int cap_fixup_hcalls; 77 static int cap_htm; /* Hardware transactional memory support */ 78 static int cap_mmu_radix; 79 static int cap_mmu_hash_v3; 80 static int cap_xive; 81 static int cap_resize_hpt; 82 static int cap_ppc_pvr_compat; 83 static int cap_ppc_safe_cache; 84 static int cap_ppc_safe_bounds_check; 85 static int cap_ppc_safe_indirect_branch; 86 static int cap_ppc_count_cache_flush_assist; 87 static int cap_ppc_nested_kvm_hv; 88 static int cap_large_decr; 89 static int cap_fwnmi; 90 static int cap_rpt_invalidate; 91 static int cap_ail_mode_3; 92 93 static uint32_t debug_inst_opcode; 94 95 /* 96 * Check whether we are running with KVM-PR (instead of KVM-HV). This 97 * should only be used for fallback tests - generally we should use 98 * explicit capabilities for the features we want, rather than 99 * assuming what is/isn't available depending on the KVM variant. 100 */ 101 static bool kvmppc_is_pr(KVMState *ks) 102 { 103 /* Assume KVM-PR if the GET_PVINFO capability is available */ 104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 105 } 106 107 static int kvm_ppc_register_host_cpu_type(void); 108 static void kvmppc_get_cpu_characteristics(KVMState *s); 109 static int kvmppc_get_dec_bits(void); 110 111 int kvm_arch_get_default_type(MachineState *ms) 112 { 113 return 0; 114 } 115 116 int kvm_arch_init(MachineState *ms, KVMState *s) 117 { 118 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 119 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 120 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 121 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 122 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 123 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 124 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 125 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 126 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 127 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 128 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 129 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 130 /* 131 * Note: we don't set cap_papr here, because this capability is 132 * only activated after this by kvmppc_set_papr() 133 */ 134 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 135 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 136 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 137 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 138 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 139 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 140 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 141 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 142 kvmppc_get_cpu_characteristics(s); 143 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 144 cap_large_decr = kvmppc_get_dec_bits(); 145 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI); 146 /* 147 * Note: setting it to false because there is not such capability 148 * in KVM at this moment. 149 * 150 * TODO: call kvm_vm_check_extension() with the right capability 151 * after the kernel starts implementing it. 152 */ 153 cap_ppc_pvr_compat = false; 154 155 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 156 error_report("KVM: Host kernel doesn't have level irq capability"); 157 exit(1); 158 } 159 160 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE); 161 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3); 162 kvm_ppc_register_host_cpu_type(); 163 164 return 0; 165 } 166 167 int kvm_arch_irqchip_create(KVMState *s) 168 { 169 return 0; 170 } 171 172 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 173 { 174 CPUPPCState *cenv = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 struct kvm_sregs sregs; 177 int ret; 178 179 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 180 /* 181 * What we're really trying to say is "if we're on BookE, we 182 * use the native PVR for now". This is the only sane way to 183 * check it though, so we potentially confuse users that they 184 * can run BookE guests on BookS. Let's hope nobody dares 185 * enough :) 186 */ 187 return 0; 188 } else { 189 if (!cap_segstate) { 190 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 191 return -ENOSYS; 192 } 193 } 194 195 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 196 if (ret) { 197 return ret; 198 } 199 200 sregs.pvr = cenv->spr[SPR_PVR]; 201 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 202 } 203 204 /* Set up a shared TLB array with KVM */ 205 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 206 { 207 CPUPPCState *env = &cpu->env; 208 CPUState *cs = CPU(cpu); 209 struct kvm_book3e_206_tlb_params params = {}; 210 struct kvm_config_tlb cfg = {}; 211 unsigned int entries = 0; 212 int ret, i; 213 214 if (!kvm_enabled() || 215 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 216 return 0; 217 } 218 219 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 220 221 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 222 params.tlb_sizes[i] = booke206_tlb_size(env, i); 223 params.tlb_ways[i] = booke206_tlb_ways(env, i); 224 entries += params.tlb_sizes[i]; 225 } 226 227 assert(entries == env->nb_tlb); 228 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 229 230 env->tlb_dirty = true; 231 232 cfg.array = (uintptr_t)env->tlb.tlbm; 233 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 234 cfg.params = (uintptr_t)¶ms; 235 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 236 237 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 238 if (ret < 0) { 239 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 240 __func__, strerror(-ret)); 241 return ret; 242 } 243 244 env->kvm_sw_tlb = true; 245 return 0; 246 } 247 248 249 #if defined(TARGET_PPC64) 250 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 251 { 252 int ret; 253 254 assert(kvm_state != NULL); 255 256 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 257 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 258 error_append_hint(errp, "Consider switching to a newer KVM\n"); 259 return; 260 } 261 262 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 263 if (ret == 0) { 264 return; 265 } 266 267 error_setg_errno(errp, -ret, 268 "KVM failed to provide the MMU features it supports"); 269 } 270 271 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 272 { 273 KVMState *s = KVM_STATE(current_accel()); 274 struct ppc_radix_page_info *radix_page_info; 275 struct kvm_ppc_rmmu_info rmmu_info = { }; 276 int i; 277 278 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 279 return NULL; 280 } 281 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 282 return NULL; 283 } 284 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 285 radix_page_info->count = 0; 286 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 287 if (rmmu_info.ap_encodings[i]) { 288 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 289 radix_page_info->count++; 290 } 291 } 292 return radix_page_info; 293 } 294 295 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 296 bool radix, bool gtse, 297 uint64_t proc_tbl) 298 { 299 CPUState *cs = CPU(cpu); 300 int ret; 301 uint64_t flags = 0; 302 struct kvm_ppc_mmuv3_cfg cfg = { 303 .process_table = proc_tbl, 304 }; 305 306 if (radix) { 307 flags |= KVM_PPC_MMUV3_RADIX; 308 } 309 if (gtse) { 310 flags |= KVM_PPC_MMUV3_GTSE; 311 } 312 cfg.flags = flags; 313 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 314 switch (ret) { 315 case 0: 316 return H_SUCCESS; 317 case -EINVAL: 318 return H_PARAMETER; 319 case -ENODEV: 320 return H_NOT_AVAILABLE; 321 default: 322 return H_HARDWARE; 323 } 324 } 325 326 bool kvmppc_hpt_needs_host_contiguous_pages(void) 327 { 328 static struct kvm_ppc_smmu_info smmu_info; 329 330 if (!kvm_enabled()) { 331 return false; 332 } 333 334 kvm_get_smmu_info(&smmu_info, &error_fatal); 335 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 336 } 337 338 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 339 { 340 struct kvm_ppc_smmu_info smmu_info; 341 int iq, ik, jq, jk; 342 Error *local_err = NULL; 343 344 /* For now, we only have anything to check on hash64 MMUs */ 345 if (!cpu->hash64_opts || !kvm_enabled()) { 346 return; 347 } 348 349 kvm_get_smmu_info(&smmu_info, &local_err); 350 if (local_err) { 351 error_propagate(errp, local_err); 352 return; 353 } 354 355 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 356 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 357 error_setg(errp, 358 "KVM does not support 1TiB segments which guest expects"); 359 return; 360 } 361 362 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 363 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 364 smmu_info.slb_size, cpu->hash64_opts->slb_size); 365 return; 366 } 367 368 /* 369 * Verify that every pagesize supported by the cpu model is 370 * supported by KVM with the same encodings 371 */ 372 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 373 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 374 struct kvm_ppc_one_seg_page_size *ksps; 375 376 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 377 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 378 break; 379 } 380 } 381 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 382 error_setg(errp, "KVM doesn't support for base page shift %u", 383 qsps->page_shift); 384 return; 385 } 386 387 ksps = &smmu_info.sps[ik]; 388 if (ksps->slb_enc != qsps->slb_enc) { 389 error_setg(errp, 390 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 391 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 392 return; 393 } 394 395 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 396 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 397 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 398 break; 399 } 400 } 401 402 if (jk >= ARRAY_SIZE(ksps->enc)) { 403 error_setg(errp, "KVM doesn't support page shift %u/%u", 404 qsps->enc[jq].page_shift, qsps->page_shift); 405 return; 406 } 407 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 408 error_setg(errp, 409 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 410 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 411 qsps->page_shift, qsps->enc[jq].pte_enc); 412 return; 413 } 414 } 415 } 416 417 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 418 /* 419 * Mostly what guest pagesizes we can use are related to the 420 * host pages used to map guest RAM, which is handled in the 421 * platform code. Cache-Inhibited largepages (64k) however are 422 * used for I/O, so if they're mapped to the host at all it 423 * will be a normal mapping, not a special hugepage one used 424 * for RAM. 425 */ 426 if (qemu_real_host_page_size() < 0x10000) { 427 error_setg(errp, 428 "KVM can't supply 64kiB CI pages, which guest expects"); 429 } 430 } 431 } 432 #endif /* !defined (TARGET_PPC64) */ 433 434 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 435 { 436 return POWERPC_CPU(cpu)->vcpu_id; 437 } 438 439 /* 440 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 441 * only 1 watchpoint, so array size of 4 is sufficient for now. 442 */ 443 #define MAX_HW_BKPTS 4 444 445 static struct HWBreakpoint { 446 target_ulong addr; 447 int type; 448 } hw_debug_points[MAX_HW_BKPTS]; 449 450 static CPUWatchpoint hw_watchpoint; 451 452 /* Default there is no breakpoint and watchpoint supported */ 453 static int max_hw_breakpoint; 454 static int max_hw_watchpoint; 455 static int nb_hw_breakpoint; 456 static int nb_hw_watchpoint; 457 458 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 459 { 460 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 461 max_hw_breakpoint = 2; 462 max_hw_watchpoint = 2; 463 } 464 465 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 466 fprintf(stderr, "Error initializing h/w breakpoints\n"); 467 return; 468 } 469 } 470 471 int kvm_arch_init_vcpu(CPUState *cs) 472 { 473 PowerPCCPU *cpu = POWERPC_CPU(cs); 474 CPUPPCState *cenv = &cpu->env; 475 int ret; 476 477 /* Synchronize sregs with kvm */ 478 ret = kvm_arch_sync_sregs(cpu); 479 if (ret) { 480 if (ret == -EINVAL) { 481 error_report("Register sync failed... If you're using kvm-hv.ko," 482 " only \"-cpu host\" is possible"); 483 } 484 return ret; 485 } 486 487 switch (cenv->mmu_model) { 488 case POWERPC_MMU_BOOKE206: 489 /* This target supports access to KVM's guest TLB */ 490 ret = kvm_booke206_tlb_init(cpu); 491 break; 492 case POWERPC_MMU_2_07: 493 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 494 /* 495 * KVM-HV has transactional memory on POWER8 also without 496 * the KVM_CAP_PPC_HTM extension, so enable it here 497 * instead as long as it's available to userspace on the 498 * host. 499 */ 500 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 501 cap_htm = true; 502 } 503 } 504 break; 505 default: 506 break; 507 } 508 509 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 510 kvmppc_hw_debug_points_init(cenv); 511 512 return ret; 513 } 514 515 int kvm_arch_destroy_vcpu(CPUState *cs) 516 { 517 return 0; 518 } 519 520 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 521 { 522 CPUPPCState *env = &cpu->env; 523 CPUState *cs = CPU(cpu); 524 struct kvm_dirty_tlb dirty_tlb; 525 unsigned char *bitmap; 526 int ret; 527 528 if (!env->kvm_sw_tlb) { 529 return; 530 } 531 532 bitmap = g_malloc((env->nb_tlb + 7) / 8); 533 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 534 535 dirty_tlb.bitmap = (uintptr_t)bitmap; 536 dirty_tlb.num_dirty = env->nb_tlb; 537 538 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 539 if (ret) { 540 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 541 __func__, strerror(-ret)); 542 } 543 544 g_free(bitmap); 545 } 546 547 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 548 { 549 PowerPCCPU *cpu = POWERPC_CPU(cs); 550 CPUPPCState *env = &cpu->env; 551 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ 552 union { 553 uint32_t u32; 554 uint64_t u64; 555 } val = { }; 556 struct kvm_one_reg reg = { 557 .id = id, 558 .addr = (uintptr_t) &val, 559 }; 560 int ret; 561 562 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 563 if (ret != 0) { 564 trace_kvm_failed_spr_get(spr, strerror(errno)); 565 } else { 566 switch (id & KVM_REG_SIZE_MASK) { 567 case KVM_REG_SIZE_U32: 568 env->spr[spr] = val.u32; 569 break; 570 571 case KVM_REG_SIZE_U64: 572 env->spr[spr] = val.u64; 573 break; 574 575 default: 576 /* Don't handle this size yet */ 577 abort(); 578 } 579 } 580 } 581 582 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 583 { 584 PowerPCCPU *cpu = POWERPC_CPU(cs); 585 CPUPPCState *env = &cpu->env; 586 union { 587 uint32_t u32; 588 uint64_t u64; 589 } val; 590 struct kvm_one_reg reg = { 591 .id = id, 592 .addr = (uintptr_t) &val, 593 }; 594 int ret; 595 596 switch (id & KVM_REG_SIZE_MASK) { 597 case KVM_REG_SIZE_U32: 598 val.u32 = env->spr[spr]; 599 break; 600 601 case KVM_REG_SIZE_U64: 602 val.u64 = env->spr[spr]; 603 break; 604 605 default: 606 /* Don't handle this size yet */ 607 abort(); 608 } 609 610 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 611 if (ret != 0) { 612 trace_kvm_failed_spr_set(spr, strerror(errno)); 613 } 614 } 615 616 static int kvm_put_fp(CPUState *cs) 617 { 618 PowerPCCPU *cpu = POWERPC_CPU(cs); 619 CPUPPCState *env = &cpu->env; 620 struct kvm_one_reg reg; 621 int i; 622 int ret; 623 624 if (env->insns_flags & PPC_FLOAT) { 625 uint64_t fpscr = env->fpscr; 626 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 627 628 reg.id = KVM_REG_PPC_FPSCR; 629 reg.addr = (uintptr_t)&fpscr; 630 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 631 if (ret < 0) { 632 trace_kvm_failed_fpscr_set(strerror(errno)); 633 return ret; 634 } 635 636 for (i = 0; i < 32; i++) { 637 uint64_t vsr[2]; 638 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 639 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 640 641 #if HOST_BIG_ENDIAN 642 vsr[0] = float64_val(*fpr); 643 vsr[1] = *vsrl; 644 #else 645 vsr[0] = *vsrl; 646 vsr[1] = float64_val(*fpr); 647 #endif 648 reg.addr = (uintptr_t) &vsr; 649 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 650 651 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 652 if (ret < 0) { 653 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 654 strerror(errno)); 655 return ret; 656 } 657 } 658 } 659 660 if (env->insns_flags & PPC_ALTIVEC) { 661 reg.id = KVM_REG_PPC_VSCR; 662 reg.addr = (uintptr_t)&env->vscr; 663 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 664 if (ret < 0) { 665 trace_kvm_failed_vscr_set(strerror(errno)); 666 return ret; 667 } 668 669 for (i = 0; i < 32; i++) { 670 reg.id = KVM_REG_PPC_VR(i); 671 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 672 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 673 if (ret < 0) { 674 trace_kvm_failed_vr_set(i, strerror(errno)); 675 return ret; 676 } 677 } 678 } 679 680 return 0; 681 } 682 683 static int kvm_get_fp(CPUState *cs) 684 { 685 PowerPCCPU *cpu = POWERPC_CPU(cs); 686 CPUPPCState *env = &cpu->env; 687 struct kvm_one_reg reg; 688 int i; 689 int ret; 690 691 if (env->insns_flags & PPC_FLOAT) { 692 uint64_t fpscr; 693 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 694 695 reg.id = KVM_REG_PPC_FPSCR; 696 reg.addr = (uintptr_t)&fpscr; 697 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 698 if (ret < 0) { 699 trace_kvm_failed_fpscr_get(strerror(errno)); 700 return ret; 701 } else { 702 env->fpscr = fpscr; 703 } 704 705 for (i = 0; i < 32; i++) { 706 uint64_t vsr[2]; 707 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 708 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 709 710 reg.addr = (uintptr_t) &vsr; 711 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 712 713 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 714 if (ret < 0) { 715 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 716 strerror(errno)); 717 return ret; 718 } else { 719 #if HOST_BIG_ENDIAN 720 *fpr = vsr[0]; 721 if (vsx) { 722 *vsrl = vsr[1]; 723 } 724 #else 725 *fpr = vsr[1]; 726 if (vsx) { 727 *vsrl = vsr[0]; 728 } 729 #endif 730 } 731 } 732 } 733 734 if (env->insns_flags & PPC_ALTIVEC) { 735 reg.id = KVM_REG_PPC_VSCR; 736 reg.addr = (uintptr_t)&env->vscr; 737 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 738 if (ret < 0) { 739 trace_kvm_failed_vscr_get(strerror(errno)); 740 return ret; 741 } 742 743 for (i = 0; i < 32; i++) { 744 reg.id = KVM_REG_PPC_VR(i); 745 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 746 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 747 if (ret < 0) { 748 trace_kvm_failed_vr_get(i, strerror(errno)); 749 return ret; 750 } 751 } 752 } 753 754 return 0; 755 } 756 757 #if defined(TARGET_PPC64) 758 static int kvm_get_vpa(CPUState *cs) 759 { 760 PowerPCCPU *cpu = POWERPC_CPU(cs); 761 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 762 struct kvm_one_reg reg; 763 int ret; 764 765 reg.id = KVM_REG_PPC_VPA_ADDR; 766 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 767 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 768 if (ret < 0) { 769 trace_kvm_failed_vpa_addr_get(strerror(errno)); 770 return ret; 771 } 772 773 assert((uintptr_t)&spapr_cpu->slb_shadow_size 774 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 775 reg.id = KVM_REG_PPC_VPA_SLB; 776 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 778 if (ret < 0) { 779 trace_kvm_failed_slb_get(strerror(errno)); 780 return ret; 781 } 782 783 assert((uintptr_t)&spapr_cpu->dtl_size 784 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 785 reg.id = KVM_REG_PPC_VPA_DTL; 786 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 787 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 788 if (ret < 0) { 789 trace_kvm_failed_dtl_get(strerror(errno)); 790 return ret; 791 } 792 793 return 0; 794 } 795 796 static int kvm_put_vpa(CPUState *cs) 797 { 798 PowerPCCPU *cpu = POWERPC_CPU(cs); 799 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 800 struct kvm_one_reg reg; 801 int ret; 802 803 /* 804 * SLB shadow or DTL can't be registered unless a master VPA is 805 * registered. That means when restoring state, if a VPA *is* 806 * registered, we need to set that up first. If not, we need to 807 * deregister the others before deregistering the master VPA 808 */ 809 assert(spapr_cpu->vpa_addr 810 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 811 812 if (spapr_cpu->vpa_addr) { 813 reg.id = KVM_REG_PPC_VPA_ADDR; 814 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 815 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 816 if (ret < 0) { 817 trace_kvm_failed_vpa_addr_set(strerror(errno)); 818 return ret; 819 } 820 } 821 822 assert((uintptr_t)&spapr_cpu->slb_shadow_size 823 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 824 reg.id = KVM_REG_PPC_VPA_SLB; 825 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 826 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 827 if (ret < 0) { 828 trace_kvm_failed_slb_set(strerror(errno)); 829 return ret; 830 } 831 832 assert((uintptr_t)&spapr_cpu->dtl_size 833 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 834 reg.id = KVM_REG_PPC_VPA_DTL; 835 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 836 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 837 if (ret < 0) { 838 trace_kvm_failed_dtl_set(strerror(errno)); 839 return ret; 840 } 841 842 if (!spapr_cpu->vpa_addr) { 843 reg.id = KVM_REG_PPC_VPA_ADDR; 844 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 845 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 846 if (ret < 0) { 847 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 848 return ret; 849 } 850 } 851 852 return 0; 853 } 854 #endif /* TARGET_PPC64 */ 855 856 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 857 { 858 CPUPPCState *env = &cpu->env; 859 struct kvm_sregs sregs = { }; 860 int i; 861 862 sregs.pvr = env->spr[SPR_PVR]; 863 864 if (cpu->vhyp) { 865 PPCVirtualHypervisorClass *vhc = 866 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 867 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 868 } else { 869 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 870 } 871 872 /* Sync SLB */ 873 #ifdef TARGET_PPC64 874 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 875 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 876 if (env->slb[i].esid & SLB_ESID_V) { 877 sregs.u.s.ppc64.slb[i].slbe |= i; 878 } 879 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 880 } 881 #endif 882 883 /* Sync SRs */ 884 for (i = 0; i < 16; i++) { 885 sregs.u.s.ppc32.sr[i] = env->sr[i]; 886 } 887 888 /* Sync BATs */ 889 for (i = 0; i < 8; i++) { 890 /* Beware. We have to swap upper and lower bits here */ 891 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 892 | env->DBAT[1][i]; 893 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 894 | env->IBAT[1][i]; 895 } 896 897 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 898 } 899 900 int kvm_arch_put_registers(CPUState *cs, int level) 901 { 902 PowerPCCPU *cpu = POWERPC_CPU(cs); 903 CPUPPCState *env = &cpu->env; 904 struct kvm_regs regs; 905 int ret; 906 int i; 907 908 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 909 if (ret < 0) { 910 return ret; 911 } 912 913 regs.ctr = env->ctr; 914 regs.lr = env->lr; 915 regs.xer = cpu_read_xer(env); 916 regs.msr = env->msr; 917 regs.pc = env->nip; 918 919 regs.srr0 = env->spr[SPR_SRR0]; 920 regs.srr1 = env->spr[SPR_SRR1]; 921 922 regs.sprg0 = env->spr[SPR_SPRG0]; 923 regs.sprg1 = env->spr[SPR_SPRG1]; 924 regs.sprg2 = env->spr[SPR_SPRG2]; 925 regs.sprg3 = env->spr[SPR_SPRG3]; 926 regs.sprg4 = env->spr[SPR_SPRG4]; 927 regs.sprg5 = env->spr[SPR_SPRG5]; 928 regs.sprg6 = env->spr[SPR_SPRG6]; 929 regs.sprg7 = env->spr[SPR_SPRG7]; 930 931 regs.pid = env->spr[SPR_BOOKE_PID]; 932 933 for (i = 0; i < 32; i++) { 934 regs.gpr[i] = env->gpr[i]; 935 } 936 937 regs.cr = ppc_get_cr(env); 938 939 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 940 if (ret < 0) { 941 return ret; 942 } 943 944 kvm_put_fp(cs); 945 946 if (env->tlb_dirty) { 947 kvm_sw_tlb_put(cpu); 948 env->tlb_dirty = false; 949 } 950 951 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 952 ret = kvmppc_put_books_sregs(cpu); 953 if (ret < 0) { 954 return ret; 955 } 956 } 957 958 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 959 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 960 } 961 962 if (cap_one_reg) { 963 int i; 964 965 /* 966 * We deliberately ignore errors here, for kernels which have 967 * the ONE_REG calls, but don't support the specific 968 * registers, there's a reasonable chance things will still 969 * work, at least until we try to migrate. 970 */ 971 for (i = 0; i < 1024; i++) { 972 uint64_t id = env->spr_cb[i].one_reg_id; 973 974 if (id != 0) { 975 kvm_put_one_spr(cs, id, i); 976 } 977 } 978 979 #ifdef TARGET_PPC64 980 if (FIELD_EX64(env->msr, MSR, TS)) { 981 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 983 } 984 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 986 } 987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 996 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 997 } 998 999 if (cap_papr) { 1000 if (kvm_put_vpa(cs) < 0) { 1001 trace_kvm_failed_put_vpa(); 1002 } 1003 } 1004 1005 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1006 1007 if (level > KVM_PUT_RUNTIME_STATE) { 1008 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1009 } 1010 #endif /* TARGET_PPC64 */ 1011 } 1012 1013 return ret; 1014 } 1015 1016 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1017 { 1018 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1019 } 1020 1021 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1022 { 1023 CPUPPCState *env = &cpu->env; 1024 struct kvm_sregs sregs; 1025 int ret; 1026 1027 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1028 if (ret < 0) { 1029 return ret; 1030 } 1031 1032 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1033 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1034 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1035 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1036 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1037 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1038 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1039 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1040 env->spr[SPR_DECR] = sregs.u.e.dec; 1041 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1042 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1043 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1044 } 1045 1046 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1047 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1048 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1049 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1050 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1051 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1052 } 1053 1054 if (sregs.u.e.features & KVM_SREGS_E_64) { 1055 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1056 } 1057 1058 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1059 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1060 } 1061 1062 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1063 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1064 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1065 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1066 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1067 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1068 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1069 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1070 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1071 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1072 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1073 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1074 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1075 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1076 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1077 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1078 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1079 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1080 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1081 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1082 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1083 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1084 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1085 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1086 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1087 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1088 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1089 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1090 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1091 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1092 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1093 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1094 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1095 1096 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1097 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1098 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1099 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1100 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1101 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1102 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1103 } 1104 1105 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1106 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1107 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1108 } 1109 1110 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1111 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1112 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1113 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1114 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1115 } 1116 } 1117 1118 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1119 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1120 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1121 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1122 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1123 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1124 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1125 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1126 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1127 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1128 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1129 } 1130 1131 if (sregs.u.e.features & KVM_SREGS_EXP) { 1132 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1133 } 1134 1135 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1136 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1137 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1138 } 1139 1140 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1141 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1142 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1143 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1144 1145 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1146 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1147 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1148 } 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1155 { 1156 CPUPPCState *env = &cpu->env; 1157 struct kvm_sregs sregs; 1158 int ret; 1159 int i; 1160 1161 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1162 if (ret < 0) { 1163 return ret; 1164 } 1165 1166 if (!cpu->vhyp) { 1167 ppc_store_sdr1(env, sregs.u.s.sdr1); 1168 } 1169 1170 /* Sync SLB */ 1171 #ifdef TARGET_PPC64 1172 /* 1173 * The packed SLB array we get from KVM_GET_SREGS only contains 1174 * information about valid entries. So we flush our internal copy 1175 * to get rid of stale ones, then put all valid SLB entries back 1176 * in. 1177 */ 1178 memset(env->slb, 0, sizeof(env->slb)); 1179 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1180 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1181 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1182 /* 1183 * Only restore valid entries 1184 */ 1185 if (rb & SLB_ESID_V) { 1186 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1187 } 1188 } 1189 #endif 1190 1191 /* Sync SRs */ 1192 for (i = 0; i < 16; i++) { 1193 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1194 } 1195 1196 /* Sync BATs */ 1197 for (i = 0; i < 8; i++) { 1198 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1199 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1200 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1201 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1202 } 1203 1204 return 0; 1205 } 1206 1207 int kvm_arch_get_registers(CPUState *cs) 1208 { 1209 PowerPCCPU *cpu = POWERPC_CPU(cs); 1210 CPUPPCState *env = &cpu->env; 1211 struct kvm_regs regs; 1212 int i, ret; 1213 1214 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1215 if (ret < 0) { 1216 return ret; 1217 } 1218 1219 ppc_set_cr(env, regs.cr); 1220 env->ctr = regs.ctr; 1221 env->lr = regs.lr; 1222 cpu_write_xer(env, regs.xer); 1223 env->msr = regs.msr; 1224 env->nip = regs.pc; 1225 1226 env->spr[SPR_SRR0] = regs.srr0; 1227 env->spr[SPR_SRR1] = regs.srr1; 1228 1229 env->spr[SPR_SPRG0] = regs.sprg0; 1230 env->spr[SPR_SPRG1] = regs.sprg1; 1231 env->spr[SPR_SPRG2] = regs.sprg2; 1232 env->spr[SPR_SPRG3] = regs.sprg3; 1233 env->spr[SPR_SPRG4] = regs.sprg4; 1234 env->spr[SPR_SPRG5] = regs.sprg5; 1235 env->spr[SPR_SPRG6] = regs.sprg6; 1236 env->spr[SPR_SPRG7] = regs.sprg7; 1237 1238 env->spr[SPR_BOOKE_PID] = regs.pid; 1239 1240 for (i = 0; i < 32; i++) { 1241 env->gpr[i] = regs.gpr[i]; 1242 } 1243 1244 kvm_get_fp(cs); 1245 1246 if (cap_booke_sregs) { 1247 ret = kvmppc_get_booke_sregs(cpu); 1248 if (ret < 0) { 1249 return ret; 1250 } 1251 } 1252 1253 if (cap_segstate) { 1254 ret = kvmppc_get_books_sregs(cpu); 1255 if (ret < 0) { 1256 return ret; 1257 } 1258 } 1259 1260 if (cap_hior) { 1261 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1262 } 1263 1264 if (cap_one_reg) { 1265 int i; 1266 1267 /* 1268 * We deliberately ignore errors here, for kernels which have 1269 * the ONE_REG calls, but don't support the specific 1270 * registers, there's a reasonable chance things will still 1271 * work, at least until we try to migrate. 1272 */ 1273 for (i = 0; i < 1024; i++) { 1274 uint64_t id = env->spr_cb[i].one_reg_id; 1275 1276 if (id != 0) { 1277 kvm_get_one_spr(cs, id, i); 1278 } 1279 } 1280 1281 #ifdef TARGET_PPC64 1282 if (FIELD_EX64(env->msr, MSR, TS)) { 1283 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1285 } 1286 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1288 } 1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1299 } 1300 1301 if (cap_papr) { 1302 if (kvm_get_vpa(cs) < 0) { 1303 trace_kvm_failed_get_vpa(); 1304 } 1305 } 1306 1307 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1308 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1309 #endif 1310 } 1311 1312 return 0; 1313 } 1314 1315 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1316 { 1317 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1318 1319 if (irq != PPC_INTERRUPT_EXT) { 1320 return 0; 1321 } 1322 1323 if (!kvm_enabled() || !cap_interrupt_unset) { 1324 return 0; 1325 } 1326 1327 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1328 1329 return 0; 1330 } 1331 1332 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1333 { 1334 return; 1335 } 1336 1337 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1338 { 1339 return MEMTXATTRS_UNSPECIFIED; 1340 } 1341 1342 int kvm_arch_process_async_events(CPUState *cs) 1343 { 1344 return cs->halted; 1345 } 1346 1347 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1348 { 1349 CPUState *cs = CPU(cpu); 1350 CPUPPCState *env = &cpu->env; 1351 1352 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && 1353 FIELD_EX64(env->msr, MSR, EE)) { 1354 cs->halted = 1; 1355 cs->exception_index = EXCP_HLT; 1356 } 1357 1358 return 0; 1359 } 1360 1361 /* map dcr access to existing qemu dcr emulation */ 1362 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1363 uint32_t dcrn, uint32_t *data) 1364 { 1365 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1366 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1373 uint32_t dcrn, uint32_t data) 1374 { 1375 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1376 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1377 } 1378 1379 return 0; 1380 } 1381 1382 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1383 { 1384 /* Mixed endian case is not handled */ 1385 uint32_t sc = debug_inst_opcode; 1386 1387 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1388 sizeof(sc), 0) || 1389 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1390 return -EINVAL; 1391 } 1392 1393 return 0; 1394 } 1395 1396 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1397 { 1398 uint32_t sc; 1399 1400 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1401 sc != debug_inst_opcode || 1402 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1403 sizeof(sc), 1)) { 1404 return -EINVAL; 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int find_hw_breakpoint(target_ulong addr, int type) 1411 { 1412 int n; 1413 1414 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1415 <= ARRAY_SIZE(hw_debug_points)); 1416 1417 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1418 if (hw_debug_points[n].addr == addr && 1419 hw_debug_points[n].type == type) { 1420 return n; 1421 } 1422 } 1423 1424 return -1; 1425 } 1426 1427 static int find_hw_watchpoint(target_ulong addr, int *flag) 1428 { 1429 int n; 1430 1431 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1432 if (n >= 0) { 1433 *flag = BP_MEM_ACCESS; 1434 return n; 1435 } 1436 1437 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1438 if (n >= 0) { 1439 *flag = BP_MEM_WRITE; 1440 return n; 1441 } 1442 1443 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1444 if (n >= 0) { 1445 *flag = BP_MEM_READ; 1446 return n; 1447 } 1448 1449 return -1; 1450 } 1451 1452 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 1453 { 1454 const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint; 1455 if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) { 1456 return -ENOBUFS; 1457 } 1458 1459 hw_debug_points[breakpoint_index].addr = addr; 1460 hw_debug_points[breakpoint_index].type = type; 1461 1462 switch (type) { 1463 case GDB_BREAKPOINT_HW: 1464 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1465 return -ENOBUFS; 1466 } 1467 1468 if (find_hw_breakpoint(addr, type) >= 0) { 1469 return -EEXIST; 1470 } 1471 1472 nb_hw_breakpoint++; 1473 break; 1474 1475 case GDB_WATCHPOINT_WRITE: 1476 case GDB_WATCHPOINT_READ: 1477 case GDB_WATCHPOINT_ACCESS: 1478 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1479 return -ENOBUFS; 1480 } 1481 1482 if (find_hw_breakpoint(addr, type) >= 0) { 1483 return -EEXIST; 1484 } 1485 1486 nb_hw_watchpoint++; 1487 break; 1488 1489 default: 1490 return -ENOSYS; 1491 } 1492 1493 return 0; 1494 } 1495 1496 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 1497 { 1498 int n; 1499 1500 n = find_hw_breakpoint(addr, type); 1501 if (n < 0) { 1502 return -ENOENT; 1503 } 1504 1505 switch (type) { 1506 case GDB_BREAKPOINT_HW: 1507 nb_hw_breakpoint--; 1508 break; 1509 1510 case GDB_WATCHPOINT_WRITE: 1511 case GDB_WATCHPOINT_READ: 1512 case GDB_WATCHPOINT_ACCESS: 1513 nb_hw_watchpoint--; 1514 break; 1515 1516 default: 1517 return -ENOSYS; 1518 } 1519 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1520 1521 return 0; 1522 } 1523 1524 void kvm_arch_remove_all_hw_breakpoints(void) 1525 { 1526 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1527 } 1528 1529 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1530 { 1531 int n; 1532 1533 /* Software Breakpoint updates */ 1534 if (kvm_sw_breakpoints_active(cs)) { 1535 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1536 } 1537 1538 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1539 <= ARRAY_SIZE(hw_debug_points)); 1540 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1541 1542 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1543 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1544 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1545 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1546 switch (hw_debug_points[n].type) { 1547 case GDB_BREAKPOINT_HW: 1548 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1549 break; 1550 case GDB_WATCHPOINT_WRITE: 1551 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1552 break; 1553 case GDB_WATCHPOINT_READ: 1554 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1555 break; 1556 case GDB_WATCHPOINT_ACCESS: 1557 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1558 KVMPPC_DEBUG_WATCH_READ; 1559 break; 1560 default: 1561 cpu_abort(cs, "Unsupported breakpoint type\n"); 1562 } 1563 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1564 } 1565 } 1566 } 1567 1568 static int kvm_handle_hw_breakpoint(CPUState *cs, 1569 struct kvm_debug_exit_arch *arch_info) 1570 { 1571 int handle = DEBUG_RETURN_GUEST; 1572 int n; 1573 int flag = 0; 1574 1575 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1576 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1577 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1578 if (n >= 0) { 1579 handle = DEBUG_RETURN_GDB; 1580 } 1581 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1582 KVMPPC_DEBUG_WATCH_WRITE)) { 1583 n = find_hw_watchpoint(arch_info->address, &flag); 1584 if (n >= 0) { 1585 handle = DEBUG_RETURN_GDB; 1586 cs->watchpoint_hit = &hw_watchpoint; 1587 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1588 hw_watchpoint.flags = flag; 1589 } 1590 } 1591 } 1592 return handle; 1593 } 1594 1595 static int kvm_handle_singlestep(void) 1596 { 1597 return DEBUG_RETURN_GDB; 1598 } 1599 1600 static int kvm_handle_sw_breakpoint(void) 1601 { 1602 return DEBUG_RETURN_GDB; 1603 } 1604 1605 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1606 { 1607 CPUState *cs = CPU(cpu); 1608 CPUPPCState *env = &cpu->env; 1609 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1610 1611 if (cs->singlestep_enabled) { 1612 return kvm_handle_singlestep(); 1613 } 1614 1615 if (arch_info->status) { 1616 return kvm_handle_hw_breakpoint(cs, arch_info); 1617 } 1618 1619 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1620 return kvm_handle_sw_breakpoint(); 1621 } 1622 1623 /* 1624 * QEMU is not able to handle debug exception, so inject 1625 * program exception to guest; 1626 * Yes program exception NOT debug exception !! 1627 * When QEMU is using debug resources then debug exception must 1628 * be always set. To achieve this we set MSR_DE and also set 1629 * MSRP_DEP so guest cannot change MSR_DE. 1630 * When emulating debug resource for guest we want guest 1631 * to control MSR_DE (enable/disable debug interrupt on need). 1632 * Supporting both configurations are NOT possible. 1633 * So the result is that we cannot share debug resources 1634 * between QEMU and Guest on BOOKE architecture. 1635 * In the current design QEMU gets the priority over guest, 1636 * this means that if QEMU is using debug resources then guest 1637 * cannot use them; 1638 * For software breakpoint QEMU uses a privileged instruction; 1639 * So there cannot be any reason that we are here for guest 1640 * set debug exception, only possibility is guest executed a 1641 * privileged / illegal instruction and that's why we are 1642 * injecting a program interrupt. 1643 */ 1644 cpu_synchronize_state(cs); 1645 /* 1646 * env->nip is PC, so increment this by 4 to use 1647 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1648 */ 1649 env->nip += 4; 1650 cs->exception_index = POWERPC_EXCP_PROGRAM; 1651 env->error_code = POWERPC_EXCP_INVAL; 1652 ppc_cpu_do_interrupt(cs); 1653 1654 return DEBUG_RETURN_GUEST; 1655 } 1656 1657 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1658 { 1659 PowerPCCPU *cpu = POWERPC_CPU(cs); 1660 CPUPPCState *env = &cpu->env; 1661 int ret; 1662 1663 qemu_mutex_lock_iothread(); 1664 1665 switch (run->exit_reason) { 1666 case KVM_EXIT_DCR: 1667 if (run->dcr.is_write) { 1668 trace_kvm_handle_dcr_write(); 1669 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1670 } else { 1671 trace_kvm_handle_dcr_read(); 1672 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1673 } 1674 break; 1675 case KVM_EXIT_HLT: 1676 trace_kvm_handle_halt(); 1677 ret = kvmppc_handle_halt(cpu); 1678 break; 1679 #if defined(TARGET_PPC64) 1680 case KVM_EXIT_PAPR_HCALL: 1681 trace_kvm_handle_papr_hcall(run->papr_hcall.nr); 1682 run->papr_hcall.ret = spapr_hypercall(cpu, 1683 run->papr_hcall.nr, 1684 run->papr_hcall.args); 1685 ret = 0; 1686 break; 1687 #endif 1688 case KVM_EXIT_EPR: 1689 trace_kvm_handle_epr(); 1690 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1691 ret = 0; 1692 break; 1693 case KVM_EXIT_WATCHDOG: 1694 trace_kvm_handle_watchdog_expiry(); 1695 watchdog_perform_action(); 1696 ret = 0; 1697 break; 1698 1699 case KVM_EXIT_DEBUG: 1700 trace_kvm_handle_debug_exception(); 1701 if (kvm_handle_debug(cpu, run)) { 1702 ret = EXCP_DEBUG; 1703 break; 1704 } 1705 /* re-enter, this exception was guest-internal */ 1706 ret = 0; 1707 break; 1708 1709 #if defined(TARGET_PPC64) 1710 case KVM_EXIT_NMI: 1711 trace_kvm_handle_nmi_exception(); 1712 ret = kvm_handle_nmi(cpu, run); 1713 break; 1714 #endif 1715 1716 default: 1717 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1718 ret = -1; 1719 break; 1720 } 1721 1722 qemu_mutex_unlock_iothread(); 1723 return ret; 1724 } 1725 1726 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1727 { 1728 CPUState *cs = CPU(cpu); 1729 uint32_t bits = tsr_bits; 1730 struct kvm_one_reg reg = { 1731 .id = KVM_REG_PPC_OR_TSR, 1732 .addr = (uintptr_t) &bits, 1733 }; 1734 1735 if (!kvm_enabled()) { 1736 return 0; 1737 } 1738 1739 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1740 } 1741 1742 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1743 { 1744 1745 CPUState *cs = CPU(cpu); 1746 uint32_t bits = tsr_bits; 1747 struct kvm_one_reg reg = { 1748 .id = KVM_REG_PPC_CLEAR_TSR, 1749 .addr = (uintptr_t) &bits, 1750 }; 1751 1752 if (!kvm_enabled()) { 1753 return 0; 1754 } 1755 1756 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1757 } 1758 1759 int kvmppc_set_tcr(PowerPCCPU *cpu) 1760 { 1761 CPUState *cs = CPU(cpu); 1762 CPUPPCState *env = &cpu->env; 1763 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1764 1765 struct kvm_one_reg reg = { 1766 .id = KVM_REG_PPC_TCR, 1767 .addr = (uintptr_t) &tcr, 1768 }; 1769 1770 if (!kvm_enabled()) { 1771 return 0; 1772 } 1773 1774 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1775 } 1776 1777 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1778 { 1779 CPUState *cs = CPU(cpu); 1780 int ret; 1781 1782 if (!kvm_enabled()) { 1783 return -1; 1784 } 1785 1786 if (!cap_ppc_watchdog) { 1787 printf("warning: KVM does not support watchdog"); 1788 return -1; 1789 } 1790 1791 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1792 if (ret < 0) { 1793 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1794 __func__, strerror(-ret)); 1795 return ret; 1796 } 1797 1798 return ret; 1799 } 1800 1801 static int read_cpuinfo(const char *field, char *value, int len) 1802 { 1803 FILE *f; 1804 int ret = -1; 1805 int field_len = strlen(field); 1806 char line[512]; 1807 1808 f = fopen("/proc/cpuinfo", "r"); 1809 if (!f) { 1810 return -1; 1811 } 1812 1813 do { 1814 if (!fgets(line, sizeof(line), f)) { 1815 break; 1816 } 1817 if (!strncmp(line, field, field_len)) { 1818 pstrcpy(value, len, line); 1819 ret = 0; 1820 break; 1821 } 1822 } while (*line); 1823 1824 fclose(f); 1825 1826 return ret; 1827 } 1828 1829 static uint32_t kvmppc_get_tbfreq_procfs(void) 1830 { 1831 char line[512]; 1832 char *ns; 1833 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND; 1834 uint32_t tbfreq_procfs; 1835 1836 if (read_cpuinfo("timebase", line, sizeof(line))) { 1837 return tbfreq_fallback; 1838 } 1839 1840 ns = strchr(line, ':'); 1841 if (!ns) { 1842 return tbfreq_fallback; 1843 } 1844 1845 tbfreq_procfs = atoi(++ns); 1846 1847 /* 0 is certainly not acceptable by the guest, return fallback value */ 1848 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback; 1849 } 1850 1851 uint32_t kvmppc_get_tbfreq(void) 1852 { 1853 static uint32_t cached_tbfreq; 1854 1855 if (!cached_tbfreq) { 1856 cached_tbfreq = kvmppc_get_tbfreq_procfs(); 1857 } 1858 1859 return cached_tbfreq; 1860 } 1861 1862 bool kvmppc_get_host_serial(char **value) 1863 { 1864 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1865 NULL); 1866 } 1867 1868 bool kvmppc_get_host_model(char **value) 1869 { 1870 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1871 } 1872 1873 /* Try to find a device tree node for a CPU with clock-frequency property */ 1874 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1875 { 1876 struct dirent *dirp; 1877 DIR *dp; 1878 1879 dp = opendir(PROC_DEVTREE_CPU); 1880 if (!dp) { 1881 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1882 return -1; 1883 } 1884 1885 buf[0] = '\0'; 1886 while ((dirp = readdir(dp)) != NULL) { 1887 FILE *f; 1888 1889 /* Don't accidentally read from the current and parent directories */ 1890 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) { 1891 continue; 1892 } 1893 1894 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1895 dirp->d_name); 1896 f = fopen(buf, "r"); 1897 if (f) { 1898 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1899 fclose(f); 1900 break; 1901 } 1902 buf[0] = '\0'; 1903 } 1904 closedir(dp); 1905 if (buf[0] == '\0') { 1906 printf("Unknown host!\n"); 1907 return -1; 1908 } 1909 1910 return 0; 1911 } 1912 1913 static uint64_t kvmppc_read_int_dt(const char *filename) 1914 { 1915 union { 1916 uint32_t v32; 1917 uint64_t v64; 1918 } u; 1919 FILE *f; 1920 int len; 1921 1922 f = fopen(filename, "rb"); 1923 if (!f) { 1924 return -1; 1925 } 1926 1927 len = fread(&u, 1, sizeof(u), f); 1928 fclose(f); 1929 switch (len) { 1930 case 4: 1931 /* property is a 32-bit quantity */ 1932 return be32_to_cpu(u.v32); 1933 case 8: 1934 return be64_to_cpu(u.v64); 1935 } 1936 1937 return 0; 1938 } 1939 1940 /* 1941 * Read a CPU node property from the host device tree that's a single 1942 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1943 * (can't find or open the property, or doesn't understand the format) 1944 */ 1945 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1946 { 1947 char buf[PATH_MAX], *tmp; 1948 uint64_t val; 1949 1950 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1951 return -1; 1952 } 1953 1954 tmp = g_strdup_printf("%s/%s", buf, propname); 1955 val = kvmppc_read_int_dt(tmp); 1956 g_free(tmp); 1957 1958 return val; 1959 } 1960 1961 uint64_t kvmppc_get_clockfreq(void) 1962 { 1963 return kvmppc_read_int_cpu_dt("clock-frequency"); 1964 } 1965 1966 static int kvmppc_get_dec_bits(void) 1967 { 1968 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1969 1970 if (nr_bits > 0) { 1971 return nr_bits; 1972 } 1973 return 0; 1974 } 1975 1976 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1977 { 1978 CPUState *cs = env_cpu(env); 1979 1980 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1981 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1982 return 0; 1983 } 1984 1985 return 1; 1986 } 1987 1988 int kvmppc_get_hasidle(CPUPPCState *env) 1989 { 1990 struct kvm_ppc_pvinfo pvinfo; 1991 1992 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1993 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1994 return 1; 1995 } 1996 1997 return 0; 1998 } 1999 2000 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 2001 { 2002 uint32_t *hc = (uint32_t *)buf; 2003 struct kvm_ppc_pvinfo pvinfo; 2004 2005 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 2006 memcpy(buf, pvinfo.hcall, buf_len); 2007 return 0; 2008 } 2009 2010 /* 2011 * Fallback to always fail hypercalls regardless of endianness: 2012 * 2013 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 2014 * li r3, -1 2015 * b .+8 (becomes nop in wrong endian) 2016 * bswap32(li r3, -1) 2017 */ 2018 2019 hc[0] = cpu_to_be32(0x08000048); 2020 hc[1] = cpu_to_be32(0x3860ffff); 2021 hc[2] = cpu_to_be32(0x48000008); 2022 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2023 2024 return 1; 2025 } 2026 2027 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2028 { 2029 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2030 } 2031 2032 void kvmppc_enable_logical_ci_hcalls(void) 2033 { 2034 /* 2035 * FIXME: it would be nice if we could detect the cases where 2036 * we're using a device which requires the in kernel 2037 * implementation of these hcalls, but the kernel lacks them and 2038 * produce a warning. 2039 */ 2040 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2041 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2042 } 2043 2044 void kvmppc_enable_set_mode_hcall(void) 2045 { 2046 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2047 } 2048 2049 void kvmppc_enable_clear_ref_mod_hcalls(void) 2050 { 2051 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2052 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2053 } 2054 2055 void kvmppc_enable_h_page_init(void) 2056 { 2057 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2058 } 2059 2060 void kvmppc_enable_h_rpt_invalidate(void) 2061 { 2062 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE); 2063 } 2064 2065 void kvmppc_set_papr(PowerPCCPU *cpu) 2066 { 2067 CPUState *cs = CPU(cpu); 2068 int ret; 2069 2070 if (!kvm_enabled()) { 2071 return; 2072 } 2073 2074 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2075 if (ret) { 2076 error_report("This vCPU type or KVM version does not support PAPR"); 2077 exit(1); 2078 } 2079 2080 /* 2081 * Update the capability flag so we sync the right information 2082 * with kvm 2083 */ 2084 cap_papr = 1; 2085 } 2086 2087 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2088 { 2089 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2090 } 2091 2092 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2093 { 2094 CPUState *cs = CPU(cpu); 2095 int ret; 2096 2097 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2098 if (ret && mpic_proxy) { 2099 error_report("This KVM version does not support EPR"); 2100 exit(1); 2101 } 2102 } 2103 2104 bool kvmppc_get_fwnmi(void) 2105 { 2106 return cap_fwnmi; 2107 } 2108 2109 int kvmppc_set_fwnmi(PowerPCCPU *cpu) 2110 { 2111 CPUState *cs = CPU(cpu); 2112 2113 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); 2114 } 2115 2116 int kvmppc_smt_threads(void) 2117 { 2118 return cap_ppc_smt ? cap_ppc_smt : 1; 2119 } 2120 2121 int kvmppc_set_smt_threads(int smt) 2122 { 2123 int ret; 2124 2125 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2126 if (!ret) { 2127 cap_ppc_smt = smt; 2128 } 2129 return ret; 2130 } 2131 2132 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2133 { 2134 int i; 2135 GString *g; 2136 char *s; 2137 2138 assert(kvm_enabled()); 2139 if (cap_ppc_smt_possible) { 2140 g = g_string_new("Available VSMT modes:"); 2141 for (i = 63; i >= 0; i--) { 2142 if ((1UL << i) & cap_ppc_smt_possible) { 2143 g_string_append_printf(g, " %lu", (1UL << i)); 2144 } 2145 } 2146 s = g_string_free(g, false); 2147 error_append_hint(errp, "%s.\n", s); 2148 g_free(s); 2149 } else { 2150 error_append_hint(errp, 2151 "This KVM seems to be too old to support VSMT.\n"); 2152 } 2153 } 2154 2155 2156 #ifdef TARGET_PPC64 2157 uint64_t kvmppc_vrma_limit(unsigned int hash_shift) 2158 { 2159 struct kvm_ppc_smmu_info info; 2160 long rampagesize, best_page_shift; 2161 int i; 2162 2163 /* 2164 * Find the largest hardware supported page size that's less than 2165 * or equal to the (logical) backing page size of guest RAM 2166 */ 2167 kvm_get_smmu_info(&info, &error_fatal); 2168 rampagesize = qemu_minrampagesize(); 2169 best_page_shift = 0; 2170 2171 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2172 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2173 2174 if (!sps->page_shift) { 2175 continue; 2176 } 2177 2178 if ((sps->page_shift > best_page_shift) 2179 && ((1UL << sps->page_shift) <= rampagesize)) { 2180 best_page_shift = sps->page_shift; 2181 } 2182 } 2183 2184 return 1ULL << (best_page_shift + hash_shift - 7); 2185 } 2186 #endif 2187 2188 bool kvmppc_spapr_use_multitce(void) 2189 { 2190 return cap_spapr_multitce; 2191 } 2192 2193 int kvmppc_spapr_enable_inkernel_multitce(void) 2194 { 2195 int ret; 2196 2197 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2198 H_PUT_TCE_INDIRECT, 1); 2199 if (!ret) { 2200 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2201 H_STUFF_TCE, 1); 2202 } 2203 2204 return ret; 2205 } 2206 2207 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2208 uint64_t bus_offset, uint32_t nb_table, 2209 int *pfd, bool need_vfio) 2210 { 2211 long len; 2212 int fd; 2213 void *table; 2214 2215 /* 2216 * Must set fd to -1 so we don't try to munmap when called for 2217 * destroying the table, which the upper layers -will- do 2218 */ 2219 *pfd = -1; 2220 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2221 return NULL; 2222 } 2223 2224 if (cap_spapr_tce_64) { 2225 struct kvm_create_spapr_tce_64 args = { 2226 .liobn = liobn, 2227 .page_shift = page_shift, 2228 .offset = bus_offset >> page_shift, 2229 .size = nb_table, 2230 .flags = 0 2231 }; 2232 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2233 if (fd < 0) { 2234 fprintf(stderr, 2235 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2236 liobn); 2237 return NULL; 2238 } 2239 } else if (cap_spapr_tce) { 2240 uint64_t window_size = (uint64_t) nb_table << page_shift; 2241 struct kvm_create_spapr_tce args = { 2242 .liobn = liobn, 2243 .window_size = window_size, 2244 }; 2245 if ((window_size != args.window_size) || bus_offset) { 2246 return NULL; 2247 } 2248 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2249 if (fd < 0) { 2250 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2251 liobn); 2252 return NULL; 2253 } 2254 } else { 2255 return NULL; 2256 } 2257 2258 len = nb_table * sizeof(uint64_t); 2259 /* FIXME: round this up to page size */ 2260 2261 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2262 if (table == MAP_FAILED) { 2263 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2264 liobn); 2265 close(fd); 2266 return NULL; 2267 } 2268 2269 *pfd = fd; 2270 return table; 2271 } 2272 2273 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2274 { 2275 long len; 2276 2277 if (fd < 0) { 2278 return -1; 2279 } 2280 2281 len = nb_table * sizeof(uint64_t); 2282 if ((munmap(table, len) < 0) || 2283 (close(fd) < 0)) { 2284 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2285 strerror(errno)); 2286 /* Leak the table */ 2287 } 2288 2289 return 0; 2290 } 2291 2292 int kvmppc_reset_htab(int shift_hint) 2293 { 2294 uint32_t shift = shift_hint; 2295 2296 if (!kvm_enabled()) { 2297 /* Full emulation, tell caller to allocate htab itself */ 2298 return 0; 2299 } 2300 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2301 int ret; 2302 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2303 if (ret == -ENOTTY) { 2304 /* 2305 * At least some versions of PR KVM advertise the 2306 * capability, but don't implement the ioctl(). Oops. 2307 * Return 0 so that we allocate the htab in qemu, as is 2308 * correct for PR. 2309 */ 2310 return 0; 2311 } else if (ret < 0) { 2312 return ret; 2313 } 2314 return shift; 2315 } 2316 2317 /* 2318 * We have a kernel that predates the htab reset calls. For PR 2319 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2320 * this era, it has allocated a 16MB fixed size hash table 2321 * already. 2322 */ 2323 if (kvmppc_is_pr(kvm_state)) { 2324 /* PR - tell caller to allocate htab */ 2325 return 0; 2326 } else { 2327 /* HV - assume 16MB kernel allocated htab */ 2328 return 24; 2329 } 2330 } 2331 2332 static inline uint32_t mfpvr(void) 2333 { 2334 uint32_t pvr; 2335 2336 asm ("mfpvr %0" 2337 : "=r"(pvr)); 2338 return pvr; 2339 } 2340 2341 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2342 { 2343 if (on) { 2344 *word |= flags; 2345 } else { 2346 *word &= ~flags; 2347 } 2348 } 2349 2350 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2351 { 2352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2353 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2354 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2355 2356 /* Now fix up the class with information we can query from the host */ 2357 pcc->pvr = mfpvr(); 2358 2359 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2360 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2361 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2362 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2363 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2364 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2365 2366 if (dcache_size != -1) { 2367 pcc->l1_dcache_size = dcache_size; 2368 } 2369 2370 if (icache_size != -1) { 2371 pcc->l1_icache_size = icache_size; 2372 } 2373 2374 #if defined(TARGET_PPC64) 2375 pcc->radix_page_info = kvm_get_radix_page_info(); 2376 2377 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2378 /* 2379 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2380 * compliant. More importantly, advertising ISA 3.00 2381 * architected mode may prevent guests from activating 2382 * necessary DD1 workarounds. 2383 */ 2384 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2385 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2386 } 2387 #endif /* defined(TARGET_PPC64) */ 2388 } 2389 2390 bool kvmppc_has_cap_epr(void) 2391 { 2392 return cap_epr; 2393 } 2394 2395 bool kvmppc_has_cap_fixup_hcalls(void) 2396 { 2397 return cap_fixup_hcalls; 2398 } 2399 2400 bool kvmppc_has_cap_htm(void) 2401 { 2402 return cap_htm; 2403 } 2404 2405 bool kvmppc_has_cap_mmu_radix(void) 2406 { 2407 return cap_mmu_radix; 2408 } 2409 2410 bool kvmppc_has_cap_mmu_hash_v3(void) 2411 { 2412 return cap_mmu_hash_v3; 2413 } 2414 2415 static bool kvmppc_power8_host(void) 2416 { 2417 bool ret = false; 2418 #ifdef TARGET_PPC64 2419 { 2420 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2421 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2422 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2423 (base_pvr == CPU_POWERPC_POWER8_BASE); 2424 } 2425 #endif /* TARGET_PPC64 */ 2426 return ret; 2427 } 2428 2429 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2430 { 2431 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2432 2433 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2434 return 2; 2435 } else if ((!l1d_thread_priv_req || 2436 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2437 (c.character & c.character_mask 2438 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2439 return 1; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2446 { 2447 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2448 return 2; 2449 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2450 return 1; 2451 } 2452 2453 return 0; 2454 } 2455 2456 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2457 { 2458 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2459 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2460 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2461 return SPAPR_CAP_FIXED_NA; 2462 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2463 return SPAPR_CAP_WORKAROUND; 2464 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2465 return SPAPR_CAP_FIXED_CCD; 2466 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2467 return SPAPR_CAP_FIXED_IBS; 2468 } 2469 2470 return 0; 2471 } 2472 2473 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2474 { 2475 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2476 return 1; 2477 } 2478 return 0; 2479 } 2480 2481 bool kvmppc_has_cap_xive(void) 2482 { 2483 return cap_xive; 2484 } 2485 2486 static void kvmppc_get_cpu_characteristics(KVMState *s) 2487 { 2488 struct kvm_ppc_cpu_char c; 2489 int ret; 2490 2491 /* Assume broken */ 2492 cap_ppc_safe_cache = 0; 2493 cap_ppc_safe_bounds_check = 0; 2494 cap_ppc_safe_indirect_branch = 0; 2495 2496 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2497 if (!ret) { 2498 return; 2499 } 2500 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2501 if (ret < 0) { 2502 return; 2503 } 2504 2505 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2506 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2507 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2508 cap_ppc_count_cache_flush_assist = 2509 parse_cap_ppc_count_cache_flush_assist(c); 2510 } 2511 2512 int kvmppc_get_cap_safe_cache(void) 2513 { 2514 return cap_ppc_safe_cache; 2515 } 2516 2517 int kvmppc_get_cap_safe_bounds_check(void) 2518 { 2519 return cap_ppc_safe_bounds_check; 2520 } 2521 2522 int kvmppc_get_cap_safe_indirect_branch(void) 2523 { 2524 return cap_ppc_safe_indirect_branch; 2525 } 2526 2527 int kvmppc_get_cap_count_cache_flush_assist(void) 2528 { 2529 return cap_ppc_count_cache_flush_assist; 2530 } 2531 2532 bool kvmppc_has_cap_nested_kvm_hv(void) 2533 { 2534 return !!cap_ppc_nested_kvm_hv; 2535 } 2536 2537 int kvmppc_set_cap_nested_kvm_hv(int enable) 2538 { 2539 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2540 } 2541 2542 bool kvmppc_has_cap_spapr_vfio(void) 2543 { 2544 return cap_spapr_vfio; 2545 } 2546 2547 int kvmppc_get_cap_large_decr(void) 2548 { 2549 return cap_large_decr; 2550 } 2551 2552 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2553 { 2554 CPUState *cs = CPU(cpu); 2555 uint64_t lpcr = 0; 2556 2557 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2558 /* Do we need to modify the LPCR? */ 2559 if (!!(lpcr & LPCR_LD) != !!enable) { 2560 if (enable) { 2561 lpcr |= LPCR_LD; 2562 } else { 2563 lpcr &= ~LPCR_LD; 2564 } 2565 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2566 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2567 2568 if (!!(lpcr & LPCR_LD) != !!enable) { 2569 return -1; 2570 } 2571 } 2572 2573 return 0; 2574 } 2575 2576 int kvmppc_has_cap_rpt_invalidate(void) 2577 { 2578 return cap_rpt_invalidate; 2579 } 2580 2581 bool kvmppc_supports_ail_3(void) 2582 { 2583 return cap_ail_mode_3; 2584 } 2585 2586 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2587 { 2588 uint32_t host_pvr = mfpvr(); 2589 PowerPCCPUClass *pvr_pcc; 2590 2591 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2592 if (pvr_pcc == NULL) { 2593 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2594 } 2595 2596 return pvr_pcc; 2597 } 2598 2599 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2600 { 2601 MachineClass *mc = MACHINE_CLASS(oc); 2602 2603 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2604 } 2605 2606 static int kvm_ppc_register_host_cpu_type(void) 2607 { 2608 TypeInfo type_info = { 2609 .name = TYPE_HOST_POWERPC_CPU, 2610 .class_init = kvmppc_host_cpu_class_init, 2611 }; 2612 PowerPCCPUClass *pvr_pcc; 2613 ObjectClass *oc; 2614 DeviceClass *dc; 2615 int i; 2616 2617 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2618 if (pvr_pcc == NULL) { 2619 return -1; 2620 } 2621 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2622 type_register(&type_info); 2623 /* override TCG default cpu type with 'host' cpu model */ 2624 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2625 false, NULL); 2626 2627 oc = object_class_by_name(type_info.name); 2628 g_assert(oc); 2629 2630 /* 2631 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2632 * we want "POWER8" to be a "family" alias that points to the current 2633 * host CPU type, too) 2634 */ 2635 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2636 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2637 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2638 char *suffix; 2639 2640 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2641 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2642 if (suffix) { 2643 *suffix = 0; 2644 } 2645 break; 2646 } 2647 } 2648 2649 return 0; 2650 } 2651 2652 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2653 { 2654 struct kvm_rtas_token_args args = { 2655 .token = token, 2656 }; 2657 2658 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2659 return -ENOENT; 2660 } 2661 2662 strncpy(args.name, function, sizeof(args.name) - 1); 2663 2664 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2665 } 2666 2667 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2668 { 2669 struct kvm_get_htab_fd s = { 2670 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2671 .start_index = index, 2672 }; 2673 int ret; 2674 2675 if (!cap_htab_fd) { 2676 error_setg(errp, "KVM version doesn't support %s the HPT", 2677 write ? "writing" : "reading"); 2678 return -ENOTSUP; 2679 } 2680 2681 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2682 if (ret < 0) { 2683 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2684 write ? "writing" : "reading", write ? "to" : "from", 2685 strerror(errno)); 2686 return -errno; 2687 } 2688 2689 return ret; 2690 } 2691 2692 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2693 { 2694 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2695 uint8_t buf[bufsize]; 2696 ssize_t rc; 2697 2698 do { 2699 rc = read(fd, buf, bufsize); 2700 if (rc < 0) { 2701 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2702 strerror(errno)); 2703 return rc; 2704 } else if (rc) { 2705 uint8_t *buffer = buf; 2706 ssize_t n = rc; 2707 while (n) { 2708 struct kvm_get_htab_header *head = 2709 (struct kvm_get_htab_header *) buffer; 2710 size_t chunksize = sizeof(*head) + 2711 HASH_PTE_SIZE_64 * head->n_valid; 2712 2713 qemu_put_be32(f, head->index); 2714 qemu_put_be16(f, head->n_valid); 2715 qemu_put_be16(f, head->n_invalid); 2716 qemu_put_buffer(f, (void *)(head + 1), 2717 HASH_PTE_SIZE_64 * head->n_valid); 2718 2719 buffer += chunksize; 2720 n -= chunksize; 2721 } 2722 } 2723 } while ((rc != 0) 2724 && ((max_ns < 0) || 2725 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2726 2727 return (rc == 0) ? 1 : 0; 2728 } 2729 2730 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2731 uint16_t n_valid, uint16_t n_invalid, Error **errp) 2732 { 2733 struct kvm_get_htab_header *buf; 2734 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2735 ssize_t rc; 2736 2737 buf = alloca(chunksize); 2738 buf->index = index; 2739 buf->n_valid = n_valid; 2740 buf->n_invalid = n_invalid; 2741 2742 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2743 2744 rc = write(fd, buf, chunksize); 2745 if (rc < 0) { 2746 error_setg_errno(errp, errno, "Error writing the KVM hash table"); 2747 return -errno; 2748 } 2749 if (rc != chunksize) { 2750 /* We should never get a short write on a single chunk */ 2751 error_setg(errp, "Short write while restoring the KVM hash table"); 2752 return -ENOSPC; 2753 } 2754 return 0; 2755 } 2756 2757 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2758 { 2759 return true; 2760 } 2761 2762 void kvm_arch_init_irq_routing(KVMState *s) 2763 { 2764 } 2765 2766 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2767 { 2768 int fd, rc; 2769 int i; 2770 2771 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2772 2773 i = 0; 2774 while (i < n) { 2775 struct kvm_get_htab_header *hdr; 2776 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2777 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2778 2779 rc = read(fd, buf, sizeof(buf)); 2780 if (rc < 0) { 2781 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2782 } 2783 2784 hdr = (struct kvm_get_htab_header *)buf; 2785 while ((i < n) && ((char *)hdr < (buf + rc))) { 2786 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2787 2788 if (hdr->index != (ptex + i)) { 2789 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2790 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2791 } 2792 2793 if (n - i < valid) { 2794 valid = n - i; 2795 } 2796 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2797 i += valid; 2798 2799 if ((n - i) < invalid) { 2800 invalid = n - i; 2801 } 2802 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2803 i += invalid; 2804 2805 hdr = (struct kvm_get_htab_header *) 2806 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2807 } 2808 } 2809 2810 close(fd); 2811 } 2812 2813 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2814 { 2815 int fd, rc; 2816 struct { 2817 struct kvm_get_htab_header hdr; 2818 uint64_t pte0; 2819 uint64_t pte1; 2820 } buf; 2821 2822 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2823 2824 buf.hdr.n_valid = 1; 2825 buf.hdr.n_invalid = 0; 2826 buf.hdr.index = ptex; 2827 buf.pte0 = cpu_to_be64(pte0); 2828 buf.pte1 = cpu_to_be64(pte1); 2829 2830 rc = write(fd, &buf, sizeof(buf)); 2831 if (rc != sizeof(buf)) { 2832 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2833 } 2834 close(fd); 2835 } 2836 2837 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2838 uint64_t address, uint32_t data, PCIDevice *dev) 2839 { 2840 return 0; 2841 } 2842 2843 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2844 int vector, PCIDevice *dev) 2845 { 2846 return 0; 2847 } 2848 2849 int kvm_arch_release_virq_post(int virq) 2850 { 2851 return 0; 2852 } 2853 2854 int kvm_arch_msi_data_to_gsi(uint32_t data) 2855 { 2856 return data & 0xffff; 2857 } 2858 2859 #if defined(TARGET_PPC64) 2860 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) 2861 { 2862 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK; 2863 2864 cpu_synchronize_state(CPU(cpu)); 2865 2866 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV); 2867 2868 return 0; 2869 } 2870 #endif 2871 2872 int kvmppc_enable_hwrng(void) 2873 { 2874 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2875 return -1; 2876 } 2877 2878 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2879 } 2880 2881 void kvmppc_check_papr_resize_hpt(Error **errp) 2882 { 2883 if (!kvm_enabled()) { 2884 return; /* No KVM, we're good */ 2885 } 2886 2887 if (cap_resize_hpt) { 2888 return; /* Kernel has explicit support, we're good */ 2889 } 2890 2891 /* Otherwise fallback on looking for PR KVM */ 2892 if (kvmppc_is_pr(kvm_state)) { 2893 return; 2894 } 2895 2896 error_setg(errp, 2897 "Hash page table resizing not available with this KVM version"); 2898 } 2899 2900 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2901 { 2902 CPUState *cs = CPU(cpu); 2903 struct kvm_ppc_resize_hpt rhpt = { 2904 .flags = flags, 2905 .shift = shift, 2906 }; 2907 2908 if (!cap_resize_hpt) { 2909 return -ENOSYS; 2910 } 2911 2912 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2913 } 2914 2915 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2916 { 2917 CPUState *cs = CPU(cpu); 2918 struct kvm_ppc_resize_hpt rhpt = { 2919 .flags = flags, 2920 .shift = shift, 2921 }; 2922 2923 if (!cap_resize_hpt) { 2924 return -ENOSYS; 2925 } 2926 2927 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2928 } 2929 2930 /* 2931 * This is a helper function to detect a post migration scenario 2932 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2933 * the guest kernel can't handle a PVR value other than the actual host 2934 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2935 * 2936 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2937 * (so, we're HV), return true. The workaround itself is done in 2938 * cpu_post_load. 2939 * 2940 * The order here is important: we'll only check for KVM PR as a 2941 * fallback if the guest kernel can't handle the situation itself. 2942 * We need to avoid as much as possible querying the running KVM type 2943 * in QEMU level. 2944 */ 2945 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2946 { 2947 CPUState *cs = CPU(cpu); 2948 2949 if (!kvm_enabled()) { 2950 return false; 2951 } 2952 2953 if (cap_ppc_pvr_compat) { 2954 return false; 2955 } 2956 2957 return !kvmppc_is_pr(cs->kvm_state); 2958 } 2959 2960 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2961 { 2962 CPUState *cs = CPU(cpu); 2963 2964 if (kvm_enabled()) { 2965 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2966 } 2967 } 2968 2969 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2970 { 2971 CPUState *cs = CPU(cpu); 2972 2973 if (kvm_enabled()) { 2974 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2975 } 2976 } 2977 2978 bool kvm_arch_cpu_check_are_resettable(void) 2979 { 2980 return true; 2981 } 2982 2983 void kvm_arch_accel_class_init(ObjectClass *oc) 2984 { 2985 } 2986