1 /* 2 * PowerPC emulation special registers manipulation helpers for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HELPER_REGS_H 21 #define HELPER_REGS_H 22 23 /* Swap temporary saved registers with GPRs */ 24 static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) 25 { 26 target_ulong tmp; 27 28 tmp = env->gpr[0]; 29 env->gpr[0] = env->tgpr[0]; 30 env->tgpr[0] = tmp; 31 tmp = env->gpr[1]; 32 env->gpr[1] = env->tgpr[1]; 33 env->tgpr[1] = tmp; 34 tmp = env->gpr[2]; 35 env->gpr[2] = env->tgpr[2]; 36 env->tgpr[2] = tmp; 37 tmp = env->gpr[3]; 38 env->gpr[3] = env->tgpr[3]; 39 env->tgpr[3] = tmp; 40 } 41 42 static inline void hreg_compute_mem_idx(CPUPPCState *env) 43 { 44 /* This is our encoding for server processors. The architecture 45 * specifies that there is no such thing as userspace with 46 * translation off, however it appears that MacOS does it and 47 * some 32-bit CPUs support it. Weird... 48 * 49 * 0 = Guest User space virtual mode 50 * 1 = Guest Kernel space virtual mode 51 * 2 = Guest User space real mode 52 * 3 = Guest Kernel space real mode 53 * 4 = HV User space virtual mode 54 * 5 = HV Kernel space virtual mode 55 * 6 = HV User space real mode 56 * 7 = HV Kernel space real mode 57 * 58 * For BookE, we need 8 MMU modes as follow: 59 * 60 * 0 = AS 0 HV User space 61 * 1 = AS 0 HV Kernel space 62 * 2 = AS 1 HV User space 63 * 3 = AS 1 HV Kernel space 64 * 4 = AS 0 Guest User space 65 * 5 = AS 0 Guest Kernel space 66 * 6 = AS 1 Guest User space 67 * 7 = AS 1 Guest Kernel space 68 */ 69 if (env->mmu_model & POWERPC_MMU_BOOKE) { 70 env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; 71 env->immu_idx += msr_is ? 2 : 0; 72 env->dmmu_idx += msr_ds ? 2 : 0; 73 env->immu_idx += msr_gs ? 4 : 0; 74 env->dmmu_idx += msr_gs ? 4 : 0; 75 } else { 76 env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; 77 env->immu_idx += msr_ir ? 0 : 2; 78 env->dmmu_idx += msr_dr ? 0 : 2; 79 env->immu_idx += msr_hv ? 4 : 0; 80 env->dmmu_idx += msr_hv ? 4 : 0; 81 } 82 } 83 84 static inline void hreg_compute_hflags(CPUPPCState *env) 85 { 86 target_ulong hflags_mask; 87 88 /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ 89 hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | 90 (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | 91 (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); 92 hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; 93 hreg_compute_mem_idx(env); 94 env->hflags = env->msr & hflags_mask; 95 /* Merge with hflags coming from other registers */ 96 env->hflags |= env->hflags_nmsr; 97 } 98 99 static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, 100 int alter_hv) 101 { 102 int excp; 103 #if !defined(CONFIG_USER_ONLY) 104 CPUState *cs = CPU(ppc_env_get_cpu(env)); 105 #endif 106 107 excp = 0; 108 value &= env->msr_mask; 109 #if !defined(CONFIG_USER_ONLY) 110 /* Neither mtmsr nor guest state can alter HV */ 111 if (!alter_hv || !(env->msr & MSR_HVB)) { 112 value &= ~MSR_HVB; 113 value |= env->msr & MSR_HVB; 114 } 115 if (((value >> MSR_IR) & 1) != msr_ir || 116 ((value >> MSR_DR) & 1) != msr_dr) { 117 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 118 } 119 if ((env->mmu_model & POWERPC_MMU_BOOKE) && 120 ((value >> MSR_GS) & 1) != msr_gs) { 121 cs->interrupt_request |= CPU_INTERRUPT_EXITTB; 122 } 123 if (unlikely((env->flags & POWERPC_FLAG_TGPR) && 124 ((value ^ env->msr) & (1 << MSR_TGPR)))) { 125 /* Swap temporary saved registers with GPRs */ 126 hreg_swap_gpr_tgpr(env); 127 } 128 if (unlikely((value >> MSR_EP) & 1) != msr_ep) { 129 /* Change the exception prefix on PowerPC 601 */ 130 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; 131 } 132 /* If PR=1 then EE, IR and DR must be 1 133 * 134 * Note: We only enforce this on 64-bit server processors. 135 * It appears that: 136 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS 137 * exploits it. 138 * - 64-bit embedded implementations do not need any operation to be 139 * performed when PR is set. 140 */ 141 if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) { 142 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); 143 } 144 #endif 145 env->msr = value; 146 hreg_compute_hflags(env); 147 #if !defined(CONFIG_USER_ONLY) 148 if (unlikely(msr_pow == 1)) { 149 if (!env->pending_interrupts && (*env->check_pow)(env)) { 150 cs->halted = 1; 151 excp = EXCP_HALTED; 152 } 153 } 154 #endif 155 156 return excp; 157 } 158 159 #if !defined(CONFIG_USER_ONLY) 160 static inline void check_tlb_flush(CPUPPCState *env, bool global) 161 { 162 CPUState *cs = CPU(ppc_env_get_cpu(env)); 163 if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { 164 tlb_flush(cs); 165 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 166 } 167 168 /* Propagate TLB invalidations to other CPUs when the guest uses broadcast 169 * TLB invalidation instructions. 170 */ 171 if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { 172 CPUState *other_cs; 173 CPU_FOREACH(other_cs) { 174 if (other_cs != cs) { 175 PowerPCCPU *cpu = POWERPC_CPU(other_cs); 176 CPUPPCState *other_env = &cpu->env; 177 178 other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 179 tlb_flush(other_cs); 180 } 181 } 182 env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; 183 } 184 } 185 #else 186 static inline void check_tlb_flush(CPUPPCState *env, bool global) { } 187 #endif 188 189 #endif /* HELPER_REGS_H */ 190