1 /* 2 * PowerPC emulation special registers manipulation helpers for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "qemu/main-loop.h" 23 #include "exec/exec-all.h" 24 #include "sysemu/kvm.h" 25 #include "helper_regs.h" 26 27 /* Swap temporary saved registers with GPRs */ 28 void hreg_swap_gpr_tgpr(CPUPPCState *env) 29 { 30 target_ulong tmp; 31 32 tmp = env->gpr[0]; 33 env->gpr[0] = env->tgpr[0]; 34 env->tgpr[0] = tmp; 35 tmp = env->gpr[1]; 36 env->gpr[1] = env->tgpr[1]; 37 env->tgpr[1] = tmp; 38 tmp = env->gpr[2]; 39 env->gpr[2] = env->tgpr[2]; 40 env->tgpr[2] = tmp; 41 tmp = env->gpr[3]; 42 env->gpr[3] = env->tgpr[3]; 43 env->tgpr[3] = tmp; 44 } 45 46 static uint32_t hreg_compute_hflags_value(CPUPPCState *env) 47 { 48 target_ulong msr = env->msr; 49 uint32_t ppc_flags = env->flags; 50 uint32_t hflags = 0; 51 uint32_t msr_mask; 52 53 /* Some bits come straight across from MSR. */ 54 QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); 55 QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); 56 QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); 57 QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); 58 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | 59 (1 << MSR_DR) | (1 << MSR_FP)); 60 61 if (ppc_flags & POWERPC_FLAG_HID0_LE) { 62 /* 63 * Note that MSR_LE is not set in env->msr_mask for this cpu, 64 * and so will never be set in msr. 65 */ 66 uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); 67 hflags |= le << MSR_LE; 68 } 69 70 if (ppc_flags & POWERPC_FLAG_DE) { 71 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 72 if (dbcr0 & DBCR0_ICMP) { 73 hflags |= 1 << HFLAGS_SE; 74 } 75 if (dbcr0 & DBCR0_BRT) { 76 hflags |= 1 << HFLAGS_BE; 77 } 78 } else { 79 if (ppc_flags & POWERPC_FLAG_BE) { 80 QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); 81 msr_mask |= 1 << MSR_BE; 82 } 83 if (ppc_flags & POWERPC_FLAG_SE) { 84 QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); 85 msr_mask |= 1 << MSR_SE; 86 } 87 } 88 89 if (msr_is_64bit(env, msr)) { 90 hflags |= 1 << HFLAGS_64; 91 } 92 if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { 93 hflags |= 1 << HFLAGS_SPE; 94 } 95 if (ppc_flags & POWERPC_FLAG_VRE) { 96 QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); 97 msr_mask |= 1 << MSR_VR; 98 } 99 if (ppc_flags & POWERPC_FLAG_VSX) { 100 QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX); 101 msr_mask |= 1 << MSR_VSX; 102 } 103 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { 104 hflags |= 1 << HFLAGS_TM; 105 } 106 if (env->spr[SPR_LPCR] & LPCR_GTSE) { 107 hflags |= 1 << HFLAGS_GTSE; 108 } 109 110 #ifndef CONFIG_USER_ONLY 111 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { 112 hflags |= 1 << HFLAGS_HV; 113 } 114 115 /* 116 * This is our encoding for server processors. The architecture 117 * specifies that there is no such thing as userspace with 118 * translation off, however it appears that MacOS does it and some 119 * 32-bit CPUs support it. Weird... 120 * 121 * 0 = Guest User space virtual mode 122 * 1 = Guest Kernel space virtual mode 123 * 2 = Guest User space real mode 124 * 3 = Guest Kernel space real mode 125 * 4 = HV User space virtual mode 126 * 5 = HV Kernel space virtual mode 127 * 6 = HV User space real mode 128 * 7 = HV Kernel space real mode 129 * 130 * For BookE, we need 8 MMU modes as follow: 131 * 132 * 0 = AS 0 HV User space 133 * 1 = AS 0 HV Kernel space 134 * 2 = AS 1 HV User space 135 * 3 = AS 1 HV Kernel space 136 * 4 = AS 0 Guest User space 137 * 5 = AS 0 Guest Kernel space 138 * 6 = AS 1 Guest User space 139 * 7 = AS 1 Guest Kernel space 140 */ 141 unsigned immu_idx, dmmu_idx; 142 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; 143 if (env->mmu_model & POWERPC_MMU_BOOKE) { 144 dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; 145 immu_idx = dmmu_idx; 146 immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; 147 dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; 148 } else { 149 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; 150 immu_idx = dmmu_idx; 151 immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; 152 dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; 153 } 154 hflags |= immu_idx << HFLAGS_IMMU_IDX; 155 hflags |= dmmu_idx << HFLAGS_DMMU_IDX; 156 #endif 157 158 return hflags | (msr & msr_mask); 159 } 160 161 void hreg_compute_hflags(CPUPPCState *env) 162 { 163 env->hflags = hreg_compute_hflags_value(env); 164 } 165 166 #ifdef CONFIG_DEBUG_TCG 167 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 168 target_ulong *cs_base, uint32_t *flags) 169 { 170 uint32_t hflags_current = env->hflags; 171 uint32_t hflags_rebuilt; 172 173 *pc = env->nip; 174 *cs_base = 0; 175 *flags = hflags_current; 176 177 hflags_rebuilt = hreg_compute_hflags_value(env); 178 if (unlikely(hflags_current != hflags_rebuilt)) { 179 cpu_abort(env_cpu(env), 180 "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", 181 hflags_current, hflags_rebuilt); 182 } 183 } 184 #endif 185 186 void cpu_interrupt_exittb(CPUState *cs) 187 { 188 if (!kvm_enabled()) { 189 return; 190 } 191 192 if (!qemu_mutex_iothread_locked()) { 193 qemu_mutex_lock_iothread(); 194 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 195 qemu_mutex_unlock_iothread(); 196 } else { 197 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 198 } 199 } 200 201 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) 202 { 203 int excp; 204 #if !defined(CONFIG_USER_ONLY) 205 CPUState *cs = env_cpu(env); 206 #endif 207 208 excp = 0; 209 value &= env->msr_mask; 210 #if !defined(CONFIG_USER_ONLY) 211 /* Neither mtmsr nor guest state can alter HV */ 212 if (!alter_hv || !(env->msr & MSR_HVB)) { 213 value &= ~MSR_HVB; 214 value |= env->msr & MSR_HVB; 215 } 216 if (((value >> MSR_IR) & 1) != msr_ir || 217 ((value >> MSR_DR) & 1) != msr_dr) { 218 cpu_interrupt_exittb(cs); 219 } 220 if ((env->mmu_model & POWERPC_MMU_BOOKE) && 221 ((value >> MSR_GS) & 1) != msr_gs) { 222 cpu_interrupt_exittb(cs); 223 } 224 if (unlikely((env->flags & POWERPC_FLAG_TGPR) && 225 ((value ^ env->msr) & (1 << MSR_TGPR)))) { 226 /* Swap temporary saved registers with GPRs */ 227 hreg_swap_gpr_tgpr(env); 228 } 229 if (unlikely((value >> MSR_EP) & 1) != msr_ep) { 230 /* Change the exception prefix on PowerPC 601 */ 231 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; 232 } 233 /* 234 * If PR=1 then EE, IR and DR must be 1 235 * 236 * Note: We only enforce this on 64-bit server processors. 237 * It appears that: 238 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS 239 * exploits it. 240 * - 64-bit embedded implementations do not need any operation to be 241 * performed when PR is set. 242 */ 243 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { 244 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); 245 } 246 #endif 247 env->msr = value; 248 hreg_compute_hflags(env); 249 #if !defined(CONFIG_USER_ONLY) 250 if (unlikely(msr_pow == 1)) { 251 if (!env->pending_interrupts && (*env->check_pow)(env)) { 252 cs->halted = 1; 253 excp = EXCP_HALTED; 254 } 255 } 256 #endif 257 258 return excp; 259 } 260 261 #ifndef CONFIG_USER_ONLY 262 void check_tlb_flush(CPUPPCState *env, bool global) 263 { 264 CPUState *cs = env_cpu(env); 265 266 /* Handle global flushes first */ 267 if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { 268 env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; 269 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 270 tlb_flush_all_cpus_synced(cs); 271 return; 272 } 273 274 /* Then handle local ones */ 275 if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { 276 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 277 tlb_flush(cs); 278 } 279 } 280 #endif 281