1 /* 2 * PowerPC gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 #include "gdbstub/helpers.h" 24 #include "internal.h" 25 26 static int ppc_gdb_register_len_apple(int n) 27 { 28 switch (n) { 29 case 0 ... 31: 30 /* gprs */ 31 return 8; 32 case 32 ... 63: 33 /* fprs */ 34 return 8; 35 case 64 ... 95: 36 return 16; 37 case 64 + 32: /* nip */ 38 case 65 + 32: /* msr */ 39 case 67 + 32: /* lr */ 40 case 68 + 32: /* ctr */ 41 case 70 + 32: /* fpscr */ 42 return 8; 43 case 66 + 32: /* cr */ 44 case 69 + 32: /* xer */ 45 return 4; 46 default: 47 return 0; 48 } 49 } 50 51 static int ppc_gdb_register_len(int n) 52 { 53 switch (n) { 54 case 0 ... 31: 55 /* gprs */ 56 return sizeof(target_ulong); 57 case 66: 58 /* cr */ 59 case 69: 60 /* xer */ 61 return 4; 62 case 64: 63 /* nip */ 64 case 65: 65 /* msr */ 66 case 67: 67 /* lr */ 68 case 68: 69 /* ctr */ 70 return sizeof(target_ulong); 71 default: 72 return 0; 73 } 74 } 75 76 /* 77 * We need to present the registers to gdb in the "current" memory 78 * ordering. For user-only mode we get this for free; 79 * TARGET_BIG_ENDIAN is set to the proper ordering for the 80 * binary, and cannot be changed. For system mode, 81 * TARGET_BIG_ENDIAN is always set, and we must check the current 82 * mode of the chip to see if we're running in little-endian. 83 */ 84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) 85 { 86 #ifndef CONFIG_USER_ONLY 87 if (!FIELD_EX64(env->msr, MSR, LE)) { 88 /* do nothing */ 89 } else if (len == 4) { 90 bswap32s((uint32_t *)mem_buf); 91 } else if (len == 8) { 92 bswap64s((uint64_t *)mem_buf); 93 } else if (len == 16) { 94 bswap128s((Int128 *)mem_buf); 95 } else { 96 g_assert_not_reached(); 97 } 98 #endif 99 } 100 101 /* 102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only 103 * expects whatever the target description contains. Due to a 104 * historical mishap the FP registers appear in between core integer 105 * regs and PC, MSR, CR, and so forth. We hack round this by giving 106 * the FP regs zero size when talking to a newer gdb. 107 */ 108 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) 110 { 111 CPUPPCState *env = cpu_env(cs); 112 uint8_t *mem_buf; 113 int r = ppc_gdb_register_len(n); 114 115 if (!r) { 116 return r; 117 } 118 119 if (n < 32) { 120 /* gprs */ 121 gdb_get_regl(buf, env->gpr[n]); 122 } else { 123 switch (n) { 124 case 64: 125 gdb_get_regl(buf, env->nip); 126 break; 127 case 65: 128 gdb_get_regl(buf, env->msr); 129 break; 130 case 66: 131 { 132 uint32_t cr = ppc_get_cr(env); 133 gdb_get_reg32(buf, cr); 134 break; 135 } 136 case 67: 137 gdb_get_regl(buf, env->lr); 138 break; 139 case 68: 140 gdb_get_regl(buf, env->ctr); 141 break; 142 case 69: 143 gdb_get_reg32(buf, cpu_read_xer(env)); 144 break; 145 } 146 } 147 mem_buf = buf->data + buf->len - r; 148 ppc_maybe_bswap_register(env, mem_buf, r); 149 return r; 150 } 151 152 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) 153 { 154 CPUPPCState *env = cpu_env(cs); 155 uint8_t *mem_buf; 156 int r = ppc_gdb_register_len_apple(n); 157 158 if (!r) { 159 return r; 160 } 161 162 if (n < 32) { 163 /* gprs */ 164 gdb_get_reg64(buf, env->gpr[n]); 165 } else if (n < 64) { 166 /* fprs */ 167 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); 168 } else if (n < 96) { 169 /* Altivec */ 170 gdb_get_reg64(buf, n - 64); 171 gdb_get_reg64(buf, 0); 172 } else { 173 switch (n) { 174 case 64 + 32: 175 gdb_get_reg64(buf, env->nip); 176 break; 177 case 65 + 32: 178 gdb_get_reg64(buf, env->msr); 179 break; 180 case 66 + 32: 181 { 182 uint32_t cr = ppc_get_cr(env); 183 gdb_get_reg32(buf, cr); 184 break; 185 } 186 case 67 + 32: 187 gdb_get_reg64(buf, env->lr); 188 break; 189 case 68 + 32: 190 gdb_get_reg64(buf, env->ctr); 191 break; 192 case 69 + 32: 193 gdb_get_reg32(buf, cpu_read_xer(env)); 194 break; 195 case 70 + 32: 196 gdb_get_reg64(buf, env->fpscr); 197 break; 198 } 199 } 200 mem_buf = buf->data + buf->len - r; 201 ppc_maybe_bswap_register(env, mem_buf, r); 202 return r; 203 } 204 205 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 206 { 207 CPUPPCState *env = cpu_env(cs); 208 int r = ppc_gdb_register_len(n); 209 210 if (!r) { 211 return r; 212 } 213 ppc_maybe_bswap_register(env, mem_buf, r); 214 if (n < 32) { 215 /* gprs */ 216 env->gpr[n] = ldtul_p(mem_buf); 217 } else if (n < 64) { 218 /* fprs */ 219 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 220 } else { 221 switch (n) { 222 case 64: 223 env->nip = ldtul_p(mem_buf); 224 break; 225 case 65: 226 ppc_store_msr(env, ldtul_p(mem_buf)); 227 break; 228 case 66: 229 { 230 uint32_t cr = ldl_p(mem_buf); 231 ppc_set_cr(env, cr); 232 break; 233 } 234 case 67: 235 env->lr = ldtul_p(mem_buf); 236 break; 237 case 68: 238 env->ctr = ldtul_p(mem_buf); 239 break; 240 case 69: 241 cpu_write_xer(env, ldl_p(mem_buf)); 242 break; 243 case 70: 244 /* fpscr */ 245 ppc_store_fpscr(env, ldtul_p(mem_buf)); 246 break; 247 } 248 } 249 return r; 250 } 251 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) 252 { 253 CPUPPCState *env = cpu_env(cs); 254 int r = ppc_gdb_register_len_apple(n); 255 256 if (!r) { 257 return r; 258 } 259 ppc_maybe_bswap_register(env, mem_buf, r); 260 if (n < 32) { 261 /* gprs */ 262 env->gpr[n] = ldq_p(mem_buf); 263 } else if (n < 64) { 264 /* fprs */ 265 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 266 } else { 267 switch (n) { 268 case 64 + 32: 269 env->nip = ldq_p(mem_buf); 270 break; 271 case 65 + 32: 272 ppc_store_msr(env, ldq_p(mem_buf)); 273 break; 274 case 66 + 32: 275 { 276 uint32_t cr = ldl_p(mem_buf); 277 ppc_set_cr(env, cr); 278 break; 279 } 280 case 67 + 32: 281 env->lr = ldq_p(mem_buf); 282 break; 283 case 68 + 32: 284 env->ctr = ldq_p(mem_buf); 285 break; 286 case 69 + 32: 287 cpu_write_xer(env, ldl_p(mem_buf)); 288 break; 289 case 70 + 32: 290 /* fpscr */ 291 ppc_store_fpscr(env, ldq_p(mem_buf)); 292 break; 293 } 294 } 295 return r; 296 } 297 298 #ifndef CONFIG_USER_ONLY 299 static void gdb_gen_spr_feature(CPUState *cs) 300 { 301 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 302 PowerPCCPU *cpu = POWERPC_CPU(cs); 303 CPUPPCState *env = &cpu->env; 304 GDBFeatureBuilder builder; 305 unsigned int num_regs = 0; 306 int i; 307 308 if (pcc->gdb_spr.xml) { 309 return; 310 } 311 312 gdb_feature_builder_init(&builder, &pcc->gdb_spr, 313 "org.qemu.power.spr", "power-spr.xml", 314 cs->gdb_num_regs); 315 316 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 317 ppc_spr_t *spr = &env->spr_cb[i]; 318 319 if (!spr->name) { 320 continue; 321 } 322 323 /* 324 * GDB identifies registers based on the order they are 325 * presented in the XML. These ids will not match QEMU's 326 * representation (which follows the PowerISA). 327 * 328 * Store the position of the current register description so 329 * we can make the correspondence later. 330 */ 331 spr->gdb_id = num_regs; 332 num_regs++; 333 334 gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), 335 TARGET_LONG_BITS, num_regs, 336 "int", "spr"); 337 } 338 339 gdb_feature_builder_end(&builder); 340 } 341 #endif 342 343 #if !defined(CONFIG_USER_ONLY) 344 static int gdb_find_spr_idx(CPUPPCState *env, int n) 345 { 346 int i; 347 348 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 349 ppc_spr_t *spr = &env->spr_cb[i]; 350 351 if (spr->name && spr->gdb_id == n) { 352 return i; 353 } 354 } 355 return -1; 356 } 357 358 static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) 359 { 360 PowerPCCPU *cpu = POWERPC_CPU(cs); 361 CPUPPCState *env = &cpu->env; 362 int reg; 363 int len; 364 365 reg = gdb_find_spr_idx(env, n); 366 if (reg < 0) { 367 return 0; 368 } 369 370 len = TARGET_LONG_SIZE; 371 372 /* Handle those SPRs that are not part of the env->spr[] array */ 373 target_ulong val; 374 switch (reg) { 375 #if defined(TARGET_PPC64) 376 case SPR_CFAR: 377 val = env->cfar; 378 break; 379 #endif 380 case SPR_HDEC: 381 val = cpu_ppc_load_hdecr(env); 382 break; 383 case SPR_TBL: 384 val = cpu_ppc_load_tbl(env); 385 break; 386 case SPR_TBU: 387 val = cpu_ppc_load_tbu(env); 388 break; 389 case SPR_DECR: 390 val = cpu_ppc_load_decr(env); 391 break; 392 default: 393 val = env->spr[reg]; 394 } 395 gdb_get_regl(buf, val); 396 397 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); 398 return len; 399 } 400 401 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) 402 { 403 PowerPCCPU *cpu = POWERPC_CPU(cs); 404 CPUPPCState *env = &cpu->env; 405 int reg; 406 int len; 407 408 reg = gdb_find_spr_idx(env, n); 409 if (reg < 0) { 410 return 0; 411 } 412 413 len = TARGET_LONG_SIZE; 414 ppc_maybe_bswap_register(env, mem_buf, len); 415 416 /* Handle those SPRs that are not part of the env->spr[] array */ 417 target_ulong val = ldn_p(mem_buf, len); 418 switch (reg) { 419 #if defined(TARGET_PPC64) 420 case SPR_CFAR: 421 env->cfar = val; 422 break; 423 #endif 424 default: 425 env->spr[reg] = val; 426 } 427 428 return len; 429 } 430 #endif 431 432 static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) 433 { 434 PowerPCCPU *cpu = POWERPC_CPU(cs); 435 CPUPPCState *env = &cpu->env; 436 uint8_t *mem_buf; 437 if (n < 32) { 438 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); 439 mem_buf = gdb_get_reg_ptr(buf, 8); 440 ppc_maybe_bswap_register(env, mem_buf, 8); 441 return 8; 442 } 443 if (n == 32) { 444 gdb_get_reg32(buf, env->fpscr); 445 mem_buf = gdb_get_reg_ptr(buf, 4); 446 ppc_maybe_bswap_register(env, mem_buf, 4); 447 return 4; 448 } 449 return 0; 450 } 451 452 static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) 453 { 454 PowerPCCPU *cpu = POWERPC_CPU(cs); 455 CPUPPCState *env = &cpu->env; 456 457 if (n < 32) { 458 ppc_maybe_bswap_register(env, mem_buf, 8); 459 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); 460 return 8; 461 } 462 if (n == 32) { 463 ppc_maybe_bswap_register(env, mem_buf, 4); 464 ppc_store_fpscr(env, ldl_p(mem_buf)); 465 return 4; 466 } 467 return 0; 468 } 469 470 static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) 471 { 472 PowerPCCPU *cpu = POWERPC_CPU(cs); 473 CPUPPCState *env = &cpu->env; 474 uint8_t *mem_buf; 475 476 if (n < 32) { 477 ppc_avr_t *avr = cpu_avr_ptr(env, n); 478 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1)); 479 mem_buf = gdb_get_reg_ptr(buf, 16); 480 ppc_maybe_bswap_register(env, mem_buf, 16); 481 return 16; 482 } 483 if (n == 32) { 484 gdb_get_reg32(buf, ppc_get_vscr(env)); 485 mem_buf = gdb_get_reg_ptr(buf, 4); 486 ppc_maybe_bswap_register(env, mem_buf, 4); 487 return 4; 488 } 489 if (n == 33) { 490 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); 491 mem_buf = gdb_get_reg_ptr(buf, 4); 492 ppc_maybe_bswap_register(env, mem_buf, 4); 493 return 4; 494 } 495 return 0; 496 } 497 498 static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) 499 { 500 PowerPCCPU *cpu = POWERPC_CPU(cs); 501 CPUPPCState *env = &cpu->env; 502 503 if (n < 32) { 504 ppc_avr_t *avr = cpu_avr_ptr(env, n); 505 ppc_maybe_bswap_register(env, mem_buf, 16); 506 avr->VsrD(0) = ldq_p(mem_buf); 507 avr->VsrD(1) = ldq_p(mem_buf + 8); 508 return 16; 509 } 510 if (n == 32) { 511 ppc_maybe_bswap_register(env, mem_buf, 4); 512 ppc_store_vscr(env, ldl_p(mem_buf)); 513 return 4; 514 } 515 if (n == 33) { 516 ppc_maybe_bswap_register(env, mem_buf, 4); 517 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 518 return 4; 519 } 520 return 0; 521 } 522 523 static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) 524 { 525 PowerPCCPU *cpu = POWERPC_CPU(cs); 526 CPUPPCState *env = &cpu->env; 527 528 if (n < 32) { 529 #if defined(TARGET_PPC64) 530 gdb_get_reg32(buf, env->gpr[n] >> 32); 531 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 532 #else 533 gdb_get_reg32(buf, env->gprh[n]); 534 #endif 535 return 4; 536 } 537 if (n == 32) { 538 gdb_get_reg64(buf, env->spe_acc); 539 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 540 return 8; 541 } 542 if (n == 33) { 543 gdb_get_reg32(buf, env->spe_fscr); 544 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 545 return 4; 546 } 547 return 0; 548 } 549 550 static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) 551 { 552 PowerPCCPU *cpu = POWERPC_CPU(cs); 553 CPUPPCState *env = &cpu->env; 554 555 if (n < 32) { 556 #if defined(TARGET_PPC64) 557 target_ulong lo = (uint32_t)env->gpr[n]; 558 target_ulong hi; 559 560 ppc_maybe_bswap_register(env, mem_buf, 4); 561 562 hi = (target_ulong)ldl_p(mem_buf) << 32; 563 env->gpr[n] = lo | hi; 564 #else 565 env->gprh[n] = ldl_p(mem_buf); 566 #endif 567 return 4; 568 } 569 if (n == 32) { 570 ppc_maybe_bswap_register(env, mem_buf, 8); 571 env->spe_acc = ldq_p(mem_buf); 572 return 8; 573 } 574 if (n == 33) { 575 ppc_maybe_bswap_register(env, mem_buf, 4); 576 env->spe_fscr = ldl_p(mem_buf); 577 return 4; 578 } 579 return 0; 580 } 581 582 static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) 583 { 584 PowerPCCPU *cpu = POWERPC_CPU(cs); 585 CPUPPCState *env = &cpu->env; 586 587 if (n < 32) { 588 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); 589 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 590 return 8; 591 } 592 return 0; 593 } 594 595 static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) 596 { 597 PowerPCCPU *cpu = POWERPC_CPU(cs); 598 CPUPPCState *env = &cpu->env; 599 600 if (n < 32) { 601 ppc_maybe_bswap_register(env, mem_buf, 8); 602 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); 603 return 8; 604 } 605 return 0; 606 } 607 608 const gchar *ppc_gdb_arch_name(CPUState *cs) 609 { 610 #if defined(TARGET_PPC64) 611 return "powerpc:common64"; 612 #else 613 return "powerpc:common"; 614 #endif 615 } 616 617 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 618 { 619 if (pcc->insns_flags & PPC_FLOAT) { 620 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 621 gdb_find_static_feature("power-fpu.xml"), 0); 622 } 623 if (pcc->insns_flags & PPC_ALTIVEC) { 624 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, 625 gdb_find_static_feature("power-altivec.xml"), 626 0); 627 } 628 if (pcc->insns_flags & PPC_SPE) { 629 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, 630 gdb_find_static_feature("power-spe.xml"), 0); 631 } 632 if (pcc->insns_flags2 & PPC2_VSX) { 633 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 634 gdb_find_static_feature("power-vsx.xml"), 0); 635 } 636 #ifndef CONFIG_USER_ONLY 637 gdb_gen_spr_feature(cs); 638 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, 639 &pcc->gdb_spr, 0); 640 #endif 641 } 642