1 /* 2 * PowerPC gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 #include "gdbstub/helpers.h" 24 #include "internal.h" 25 26 static int ppc_gdb_register_len_apple(int n) 27 { 28 switch (n) { 29 case 0 ... 31: 30 /* gprs */ 31 return 8; 32 case 32 ... 63: 33 /* fprs */ 34 return 8; 35 case 64 ... 95: 36 return 16; 37 case 64 + 32: /* nip */ 38 case 65 + 32: /* msr */ 39 case 67 + 32: /* lr */ 40 case 68 + 32: /* ctr */ 41 case 70 + 32: /* fpscr */ 42 return 8; 43 case 66 + 32: /* cr */ 44 case 69 + 32: /* xer */ 45 return 4; 46 default: 47 return 0; 48 } 49 } 50 51 static int ppc_gdb_register_len(int n) 52 { 53 switch (n) { 54 case 0 ... 31: 55 /* gprs */ 56 return sizeof(target_ulong); 57 case 66: 58 /* cr */ 59 case 69: 60 /* xer */ 61 return 4; 62 case 64: 63 /* nip */ 64 case 65: 65 /* msr */ 66 case 67: 67 /* lr */ 68 case 68: 69 /* ctr */ 70 return sizeof(target_ulong); 71 default: 72 return 0; 73 } 74 } 75 76 /* 77 * We need to present the registers to gdb in the "current" memory 78 * ordering. For user-only mode we get this for free; 79 * TARGET_BIG_ENDIAN is set to the proper ordering for the 80 * binary, and cannot be changed. For system mode, 81 * TARGET_BIG_ENDIAN is always set, and we must check the current 82 * mode of the chip to see if we're running in little-endian. 83 */ 84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) 85 { 86 #ifndef CONFIG_USER_ONLY 87 if (!FIELD_EX64(env->msr, MSR, LE)) { 88 /* do nothing */ 89 } else if (len == 4) { 90 bswap32s((uint32_t *)mem_buf); 91 } else if (len == 8) { 92 bswap64s((uint64_t *)mem_buf); 93 } else if (len == 16) { 94 bswap128s((Int128 *)mem_buf); 95 } else { 96 g_assert_not_reached(); 97 } 98 #endif 99 } 100 101 /* 102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only 103 * expects whatever the target description contains. Due to a 104 * historical mishap the FP registers appear in between core integer 105 * regs and PC, MSR, CR, and so forth. We hack round this by giving 106 * the FP regs zero size when talking to a newer gdb. 107 */ 108 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) 110 { 111 CPUPPCState *env = cpu_env(cs); 112 uint8_t *mem_buf; 113 int r = ppc_gdb_register_len(n); 114 115 if (!r) { 116 return r; 117 } 118 119 if (n < 32) { 120 /* gprs */ 121 gdb_get_regl(buf, env->gpr[n]); 122 } else { 123 switch (n) { 124 case 64: 125 gdb_get_regl(buf, env->nip); 126 break; 127 case 65: 128 gdb_get_regl(buf, env->msr); 129 break; 130 case 66: 131 { 132 uint32_t cr = ppc_get_cr(env); 133 gdb_get_reg32(buf, cr); 134 break; 135 } 136 case 67: 137 gdb_get_regl(buf, env->lr); 138 break; 139 case 68: 140 gdb_get_regl(buf, env->ctr); 141 break; 142 case 69: 143 gdb_get_reg32(buf, cpu_read_xer(env)); 144 break; 145 } 146 } 147 mem_buf = buf->data + buf->len - r; 148 ppc_maybe_bswap_register(env, mem_buf, r); 149 return r; 150 } 151 152 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) 153 { 154 CPUPPCState *env = cpu_env(cs); 155 uint8_t *mem_buf; 156 int r = ppc_gdb_register_len_apple(n); 157 158 if (!r) { 159 return r; 160 } 161 162 if (n < 32) { 163 /* gprs */ 164 gdb_get_reg64(buf, env->gpr[n]); 165 } else if (n < 64) { 166 /* fprs */ 167 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); 168 } else if (n < 96) { 169 /* Altivec */ 170 gdb_get_reg64(buf, n - 64); 171 gdb_get_reg64(buf, 0); 172 } else { 173 switch (n) { 174 case 64 + 32: 175 gdb_get_reg64(buf, env->nip); 176 break; 177 case 65 + 32: 178 gdb_get_reg64(buf, env->msr); 179 break; 180 case 66 + 32: 181 { 182 uint32_t cr = ppc_get_cr(env); 183 gdb_get_reg32(buf, cr); 184 break; 185 } 186 case 67 + 32: 187 gdb_get_reg64(buf, env->lr); 188 break; 189 case 68 + 32: 190 gdb_get_reg64(buf, env->ctr); 191 break; 192 case 69 + 32: 193 gdb_get_reg32(buf, cpu_read_xer(env)); 194 break; 195 case 70 + 32: 196 gdb_get_reg64(buf, env->fpscr); 197 break; 198 } 199 } 200 mem_buf = buf->data + buf->len - r; 201 ppc_maybe_bswap_register(env, mem_buf, r); 202 return r; 203 } 204 205 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 206 { 207 CPUPPCState *env = cpu_env(cs); 208 int r = ppc_gdb_register_len(n); 209 210 if (!r) { 211 return r; 212 } 213 ppc_maybe_bswap_register(env, mem_buf, r); 214 if (n < 32) { 215 /* gprs */ 216 env->gpr[n] = ldtul_p(mem_buf); 217 } else if (n < 64) { 218 /* fprs */ 219 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 220 } else { 221 switch (n) { 222 case 64: 223 env->nip = ldtul_p(mem_buf); 224 break; 225 case 65: 226 ppc_store_msr(env, ldtul_p(mem_buf)); 227 break; 228 case 66: 229 { 230 uint32_t cr = ldl_p(mem_buf); 231 ppc_set_cr(env, cr); 232 break; 233 } 234 case 67: 235 env->lr = ldtul_p(mem_buf); 236 break; 237 case 68: 238 env->ctr = ldtul_p(mem_buf); 239 break; 240 case 69: 241 cpu_write_xer(env, ldl_p(mem_buf)); 242 break; 243 case 70: 244 /* fpscr */ 245 ppc_store_fpscr(env, ldtul_p(mem_buf)); 246 break; 247 } 248 } 249 return r; 250 } 251 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) 252 { 253 CPUPPCState *env = cpu_env(cs); 254 int r = ppc_gdb_register_len_apple(n); 255 256 if (!r) { 257 return r; 258 } 259 ppc_maybe_bswap_register(env, mem_buf, r); 260 if (n < 32) { 261 /* gprs */ 262 env->gpr[n] = ldq_p(mem_buf); 263 } else if (n < 64) { 264 /* fprs */ 265 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 266 } else { 267 switch (n) { 268 case 64 + 32: 269 env->nip = ldq_p(mem_buf); 270 break; 271 case 65 + 32: 272 ppc_store_msr(env, ldq_p(mem_buf)); 273 break; 274 case 66 + 32: 275 { 276 uint32_t cr = ldl_p(mem_buf); 277 ppc_set_cr(env, cr); 278 break; 279 } 280 case 67 + 32: 281 env->lr = ldq_p(mem_buf); 282 break; 283 case 68 + 32: 284 env->ctr = ldq_p(mem_buf); 285 break; 286 case 69 + 32: 287 cpu_write_xer(env, ldl_p(mem_buf)); 288 break; 289 case 70 + 32: 290 /* fpscr */ 291 ppc_store_fpscr(env, ldq_p(mem_buf)); 292 break; 293 } 294 } 295 return r; 296 } 297 298 #ifndef CONFIG_USER_ONLY 299 static void gdb_gen_spr_feature(CPUState *cs) 300 { 301 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 302 PowerPCCPU *cpu = POWERPC_CPU(cs); 303 CPUPPCState *env = &cpu->env; 304 GDBFeatureBuilder builder; 305 unsigned int num_regs = 0; 306 int i; 307 308 if (pcc->gdb_spr.xml) { 309 return; 310 } 311 312 gdb_feature_builder_init(&builder, &pcc->gdb_spr, 313 "org.qemu.power.spr", "power-spr.xml", 314 cs->gdb_num_regs); 315 316 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 317 ppc_spr_t *spr = &env->spr_cb[i]; 318 319 if (!spr->name) { 320 continue; 321 } 322 323 gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), 324 TARGET_LONG_BITS, num_regs, 325 "int", "spr"); 326 /* 327 * GDB identifies registers based on the order they are 328 * presented in the XML. These ids will not match QEMU's 329 * representation (which follows the PowerISA). 330 * 331 * Store the position of the current register description so 332 * we can make the correspondence later. 333 */ 334 spr->gdb_id = num_regs; 335 num_regs++; 336 } 337 338 gdb_feature_builder_end(&builder); 339 } 340 #endif 341 342 #if !defined(CONFIG_USER_ONLY) 343 static int gdb_find_spr_idx(CPUPPCState *env, int n) 344 { 345 int i; 346 347 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 348 ppc_spr_t *spr = &env->spr_cb[i]; 349 350 if (spr->name && spr->gdb_id == n) { 351 return i; 352 } 353 } 354 return -1; 355 } 356 357 static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) 358 { 359 PowerPCCPU *cpu = POWERPC_CPU(cs); 360 CPUPPCState *env = &cpu->env; 361 int reg; 362 int len; 363 364 reg = gdb_find_spr_idx(env, n); 365 if (reg < 0) { 366 return 0; 367 } 368 369 len = TARGET_LONG_SIZE; 370 371 /* Handle those SPRs that are not part of the env->spr[] array */ 372 target_ulong val; 373 switch (reg) { 374 #if defined(TARGET_PPC64) 375 case SPR_CFAR: 376 val = env->cfar; 377 break; 378 #endif 379 case SPR_HDEC: 380 val = cpu_ppc_load_hdecr(env); 381 break; 382 case SPR_TBL: 383 val = cpu_ppc_load_tbl(env); 384 break; 385 case SPR_TBU: 386 val = cpu_ppc_load_tbu(env); 387 break; 388 case SPR_DECR: 389 val = cpu_ppc_load_decr(env); 390 break; 391 default: 392 val = env->spr[reg]; 393 } 394 gdb_get_regl(buf, val); 395 396 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); 397 return len; 398 } 399 400 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) 401 { 402 PowerPCCPU *cpu = POWERPC_CPU(cs); 403 CPUPPCState *env = &cpu->env; 404 int reg; 405 int len; 406 407 reg = gdb_find_spr_idx(env, n); 408 if (reg < 0) { 409 return 0; 410 } 411 412 len = TARGET_LONG_SIZE; 413 ppc_maybe_bswap_register(env, mem_buf, len); 414 415 /* Handle those SPRs that are not part of the env->spr[] array */ 416 target_ulong val = ldn_p(mem_buf, len); 417 switch (reg) { 418 #if defined(TARGET_PPC64) 419 case SPR_CFAR: 420 env->cfar = val; 421 break; 422 #endif 423 default: 424 env->spr[reg] = val; 425 } 426 427 return len; 428 } 429 #endif 430 431 static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) 432 { 433 PowerPCCPU *cpu = POWERPC_CPU(cs); 434 CPUPPCState *env = &cpu->env; 435 uint8_t *mem_buf; 436 if (n < 32) { 437 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); 438 mem_buf = gdb_get_reg_ptr(buf, 8); 439 ppc_maybe_bswap_register(env, mem_buf, 8); 440 return 8; 441 } 442 if (n == 32) { 443 gdb_get_reg32(buf, env->fpscr); 444 mem_buf = gdb_get_reg_ptr(buf, 4); 445 ppc_maybe_bswap_register(env, mem_buf, 4); 446 return 4; 447 } 448 return 0; 449 } 450 451 static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) 452 { 453 PowerPCCPU *cpu = POWERPC_CPU(cs); 454 CPUPPCState *env = &cpu->env; 455 456 if (n < 32) { 457 ppc_maybe_bswap_register(env, mem_buf, 8); 458 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); 459 return 8; 460 } 461 if (n == 32) { 462 ppc_maybe_bswap_register(env, mem_buf, 4); 463 ppc_store_fpscr(env, ldl_p(mem_buf)); 464 return 4; 465 } 466 return 0; 467 } 468 469 static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) 470 { 471 PowerPCCPU *cpu = POWERPC_CPU(cs); 472 CPUPPCState *env = &cpu->env; 473 uint8_t *mem_buf; 474 475 if (n < 32) { 476 ppc_avr_t *avr = cpu_avr_ptr(env, n); 477 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1)); 478 mem_buf = gdb_get_reg_ptr(buf, 16); 479 ppc_maybe_bswap_register(env, mem_buf, 16); 480 return 16; 481 } 482 if (n == 32) { 483 gdb_get_reg32(buf, ppc_get_vscr(env)); 484 mem_buf = gdb_get_reg_ptr(buf, 4); 485 ppc_maybe_bswap_register(env, mem_buf, 4); 486 return 4; 487 } 488 if (n == 33) { 489 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); 490 mem_buf = gdb_get_reg_ptr(buf, 4); 491 ppc_maybe_bswap_register(env, mem_buf, 4); 492 return 4; 493 } 494 return 0; 495 } 496 497 static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) 498 { 499 PowerPCCPU *cpu = POWERPC_CPU(cs); 500 CPUPPCState *env = &cpu->env; 501 502 if (n < 32) { 503 ppc_avr_t *avr = cpu_avr_ptr(env, n); 504 ppc_maybe_bswap_register(env, mem_buf, 16); 505 avr->VsrD(0) = ldq_p(mem_buf); 506 avr->VsrD(1) = ldq_p(mem_buf + 8); 507 return 16; 508 } 509 if (n == 32) { 510 ppc_maybe_bswap_register(env, mem_buf, 4); 511 ppc_store_vscr(env, ldl_p(mem_buf)); 512 return 4; 513 } 514 if (n == 33) { 515 ppc_maybe_bswap_register(env, mem_buf, 4); 516 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 517 return 4; 518 } 519 return 0; 520 } 521 522 static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) 523 { 524 PowerPCCPU *cpu = POWERPC_CPU(cs); 525 CPUPPCState *env = &cpu->env; 526 527 if (n < 32) { 528 #if defined(TARGET_PPC64) 529 gdb_get_reg32(buf, env->gpr[n] >> 32); 530 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 531 #else 532 gdb_get_reg32(buf, env->gprh[n]); 533 #endif 534 return 4; 535 } 536 if (n == 32) { 537 gdb_get_reg64(buf, env->spe_acc); 538 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 539 return 8; 540 } 541 if (n == 33) { 542 gdb_get_reg32(buf, env->spe_fscr); 543 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 544 return 4; 545 } 546 return 0; 547 } 548 549 static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) 550 { 551 PowerPCCPU *cpu = POWERPC_CPU(cs); 552 CPUPPCState *env = &cpu->env; 553 554 if (n < 32) { 555 #if defined(TARGET_PPC64) 556 target_ulong lo = (uint32_t)env->gpr[n]; 557 target_ulong hi; 558 559 ppc_maybe_bswap_register(env, mem_buf, 4); 560 561 hi = (target_ulong)ldl_p(mem_buf) << 32; 562 env->gpr[n] = lo | hi; 563 #else 564 env->gprh[n] = ldl_p(mem_buf); 565 #endif 566 return 4; 567 } 568 if (n == 32) { 569 ppc_maybe_bswap_register(env, mem_buf, 8); 570 env->spe_acc = ldq_p(mem_buf); 571 return 8; 572 } 573 if (n == 33) { 574 ppc_maybe_bswap_register(env, mem_buf, 4); 575 env->spe_fscr = ldl_p(mem_buf); 576 return 4; 577 } 578 return 0; 579 } 580 581 static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) 582 { 583 PowerPCCPU *cpu = POWERPC_CPU(cs); 584 CPUPPCState *env = &cpu->env; 585 586 if (n < 32) { 587 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); 588 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 589 return 8; 590 } 591 return 0; 592 } 593 594 static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) 595 { 596 PowerPCCPU *cpu = POWERPC_CPU(cs); 597 CPUPPCState *env = &cpu->env; 598 599 if (n < 32) { 600 ppc_maybe_bswap_register(env, mem_buf, 8); 601 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); 602 return 8; 603 } 604 return 0; 605 } 606 607 const gchar *ppc_gdb_arch_name(CPUState *cs) 608 { 609 #if defined(TARGET_PPC64) 610 return "powerpc:common64"; 611 #else 612 return "powerpc:common"; 613 #endif 614 } 615 616 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 617 { 618 if (pcc->insns_flags & PPC_FLOAT) { 619 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 620 gdb_find_static_feature("power-fpu.xml"), 0); 621 } 622 if (pcc->insns_flags & PPC_ALTIVEC) { 623 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, 624 gdb_find_static_feature("power-altivec.xml"), 625 0); 626 } 627 if (pcc->insns_flags & PPC_SPE) { 628 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, 629 gdb_find_static_feature("power-spe.xml"), 0); 630 } 631 if (pcc->insns_flags2 & PPC2_VSX) { 632 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 633 gdb_find_static_feature("power-vsx.xml"), 0); 634 } 635 #ifndef CONFIG_USER_ONLY 636 gdb_gen_spr_feature(cs); 637 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, 638 &pcc->gdb_spr, 0); 639 #endif 640 } 641