1 /* 2 * PowerPC gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 #include "gdbstub/helpers.h" 24 #include "internal.h" 25 26 static int ppc_gdb_register_len_apple(int n) 27 { 28 switch (n) { 29 case 0 ... 31: 30 /* gprs */ 31 return 8; 32 case 32 ... 63: 33 /* fprs */ 34 return 8; 35 case 64 ... 95: 36 return 16; 37 case 64 + 32: /* nip */ 38 case 65 + 32: /* msr */ 39 case 67 + 32: /* lr */ 40 case 68 + 32: /* ctr */ 41 case 70 + 32: /* fpscr */ 42 return 8; 43 case 66 + 32: /* cr */ 44 case 69 + 32: /* xer */ 45 return 4; 46 default: 47 return 0; 48 } 49 } 50 51 static int ppc_gdb_register_len(int n) 52 { 53 switch (n) { 54 case 0 ... 31: 55 /* gprs */ 56 return sizeof(target_ulong); 57 case 66: 58 /* cr */ 59 case 69: 60 /* xer */ 61 return 4; 62 case 64: 63 /* nip */ 64 case 65: 65 /* msr */ 66 case 67: 67 /* lr */ 68 case 68: 69 /* ctr */ 70 return sizeof(target_ulong); 71 default: 72 return 0; 73 } 74 } 75 76 /* 77 * We need to present the registers to gdb in the "current" memory 78 * ordering. For user-only mode we get this for free; 79 * TARGET_BIG_ENDIAN is set to the proper ordering for the 80 * binary, and cannot be changed. For system mode, 81 * TARGET_BIG_ENDIAN is always set, and we must check the current 82 * mode of the chip to see if we're running in little-endian. 83 */ 84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) 85 { 86 #ifndef CONFIG_USER_ONLY 87 if (!FIELD_EX64(env->msr, MSR, LE)) { 88 /* do nothing */ 89 } else if (len == 4) { 90 bswap32s((uint32_t *)mem_buf); 91 } else if (len == 8) { 92 bswap64s((uint64_t *)mem_buf); 93 } else if (len == 16) { 94 bswap128s((Int128 *)mem_buf); 95 } else { 96 g_assert_not_reached(); 97 } 98 #endif 99 } 100 101 /* 102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only 103 * expects whatever the target description contains. Due to a 104 * historical mishap the FP registers appear in between core integer 105 * regs and PC, MSR, CR, and so forth. We hack round this by giving 106 * the FP regs zero size when talking to a newer gdb. 107 */ 108 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) 110 { 111 PowerPCCPU *cpu = POWERPC_CPU(cs); 112 CPUPPCState *env = &cpu->env; 113 uint8_t *mem_buf; 114 int r = ppc_gdb_register_len(n); 115 116 if (!r) { 117 return r; 118 } 119 120 if (n < 32) { 121 /* gprs */ 122 gdb_get_regl(buf, env->gpr[n]); 123 } else { 124 switch (n) { 125 case 64: 126 gdb_get_regl(buf, env->nip); 127 break; 128 case 65: 129 gdb_get_regl(buf, env->msr); 130 break; 131 case 66: 132 { 133 uint32_t cr = ppc_get_cr(env); 134 gdb_get_reg32(buf, cr); 135 break; 136 } 137 case 67: 138 gdb_get_regl(buf, env->lr); 139 break; 140 case 68: 141 gdb_get_regl(buf, env->ctr); 142 break; 143 case 69: 144 gdb_get_reg32(buf, cpu_read_xer(env)); 145 break; 146 } 147 } 148 mem_buf = buf->data + buf->len - r; 149 ppc_maybe_bswap_register(env, mem_buf, r); 150 return r; 151 } 152 153 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) 154 { 155 PowerPCCPU *cpu = POWERPC_CPU(cs); 156 CPUPPCState *env = &cpu->env; 157 uint8_t *mem_buf; 158 int r = ppc_gdb_register_len_apple(n); 159 160 if (!r) { 161 return r; 162 } 163 164 if (n < 32) { 165 /* gprs */ 166 gdb_get_reg64(buf, env->gpr[n]); 167 } else if (n < 64) { 168 /* fprs */ 169 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); 170 } else if (n < 96) { 171 /* Altivec */ 172 gdb_get_reg64(buf, n - 64); 173 gdb_get_reg64(buf, 0); 174 } else { 175 switch (n) { 176 case 64 + 32: 177 gdb_get_reg64(buf, env->nip); 178 break; 179 case 65 + 32: 180 gdb_get_reg64(buf, env->msr); 181 break; 182 case 66 + 32: 183 { 184 uint32_t cr = ppc_get_cr(env); 185 gdb_get_reg32(buf, cr); 186 break; 187 } 188 case 67 + 32: 189 gdb_get_reg64(buf, env->lr); 190 break; 191 case 68 + 32: 192 gdb_get_reg64(buf, env->ctr); 193 break; 194 case 69 + 32: 195 gdb_get_reg32(buf, cpu_read_xer(env)); 196 break; 197 case 70 + 32: 198 gdb_get_reg64(buf, env->fpscr); 199 break; 200 } 201 } 202 mem_buf = buf->data + buf->len - r; 203 ppc_maybe_bswap_register(env, mem_buf, r); 204 return r; 205 } 206 207 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 208 { 209 PowerPCCPU *cpu = POWERPC_CPU(cs); 210 CPUPPCState *env = &cpu->env; 211 int r = ppc_gdb_register_len(n); 212 213 if (!r) { 214 return r; 215 } 216 ppc_maybe_bswap_register(env, mem_buf, r); 217 if (n < 32) { 218 /* gprs */ 219 env->gpr[n] = ldtul_p(mem_buf); 220 } else if (n < 64) { 221 /* fprs */ 222 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 223 } else { 224 switch (n) { 225 case 64: 226 env->nip = ldtul_p(mem_buf); 227 break; 228 case 65: 229 ppc_store_msr(env, ldtul_p(mem_buf)); 230 break; 231 case 66: 232 { 233 uint32_t cr = ldl_p(mem_buf); 234 ppc_set_cr(env, cr); 235 break; 236 } 237 case 67: 238 env->lr = ldtul_p(mem_buf); 239 break; 240 case 68: 241 env->ctr = ldtul_p(mem_buf); 242 break; 243 case 69: 244 cpu_write_xer(env, ldl_p(mem_buf)); 245 break; 246 case 70: 247 /* fpscr */ 248 ppc_store_fpscr(env, ldtul_p(mem_buf)); 249 break; 250 } 251 } 252 return r; 253 } 254 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) 255 { 256 PowerPCCPU *cpu = POWERPC_CPU(cs); 257 CPUPPCState *env = &cpu->env; 258 int r = ppc_gdb_register_len_apple(n); 259 260 if (!r) { 261 return r; 262 } 263 ppc_maybe_bswap_register(env, mem_buf, r); 264 if (n < 32) { 265 /* gprs */ 266 env->gpr[n] = ldq_p(mem_buf); 267 } else if (n < 64) { 268 /* fprs */ 269 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 270 } else { 271 switch (n) { 272 case 64 + 32: 273 env->nip = ldq_p(mem_buf); 274 break; 275 case 65 + 32: 276 ppc_store_msr(env, ldq_p(mem_buf)); 277 break; 278 case 66 + 32: 279 { 280 uint32_t cr = ldl_p(mem_buf); 281 ppc_set_cr(env, cr); 282 break; 283 } 284 case 67 + 32: 285 env->lr = ldq_p(mem_buf); 286 break; 287 case 68 + 32: 288 env->ctr = ldq_p(mem_buf); 289 break; 290 case 69 + 32: 291 cpu_write_xer(env, ldl_p(mem_buf)); 292 break; 293 case 70 + 32: 294 /* fpscr */ 295 ppc_store_fpscr(env, ldq_p(mem_buf)); 296 break; 297 } 298 } 299 return r; 300 } 301 302 #ifndef CONFIG_USER_ONLY 303 static void gdb_gen_spr_feature(CPUState *cs) 304 { 305 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 306 PowerPCCPU *cpu = POWERPC_CPU(cs); 307 CPUPPCState *env = &cpu->env; 308 GDBFeatureBuilder builder; 309 unsigned int num_regs = 0; 310 int i; 311 312 if (pcc->gdb_spr.xml) { 313 return; 314 } 315 316 gdb_feature_builder_init(&builder, &pcc->gdb_spr, 317 "org.qemu.power.spr", "power-spr.xml", 318 cs->gdb_num_regs); 319 320 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 321 ppc_spr_t *spr = &env->spr_cb[i]; 322 323 if (!spr->name) { 324 continue; 325 } 326 327 gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), 328 TARGET_LONG_BITS, num_regs, 329 "int", "spr"); 330 /* 331 * GDB identifies registers based on the order they are 332 * presented in the XML. These ids will not match QEMU's 333 * representation (which follows the PowerISA). 334 * 335 * Store the position of the current register description so 336 * we can make the correspondence later. 337 */ 338 spr->gdb_id = num_regs; 339 num_regs++; 340 } 341 342 gdb_feature_builder_end(&builder); 343 } 344 #endif 345 346 #if !defined(CONFIG_USER_ONLY) 347 static int gdb_find_spr_idx(CPUPPCState *env, int n) 348 { 349 int i; 350 351 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 352 ppc_spr_t *spr = &env->spr_cb[i]; 353 354 if (spr->name && spr->gdb_id == n) { 355 return i; 356 } 357 } 358 return -1; 359 } 360 361 static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) 362 { 363 PowerPCCPU *cpu = POWERPC_CPU(cs); 364 CPUPPCState *env = &cpu->env; 365 int reg; 366 int len; 367 368 reg = gdb_find_spr_idx(env, n); 369 if (reg < 0) { 370 return 0; 371 } 372 373 len = TARGET_LONG_SIZE; 374 375 /* Handle those SPRs that are not part of the env->spr[] array */ 376 target_ulong val; 377 switch (reg) { 378 #if defined(TARGET_PPC64) 379 case SPR_CFAR: 380 val = env->cfar; 381 break; 382 #endif 383 case SPR_HDEC: 384 val = cpu_ppc_load_hdecr(env); 385 break; 386 case SPR_TBL: 387 val = cpu_ppc_load_tbl(env); 388 break; 389 case SPR_TBU: 390 val = cpu_ppc_load_tbu(env); 391 break; 392 case SPR_DECR: 393 val = cpu_ppc_load_decr(env); 394 break; 395 default: 396 val = env->spr[reg]; 397 } 398 gdb_get_regl(buf, val); 399 400 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); 401 return len; 402 } 403 404 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) 405 { 406 PowerPCCPU *cpu = POWERPC_CPU(cs); 407 CPUPPCState *env = &cpu->env; 408 int reg; 409 int len; 410 411 reg = gdb_find_spr_idx(env, n); 412 if (reg < 0) { 413 return 0; 414 } 415 416 len = TARGET_LONG_SIZE; 417 ppc_maybe_bswap_register(env, mem_buf, len); 418 419 /* Handle those SPRs that are not part of the env->spr[] array */ 420 target_ulong val = ldn_p(mem_buf, len); 421 switch (reg) { 422 #if defined(TARGET_PPC64) 423 case SPR_CFAR: 424 env->cfar = val; 425 break; 426 #endif 427 default: 428 env->spr[reg] = val; 429 } 430 431 return len; 432 } 433 #endif 434 435 static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) 436 { 437 PowerPCCPU *cpu = POWERPC_CPU(cs); 438 CPUPPCState *env = &cpu->env; 439 uint8_t *mem_buf; 440 if (n < 32) { 441 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); 442 mem_buf = gdb_get_reg_ptr(buf, 8); 443 ppc_maybe_bswap_register(env, mem_buf, 8); 444 return 8; 445 } 446 if (n == 32) { 447 gdb_get_reg32(buf, env->fpscr); 448 mem_buf = gdb_get_reg_ptr(buf, 4); 449 ppc_maybe_bswap_register(env, mem_buf, 4); 450 return 4; 451 } 452 return 0; 453 } 454 455 static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) 456 { 457 PowerPCCPU *cpu = POWERPC_CPU(cs); 458 CPUPPCState *env = &cpu->env; 459 460 if (n < 32) { 461 ppc_maybe_bswap_register(env, mem_buf, 8); 462 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); 463 return 8; 464 } 465 if (n == 32) { 466 ppc_maybe_bswap_register(env, mem_buf, 4); 467 ppc_store_fpscr(env, ldl_p(mem_buf)); 468 return 4; 469 } 470 return 0; 471 } 472 473 static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) 474 { 475 PowerPCCPU *cpu = POWERPC_CPU(cs); 476 CPUPPCState *env = &cpu->env; 477 uint8_t *mem_buf; 478 479 if (n < 32) { 480 ppc_avr_t *avr = cpu_avr_ptr(env, n); 481 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1)); 482 mem_buf = gdb_get_reg_ptr(buf, 16); 483 ppc_maybe_bswap_register(env, mem_buf, 16); 484 return 16; 485 } 486 if (n == 32) { 487 gdb_get_reg32(buf, ppc_get_vscr(env)); 488 mem_buf = gdb_get_reg_ptr(buf, 4); 489 ppc_maybe_bswap_register(env, mem_buf, 4); 490 return 4; 491 } 492 if (n == 33) { 493 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); 494 mem_buf = gdb_get_reg_ptr(buf, 4); 495 ppc_maybe_bswap_register(env, mem_buf, 4); 496 return 4; 497 } 498 return 0; 499 } 500 501 static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) 502 { 503 PowerPCCPU *cpu = POWERPC_CPU(cs); 504 CPUPPCState *env = &cpu->env; 505 506 if (n < 32) { 507 ppc_avr_t *avr = cpu_avr_ptr(env, n); 508 ppc_maybe_bswap_register(env, mem_buf, 16); 509 avr->VsrD(0) = ldq_p(mem_buf); 510 avr->VsrD(1) = ldq_p(mem_buf + 8); 511 return 16; 512 } 513 if (n == 32) { 514 ppc_maybe_bswap_register(env, mem_buf, 4); 515 ppc_store_vscr(env, ldl_p(mem_buf)); 516 return 4; 517 } 518 if (n == 33) { 519 ppc_maybe_bswap_register(env, mem_buf, 4); 520 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 521 return 4; 522 } 523 return 0; 524 } 525 526 static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) 527 { 528 PowerPCCPU *cpu = POWERPC_CPU(cs); 529 CPUPPCState *env = &cpu->env; 530 531 if (n < 32) { 532 #if defined(TARGET_PPC64) 533 gdb_get_reg32(buf, env->gpr[n] >> 32); 534 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 535 #else 536 gdb_get_reg32(buf, env->gprh[n]); 537 #endif 538 return 4; 539 } 540 if (n == 32) { 541 gdb_get_reg64(buf, env->spe_acc); 542 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 543 return 8; 544 } 545 if (n == 33) { 546 gdb_get_reg32(buf, env->spe_fscr); 547 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 548 return 4; 549 } 550 return 0; 551 } 552 553 static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) 554 { 555 PowerPCCPU *cpu = POWERPC_CPU(cs); 556 CPUPPCState *env = &cpu->env; 557 558 if (n < 32) { 559 #if defined(TARGET_PPC64) 560 target_ulong lo = (uint32_t)env->gpr[n]; 561 target_ulong hi; 562 563 ppc_maybe_bswap_register(env, mem_buf, 4); 564 565 hi = (target_ulong)ldl_p(mem_buf) << 32; 566 env->gpr[n] = lo | hi; 567 #else 568 env->gprh[n] = ldl_p(mem_buf); 569 #endif 570 return 4; 571 } 572 if (n == 32) { 573 ppc_maybe_bswap_register(env, mem_buf, 8); 574 env->spe_acc = ldq_p(mem_buf); 575 return 8; 576 } 577 if (n == 33) { 578 ppc_maybe_bswap_register(env, mem_buf, 4); 579 env->spe_fscr = ldl_p(mem_buf); 580 return 4; 581 } 582 return 0; 583 } 584 585 static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) 586 { 587 PowerPCCPU *cpu = POWERPC_CPU(cs); 588 CPUPPCState *env = &cpu->env; 589 590 if (n < 32) { 591 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); 592 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 593 return 8; 594 } 595 return 0; 596 } 597 598 static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) 599 { 600 PowerPCCPU *cpu = POWERPC_CPU(cs); 601 CPUPPCState *env = &cpu->env; 602 603 if (n < 32) { 604 ppc_maybe_bswap_register(env, mem_buf, 8); 605 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); 606 return 8; 607 } 608 return 0; 609 } 610 611 const gchar *ppc_gdb_arch_name(CPUState *cs) 612 { 613 #if defined(TARGET_PPC64) 614 return "powerpc:common64"; 615 #else 616 return "powerpc:common"; 617 #endif 618 } 619 620 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 621 { 622 if (pcc->insns_flags & PPC_FLOAT) { 623 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 624 gdb_find_static_feature("power-fpu.xml"), 0); 625 } 626 if (pcc->insns_flags & PPC_ALTIVEC) { 627 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, 628 gdb_find_static_feature("power-altivec.xml"), 629 0); 630 } 631 if (pcc->insns_flags & PPC_SPE) { 632 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, 633 gdb_find_static_feature("power-spe.xml"), 0); 634 } 635 if (pcc->insns_flags2 & PPC2_VSX) { 636 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 637 gdb_find_static_feature("power-vsx.xml"), 0); 638 } 639 #ifndef CONFIG_USER_ONLY 640 gdb_gen_spr_feature(cs); 641 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, 642 &pcc->gdb_spr, 0); 643 #endif 644 } 645