1 /* 2 * PowerPC gdb server stub 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * Copyright (c) 2013 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/gdbstub.h" 23 #include "gdbstub/helpers.h" 24 #include "internal.h" 25 26 static int ppc_gdb_register_len_apple(int n) 27 { 28 switch (n) { 29 case 0 ... 31: 30 /* gprs */ 31 return 8; 32 case 32 ... 63: 33 /* fprs */ 34 return 8; 35 case 64 ... 95: 36 return 16; 37 case 64 + 32: /* nip */ 38 case 65 + 32: /* msr */ 39 case 67 + 32: /* lr */ 40 case 68 + 32: /* ctr */ 41 case 70 + 32: /* fpscr */ 42 return 8; 43 case 66 + 32: /* cr */ 44 case 69 + 32: /* xer */ 45 return 4; 46 default: 47 return 0; 48 } 49 } 50 51 static int ppc_gdb_register_len(int n) 52 { 53 switch (n) { 54 case 0 ... 31: 55 /* gprs */ 56 return sizeof(target_ulong); 57 case 66: 58 /* cr */ 59 case 69: 60 /* xer */ 61 return 4; 62 case 64: 63 /* nip */ 64 case 65: 65 /* msr */ 66 case 67: 67 /* lr */ 68 case 68: 69 /* ctr */ 70 return sizeof(target_ulong); 71 default: 72 return 0; 73 } 74 } 75 76 /* 77 * We need to present the registers to gdb in the "current" memory 78 * ordering. For user-only mode we get this for free; 79 * TARGET_BIG_ENDIAN is set to the proper ordering for the 80 * binary, and cannot be changed. For system mode, 81 * TARGET_BIG_ENDIAN is always set, and we must check the current 82 * mode of the chip to see if we're running in little-endian. 83 */ 84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) 85 { 86 #ifndef CONFIG_USER_ONLY 87 if (!FIELD_EX64(env->msr, MSR, LE)) { 88 /* do nothing */ 89 } else if (len == 4) { 90 bswap32s((uint32_t *)mem_buf); 91 } else if (len == 8) { 92 bswap64s((uint64_t *)mem_buf); 93 } else if (len == 16) { 94 bswap128s((Int128 *)mem_buf); 95 } else { 96 g_assert_not_reached(); 97 } 98 #endif 99 } 100 101 /* 102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only 103 * expects whatever the target description contains. Due to a 104 * historical mishap the FP registers appear in between core integer 105 * regs and PC, MSR, CR, and so forth. We hack round this by giving 106 * the FP regs zero size when talking to a newer gdb. 107 */ 108 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) 110 { 111 PowerPCCPU *cpu = POWERPC_CPU(cs); 112 CPUPPCState *env = &cpu->env; 113 uint8_t *mem_buf; 114 int r = ppc_gdb_register_len(n); 115 116 if (!r) { 117 return r; 118 } 119 120 if (n < 32) { 121 /* gprs */ 122 gdb_get_regl(buf, env->gpr[n]); 123 } else { 124 switch (n) { 125 case 64: 126 gdb_get_regl(buf, env->nip); 127 break; 128 case 65: 129 gdb_get_regl(buf, env->msr); 130 break; 131 case 66: 132 { 133 uint32_t cr = ppc_get_cr(env); 134 gdb_get_reg32(buf, cr); 135 break; 136 } 137 case 67: 138 gdb_get_regl(buf, env->lr); 139 break; 140 case 68: 141 gdb_get_regl(buf, env->ctr); 142 break; 143 case 69: 144 gdb_get_reg32(buf, cpu_read_xer(env)); 145 break; 146 } 147 } 148 mem_buf = buf->data + buf->len - r; 149 ppc_maybe_bswap_register(env, mem_buf, r); 150 return r; 151 } 152 153 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) 154 { 155 PowerPCCPU *cpu = POWERPC_CPU(cs); 156 CPUPPCState *env = &cpu->env; 157 uint8_t *mem_buf; 158 int r = ppc_gdb_register_len_apple(n); 159 160 if (!r) { 161 return r; 162 } 163 164 if (n < 32) { 165 /* gprs */ 166 gdb_get_reg64(buf, env->gpr[n]); 167 } else if (n < 64) { 168 /* fprs */ 169 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); 170 } else if (n < 96) { 171 /* Altivec */ 172 gdb_get_reg64(buf, n - 64); 173 gdb_get_reg64(buf, 0); 174 } else { 175 switch (n) { 176 case 64 + 32: 177 gdb_get_reg64(buf, env->nip); 178 break; 179 case 65 + 32: 180 gdb_get_reg64(buf, env->msr); 181 break; 182 case 66 + 32: 183 { 184 uint32_t cr = ppc_get_cr(env); 185 gdb_get_reg32(buf, cr); 186 break; 187 } 188 case 67 + 32: 189 gdb_get_reg64(buf, env->lr); 190 break; 191 case 68 + 32: 192 gdb_get_reg64(buf, env->ctr); 193 break; 194 case 69 + 32: 195 gdb_get_reg32(buf, cpu_read_xer(env)); 196 break; 197 case 70 + 32: 198 gdb_get_reg64(buf, env->fpscr); 199 break; 200 } 201 } 202 mem_buf = buf->data + buf->len - r; 203 ppc_maybe_bswap_register(env, mem_buf, r); 204 return r; 205 } 206 207 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 208 { 209 PowerPCCPU *cpu = POWERPC_CPU(cs); 210 CPUPPCState *env = &cpu->env; 211 int r = ppc_gdb_register_len(n); 212 213 if (!r) { 214 return r; 215 } 216 ppc_maybe_bswap_register(env, mem_buf, r); 217 if (n < 32) { 218 /* gprs */ 219 env->gpr[n] = ldtul_p(mem_buf); 220 } else if (n < 64) { 221 /* fprs */ 222 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 223 } else { 224 switch (n) { 225 case 64: 226 env->nip = ldtul_p(mem_buf); 227 break; 228 case 65: 229 ppc_store_msr(env, ldtul_p(mem_buf)); 230 break; 231 case 66: 232 { 233 uint32_t cr = ldl_p(mem_buf); 234 ppc_set_cr(env, cr); 235 break; 236 } 237 case 67: 238 env->lr = ldtul_p(mem_buf); 239 break; 240 case 68: 241 env->ctr = ldtul_p(mem_buf); 242 break; 243 case 69: 244 cpu_write_xer(env, ldl_p(mem_buf)); 245 break; 246 case 70: 247 /* fpscr */ 248 ppc_store_fpscr(env, ldtul_p(mem_buf)); 249 break; 250 } 251 } 252 return r; 253 } 254 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) 255 { 256 PowerPCCPU *cpu = POWERPC_CPU(cs); 257 CPUPPCState *env = &cpu->env; 258 int r = ppc_gdb_register_len_apple(n); 259 260 if (!r) { 261 return r; 262 } 263 ppc_maybe_bswap_register(env, mem_buf, r); 264 if (n < 32) { 265 /* gprs */ 266 env->gpr[n] = ldq_p(mem_buf); 267 } else if (n < 64) { 268 /* fprs */ 269 *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf); 270 } else { 271 switch (n) { 272 case 64 + 32: 273 env->nip = ldq_p(mem_buf); 274 break; 275 case 65 + 32: 276 ppc_store_msr(env, ldq_p(mem_buf)); 277 break; 278 case 66 + 32: 279 { 280 uint32_t cr = ldl_p(mem_buf); 281 ppc_set_cr(env, cr); 282 break; 283 } 284 case 67 + 32: 285 env->lr = ldq_p(mem_buf); 286 break; 287 case 68 + 32: 288 env->ctr = ldq_p(mem_buf); 289 break; 290 case 69 + 32: 291 cpu_write_xer(env, ldl_p(mem_buf)); 292 break; 293 case 70 + 32: 294 /* fpscr */ 295 ppc_store_fpscr(env, ldq_p(mem_buf)); 296 break; 297 } 298 } 299 return r; 300 } 301 302 #ifndef CONFIG_USER_ONLY 303 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) 304 { 305 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 306 CPUPPCState *env = &cpu->env; 307 GString *xml; 308 char *spr_name; 309 unsigned int num_regs = 0; 310 int i; 311 312 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 313 ppc_spr_t *spr = &env->spr_cb[i]; 314 315 if (!spr->name) { 316 continue; 317 } 318 319 /* 320 * GDB identifies registers based on the order they are 321 * presented in the XML. These ids will not match QEMU's 322 * representation (which follows the PowerISA). 323 * 324 * Store the position of the current register description so 325 * we can make the correspondence later. 326 */ 327 spr->gdb_id = num_regs; 328 num_regs++; 329 } 330 331 if (pcc->gdb_spr_xml) { 332 return; 333 } 334 335 xml = g_string_new("<?xml version=\"1.0\"?>"); 336 g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); 337 g_string_append(xml, "<feature name=\"org.qemu.power.spr\">"); 338 339 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 340 ppc_spr_t *spr = &env->spr_cb[i]; 341 342 if (!spr->name) { 343 continue; 344 } 345 346 spr_name = g_ascii_strdown(spr->name, -1); 347 g_string_append_printf(xml, "<reg name=\"%s\"", spr_name); 348 g_free(spr_name); 349 350 g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS); 351 g_string_append(xml, " group=\"spr\"/>"); 352 } 353 354 g_string_append(xml, "</feature>"); 355 356 pcc->gdb_num_sprs = num_regs; 357 pcc->gdb_spr_xml = g_string_free(xml, false); 358 } 359 360 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) 361 { 362 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 363 364 if (strcmp(xml_name, "power-spr.xml") == 0) { 365 return pcc->gdb_spr_xml; 366 } 367 return NULL; 368 } 369 #endif 370 371 #if !defined(CONFIG_USER_ONLY) 372 static int gdb_find_spr_idx(CPUPPCState *env, int n) 373 { 374 int i; 375 376 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 377 ppc_spr_t *spr = &env->spr_cb[i]; 378 379 if (spr->name && spr->gdb_id == n) { 380 return i; 381 } 382 } 383 return -1; 384 } 385 386 static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) 387 { 388 int reg; 389 int len; 390 391 reg = gdb_find_spr_idx(env, n); 392 if (reg < 0) { 393 return 0; 394 } 395 396 len = TARGET_LONG_SIZE; 397 398 /* Handle those SPRs that are not part of the env->spr[] array */ 399 target_ulong val; 400 switch (reg) { 401 #if defined(TARGET_PPC64) 402 case SPR_CFAR: 403 val = env->cfar; 404 break; 405 #endif 406 case SPR_HDEC: 407 val = cpu_ppc_load_hdecr(env); 408 break; 409 case SPR_TBL: 410 val = cpu_ppc_load_tbl(env); 411 break; 412 case SPR_TBU: 413 val = cpu_ppc_load_tbu(env); 414 break; 415 case SPR_DECR: 416 val = cpu_ppc_load_decr(env); 417 break; 418 default: 419 val = env->spr[reg]; 420 } 421 gdb_get_regl(buf, val); 422 423 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); 424 return len; 425 } 426 427 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 428 { 429 int reg; 430 int len; 431 432 reg = gdb_find_spr_idx(env, n); 433 if (reg < 0) { 434 return 0; 435 } 436 437 len = TARGET_LONG_SIZE; 438 ppc_maybe_bswap_register(env, mem_buf, len); 439 440 /* Handle those SPRs that are not part of the env->spr[] array */ 441 target_ulong val = ldn_p(mem_buf, len); 442 switch (reg) { 443 #if defined(TARGET_PPC64) 444 case SPR_CFAR: 445 env->cfar = val; 446 break; 447 #endif 448 default: 449 env->spr[reg] = val; 450 } 451 452 return len; 453 } 454 #endif 455 456 static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) 457 { 458 uint8_t *mem_buf; 459 if (n < 32) { 460 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); 461 mem_buf = gdb_get_reg_ptr(buf, 8); 462 ppc_maybe_bswap_register(env, mem_buf, 8); 463 return 8; 464 } 465 if (n == 32) { 466 gdb_get_reg32(buf, env->fpscr); 467 mem_buf = gdb_get_reg_ptr(buf, 4); 468 ppc_maybe_bswap_register(env, mem_buf, 4); 469 return 4; 470 } 471 return 0; 472 } 473 474 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 475 { 476 if (n < 32) { 477 ppc_maybe_bswap_register(env, mem_buf, 8); 478 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); 479 return 8; 480 } 481 if (n == 32) { 482 ppc_maybe_bswap_register(env, mem_buf, 4); 483 ppc_store_fpscr(env, ldl_p(mem_buf)); 484 return 4; 485 } 486 return 0; 487 } 488 489 static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) 490 { 491 uint8_t *mem_buf; 492 493 if (n < 32) { 494 ppc_avr_t *avr = cpu_avr_ptr(env, n); 495 gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1)); 496 mem_buf = gdb_get_reg_ptr(buf, 16); 497 ppc_maybe_bswap_register(env, mem_buf, 16); 498 return 16; 499 } 500 if (n == 32) { 501 gdb_get_reg32(buf, ppc_get_vscr(env)); 502 mem_buf = gdb_get_reg_ptr(buf, 4); 503 ppc_maybe_bswap_register(env, mem_buf, 4); 504 return 4; 505 } 506 if (n == 33) { 507 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); 508 mem_buf = gdb_get_reg_ptr(buf, 4); 509 ppc_maybe_bswap_register(env, mem_buf, 4); 510 return 4; 511 } 512 return 0; 513 } 514 515 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 516 { 517 if (n < 32) { 518 ppc_avr_t *avr = cpu_avr_ptr(env, n); 519 ppc_maybe_bswap_register(env, mem_buf, 16); 520 avr->VsrD(0) = ldq_p(mem_buf); 521 avr->VsrD(1) = ldq_p(mem_buf + 8); 522 return 16; 523 } 524 if (n == 32) { 525 ppc_maybe_bswap_register(env, mem_buf, 4); 526 ppc_store_vscr(env, ldl_p(mem_buf)); 527 return 4; 528 } 529 if (n == 33) { 530 ppc_maybe_bswap_register(env, mem_buf, 4); 531 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 532 return 4; 533 } 534 return 0; 535 } 536 537 static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) 538 { 539 if (n < 32) { 540 #if defined(TARGET_PPC64) 541 gdb_get_reg32(buf, env->gpr[n] >> 32); 542 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 543 #else 544 gdb_get_reg32(buf, env->gprh[n]); 545 #endif 546 return 4; 547 } 548 if (n == 32) { 549 gdb_get_reg64(buf, env->spe_acc); 550 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 551 return 8; 552 } 553 if (n == 33) { 554 gdb_get_reg32(buf, env->spe_fscr); 555 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 556 return 4; 557 } 558 return 0; 559 } 560 561 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 562 { 563 if (n < 32) { 564 #if defined(TARGET_PPC64) 565 target_ulong lo = (uint32_t)env->gpr[n]; 566 target_ulong hi; 567 568 ppc_maybe_bswap_register(env, mem_buf, 4); 569 570 hi = (target_ulong)ldl_p(mem_buf) << 32; 571 env->gpr[n] = lo | hi; 572 #else 573 env->gprh[n] = ldl_p(mem_buf); 574 #endif 575 return 4; 576 } 577 if (n == 32) { 578 ppc_maybe_bswap_register(env, mem_buf, 8); 579 env->spe_acc = ldq_p(mem_buf); 580 return 8; 581 } 582 if (n == 33) { 583 ppc_maybe_bswap_register(env, mem_buf, 4); 584 env->spe_fscr = ldl_p(mem_buf); 585 return 4; 586 } 587 return 0; 588 } 589 590 static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) 591 { 592 if (n < 32) { 593 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); 594 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 595 return 8; 596 } 597 return 0; 598 } 599 600 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 601 { 602 if (n < 32) { 603 ppc_maybe_bswap_register(env, mem_buf, 8); 604 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); 605 return 8; 606 } 607 return 0; 608 } 609 610 const gchar *ppc_gdb_arch_name(CPUState *cs) 611 { 612 #if defined(TARGET_PPC64) 613 return "powerpc:common64"; 614 #else 615 return "powerpc:common"; 616 #endif 617 } 618 619 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 620 { 621 if (pcc->insns_flags & PPC_FLOAT) { 622 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 623 33, "power-fpu.xml", 0); 624 } 625 if (pcc->insns_flags & PPC_ALTIVEC) { 626 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, 627 34, "power-altivec.xml", 0); 628 } 629 if (pcc->insns_flags & PPC_SPE) { 630 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, 631 34, "power-spe.xml", 0); 632 } 633 if (pcc->insns_flags2 & PPC2_VSX) { 634 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 635 32, "power-vsx.xml", 0); 636 } 637 #ifndef CONFIG_USER_ONLY 638 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, 639 pcc->gdb_num_sprs, "power-spr.xml", 0); 640 #endif 641 } 642