1 /* 2 * PowerPC exception emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/main-loop.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "exec/exec-all.h" 24 #include "exec/cpu_ldst.h" 25 26 #include "helper_regs.h" 27 28 //#define DEBUG_OP 29 //#define DEBUG_SOFTWARE_TLB 30 //#define DEBUG_EXCEPTIONS 31 32 #ifdef DEBUG_EXCEPTIONS 33 # define LOG_EXCP(...) qemu_log(__VA_ARGS__) 34 #else 35 # define LOG_EXCP(...) do { } while (0) 36 #endif 37 38 /*****************************************************************************/ 39 /* Exception processing */ 40 #if defined(CONFIG_USER_ONLY) 41 void ppc_cpu_do_interrupt(CPUState *cs) 42 { 43 PowerPCCPU *cpu = POWERPC_CPU(cs); 44 CPUPPCState *env = &cpu->env; 45 46 cs->exception_index = POWERPC_EXCP_NONE; 47 env->error_code = 0; 48 } 49 50 static void ppc_hw_interrupt(CPUPPCState *env) 51 { 52 CPUState *cs = CPU(ppc_env_get_cpu(env)); 53 54 cs->exception_index = POWERPC_EXCP_NONE; 55 env->error_code = 0; 56 } 57 #else /* defined(CONFIG_USER_ONLY) */ 58 static inline void dump_syscall(CPUPPCState *env) 59 { 60 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 61 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 62 " nip=" TARGET_FMT_lx "\n", 63 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), 64 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), 65 ppc_dump_gpr(env, 6), env->nip); 66 } 67 68 /* Note that this function should be greatly optimized 69 * when called with a constant excp, from ppc_hw_interrupt 70 */ 71 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) 72 { 73 CPUState *cs = CPU(cpu); 74 CPUPPCState *env = &cpu->env; 75 target_ulong msr, new_msr, vector; 76 int srr0, srr1, asrr0, asrr1, lev, ail; 77 bool lpes0; 78 79 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx 80 " => %08x (%02x)\n", env->nip, excp, env->error_code); 81 82 /* new srr1 value excluding must-be-zero bits */ 83 if (excp_model == POWERPC_EXCP_BOOKE) { 84 msr = env->msr; 85 } else { 86 msr = env->msr & ~0x783f0000ULL; 87 } 88 89 /* new interrupt handler msr preserves existing HV and ME unless 90 * explicitly overriden 91 */ 92 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); 93 94 /* target registers */ 95 srr0 = SPR_SRR0; 96 srr1 = SPR_SRR1; 97 asrr0 = -1; 98 asrr1 = -1; 99 100 /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */ 101 if (env->in_pm_state) { 102 env->in_pm_state = false; 103 104 /* Pretend to be returning from doze always as we don't lose state */ 105 msr |= (0x1ull << (63 - 47)); 106 107 /* Non-machine check are routed to 0x100 with a wakeup cause 108 * encoded in SRR1 109 */ 110 if (excp != POWERPC_EXCP_MCHECK) { 111 switch (excp) { 112 case POWERPC_EXCP_RESET: 113 msr |= 0x4ull << (63 - 45); 114 break; 115 case POWERPC_EXCP_EXTERNAL: 116 msr |= 0x8ull << (63 - 45); 117 break; 118 case POWERPC_EXCP_DECR: 119 msr |= 0x6ull << (63 - 45); 120 break; 121 case POWERPC_EXCP_SDOOR: 122 msr |= 0x5ull << (63 - 45); 123 break; 124 case POWERPC_EXCP_SDOOR_HV: 125 msr |= 0x3ull << (63 - 45); 126 break; 127 case POWERPC_EXCP_HV_MAINT: 128 msr |= 0xaull << (63 - 45); 129 break; 130 default: 131 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", 132 excp); 133 } 134 excp = POWERPC_EXCP_RESET; 135 } 136 } 137 138 /* Exception targetting modifiers 139 * 140 * LPES0 is supported on POWER7/8 141 * LPES1 is not supported (old iSeries mode) 142 * 143 * On anything else, we behave as if LPES0 is 1 144 * (externals don't alter MSR:HV) 145 * 146 * AIL is initialized here but can be cleared by 147 * selected exceptions 148 */ 149 #if defined(TARGET_PPC64) 150 if (excp_model == POWERPC_EXCP_POWER7 || 151 excp_model == POWERPC_EXCP_POWER8) { 152 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 153 if (excp_model == POWERPC_EXCP_POWER8) { 154 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; 155 } else { 156 ail = 0; 157 } 158 } else 159 #endif /* defined(TARGET_PPC64) */ 160 { 161 lpes0 = true; 162 ail = 0; 163 } 164 165 /* Hypervisor emulation assistance interrupt only exists on server 166 * arch 2.05 server or later. We also don't want to generate it if 167 * we don't have HVB in msr_mask (PAPR mode). 168 */ 169 if (excp == POWERPC_EXCP_HV_EMU 170 #if defined(TARGET_PPC64) 171 && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) 172 #endif /* defined(TARGET_PPC64) */ 173 174 ) { 175 excp = POWERPC_EXCP_PROGRAM; 176 } 177 178 switch (excp) { 179 case POWERPC_EXCP_NONE: 180 /* Should never happen */ 181 return; 182 case POWERPC_EXCP_CRITICAL: /* Critical input */ 183 switch (excp_model) { 184 case POWERPC_EXCP_40x: 185 srr0 = SPR_40x_SRR2; 186 srr1 = SPR_40x_SRR3; 187 break; 188 case POWERPC_EXCP_BOOKE: 189 srr0 = SPR_BOOKE_CSRR0; 190 srr1 = SPR_BOOKE_CSRR1; 191 break; 192 case POWERPC_EXCP_G2: 193 break; 194 default: 195 goto excp_invalid; 196 } 197 break; 198 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 199 if (msr_me == 0) { 200 /* Machine check exception is not enabled. 201 * Enter checkstop state. 202 */ 203 fprintf(stderr, "Machine check while not allowed. " 204 "Entering checkstop state\n"); 205 if (qemu_log_separate()) { 206 qemu_log("Machine check while not allowed. " 207 "Entering checkstop state\n"); 208 } 209 cs->halted = 1; 210 cpu_interrupt_exittb(cs); 211 } 212 if (env->msr_mask & MSR_HVB) { 213 /* ISA specifies HV, but can be delivered to guest with HV clear 214 * (e.g., see FWNMI in PAPR). 215 */ 216 new_msr |= (target_ulong)MSR_HVB; 217 } 218 ail = 0; 219 220 /* machine check exceptions don't have ME set */ 221 new_msr &= ~((target_ulong)1 << MSR_ME); 222 223 /* XXX: should also have something loaded in DAR / DSISR */ 224 switch (excp_model) { 225 case POWERPC_EXCP_40x: 226 srr0 = SPR_40x_SRR2; 227 srr1 = SPR_40x_SRR3; 228 break; 229 case POWERPC_EXCP_BOOKE: 230 /* FIXME: choose one or the other based on CPU type */ 231 srr0 = SPR_BOOKE_MCSRR0; 232 srr1 = SPR_BOOKE_MCSRR1; 233 asrr0 = SPR_BOOKE_CSRR0; 234 asrr1 = SPR_BOOKE_CSRR1; 235 break; 236 default: 237 break; 238 } 239 break; 240 case POWERPC_EXCP_DSI: /* Data storage exception */ 241 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx 242 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); 243 break; 244 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 245 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx 246 "\n", msr, env->nip); 247 msr |= env->error_code; 248 break; 249 case POWERPC_EXCP_EXTERNAL: /* External input */ 250 cs = CPU(cpu); 251 252 if (!lpes0) { 253 new_msr |= (target_ulong)MSR_HVB; 254 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 255 srr0 = SPR_HSRR0; 256 srr1 = SPR_HSRR1; 257 } 258 if (env->mpic_proxy) { 259 /* IACK the IRQ on delivery */ 260 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); 261 } 262 break; 263 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 264 /* Get rS/rD and rA from faulting opcode */ 265 /* Note: the opcode fields will not be set properly for a direct 266 * store load/store, but nobody cares as nobody actually uses 267 * direct store segments. 268 */ 269 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 270 break; 271 case POWERPC_EXCP_PROGRAM: /* Program exception */ 272 switch (env->error_code & ~0xF) { 273 case POWERPC_EXCP_FP: 274 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { 275 LOG_EXCP("Ignore floating point exception\n"); 276 cs->exception_index = POWERPC_EXCP_NONE; 277 env->error_code = 0; 278 return; 279 } 280 281 /* FP exceptions always have NIP pointing to the faulting 282 * instruction, so always use store_next and claim we are 283 * precise in the MSR. 284 */ 285 msr |= 0x00100000; 286 env->spr[SPR_BOOKE_ESR] = ESR_FP; 287 break; 288 case POWERPC_EXCP_INVAL: 289 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); 290 msr |= 0x00080000; 291 env->spr[SPR_BOOKE_ESR] = ESR_PIL; 292 break; 293 case POWERPC_EXCP_PRIV: 294 msr |= 0x00040000; 295 env->spr[SPR_BOOKE_ESR] = ESR_PPR; 296 break; 297 case POWERPC_EXCP_TRAP: 298 msr |= 0x00020000; 299 env->spr[SPR_BOOKE_ESR] = ESR_PTR; 300 break; 301 default: 302 /* Should never occur */ 303 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 304 env->error_code); 305 break; 306 } 307 break; 308 case POWERPC_EXCP_SYSCALL: /* System call exception */ 309 dump_syscall(env); 310 lev = env->error_code; 311 312 /* We need to correct the NIP which in this case is supposed 313 * to point to the next instruction 314 */ 315 env->nip += 4; 316 317 /* "PAPR mode" built-in hypercall emulation */ 318 if ((lev == 1) && cpu->vhyp) { 319 PPCVirtualHypervisorClass *vhc = 320 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 321 vhc->hypercall(cpu->vhyp, cpu); 322 return; 323 } 324 if (lev == 1) { 325 new_msr |= (target_ulong)MSR_HVB; 326 } 327 break; 328 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 329 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 330 case POWERPC_EXCP_DECR: /* Decrementer exception */ 331 break; 332 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 333 /* FIT on 4xx */ 334 LOG_EXCP("FIT exception\n"); 335 break; 336 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 337 LOG_EXCP("WDT exception\n"); 338 switch (excp_model) { 339 case POWERPC_EXCP_BOOKE: 340 srr0 = SPR_BOOKE_CSRR0; 341 srr1 = SPR_BOOKE_CSRR1; 342 break; 343 default: 344 break; 345 } 346 break; 347 case POWERPC_EXCP_DTLB: /* Data TLB error */ 348 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 349 break; 350 case POWERPC_EXCP_DEBUG: /* Debug interrupt */ 351 switch (excp_model) { 352 case POWERPC_EXCP_BOOKE: 353 /* FIXME: choose one or the other based on CPU type */ 354 srr0 = SPR_BOOKE_DSRR0; 355 srr1 = SPR_BOOKE_DSRR1; 356 asrr0 = SPR_BOOKE_CSRR0; 357 asrr1 = SPR_BOOKE_CSRR1; 358 break; 359 default: 360 break; 361 } 362 /* XXX: TODO */ 363 cpu_abort(cs, "Debug exception is not implemented yet !\n"); 364 break; 365 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ 366 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 367 break; 368 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ 369 /* XXX: TODO */ 370 cpu_abort(cs, "Embedded floating point data exception " 371 "is not implemented yet !\n"); 372 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 373 break; 374 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ 375 /* XXX: TODO */ 376 cpu_abort(cs, "Embedded floating point round exception " 377 "is not implemented yet !\n"); 378 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 379 break; 380 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ 381 /* XXX: TODO */ 382 cpu_abort(cs, 383 "Performance counter exception is not implemented yet !\n"); 384 break; 385 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 386 break; 387 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 388 srr0 = SPR_BOOKE_CSRR0; 389 srr1 = SPR_BOOKE_CSRR1; 390 break; 391 case POWERPC_EXCP_RESET: /* System reset exception */ 392 /* A power-saving exception sets ME, otherwise it is unchanged */ 393 if (msr_pow) { 394 /* indicate that we resumed from power save mode */ 395 msr |= 0x10000; 396 new_msr |= ((target_ulong)1 << MSR_ME); 397 } 398 if (env->msr_mask & MSR_HVB) { 399 /* ISA specifies HV, but can be delivered to guest with HV clear 400 * (e.g., see FWNMI in PAPR, NMI injection in QEMU). 401 */ 402 new_msr |= (target_ulong)MSR_HVB; 403 } else { 404 if (msr_pow) { 405 cpu_abort(cs, "Trying to deliver power-saving system reset " 406 "exception %d with no HV support\n", excp); 407 } 408 } 409 ail = 0; 410 break; 411 case POWERPC_EXCP_DSEG: /* Data segment exception */ 412 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 413 case POWERPC_EXCP_TRACE: /* Trace exception */ 414 break; 415 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 416 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 417 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ 418 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 419 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ 420 case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ 421 case POWERPC_EXCP_HV_EMU: 422 srr0 = SPR_HSRR0; 423 srr1 = SPR_HSRR1; 424 new_msr |= (target_ulong)MSR_HVB; 425 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 426 break; 427 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 428 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ 429 case POWERPC_EXCP_FU: /* Facility unavailable exception */ 430 #ifdef TARGET_PPC64 431 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); 432 #endif 433 break; 434 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ 435 LOG_EXCP("PIT exception\n"); 436 break; 437 case POWERPC_EXCP_IO: /* IO error exception */ 438 /* XXX: TODO */ 439 cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); 440 break; 441 case POWERPC_EXCP_RUNM: /* Run mode exception */ 442 /* XXX: TODO */ 443 cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); 444 break; 445 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 446 /* XXX: TODO */ 447 cpu_abort(cs, "602 emulation trap exception " 448 "is not implemented yet !\n"); 449 break; 450 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 451 switch (excp_model) { 452 case POWERPC_EXCP_602: 453 case POWERPC_EXCP_603: 454 case POWERPC_EXCP_603E: 455 case POWERPC_EXCP_G2: 456 goto tlb_miss_tgpr; 457 case POWERPC_EXCP_7x5: 458 goto tlb_miss; 459 case POWERPC_EXCP_74xx: 460 goto tlb_miss_74xx; 461 default: 462 cpu_abort(cs, "Invalid instruction TLB miss exception\n"); 463 break; 464 } 465 break; 466 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 467 switch (excp_model) { 468 case POWERPC_EXCP_602: 469 case POWERPC_EXCP_603: 470 case POWERPC_EXCP_603E: 471 case POWERPC_EXCP_G2: 472 goto tlb_miss_tgpr; 473 case POWERPC_EXCP_7x5: 474 goto tlb_miss; 475 case POWERPC_EXCP_74xx: 476 goto tlb_miss_74xx; 477 default: 478 cpu_abort(cs, "Invalid data load TLB miss exception\n"); 479 break; 480 } 481 break; 482 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 483 switch (excp_model) { 484 case POWERPC_EXCP_602: 485 case POWERPC_EXCP_603: 486 case POWERPC_EXCP_603E: 487 case POWERPC_EXCP_G2: 488 tlb_miss_tgpr: 489 /* Swap temporary saved registers with GPRs */ 490 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { 491 new_msr |= (target_ulong)1 << MSR_TGPR; 492 hreg_swap_gpr_tgpr(env); 493 } 494 goto tlb_miss; 495 case POWERPC_EXCP_7x5: 496 tlb_miss: 497 #if defined(DEBUG_SOFTWARE_TLB) 498 if (qemu_log_enabled()) { 499 const char *es; 500 target_ulong *miss, *cmp; 501 int en; 502 503 if (excp == POWERPC_EXCP_IFTLB) { 504 es = "I"; 505 en = 'I'; 506 miss = &env->spr[SPR_IMISS]; 507 cmp = &env->spr[SPR_ICMP]; 508 } else { 509 if (excp == POWERPC_EXCP_DLTLB) { 510 es = "DL"; 511 } else { 512 es = "DS"; 513 } 514 en = 'D'; 515 miss = &env->spr[SPR_DMISS]; 516 cmp = &env->spr[SPR_DCMP]; 517 } 518 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " 519 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " 520 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, 521 env->spr[SPR_HASH1], env->spr[SPR_HASH2], 522 env->error_code); 523 } 524 #endif 525 msr |= env->crf[0] << 28; 526 msr |= env->error_code; /* key, D/I, S/L bits */ 527 /* Set way using a LRU mechanism */ 528 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; 529 break; 530 case POWERPC_EXCP_74xx: 531 tlb_miss_74xx: 532 #if defined(DEBUG_SOFTWARE_TLB) 533 if (qemu_log_enabled()) { 534 const char *es; 535 target_ulong *miss, *cmp; 536 int en; 537 538 if (excp == POWERPC_EXCP_IFTLB) { 539 es = "I"; 540 en = 'I'; 541 miss = &env->spr[SPR_TLBMISS]; 542 cmp = &env->spr[SPR_PTEHI]; 543 } else { 544 if (excp == POWERPC_EXCP_DLTLB) { 545 es = "DL"; 546 } else { 547 es = "DS"; 548 } 549 en = 'D'; 550 miss = &env->spr[SPR_TLBMISS]; 551 cmp = &env->spr[SPR_PTEHI]; 552 } 553 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " 554 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, 555 env->error_code); 556 } 557 #endif 558 msr |= env->error_code; /* key bit */ 559 break; 560 default: 561 cpu_abort(cs, "Invalid data store TLB miss exception\n"); 562 break; 563 } 564 break; 565 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 566 /* XXX: TODO */ 567 cpu_abort(cs, "Floating point assist exception " 568 "is not implemented yet !\n"); 569 break; 570 case POWERPC_EXCP_DABR: /* Data address breakpoint */ 571 /* XXX: TODO */ 572 cpu_abort(cs, "DABR exception is not implemented yet !\n"); 573 break; 574 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 575 /* XXX: TODO */ 576 cpu_abort(cs, "IABR exception is not implemented yet !\n"); 577 break; 578 case POWERPC_EXCP_SMI: /* System management interrupt */ 579 /* XXX: TODO */ 580 cpu_abort(cs, "SMI exception is not implemented yet !\n"); 581 break; 582 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 583 /* XXX: TODO */ 584 cpu_abort(cs, "Thermal management exception " 585 "is not implemented yet !\n"); 586 break; 587 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ 588 /* XXX: TODO */ 589 cpu_abort(cs, 590 "Performance counter exception is not implemented yet !\n"); 591 break; 592 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 593 /* XXX: TODO */ 594 cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); 595 break; 596 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 597 /* XXX: TODO */ 598 cpu_abort(cs, 599 "970 soft-patch exception is not implemented yet !\n"); 600 break; 601 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 602 /* XXX: TODO */ 603 cpu_abort(cs, 604 "970 maintenance exception is not implemented yet !\n"); 605 break; 606 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ 607 /* XXX: TODO */ 608 cpu_abort(cs, "Maskable external exception " 609 "is not implemented yet !\n"); 610 break; 611 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ 612 /* XXX: TODO */ 613 cpu_abort(cs, "Non maskable external exception " 614 "is not implemented yet !\n"); 615 break; 616 default: 617 excp_invalid: 618 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 619 break; 620 } 621 622 /* Save PC */ 623 env->spr[srr0] = env->nip; 624 625 /* Save MSR */ 626 env->spr[srr1] = msr; 627 628 /* Sanity check */ 629 if (!(env->msr_mask & MSR_HVB)) { 630 if (new_msr & MSR_HVB) { 631 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " 632 "no HV support\n", excp); 633 } 634 if (srr0 == SPR_HSRR0) { 635 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " 636 "no HV support\n", excp); 637 } 638 } 639 640 /* If any alternate SRR register are defined, duplicate saved values */ 641 if (asrr0 != -1) { 642 env->spr[asrr0] = env->spr[srr0]; 643 } 644 if (asrr1 != -1) { 645 env->spr[asrr1] = env->spr[srr1]; 646 } 647 648 /* Sort out endianness of interrupt, this differs depending on the 649 * CPU, the HV mode, etc... 650 */ 651 #ifdef TARGET_PPC64 652 if (excp_model == POWERPC_EXCP_POWER7) { 653 if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { 654 new_msr |= (target_ulong)1 << MSR_LE; 655 } 656 } else if (excp_model == POWERPC_EXCP_POWER8) { 657 if (new_msr & MSR_HVB) { 658 if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) { 659 new_msr |= (target_ulong)1 << MSR_LE; 660 } 661 } else if (env->spr[SPR_LPCR] & LPCR_ILE) { 662 new_msr |= (target_ulong)1 << MSR_LE; 663 } 664 } else if (msr_ile) { 665 new_msr |= (target_ulong)1 << MSR_LE; 666 } 667 #else 668 if (msr_ile) { 669 new_msr |= (target_ulong)1 << MSR_LE; 670 } 671 #endif 672 673 /* Jump to handler */ 674 vector = env->excp_vectors[excp]; 675 if (vector == (target_ulong)-1ULL) { 676 cpu_abort(cs, "Raised an exception without defined vector %d\n", 677 excp); 678 } 679 vector |= env->excp_prefix; 680 681 /* AIL only works if there is no HV transition and we are running with 682 * translations enabled 683 */ 684 if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || 685 ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { 686 ail = 0; 687 } 688 /* Handle AIL */ 689 if (ail) { 690 new_msr |= (1 << MSR_IR) | (1 << MSR_DR); 691 switch(ail) { 692 case AIL_0001_8000: 693 vector |= 0x18000; 694 break; 695 case AIL_C000_0000_0000_4000: 696 vector |= 0xc000000000004000ull; 697 break; 698 default: 699 cpu_abort(cs, "Invalid AIL combination %d\n", ail); 700 break; 701 } 702 } 703 704 #if defined(TARGET_PPC64) 705 if (excp_model == POWERPC_EXCP_BOOKE) { 706 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { 707 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ 708 new_msr |= (target_ulong)1 << MSR_CM; 709 } else { 710 vector = (uint32_t)vector; 711 } 712 } else { 713 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { 714 vector = (uint32_t)vector; 715 } else { 716 new_msr |= (target_ulong)1 << MSR_SF; 717 } 718 } 719 #endif 720 /* We don't use hreg_store_msr here as already have treated 721 * any special case that could occur. Just store MSR and update hflags 722 * 723 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it 724 * will prevent setting of the HV bit which some exceptions might need 725 * to do. 726 */ 727 env->msr = new_msr & env->msr_mask; 728 hreg_compute_hflags(env); 729 env->nip = vector; 730 /* Reset exception state */ 731 cs->exception_index = POWERPC_EXCP_NONE; 732 env->error_code = 0; 733 734 /* Reset the reservation */ 735 env->reserve_addr = -1; 736 737 /* Any interrupt is context synchronizing, check if TCG TLB 738 * needs a delayed flush on ppc64 739 */ 740 check_tlb_flush(env, false); 741 } 742 743 void ppc_cpu_do_interrupt(CPUState *cs) 744 { 745 PowerPCCPU *cpu = POWERPC_CPU(cs); 746 CPUPPCState *env = &cpu->env; 747 748 powerpc_excp(cpu, env->excp_model, cs->exception_index); 749 } 750 751 static void ppc_hw_interrupt(CPUPPCState *env) 752 { 753 PowerPCCPU *cpu = ppc_env_get_cpu(env); 754 #if 0 755 CPUState *cs = CPU(cpu); 756 757 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n", 758 __func__, env, env->pending_interrupts, 759 cs->interrupt_request, (int)msr_me, (int)msr_ee); 760 #endif 761 /* External reset */ 762 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { 763 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); 764 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); 765 return; 766 } 767 /* Machine check exception */ 768 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { 769 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); 770 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); 771 return; 772 } 773 #if 0 /* TODO */ 774 /* External debug exception */ 775 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { 776 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); 777 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); 778 return; 779 } 780 #endif 781 /* Hypervisor decrementer exception */ 782 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { 783 /* LPCR will be clear when not supported so this will work */ 784 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 785 if ((msr_ee != 0 || msr_hv == 0) && hdice) { 786 /* HDEC clears on delivery */ 787 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); 788 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); 789 return; 790 } 791 } 792 /* Extermal interrupt can ignore MSR:EE under some circumstances */ 793 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { 794 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 795 if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) { 796 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); 797 return; 798 } 799 } 800 if (msr_ce != 0) { 801 /* External critical interrupt */ 802 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { 803 /* Taking a critical external interrupt does not clear the external 804 * critical interrupt status 805 */ 806 #if 0 807 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); 808 #endif 809 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); 810 return; 811 } 812 } 813 if (msr_ee != 0) { 814 /* Watchdog timer on embedded PowerPC */ 815 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { 816 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); 817 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); 818 return; 819 } 820 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { 821 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); 822 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); 823 return; 824 } 825 /* Fixed interval timer on embedded PowerPC */ 826 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { 827 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); 828 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); 829 return; 830 } 831 /* Programmable interval timer on embedded PowerPC */ 832 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { 833 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); 834 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); 835 return; 836 } 837 /* Decrementer exception */ 838 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { 839 if (ppc_decr_clear_on_delivery(env)) { 840 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); 841 } 842 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); 843 return; 844 } 845 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { 846 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); 847 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); 848 return; 849 } 850 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) { 851 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL); 852 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV); 853 return; 854 } 855 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { 856 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); 857 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); 858 return; 859 } 860 /* Thermal interrupt */ 861 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { 862 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); 863 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); 864 return; 865 } 866 } 867 } 868 869 void ppc_cpu_do_system_reset(CPUState *cs) 870 { 871 PowerPCCPU *cpu = POWERPC_CPU(cs); 872 CPUPPCState *env = &cpu->env; 873 874 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); 875 } 876 #endif /* !CONFIG_USER_ONLY */ 877 878 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 879 { 880 PowerPCCPU *cpu = POWERPC_CPU(cs); 881 CPUPPCState *env = &cpu->env; 882 883 if (interrupt_request & CPU_INTERRUPT_HARD) { 884 ppc_hw_interrupt(env); 885 if (env->pending_interrupts == 0) { 886 cs->interrupt_request &= ~CPU_INTERRUPT_HARD; 887 } 888 return true; 889 } 890 return false; 891 } 892 893 #if defined(DEBUG_OP) 894 static void cpu_dump_rfi(target_ulong RA, target_ulong msr) 895 { 896 qemu_log("Return from exception at " TARGET_FMT_lx " with flags " 897 TARGET_FMT_lx "\n", RA, msr); 898 } 899 #endif 900 901 /*****************************************************************************/ 902 /* Exceptions processing helpers */ 903 904 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 905 uint32_t error_code, uintptr_t raddr) 906 { 907 CPUState *cs = CPU(ppc_env_get_cpu(env)); 908 909 cs->exception_index = exception; 910 env->error_code = error_code; 911 cpu_loop_exit_restore(cs, raddr); 912 } 913 914 void raise_exception_err(CPUPPCState *env, uint32_t exception, 915 uint32_t error_code) 916 { 917 raise_exception_err_ra(env, exception, error_code, 0); 918 } 919 920 void raise_exception(CPUPPCState *env, uint32_t exception) 921 { 922 raise_exception_err_ra(env, exception, 0, 0); 923 } 924 925 void raise_exception_ra(CPUPPCState *env, uint32_t exception, 926 uintptr_t raddr) 927 { 928 raise_exception_err_ra(env, exception, 0, raddr); 929 } 930 931 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, 932 uint32_t error_code) 933 { 934 raise_exception_err_ra(env, exception, error_code, 0); 935 } 936 937 void helper_raise_exception(CPUPPCState *env, uint32_t exception) 938 { 939 raise_exception_err_ra(env, exception, 0, 0); 940 } 941 942 #if !defined(CONFIG_USER_ONLY) 943 void helper_store_msr(CPUPPCState *env, target_ulong val) 944 { 945 uint32_t excp = hreg_store_msr(env, val, 0); 946 947 if (excp != 0) { 948 CPUState *cs = CPU(ppc_env_get_cpu(env)); 949 cpu_interrupt_exittb(cs); 950 raise_exception(env, excp); 951 } 952 } 953 954 #if defined(TARGET_PPC64) 955 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) 956 { 957 CPUState *cs; 958 959 cs = CPU(ppc_env_get_cpu(env)); 960 cs->halted = 1; 961 env->in_pm_state = true; 962 963 /* The architecture specifies that HDEC interrupts are 964 * discarded in PM states 965 */ 966 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); 967 968 /* Technically, nap doesn't set EE, but if we don't set it 969 * then ppc_hw_interrupt() won't deliver. We could add some 970 * other tests there based on LPCR but it's simpler to just 971 * whack EE in. It will be cleared by the 0x100 at wakeup 972 * anyway. It will still be observable by the guest in SRR1 973 * but this doesn't seem to be a problem. 974 */ 975 env->msr |= (1ull << MSR_EE); 976 raise_exception(env, EXCP_HLT); 977 } 978 #endif /* defined(TARGET_PPC64) */ 979 980 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) 981 { 982 CPUState *cs = CPU(ppc_env_get_cpu(env)); 983 984 /* MSR:POW cannot be set by any form of rfi */ 985 msr &= ~(1ULL << MSR_POW); 986 987 #if defined(TARGET_PPC64) 988 /* Switching to 32-bit ? Crop the nip */ 989 if (!msr_is_64bit(env, msr)) { 990 nip = (uint32_t)nip; 991 } 992 #else 993 nip = (uint32_t)nip; 994 #endif 995 /* XXX: beware: this is false if VLE is supported */ 996 env->nip = nip & ~((target_ulong)0x00000003); 997 hreg_store_msr(env, msr, 1); 998 #if defined(DEBUG_OP) 999 cpu_dump_rfi(env->nip, env->msr); 1000 #endif 1001 /* No need to raise an exception here, 1002 * as rfi is always the last insn of a TB 1003 */ 1004 cpu_interrupt_exittb(cs); 1005 /* Reset the reservation */ 1006 env->reserve_addr = -1; 1007 1008 /* Context synchronizing: check if TCG TLB needs flush */ 1009 check_tlb_flush(env, false); 1010 } 1011 1012 void helper_rfi(CPUPPCState *env) 1013 { 1014 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); 1015 } 1016 1017 #define MSR_BOOK3S_MASK 1018 #if defined(TARGET_PPC64) 1019 void helper_rfid(CPUPPCState *env) 1020 { 1021 /* The architeture defines a number of rules for which bits 1022 * can change but in practice, we handle this in hreg_store_msr() 1023 * which will be called by do_rfi(), so there is no need to filter 1024 * here 1025 */ 1026 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); 1027 } 1028 1029 void helper_hrfid(CPUPPCState *env) 1030 { 1031 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 1032 } 1033 #endif 1034 1035 /*****************************************************************************/ 1036 /* Embedded PowerPC specific helpers */ 1037 void helper_40x_rfci(CPUPPCState *env) 1038 { 1039 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); 1040 } 1041 1042 void helper_rfci(CPUPPCState *env) 1043 { 1044 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); 1045 } 1046 1047 void helper_rfdi(CPUPPCState *env) 1048 { 1049 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ 1050 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); 1051 } 1052 1053 void helper_rfmci(CPUPPCState *env) 1054 { 1055 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ 1056 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 1057 } 1058 #endif 1059 1060 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 1061 uint32_t flags) 1062 { 1063 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || 1064 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || 1065 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || 1066 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || 1067 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { 1068 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 1069 POWERPC_EXCP_TRAP, GETPC()); 1070 } 1071 } 1072 1073 #if defined(TARGET_PPC64) 1074 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 1075 uint32_t flags) 1076 { 1077 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || 1078 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || 1079 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || 1080 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || 1081 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { 1082 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 1083 POWERPC_EXCP_TRAP, GETPC()); 1084 } 1085 } 1086 #endif 1087 1088 #if !defined(CONFIG_USER_ONLY) 1089 /*****************************************************************************/ 1090 /* PowerPC 601 specific instructions (POWER bridge) */ 1091 1092 void helper_rfsvc(CPUPPCState *env) 1093 { 1094 do_rfi(env, env->lr, env->ctr & 0x0000FFFF); 1095 } 1096 1097 /* Embedded.Processor Control */ 1098 static int dbell2irq(target_ulong rb) 1099 { 1100 int msg = rb & DBELL_TYPE_MASK; 1101 int irq = -1; 1102 1103 switch (msg) { 1104 case DBELL_TYPE_DBELL: 1105 irq = PPC_INTERRUPT_DOORBELL; 1106 break; 1107 case DBELL_TYPE_DBELL_CRIT: 1108 irq = PPC_INTERRUPT_CDOORBELL; 1109 break; 1110 case DBELL_TYPE_G_DBELL: 1111 case DBELL_TYPE_G_DBELL_CRIT: 1112 case DBELL_TYPE_G_DBELL_MC: 1113 /* XXX implement */ 1114 default: 1115 break; 1116 } 1117 1118 return irq; 1119 } 1120 1121 void helper_msgclr(CPUPPCState *env, target_ulong rb) 1122 { 1123 int irq = dbell2irq(rb); 1124 1125 if (irq < 0) { 1126 return; 1127 } 1128 1129 env->pending_interrupts &= ~(1 << irq); 1130 } 1131 1132 void helper_msgsnd(target_ulong rb) 1133 { 1134 int irq = dbell2irq(rb); 1135 int pir = rb & DBELL_PIRTAG_MASK; 1136 CPUState *cs; 1137 1138 if (irq < 0) { 1139 return; 1140 } 1141 1142 qemu_mutex_lock_iothread(); 1143 CPU_FOREACH(cs) { 1144 PowerPCCPU *cpu = POWERPC_CPU(cs); 1145 CPUPPCState *cenv = &cpu->env; 1146 1147 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { 1148 cenv->pending_interrupts |= 1 << irq; 1149 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 1150 } 1151 } 1152 qemu_mutex_unlock_iothread(); 1153 } 1154 1155 /* Server Processor Control */ 1156 static int book3s_dbell2irq(target_ulong rb) 1157 { 1158 int msg = rb & DBELL_TYPE_MASK; 1159 1160 /* A Directed Hypervisor Doorbell message is sent only if the 1161 * message type is 5. All other types are reserved and the 1162 * instruction is a no-op */ 1163 return msg == DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : -1; 1164 } 1165 1166 void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) 1167 { 1168 int irq = book3s_dbell2irq(rb); 1169 1170 if (irq < 0) { 1171 return; 1172 } 1173 1174 env->pending_interrupts &= ~(1 << irq); 1175 } 1176 1177 void helper_book3s_msgsnd(target_ulong rb) 1178 { 1179 int irq = book3s_dbell2irq(rb); 1180 int pir = rb & DBELL_PROCIDTAG_MASK; 1181 CPUState *cs; 1182 1183 if (irq < 0) { 1184 return; 1185 } 1186 1187 qemu_mutex_lock_iothread(); 1188 CPU_FOREACH(cs) { 1189 PowerPCCPU *cpu = POWERPC_CPU(cs); 1190 CPUPPCState *cenv = &cpu->env; 1191 1192 /* TODO: broadcast message to all threads of the same processor */ 1193 if (cenv->spr_cb[SPR_PIR].default_value == pir) { 1194 cenv->pending_interrupts |= 1 << irq; 1195 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 1196 } 1197 } 1198 qemu_mutex_unlock_iothread(); 1199 } 1200 #endif 1201