1 /* 2 * PowerPC exception emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/main-loop.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "exec/exec-all.h" 24 #include "exec/cpu_ldst.h" 25 #include "internal.h" 26 #include "helper_regs.h" 27 28 //#define DEBUG_OP 29 //#define DEBUG_SOFTWARE_TLB 30 //#define DEBUG_EXCEPTIONS 31 32 #ifdef DEBUG_EXCEPTIONS 33 # define LOG_EXCP(...) qemu_log(__VA_ARGS__) 34 #else 35 # define LOG_EXCP(...) do { } while (0) 36 #endif 37 38 /*****************************************************************************/ 39 /* Exception processing */ 40 #if defined(CONFIG_USER_ONLY) 41 void ppc_cpu_do_interrupt(CPUState *cs) 42 { 43 PowerPCCPU *cpu = POWERPC_CPU(cs); 44 CPUPPCState *env = &cpu->env; 45 46 cs->exception_index = POWERPC_EXCP_NONE; 47 env->error_code = 0; 48 } 49 50 static void ppc_hw_interrupt(CPUPPCState *env) 51 { 52 CPUState *cs = CPU(ppc_env_get_cpu(env)); 53 54 cs->exception_index = POWERPC_EXCP_NONE; 55 env->error_code = 0; 56 } 57 #else /* defined(CONFIG_USER_ONLY) */ 58 static inline void dump_syscall(CPUPPCState *env) 59 { 60 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 61 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 62 " nip=" TARGET_FMT_lx "\n", 63 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), 64 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), 65 ppc_dump_gpr(env, 6), env->nip); 66 } 67 68 /* Note that this function should be greatly optimized 69 * when called with a constant excp, from ppc_hw_interrupt 70 */ 71 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) 72 { 73 CPUState *cs = CPU(cpu); 74 CPUPPCState *env = &cpu->env; 75 target_ulong msr, new_msr, vector; 76 int srr0, srr1, asrr0, asrr1, lev, ail; 77 bool lpes0; 78 79 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx 80 " => %08x (%02x)\n", env->nip, excp, env->error_code); 81 82 /* new srr1 value excluding must-be-zero bits */ 83 if (excp_model == POWERPC_EXCP_BOOKE) { 84 msr = env->msr; 85 } else { 86 msr = env->msr & ~0x783f0000ULL; 87 } 88 89 /* new interrupt handler msr preserves existing HV and ME unless 90 * explicitly overriden 91 */ 92 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); 93 94 /* target registers */ 95 srr0 = SPR_SRR0; 96 srr1 = SPR_SRR1; 97 asrr0 = -1; 98 asrr1 = -1; 99 100 /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */ 101 if (env->in_pm_state) { 102 env->in_pm_state = false; 103 104 /* Pretend to be returning from doze always as we don't lose state */ 105 msr |= (0x1ull << (63 - 47)); 106 107 /* Non-machine check are routed to 0x100 with a wakeup cause 108 * encoded in SRR1 109 */ 110 if (excp != POWERPC_EXCP_MCHECK) { 111 switch (excp) { 112 case POWERPC_EXCP_RESET: 113 msr |= 0x4ull << (63 - 45); 114 break; 115 case POWERPC_EXCP_EXTERNAL: 116 msr |= 0x8ull << (63 - 45); 117 break; 118 case POWERPC_EXCP_DECR: 119 msr |= 0x6ull << (63 - 45); 120 break; 121 case POWERPC_EXCP_SDOOR: 122 msr |= 0x5ull << (63 - 45); 123 break; 124 case POWERPC_EXCP_SDOOR_HV: 125 msr |= 0x3ull << (63 - 45); 126 break; 127 case POWERPC_EXCP_HV_MAINT: 128 msr |= 0xaull << (63 - 45); 129 break; 130 default: 131 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", 132 excp); 133 } 134 excp = POWERPC_EXCP_RESET; 135 } 136 } 137 138 /* Exception targetting modifiers 139 * 140 * LPES0 is supported on POWER7/8 141 * LPES1 is not supported (old iSeries mode) 142 * 143 * On anything else, we behave as if LPES0 is 1 144 * (externals don't alter MSR:HV) 145 * 146 * AIL is initialized here but can be cleared by 147 * selected exceptions 148 */ 149 #if defined(TARGET_PPC64) 150 if (excp_model == POWERPC_EXCP_POWER7 || 151 excp_model == POWERPC_EXCP_POWER8) { 152 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 153 if (excp_model == POWERPC_EXCP_POWER8) { 154 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; 155 } else { 156 ail = 0; 157 } 158 } else 159 #endif /* defined(TARGET_PPC64) */ 160 { 161 lpes0 = true; 162 ail = 0; 163 } 164 165 /* Hypervisor emulation assistance interrupt only exists on server 166 * arch 2.05 server or later. We also don't want to generate it if 167 * we don't have HVB in msr_mask (PAPR mode). 168 */ 169 if (excp == POWERPC_EXCP_HV_EMU 170 #if defined(TARGET_PPC64) 171 && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) 172 #endif /* defined(TARGET_PPC64) */ 173 174 ) { 175 excp = POWERPC_EXCP_PROGRAM; 176 } 177 178 switch (excp) { 179 case POWERPC_EXCP_NONE: 180 /* Should never happen */ 181 return; 182 case POWERPC_EXCP_CRITICAL: /* Critical input */ 183 switch (excp_model) { 184 case POWERPC_EXCP_40x: 185 srr0 = SPR_40x_SRR2; 186 srr1 = SPR_40x_SRR3; 187 break; 188 case POWERPC_EXCP_BOOKE: 189 srr0 = SPR_BOOKE_CSRR0; 190 srr1 = SPR_BOOKE_CSRR1; 191 break; 192 case POWERPC_EXCP_G2: 193 break; 194 default: 195 goto excp_invalid; 196 } 197 break; 198 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 199 if (msr_me == 0) { 200 /* Machine check exception is not enabled. 201 * Enter checkstop state. 202 */ 203 fprintf(stderr, "Machine check while not allowed. " 204 "Entering checkstop state\n"); 205 if (qemu_log_separate()) { 206 qemu_log("Machine check while not allowed. " 207 "Entering checkstop state\n"); 208 } 209 cs->halted = 1; 210 cpu_interrupt_exittb(cs); 211 } 212 if (env->msr_mask & MSR_HVB) { 213 /* ISA specifies HV, but can be delivered to guest with HV clear 214 * (e.g., see FWNMI in PAPR). 215 */ 216 new_msr |= (target_ulong)MSR_HVB; 217 } 218 ail = 0; 219 220 /* machine check exceptions don't have ME set */ 221 new_msr &= ~((target_ulong)1 << MSR_ME); 222 223 /* XXX: should also have something loaded in DAR / DSISR */ 224 switch (excp_model) { 225 case POWERPC_EXCP_40x: 226 srr0 = SPR_40x_SRR2; 227 srr1 = SPR_40x_SRR3; 228 break; 229 case POWERPC_EXCP_BOOKE: 230 /* FIXME: choose one or the other based on CPU type */ 231 srr0 = SPR_BOOKE_MCSRR0; 232 srr1 = SPR_BOOKE_MCSRR1; 233 asrr0 = SPR_BOOKE_CSRR0; 234 asrr1 = SPR_BOOKE_CSRR1; 235 break; 236 default: 237 break; 238 } 239 break; 240 case POWERPC_EXCP_DSI: /* Data storage exception */ 241 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx 242 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); 243 break; 244 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 245 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx 246 "\n", msr, env->nip); 247 msr |= env->error_code; 248 break; 249 case POWERPC_EXCP_EXTERNAL: /* External input */ 250 cs = CPU(cpu); 251 252 if (!lpes0) { 253 new_msr |= (target_ulong)MSR_HVB; 254 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 255 srr0 = SPR_HSRR0; 256 srr1 = SPR_HSRR1; 257 } 258 if (env->mpic_proxy) { 259 /* IACK the IRQ on delivery */ 260 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); 261 } 262 break; 263 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 264 /* Get rS/rD and rA from faulting opcode */ 265 /* Note: the opcode fields will not be set properly for a direct 266 * store load/store, but nobody cares as nobody actually uses 267 * direct store segments. 268 */ 269 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 270 break; 271 case POWERPC_EXCP_PROGRAM: /* Program exception */ 272 switch (env->error_code & ~0xF) { 273 case POWERPC_EXCP_FP: 274 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { 275 LOG_EXCP("Ignore floating point exception\n"); 276 cs->exception_index = POWERPC_EXCP_NONE; 277 env->error_code = 0; 278 return; 279 } 280 281 /* FP exceptions always have NIP pointing to the faulting 282 * instruction, so always use store_next and claim we are 283 * precise in the MSR. 284 */ 285 msr |= 0x00100000; 286 env->spr[SPR_BOOKE_ESR] = ESR_FP; 287 break; 288 case POWERPC_EXCP_INVAL: 289 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); 290 msr |= 0x00080000; 291 env->spr[SPR_BOOKE_ESR] = ESR_PIL; 292 break; 293 case POWERPC_EXCP_PRIV: 294 msr |= 0x00040000; 295 env->spr[SPR_BOOKE_ESR] = ESR_PPR; 296 break; 297 case POWERPC_EXCP_TRAP: 298 msr |= 0x00020000; 299 env->spr[SPR_BOOKE_ESR] = ESR_PTR; 300 break; 301 default: 302 /* Should never occur */ 303 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 304 env->error_code); 305 break; 306 } 307 break; 308 case POWERPC_EXCP_SYSCALL: /* System call exception */ 309 dump_syscall(env); 310 lev = env->error_code; 311 312 /* We need to correct the NIP which in this case is supposed 313 * to point to the next instruction 314 */ 315 env->nip += 4; 316 317 /* "PAPR mode" built-in hypercall emulation */ 318 if ((lev == 1) && cpu->vhyp) { 319 PPCVirtualHypervisorClass *vhc = 320 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 321 vhc->hypercall(cpu->vhyp, cpu); 322 return; 323 } 324 if (lev == 1) { 325 new_msr |= (target_ulong)MSR_HVB; 326 } 327 break; 328 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 329 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 330 case POWERPC_EXCP_DECR: /* Decrementer exception */ 331 break; 332 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 333 /* FIT on 4xx */ 334 LOG_EXCP("FIT exception\n"); 335 break; 336 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 337 LOG_EXCP("WDT exception\n"); 338 switch (excp_model) { 339 case POWERPC_EXCP_BOOKE: 340 srr0 = SPR_BOOKE_CSRR0; 341 srr1 = SPR_BOOKE_CSRR1; 342 break; 343 default: 344 break; 345 } 346 break; 347 case POWERPC_EXCP_DTLB: /* Data TLB error */ 348 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 349 break; 350 case POWERPC_EXCP_DEBUG: /* Debug interrupt */ 351 if (env->flags & POWERPC_FLAG_DE) { 352 /* FIXME: choose one or the other based on CPU type */ 353 srr0 = SPR_BOOKE_DSRR0; 354 srr1 = SPR_BOOKE_DSRR1; 355 asrr0 = SPR_BOOKE_CSRR0; 356 asrr1 = SPR_BOOKE_CSRR1; 357 /* DBSR already modified by caller */ 358 } else { 359 cpu_abort(cs, "Debug exception triggered on unsupported model\n"); 360 } 361 break; 362 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ 363 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 364 break; 365 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ 366 /* XXX: TODO */ 367 cpu_abort(cs, "Embedded floating point data exception " 368 "is not implemented yet !\n"); 369 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 370 break; 371 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ 372 /* XXX: TODO */ 373 cpu_abort(cs, "Embedded floating point round exception " 374 "is not implemented yet !\n"); 375 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 376 break; 377 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ 378 /* XXX: TODO */ 379 cpu_abort(cs, 380 "Performance counter exception is not implemented yet !\n"); 381 break; 382 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 383 break; 384 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 385 srr0 = SPR_BOOKE_CSRR0; 386 srr1 = SPR_BOOKE_CSRR1; 387 break; 388 case POWERPC_EXCP_RESET: /* System reset exception */ 389 /* A power-saving exception sets ME, otherwise it is unchanged */ 390 if (msr_pow) { 391 /* indicate that we resumed from power save mode */ 392 msr |= 0x10000; 393 new_msr |= ((target_ulong)1 << MSR_ME); 394 } 395 if (env->msr_mask & MSR_HVB) { 396 /* ISA specifies HV, but can be delivered to guest with HV clear 397 * (e.g., see FWNMI in PAPR, NMI injection in QEMU). 398 */ 399 new_msr |= (target_ulong)MSR_HVB; 400 } else { 401 if (msr_pow) { 402 cpu_abort(cs, "Trying to deliver power-saving system reset " 403 "exception %d with no HV support\n", excp); 404 } 405 } 406 ail = 0; 407 break; 408 case POWERPC_EXCP_DSEG: /* Data segment exception */ 409 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 410 case POWERPC_EXCP_TRACE: /* Trace exception */ 411 break; 412 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 413 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 414 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ 415 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 416 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ 417 case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ 418 case POWERPC_EXCP_HV_EMU: 419 srr0 = SPR_HSRR0; 420 srr1 = SPR_HSRR1; 421 new_msr |= (target_ulong)MSR_HVB; 422 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 423 break; 424 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 425 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ 426 case POWERPC_EXCP_FU: /* Facility unavailable exception */ 427 #ifdef TARGET_PPC64 428 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); 429 #endif 430 break; 431 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ 432 LOG_EXCP("PIT exception\n"); 433 break; 434 case POWERPC_EXCP_IO: /* IO error exception */ 435 /* XXX: TODO */ 436 cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); 437 break; 438 case POWERPC_EXCP_RUNM: /* Run mode exception */ 439 /* XXX: TODO */ 440 cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); 441 break; 442 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 443 /* XXX: TODO */ 444 cpu_abort(cs, "602 emulation trap exception " 445 "is not implemented yet !\n"); 446 break; 447 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 448 switch (excp_model) { 449 case POWERPC_EXCP_602: 450 case POWERPC_EXCP_603: 451 case POWERPC_EXCP_603E: 452 case POWERPC_EXCP_G2: 453 goto tlb_miss_tgpr; 454 case POWERPC_EXCP_7x5: 455 goto tlb_miss; 456 case POWERPC_EXCP_74xx: 457 goto tlb_miss_74xx; 458 default: 459 cpu_abort(cs, "Invalid instruction TLB miss exception\n"); 460 break; 461 } 462 break; 463 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 464 switch (excp_model) { 465 case POWERPC_EXCP_602: 466 case POWERPC_EXCP_603: 467 case POWERPC_EXCP_603E: 468 case POWERPC_EXCP_G2: 469 goto tlb_miss_tgpr; 470 case POWERPC_EXCP_7x5: 471 goto tlb_miss; 472 case POWERPC_EXCP_74xx: 473 goto tlb_miss_74xx; 474 default: 475 cpu_abort(cs, "Invalid data load TLB miss exception\n"); 476 break; 477 } 478 break; 479 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 480 switch (excp_model) { 481 case POWERPC_EXCP_602: 482 case POWERPC_EXCP_603: 483 case POWERPC_EXCP_603E: 484 case POWERPC_EXCP_G2: 485 tlb_miss_tgpr: 486 /* Swap temporary saved registers with GPRs */ 487 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { 488 new_msr |= (target_ulong)1 << MSR_TGPR; 489 hreg_swap_gpr_tgpr(env); 490 } 491 goto tlb_miss; 492 case POWERPC_EXCP_7x5: 493 tlb_miss: 494 #if defined(DEBUG_SOFTWARE_TLB) 495 if (qemu_log_enabled()) { 496 const char *es; 497 target_ulong *miss, *cmp; 498 int en; 499 500 if (excp == POWERPC_EXCP_IFTLB) { 501 es = "I"; 502 en = 'I'; 503 miss = &env->spr[SPR_IMISS]; 504 cmp = &env->spr[SPR_ICMP]; 505 } else { 506 if (excp == POWERPC_EXCP_DLTLB) { 507 es = "DL"; 508 } else { 509 es = "DS"; 510 } 511 en = 'D'; 512 miss = &env->spr[SPR_DMISS]; 513 cmp = &env->spr[SPR_DCMP]; 514 } 515 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " 516 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " 517 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, 518 env->spr[SPR_HASH1], env->spr[SPR_HASH2], 519 env->error_code); 520 } 521 #endif 522 msr |= env->crf[0] << 28; 523 msr |= env->error_code; /* key, D/I, S/L bits */ 524 /* Set way using a LRU mechanism */ 525 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; 526 break; 527 case POWERPC_EXCP_74xx: 528 tlb_miss_74xx: 529 #if defined(DEBUG_SOFTWARE_TLB) 530 if (qemu_log_enabled()) { 531 const char *es; 532 target_ulong *miss, *cmp; 533 int en; 534 535 if (excp == POWERPC_EXCP_IFTLB) { 536 es = "I"; 537 en = 'I'; 538 miss = &env->spr[SPR_TLBMISS]; 539 cmp = &env->spr[SPR_PTEHI]; 540 } else { 541 if (excp == POWERPC_EXCP_DLTLB) { 542 es = "DL"; 543 } else { 544 es = "DS"; 545 } 546 en = 'D'; 547 miss = &env->spr[SPR_TLBMISS]; 548 cmp = &env->spr[SPR_PTEHI]; 549 } 550 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " 551 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, 552 env->error_code); 553 } 554 #endif 555 msr |= env->error_code; /* key bit */ 556 break; 557 default: 558 cpu_abort(cs, "Invalid data store TLB miss exception\n"); 559 break; 560 } 561 break; 562 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 563 /* XXX: TODO */ 564 cpu_abort(cs, "Floating point assist exception " 565 "is not implemented yet !\n"); 566 break; 567 case POWERPC_EXCP_DABR: /* Data address breakpoint */ 568 /* XXX: TODO */ 569 cpu_abort(cs, "DABR exception is not implemented yet !\n"); 570 break; 571 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 572 /* XXX: TODO */ 573 cpu_abort(cs, "IABR exception is not implemented yet !\n"); 574 break; 575 case POWERPC_EXCP_SMI: /* System management interrupt */ 576 /* XXX: TODO */ 577 cpu_abort(cs, "SMI exception is not implemented yet !\n"); 578 break; 579 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 580 /* XXX: TODO */ 581 cpu_abort(cs, "Thermal management exception " 582 "is not implemented yet !\n"); 583 break; 584 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ 585 /* XXX: TODO */ 586 cpu_abort(cs, 587 "Performance counter exception is not implemented yet !\n"); 588 break; 589 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 590 /* XXX: TODO */ 591 cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); 592 break; 593 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 594 /* XXX: TODO */ 595 cpu_abort(cs, 596 "970 soft-patch exception is not implemented yet !\n"); 597 break; 598 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 599 /* XXX: TODO */ 600 cpu_abort(cs, 601 "970 maintenance exception is not implemented yet !\n"); 602 break; 603 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ 604 /* XXX: TODO */ 605 cpu_abort(cs, "Maskable external exception " 606 "is not implemented yet !\n"); 607 break; 608 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ 609 /* XXX: TODO */ 610 cpu_abort(cs, "Non maskable external exception " 611 "is not implemented yet !\n"); 612 break; 613 default: 614 excp_invalid: 615 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 616 break; 617 } 618 619 /* Save PC */ 620 env->spr[srr0] = env->nip; 621 622 /* Save MSR */ 623 env->spr[srr1] = msr; 624 625 /* Sanity check */ 626 if (!(env->msr_mask & MSR_HVB)) { 627 if (new_msr & MSR_HVB) { 628 cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " 629 "no HV support\n", excp); 630 } 631 if (srr0 == SPR_HSRR0) { 632 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " 633 "no HV support\n", excp); 634 } 635 } 636 637 /* If any alternate SRR register are defined, duplicate saved values */ 638 if (asrr0 != -1) { 639 env->spr[asrr0] = env->spr[srr0]; 640 } 641 if (asrr1 != -1) { 642 env->spr[asrr1] = env->spr[srr1]; 643 } 644 645 /* Sort out endianness of interrupt, this differs depending on the 646 * CPU, the HV mode, etc... 647 */ 648 #ifdef TARGET_PPC64 649 if (excp_model == POWERPC_EXCP_POWER7) { 650 if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { 651 new_msr |= (target_ulong)1 << MSR_LE; 652 } 653 } else if (excp_model == POWERPC_EXCP_POWER8) { 654 if (new_msr & MSR_HVB) { 655 if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) { 656 new_msr |= (target_ulong)1 << MSR_LE; 657 } 658 } else if (env->spr[SPR_LPCR] & LPCR_ILE) { 659 new_msr |= (target_ulong)1 << MSR_LE; 660 } 661 } else if (msr_ile) { 662 new_msr |= (target_ulong)1 << MSR_LE; 663 } 664 #else 665 if (msr_ile) { 666 new_msr |= (target_ulong)1 << MSR_LE; 667 } 668 #endif 669 670 /* Jump to handler */ 671 vector = env->excp_vectors[excp]; 672 if (vector == (target_ulong)-1ULL) { 673 cpu_abort(cs, "Raised an exception without defined vector %d\n", 674 excp); 675 } 676 vector |= env->excp_prefix; 677 678 /* AIL only works if there is no HV transition and we are running with 679 * translations enabled 680 */ 681 if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || 682 ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { 683 ail = 0; 684 } 685 /* Handle AIL */ 686 if (ail) { 687 new_msr |= (1 << MSR_IR) | (1 << MSR_DR); 688 switch(ail) { 689 case AIL_0001_8000: 690 vector |= 0x18000; 691 break; 692 case AIL_C000_0000_0000_4000: 693 vector |= 0xc000000000004000ull; 694 break; 695 default: 696 cpu_abort(cs, "Invalid AIL combination %d\n", ail); 697 break; 698 } 699 } 700 701 #if defined(TARGET_PPC64) 702 if (excp_model == POWERPC_EXCP_BOOKE) { 703 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { 704 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ 705 new_msr |= (target_ulong)1 << MSR_CM; 706 } else { 707 vector = (uint32_t)vector; 708 } 709 } else { 710 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { 711 vector = (uint32_t)vector; 712 } else { 713 new_msr |= (target_ulong)1 << MSR_SF; 714 } 715 } 716 #endif 717 /* We don't use hreg_store_msr here as already have treated 718 * any special case that could occur. Just store MSR and update hflags 719 * 720 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it 721 * will prevent setting of the HV bit which some exceptions might need 722 * to do. 723 */ 724 env->msr = new_msr & env->msr_mask; 725 hreg_compute_hflags(env); 726 env->nip = vector; 727 /* Reset exception state */ 728 cs->exception_index = POWERPC_EXCP_NONE; 729 env->error_code = 0; 730 731 /* Reset the reservation */ 732 env->reserve_addr = -1; 733 734 /* Any interrupt is context synchronizing, check if TCG TLB 735 * needs a delayed flush on ppc64 736 */ 737 check_tlb_flush(env, false); 738 } 739 740 void ppc_cpu_do_interrupt(CPUState *cs) 741 { 742 PowerPCCPU *cpu = POWERPC_CPU(cs); 743 CPUPPCState *env = &cpu->env; 744 745 powerpc_excp(cpu, env->excp_model, cs->exception_index); 746 } 747 748 static void ppc_hw_interrupt(CPUPPCState *env) 749 { 750 PowerPCCPU *cpu = ppc_env_get_cpu(env); 751 752 /* External reset */ 753 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { 754 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); 755 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); 756 return; 757 } 758 /* Machine check exception */ 759 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { 760 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); 761 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); 762 return; 763 } 764 #if 0 /* TODO */ 765 /* External debug exception */ 766 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { 767 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); 768 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); 769 return; 770 } 771 #endif 772 /* Hypervisor decrementer exception */ 773 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { 774 /* LPCR will be clear when not supported so this will work */ 775 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 776 if ((msr_ee != 0 || msr_hv == 0) && hdice) { 777 /* HDEC clears on delivery */ 778 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); 779 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); 780 return; 781 } 782 } 783 /* Extermal interrupt can ignore MSR:EE under some circumstances */ 784 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { 785 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 786 if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) { 787 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); 788 return; 789 } 790 } 791 if (msr_ce != 0) { 792 /* External critical interrupt */ 793 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { 794 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); 795 return; 796 } 797 } 798 if (msr_ee != 0) { 799 /* Watchdog timer on embedded PowerPC */ 800 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { 801 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); 802 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); 803 return; 804 } 805 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { 806 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); 807 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); 808 return; 809 } 810 /* Fixed interval timer on embedded PowerPC */ 811 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { 812 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); 813 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); 814 return; 815 } 816 /* Programmable interval timer on embedded PowerPC */ 817 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { 818 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); 819 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); 820 return; 821 } 822 /* Decrementer exception */ 823 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { 824 if (ppc_decr_clear_on_delivery(env)) { 825 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); 826 } 827 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); 828 return; 829 } 830 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { 831 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); 832 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); 833 return; 834 } 835 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) { 836 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL); 837 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV); 838 return; 839 } 840 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { 841 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); 842 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); 843 return; 844 } 845 /* Thermal interrupt */ 846 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { 847 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); 848 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); 849 return; 850 } 851 } 852 } 853 854 void ppc_cpu_do_system_reset(CPUState *cs) 855 { 856 PowerPCCPU *cpu = POWERPC_CPU(cs); 857 CPUPPCState *env = &cpu->env; 858 859 powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); 860 } 861 #endif /* !CONFIG_USER_ONLY */ 862 863 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 864 { 865 PowerPCCPU *cpu = POWERPC_CPU(cs); 866 CPUPPCState *env = &cpu->env; 867 868 if (interrupt_request & CPU_INTERRUPT_HARD) { 869 ppc_hw_interrupt(env); 870 if (env->pending_interrupts == 0) { 871 cs->interrupt_request &= ~CPU_INTERRUPT_HARD; 872 } 873 return true; 874 } 875 return false; 876 } 877 878 #if defined(DEBUG_OP) 879 static void cpu_dump_rfi(target_ulong RA, target_ulong msr) 880 { 881 qemu_log("Return from exception at " TARGET_FMT_lx " with flags " 882 TARGET_FMT_lx "\n", RA, msr); 883 } 884 #endif 885 886 /*****************************************************************************/ 887 /* Exceptions processing helpers */ 888 889 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 890 uint32_t error_code, uintptr_t raddr) 891 { 892 CPUState *cs = CPU(ppc_env_get_cpu(env)); 893 894 cs->exception_index = exception; 895 env->error_code = error_code; 896 cpu_loop_exit_restore(cs, raddr); 897 } 898 899 void raise_exception_err(CPUPPCState *env, uint32_t exception, 900 uint32_t error_code) 901 { 902 raise_exception_err_ra(env, exception, error_code, 0); 903 } 904 905 void raise_exception(CPUPPCState *env, uint32_t exception) 906 { 907 raise_exception_err_ra(env, exception, 0, 0); 908 } 909 910 void raise_exception_ra(CPUPPCState *env, uint32_t exception, 911 uintptr_t raddr) 912 { 913 raise_exception_err_ra(env, exception, 0, raddr); 914 } 915 916 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, 917 uint32_t error_code) 918 { 919 raise_exception_err_ra(env, exception, error_code, 0); 920 } 921 922 void helper_raise_exception(CPUPPCState *env, uint32_t exception) 923 { 924 raise_exception_err_ra(env, exception, 0, 0); 925 } 926 927 #if !defined(CONFIG_USER_ONLY) 928 void helper_store_msr(CPUPPCState *env, target_ulong val) 929 { 930 uint32_t excp = hreg_store_msr(env, val, 0); 931 932 if (excp != 0) { 933 CPUState *cs = CPU(ppc_env_get_cpu(env)); 934 cpu_interrupt_exittb(cs); 935 raise_exception(env, excp); 936 } 937 } 938 939 #if defined(TARGET_PPC64) 940 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) 941 { 942 CPUState *cs; 943 944 cs = CPU(ppc_env_get_cpu(env)); 945 cs->halted = 1; 946 env->in_pm_state = true; 947 948 /* The architecture specifies that HDEC interrupts are 949 * discarded in PM states 950 */ 951 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); 952 953 /* Technically, nap doesn't set EE, but if we don't set it 954 * then ppc_hw_interrupt() won't deliver. We could add some 955 * other tests there based on LPCR but it's simpler to just 956 * whack EE in. It will be cleared by the 0x100 at wakeup 957 * anyway. It will still be observable by the guest in SRR1 958 * but this doesn't seem to be a problem. 959 */ 960 env->msr |= (1ull << MSR_EE); 961 raise_exception(env, EXCP_HLT); 962 } 963 #endif /* defined(TARGET_PPC64) */ 964 965 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) 966 { 967 CPUState *cs = CPU(ppc_env_get_cpu(env)); 968 969 /* MSR:POW cannot be set by any form of rfi */ 970 msr &= ~(1ULL << MSR_POW); 971 972 #if defined(TARGET_PPC64) 973 /* Switching to 32-bit ? Crop the nip */ 974 if (!msr_is_64bit(env, msr)) { 975 nip = (uint32_t)nip; 976 } 977 #else 978 nip = (uint32_t)nip; 979 #endif 980 /* XXX: beware: this is false if VLE is supported */ 981 env->nip = nip & ~((target_ulong)0x00000003); 982 hreg_store_msr(env, msr, 1); 983 #if defined(DEBUG_OP) 984 cpu_dump_rfi(env->nip, env->msr); 985 #endif 986 /* No need to raise an exception here, 987 * as rfi is always the last insn of a TB 988 */ 989 cpu_interrupt_exittb(cs); 990 /* Reset the reservation */ 991 env->reserve_addr = -1; 992 993 /* Context synchronizing: check if TCG TLB needs flush */ 994 check_tlb_flush(env, false); 995 } 996 997 void helper_rfi(CPUPPCState *env) 998 { 999 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); 1000 } 1001 1002 #define MSR_BOOK3S_MASK 1003 #if defined(TARGET_PPC64) 1004 void helper_rfid(CPUPPCState *env) 1005 { 1006 /* The architeture defines a number of rules for which bits 1007 * can change but in practice, we handle this in hreg_store_msr() 1008 * which will be called by do_rfi(), so there is no need to filter 1009 * here 1010 */ 1011 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); 1012 } 1013 1014 void helper_hrfid(CPUPPCState *env) 1015 { 1016 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 1017 } 1018 #endif 1019 1020 /*****************************************************************************/ 1021 /* Embedded PowerPC specific helpers */ 1022 void helper_40x_rfci(CPUPPCState *env) 1023 { 1024 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); 1025 } 1026 1027 void helper_rfci(CPUPPCState *env) 1028 { 1029 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); 1030 } 1031 1032 void helper_rfdi(CPUPPCState *env) 1033 { 1034 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ 1035 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); 1036 } 1037 1038 void helper_rfmci(CPUPPCState *env) 1039 { 1040 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ 1041 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 1042 } 1043 #endif 1044 1045 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 1046 uint32_t flags) 1047 { 1048 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || 1049 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || 1050 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || 1051 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || 1052 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { 1053 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 1054 POWERPC_EXCP_TRAP, GETPC()); 1055 } 1056 } 1057 1058 #if defined(TARGET_PPC64) 1059 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 1060 uint32_t flags) 1061 { 1062 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || 1063 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || 1064 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || 1065 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || 1066 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { 1067 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 1068 POWERPC_EXCP_TRAP, GETPC()); 1069 } 1070 } 1071 #endif 1072 1073 #if !defined(CONFIG_USER_ONLY) 1074 /*****************************************************************************/ 1075 /* PowerPC 601 specific instructions (POWER bridge) */ 1076 1077 void helper_rfsvc(CPUPPCState *env) 1078 { 1079 do_rfi(env, env->lr, env->ctr & 0x0000FFFF); 1080 } 1081 1082 /* Embedded.Processor Control */ 1083 static int dbell2irq(target_ulong rb) 1084 { 1085 int msg = rb & DBELL_TYPE_MASK; 1086 int irq = -1; 1087 1088 switch (msg) { 1089 case DBELL_TYPE_DBELL: 1090 irq = PPC_INTERRUPT_DOORBELL; 1091 break; 1092 case DBELL_TYPE_DBELL_CRIT: 1093 irq = PPC_INTERRUPT_CDOORBELL; 1094 break; 1095 case DBELL_TYPE_G_DBELL: 1096 case DBELL_TYPE_G_DBELL_CRIT: 1097 case DBELL_TYPE_G_DBELL_MC: 1098 /* XXX implement */ 1099 default: 1100 break; 1101 } 1102 1103 return irq; 1104 } 1105 1106 void helper_msgclr(CPUPPCState *env, target_ulong rb) 1107 { 1108 int irq = dbell2irq(rb); 1109 1110 if (irq < 0) { 1111 return; 1112 } 1113 1114 env->pending_interrupts &= ~(1 << irq); 1115 } 1116 1117 void helper_msgsnd(target_ulong rb) 1118 { 1119 int irq = dbell2irq(rb); 1120 int pir = rb & DBELL_PIRTAG_MASK; 1121 CPUState *cs; 1122 1123 if (irq < 0) { 1124 return; 1125 } 1126 1127 qemu_mutex_lock_iothread(); 1128 CPU_FOREACH(cs) { 1129 PowerPCCPU *cpu = POWERPC_CPU(cs); 1130 CPUPPCState *cenv = &cpu->env; 1131 1132 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { 1133 cenv->pending_interrupts |= 1 << irq; 1134 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 1135 } 1136 } 1137 qemu_mutex_unlock_iothread(); 1138 } 1139 1140 /* Server Processor Control */ 1141 static int book3s_dbell2irq(target_ulong rb) 1142 { 1143 int msg = rb & DBELL_TYPE_MASK; 1144 1145 /* A Directed Hypervisor Doorbell message is sent only if the 1146 * message type is 5. All other types are reserved and the 1147 * instruction is a no-op */ 1148 return msg == DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : -1; 1149 } 1150 1151 void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) 1152 { 1153 int irq = book3s_dbell2irq(rb); 1154 1155 if (irq < 0) { 1156 return; 1157 } 1158 1159 env->pending_interrupts &= ~(1 << irq); 1160 } 1161 1162 void helper_book3s_msgsnd(target_ulong rb) 1163 { 1164 int irq = book3s_dbell2irq(rb); 1165 int pir = rb & DBELL_PROCIDTAG_MASK; 1166 CPUState *cs; 1167 1168 if (irq < 0) { 1169 return; 1170 } 1171 1172 qemu_mutex_lock_iothread(); 1173 CPU_FOREACH(cs) { 1174 PowerPCCPU *cpu = POWERPC_CPU(cs); 1175 CPUPPCState *cenv = &cpu->env; 1176 1177 /* TODO: broadcast message to all threads of the same processor */ 1178 if (cenv->spr_cb[SPR_PIR].default_value == pir) { 1179 cenv->pending_interrupts |= 1 << irq; 1180 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 1181 } 1182 } 1183 qemu_mutex_unlock_iothread(); 1184 } 1185 #endif 1186 1187 void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 1188 MMUAccessType access_type, 1189 int mmu_idx, uintptr_t retaddr) 1190 { 1191 CPUPPCState *env = cs->env_ptr; 1192 uint32_t insn; 1193 1194 /* Restore state and reload the insn we executed, for filling in DSISR. */ 1195 cpu_restore_state(cs, retaddr, true); 1196 insn = cpu_ldl_code(env, env->nip); 1197 1198 cs->exception_index = POWERPC_EXCP_ALIGN; 1199 env->error_code = insn & 0x03FF0000; 1200 cpu_loop_exit(cs); 1201 } 1202