1 /* 2 * PowerPC exception emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/main-loop.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "internal.h" 25 #include "helper_regs.h" 26 #include "hw/ppc/ppc.h" 27 28 #include "trace.h" 29 30 #ifdef CONFIG_TCG 31 #include "exec/helper-proto.h" 32 #include "exec/cpu_ldst.h" 33 #endif 34 35 /*****************************************************************************/ 36 /* Exception processing */ 37 #if !defined(CONFIG_USER_ONLY) 38 39 static const char *powerpc_excp_name(int excp) 40 { 41 switch (excp) { 42 case POWERPC_EXCP_CRITICAL: return "CRITICAL"; 43 case POWERPC_EXCP_MCHECK: return "MCHECK"; 44 case POWERPC_EXCP_DSI: return "DSI"; 45 case POWERPC_EXCP_ISI: return "ISI"; 46 case POWERPC_EXCP_EXTERNAL: return "EXTERNAL"; 47 case POWERPC_EXCP_ALIGN: return "ALIGN"; 48 case POWERPC_EXCP_PROGRAM: return "PROGRAM"; 49 case POWERPC_EXCP_FPU: return "FPU"; 50 case POWERPC_EXCP_SYSCALL: return "SYSCALL"; 51 case POWERPC_EXCP_APU: return "APU"; 52 case POWERPC_EXCP_DECR: return "DECR"; 53 case POWERPC_EXCP_FIT: return "FIT"; 54 case POWERPC_EXCP_WDT: return "WDT"; 55 case POWERPC_EXCP_DTLB: return "DTLB"; 56 case POWERPC_EXCP_ITLB: return "ITLB"; 57 case POWERPC_EXCP_DEBUG: return "DEBUG"; 58 case POWERPC_EXCP_SPEU: return "SPEU"; 59 case POWERPC_EXCP_EFPDI: return "EFPDI"; 60 case POWERPC_EXCP_EFPRI: return "EFPRI"; 61 case POWERPC_EXCP_EPERFM: return "EPERFM"; 62 case POWERPC_EXCP_DOORI: return "DOORI"; 63 case POWERPC_EXCP_DOORCI: return "DOORCI"; 64 case POWERPC_EXCP_GDOORI: return "GDOORI"; 65 case POWERPC_EXCP_GDOORCI: return "GDOORCI"; 66 case POWERPC_EXCP_HYPPRIV: return "HYPPRIV"; 67 case POWERPC_EXCP_RESET: return "RESET"; 68 case POWERPC_EXCP_DSEG: return "DSEG"; 69 case POWERPC_EXCP_ISEG: return "ISEG"; 70 case POWERPC_EXCP_HDECR: return "HDECR"; 71 case POWERPC_EXCP_TRACE: return "TRACE"; 72 case POWERPC_EXCP_HDSI: return "HDSI"; 73 case POWERPC_EXCP_HISI: return "HISI"; 74 case POWERPC_EXCP_HDSEG: return "HDSEG"; 75 case POWERPC_EXCP_HISEG: return "HISEG"; 76 case POWERPC_EXCP_VPU: return "VPU"; 77 case POWERPC_EXCP_PIT: return "PIT"; 78 case POWERPC_EXCP_EMUL: return "EMUL"; 79 case POWERPC_EXCP_IFTLB: return "IFTLB"; 80 case POWERPC_EXCP_DLTLB: return "DLTLB"; 81 case POWERPC_EXCP_DSTLB: return "DSTLB"; 82 case POWERPC_EXCP_FPA: return "FPA"; 83 case POWERPC_EXCP_DABR: return "DABR"; 84 case POWERPC_EXCP_IABR: return "IABR"; 85 case POWERPC_EXCP_SMI: return "SMI"; 86 case POWERPC_EXCP_PERFM: return "PERFM"; 87 case POWERPC_EXCP_THERM: return "THERM"; 88 case POWERPC_EXCP_VPUA: return "VPUA"; 89 case POWERPC_EXCP_SOFTP: return "SOFTP"; 90 case POWERPC_EXCP_MAINT: return "MAINT"; 91 case POWERPC_EXCP_MEXTBR: return "MEXTBR"; 92 case POWERPC_EXCP_NMEXTBR: return "NMEXTBR"; 93 case POWERPC_EXCP_ITLBE: return "ITLBE"; 94 case POWERPC_EXCP_DTLBE: return "DTLBE"; 95 case POWERPC_EXCP_VSXU: return "VSXU"; 96 case POWERPC_EXCP_FU: return "FU"; 97 case POWERPC_EXCP_HV_EMU: return "HV_EMU"; 98 case POWERPC_EXCP_HV_MAINT: return "HV_MAINT"; 99 case POWERPC_EXCP_HV_FU: return "HV_FU"; 100 case POWERPC_EXCP_SDOOR: return "SDOOR"; 101 case POWERPC_EXCP_SDOOR_HV: return "SDOOR_HV"; 102 case POWERPC_EXCP_HVIRT: return "HVIRT"; 103 case POWERPC_EXCP_SYSCALL_VECTORED: return "SYSCALL_VECTORED"; 104 default: 105 g_assert_not_reached(); 106 } 107 } 108 109 static void dump_syscall(CPUPPCState *env) 110 { 111 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 112 " r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64 113 " r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64 114 " nip=" TARGET_FMT_lx "\n", 115 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), 116 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), 117 ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7), 118 ppc_dump_gpr(env, 8), env->nip); 119 } 120 121 static void dump_hcall(CPUPPCState *env) 122 { 123 qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64 124 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 125 " r7=%016" PRIx64 " r8=%016" PRIx64 " r9=%016" PRIx64 126 " r10=%016" PRIx64 " r11=%016" PRIx64 " r12=%016" PRIx64 127 " nip=" TARGET_FMT_lx "\n", 128 ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), 129 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), 130 ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8), 131 ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10), 132 ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12), 133 env->nip); 134 } 135 136 static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) 137 { 138 const char *es; 139 target_ulong *miss, *cmp; 140 int en; 141 142 if (!qemu_loglevel_mask(CPU_LOG_MMU)) { 143 return; 144 } 145 146 if (excp == POWERPC_EXCP_IFTLB) { 147 es = "I"; 148 en = 'I'; 149 miss = &env->spr[SPR_IMISS]; 150 cmp = &env->spr[SPR_ICMP]; 151 } else { 152 if (excp == POWERPC_EXCP_DLTLB) { 153 es = "DL"; 154 } else { 155 es = "DS"; 156 } 157 en = 'D'; 158 miss = &env->spr[SPR_DMISS]; 159 cmp = &env->spr[SPR_DCMP]; 160 } 161 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " 162 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " 163 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, 164 env->spr[SPR_HASH1], env->spr[SPR_HASH2], 165 env->error_code); 166 } 167 168 #if defined(TARGET_PPC64) 169 static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, 170 target_ulong *msr) 171 { 172 /* We no longer are in a PM state */ 173 env->resume_as_sreset = false; 174 175 /* Pretend to be returning from doze always as we don't lose state */ 176 *msr |= SRR1_WS_NOLOSS; 177 178 /* Machine checks are sent normally */ 179 if (excp == POWERPC_EXCP_MCHECK) { 180 return excp; 181 } 182 switch (excp) { 183 case POWERPC_EXCP_RESET: 184 *msr |= SRR1_WAKERESET; 185 break; 186 case POWERPC_EXCP_EXTERNAL: 187 *msr |= SRR1_WAKEEE; 188 break; 189 case POWERPC_EXCP_DECR: 190 *msr |= SRR1_WAKEDEC; 191 break; 192 case POWERPC_EXCP_SDOOR: 193 *msr |= SRR1_WAKEDBELL; 194 break; 195 case POWERPC_EXCP_SDOOR_HV: 196 *msr |= SRR1_WAKEHDBELL; 197 break; 198 case POWERPC_EXCP_HV_MAINT: 199 *msr |= SRR1_WAKEHMI; 200 break; 201 case POWERPC_EXCP_HVIRT: 202 *msr |= SRR1_WAKEHVI; 203 break; 204 default: 205 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", 206 excp); 207 } 208 return POWERPC_EXCP_RESET; 209 } 210 211 /* 212 * AIL - Alternate Interrupt Location, a mode that allows interrupts to be 213 * taken with the MMU on, and which uses an alternate location (e.g., so the 214 * kernel/hv can map the vectors there with an effective address). 215 * 216 * An interrupt is considered to be taken "with AIL" or "AIL applies" if they 217 * are delivered in this way. AIL requires the LPCR to be set to enable this 218 * mode, and then a number of conditions have to be true for AIL to apply. 219 * 220 * First of all, SRESET, MCE, and HMI are always delivered without AIL, because 221 * they specifically want to be in real mode (e.g., the MCE might be signaling 222 * a SLB multi-hit which requires SLB flush before the MMU can be enabled). 223 * 224 * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV], 225 * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current 226 * radix mode (LPCR[HR]). 227 * 228 * POWER8, POWER9 with LPCR[HR]=0 229 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | 230 * +-----------+-------------+---------+-------------+-----+ 231 * | a | 00/01/10 | x | x | 0 | 232 * | a | 11 | 0 | 1 | 0 | 233 * | a | 11 | 1 | 1 | a | 234 * | a | 11 | 0 | 0 | a | 235 * +-------------------------------------------------------+ 236 * 237 * POWER9 with LPCR[HR]=1 238 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | 239 * +-----------+-------------+---------+-------------+-----+ 240 * | a | 00/01/10 | x | x | 0 | 241 * | a | 11 | x | x | a | 242 * +-------------------------------------------------------+ 243 * 244 * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to 245 * the hypervisor in AIL mode if the guest is radix. This is good for 246 * performance but allows the guest to influence the AIL of hypervisor 247 * interrupts using its MSR, and also the hypervisor must disallow guest 248 * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to 249 * use AIL for its MSR[HV] 0->1 interrupts. 250 * 251 * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to 252 * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and 253 * MSR[HV] 1->1). 254 * 255 * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1. 256 * 257 * POWER10 behaviour is 258 * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL | 259 * +-----------+------------+-------------+---------+-------------+-----+ 260 * | a | h | 00/01/10 | 0 | 0 | 0 | 261 * | a | h | 11 | 0 | 0 | a | 262 * | a | h | x | 0 | 1 | h | 263 * | a | h | 00/01/10 | 1 | 1 | 0 | 264 * | a | h | 11 | 1 | 1 | h | 265 * +--------------------------------------------------------------------+ 266 */ 267 static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr, 268 target_ulong *new_msr, target_ulong *vector) 269 { 270 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 271 CPUPPCState *env = &cpu->env; 272 bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1); 273 bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB); 274 int ail = 0; 275 276 if (excp == POWERPC_EXCP_MCHECK || 277 excp == POWERPC_EXCP_RESET || 278 excp == POWERPC_EXCP_HV_MAINT) { 279 /* SRESET, MCE, HMI never apply AIL */ 280 return; 281 } 282 283 if (!(pcc->lpcr_mask & LPCR_AIL)) { 284 /* This CPU does not have AIL */ 285 return; 286 } 287 288 /* P8 & P9 */ 289 if (!(pcc->lpcr_mask & LPCR_HAIL)) { 290 if (!mmu_all_on) { 291 /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */ 292 return; 293 } 294 if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { 295 /* 296 * AIL does not work if there is a MSR[HV] 0->1 transition and the 297 * partition is in HPT mode. For radix guests, such interrupts are 298 * allowed to be delivered to the hypervisor in ail mode. 299 */ 300 return; 301 } 302 303 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; 304 if (ail == 0) { 305 return; 306 } 307 if (ail == 1) { 308 /* AIL=1 is reserved, treat it like AIL=0 */ 309 return; 310 } 311 312 /* P10 and up */ 313 } else { 314 if (!mmu_all_on && !hv_escalation) { 315 /* 316 * AIL works for HV interrupts even with guest MSR[IR/DR] disabled. 317 * Guest->guest and HV->HV interrupts do require MMU on. 318 */ 319 return; 320 } 321 322 if (*new_msr & MSR_HVB) { 323 if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { 324 /* HV interrupts depend on LPCR[HAIL] */ 325 return; 326 } 327 ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */ 328 } else { 329 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; 330 } 331 if (ail == 0) { 332 return; 333 } 334 if (ail == 1 || ail == 2) { 335 /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */ 336 return; 337 } 338 } 339 340 /* 341 * AIL applies, so the new MSR gets IR and DR set, and an offset applied 342 * to the new IP. 343 */ 344 *new_msr |= (1 << MSR_IR) | (1 << MSR_DR); 345 346 if (excp != POWERPC_EXCP_SYSCALL_VECTORED) { 347 if (ail == 2) { 348 *vector |= 0x0000000000018000ull; 349 } else if (ail == 3) { 350 *vector |= 0xc000000000004000ull; 351 } 352 } else { 353 /* 354 * scv AIL is a little different. AIL=2 does not change the address, 355 * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000. 356 */ 357 if (ail == 3) { 358 *vector &= ~0x0000000000017000ull; /* Un-apply the base offset */ 359 *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */ 360 } 361 } 362 } 363 #endif 364 365 static void powerpc_reset_excp_state(PowerPCCPU *cpu) 366 { 367 CPUState *cs = CPU(cpu); 368 CPUPPCState *env = &cpu->env; 369 370 /* Reset exception state */ 371 cs->exception_index = POWERPC_EXCP_NONE; 372 env->error_code = 0; 373 } 374 375 static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, 376 target_ulong msr) 377 { 378 CPUPPCState *env = &cpu->env; 379 380 assert((msr & env->msr_mask) == msr); 381 382 /* 383 * We don't use hreg_store_msr here as already have treated any 384 * special case that could occur. Just store MSR and update hflags 385 * 386 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it 387 * will prevent setting of the HV bit which some exceptions might need 388 * to do. 389 */ 390 env->nip = vector; 391 env->msr = msr; 392 hreg_compute_hflags(env); 393 ppc_maybe_interrupt(env); 394 395 powerpc_reset_excp_state(cpu); 396 397 /* 398 * Any interrupt is context synchronizing, check if TCG TLB needs 399 * a delayed flush on ppc64 400 */ 401 check_tlb_flush(env, false); 402 403 /* Reset the reservation */ 404 env->reserve_addr = -1; 405 } 406 407 static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) 408 { 409 CPUState *cs = CPU(cpu); 410 CPUPPCState *env = &cpu->env; 411 target_ulong msr, new_msr, vector; 412 int srr0, srr1; 413 414 /* new srr1 value excluding must-be-zero bits */ 415 msr = env->msr & ~0x783f0000ULL; 416 417 /* 418 * new interrupt handler msr preserves existing ME unless 419 * explicitly overriden. 420 */ 421 new_msr = env->msr & (((target_ulong)1 << MSR_ME)); 422 423 /* target registers */ 424 srr0 = SPR_SRR0; 425 srr1 = SPR_SRR1; 426 427 /* 428 * Hypervisor emulation assistance interrupt only exists on server 429 * arch 2.05 server or later. 430 */ 431 if (excp == POWERPC_EXCP_HV_EMU) { 432 excp = POWERPC_EXCP_PROGRAM; 433 } 434 435 vector = env->excp_vectors[excp]; 436 if (vector == (target_ulong)-1ULL) { 437 cpu_abort(cs, "Raised an exception without defined vector %d\n", 438 excp); 439 } 440 441 vector |= env->excp_prefix; 442 443 switch (excp) { 444 case POWERPC_EXCP_CRITICAL: /* Critical input */ 445 srr0 = SPR_40x_SRR2; 446 srr1 = SPR_40x_SRR3; 447 break; 448 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 449 if (!FIELD_EX64(env->msr, MSR, ME)) { 450 /* 451 * Machine check exception is not enabled. Enter 452 * checkstop state. 453 */ 454 fprintf(stderr, "Machine check while not allowed. " 455 "Entering checkstop state\n"); 456 if (qemu_log_separate()) { 457 qemu_log("Machine check while not allowed. " 458 "Entering checkstop state\n"); 459 } 460 cs->halted = 1; 461 cpu_interrupt_exittb(cs); 462 } 463 464 /* machine check exceptions don't have ME set */ 465 new_msr &= ~((target_ulong)1 << MSR_ME); 466 467 srr0 = SPR_40x_SRR2; 468 srr1 = SPR_40x_SRR3; 469 break; 470 case POWERPC_EXCP_DSI: /* Data storage exception */ 471 trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 472 break; 473 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 474 trace_ppc_excp_isi(msr, env->nip); 475 break; 476 case POWERPC_EXCP_EXTERNAL: /* External input */ 477 break; 478 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 479 break; 480 case POWERPC_EXCP_PROGRAM: /* Program exception */ 481 switch (env->error_code & ~0xF) { 482 case POWERPC_EXCP_FP: 483 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 484 trace_ppc_excp_fp_ignore(); 485 powerpc_reset_excp_state(cpu); 486 return; 487 } 488 env->spr[SPR_40x_ESR] = ESR_FP; 489 break; 490 case POWERPC_EXCP_INVAL: 491 trace_ppc_excp_inval(env->nip); 492 env->spr[SPR_40x_ESR] = ESR_PIL; 493 break; 494 case POWERPC_EXCP_PRIV: 495 env->spr[SPR_40x_ESR] = ESR_PPR; 496 break; 497 case POWERPC_EXCP_TRAP: 498 env->spr[SPR_40x_ESR] = ESR_PTR; 499 break; 500 default: 501 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 502 env->error_code); 503 break; 504 } 505 break; 506 case POWERPC_EXCP_SYSCALL: /* System call exception */ 507 dump_syscall(env); 508 509 /* 510 * We need to correct the NIP which in this case is supposed 511 * to point to the next instruction 512 */ 513 env->nip += 4; 514 break; 515 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 516 trace_ppc_excp_print("FIT"); 517 break; 518 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 519 trace_ppc_excp_print("WDT"); 520 break; 521 case POWERPC_EXCP_DTLB: /* Data TLB error */ 522 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 523 break; 524 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ 525 trace_ppc_excp_print("PIT"); 526 break; 527 case POWERPC_EXCP_DEBUG: /* Debug interrupt */ 528 cpu_abort(cs, "%s exception not implemented\n", 529 powerpc_excp_name(excp)); 530 break; 531 default: 532 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 533 break; 534 } 535 536 /* Save PC */ 537 env->spr[srr0] = env->nip; 538 539 /* Save MSR */ 540 env->spr[srr1] = msr; 541 542 powerpc_set_excp_state(cpu, vector, new_msr); 543 } 544 545 static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) 546 { 547 CPUState *cs = CPU(cpu); 548 CPUPPCState *env = &cpu->env; 549 target_ulong msr, new_msr, vector; 550 551 /* new srr1 value excluding must-be-zero bits */ 552 msr = env->msr & ~0x783f0000ULL; 553 554 /* 555 * new interrupt handler msr preserves existing ME unless 556 * explicitly overriden 557 */ 558 new_msr = env->msr & ((target_ulong)1 << MSR_ME); 559 560 /* 561 * Hypervisor emulation assistance interrupt only exists on server 562 * arch 2.05 server or later. 563 */ 564 if (excp == POWERPC_EXCP_HV_EMU) { 565 excp = POWERPC_EXCP_PROGRAM; 566 } 567 568 vector = env->excp_vectors[excp]; 569 if (vector == (target_ulong)-1ULL) { 570 cpu_abort(cs, "Raised an exception without defined vector %d\n", 571 excp); 572 } 573 574 vector |= env->excp_prefix; 575 576 switch (excp) { 577 case POWERPC_EXCP_CRITICAL: /* Critical input */ 578 break; 579 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 580 if (!FIELD_EX64(env->msr, MSR, ME)) { 581 /* 582 * Machine check exception is not enabled. Enter 583 * checkstop state. 584 */ 585 fprintf(stderr, "Machine check while not allowed. " 586 "Entering checkstop state\n"); 587 if (qemu_log_separate()) { 588 qemu_log("Machine check while not allowed. " 589 "Entering checkstop state\n"); 590 } 591 cs->halted = 1; 592 cpu_interrupt_exittb(cs); 593 } 594 595 /* machine check exceptions don't have ME set */ 596 new_msr &= ~((target_ulong)1 << MSR_ME); 597 598 break; 599 case POWERPC_EXCP_DSI: /* Data storage exception */ 600 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); 601 break; 602 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 603 trace_ppc_excp_isi(msr, env->nip); 604 msr |= env->error_code; 605 break; 606 case POWERPC_EXCP_EXTERNAL: /* External input */ 607 break; 608 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 609 /* Get rS/rD and rA from faulting opcode */ 610 /* 611 * Note: the opcode fields will not be set properly for a 612 * direct store load/store, but nobody cares as nobody 613 * actually uses direct store segments. 614 */ 615 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 616 break; 617 case POWERPC_EXCP_PROGRAM: /* Program exception */ 618 switch (env->error_code & ~0xF) { 619 case POWERPC_EXCP_FP: 620 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 621 trace_ppc_excp_fp_ignore(); 622 powerpc_reset_excp_state(cpu); 623 return; 624 } 625 626 /* 627 * FP exceptions always have NIP pointing to the faulting 628 * instruction, so always use store_next and claim we are 629 * precise in the MSR. 630 */ 631 msr |= 0x00100000; 632 break; 633 case POWERPC_EXCP_INVAL: 634 trace_ppc_excp_inval(env->nip); 635 msr |= 0x00080000; 636 break; 637 case POWERPC_EXCP_PRIV: 638 msr |= 0x00040000; 639 break; 640 case POWERPC_EXCP_TRAP: 641 msr |= 0x00020000; 642 break; 643 default: 644 /* Should never occur */ 645 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 646 env->error_code); 647 break; 648 } 649 break; 650 case POWERPC_EXCP_SYSCALL: /* System call exception */ 651 dump_syscall(env); 652 653 /* 654 * We need to correct the NIP which in this case is supposed 655 * to point to the next instruction 656 */ 657 env->nip += 4; 658 break; 659 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 660 case POWERPC_EXCP_DECR: /* Decrementer exception */ 661 break; 662 case POWERPC_EXCP_DTLB: /* Data TLB error */ 663 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 664 break; 665 case POWERPC_EXCP_RESET: /* System reset exception */ 666 if (FIELD_EX64(env->msr, MSR, POW)) { 667 cpu_abort(cs, "Trying to deliver power-saving system reset " 668 "exception %d with no HV support\n", excp); 669 } 670 break; 671 case POWERPC_EXCP_TRACE: /* Trace exception */ 672 break; 673 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 674 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 675 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 676 /* Swap temporary saved registers with GPRs */ 677 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { 678 new_msr |= (target_ulong)1 << MSR_TGPR; 679 hreg_swap_gpr_tgpr(env); 680 } 681 682 ppc_excp_debug_sw_tlb(env, excp); 683 684 msr |= env->crf[0] << 28; 685 msr |= env->error_code; /* key, D/I, S/L bits */ 686 /* Set way using a LRU mechanism */ 687 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; 688 break; 689 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 690 case POWERPC_EXCP_DABR: /* Data address breakpoint */ 691 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 692 case POWERPC_EXCP_SMI: /* System management interrupt */ 693 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ 694 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ 695 cpu_abort(cs, "%s exception not implemented\n", 696 powerpc_excp_name(excp)); 697 break; 698 default: 699 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 700 break; 701 } 702 703 /* 704 * Sort out endianness of interrupt, this differs depending on the 705 * CPU, the HV mode, etc... 706 */ 707 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { 708 new_msr |= (target_ulong)1 << MSR_LE; 709 } 710 711 /* Save PC */ 712 env->spr[SPR_SRR0] = env->nip; 713 714 /* Save MSR */ 715 env->spr[SPR_SRR1] = msr; 716 717 powerpc_set_excp_state(cpu, vector, new_msr); 718 } 719 720 static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) 721 { 722 CPUState *cs = CPU(cpu); 723 CPUPPCState *env = &cpu->env; 724 target_ulong msr, new_msr, vector; 725 726 /* new srr1 value excluding must-be-zero bits */ 727 msr = env->msr & ~0x783f0000ULL; 728 729 /* 730 * new interrupt handler msr preserves existing ME unless 731 * explicitly overriden 732 */ 733 new_msr = env->msr & ((target_ulong)1 << MSR_ME); 734 735 /* 736 * Hypervisor emulation assistance interrupt only exists on server 737 * arch 2.05 server or later. 738 */ 739 if (excp == POWERPC_EXCP_HV_EMU) { 740 excp = POWERPC_EXCP_PROGRAM; 741 } 742 743 vector = env->excp_vectors[excp]; 744 if (vector == (target_ulong)-1ULL) { 745 cpu_abort(cs, "Raised an exception without defined vector %d\n", 746 excp); 747 } 748 749 vector |= env->excp_prefix; 750 751 switch (excp) { 752 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 753 if (!FIELD_EX64(env->msr, MSR, ME)) { 754 /* 755 * Machine check exception is not enabled. Enter 756 * checkstop state. 757 */ 758 fprintf(stderr, "Machine check while not allowed. " 759 "Entering checkstop state\n"); 760 if (qemu_log_separate()) { 761 qemu_log("Machine check while not allowed. " 762 "Entering checkstop state\n"); 763 } 764 cs->halted = 1; 765 cpu_interrupt_exittb(cs); 766 } 767 768 /* machine check exceptions don't have ME set */ 769 new_msr &= ~((target_ulong)1 << MSR_ME); 770 771 break; 772 case POWERPC_EXCP_DSI: /* Data storage exception */ 773 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); 774 break; 775 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 776 trace_ppc_excp_isi(msr, env->nip); 777 msr |= env->error_code; 778 break; 779 case POWERPC_EXCP_EXTERNAL: /* External input */ 780 break; 781 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 782 /* Get rS/rD and rA from faulting opcode */ 783 /* 784 * Note: the opcode fields will not be set properly for a 785 * direct store load/store, but nobody cares as nobody 786 * actually uses direct store segments. 787 */ 788 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 789 break; 790 case POWERPC_EXCP_PROGRAM: /* Program exception */ 791 switch (env->error_code & ~0xF) { 792 case POWERPC_EXCP_FP: 793 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 794 trace_ppc_excp_fp_ignore(); 795 powerpc_reset_excp_state(cpu); 796 return; 797 } 798 799 /* 800 * FP exceptions always have NIP pointing to the faulting 801 * instruction, so always use store_next and claim we are 802 * precise in the MSR. 803 */ 804 msr |= 0x00100000; 805 break; 806 case POWERPC_EXCP_INVAL: 807 trace_ppc_excp_inval(env->nip); 808 msr |= 0x00080000; 809 break; 810 case POWERPC_EXCP_PRIV: 811 msr |= 0x00040000; 812 break; 813 case POWERPC_EXCP_TRAP: 814 msr |= 0x00020000; 815 break; 816 default: 817 /* Should never occur */ 818 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 819 env->error_code); 820 break; 821 } 822 break; 823 case POWERPC_EXCP_SYSCALL: /* System call exception */ 824 { 825 int lev = env->error_code; 826 827 if (lev == 1 && cpu->vhyp) { 828 dump_hcall(env); 829 } else { 830 dump_syscall(env); 831 } 832 833 /* 834 * We need to correct the NIP which in this case is supposed 835 * to point to the next instruction 836 */ 837 env->nip += 4; 838 839 /* 840 * The Virtual Open Firmware (VOF) relies on the 'sc 1' 841 * instruction to communicate with QEMU. The pegasos2 machine 842 * uses VOF and the 7xx CPUs, so although the 7xx don't have 843 * HV mode, we need to keep hypercall support. 844 */ 845 if (lev == 1 && cpu->vhyp) { 846 PPCVirtualHypervisorClass *vhc = 847 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 848 vhc->hypercall(cpu->vhyp, cpu); 849 return; 850 } 851 852 break; 853 } 854 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 855 case POWERPC_EXCP_DECR: /* Decrementer exception */ 856 break; 857 case POWERPC_EXCP_RESET: /* System reset exception */ 858 if (FIELD_EX64(env->msr, MSR, POW)) { 859 cpu_abort(cs, "Trying to deliver power-saving system reset " 860 "exception %d with no HV support\n", excp); 861 } 862 break; 863 case POWERPC_EXCP_TRACE: /* Trace exception */ 864 break; 865 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 866 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 867 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 868 ppc_excp_debug_sw_tlb(env, excp); 869 870 msr |= env->crf[0] << 28; 871 msr |= env->error_code; /* key, D/I, S/L bits */ 872 /* Set way using a LRU mechanism */ 873 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; 874 875 break; 876 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 877 case POWERPC_EXCP_SMI: /* System management interrupt */ 878 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 879 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ 880 cpu_abort(cs, "%s exception not implemented\n", 881 powerpc_excp_name(excp)); 882 break; 883 default: 884 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 885 break; 886 } 887 888 /* 889 * Sort out endianness of interrupt, this differs depending on the 890 * CPU, the HV mode, etc... 891 */ 892 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { 893 new_msr |= (target_ulong)1 << MSR_LE; 894 } 895 896 /* Save PC */ 897 env->spr[SPR_SRR0] = env->nip; 898 899 /* Save MSR */ 900 env->spr[SPR_SRR1] = msr; 901 902 powerpc_set_excp_state(cpu, vector, new_msr); 903 } 904 905 static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) 906 { 907 CPUState *cs = CPU(cpu); 908 CPUPPCState *env = &cpu->env; 909 target_ulong msr, new_msr, vector; 910 911 /* new srr1 value excluding must-be-zero bits */ 912 msr = env->msr & ~0x783f0000ULL; 913 914 /* 915 * new interrupt handler msr preserves existing ME unless 916 * explicitly overriden 917 */ 918 new_msr = env->msr & ((target_ulong)1 << MSR_ME); 919 920 /* 921 * Hypervisor emulation assistance interrupt only exists on server 922 * arch 2.05 server or later. 923 */ 924 if (excp == POWERPC_EXCP_HV_EMU) { 925 excp = POWERPC_EXCP_PROGRAM; 926 } 927 928 vector = env->excp_vectors[excp]; 929 if (vector == (target_ulong)-1ULL) { 930 cpu_abort(cs, "Raised an exception without defined vector %d\n", 931 excp); 932 } 933 934 vector |= env->excp_prefix; 935 936 switch (excp) { 937 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 938 if (!FIELD_EX64(env->msr, MSR, ME)) { 939 /* 940 * Machine check exception is not enabled. Enter 941 * checkstop state. 942 */ 943 fprintf(stderr, "Machine check while not allowed. " 944 "Entering checkstop state\n"); 945 if (qemu_log_separate()) { 946 qemu_log("Machine check while not allowed. " 947 "Entering checkstop state\n"); 948 } 949 cs->halted = 1; 950 cpu_interrupt_exittb(cs); 951 } 952 953 /* machine check exceptions don't have ME set */ 954 new_msr &= ~((target_ulong)1 << MSR_ME); 955 956 break; 957 case POWERPC_EXCP_DSI: /* Data storage exception */ 958 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); 959 break; 960 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 961 trace_ppc_excp_isi(msr, env->nip); 962 msr |= env->error_code; 963 break; 964 case POWERPC_EXCP_EXTERNAL: /* External input */ 965 break; 966 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 967 /* Get rS/rD and rA from faulting opcode */ 968 /* 969 * Note: the opcode fields will not be set properly for a 970 * direct store load/store, but nobody cares as nobody 971 * actually uses direct store segments. 972 */ 973 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 974 break; 975 case POWERPC_EXCP_PROGRAM: /* Program exception */ 976 switch (env->error_code & ~0xF) { 977 case POWERPC_EXCP_FP: 978 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 979 trace_ppc_excp_fp_ignore(); 980 powerpc_reset_excp_state(cpu); 981 return; 982 } 983 984 /* 985 * FP exceptions always have NIP pointing to the faulting 986 * instruction, so always use store_next and claim we are 987 * precise in the MSR. 988 */ 989 msr |= 0x00100000; 990 break; 991 case POWERPC_EXCP_INVAL: 992 trace_ppc_excp_inval(env->nip); 993 msr |= 0x00080000; 994 break; 995 case POWERPC_EXCP_PRIV: 996 msr |= 0x00040000; 997 break; 998 case POWERPC_EXCP_TRAP: 999 msr |= 0x00020000; 1000 break; 1001 default: 1002 /* Should never occur */ 1003 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 1004 env->error_code); 1005 break; 1006 } 1007 break; 1008 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1009 { 1010 int lev = env->error_code; 1011 1012 if ((lev == 1) && cpu->vhyp) { 1013 dump_hcall(env); 1014 } else { 1015 dump_syscall(env); 1016 } 1017 1018 /* 1019 * We need to correct the NIP which in this case is supposed 1020 * to point to the next instruction 1021 */ 1022 env->nip += 4; 1023 1024 /* 1025 * The Virtual Open Firmware (VOF) relies on the 'sc 1' 1026 * instruction to communicate with QEMU. The pegasos2 machine 1027 * uses VOF and the 74xx CPUs, so although the 74xx don't have 1028 * HV mode, we need to keep hypercall support. 1029 */ 1030 if ((lev == 1) && cpu->vhyp) { 1031 PPCVirtualHypervisorClass *vhc = 1032 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 1033 vhc->hypercall(cpu->vhyp, cpu); 1034 return; 1035 } 1036 1037 break; 1038 } 1039 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1040 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1041 break; 1042 case POWERPC_EXCP_RESET: /* System reset exception */ 1043 if (FIELD_EX64(env->msr, MSR, POW)) { 1044 cpu_abort(cs, "Trying to deliver power-saving system reset " 1045 "exception %d with no HV support\n", excp); 1046 } 1047 break; 1048 case POWERPC_EXCP_TRACE: /* Trace exception */ 1049 break; 1050 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1051 break; 1052 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1053 case POWERPC_EXCP_SMI: /* System management interrupt */ 1054 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1055 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ 1056 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1057 cpu_abort(cs, "%s exception not implemented\n", 1058 powerpc_excp_name(excp)); 1059 break; 1060 default: 1061 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 1062 break; 1063 } 1064 1065 /* 1066 * Sort out endianness of interrupt, this differs depending on the 1067 * CPU, the HV mode, etc... 1068 */ 1069 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { 1070 new_msr |= (target_ulong)1 << MSR_LE; 1071 } 1072 1073 /* Save PC */ 1074 env->spr[SPR_SRR0] = env->nip; 1075 1076 /* Save MSR */ 1077 env->spr[SPR_SRR1] = msr; 1078 1079 powerpc_set_excp_state(cpu, vector, new_msr); 1080 } 1081 1082 static void powerpc_excp_booke(PowerPCCPU *cpu, int excp) 1083 { 1084 CPUState *cs = CPU(cpu); 1085 CPUPPCState *env = &cpu->env; 1086 target_ulong msr, new_msr, vector; 1087 int srr0, srr1; 1088 1089 msr = env->msr; 1090 1091 /* 1092 * new interrupt handler msr preserves existing ME unless 1093 * explicitly overriden 1094 */ 1095 new_msr = env->msr & ((target_ulong)1 << MSR_ME); 1096 1097 /* target registers */ 1098 srr0 = SPR_SRR0; 1099 srr1 = SPR_SRR1; 1100 1101 /* 1102 * Hypervisor emulation assistance interrupt only exists on server 1103 * arch 2.05 server or later. 1104 */ 1105 if (excp == POWERPC_EXCP_HV_EMU) { 1106 excp = POWERPC_EXCP_PROGRAM; 1107 } 1108 1109 #ifdef TARGET_PPC64 1110 /* 1111 * SPEU and VPU share the same IVOR but they exist in different 1112 * processors. SPEU is e500v1/2 only and VPU is e6500 only. 1113 */ 1114 if (excp == POWERPC_EXCP_VPU) { 1115 excp = POWERPC_EXCP_SPEU; 1116 } 1117 #endif 1118 1119 vector = env->excp_vectors[excp]; 1120 if (vector == (target_ulong)-1ULL) { 1121 cpu_abort(cs, "Raised an exception without defined vector %d\n", 1122 excp); 1123 } 1124 1125 vector |= env->excp_prefix; 1126 1127 switch (excp) { 1128 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1129 srr0 = SPR_BOOKE_CSRR0; 1130 srr1 = SPR_BOOKE_CSRR1; 1131 break; 1132 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1133 if (!FIELD_EX64(env->msr, MSR, ME)) { 1134 /* 1135 * Machine check exception is not enabled. Enter 1136 * checkstop state. 1137 */ 1138 fprintf(stderr, "Machine check while not allowed. " 1139 "Entering checkstop state\n"); 1140 if (qemu_log_separate()) { 1141 qemu_log("Machine check while not allowed. " 1142 "Entering checkstop state\n"); 1143 } 1144 cs->halted = 1; 1145 cpu_interrupt_exittb(cs); 1146 } 1147 1148 /* machine check exceptions don't have ME set */ 1149 new_msr &= ~((target_ulong)1 << MSR_ME); 1150 1151 /* FIXME: choose one or the other based on CPU type */ 1152 srr0 = SPR_BOOKE_MCSRR0; 1153 srr1 = SPR_BOOKE_MCSRR1; 1154 1155 env->spr[SPR_BOOKE_CSRR0] = env->nip; 1156 env->spr[SPR_BOOKE_CSRR1] = msr; 1157 1158 break; 1159 case POWERPC_EXCP_DSI: /* Data storage exception */ 1160 trace_ppc_excp_dsi(env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 1161 break; 1162 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1163 trace_ppc_excp_isi(msr, env->nip); 1164 break; 1165 case POWERPC_EXCP_EXTERNAL: /* External input */ 1166 if (env->mpic_proxy) { 1167 /* IACK the IRQ on delivery */ 1168 env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); 1169 } 1170 break; 1171 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1172 break; 1173 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1174 switch (env->error_code & ~0xF) { 1175 case POWERPC_EXCP_FP: 1176 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 1177 trace_ppc_excp_fp_ignore(); 1178 powerpc_reset_excp_state(cpu); 1179 return; 1180 } 1181 1182 /* 1183 * FP exceptions always have NIP pointing to the faulting 1184 * instruction, so always use store_next and claim we are 1185 * precise in the MSR. 1186 */ 1187 msr |= 0x00100000; 1188 env->spr[SPR_BOOKE_ESR] = ESR_FP; 1189 break; 1190 case POWERPC_EXCP_INVAL: 1191 trace_ppc_excp_inval(env->nip); 1192 msr |= 0x00080000; 1193 env->spr[SPR_BOOKE_ESR] = ESR_PIL; 1194 break; 1195 case POWERPC_EXCP_PRIV: 1196 msr |= 0x00040000; 1197 env->spr[SPR_BOOKE_ESR] = ESR_PPR; 1198 break; 1199 case POWERPC_EXCP_TRAP: 1200 msr |= 0x00020000; 1201 env->spr[SPR_BOOKE_ESR] = ESR_PTR; 1202 break; 1203 default: 1204 /* Should never occur */ 1205 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 1206 env->error_code); 1207 break; 1208 } 1209 break; 1210 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1211 dump_syscall(env); 1212 1213 /* 1214 * We need to correct the NIP which in this case is supposed 1215 * to point to the next instruction 1216 */ 1217 env->nip += 4; 1218 break; 1219 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1220 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1221 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1222 break; 1223 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1224 /* FIT on 4xx */ 1225 trace_ppc_excp_print("FIT"); 1226 break; 1227 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1228 trace_ppc_excp_print("WDT"); 1229 srr0 = SPR_BOOKE_CSRR0; 1230 srr1 = SPR_BOOKE_CSRR1; 1231 break; 1232 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1233 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1234 break; 1235 case POWERPC_EXCP_DEBUG: /* Debug interrupt */ 1236 if (env->flags & POWERPC_FLAG_DE) { 1237 /* FIXME: choose one or the other based on CPU type */ 1238 srr0 = SPR_BOOKE_DSRR0; 1239 srr1 = SPR_BOOKE_DSRR1; 1240 1241 env->spr[SPR_BOOKE_CSRR0] = env->nip; 1242 env->spr[SPR_BOOKE_CSRR1] = msr; 1243 1244 /* DBSR already modified by caller */ 1245 } else { 1246 cpu_abort(cs, "Debug exception triggered on unsupported model\n"); 1247 } 1248 break; 1249 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */ 1250 env->spr[SPR_BOOKE_ESR] = ESR_SPV; 1251 break; 1252 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1253 break; 1254 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1255 srr0 = SPR_BOOKE_CSRR0; 1256 srr1 = SPR_BOOKE_CSRR1; 1257 break; 1258 case POWERPC_EXCP_RESET: /* System reset exception */ 1259 if (FIELD_EX64(env->msr, MSR, POW)) { 1260 cpu_abort(cs, "Trying to deliver power-saving system reset " 1261 "exception %d with no HV support\n", excp); 1262 } 1263 break; 1264 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ 1265 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ 1266 cpu_abort(cs, "%s exception not implemented\n", 1267 powerpc_excp_name(excp)); 1268 break; 1269 default: 1270 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 1271 break; 1272 } 1273 1274 #if defined(TARGET_PPC64) 1275 if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { 1276 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ 1277 new_msr |= (target_ulong)1 << MSR_CM; 1278 } else { 1279 vector = (uint32_t)vector; 1280 } 1281 #endif 1282 1283 /* Save PC */ 1284 env->spr[srr0] = env->nip; 1285 1286 /* Save MSR */ 1287 env->spr[srr1] = msr; 1288 1289 powerpc_set_excp_state(cpu, vector, new_msr); 1290 } 1291 1292 /* 1293 * When running a nested HV guest under vhyp, external interrupts are 1294 * delivered as HVIRT. 1295 */ 1296 static bool books_vhyp_promotes_external_to_hvirt(PowerPCCPU *cpu) 1297 { 1298 if (cpu->vhyp) { 1299 return vhyp_cpu_in_nested(cpu); 1300 } 1301 return false; 1302 } 1303 1304 #ifdef TARGET_PPC64 1305 /* 1306 * When running under vhyp, hcalls are always intercepted and sent to the 1307 * vhc->hypercall handler. 1308 */ 1309 static bool books_vhyp_handles_hcall(PowerPCCPU *cpu) 1310 { 1311 if (cpu->vhyp) { 1312 return !vhyp_cpu_in_nested(cpu); 1313 } 1314 return false; 1315 } 1316 1317 /* 1318 * When running a nested KVM HV guest under vhyp, HV exceptions are not 1319 * delivered to the guest (because there is no concept of HV support), but 1320 * rather they are sent tothe vhyp to exit from the L2 back to the L1 and 1321 * return from the H_ENTER_NESTED hypercall. 1322 */ 1323 static bool books_vhyp_handles_hv_excp(PowerPCCPU *cpu) 1324 { 1325 if (cpu->vhyp) { 1326 return vhyp_cpu_in_nested(cpu); 1327 } 1328 return false; 1329 } 1330 1331 static void powerpc_excp_books(PowerPCCPU *cpu, int excp) 1332 { 1333 CPUState *cs = CPU(cpu); 1334 CPUPPCState *env = &cpu->env; 1335 target_ulong msr, new_msr, vector; 1336 int srr0, srr1, lev = -1; 1337 1338 /* new srr1 value excluding must-be-zero bits */ 1339 msr = env->msr & ~0x783f0000ULL; 1340 1341 /* 1342 * new interrupt handler msr preserves existing HV and ME unless 1343 * explicitly overriden 1344 */ 1345 new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); 1346 1347 /* target registers */ 1348 srr0 = SPR_SRR0; 1349 srr1 = SPR_SRR1; 1350 1351 /* 1352 * check for special resume at 0x100 from doze/nap/sleep/winkle on 1353 * P7/P8/P9 1354 */ 1355 if (env->resume_as_sreset) { 1356 excp = powerpc_reset_wakeup(cs, env, excp, &msr); 1357 } 1358 1359 /* 1360 * We don't want to generate a Hypervisor Emulation Assistance 1361 * Interrupt if we don't have HVB in msr_mask (PAPR mode), 1362 * unless running a nested-hv guest, in which case the L1 1363 * kernel wants the interrupt. 1364 */ 1365 if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB) && 1366 !books_vhyp_handles_hv_excp(cpu)) { 1367 excp = POWERPC_EXCP_PROGRAM; 1368 } 1369 1370 vector = env->excp_vectors[excp]; 1371 if (vector == (target_ulong)-1ULL) { 1372 cpu_abort(cs, "Raised an exception without defined vector %d\n", 1373 excp); 1374 } 1375 1376 vector |= env->excp_prefix; 1377 1378 switch (excp) { 1379 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1380 if (!FIELD_EX64(env->msr, MSR, ME)) { 1381 /* 1382 * Machine check exception is not enabled. Enter 1383 * checkstop state. 1384 */ 1385 fprintf(stderr, "Machine check while not allowed. " 1386 "Entering checkstop state\n"); 1387 if (qemu_log_separate()) { 1388 qemu_log("Machine check while not allowed. " 1389 "Entering checkstop state\n"); 1390 } 1391 cs->halted = 1; 1392 cpu_interrupt_exittb(cs); 1393 } 1394 if (env->msr_mask & MSR_HVB) { 1395 /* 1396 * ISA specifies HV, but can be delivered to guest with HV 1397 * clear (e.g., see FWNMI in PAPR). 1398 */ 1399 new_msr |= (target_ulong)MSR_HVB; 1400 } 1401 1402 /* machine check exceptions don't have ME set */ 1403 new_msr &= ~((target_ulong)1 << MSR_ME); 1404 1405 break; 1406 case POWERPC_EXCP_DSI: /* Data storage exception */ 1407 trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); 1408 break; 1409 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1410 trace_ppc_excp_isi(msr, env->nip); 1411 msr |= env->error_code; 1412 break; 1413 case POWERPC_EXCP_EXTERNAL: /* External input */ 1414 { 1415 bool lpes0; 1416 1417 /* 1418 * LPES0 is only taken into consideration if we support HV 1419 * mode for this CPU. 1420 */ 1421 if (!env->has_hv_mode) { 1422 break; 1423 } 1424 1425 lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 1426 1427 if (!lpes0) { 1428 new_msr |= (target_ulong)MSR_HVB; 1429 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 1430 srr0 = SPR_HSRR0; 1431 srr1 = SPR_HSRR1; 1432 } 1433 1434 break; 1435 } 1436 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1437 /* Optional DSISR update was removed from ISA v3.0 */ 1438 if (!(env->insns_flags2 & PPC2_ISA300)) { 1439 /* Get rS/rD and rA from faulting opcode */ 1440 /* 1441 * Note: the opcode fields will not be set properly for a 1442 * direct store load/store, but nobody cares as nobody 1443 * actually uses direct store segments. 1444 */ 1445 env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; 1446 } 1447 break; 1448 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1449 switch (env->error_code & ~0xF) { 1450 case POWERPC_EXCP_FP: 1451 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { 1452 trace_ppc_excp_fp_ignore(); 1453 powerpc_reset_excp_state(cpu); 1454 return; 1455 } 1456 1457 /* 1458 * FP exceptions always have NIP pointing to the faulting 1459 * instruction, so always use store_next and claim we are 1460 * precise in the MSR. 1461 */ 1462 msr |= 0x00100000; 1463 break; 1464 case POWERPC_EXCP_INVAL: 1465 trace_ppc_excp_inval(env->nip); 1466 msr |= 0x00080000; 1467 break; 1468 case POWERPC_EXCP_PRIV: 1469 msr |= 0x00040000; 1470 break; 1471 case POWERPC_EXCP_TRAP: 1472 msr |= 0x00020000; 1473 break; 1474 default: 1475 /* Should never occur */ 1476 cpu_abort(cs, "Invalid program exception %d. Aborting\n", 1477 env->error_code); 1478 break; 1479 } 1480 break; 1481 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1482 lev = env->error_code; 1483 1484 if ((lev == 1) && cpu->vhyp) { 1485 dump_hcall(env); 1486 } else { 1487 dump_syscall(env); 1488 } 1489 1490 /* 1491 * We need to correct the NIP which in this case is supposed 1492 * to point to the next instruction 1493 */ 1494 env->nip += 4; 1495 1496 /* "PAPR mode" built-in hypercall emulation */ 1497 if ((lev == 1) && books_vhyp_handles_hcall(cpu)) { 1498 PPCVirtualHypervisorClass *vhc = 1499 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 1500 vhc->hypercall(cpu->vhyp, cpu); 1501 return; 1502 } 1503 if (lev == 1) { 1504 new_msr |= (target_ulong)MSR_HVB; 1505 } 1506 break; 1507 case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */ 1508 lev = env->error_code; 1509 dump_syscall(env); 1510 env->nip += 4; 1511 new_msr |= env->msr & ((target_ulong)1 << MSR_EE); 1512 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 1513 1514 vector += lev * 0x20; 1515 1516 env->lr = env->nip; 1517 env->ctr = msr; 1518 break; 1519 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1520 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1521 break; 1522 case POWERPC_EXCP_RESET: /* System reset exception */ 1523 /* A power-saving exception sets ME, otherwise it is unchanged */ 1524 if (FIELD_EX64(env->msr, MSR, POW)) { 1525 /* indicate that we resumed from power save mode */ 1526 msr |= 0x10000; 1527 new_msr |= ((target_ulong)1 << MSR_ME); 1528 } 1529 if (env->msr_mask & MSR_HVB) { 1530 /* 1531 * ISA specifies HV, but can be delivered to guest with HV 1532 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). 1533 */ 1534 new_msr |= (target_ulong)MSR_HVB; 1535 } else { 1536 if (FIELD_EX64(env->msr, MSR, POW)) { 1537 cpu_abort(cs, "Trying to deliver power-saving system reset " 1538 "exception %d with no HV support\n", excp); 1539 } 1540 } 1541 break; 1542 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1543 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1544 case POWERPC_EXCP_TRACE: /* Trace exception */ 1545 break; 1546 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ 1547 msr |= env->error_code; 1548 /* fall through */ 1549 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1550 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1551 case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ 1552 case POWERPC_EXCP_HV_EMU: 1553 case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ 1554 srr0 = SPR_HSRR0; 1555 srr1 = SPR_HSRR1; 1556 new_msr |= (target_ulong)MSR_HVB; 1557 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 1558 break; 1559 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1560 case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ 1561 case POWERPC_EXCP_FU: /* Facility unavailable exception */ 1562 env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); 1563 break; 1564 case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */ 1565 env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS); 1566 srr0 = SPR_HSRR0; 1567 srr1 = SPR_HSRR1; 1568 new_msr |= (target_ulong)MSR_HVB; 1569 new_msr |= env->msr & ((target_ulong)1 << MSR_RI); 1570 break; 1571 case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */ 1572 case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */ 1573 env->spr[SPR_BESCR] &= ~BESCR_GE; 1574 1575 /* 1576 * Save NIP for rfebb insn in SPR_EBBRR. Next nip is 1577 * stored in the EBB Handler SPR_EBBHR. 1578 */ 1579 env->spr[SPR_EBBRR] = env->nip; 1580 powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr); 1581 1582 /* 1583 * This exception is handled in userspace. No need to proceed. 1584 */ 1585 return; 1586 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1587 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ 1588 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1589 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1590 case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */ 1591 case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */ 1592 cpu_abort(cs, "%s exception not implemented\n", 1593 powerpc_excp_name(excp)); 1594 break; 1595 default: 1596 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 1597 break; 1598 } 1599 1600 /* 1601 * Sort out endianness of interrupt, this differs depending on the 1602 * CPU, the HV mode, etc... 1603 */ 1604 if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { 1605 new_msr |= (target_ulong)1 << MSR_LE; 1606 } 1607 1608 new_msr |= (target_ulong)1 << MSR_SF; 1609 1610 if (excp != POWERPC_EXCP_SYSCALL_VECTORED) { 1611 /* Save PC */ 1612 env->spr[srr0] = env->nip; 1613 1614 /* Save MSR */ 1615 env->spr[srr1] = msr; 1616 } 1617 1618 if ((new_msr & MSR_HVB) && books_vhyp_handles_hv_excp(cpu)) { 1619 PPCVirtualHypervisorClass *vhc = 1620 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 1621 /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */ 1622 vhc->deliver_hv_excp(cpu, excp); 1623 1624 powerpc_reset_excp_state(cpu); 1625 1626 } else { 1627 /* Sanity check */ 1628 if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) { 1629 cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " 1630 "no HV support\n", excp); 1631 } 1632 1633 /* This can update new_msr and vector if AIL applies */ 1634 ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector); 1635 1636 powerpc_set_excp_state(cpu, vector, new_msr); 1637 } 1638 } 1639 #else 1640 static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp) 1641 { 1642 g_assert_not_reached(); 1643 } 1644 #endif 1645 1646 static void powerpc_excp(PowerPCCPU *cpu, int excp) 1647 { 1648 CPUState *cs = CPU(cpu); 1649 CPUPPCState *env = &cpu->env; 1650 1651 if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) { 1652 cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); 1653 } 1654 1655 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx 1656 " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp), 1657 excp, env->error_code); 1658 1659 switch (env->excp_model) { 1660 case POWERPC_EXCP_40x: 1661 powerpc_excp_40x(cpu, excp); 1662 break; 1663 case POWERPC_EXCP_6xx: 1664 powerpc_excp_6xx(cpu, excp); 1665 break; 1666 case POWERPC_EXCP_7xx: 1667 powerpc_excp_7xx(cpu, excp); 1668 break; 1669 case POWERPC_EXCP_74xx: 1670 powerpc_excp_74xx(cpu, excp); 1671 break; 1672 case POWERPC_EXCP_BOOKE: 1673 powerpc_excp_booke(cpu, excp); 1674 break; 1675 case POWERPC_EXCP_970: 1676 case POWERPC_EXCP_POWER7: 1677 case POWERPC_EXCP_POWER8: 1678 case POWERPC_EXCP_POWER9: 1679 case POWERPC_EXCP_POWER10: 1680 powerpc_excp_books(cpu, excp); 1681 break; 1682 default: 1683 g_assert_not_reached(); 1684 } 1685 } 1686 1687 void ppc_cpu_do_interrupt(CPUState *cs) 1688 { 1689 PowerPCCPU *cpu = POWERPC_CPU(cs); 1690 1691 powerpc_excp(cpu, cs->exception_index); 1692 } 1693 1694 #if defined(TARGET_PPC64) 1695 #define P7_UNUSED_INTERRUPTS \ 1696 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \ 1697 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \ 1698 PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \ 1699 PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB) 1700 1701 static int p7_interrupt_powersave(CPUPPCState *env) 1702 { 1703 if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && 1704 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 1705 return PPC_INTERRUPT_EXT; 1706 } 1707 if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && 1708 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 1709 return PPC_INTERRUPT_DECR; 1710 } 1711 if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && 1712 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 1713 return PPC_INTERRUPT_MCK; 1714 } 1715 if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && 1716 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 1717 return PPC_INTERRUPT_HMI; 1718 } 1719 if (env->pending_interrupts & PPC_INTERRUPT_RESET) { 1720 return PPC_INTERRUPT_RESET; 1721 } 1722 return 0; 1723 } 1724 1725 static int p7_next_unmasked_interrupt(CPUPPCState *env) 1726 { 1727 PowerPCCPU *cpu = env_archcpu(env); 1728 CPUState *cs = CPU(cpu); 1729 /* Ignore MSR[EE] when coming out of some power management states */ 1730 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; 1731 1732 assert((env->pending_interrupts & P7_UNUSED_INTERRUPTS) == 0); 1733 1734 if (cs->halted) { 1735 /* LPCR[PECE] controls which interrupts can exit power-saving mode */ 1736 return p7_interrupt_powersave(env); 1737 } 1738 1739 /* Machine check exception */ 1740 if (env->pending_interrupts & PPC_INTERRUPT_MCK) { 1741 return PPC_INTERRUPT_MCK; 1742 } 1743 1744 /* Hypervisor decrementer exception */ 1745 if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { 1746 /* LPCR will be clear when not supported so this will work */ 1747 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 1748 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { 1749 /* HDEC clears on delivery */ 1750 return PPC_INTERRUPT_HDECR; 1751 } 1752 } 1753 1754 /* External interrupt can ignore MSR:EE under some circumstances */ 1755 if (env->pending_interrupts & PPC_INTERRUPT_EXT) { 1756 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 1757 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 1758 /* HEIC blocks delivery to the hypervisor */ 1759 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && 1760 !FIELD_EX64(env->msr, MSR, PR))) || 1761 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { 1762 return PPC_INTERRUPT_EXT; 1763 } 1764 } 1765 if (msr_ee != 0) { 1766 /* Decrementer exception */ 1767 if (env->pending_interrupts & PPC_INTERRUPT_DECR) { 1768 return PPC_INTERRUPT_DECR; 1769 } 1770 if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { 1771 return PPC_INTERRUPT_PERFM; 1772 } 1773 } 1774 1775 return 0; 1776 } 1777 1778 #define P8_UNUSED_INTERRUPTS \ 1779 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_HVIRT | \ 1780 PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \ 1781 PPC_INTERRUPT_FIT | PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM) 1782 1783 static int p8_interrupt_powersave(CPUPPCState *env) 1784 { 1785 if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && 1786 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 1787 return PPC_INTERRUPT_EXT; 1788 } 1789 if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && 1790 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 1791 return PPC_INTERRUPT_DECR; 1792 } 1793 if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && 1794 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 1795 return PPC_INTERRUPT_MCK; 1796 } 1797 if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && 1798 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 1799 return PPC_INTERRUPT_HMI; 1800 } 1801 if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && 1802 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 1803 return PPC_INTERRUPT_DOORBELL; 1804 } 1805 if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && 1806 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 1807 return PPC_INTERRUPT_HDOORBELL; 1808 } 1809 if (env->pending_interrupts & PPC_INTERRUPT_RESET) { 1810 return PPC_INTERRUPT_RESET; 1811 } 1812 return 0; 1813 } 1814 1815 static int p8_next_unmasked_interrupt(CPUPPCState *env) 1816 { 1817 PowerPCCPU *cpu = env_archcpu(env); 1818 CPUState *cs = CPU(cpu); 1819 /* Ignore MSR[EE] when coming out of some power management states */ 1820 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; 1821 1822 assert((env->pending_interrupts & P8_UNUSED_INTERRUPTS) == 0); 1823 1824 if (cs->halted) { 1825 /* LPCR[PECE] controls which interrupts can exit power-saving mode */ 1826 return p8_interrupt_powersave(env); 1827 } 1828 1829 /* Machine check exception */ 1830 if (env->pending_interrupts & PPC_INTERRUPT_MCK) { 1831 return PPC_INTERRUPT_MCK; 1832 } 1833 1834 /* Hypervisor decrementer exception */ 1835 if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { 1836 /* LPCR will be clear when not supported so this will work */ 1837 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 1838 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { 1839 /* HDEC clears on delivery */ 1840 return PPC_INTERRUPT_HDECR; 1841 } 1842 } 1843 1844 /* External interrupt can ignore MSR:EE under some circumstances */ 1845 if (env->pending_interrupts & PPC_INTERRUPT_EXT) { 1846 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 1847 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 1848 /* HEIC blocks delivery to the hypervisor */ 1849 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && 1850 !FIELD_EX64(env->msr, MSR, PR))) || 1851 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { 1852 return PPC_INTERRUPT_EXT; 1853 } 1854 } 1855 if (msr_ee != 0) { 1856 /* Decrementer exception */ 1857 if (env->pending_interrupts & PPC_INTERRUPT_DECR) { 1858 return PPC_INTERRUPT_DECR; 1859 } 1860 if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { 1861 return PPC_INTERRUPT_DOORBELL; 1862 } 1863 if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { 1864 return PPC_INTERRUPT_HDOORBELL; 1865 } 1866 if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { 1867 return PPC_INTERRUPT_PERFM; 1868 } 1869 /* EBB exception */ 1870 if (env->pending_interrupts & PPC_INTERRUPT_EBB) { 1871 /* 1872 * EBB exception must be taken in problem state and 1873 * with BESCR_GE set. 1874 */ 1875 if (FIELD_EX64(env->msr, MSR, PR) && 1876 (env->spr[SPR_BESCR] & BESCR_GE)) { 1877 return PPC_INTERRUPT_EBB; 1878 } 1879 } 1880 } 1881 1882 return 0; 1883 } 1884 1885 #define P9_UNUSED_INTERRUPTS \ 1886 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_CEXT | \ 1887 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \ 1888 PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM) 1889 1890 static int p9_interrupt_powersave(CPUPPCState *env) 1891 { 1892 /* External Exception */ 1893 if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && 1894 (env->spr[SPR_LPCR] & LPCR_EEE)) { 1895 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 1896 if (!heic || !FIELD_EX64_HV(env->msr) || 1897 FIELD_EX64(env->msr, MSR, PR)) { 1898 return PPC_INTERRUPT_EXT; 1899 } 1900 } 1901 /* Decrementer Exception */ 1902 if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && 1903 (env->spr[SPR_LPCR] & LPCR_DEE)) { 1904 return PPC_INTERRUPT_DECR; 1905 } 1906 /* Machine Check or Hypervisor Maintenance Exception */ 1907 if (env->spr[SPR_LPCR] & LPCR_OEE) { 1908 if (env->pending_interrupts & PPC_INTERRUPT_MCK) { 1909 return PPC_INTERRUPT_MCK; 1910 } 1911 if (env->pending_interrupts & PPC_INTERRUPT_HMI) { 1912 return PPC_INTERRUPT_HMI; 1913 } 1914 } 1915 /* Privileged Doorbell Exception */ 1916 if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && 1917 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 1918 return PPC_INTERRUPT_DOORBELL; 1919 } 1920 /* Hypervisor Doorbell Exception */ 1921 if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && 1922 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 1923 return PPC_INTERRUPT_HDOORBELL; 1924 } 1925 /* Hypervisor virtualization exception */ 1926 if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && 1927 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 1928 return PPC_INTERRUPT_HVIRT; 1929 } 1930 if (env->pending_interrupts & PPC_INTERRUPT_RESET) { 1931 return PPC_INTERRUPT_RESET; 1932 } 1933 return 0; 1934 } 1935 1936 static int p9_next_unmasked_interrupt(CPUPPCState *env) 1937 { 1938 PowerPCCPU *cpu = env_archcpu(env); 1939 CPUState *cs = CPU(cpu); 1940 /* Ignore MSR[EE] when coming out of some power management states */ 1941 bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; 1942 1943 assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0); 1944 1945 if (cs->halted) { 1946 if (env->spr[SPR_PSSCR] & PSSCR_EC) { 1947 /* 1948 * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can 1949 * wakeup the processor 1950 */ 1951 return p9_interrupt_powersave(env); 1952 } else { 1953 /* 1954 * When it's clear, any system-caused exception exits power-saving 1955 * mode, even the ones that gate on MSR[EE]. 1956 */ 1957 msr_ee = true; 1958 } 1959 } 1960 1961 /* Machine check exception */ 1962 if (env->pending_interrupts & PPC_INTERRUPT_MCK) { 1963 return PPC_INTERRUPT_MCK; 1964 } 1965 1966 /* Hypervisor decrementer exception */ 1967 if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { 1968 /* LPCR will be clear when not supported so this will work */ 1969 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 1970 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { 1971 /* HDEC clears on delivery */ 1972 return PPC_INTERRUPT_HDECR; 1973 } 1974 } 1975 1976 /* Hypervisor virtualization interrupt */ 1977 if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { 1978 /* LPCR will be clear when not supported so this will work */ 1979 bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); 1980 if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) { 1981 return PPC_INTERRUPT_HVIRT; 1982 } 1983 } 1984 1985 /* External interrupt can ignore MSR:EE under some circumstances */ 1986 if (env->pending_interrupts & PPC_INTERRUPT_EXT) { 1987 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 1988 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 1989 /* HEIC blocks delivery to the hypervisor */ 1990 if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && 1991 !FIELD_EX64(env->msr, MSR, PR))) || 1992 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { 1993 return PPC_INTERRUPT_EXT; 1994 } 1995 } 1996 if (msr_ee != 0) { 1997 /* Decrementer exception */ 1998 if (env->pending_interrupts & PPC_INTERRUPT_DECR) { 1999 return PPC_INTERRUPT_DECR; 2000 } 2001 if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { 2002 return PPC_INTERRUPT_DOORBELL; 2003 } 2004 if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { 2005 return PPC_INTERRUPT_HDOORBELL; 2006 } 2007 if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { 2008 return PPC_INTERRUPT_PERFM; 2009 } 2010 /* EBB exception */ 2011 if (env->pending_interrupts & PPC_INTERRUPT_EBB) { 2012 /* 2013 * EBB exception must be taken in problem state and 2014 * with BESCR_GE set. 2015 */ 2016 if (FIELD_EX64(env->msr, MSR, PR) && 2017 (env->spr[SPR_BESCR] & BESCR_GE)) { 2018 return PPC_INTERRUPT_EBB; 2019 } 2020 } 2021 } 2022 2023 return 0; 2024 } 2025 #endif 2026 2027 static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env) 2028 { 2029 bool async_deliver; 2030 2031 /* External reset */ 2032 if (env->pending_interrupts & PPC_INTERRUPT_RESET) { 2033 return PPC_INTERRUPT_RESET; 2034 } 2035 /* Machine check exception */ 2036 if (env->pending_interrupts & PPC_INTERRUPT_MCK) { 2037 return PPC_INTERRUPT_MCK; 2038 } 2039 #if 0 /* TODO */ 2040 /* External debug exception */ 2041 if (env->pending_interrupts & PPC_INTERRUPT_DEBUG) { 2042 return PPC_INTERRUPT_DEBUG; 2043 } 2044 #endif 2045 2046 /* 2047 * For interrupts that gate on MSR:EE, we need to do something a 2048 * bit more subtle, as we need to let them through even when EE is 2049 * clear when coming out of some power management states (in order 2050 * for them to become a 0x100). 2051 */ 2052 async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; 2053 2054 /* Hypervisor decrementer exception */ 2055 if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { 2056 /* LPCR will be clear when not supported so this will work */ 2057 bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); 2058 if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { 2059 /* HDEC clears on delivery */ 2060 return PPC_INTERRUPT_HDECR; 2061 } 2062 } 2063 2064 /* Hypervisor virtualization interrupt */ 2065 if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { 2066 /* LPCR will be clear when not supported so this will work */ 2067 bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); 2068 if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { 2069 return PPC_INTERRUPT_HVIRT; 2070 } 2071 } 2072 2073 /* External interrupt can ignore MSR:EE under some circumstances */ 2074 if (env->pending_interrupts & PPC_INTERRUPT_EXT) { 2075 bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); 2076 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 2077 /* HEIC blocks delivery to the hypervisor */ 2078 if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && 2079 !FIELD_EX64(env->msr, MSR, PR))) || 2080 (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { 2081 return PPC_INTERRUPT_EXT; 2082 } 2083 } 2084 if (FIELD_EX64(env->msr, MSR, CE)) { 2085 /* External critical interrupt */ 2086 if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { 2087 return PPC_INTERRUPT_CEXT; 2088 } 2089 } 2090 if (async_deliver != 0) { 2091 /* Watchdog timer on embedded PowerPC */ 2092 if (env->pending_interrupts & PPC_INTERRUPT_WDT) { 2093 return PPC_INTERRUPT_WDT; 2094 } 2095 if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { 2096 return PPC_INTERRUPT_CDOORBELL; 2097 } 2098 /* Fixed interval timer on embedded PowerPC */ 2099 if (env->pending_interrupts & PPC_INTERRUPT_FIT) { 2100 return PPC_INTERRUPT_FIT; 2101 } 2102 /* Programmable interval timer on embedded PowerPC */ 2103 if (env->pending_interrupts & PPC_INTERRUPT_PIT) { 2104 return PPC_INTERRUPT_PIT; 2105 } 2106 /* Decrementer exception */ 2107 if (env->pending_interrupts & PPC_INTERRUPT_DECR) { 2108 return PPC_INTERRUPT_DECR; 2109 } 2110 if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { 2111 return PPC_INTERRUPT_DOORBELL; 2112 } 2113 if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { 2114 return PPC_INTERRUPT_HDOORBELL; 2115 } 2116 if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { 2117 return PPC_INTERRUPT_PERFM; 2118 } 2119 /* Thermal interrupt */ 2120 if (env->pending_interrupts & PPC_INTERRUPT_THERM) { 2121 return PPC_INTERRUPT_THERM; 2122 } 2123 /* EBB exception */ 2124 if (env->pending_interrupts & PPC_INTERRUPT_EBB) { 2125 /* 2126 * EBB exception must be taken in problem state and 2127 * with BESCR_GE set. 2128 */ 2129 if (FIELD_EX64(env->msr, MSR, PR) && 2130 (env->spr[SPR_BESCR] & BESCR_GE)) { 2131 return PPC_INTERRUPT_EBB; 2132 } 2133 } 2134 } 2135 2136 return 0; 2137 } 2138 2139 static int ppc_next_unmasked_interrupt(CPUPPCState *env) 2140 { 2141 switch (env->excp_model) { 2142 #if defined(TARGET_PPC64) 2143 case POWERPC_EXCP_POWER7: 2144 return p7_next_unmasked_interrupt(env); 2145 case POWERPC_EXCP_POWER8: 2146 return p8_next_unmasked_interrupt(env); 2147 case POWERPC_EXCP_POWER9: 2148 case POWERPC_EXCP_POWER10: 2149 return p9_next_unmasked_interrupt(env); 2150 #endif 2151 default: 2152 return ppc_next_unmasked_interrupt_generic(env); 2153 } 2154 } 2155 2156 /* 2157 * Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be 2158 * delivered and clears CPU_INTERRUPT_HARD otherwise. 2159 * 2160 * This method is called by ppc_set_interrupt when an interrupt is raised or 2161 * lowered, and should also be called whenever an interrupt masking condition 2162 * is changed, e.g.: 2163 * - When relevant bits of MSR are altered, like EE, HV, PR, etc.; 2164 * - When relevant bits of LPCR are altered, like PECE, HDICE, HVICE, etc.; 2165 * - When PSSCR[EC] or env->resume_as_sreset are changed; 2166 * - When cs->halted is changed and the CPU has a different interrupt masking 2167 * logic in power-saving mode (e.g., POWER7/8/9/10); 2168 */ 2169 void ppc_maybe_interrupt(CPUPPCState *env) 2170 { 2171 CPUState *cs = env_cpu(env); 2172 QEMU_IOTHREAD_LOCK_GUARD(); 2173 2174 if (ppc_next_unmasked_interrupt(env)) { 2175 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 2176 } else { 2177 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 2178 } 2179 } 2180 2181 #if defined(TARGET_PPC64) 2182 static void p7_deliver_interrupt(CPUPPCState *env, int interrupt) 2183 { 2184 PowerPCCPU *cpu = env_archcpu(env); 2185 CPUState *cs = env_cpu(env); 2186 2187 switch (interrupt) { 2188 case PPC_INTERRUPT_MCK: /* Machine check exception */ 2189 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; 2190 powerpc_excp(cpu, POWERPC_EXCP_MCHECK); 2191 break; 2192 2193 case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ 2194 /* HDEC clears on delivery */ 2195 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; 2196 powerpc_excp(cpu, POWERPC_EXCP_HDECR); 2197 break; 2198 2199 case PPC_INTERRUPT_EXT: 2200 if (books_vhyp_promotes_external_to_hvirt(cpu)) { 2201 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2202 } else { 2203 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); 2204 } 2205 break; 2206 2207 case PPC_INTERRUPT_DECR: /* Decrementer exception */ 2208 powerpc_excp(cpu, POWERPC_EXCP_DECR); 2209 break; 2210 case PPC_INTERRUPT_PERFM: 2211 env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; 2212 powerpc_excp(cpu, POWERPC_EXCP_PERFM); 2213 break; 2214 case 0: 2215 /* 2216 * This is a bug ! It means that has_work took us out of halt without 2217 * anything to deliver while in a PM state that requires getting 2218 * out via a 0x100 2219 * 2220 * This means we will incorrectly execute past the power management 2221 * instruction instead of triggering a reset. 2222 * 2223 * It generally means a discrepancy between the wakeup conditions in the 2224 * processor has_work implementation and the logic in this function. 2225 */ 2226 assert(!env->resume_as_sreset); 2227 break; 2228 default: 2229 cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt); 2230 } 2231 } 2232 2233 static void p8_deliver_interrupt(CPUPPCState *env, int interrupt) 2234 { 2235 PowerPCCPU *cpu = env_archcpu(env); 2236 CPUState *cs = env_cpu(env); 2237 2238 switch (interrupt) { 2239 case PPC_INTERRUPT_MCK: /* Machine check exception */ 2240 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; 2241 powerpc_excp(cpu, POWERPC_EXCP_MCHECK); 2242 break; 2243 2244 case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ 2245 /* HDEC clears on delivery */ 2246 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; 2247 powerpc_excp(cpu, POWERPC_EXCP_HDECR); 2248 break; 2249 2250 case PPC_INTERRUPT_EXT: 2251 if (books_vhyp_promotes_external_to_hvirt(cpu)) { 2252 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2253 } else { 2254 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); 2255 } 2256 break; 2257 2258 case PPC_INTERRUPT_DECR: /* Decrementer exception */ 2259 powerpc_excp(cpu, POWERPC_EXCP_DECR); 2260 break; 2261 case PPC_INTERRUPT_DOORBELL: 2262 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; 2263 if (is_book3s_arch2x(env)) { 2264 powerpc_excp(cpu, POWERPC_EXCP_SDOOR); 2265 } else { 2266 powerpc_excp(cpu, POWERPC_EXCP_DOORI); 2267 } 2268 break; 2269 case PPC_INTERRUPT_HDOORBELL: 2270 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; 2271 powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); 2272 break; 2273 case PPC_INTERRUPT_PERFM: 2274 env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; 2275 powerpc_excp(cpu, POWERPC_EXCP_PERFM); 2276 break; 2277 case PPC_INTERRUPT_EBB: /* EBB exception */ 2278 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; 2279 if (env->spr[SPR_BESCR] & BESCR_PMEO) { 2280 powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); 2281 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { 2282 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); 2283 } 2284 break; 2285 case 0: 2286 /* 2287 * This is a bug ! It means that has_work took us out of halt without 2288 * anything to deliver while in a PM state that requires getting 2289 * out via a 0x100 2290 * 2291 * This means we will incorrectly execute past the power management 2292 * instruction instead of triggering a reset. 2293 * 2294 * It generally means a discrepancy between the wakeup conditions in the 2295 * processor has_work implementation and the logic in this function. 2296 */ 2297 assert(!env->resume_as_sreset); 2298 break; 2299 default: 2300 cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt); 2301 } 2302 } 2303 2304 static void p9_deliver_interrupt(CPUPPCState *env, int interrupt) 2305 { 2306 PowerPCCPU *cpu = env_archcpu(env); 2307 CPUState *cs = env_cpu(env); 2308 2309 if (cs->halted && !(env->spr[SPR_PSSCR] & PSSCR_EC) && 2310 !FIELD_EX64(env->msr, MSR, EE)) { 2311 /* 2312 * A pending interrupt took us out of power-saving, but MSR[EE] says 2313 * that we should return to NIP+4 instead of delivering it. 2314 */ 2315 return; 2316 } 2317 2318 switch (interrupt) { 2319 case PPC_INTERRUPT_MCK: /* Machine check exception */ 2320 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; 2321 powerpc_excp(cpu, POWERPC_EXCP_MCHECK); 2322 break; 2323 2324 case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ 2325 /* HDEC clears on delivery */ 2326 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; 2327 powerpc_excp(cpu, POWERPC_EXCP_HDECR); 2328 break; 2329 case PPC_INTERRUPT_HVIRT: /* Hypervisor virtualization interrupt */ 2330 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2331 break; 2332 2333 case PPC_INTERRUPT_EXT: 2334 if (books_vhyp_promotes_external_to_hvirt(cpu)) { 2335 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2336 } else { 2337 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); 2338 } 2339 break; 2340 2341 case PPC_INTERRUPT_DECR: /* Decrementer exception */ 2342 powerpc_excp(cpu, POWERPC_EXCP_DECR); 2343 break; 2344 case PPC_INTERRUPT_DOORBELL: 2345 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; 2346 powerpc_excp(cpu, POWERPC_EXCP_SDOOR); 2347 break; 2348 case PPC_INTERRUPT_HDOORBELL: 2349 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; 2350 powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); 2351 break; 2352 case PPC_INTERRUPT_PERFM: 2353 env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; 2354 powerpc_excp(cpu, POWERPC_EXCP_PERFM); 2355 break; 2356 case PPC_INTERRUPT_EBB: /* EBB exception */ 2357 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; 2358 if (env->spr[SPR_BESCR] & BESCR_PMEO) { 2359 powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); 2360 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { 2361 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); 2362 } 2363 break; 2364 case 0: 2365 /* 2366 * This is a bug ! It means that has_work took us out of halt without 2367 * anything to deliver while in a PM state that requires getting 2368 * out via a 0x100 2369 * 2370 * This means we will incorrectly execute past the power management 2371 * instruction instead of triggering a reset. 2372 * 2373 * It generally means a discrepancy between the wakeup conditions in the 2374 * processor has_work implementation and the logic in this function. 2375 */ 2376 assert(!env->resume_as_sreset); 2377 break; 2378 default: 2379 cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt); 2380 } 2381 } 2382 #endif 2383 2384 static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt) 2385 { 2386 PowerPCCPU *cpu = env_archcpu(env); 2387 CPUState *cs = env_cpu(env); 2388 2389 switch (interrupt) { 2390 case PPC_INTERRUPT_RESET: /* External reset */ 2391 env->pending_interrupts &= ~PPC_INTERRUPT_RESET; 2392 powerpc_excp(cpu, POWERPC_EXCP_RESET); 2393 break; 2394 case PPC_INTERRUPT_MCK: /* Machine check exception */ 2395 env->pending_interrupts &= ~PPC_INTERRUPT_MCK; 2396 powerpc_excp(cpu, POWERPC_EXCP_MCHECK); 2397 break; 2398 2399 case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ 2400 /* HDEC clears on delivery */ 2401 env->pending_interrupts &= ~PPC_INTERRUPT_HDECR; 2402 powerpc_excp(cpu, POWERPC_EXCP_HDECR); 2403 break; 2404 case PPC_INTERRUPT_HVIRT: /* Hypervisor virtualization interrupt */ 2405 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2406 break; 2407 2408 case PPC_INTERRUPT_EXT: 2409 if (books_vhyp_promotes_external_to_hvirt(cpu)) { 2410 powerpc_excp(cpu, POWERPC_EXCP_HVIRT); 2411 } else { 2412 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); 2413 } 2414 break; 2415 case PPC_INTERRUPT_CEXT: /* External critical interrupt */ 2416 powerpc_excp(cpu, POWERPC_EXCP_CRITICAL); 2417 break; 2418 2419 case PPC_INTERRUPT_WDT: /* Watchdog timer on embedded PowerPC */ 2420 env->pending_interrupts &= ~PPC_INTERRUPT_WDT; 2421 powerpc_excp(cpu, POWERPC_EXCP_WDT); 2422 break; 2423 case PPC_INTERRUPT_CDOORBELL: 2424 env->pending_interrupts &= ~PPC_INTERRUPT_CDOORBELL; 2425 powerpc_excp(cpu, POWERPC_EXCP_DOORCI); 2426 break; 2427 case PPC_INTERRUPT_FIT: /* Fixed interval timer on embedded PowerPC */ 2428 env->pending_interrupts &= ~PPC_INTERRUPT_FIT; 2429 powerpc_excp(cpu, POWERPC_EXCP_FIT); 2430 break; 2431 case PPC_INTERRUPT_PIT: /* Programmable interval timer on embedded ppc */ 2432 env->pending_interrupts &= ~PPC_INTERRUPT_PIT; 2433 powerpc_excp(cpu, POWERPC_EXCP_PIT); 2434 break; 2435 case PPC_INTERRUPT_DECR: /* Decrementer exception */ 2436 if (ppc_decr_clear_on_delivery(env)) { 2437 env->pending_interrupts &= ~PPC_INTERRUPT_DECR; 2438 } 2439 powerpc_excp(cpu, POWERPC_EXCP_DECR); 2440 break; 2441 case PPC_INTERRUPT_DOORBELL: 2442 env->pending_interrupts &= ~PPC_INTERRUPT_DOORBELL; 2443 if (is_book3s_arch2x(env)) { 2444 powerpc_excp(cpu, POWERPC_EXCP_SDOOR); 2445 } else { 2446 powerpc_excp(cpu, POWERPC_EXCP_DOORI); 2447 } 2448 break; 2449 case PPC_INTERRUPT_HDOORBELL: 2450 env->pending_interrupts &= ~PPC_INTERRUPT_HDOORBELL; 2451 powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); 2452 break; 2453 case PPC_INTERRUPT_PERFM: 2454 env->pending_interrupts &= ~PPC_INTERRUPT_PERFM; 2455 powerpc_excp(cpu, POWERPC_EXCP_PERFM); 2456 break; 2457 case PPC_INTERRUPT_THERM: /* Thermal interrupt */ 2458 env->pending_interrupts &= ~PPC_INTERRUPT_THERM; 2459 powerpc_excp(cpu, POWERPC_EXCP_THERM); 2460 break; 2461 case PPC_INTERRUPT_EBB: /* EBB exception */ 2462 env->pending_interrupts &= ~PPC_INTERRUPT_EBB; 2463 if (env->spr[SPR_BESCR] & BESCR_PMEO) { 2464 powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); 2465 } else if (env->spr[SPR_BESCR] & BESCR_EEO) { 2466 powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); 2467 } 2468 break; 2469 case 0: 2470 /* 2471 * This is a bug ! It means that has_work took us out of halt without 2472 * anything to deliver while in a PM state that requires getting 2473 * out via a 0x100 2474 * 2475 * This means we will incorrectly execute past the power management 2476 * instruction instead of triggering a reset. 2477 * 2478 * It generally means a discrepancy between the wakeup conditions in the 2479 * processor has_work implementation and the logic in this function. 2480 */ 2481 assert(!env->resume_as_sreset); 2482 break; 2483 default: 2484 cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt); 2485 } 2486 } 2487 2488 static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt) 2489 { 2490 switch (env->excp_model) { 2491 #if defined(TARGET_PPC64) 2492 case POWERPC_EXCP_POWER7: 2493 p7_deliver_interrupt(env, interrupt); 2494 break; 2495 case POWERPC_EXCP_POWER8: 2496 p8_deliver_interrupt(env, interrupt); 2497 break; 2498 case POWERPC_EXCP_POWER9: 2499 case POWERPC_EXCP_POWER10: 2500 p9_deliver_interrupt(env, interrupt); 2501 break; 2502 #endif 2503 default: 2504 ppc_deliver_interrupt_generic(env, interrupt); 2505 } 2506 } 2507 2508 void ppc_cpu_do_system_reset(CPUState *cs) 2509 { 2510 PowerPCCPU *cpu = POWERPC_CPU(cs); 2511 2512 powerpc_excp(cpu, POWERPC_EXCP_RESET); 2513 } 2514 2515 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) 2516 { 2517 PowerPCCPU *cpu = POWERPC_CPU(cs); 2518 CPUPPCState *env = &cpu->env; 2519 target_ulong msr = 0; 2520 2521 /* 2522 * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already 2523 * been set by KVM. 2524 */ 2525 msr = (1ULL << MSR_ME); 2526 msr |= env->msr & (1ULL << MSR_SF); 2527 if (ppc_interrupts_little_endian(cpu, false)) { 2528 msr |= (1ULL << MSR_LE); 2529 } 2530 2531 /* Anything for nested required here? MSR[HV] bit? */ 2532 2533 powerpc_set_excp_state(cpu, vector, msr); 2534 } 2535 2536 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 2537 { 2538 PowerPCCPU *cpu = POWERPC_CPU(cs); 2539 CPUPPCState *env = &cpu->env; 2540 int interrupt; 2541 2542 if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) { 2543 return false; 2544 } 2545 2546 interrupt = ppc_next_unmasked_interrupt(env); 2547 if (interrupt == 0) { 2548 return false; 2549 } 2550 2551 ppc_deliver_interrupt(env, interrupt); 2552 if (env->pending_interrupts == 0) { 2553 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 2554 } 2555 return true; 2556 } 2557 2558 #endif /* !CONFIG_USER_ONLY */ 2559 2560 /*****************************************************************************/ 2561 /* Exceptions processing helpers */ 2562 2563 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 2564 uint32_t error_code, uintptr_t raddr) 2565 { 2566 CPUState *cs = env_cpu(env); 2567 2568 cs->exception_index = exception; 2569 env->error_code = error_code; 2570 cpu_loop_exit_restore(cs, raddr); 2571 } 2572 2573 void raise_exception_err(CPUPPCState *env, uint32_t exception, 2574 uint32_t error_code) 2575 { 2576 raise_exception_err_ra(env, exception, error_code, 0); 2577 } 2578 2579 void raise_exception(CPUPPCState *env, uint32_t exception) 2580 { 2581 raise_exception_err_ra(env, exception, 0, 0); 2582 } 2583 2584 void raise_exception_ra(CPUPPCState *env, uint32_t exception, 2585 uintptr_t raddr) 2586 { 2587 raise_exception_err_ra(env, exception, 0, raddr); 2588 } 2589 2590 #ifdef CONFIG_TCG 2591 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, 2592 uint32_t error_code) 2593 { 2594 raise_exception_err_ra(env, exception, error_code, 0); 2595 } 2596 2597 void helper_raise_exception(CPUPPCState *env, uint32_t exception) 2598 { 2599 raise_exception_err_ra(env, exception, 0, 0); 2600 } 2601 #endif 2602 2603 #if !defined(CONFIG_USER_ONLY) 2604 #ifdef CONFIG_TCG 2605 void helper_store_msr(CPUPPCState *env, target_ulong val) 2606 { 2607 uint32_t excp = hreg_store_msr(env, val, 0); 2608 2609 if (excp != 0) { 2610 CPUState *cs = env_cpu(env); 2611 cpu_interrupt_exittb(cs); 2612 raise_exception(env, excp); 2613 } 2614 } 2615 2616 void helper_ppc_maybe_interrupt(CPUPPCState *env) 2617 { 2618 ppc_maybe_interrupt(env); 2619 } 2620 2621 #if defined(TARGET_PPC64) 2622 void helper_scv(CPUPPCState *env, uint32_t lev) 2623 { 2624 if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { 2625 raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); 2626 } else { 2627 raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); 2628 } 2629 } 2630 2631 void helper_pminsn(CPUPPCState *env, uint32_t insn) 2632 { 2633 CPUState *cs; 2634 2635 cs = env_cpu(env); 2636 cs->halted = 1; 2637 2638 /* Condition for waking up at 0x100 */ 2639 env->resume_as_sreset = (insn != PPC_PM_STOP) || 2640 (env->spr[SPR_PSSCR] & PSSCR_EC); 2641 2642 ppc_maybe_interrupt(env); 2643 } 2644 #endif /* defined(TARGET_PPC64) */ 2645 2646 static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) 2647 { 2648 CPUState *cs = env_cpu(env); 2649 2650 /* MSR:POW cannot be set by any form of rfi */ 2651 msr &= ~(1ULL << MSR_POW); 2652 2653 /* MSR:TGPR cannot be set by any form of rfi */ 2654 if (env->flags & POWERPC_FLAG_TGPR) 2655 msr &= ~(1ULL << MSR_TGPR); 2656 2657 #if defined(TARGET_PPC64) 2658 /* Switching to 32-bit ? Crop the nip */ 2659 if (!msr_is_64bit(env, msr)) { 2660 nip = (uint32_t)nip; 2661 } 2662 #else 2663 nip = (uint32_t)nip; 2664 #endif 2665 /* XXX: beware: this is false if VLE is supported */ 2666 env->nip = nip & ~((target_ulong)0x00000003); 2667 hreg_store_msr(env, msr, 1); 2668 trace_ppc_excp_rfi(env->nip, env->msr); 2669 /* 2670 * No need to raise an exception here, as rfi is always the last 2671 * insn of a TB 2672 */ 2673 cpu_interrupt_exittb(cs); 2674 /* Reset the reservation */ 2675 env->reserve_addr = -1; 2676 2677 /* Context synchronizing: check if TCG TLB needs flush */ 2678 check_tlb_flush(env, false); 2679 } 2680 2681 void helper_rfi(CPUPPCState *env) 2682 { 2683 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); 2684 } 2685 2686 #if defined(TARGET_PPC64) 2687 void helper_rfid(CPUPPCState *env) 2688 { 2689 /* 2690 * The architecture defines a number of rules for which bits can 2691 * change but in practice, we handle this in hreg_store_msr() 2692 * which will be called by do_rfi(), so there is no need to filter 2693 * here 2694 */ 2695 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); 2696 } 2697 2698 void helper_rfscv(CPUPPCState *env) 2699 { 2700 do_rfi(env, env->lr, env->ctr); 2701 } 2702 2703 void helper_hrfid(CPUPPCState *env) 2704 { 2705 do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 2706 } 2707 #endif 2708 2709 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2710 void helper_rfebb(CPUPPCState *env, target_ulong s) 2711 { 2712 target_ulong msr = env->msr; 2713 2714 /* 2715 * Handling of BESCR bits 32:33 according to PowerISA v3.1: 2716 * 2717 * "If BESCR 32:33 != 0b00 the instruction is treated as if 2718 * the instruction form were invalid." 2719 */ 2720 if (env->spr[SPR_BESCR] & BESCR_INVALID) { 2721 raise_exception_err(env, POWERPC_EXCP_PROGRAM, 2722 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); 2723 } 2724 2725 env->nip = env->spr[SPR_EBBRR]; 2726 2727 /* Switching to 32-bit ? Crop the nip */ 2728 if (!msr_is_64bit(env, msr)) { 2729 env->nip = (uint32_t)env->spr[SPR_EBBRR]; 2730 } 2731 2732 if (s) { 2733 env->spr[SPR_BESCR] |= BESCR_GE; 2734 } else { 2735 env->spr[SPR_BESCR] &= ~BESCR_GE; 2736 } 2737 } 2738 2739 /* 2740 * Triggers or queues an 'ebb_excp' EBB exception. All checks 2741 * but FSCR, HFSCR and msr_pr must be done beforehand. 2742 * 2743 * PowerISA v3.1 isn't clear about whether an EBB should be 2744 * postponed or cancelled if the EBB facility is unavailable. 2745 * Our assumption here is that the EBB is cancelled if both 2746 * FSCR and HFSCR EBB facilities aren't available. 2747 */ 2748 static void do_ebb(CPUPPCState *env, int ebb_excp) 2749 { 2750 PowerPCCPU *cpu = env_archcpu(env); 2751 2752 /* 2753 * FSCR_EBB and FSCR_IC_EBB are the same bits used with 2754 * HFSCR. 2755 */ 2756 helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB); 2757 helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB); 2758 2759 if (ebb_excp == POWERPC_EXCP_PERFM_EBB) { 2760 env->spr[SPR_BESCR] |= BESCR_PMEO; 2761 } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) { 2762 env->spr[SPR_BESCR] |= BESCR_EEO; 2763 } 2764 2765 if (FIELD_EX64(env->msr, MSR, PR)) { 2766 powerpc_excp(cpu, ebb_excp); 2767 } else { 2768 ppc_set_irq(cpu, PPC_INTERRUPT_EBB, 1); 2769 } 2770 } 2771 2772 void raise_ebb_perfm_exception(CPUPPCState *env) 2773 { 2774 bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && 2775 env->spr[SPR_BESCR] & BESCR_PME && 2776 env->spr[SPR_BESCR] & BESCR_GE; 2777 2778 if (!perfm_ebb_enabled) { 2779 return; 2780 } 2781 2782 do_ebb(env, POWERPC_EXCP_PERFM_EBB); 2783 } 2784 #endif 2785 2786 /*****************************************************************************/ 2787 /* Embedded PowerPC specific helpers */ 2788 void helper_40x_rfci(CPUPPCState *env) 2789 { 2790 do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); 2791 } 2792 2793 void helper_rfci(CPUPPCState *env) 2794 { 2795 do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); 2796 } 2797 2798 void helper_rfdi(CPUPPCState *env) 2799 { 2800 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ 2801 do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); 2802 } 2803 2804 void helper_rfmci(CPUPPCState *env) 2805 { 2806 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ 2807 do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 2808 } 2809 #endif /* CONFIG_TCG */ 2810 #endif /* !defined(CONFIG_USER_ONLY) */ 2811 2812 #ifdef CONFIG_TCG 2813 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 2814 uint32_t flags) 2815 { 2816 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || 2817 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || 2818 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || 2819 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || 2820 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { 2821 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 2822 POWERPC_EXCP_TRAP, GETPC()); 2823 } 2824 } 2825 2826 #if defined(TARGET_PPC64) 2827 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, 2828 uint32_t flags) 2829 { 2830 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || 2831 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || 2832 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || 2833 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || 2834 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { 2835 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 2836 POWERPC_EXCP_TRAP, GETPC()); 2837 } 2838 } 2839 #endif 2840 #endif 2841 2842 #ifdef CONFIG_TCG 2843 static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane) 2844 { 2845 const uint16_t c = 0xfffc; 2846 const uint64_t z0 = 0xfa2561cdf44ac398ULL; 2847 uint16_t z = 0, temp; 2848 uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32]; 2849 2850 for (int i = 3; i >= 0; i--) { 2851 k[i] = key & 0xffff; 2852 key >>= 16; 2853 } 2854 xleft[0] = x & 0xffff; 2855 xright[0] = (x >> 16) & 0xffff; 2856 2857 for (int i = 0; i < 28; i++) { 2858 z = (z0 >> (63 - i)) & 1; 2859 temp = ror16(k[i + 3], 3) ^ k[i + 1]; 2860 k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1); 2861 } 2862 2863 for (int i = 0; i < 8; i++) { 2864 eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)]; 2865 eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)]; 2866 eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)]; 2867 eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)]; 2868 } 2869 2870 for (int i = 0; i < 32; i++) { 2871 fxleft[i] = (rol16(xleft[i], 1) & 2872 rol16(xleft[i], 8)) ^ rol16(xleft[i], 2); 2873 xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i]; 2874 xright[i + 1] = xleft[i]; 2875 } 2876 2877 return (((uint32_t)xright[32]) << 16) | xleft[32]; 2878 } 2879 2880 static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key) 2881 { 2882 uint64_t stage0_h = 0ULL, stage0_l = 0ULL; 2883 uint64_t stage1_h, stage1_l; 2884 2885 for (int i = 0; i < 4; i++) { 2886 stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1)); 2887 stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i); 2888 stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1)); 2889 stage0_l |= (ra & 0xff) << (8 * 2 * i); 2890 rb >>= 8; 2891 ra >>= 8; 2892 } 2893 2894 stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32; 2895 stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1); 2896 stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32; 2897 stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3); 2898 2899 return stage1_h ^ stage1_l; 2900 } 2901 2902 static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra, 2903 target_ulong rb, uint64_t key, bool store) 2904 { 2905 uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash; 2906 2907 if (store) { 2908 cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); 2909 } else { 2910 loaded_hash = cpu_ldq_data_ra(env, ea, GETPC()); 2911 if (loaded_hash != calculated_hash) { 2912 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 2913 POWERPC_EXCP_TRAP, GETPC()); 2914 } 2915 } 2916 } 2917 2918 #include "qemu/guest-random.h" 2919 2920 #ifdef TARGET_PPC64 2921 #define HELPER_HASH(op, key, store, dexcr_aspect) \ 2922 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \ 2923 target_ulong rb) \ 2924 { \ 2925 if (env->msr & R_MSR_PR_MASK) { \ 2926 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \ 2927 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \ 2928 return; \ 2929 } else if (!(env->msr & R_MSR_HV_MASK)) { \ 2930 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \ 2931 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \ 2932 return; \ 2933 } else if (!(env->msr & R_MSR_S_MASK)) { \ 2934 if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \ 2935 return; \ 2936 } \ 2937 \ 2938 do_hash(env, ea, ra, rb, key, store); \ 2939 } 2940 #else 2941 #define HELPER_HASH(op, key, store, dexcr_aspect) \ 2942 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \ 2943 target_ulong rb) \ 2944 { \ 2945 do_hash(env, ea, ra, rb, key, store); \ 2946 } 2947 #endif /* TARGET_PPC64 */ 2948 2949 HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE) 2950 HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE) 2951 HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE) 2952 HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE) 2953 #endif /* CONFIG_TCG */ 2954 2955 #if !defined(CONFIG_USER_ONLY) 2956 2957 #ifdef CONFIG_TCG 2958 2959 /* Embedded.Processor Control */ 2960 static int dbell2irq(target_ulong rb) 2961 { 2962 int msg = rb & DBELL_TYPE_MASK; 2963 int irq = -1; 2964 2965 switch (msg) { 2966 case DBELL_TYPE_DBELL: 2967 irq = PPC_INTERRUPT_DOORBELL; 2968 break; 2969 case DBELL_TYPE_DBELL_CRIT: 2970 irq = PPC_INTERRUPT_CDOORBELL; 2971 break; 2972 case DBELL_TYPE_G_DBELL: 2973 case DBELL_TYPE_G_DBELL_CRIT: 2974 case DBELL_TYPE_G_DBELL_MC: 2975 /* XXX implement */ 2976 default: 2977 break; 2978 } 2979 2980 return irq; 2981 } 2982 2983 void helper_msgclr(CPUPPCState *env, target_ulong rb) 2984 { 2985 int irq = dbell2irq(rb); 2986 2987 if (irq < 0) { 2988 return; 2989 } 2990 2991 ppc_set_irq(env_archcpu(env), irq, 0); 2992 } 2993 2994 void helper_msgsnd(target_ulong rb) 2995 { 2996 int irq = dbell2irq(rb); 2997 int pir = rb & DBELL_PIRTAG_MASK; 2998 CPUState *cs; 2999 3000 if (irq < 0) { 3001 return; 3002 } 3003 3004 qemu_mutex_lock_iothread(); 3005 CPU_FOREACH(cs) { 3006 PowerPCCPU *cpu = POWERPC_CPU(cs); 3007 CPUPPCState *cenv = &cpu->env; 3008 3009 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { 3010 ppc_set_irq(cpu, irq, 1); 3011 } 3012 } 3013 qemu_mutex_unlock_iothread(); 3014 } 3015 3016 /* Server Processor Control */ 3017 3018 static bool dbell_type_server(target_ulong rb) 3019 { 3020 /* 3021 * A Directed Hypervisor Doorbell message is sent only if the 3022 * message type is 5. All other types are reserved and the 3023 * instruction is a no-op 3024 */ 3025 return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER; 3026 } 3027 3028 void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) 3029 { 3030 if (!dbell_type_server(rb)) { 3031 return; 3032 } 3033 3034 ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); 3035 } 3036 3037 static void book3s_msgsnd_common(int pir, int irq) 3038 { 3039 CPUState *cs; 3040 3041 qemu_mutex_lock_iothread(); 3042 CPU_FOREACH(cs) { 3043 PowerPCCPU *cpu = POWERPC_CPU(cs); 3044 CPUPPCState *cenv = &cpu->env; 3045 3046 /* TODO: broadcast message to all threads of the same processor */ 3047 if (cenv->spr_cb[SPR_PIR].default_value == pir) { 3048 ppc_set_irq(cpu, irq, 1); 3049 } 3050 } 3051 qemu_mutex_unlock_iothread(); 3052 } 3053 3054 void helper_book3s_msgsnd(target_ulong rb) 3055 { 3056 int pir = rb & DBELL_PROCIDTAG_MASK; 3057 3058 if (!dbell_type_server(rb)) { 3059 return; 3060 } 3061 3062 book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL); 3063 } 3064 3065 #if defined(TARGET_PPC64) 3066 void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) 3067 { 3068 helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); 3069 3070 if (!dbell_type_server(rb)) { 3071 return; 3072 } 3073 3074 ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); 3075 } 3076 3077 /* 3078 * sends a message to other threads that are on the same 3079 * multi-threaded processor 3080 */ 3081 void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) 3082 { 3083 int pir = env->spr_cb[SPR_PIR].default_value; 3084 3085 helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); 3086 3087 if (!dbell_type_server(rb)) { 3088 return; 3089 } 3090 3091 /* TODO: TCG supports only one thread */ 3092 3093 book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); 3094 } 3095 #endif /* TARGET_PPC64 */ 3096 3097 void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, 3098 MMUAccessType access_type, 3099 int mmu_idx, uintptr_t retaddr) 3100 { 3101 CPUPPCState *env = cs->env_ptr; 3102 uint32_t insn; 3103 3104 /* Restore state and reload the insn we executed, for filling in DSISR. */ 3105 cpu_restore_state(cs, retaddr); 3106 insn = cpu_ldl_code(env, env->nip); 3107 3108 switch (env->mmu_model) { 3109 case POWERPC_MMU_SOFT_4xx: 3110 env->spr[SPR_40x_DEAR] = vaddr; 3111 break; 3112 case POWERPC_MMU_BOOKE: 3113 case POWERPC_MMU_BOOKE206: 3114 env->spr[SPR_BOOKE_DEAR] = vaddr; 3115 break; 3116 default: 3117 env->spr[SPR_DAR] = vaddr; 3118 break; 3119 } 3120 3121 cs->exception_index = POWERPC_EXCP_ALIGN; 3122 env->error_code = insn & 0x03FF0000; 3123 cpu_loop_exit(cs); 3124 } 3125 #endif /* CONFIG_TCG */ 3126 #endif /* !CONFIG_USER_ONLY */ 3127