1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_common.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 static void register_745_sprs(CPUPPCState *env) 61 { 62 /* SGPRs */ 63 spr_register(env, SPR_SPRG4, "SPRG4", 64 SPR_NOACCESS, SPR_NOACCESS, 65 &spr_read_generic, &spr_write_generic, 66 0x00000000); 67 spr_register(env, SPR_SPRG5, "SPRG5", 68 SPR_NOACCESS, SPR_NOACCESS, 69 &spr_read_generic, &spr_write_generic, 70 0x00000000); 71 spr_register(env, SPR_SPRG6, "SPRG6", 72 SPR_NOACCESS, SPR_NOACCESS, 73 &spr_read_generic, &spr_write_generic, 74 0x00000000); 75 spr_register(env, SPR_SPRG7, "SPRG7", 76 SPR_NOACCESS, SPR_NOACCESS, 77 &spr_read_generic, &spr_write_generic, 78 0x00000000); 79 80 /* Hardware implementation registers */ 81 spr_register(env, SPR_HID0, "HID0", 82 SPR_NOACCESS, SPR_NOACCESS, 83 &spr_read_generic, &spr_write_generic, 84 0x00000000); 85 86 spr_register(env, SPR_HID1, "HID1", 87 SPR_NOACCESS, SPR_NOACCESS, 88 &spr_read_generic, &spr_write_generic, 89 0x00000000); 90 91 spr_register(env, SPR_HID2, "HID2", 92 SPR_NOACCESS, SPR_NOACCESS, 93 &spr_read_generic, &spr_write_generic, 94 0x00000000); 95 } 96 97 static void register_755_sprs(CPUPPCState *env) 98 { 99 /* L2 cache control */ 100 spr_register(env, SPR_L2CR, "L2CR", 101 SPR_NOACCESS, SPR_NOACCESS, 102 &spr_read_generic, spr_access_nop, 103 0x00000000); 104 105 spr_register(env, SPR_L2PMCR, "L2PMCR", 106 SPR_NOACCESS, SPR_NOACCESS, 107 &spr_read_generic, &spr_write_generic, 108 0x00000000); 109 } 110 111 /* SPR common to all 7xx PowerPC implementations */ 112 static void register_7xx_sprs(CPUPPCState *env) 113 { 114 /* Breakpoints */ 115 spr_register_kvm(env, SPR_DABR, "DABR", 116 SPR_NOACCESS, SPR_NOACCESS, 117 &spr_read_generic, &spr_write_generic, 118 KVM_REG_PPC_DABR, 0x00000000); 119 120 spr_register(env, SPR_IABR, "IABR", 121 SPR_NOACCESS, SPR_NOACCESS, 122 &spr_read_generic, &spr_write_generic, 123 0x00000000); 124 /* Cache management */ 125 spr_register(env, SPR_ICTC, "ICTC", 126 SPR_NOACCESS, SPR_NOACCESS, 127 &spr_read_generic, &spr_write_generic, 128 0x00000000); 129 /* Performance monitors */ 130 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 131 SPR_NOACCESS, SPR_NOACCESS, 132 &spr_read_generic, &spr_write_generic, 133 0x00000000); 134 135 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 136 SPR_NOACCESS, SPR_NOACCESS, 137 &spr_read_generic, &spr_write_generic, 138 0x00000000); 139 140 spr_register(env, SPR_7XX_PMC1, "PMC1", 141 SPR_NOACCESS, SPR_NOACCESS, 142 &spr_read_generic, &spr_write_generic, 143 0x00000000); 144 145 spr_register(env, SPR_7XX_PMC2, "PMC2", 146 SPR_NOACCESS, SPR_NOACCESS, 147 &spr_read_generic, &spr_write_generic, 148 0x00000000); 149 150 spr_register(env, SPR_7XX_PMC3, "PMC3", 151 SPR_NOACCESS, SPR_NOACCESS, 152 &spr_read_generic, &spr_write_generic, 153 0x00000000); 154 155 spr_register(env, SPR_7XX_PMC4, "PMC4", 156 SPR_NOACCESS, SPR_NOACCESS, 157 &spr_read_generic, &spr_write_generic, 158 0x00000000); 159 160 spr_register(env, SPR_7XX_SIAR, "SIAR", 161 SPR_NOACCESS, SPR_NOACCESS, 162 &spr_read_generic, SPR_NOACCESS, 163 0x00000000); 164 165 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 166 &spr_read_ureg, SPR_NOACCESS, 167 &spr_read_ureg, SPR_NOACCESS, 168 0x00000000); 169 170 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 171 &spr_read_ureg, SPR_NOACCESS, 172 &spr_read_ureg, SPR_NOACCESS, 173 0x00000000); 174 175 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 176 &spr_read_ureg, SPR_NOACCESS, 177 &spr_read_ureg, SPR_NOACCESS, 178 0x00000000); 179 180 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 181 &spr_read_ureg, SPR_NOACCESS, 182 &spr_read_ureg, SPR_NOACCESS, 183 0x00000000); 184 185 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 186 &spr_read_ureg, SPR_NOACCESS, 187 &spr_read_ureg, SPR_NOACCESS, 188 0x00000000); 189 190 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 191 &spr_read_ureg, SPR_NOACCESS, 192 &spr_read_ureg, SPR_NOACCESS, 193 0x00000000); 194 195 spr_register(env, SPR_7XX_USIAR, "USIAR", 196 &spr_read_ureg, SPR_NOACCESS, 197 &spr_read_ureg, SPR_NOACCESS, 198 0x00000000); 199 /* External access control */ 200 spr_register(env, SPR_EAR, "EAR", 201 SPR_NOACCESS, SPR_NOACCESS, 202 &spr_read_generic, &spr_write_generic, 203 0x00000000); 204 205 /* Hardware implementation registers */ 206 spr_register(env, SPR_HID0, "HID0", 207 SPR_NOACCESS, SPR_NOACCESS, 208 &spr_read_generic, &spr_write_generic, 209 0x00000000); 210 211 spr_register(env, SPR_HID1, "HID1", 212 SPR_NOACCESS, SPR_NOACCESS, 213 &spr_read_generic, &spr_write_generic, 214 0x00000000); 215 } 216 217 #ifdef TARGET_PPC64 218 static void register_amr_sprs(CPUPPCState *env) 219 { 220 #ifndef CONFIG_USER_ONLY 221 /* 222 * Virtual Page Class Key protection 223 * 224 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 225 * userspace accessible, 29 is privileged. So we only need to set 226 * the kvm ONE_REG id on one of them, we use 29 227 */ 228 spr_register(env, SPR_UAMR, "UAMR", 229 &spr_read_generic, &spr_write_amr, 230 &spr_read_generic, &spr_write_amr, 231 0); 232 spr_register_kvm_hv(env, SPR_AMR, "AMR", 233 SPR_NOACCESS, SPR_NOACCESS, 234 &spr_read_generic, &spr_write_amr, 235 &spr_read_generic, &spr_write_generic, 236 KVM_REG_PPC_AMR, 0); 237 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 238 SPR_NOACCESS, SPR_NOACCESS, 239 &spr_read_generic, &spr_write_uamor, 240 &spr_read_generic, &spr_write_generic, 241 KVM_REG_PPC_UAMOR, 0); 242 spr_register_hv(env, SPR_AMOR, "AMOR", 243 SPR_NOACCESS, SPR_NOACCESS, 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_generic, &spr_write_generic, 246 0); 247 #endif /* !CONFIG_USER_ONLY */ 248 } 249 250 static void register_iamr_sprs(CPUPPCState *env) 251 { 252 #ifndef CONFIG_USER_ONLY 253 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 254 SPR_NOACCESS, SPR_NOACCESS, 255 &spr_read_generic, &spr_write_iamr, 256 &spr_read_generic, &spr_write_generic, 257 KVM_REG_PPC_IAMR, 0); 258 #endif /* !CONFIG_USER_ONLY */ 259 } 260 #endif /* TARGET_PPC64 */ 261 262 /* SPR specific to PowerPC 604 implementation */ 263 static void register_604_sprs(CPUPPCState *env) 264 { 265 /* Processor identification */ 266 spr_register(env, SPR_PIR, "PIR", 267 SPR_NOACCESS, SPR_NOACCESS, 268 &spr_read_generic, &spr_write_pir, 269 0x00000000); 270 /* Breakpoints */ 271 spr_register(env, SPR_IABR, "IABR", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_generic, &spr_write_generic, 274 0x00000000); 275 276 spr_register_kvm(env, SPR_DABR, "DABR", 277 SPR_NOACCESS, SPR_NOACCESS, 278 &spr_read_generic, &spr_write_generic, 279 KVM_REG_PPC_DABR, 0x00000000); 280 /* Performance counters */ 281 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 282 SPR_NOACCESS, SPR_NOACCESS, 283 &spr_read_generic, &spr_write_generic, 284 0x00000000); 285 286 spr_register(env, SPR_7XX_PMC1, "PMC1", 287 SPR_NOACCESS, SPR_NOACCESS, 288 &spr_read_generic, &spr_write_generic, 289 0x00000000); 290 291 spr_register(env, SPR_7XX_PMC2, "PMC2", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_generic, &spr_write_generic, 294 0x00000000); 295 296 spr_register(env, SPR_7XX_SIAR, "SIAR", 297 SPR_NOACCESS, SPR_NOACCESS, 298 &spr_read_generic, SPR_NOACCESS, 299 0x00000000); 300 301 spr_register(env, SPR_SDA, "SDA", 302 SPR_NOACCESS, SPR_NOACCESS, 303 &spr_read_generic, SPR_NOACCESS, 304 0x00000000); 305 /* External access control */ 306 spr_register(env, SPR_EAR, "EAR", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_generic, &spr_write_generic, 309 0x00000000); 310 311 /* Hardware implementation registers */ 312 spr_register(env, SPR_HID0, "HID0", 313 SPR_NOACCESS, SPR_NOACCESS, 314 &spr_read_generic, &spr_write_generic, 315 0x00000000); 316 } 317 318 static void register_604e_sprs(CPUPPCState *env) 319 { 320 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 321 SPR_NOACCESS, SPR_NOACCESS, 322 &spr_read_generic, &spr_write_generic, 323 0x00000000); 324 325 spr_register(env, SPR_7XX_PMC3, "PMC3", 326 SPR_NOACCESS, SPR_NOACCESS, 327 &spr_read_generic, &spr_write_generic, 328 0x00000000); 329 330 spr_register(env, SPR_7XX_PMC4, "PMC4", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_generic, &spr_write_generic, 333 0x00000000); 334 /* Hardware implementation registers */ 335 spr_register(env, SPR_HID1, "HID1", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_generic, &spr_write_generic, 338 0x00000000); 339 } 340 341 /* SPR specific to PowerPC 603 implementation */ 342 static void register_603_sprs(CPUPPCState *env) 343 { 344 /* External access control */ 345 spr_register(env, SPR_EAR, "EAR", 346 SPR_NOACCESS, SPR_NOACCESS, 347 &spr_read_generic, &spr_write_generic, 348 0x00000000); 349 /* Breakpoints */ 350 spr_register(env, SPR_IABR, "IABR", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_generic, &spr_write_generic, 353 0x00000000); 354 355 spr_register(env, SPR_HID0, "HID0", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_generic, &spr_write_generic, 358 0x00000000); 359 360 spr_register(env, SPR_HID1, "HID1", 361 SPR_NOACCESS, SPR_NOACCESS, 362 &spr_read_generic, &spr_write_generic, 363 0x00000000); 364 } 365 366 static void register_e300_sprs(CPUPPCState *env) 367 { 368 /* hardware implementation registers */ 369 spr_register(env, SPR_HID2, "HID2", 370 SPR_NOACCESS, SPR_NOACCESS, 371 &spr_read_generic, &spr_write_generic, 372 0x00000000); 373 /* Breakpoints */ 374 spr_register(env, SPR_DABR, "DABR", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_generic, &spr_write_generic, 377 0x00000000); 378 379 spr_register(env, SPR_DABR2, "DABR2", 380 SPR_NOACCESS, SPR_NOACCESS, 381 &spr_read_generic, &spr_write_generic, 382 0x00000000); 383 384 spr_register(env, SPR_IABR2, "IABR2", 385 SPR_NOACCESS, SPR_NOACCESS, 386 &spr_read_generic, &spr_write_generic, 387 0x00000000); 388 389 spr_register(env, SPR_IBCR, "IBCR", 390 SPR_NOACCESS, SPR_NOACCESS, 391 &spr_read_generic, &spr_write_generic, 392 0x00000000); 393 394 spr_register(env, SPR_DBCR, "DBCR", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, &spr_write_generic, 397 0x00000000); 398 } 399 400 /* SPR specific to PowerPC G2 implementation */ 401 static void register_G2_sprs(CPUPPCState *env) 402 { 403 /* Memory base address */ 404 /* MBAR */ 405 spr_register(env, SPR_MBAR, "MBAR", 406 SPR_NOACCESS, SPR_NOACCESS, 407 &spr_read_generic, &spr_write_generic, 408 0x00000000); 409 /* Exception processing */ 410 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_generic, &spr_write_generic, 413 0x00000000); 414 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_generic, &spr_write_generic, 417 0x00000000); 418 /* Breakpoints */ 419 spr_register(env, SPR_DABR, "DABR", 420 SPR_NOACCESS, SPR_NOACCESS, 421 &spr_read_generic, &spr_write_generic, 422 0x00000000); 423 424 spr_register(env, SPR_DABR2, "DABR2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, &spr_write_generic, 427 0x00000000); 428 429 spr_register(env, SPR_IABR, "IABR", 430 SPR_NOACCESS, SPR_NOACCESS, 431 &spr_read_generic, &spr_write_generic, 432 0x00000000); 433 434 spr_register(env, SPR_IABR2, "IABR2", 435 SPR_NOACCESS, SPR_NOACCESS, 436 &spr_read_generic, &spr_write_generic, 437 0x00000000); 438 439 spr_register(env, SPR_IBCR, "IBCR", 440 SPR_NOACCESS, SPR_NOACCESS, 441 &spr_read_generic, &spr_write_generic, 442 0x00000000); 443 444 spr_register(env, SPR_DBCR, "DBCR", 445 SPR_NOACCESS, SPR_NOACCESS, 446 &spr_read_generic, &spr_write_generic, 447 0x00000000); 448 449 /* External access control */ 450 spr_register(env, SPR_EAR, "EAR", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, &spr_write_generic, 453 0x00000000); 454 /* Hardware implementation register */ 455 spr_register(env, SPR_HID0, "HID0", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 460 spr_register(env, SPR_HID1, "HID1", 461 SPR_NOACCESS, SPR_NOACCESS, 462 &spr_read_generic, &spr_write_generic, 463 0x00000000); 464 465 spr_register(env, SPR_HID2, "HID2", 466 SPR_NOACCESS, SPR_NOACCESS, 467 &spr_read_generic, &spr_write_generic, 468 0x00000000); 469 470 /* SGPRs */ 471 spr_register(env, SPR_SPRG4, "SPRG4", 472 SPR_NOACCESS, SPR_NOACCESS, 473 &spr_read_generic, &spr_write_generic, 474 0x00000000); 475 spr_register(env, SPR_SPRG5, "SPRG5", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 spr_register(env, SPR_SPRG6, "SPRG6", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 spr_register(env, SPR_SPRG7, "SPRG7", 484 SPR_NOACCESS, SPR_NOACCESS, 485 &spr_read_generic, &spr_write_generic, 486 0x00000000); 487 } 488 489 static void register_74xx_sprs(CPUPPCState *env) 490 { 491 /* Breakpoints */ 492 spr_register_kvm(env, SPR_DABR, "DABR", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 KVM_REG_PPC_DABR, 0x00000000); 496 497 spr_register(env, SPR_IABR, "IABR", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* Cache management */ 502 spr_register(env, SPR_ICTC, "ICTC", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* Performance monitors */ 507 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 512 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 517 spr_register(env, SPR_7XX_PMC1, "PMC1", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, &spr_write_generic, 520 0x00000000); 521 522 spr_register(env, SPR_7XX_PMC2, "PMC2", 523 SPR_NOACCESS, SPR_NOACCESS, 524 &spr_read_generic, &spr_write_generic, 525 0x00000000); 526 527 spr_register(env, SPR_7XX_PMC3, "PMC3", 528 SPR_NOACCESS, SPR_NOACCESS, 529 &spr_read_generic, &spr_write_generic, 530 0x00000000); 531 532 spr_register(env, SPR_7XX_PMC4, "PMC4", 533 SPR_NOACCESS, SPR_NOACCESS, 534 &spr_read_generic, &spr_write_generic, 535 0x00000000); 536 537 spr_register(env, SPR_7XX_SIAR, "SIAR", 538 SPR_NOACCESS, SPR_NOACCESS, 539 &spr_read_generic, SPR_NOACCESS, 540 0x00000000); 541 542 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 547 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 552 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 557 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 558 &spr_read_ureg, SPR_NOACCESS, 559 &spr_read_ureg, SPR_NOACCESS, 560 0x00000000); 561 562 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 563 &spr_read_ureg, SPR_NOACCESS, 564 &spr_read_ureg, SPR_NOACCESS, 565 0x00000000); 566 567 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 568 &spr_read_ureg, SPR_NOACCESS, 569 &spr_read_ureg, SPR_NOACCESS, 570 0x00000000); 571 572 spr_register(env, SPR_7XX_USIAR, "USIAR", 573 &spr_read_ureg, SPR_NOACCESS, 574 &spr_read_ureg, SPR_NOACCESS, 575 0x00000000); 576 /* External access control */ 577 spr_register(env, SPR_EAR, "EAR", 578 SPR_NOACCESS, SPR_NOACCESS, 579 &spr_read_generic, &spr_write_generic, 580 0x00000000); 581 582 /* Processor identification */ 583 spr_register(env, SPR_PIR, "PIR", 584 SPR_NOACCESS, SPR_NOACCESS, 585 &spr_read_generic, &spr_write_pir, 586 0x00000000); 587 588 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 589 SPR_NOACCESS, SPR_NOACCESS, 590 &spr_read_generic, &spr_write_generic, 591 0x00000000); 592 593 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 594 &spr_read_ureg, SPR_NOACCESS, 595 &spr_read_ureg, SPR_NOACCESS, 596 0x00000000); 597 598 spr_register(env, SPR_BAMR, "BAMR", 599 SPR_NOACCESS, SPR_NOACCESS, 600 &spr_read_generic, &spr_write_generic, 601 0x00000000); 602 603 spr_register(env, SPR_MSSCR0, "MSSCR0", 604 SPR_NOACCESS, SPR_NOACCESS, 605 &spr_read_generic, &spr_write_generic, 606 0x00000000); 607 /* Hardware implementation registers */ 608 spr_register(env, SPR_HID0, "HID0", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_generic, &spr_write_generic, 611 0x00000000); 612 613 spr_register(env, SPR_HID1, "HID1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_generic, &spr_write_generic, 616 0x00000000); 617 /* Altivec */ 618 spr_register(env, SPR_VRSAVE, "VRSAVE", 619 &spr_read_generic, &spr_write_generic, 620 &spr_read_generic, &spr_write_generic, 621 0x00000000); 622 623 spr_register(env, SPR_L2CR, "L2CR", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_generic, spr_access_nop, 626 0x00000000); 627 } 628 629 static void register_l3_ctrl(CPUPPCState *env) 630 { 631 /* L3CR */ 632 spr_register(env, SPR_L3CR, "L3CR", 633 SPR_NOACCESS, SPR_NOACCESS, 634 &spr_read_generic, &spr_write_generic, 635 0x00000000); 636 /* L3ITCR0 */ 637 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 638 SPR_NOACCESS, SPR_NOACCESS, 639 &spr_read_generic, &spr_write_generic, 640 0x00000000); 641 /* L3PM */ 642 spr_register(env, SPR_L3PM, "L3PM", 643 SPR_NOACCESS, SPR_NOACCESS, 644 &spr_read_generic, &spr_write_generic, 645 0x00000000); 646 } 647 648 /* PowerPC BookE SPR */ 649 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 650 { 651 const char *ivor_names[64] = { 652 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 653 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 654 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 655 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 656 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 657 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 658 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 659 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 660 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 661 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 662 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 663 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 664 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 665 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 666 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 667 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 668 }; 669 #define SPR_BOOKE_IVORxx (-1) 670 int ivor_sprn[64] = { 671 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 672 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 673 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 674 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 675 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 676 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 677 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 678 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 679 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 680 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 681 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 685 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 687 }; 688 int i; 689 690 /* Interrupt processing */ 691 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 692 SPR_NOACCESS, SPR_NOACCESS, 693 &spr_read_generic, &spr_write_generic, 694 0x00000000); 695 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 /* Debug */ 700 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 705 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, &spr_write_generic, 713 0x00000000); 714 715 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 720 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 721 SPR_NOACCESS, SPR_NOACCESS, 722 &spr_read_generic, &spr_write_40x_dbcr0, 723 0x00000000); 724 725 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_generic, 728 0x00000000); 729 730 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 739 SPR_NOACCESS, SPR_NOACCESS, 740 &spr_read_generic, &spr_write_generic, 741 0x00000000); 742 743 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_clear, 746 0x00000000); 747 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 748 SPR_NOACCESS, SPR_NOACCESS, 749 &spr_read_generic, &spr_write_generic, 750 0x00000000); 751 spr_register(env, SPR_BOOKE_ESR, "ESR", 752 SPR_NOACCESS, SPR_NOACCESS, 753 &spr_read_generic, &spr_write_generic, 754 0x00000000); 755 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 756 SPR_NOACCESS, SPR_NOACCESS, 757 &spr_read_generic, &spr_write_excp_prefix, 758 0x00000000); 759 /* Exception vectors */ 760 for (i = 0; i < 64; i++) { 761 if (ivor_mask & (1ULL << i)) { 762 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 763 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 764 exit(1); 765 } 766 spr_register(env, ivor_sprn[i], ivor_names[i], 767 SPR_NOACCESS, SPR_NOACCESS, 768 &spr_read_generic, &spr_write_excp_vector, 769 0x00000000); 770 } 771 } 772 spr_register(env, SPR_BOOKE_PID, "PID", 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_booke_pid, 775 0x00000000); 776 spr_register(env, SPR_BOOKE_TCR, "TCR", 777 SPR_NOACCESS, SPR_NOACCESS, 778 &spr_read_generic, &spr_write_booke_tcr, 779 0x00000000); 780 spr_register(env, SPR_BOOKE_TSR, "TSR", 781 SPR_NOACCESS, SPR_NOACCESS, 782 &spr_read_generic, &spr_write_booke_tsr, 783 0x00000000); 784 /* Timer */ 785 spr_register(env, SPR_DECR, "DECR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_decr, &spr_write_decr, 788 0x00000000); 789 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 SPR_NOACCESS, &spr_write_generic, 792 0x00000000); 793 /* SPRGs */ 794 spr_register(env, SPR_USPRG0, "USPRG0", 795 &spr_read_generic, &spr_write_generic, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 spr_register(env, SPR_SPRG4, "SPRG4", 799 SPR_NOACCESS, SPR_NOACCESS, 800 &spr_read_generic, &spr_write_generic, 801 0x00000000); 802 spr_register(env, SPR_SPRG5, "SPRG5", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 spr_register(env, SPR_SPRG6, "SPRG6", 807 SPR_NOACCESS, SPR_NOACCESS, 808 &spr_read_generic, &spr_write_generic, 809 0x00000000); 810 spr_register(env, SPR_SPRG7, "SPRG7", 811 SPR_NOACCESS, SPR_NOACCESS, 812 &spr_read_generic, &spr_write_generic, 813 0x00000000); 814 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 815 SPR_NOACCESS, SPR_NOACCESS, 816 &spr_read_generic, &spr_write_generic, 817 0x00000000); 818 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 819 SPR_NOACCESS, SPR_NOACCESS, 820 &spr_read_generic, &spr_write_generic, 821 0x00000000); 822 } 823 824 #if !defined(CONFIG_USER_ONLY) 825 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 826 uint32_t maxsize, uint32_t flags, 827 uint32_t nentries) 828 { 829 return (assoc << TLBnCFG_ASSOC_SHIFT) | 830 (minsize << TLBnCFG_MINSIZE_SHIFT) | 831 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 832 flags | nentries; 833 } 834 #endif /* !CONFIG_USER_ONLY */ 835 836 /* BookE 2.06 storage control registers */ 837 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 838 uint32_t *tlbncfg, uint32_t mmucfg) 839 { 840 #if !defined(CONFIG_USER_ONLY) 841 const char *mas_names[8] = { 842 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 843 }; 844 int mas_sprn[8] = { 845 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 846 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 847 }; 848 int i; 849 850 /* TLB assist registers */ 851 for (i = 0; i < 8; i++) { 852 if (mas_mask & (1 << i)) { 853 spr_register(env, mas_sprn[i], mas_names[i], 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_generic, 856 (i == 2 && (env->insns_flags & PPC_64B)) 857 ? &spr_write_generic : &spr_write_generic32, 858 0x00000000); 859 } 860 } 861 if (env->nb_pids > 1) { 862 spr_register(env, SPR_BOOKE_PID1, "PID1", 863 SPR_NOACCESS, SPR_NOACCESS, 864 &spr_read_generic, &spr_write_booke_pid, 865 0x00000000); 866 } 867 if (env->nb_pids > 2) { 868 spr_register(env, SPR_BOOKE_PID2, "PID2", 869 SPR_NOACCESS, SPR_NOACCESS, 870 &spr_read_generic, &spr_write_booke_pid, 871 0x00000000); 872 } 873 874 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_eplc, 877 0x00000000); 878 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 879 SPR_NOACCESS, SPR_NOACCESS, 880 &spr_read_generic, &spr_write_epsc, 881 0x00000000); 882 883 spr_register(env, SPR_MMUCFG, "MMUCFG", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, SPR_NOACCESS, 886 mmucfg); 887 switch (env->nb_ways) { 888 case 4: 889 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, SPR_NOACCESS, 892 tlbncfg[3]); 893 /* Fallthru */ 894 case 3: 895 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, SPR_NOACCESS, 898 tlbncfg[2]); 899 /* Fallthru */ 900 case 2: 901 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 902 SPR_NOACCESS, SPR_NOACCESS, 903 &spr_read_generic, SPR_NOACCESS, 904 tlbncfg[1]); 905 /* Fallthru */ 906 case 1: 907 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, SPR_NOACCESS, 910 tlbncfg[0]); 911 /* Fallthru */ 912 case 0: 913 default: 914 break; 915 } 916 #endif 917 } 918 919 /* SPR specific to PowerPC 440 implementation */ 920 static void register_440_sprs(CPUPPCState *env) 921 { 922 /* Cache control */ 923 spr_register(env, SPR_440_DNV0, "DNV0", 924 SPR_NOACCESS, SPR_NOACCESS, 925 &spr_read_generic, &spr_write_generic, 926 0x00000000); 927 928 spr_register(env, SPR_440_DNV1, "DNV1", 929 SPR_NOACCESS, SPR_NOACCESS, 930 &spr_read_generic, &spr_write_generic, 931 0x00000000); 932 933 spr_register(env, SPR_440_DNV2, "DNV2", 934 SPR_NOACCESS, SPR_NOACCESS, 935 &spr_read_generic, &spr_write_generic, 936 0x00000000); 937 938 spr_register(env, SPR_440_DNV3, "DNV3", 939 SPR_NOACCESS, SPR_NOACCESS, 940 &spr_read_generic, &spr_write_generic, 941 0x00000000); 942 943 spr_register(env, SPR_440_DTV0, "DTV0", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 948 spr_register(env, SPR_440_DTV1, "DTV1", 949 SPR_NOACCESS, SPR_NOACCESS, 950 &spr_read_generic, &spr_write_generic, 951 0x00000000); 952 953 spr_register(env, SPR_440_DTV2, "DTV2", 954 SPR_NOACCESS, SPR_NOACCESS, 955 &spr_read_generic, &spr_write_generic, 956 0x00000000); 957 958 spr_register(env, SPR_440_DTV3, "DTV3", 959 SPR_NOACCESS, SPR_NOACCESS, 960 &spr_read_generic, &spr_write_generic, 961 0x00000000); 962 963 spr_register(env, SPR_440_DVLIM, "DVLIM", 964 SPR_NOACCESS, SPR_NOACCESS, 965 &spr_read_generic, &spr_write_generic, 966 0x00000000); 967 968 spr_register(env, SPR_440_INV0, "INV0", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_generic, 971 0x00000000); 972 973 spr_register(env, SPR_440_INV1, "INV1", 974 SPR_NOACCESS, SPR_NOACCESS, 975 &spr_read_generic, &spr_write_generic, 976 0x00000000); 977 978 spr_register(env, SPR_440_INV2, "INV2", 979 SPR_NOACCESS, SPR_NOACCESS, 980 &spr_read_generic, &spr_write_generic, 981 0x00000000); 982 983 spr_register(env, SPR_440_INV3, "INV3", 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_generic, 986 0x00000000); 987 988 spr_register(env, SPR_440_ITV0, "ITV0", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_generic, &spr_write_generic, 991 0x00000000); 992 993 spr_register(env, SPR_440_ITV1, "ITV1", 994 SPR_NOACCESS, SPR_NOACCESS, 995 &spr_read_generic, &spr_write_generic, 996 0x00000000); 997 998 spr_register(env, SPR_440_ITV2, "ITV2", 999 SPR_NOACCESS, SPR_NOACCESS, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 1003 spr_register(env, SPR_440_ITV3, "ITV3", 1004 SPR_NOACCESS, SPR_NOACCESS, 1005 &spr_read_generic, &spr_write_generic, 1006 0x00000000); 1007 1008 spr_register(env, SPR_440_IVLIM, "IVLIM", 1009 SPR_NOACCESS, SPR_NOACCESS, 1010 &spr_read_generic, &spr_write_generic, 1011 0x00000000); 1012 /* Cache debug */ 1013 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1014 SPR_NOACCESS, SPR_NOACCESS, 1015 &spr_read_generic, SPR_NOACCESS, 1016 0x00000000); 1017 1018 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1019 SPR_NOACCESS, SPR_NOACCESS, 1020 &spr_read_generic, SPR_NOACCESS, 1021 0x00000000); 1022 1023 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1024 SPR_NOACCESS, SPR_NOACCESS, 1025 &spr_read_generic, SPR_NOACCESS, 1026 0x00000000); 1027 1028 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1029 SPR_NOACCESS, SPR_NOACCESS, 1030 &spr_read_generic, SPR_NOACCESS, 1031 0x00000000); 1032 1033 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1034 SPR_NOACCESS, SPR_NOACCESS, 1035 &spr_read_generic, SPR_NOACCESS, 1036 0x00000000); 1037 1038 spr_register(env, SPR_440_DBDR, "DBDR", 1039 SPR_NOACCESS, SPR_NOACCESS, 1040 &spr_read_generic, &spr_write_generic, 1041 0x00000000); 1042 /* Processor control */ 1043 spr_register(env, SPR_4xx_CCR0, "CCR0", 1044 SPR_NOACCESS, SPR_NOACCESS, 1045 &spr_read_generic, &spr_write_generic, 1046 0x00000000); 1047 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1048 SPR_NOACCESS, SPR_NOACCESS, 1049 &spr_read_generic, SPR_NOACCESS, 1050 0x00000000); 1051 /* Storage control */ 1052 spr_register(env, SPR_440_MMUCR, "MMUCR", 1053 SPR_NOACCESS, SPR_NOACCESS, 1054 &spr_read_generic, &spr_write_generic, 1055 0x00000000); 1056 1057 /* Processor identification */ 1058 spr_register(env, SPR_BOOKE_PIR, "PIR", 1059 SPR_NOACCESS, SPR_NOACCESS, 1060 &spr_read_generic, &spr_write_pir, 1061 0x00000000); 1062 1063 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1064 SPR_NOACCESS, SPR_NOACCESS, 1065 &spr_read_generic, &spr_write_generic, 1066 0x00000000); 1067 1068 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1069 SPR_NOACCESS, SPR_NOACCESS, 1070 &spr_read_generic, &spr_write_generic, 1071 0x00000000); 1072 1073 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1074 SPR_NOACCESS, SPR_NOACCESS, 1075 &spr_read_generic, &spr_write_generic, 1076 0x00000000); 1077 1078 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1079 SPR_NOACCESS, SPR_NOACCESS, 1080 &spr_read_generic, &spr_write_generic, 1081 0x00000000); 1082 } 1083 1084 /* SPR shared between PowerPC 40x implementations */ 1085 static void register_40x_sprs(CPUPPCState *env) 1086 { 1087 /* Cache */ 1088 /* not emulated, as QEMU do not emulate caches */ 1089 spr_register(env, SPR_40x_DCCR, "DCCR", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, &spr_write_generic, 1092 0x00000000); 1093 /* not emulated, as QEMU do not emulate caches */ 1094 spr_register(env, SPR_40x_ICCR, "ICCR", 1095 SPR_NOACCESS, SPR_NOACCESS, 1096 &spr_read_generic, &spr_write_generic, 1097 0x00000000); 1098 /* not emulated, as QEMU do not emulate caches */ 1099 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1100 SPR_NOACCESS, SPR_NOACCESS, 1101 &spr_read_generic, SPR_NOACCESS, 1102 0x00000000); 1103 /* Exception */ 1104 spr_register(env, SPR_40x_DEAR, "DEAR", 1105 SPR_NOACCESS, SPR_NOACCESS, 1106 &spr_read_generic, &spr_write_generic, 1107 0x00000000); 1108 spr_register(env, SPR_40x_ESR, "ESR", 1109 SPR_NOACCESS, SPR_NOACCESS, 1110 &spr_read_generic, &spr_write_generic, 1111 0x00000000); 1112 spr_register(env, SPR_40x_EVPR, "EVPR", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_excp_prefix, 1115 0x00000000); 1116 spr_register(env, SPR_40x_SRR2, "SRR2", 1117 &spr_read_generic, &spr_write_generic, 1118 &spr_read_generic, &spr_write_generic, 1119 0x00000000); 1120 spr_register(env, SPR_40x_SRR3, "SRR3", 1121 &spr_read_generic, &spr_write_generic, 1122 &spr_read_generic, &spr_write_generic, 1123 0x00000000); 1124 /* Timers */ 1125 spr_register(env, SPR_40x_PIT, "PIT", 1126 SPR_NOACCESS, SPR_NOACCESS, 1127 &spr_read_40x_pit, &spr_write_40x_pit, 1128 0x00000000); 1129 spr_register(env, SPR_40x_TCR, "TCR", 1130 SPR_NOACCESS, SPR_NOACCESS, 1131 &spr_read_generic, &spr_write_40x_tcr, 1132 0x00000000); 1133 spr_register(env, SPR_40x_TSR, "TSR", 1134 SPR_NOACCESS, SPR_NOACCESS, 1135 &spr_read_generic, &spr_write_40x_tsr, 1136 0x00000000); 1137 } 1138 1139 /* SPR specific to PowerPC 405 implementation */ 1140 static void register_405_sprs(CPUPPCState *env) 1141 { 1142 /* MMU */ 1143 spr_register(env, SPR_40x_PID, "PID", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_generic, &spr_write_40x_pid, 1146 0x00000000); 1147 spr_register(env, SPR_4xx_CCR0, "CCR0", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00700000); 1151 /* Debug interface */ 1152 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_40x_dbcr0, 1155 0x00000000); 1156 1157 spr_register(env, SPR_405_DBCR1, "DBCR1", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 1162 spr_register(env, SPR_40x_DBSR, "DBSR", 1163 SPR_NOACCESS, SPR_NOACCESS, 1164 &spr_read_generic, &spr_write_clear, 1165 /* Last reset was system reset */ 1166 0x00000300); 1167 1168 spr_register(env, SPR_40x_DAC1, "DAC1", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 spr_register(env, SPR_40x_DAC2, "DAC2", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 1177 spr_register(env, SPR_405_DVC1, "DVC1", 1178 SPR_NOACCESS, SPR_NOACCESS, 1179 &spr_read_generic, &spr_write_generic, 1180 0x00000000); 1181 1182 spr_register(env, SPR_405_DVC2, "DVC2", 1183 SPR_NOACCESS, SPR_NOACCESS, 1184 &spr_read_generic, &spr_write_generic, 1185 0x00000000); 1186 1187 spr_register(env, SPR_40x_IAC1, "IAC1", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, &spr_write_generic, 1190 0x00000000); 1191 spr_register(env, SPR_40x_IAC2, "IAC2", 1192 SPR_NOACCESS, SPR_NOACCESS, 1193 &spr_read_generic, &spr_write_generic, 1194 0x00000000); 1195 1196 spr_register(env, SPR_405_IAC3, "IAC3", 1197 SPR_NOACCESS, SPR_NOACCESS, 1198 &spr_read_generic, &spr_write_generic, 1199 0x00000000); 1200 1201 spr_register(env, SPR_405_IAC4, "IAC4", 1202 SPR_NOACCESS, SPR_NOACCESS, 1203 &spr_read_generic, &spr_write_generic, 1204 0x00000000); 1205 /* Storage control */ 1206 spr_register(env, SPR_405_SLER, "SLER", 1207 SPR_NOACCESS, SPR_NOACCESS, 1208 &spr_read_generic, &spr_write_40x_sler, 1209 0x00000000); 1210 spr_register(env, SPR_40x_ZPR, "ZPR", 1211 SPR_NOACCESS, SPR_NOACCESS, 1212 &spr_read_generic, &spr_write_generic, 1213 0x00000000); 1214 1215 spr_register(env, SPR_405_SU0R, "SU0R", 1216 SPR_NOACCESS, SPR_NOACCESS, 1217 &spr_read_generic, &spr_write_generic, 1218 0x00000000); 1219 /* SPRG */ 1220 spr_register(env, SPR_USPRG0, "USPRG0", 1221 &spr_read_ureg, SPR_NOACCESS, 1222 &spr_read_ureg, SPR_NOACCESS, 1223 0x00000000); 1224 spr_register(env, SPR_SPRG4, "SPRG4", 1225 SPR_NOACCESS, SPR_NOACCESS, 1226 &spr_read_generic, &spr_write_generic, 1227 0x00000000); 1228 spr_register(env, SPR_SPRG5, "SPRG5", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 spr_register(env, SPR_SPRG6, "SPRG6", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 spr_read_generic, &spr_write_generic, 1235 0x00000000); 1236 spr_register(env, SPR_SPRG7, "SPRG7", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 spr_read_generic, &spr_write_generic, 1239 0x00000000); 1240 1241 /* Bus access control */ 1242 /* not emulated, as QEMU never does speculative access */ 1243 spr_register(env, SPR_40x_SGR, "SGR", 1244 SPR_NOACCESS, SPR_NOACCESS, 1245 &spr_read_generic, &spr_write_generic, 1246 0xFFFFFFFF); 1247 /* not emulated, as QEMU do not emulate caches */ 1248 spr_register(env, SPR_40x_DCWR, "DCWR", 1249 SPR_NOACCESS, SPR_NOACCESS, 1250 &spr_read_generic, &spr_write_generic, 1251 0x00000000); 1252 } 1253 1254 1255 static void register_5xx_8xx_sprs(CPUPPCState *env) 1256 { 1257 /* Exception processing */ 1258 spr_register_kvm(env, SPR_DSISR, "DSISR", 1259 SPR_NOACCESS, SPR_NOACCESS, 1260 &spr_read_generic, &spr_write_generic, 1261 KVM_REG_PPC_DSISR, 0x00000000); 1262 spr_register_kvm(env, SPR_DAR, "DAR", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 KVM_REG_PPC_DAR, 0x00000000); 1266 /* Timer */ 1267 spr_register(env, SPR_DECR, "DECR", 1268 SPR_NOACCESS, SPR_NOACCESS, 1269 &spr_read_decr, &spr_write_decr, 1270 0x00000000); 1271 1272 spr_register(env, SPR_MPC_EIE, "EIE", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_generic, &spr_write_generic, 1275 0x00000000); 1276 1277 spr_register(env, SPR_MPC_EID, "EID", 1278 SPR_NOACCESS, SPR_NOACCESS, 1279 &spr_read_generic, &spr_write_generic, 1280 0x00000000); 1281 1282 spr_register(env, SPR_MPC_NRI, "NRI", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 1287 spr_register(env, SPR_MPC_CMPA, "CMPA", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, &spr_write_generic, 1290 0x00000000); 1291 1292 spr_register(env, SPR_MPC_CMPB, "CMPB", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, &spr_write_generic, 1295 0x00000000); 1296 1297 spr_register(env, SPR_MPC_CMPC, "CMPC", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 1302 spr_register(env, SPR_MPC_CMPD, "CMPD", 1303 SPR_NOACCESS, SPR_NOACCESS, 1304 &spr_read_generic, &spr_write_generic, 1305 0x00000000); 1306 1307 spr_register(env, SPR_MPC_ECR, "ECR", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, &spr_write_generic, 1310 0x00000000); 1311 1312 spr_register(env, SPR_MPC_DER, "DER", 1313 SPR_NOACCESS, SPR_NOACCESS, 1314 &spr_read_generic, &spr_write_generic, 1315 0x00000000); 1316 1317 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1318 SPR_NOACCESS, SPR_NOACCESS, 1319 &spr_read_generic, &spr_write_generic, 1320 0x00000000); 1321 1322 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1323 SPR_NOACCESS, SPR_NOACCESS, 1324 &spr_read_generic, &spr_write_generic, 1325 0x00000000); 1326 1327 spr_register(env, SPR_MPC_CMPE, "CMPE", 1328 SPR_NOACCESS, SPR_NOACCESS, 1329 &spr_read_generic, &spr_write_generic, 1330 0x00000000); 1331 1332 spr_register(env, SPR_MPC_CMPF, "CMPF", 1333 SPR_NOACCESS, SPR_NOACCESS, 1334 &spr_read_generic, &spr_write_generic, 1335 0x00000000); 1336 1337 spr_register(env, SPR_MPC_CMPG, "CMPG", 1338 SPR_NOACCESS, SPR_NOACCESS, 1339 &spr_read_generic, &spr_write_generic, 1340 0x00000000); 1341 1342 spr_register(env, SPR_MPC_CMPH, "CMPH", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, &spr_write_generic, 1345 0x00000000); 1346 1347 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1348 SPR_NOACCESS, SPR_NOACCESS, 1349 &spr_read_generic, &spr_write_generic, 1350 0x00000000); 1351 1352 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1353 SPR_NOACCESS, SPR_NOACCESS, 1354 &spr_read_generic, &spr_write_generic, 1355 0x00000000); 1356 1357 spr_register(env, SPR_MPC_BAR, "BAR", 1358 SPR_NOACCESS, SPR_NOACCESS, 1359 &spr_read_generic, &spr_write_generic, 1360 0x00000000); 1361 1362 spr_register(env, SPR_MPC_DPDR, "DPDR", 1363 SPR_NOACCESS, SPR_NOACCESS, 1364 &spr_read_generic, &spr_write_generic, 1365 0x00000000); 1366 1367 spr_register(env, SPR_MPC_IMMR, "IMMR", 1368 SPR_NOACCESS, SPR_NOACCESS, 1369 &spr_read_generic, &spr_write_generic, 1370 0x00000000); 1371 } 1372 1373 static void register_5xx_sprs(CPUPPCState *env) 1374 { 1375 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 1380 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 1385 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, &spr_write_generic, 1388 0x00000000); 1389 1390 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_generic, &spr_write_generic, 1393 0x00000000); 1394 1395 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1396 SPR_NOACCESS, SPR_NOACCESS, 1397 &spr_read_generic, &spr_write_generic, 1398 0x00000000); 1399 1400 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 &spr_read_generic, &spr_write_generic, 1403 0x00000000); 1404 1405 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1406 SPR_NOACCESS, SPR_NOACCESS, 1407 &spr_read_generic, &spr_write_generic, 1408 0x00000000); 1409 1410 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, &spr_write_generic, 1413 0x00000000); 1414 1415 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 0x00000000); 1419 1420 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 1425 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 &spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 1430 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1431 SPR_NOACCESS, SPR_NOACCESS, 1432 &spr_read_generic, &spr_write_generic, 1433 0x00000000); 1434 1435 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1436 SPR_NOACCESS, SPR_NOACCESS, 1437 &spr_read_generic, &spr_write_generic, 1438 0x00000000); 1439 1440 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 0x00000000); 1444 1445 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 1450 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 0x00000000); 1454 1455 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 1460 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 1465 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_generic, 1468 0x00000000); 1469 1470 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_generic, 1478 0x00000000); 1479 } 1480 1481 static void register_8xx_sprs(CPUPPCState *env) 1482 { 1483 1484 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, &spr_write_generic, 1487 0x00000000); 1488 1489 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 1494 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 1499 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, &spr_write_generic, 1502 0x00000000); 1503 1504 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 1509 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 1514 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_generic, 1517 0x00000000); 1518 1519 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1520 SPR_NOACCESS, SPR_NOACCESS, 1521 &spr_read_generic, &spr_write_generic, 1522 0x00000000); 1523 1524 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 1529 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 1534 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 1539 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 1544 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1545 SPR_NOACCESS, SPR_NOACCESS, 1546 &spr_read_generic, &spr_write_generic, 1547 0x00000000); 1548 1549 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 1554 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1555 SPR_NOACCESS, SPR_NOACCESS, 1556 &spr_read_generic, &spr_write_generic, 1557 0x00000000); 1558 1559 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1560 SPR_NOACCESS, SPR_NOACCESS, 1561 &spr_read_generic, &spr_write_generic, 1562 0x00000000); 1563 1564 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1565 SPR_NOACCESS, SPR_NOACCESS, 1566 &spr_read_generic, &spr_write_generic, 1567 0x00000000); 1568 1569 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1570 SPR_NOACCESS, SPR_NOACCESS, 1571 &spr_read_generic, &spr_write_generic, 1572 0x00000000); 1573 1574 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1575 SPR_NOACCESS, SPR_NOACCESS, 1576 &spr_read_generic, &spr_write_generic, 1577 0x00000000); 1578 1579 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1580 SPR_NOACCESS, SPR_NOACCESS, 1581 &spr_read_generic, &spr_write_generic, 1582 0x00000000); 1583 1584 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1585 SPR_NOACCESS, SPR_NOACCESS, 1586 &spr_read_generic, &spr_write_generic, 1587 0x00000000); 1588 1589 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1590 SPR_NOACCESS, SPR_NOACCESS, 1591 &spr_read_generic, &spr_write_generic, 1592 0x00000000); 1593 1594 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1595 SPR_NOACCESS, SPR_NOACCESS, 1596 &spr_read_generic, &spr_write_generic, 1597 0x00000000); 1598 1599 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1600 SPR_NOACCESS, SPR_NOACCESS, 1601 &spr_read_generic, &spr_write_generic, 1602 0x00000000); 1603 1604 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1605 SPR_NOACCESS, SPR_NOACCESS, 1606 &spr_read_generic, &spr_write_generic, 1607 0x00000000); 1608 } 1609 1610 /* 1611 * AMR => SPR 29 (Power 2.04) 1612 * CTRL => SPR 136 (Power 2.04) 1613 * CTRL => SPR 152 (Power 2.04) 1614 * SCOMC => SPR 276 (64 bits ?) 1615 * SCOMD => SPR 277 (64 bits ?) 1616 * TBU40 => SPR 286 (Power 2.04 hypv) 1617 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1618 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1619 * HDSISR => SPR 306 (Power 2.04 hypv) 1620 * HDAR => SPR 307 (Power 2.04 hypv) 1621 * PURR => SPR 309 (Power 2.04 hypv) 1622 * HDEC => SPR 310 (Power 2.04 hypv) 1623 * HIOR => SPR 311 (hypv) 1624 * RMOR => SPR 312 (970) 1625 * HRMOR => SPR 313 (Power 2.04 hypv) 1626 * HSRR0 => SPR 314 (Power 2.04 hypv) 1627 * HSRR1 => SPR 315 (Power 2.04 hypv) 1628 * LPIDR => SPR 317 (970) 1629 * EPR => SPR 702 (Power 2.04 emb) 1630 * perf => 768-783 (Power 2.04) 1631 * perf => 784-799 (Power 2.04) 1632 * PPR => SPR 896 (Power 2.04) 1633 * DABRX => 1015 (Power 2.04 hypv) 1634 * FPECR => SPR 1022 (?) 1635 * ... and more (thermal management, performance counters, ...) 1636 */ 1637 1638 /*****************************************************************************/ 1639 /* Exception vectors models */ 1640 static void init_excp_4xx_softmmu(CPUPPCState *env) 1641 { 1642 #if !defined(CONFIG_USER_ONLY) 1643 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1644 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1645 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1646 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1647 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1648 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1649 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1650 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1651 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1652 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1653 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1654 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1655 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1656 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1657 env->ivor_mask = 0x0000FFF0UL; 1658 env->ivpr_mask = 0xFFFF0000UL; 1659 /* Hardware reset vector */ 1660 env->hreset_vector = 0xFFFFFFFCUL; 1661 #endif 1662 } 1663 1664 static void init_excp_MPC5xx(CPUPPCState *env) 1665 { 1666 #if !defined(CONFIG_USER_ONLY) 1667 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1668 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1669 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1670 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1671 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1672 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1673 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1674 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1675 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1676 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1677 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1678 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1679 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1680 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1681 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1682 env->ivor_mask = 0x0000FFF0UL; 1683 env->ivpr_mask = 0xFFFF0000UL; 1684 /* Hardware reset vector */ 1685 env->hreset_vector = 0x00000100UL; 1686 #endif 1687 } 1688 1689 static void init_excp_MPC8xx(CPUPPCState *env) 1690 { 1691 #if !defined(CONFIG_USER_ONLY) 1692 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1693 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1694 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1695 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1696 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1697 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1698 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1699 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1700 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1701 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1702 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1703 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1704 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1705 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1706 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1707 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1708 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1709 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1710 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1711 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1712 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1713 env->ivor_mask = 0x0000FFF0UL; 1714 env->ivpr_mask = 0xFFFF0000UL; 1715 /* Hardware reset vector */ 1716 env->hreset_vector = 0x00000100UL; 1717 #endif 1718 } 1719 1720 static void init_excp_G2(CPUPPCState *env) 1721 { 1722 #if !defined(CONFIG_USER_ONLY) 1723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1725 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1726 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1732 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1734 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1735 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1736 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1737 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1739 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1740 /* Hardware reset vector */ 1741 env->hreset_vector = 0x00000100UL; 1742 #endif 1743 } 1744 1745 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1746 { 1747 #if !defined(CONFIG_USER_ONLY) 1748 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1749 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1750 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1751 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1752 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1757 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1758 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1760 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1761 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1762 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1763 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1764 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1765 /* 1766 * These two are the same IVOR as POWERPC_EXCP_VPU and 1767 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1768 * powerpc_excp(). 1769 */ 1770 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1771 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1772 1773 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1774 env->ivor_mask = 0x0000FFF7UL; 1775 env->ivpr_mask = ivpr_mask; 1776 /* Hardware reset vector */ 1777 env->hreset_vector = 0xFFFFFFFCUL; 1778 #endif 1779 } 1780 1781 static void init_excp_BookE(CPUPPCState *env) 1782 { 1783 #if !defined(CONFIG_USER_ONLY) 1784 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1787 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1788 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1789 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1790 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1791 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1792 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1793 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1794 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1795 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1796 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1797 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1798 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1799 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1800 env->ivor_mask = 0x0000FFF0UL; 1801 env->ivpr_mask = 0xFFFF0000UL; 1802 /* Hardware reset vector */ 1803 env->hreset_vector = 0xFFFFFFFCUL; 1804 #endif 1805 } 1806 1807 static void init_excp_603(CPUPPCState *env) 1808 { 1809 #if !defined(CONFIG_USER_ONLY) 1810 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1818 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1820 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1821 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1822 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1823 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1824 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1825 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1826 /* Hardware reset vector */ 1827 env->hreset_vector = 0x00000100UL; 1828 #endif 1829 } 1830 1831 static void init_excp_604(CPUPPCState *env) 1832 { 1833 #if !defined(CONFIG_USER_ONLY) 1834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1835 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1836 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1837 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1838 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1839 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1840 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1841 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1842 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1844 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1845 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1846 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1847 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1848 /* Hardware reset vector */ 1849 env->hreset_vector = 0x00000100UL; 1850 #endif 1851 } 1852 1853 static void init_excp_7x0(CPUPPCState *env) 1854 { 1855 #if !defined(CONFIG_USER_ONLY) 1856 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1857 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1858 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1859 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1860 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1861 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1862 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1863 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1864 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1865 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1866 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1867 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1868 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1869 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1870 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1871 /* Hardware reset vector */ 1872 env->hreset_vector = 0x00000100UL; 1873 #endif 1874 } 1875 1876 static void init_excp_750cl(CPUPPCState *env) 1877 { 1878 #if !defined(CONFIG_USER_ONLY) 1879 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1880 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1881 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1882 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1883 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1884 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1885 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1886 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1887 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1888 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1889 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1890 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1893 /* Hardware reset vector */ 1894 env->hreset_vector = 0x00000100UL; 1895 #endif 1896 } 1897 1898 static void init_excp_750cx(CPUPPCState *env) 1899 { 1900 #if !defined(CONFIG_USER_ONLY) 1901 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1902 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1903 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1904 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1905 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1906 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1907 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1908 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1909 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1910 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1911 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1912 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1913 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1914 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1915 /* Hardware reset vector */ 1916 env->hreset_vector = 0x00000100UL; 1917 #endif 1918 } 1919 1920 /* XXX: Check if this is correct */ 1921 static void init_excp_7x5(CPUPPCState *env) 1922 { 1923 #if !defined(CONFIG_USER_ONLY) 1924 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1925 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1926 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1927 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1928 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1929 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1930 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1931 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1932 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1933 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1934 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1935 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1936 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1937 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1938 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1939 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1940 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1941 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1942 /* Hardware reset vector */ 1943 env->hreset_vector = 0x00000100UL; 1944 #endif 1945 } 1946 1947 static void init_excp_7400(CPUPPCState *env) 1948 { 1949 #if !defined(CONFIG_USER_ONLY) 1950 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1951 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1952 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1953 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1954 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1955 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1956 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1957 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1958 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1959 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1960 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1961 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1962 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1963 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1964 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1965 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1966 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1967 /* Hardware reset vector */ 1968 env->hreset_vector = 0x00000100UL; 1969 #endif 1970 } 1971 1972 static void init_excp_7450(CPUPPCState *env) 1973 { 1974 #if !defined(CONFIG_USER_ONLY) 1975 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1976 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1977 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1978 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1979 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1980 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1981 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1982 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1983 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1984 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1985 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1986 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1987 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1988 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1989 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1990 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1991 /* Hardware reset vector */ 1992 env->hreset_vector = 0x00000100UL; 1993 #endif 1994 } 1995 1996 #if defined(TARGET_PPC64) 1997 static void init_excp_970(CPUPPCState *env) 1998 { 1999 #if !defined(CONFIG_USER_ONLY) 2000 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2001 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2002 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2003 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2004 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2005 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2006 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2007 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2008 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2009 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2010 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2011 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2012 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2013 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2014 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2015 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2016 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2017 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2018 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2019 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2020 /* Hardware reset vector */ 2021 env->hreset_vector = 0x0000000000000100ULL; 2022 #endif 2023 } 2024 2025 static void init_excp_POWER7(CPUPPCState *env) 2026 { 2027 #if !defined(CONFIG_USER_ONLY) 2028 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2029 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2030 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2031 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2032 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2033 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2034 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2035 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2036 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2037 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2038 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2039 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2040 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2041 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2042 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2043 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2044 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2045 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2046 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2047 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2048 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2049 /* Hardware reset vector */ 2050 env->hreset_vector = 0x0000000000000100ULL; 2051 #endif 2052 } 2053 2054 static void init_excp_POWER8(CPUPPCState *env) 2055 { 2056 init_excp_POWER7(env); 2057 2058 #if !defined(CONFIG_USER_ONLY) 2059 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2060 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2061 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2062 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2063 #endif 2064 } 2065 2066 static void init_excp_POWER9(CPUPPCState *env) 2067 { 2068 init_excp_POWER8(env); 2069 2070 #if !defined(CONFIG_USER_ONLY) 2071 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2072 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2073 #endif 2074 } 2075 2076 static void init_excp_POWER10(CPUPPCState *env) 2077 { 2078 init_excp_POWER9(env); 2079 } 2080 2081 #endif 2082 2083 static int check_pow_hid0(CPUPPCState *env) 2084 { 2085 if (env->spr[SPR_HID0] & 0x00E00000) { 2086 return 1; 2087 } 2088 2089 return 0; 2090 } 2091 2092 static int check_pow_hid0_74xx(CPUPPCState *env) 2093 { 2094 if (env->spr[SPR_HID0] & 0x00600000) { 2095 return 1; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static void init_proc_405(CPUPPCState *env) 2102 { 2103 register_40x_sprs(env); 2104 register_405_sprs(env); 2105 register_usprgh_sprs(env); 2106 2107 /* Memory management */ 2108 #if !defined(CONFIG_USER_ONLY) 2109 env->nb_tlb = 64; 2110 env->nb_ways = 1; 2111 env->id_tlbs = 0; 2112 env->tlb_type = TLB_EMB; 2113 #endif 2114 init_excp_4xx_softmmu(env); 2115 env->dcache_line_size = 32; 2116 env->icache_line_size = 32; 2117 /* Allocate hardware IRQ controller */ 2118 ppc40x_irq_init(env_archcpu(env)); 2119 2120 SET_FIT_PERIOD(8, 12, 16, 20); 2121 SET_WDT_PERIOD(16, 20, 24, 28); 2122 } 2123 2124 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2125 { 2126 DeviceClass *dc = DEVICE_CLASS(oc); 2127 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2128 2129 dc->desc = "PowerPC 405"; 2130 pcc->init_proc = init_proc_405; 2131 pcc->check_pow = check_pow_nocheck; 2132 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2133 PPC_DCR | PPC_WRTEE | 2134 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2135 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2136 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2137 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2138 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2139 pcc->msr_mask = (1ull << MSR_WE) | 2140 (1ull << MSR_CE) | 2141 (1ull << MSR_EE) | 2142 (1ull << MSR_PR) | 2143 (1ull << MSR_FP) | 2144 (1ull << MSR_ME) | 2145 (1ull << MSR_DWE) | 2146 (1ull << MSR_DE) | 2147 (1ull << MSR_IR) | 2148 (1ull << MSR_DR); 2149 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2150 pcc->excp_model = POWERPC_EXCP_40x; 2151 pcc->bus_model = PPC_FLAGS_INPUT_405; 2152 pcc->bfd_mach = bfd_mach_ppc_403; 2153 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2154 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2155 } 2156 2157 static void init_proc_440EP(CPUPPCState *env) 2158 { 2159 register_BookE_sprs(env, 0x000000000000FFFFULL); 2160 register_440_sprs(env); 2161 register_usprgh_sprs(env); 2162 2163 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2164 SPR_NOACCESS, SPR_NOACCESS, 2165 &spr_read_generic, &spr_write_generic, 2166 0x00000000); 2167 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2168 SPR_NOACCESS, SPR_NOACCESS, 2169 &spr_read_generic, &spr_write_generic, 2170 0x00000000); 2171 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2172 SPR_NOACCESS, SPR_NOACCESS, 2173 &spr_read_generic, &spr_write_generic, 2174 0x00000000); 2175 2176 spr_register(env, SPR_440_CCR1, "CCR1", 2177 SPR_NOACCESS, SPR_NOACCESS, 2178 &spr_read_generic, &spr_write_generic, 2179 0x00000000); 2180 /* Memory management */ 2181 #if !defined(CONFIG_USER_ONLY) 2182 env->nb_tlb = 64; 2183 env->nb_ways = 1; 2184 env->id_tlbs = 0; 2185 env->tlb_type = TLB_EMB; 2186 #endif 2187 init_excp_BookE(env); 2188 env->dcache_line_size = 32; 2189 env->icache_line_size = 32; 2190 ppc40x_irq_init(env_archcpu(env)); 2191 2192 SET_FIT_PERIOD(12, 16, 20, 24); 2193 SET_WDT_PERIOD(20, 24, 28, 32); 2194 } 2195 2196 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2197 { 2198 DeviceClass *dc = DEVICE_CLASS(oc); 2199 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2200 2201 dc->desc = "PowerPC 440 EP"; 2202 pcc->init_proc = init_proc_440EP; 2203 pcc->check_pow = check_pow_nocheck; 2204 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2205 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2206 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2207 PPC_FLOAT_STFIWX | 2208 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2209 PPC_CACHE | PPC_CACHE_ICBI | 2210 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2211 PPC_MEM_TLBSYNC | PPC_MFTB | 2212 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2213 PPC_440_SPEC; 2214 pcc->msr_mask = (1ull << MSR_POW) | 2215 (1ull << MSR_CE) | 2216 (1ull << MSR_EE) | 2217 (1ull << MSR_PR) | 2218 (1ull << MSR_FP) | 2219 (1ull << MSR_ME) | 2220 (1ull << MSR_FE0) | 2221 (1ull << MSR_DWE) | 2222 (1ull << MSR_DE) | 2223 (1ull << MSR_FE1) | 2224 (1ull << MSR_IR) | 2225 (1ull << MSR_DR); 2226 pcc->mmu_model = POWERPC_MMU_BOOKE; 2227 pcc->excp_model = POWERPC_EXCP_BOOKE; 2228 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2229 pcc->bfd_mach = bfd_mach_ppc_403; 2230 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2231 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2232 } 2233 2234 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2235 { 2236 DeviceClass *dc = DEVICE_CLASS(oc); 2237 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2238 2239 dc->desc = "PowerPC 460 EX"; 2240 pcc->init_proc = init_proc_440EP; 2241 pcc->check_pow = check_pow_nocheck; 2242 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2243 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2244 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2245 PPC_FLOAT_STFIWX | 2246 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2247 PPC_CACHE | PPC_CACHE_ICBI | 2248 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2249 PPC_MEM_TLBSYNC | PPC_MFTB | 2250 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2251 PPC_440_SPEC; 2252 pcc->msr_mask = (1ull << MSR_POW) | 2253 (1ull << MSR_CE) | 2254 (1ull << MSR_EE) | 2255 (1ull << MSR_PR) | 2256 (1ull << MSR_FP) | 2257 (1ull << MSR_ME) | 2258 (1ull << MSR_FE0) | 2259 (1ull << MSR_DWE) | 2260 (1ull << MSR_DE) | 2261 (1ull << MSR_FE1) | 2262 (1ull << MSR_IR) | 2263 (1ull << MSR_DR); 2264 pcc->mmu_model = POWERPC_MMU_BOOKE; 2265 pcc->excp_model = POWERPC_EXCP_BOOKE; 2266 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2267 pcc->bfd_mach = bfd_mach_ppc_403; 2268 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2269 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2270 } 2271 2272 static void init_proc_440GP(CPUPPCState *env) 2273 { 2274 register_BookE_sprs(env, 0x000000000000FFFFULL); 2275 register_440_sprs(env); 2276 register_usprgh_sprs(env); 2277 2278 /* Memory management */ 2279 #if !defined(CONFIG_USER_ONLY) 2280 env->nb_tlb = 64; 2281 env->nb_ways = 1; 2282 env->id_tlbs = 0; 2283 env->tlb_type = TLB_EMB; 2284 #endif 2285 init_excp_BookE(env); 2286 env->dcache_line_size = 32; 2287 env->icache_line_size = 32; 2288 /* XXX: TODO: allocate internal IRQ controller */ 2289 2290 SET_FIT_PERIOD(12, 16, 20, 24); 2291 SET_WDT_PERIOD(20, 24, 28, 32); 2292 } 2293 2294 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2295 { 2296 DeviceClass *dc = DEVICE_CLASS(oc); 2297 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2298 2299 dc->desc = "PowerPC 440 GP"; 2300 pcc->init_proc = init_proc_440GP; 2301 pcc->check_pow = check_pow_nocheck; 2302 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2303 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2304 PPC_CACHE | PPC_CACHE_ICBI | 2305 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2306 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2307 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2308 PPC_440_SPEC; 2309 pcc->msr_mask = (1ull << MSR_POW) | 2310 (1ull << MSR_CE) | 2311 (1ull << MSR_EE) | 2312 (1ull << MSR_PR) | 2313 (1ull << MSR_FP) | 2314 (1ull << MSR_ME) | 2315 (1ull << MSR_FE0) | 2316 (1ull << MSR_DWE) | 2317 (1ull << MSR_DE) | 2318 (1ull << MSR_FE1) | 2319 (1ull << MSR_IR) | 2320 (1ull << MSR_DR); 2321 pcc->mmu_model = POWERPC_MMU_BOOKE; 2322 pcc->excp_model = POWERPC_EXCP_BOOKE; 2323 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2324 pcc->bfd_mach = bfd_mach_ppc_403; 2325 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2326 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2327 } 2328 2329 static void init_proc_440x5(CPUPPCState *env) 2330 { 2331 register_BookE_sprs(env, 0x000000000000FFFFULL); 2332 register_440_sprs(env); 2333 register_usprgh_sprs(env); 2334 2335 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2336 SPR_NOACCESS, SPR_NOACCESS, 2337 &spr_read_generic, &spr_write_generic, 2338 0x00000000); 2339 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2340 SPR_NOACCESS, SPR_NOACCESS, 2341 &spr_read_generic, &spr_write_generic, 2342 0x00000000); 2343 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2344 SPR_NOACCESS, SPR_NOACCESS, 2345 &spr_read_generic, &spr_write_generic, 2346 0x00000000); 2347 2348 spr_register(env, SPR_440_CCR1, "CCR1", 2349 SPR_NOACCESS, SPR_NOACCESS, 2350 &spr_read_generic, &spr_write_generic, 2351 0x00000000); 2352 /* Memory management */ 2353 #if !defined(CONFIG_USER_ONLY) 2354 env->nb_tlb = 64; 2355 env->nb_ways = 1; 2356 env->id_tlbs = 0; 2357 env->tlb_type = TLB_EMB; 2358 #endif 2359 init_excp_BookE(env); 2360 env->dcache_line_size = 32; 2361 env->icache_line_size = 32; 2362 ppc40x_irq_init(env_archcpu(env)); 2363 2364 SET_FIT_PERIOD(12, 16, 20, 24); 2365 SET_WDT_PERIOD(20, 24, 28, 32); 2366 } 2367 2368 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2369 { 2370 DeviceClass *dc = DEVICE_CLASS(oc); 2371 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2372 2373 dc->desc = "PowerPC 440x5"; 2374 pcc->init_proc = init_proc_440x5; 2375 pcc->check_pow = check_pow_nocheck; 2376 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2377 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2378 PPC_CACHE | PPC_CACHE_ICBI | 2379 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2380 PPC_MEM_TLBSYNC | PPC_MFTB | 2381 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2382 PPC_440_SPEC; 2383 pcc->msr_mask = (1ull << MSR_POW) | 2384 (1ull << MSR_CE) | 2385 (1ull << MSR_EE) | 2386 (1ull << MSR_PR) | 2387 (1ull << MSR_FP) | 2388 (1ull << MSR_ME) | 2389 (1ull << MSR_FE0) | 2390 (1ull << MSR_DWE) | 2391 (1ull << MSR_DE) | 2392 (1ull << MSR_FE1) | 2393 (1ull << MSR_IR) | 2394 (1ull << MSR_DR); 2395 pcc->mmu_model = POWERPC_MMU_BOOKE; 2396 pcc->excp_model = POWERPC_EXCP_BOOKE; 2397 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2398 pcc->bfd_mach = bfd_mach_ppc_403; 2399 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2400 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2401 } 2402 2403 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2404 { 2405 DeviceClass *dc = DEVICE_CLASS(oc); 2406 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2407 2408 dc->desc = "PowerPC 440x5 with double precision FPU"; 2409 pcc->init_proc = init_proc_440x5; 2410 pcc->check_pow = check_pow_nocheck; 2411 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2412 PPC_FLOAT | PPC_FLOAT_FSQRT | 2413 PPC_FLOAT_STFIWX | 2414 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2415 PPC_CACHE | PPC_CACHE_ICBI | 2416 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2417 PPC_MEM_TLBSYNC | PPC_MFTB | 2418 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2419 PPC_440_SPEC; 2420 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2421 pcc->msr_mask = (1ull << MSR_POW) | 2422 (1ull << MSR_CE) | 2423 (1ull << MSR_EE) | 2424 (1ull << MSR_PR) | 2425 (1ull << MSR_FP) | 2426 (1ull << MSR_ME) | 2427 (1ull << MSR_FE0) | 2428 (1ull << MSR_DWE) | 2429 (1ull << MSR_DE) | 2430 (1ull << MSR_FE1) | 2431 (1ull << MSR_IR) | 2432 (1ull << MSR_DR); 2433 pcc->mmu_model = POWERPC_MMU_BOOKE; 2434 pcc->excp_model = POWERPC_EXCP_BOOKE; 2435 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2436 pcc->bfd_mach = bfd_mach_ppc_403; 2437 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2438 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2439 } 2440 2441 static void init_proc_MPC5xx(CPUPPCState *env) 2442 { 2443 register_5xx_8xx_sprs(env); 2444 register_5xx_sprs(env); 2445 init_excp_MPC5xx(env); 2446 env->dcache_line_size = 32; 2447 env->icache_line_size = 32; 2448 /* XXX: TODO: allocate internal IRQ controller */ 2449 } 2450 2451 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2452 { 2453 DeviceClass *dc = DEVICE_CLASS(oc); 2454 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2455 2456 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2457 pcc->init_proc = init_proc_MPC5xx; 2458 pcc->check_pow = check_pow_none; 2459 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2460 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2461 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2462 PPC_MFTB; 2463 pcc->msr_mask = (1ull << MSR_ILE) | 2464 (1ull << MSR_EE) | 2465 (1ull << MSR_PR) | 2466 (1ull << MSR_FP) | 2467 (1ull << MSR_ME) | 2468 (1ull << MSR_FE0) | 2469 (1ull << MSR_SE) | 2470 (1ull << MSR_DE) | 2471 (1ull << MSR_FE1) | 2472 (1ull << MSR_EP) | 2473 (1ull << MSR_RI) | 2474 (1ull << MSR_LE); 2475 pcc->mmu_model = POWERPC_MMU_REAL; 2476 pcc->excp_model = POWERPC_EXCP_6xx; 2477 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2478 pcc->bfd_mach = bfd_mach_ppc_505; 2479 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2480 POWERPC_FLAG_BUS_CLK; 2481 } 2482 2483 static void init_proc_MPC8xx(CPUPPCState *env) 2484 { 2485 register_5xx_8xx_sprs(env); 2486 register_8xx_sprs(env); 2487 init_excp_MPC8xx(env); 2488 env->dcache_line_size = 32; 2489 env->icache_line_size = 32; 2490 /* XXX: TODO: allocate internal IRQ controller */ 2491 } 2492 2493 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2494 { 2495 DeviceClass *dc = DEVICE_CLASS(oc); 2496 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2497 2498 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2499 pcc->init_proc = init_proc_MPC8xx; 2500 pcc->check_pow = check_pow_none; 2501 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2502 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2503 PPC_CACHE_ICBI | PPC_MFTB; 2504 pcc->msr_mask = (1ull << MSR_ILE) | 2505 (1ull << MSR_EE) | 2506 (1ull << MSR_PR) | 2507 (1ull << MSR_FP) | 2508 (1ull << MSR_ME) | 2509 (1ull << MSR_SE) | 2510 (1ull << MSR_DE) | 2511 (1ull << MSR_EP) | 2512 (1ull << MSR_IR) | 2513 (1ull << MSR_DR) | 2514 (1ull << MSR_RI) | 2515 (1ull << MSR_LE); 2516 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2517 pcc->excp_model = POWERPC_EXCP_6xx; 2518 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2519 pcc->bfd_mach = bfd_mach_ppc_860; 2520 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2521 POWERPC_FLAG_BUS_CLK; 2522 } 2523 2524 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2525 2526 static void init_proc_G2(CPUPPCState *env) 2527 { 2528 register_non_embedded_sprs(env); 2529 register_sdr1_sprs(env); 2530 register_G2_sprs(env); 2531 2532 /* Memory management */ 2533 register_low_BATs(env); 2534 register_high_BATs(env); 2535 register_6xx_7xx_soft_tlb(env, 64, 2); 2536 init_excp_G2(env); 2537 env->dcache_line_size = 32; 2538 env->icache_line_size = 32; 2539 /* Allocate hardware IRQ controller */ 2540 ppc6xx_irq_init(env_archcpu(env)); 2541 } 2542 2543 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2544 { 2545 DeviceClass *dc = DEVICE_CLASS(oc); 2546 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2547 2548 dc->desc = "PowerPC G2"; 2549 pcc->init_proc = init_proc_G2; 2550 pcc->check_pow = check_pow_hid0; 2551 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2552 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2553 PPC_FLOAT_STFIWX | 2554 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2555 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2556 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2557 PPC_SEGMENT | PPC_EXTERN; 2558 pcc->msr_mask = (1ull << MSR_POW) | 2559 (1ull << MSR_TGPR) | 2560 (1ull << MSR_EE) | 2561 (1ull << MSR_PR) | 2562 (1ull << MSR_FP) | 2563 (1ull << MSR_ME) | 2564 (1ull << MSR_FE0) | 2565 (1ull << MSR_SE) | 2566 (1ull << MSR_DE) | 2567 (1ull << MSR_FE1) | 2568 (1ull << MSR_AL) | 2569 (1ull << MSR_EP) | 2570 (1ull << MSR_IR) | 2571 (1ull << MSR_DR) | 2572 (1ull << MSR_RI); 2573 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2574 pcc->excp_model = POWERPC_EXCP_6xx; 2575 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2576 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2577 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2578 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2579 } 2580 2581 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2582 { 2583 DeviceClass *dc = DEVICE_CLASS(oc); 2584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2585 2586 dc->desc = "PowerPC G2LE"; 2587 pcc->init_proc = init_proc_G2; 2588 pcc->check_pow = check_pow_hid0; 2589 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2590 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2591 PPC_FLOAT_STFIWX | 2592 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2593 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2594 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2595 PPC_SEGMENT | PPC_EXTERN; 2596 pcc->msr_mask = (1ull << MSR_POW) | 2597 (1ull << MSR_TGPR) | 2598 (1ull << MSR_ILE) | 2599 (1ull << MSR_EE) | 2600 (1ull << MSR_PR) | 2601 (1ull << MSR_FP) | 2602 (1ull << MSR_ME) | 2603 (1ull << MSR_FE0) | 2604 (1ull << MSR_SE) | 2605 (1ull << MSR_DE) | 2606 (1ull << MSR_FE1) | 2607 (1ull << MSR_AL) | 2608 (1ull << MSR_EP) | 2609 (1ull << MSR_IR) | 2610 (1ull << MSR_DR) | 2611 (1ull << MSR_RI) | 2612 (1ull << MSR_LE); 2613 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2614 pcc->excp_model = POWERPC_EXCP_6xx; 2615 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2616 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2617 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2618 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2619 } 2620 2621 static void init_proc_e200(CPUPPCState *env) 2622 { 2623 register_BookE_sprs(env, 0x000000070000FFFFULL); 2624 2625 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2626 &spr_read_spefscr, &spr_write_spefscr, 2627 &spr_read_spefscr, &spr_write_spefscr, 2628 0x00000000); 2629 /* Memory management */ 2630 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2631 register_usprgh_sprs(env); 2632 2633 spr_register(env, SPR_HID0, "HID0", 2634 SPR_NOACCESS, SPR_NOACCESS, 2635 &spr_read_generic, &spr_write_generic, 2636 0x00000000); 2637 2638 spr_register(env, SPR_HID1, "HID1", 2639 SPR_NOACCESS, SPR_NOACCESS, 2640 &spr_read_generic, &spr_write_generic, 2641 0x00000000); 2642 2643 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2644 SPR_NOACCESS, SPR_NOACCESS, 2645 &spr_read_generic, &spr_write_generic, 2646 0x00000000); 2647 2648 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2649 SPR_NOACCESS, SPR_NOACCESS, 2650 &spr_read_generic, &spr_write_generic, 2651 0x00000000); 2652 2653 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2654 SPR_NOACCESS, SPR_NOACCESS, 2655 &spr_read_generic, &spr_write_generic, 2656 0x00000000); 2657 2658 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2659 SPR_NOACCESS, SPR_NOACCESS, 2660 &spr_read_generic, &spr_write_generic, 2661 0x00000000); 2662 2663 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2664 SPR_NOACCESS, SPR_NOACCESS, 2665 &spr_read_generic, &spr_write_generic, 2666 0x00000000); 2667 2668 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2669 &spr_read_generic, SPR_NOACCESS, 2670 &spr_read_generic, SPR_NOACCESS, 2671 0x00000000); 2672 2673 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2674 SPR_NOACCESS, SPR_NOACCESS, 2675 &spr_read_generic, &spr_write_generic, 2676 0x00000000); 2677 2678 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2679 SPR_NOACCESS, SPR_NOACCESS, 2680 &spr_read_generic, &spr_write_generic, 2681 0x00000000); 2682 2683 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2684 SPR_NOACCESS, SPR_NOACCESS, 2685 &spr_read_generic, &spr_write_generic, 2686 0x00000000); 2687 2688 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2689 SPR_NOACCESS, SPR_NOACCESS, 2690 &spr_read_generic, &spr_write_generic, 2691 0x00000000); 2692 2693 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2694 SPR_NOACCESS, SPR_NOACCESS, 2695 &spr_read_generic, &spr_write_generic, 2696 0x00000000); 2697 2698 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2699 SPR_NOACCESS, SPR_NOACCESS, 2700 &spr_read_generic, &spr_write_generic, 2701 0x00000000); 2702 2703 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2704 SPR_NOACCESS, SPR_NOACCESS, 2705 &spr_read_generic, &spr_write_generic, 2706 0x00000000); /* TOFIX */ 2707 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2708 SPR_NOACCESS, SPR_NOACCESS, 2709 &spr_read_generic, &spr_write_generic, 2710 0x00000000); 2711 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2712 SPR_NOACCESS, SPR_NOACCESS, 2713 &spr_read_generic, &spr_write_generic, 2714 0x00000000); 2715 #if !defined(CONFIG_USER_ONLY) 2716 env->nb_tlb = 64; 2717 env->nb_ways = 1; 2718 env->id_tlbs = 0; 2719 env->tlb_type = TLB_EMB; 2720 #endif 2721 init_excp_e200(env, 0xFFFF0000UL); 2722 env->dcache_line_size = 32; 2723 env->icache_line_size = 32; 2724 /* XXX: TODO: allocate internal IRQ controller */ 2725 } 2726 2727 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2728 { 2729 DeviceClass *dc = DEVICE_CLASS(oc); 2730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2731 2732 dc->desc = "e200 core"; 2733 pcc->init_proc = init_proc_e200; 2734 pcc->check_pow = check_pow_hid0; 2735 /* 2736 * XXX: unimplemented instructions: 2737 * dcblc 2738 * dcbtlst 2739 * dcbtstls 2740 * icblc 2741 * icbtls 2742 * tlbivax 2743 * all SPE multiply-accumulate instructions 2744 */ 2745 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2746 PPC_SPE | PPC_SPE_SINGLE | 2747 PPC_WRTEE | PPC_RFDI | 2748 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2749 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2750 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2751 PPC_BOOKE; 2752 pcc->msr_mask = (1ull << MSR_UCLE) | 2753 (1ull << MSR_SPE) | 2754 (1ull << MSR_POW) | 2755 (1ull << MSR_CE) | 2756 (1ull << MSR_EE) | 2757 (1ull << MSR_PR) | 2758 (1ull << MSR_FP) | 2759 (1ull << MSR_ME) | 2760 (1ull << MSR_FE0) | 2761 (1ull << MSR_DWE) | 2762 (1ull << MSR_DE) | 2763 (1ull << MSR_FE1) | 2764 (1ull << MSR_IR) | 2765 (1ull << MSR_DR); 2766 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2767 pcc->excp_model = POWERPC_EXCP_BOOKE; 2768 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2769 pcc->bfd_mach = bfd_mach_ppc_860; 2770 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2771 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2772 POWERPC_FLAG_BUS_CLK; 2773 } 2774 2775 enum fsl_e500_version { 2776 fsl_e500v1, 2777 fsl_e500v2, 2778 fsl_e500mc, 2779 fsl_e5500, 2780 fsl_e6500, 2781 }; 2782 2783 static void init_proc_e500(CPUPPCState *env, int version) 2784 { 2785 uint32_t tlbncfg[2]; 2786 uint64_t ivor_mask; 2787 uint64_t ivpr_mask = 0xFFFF0000ULL; 2788 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2789 | 0x0020; /* 32 kb */ 2790 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2791 | 0x0020; /* 32 kb */ 2792 uint32_t mmucfg = 0; 2793 #if !defined(CONFIG_USER_ONLY) 2794 int i; 2795 #endif 2796 2797 /* 2798 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2799 * complain when accessing them. 2800 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2801 */ 2802 switch (version) { 2803 case fsl_e500v1: 2804 case fsl_e500v2: 2805 default: 2806 ivor_mask = 0x0000000F0000FFFFULL; 2807 break; 2808 case fsl_e500mc: 2809 case fsl_e5500: 2810 ivor_mask = 0x000003FE0000FFFFULL; 2811 break; 2812 case fsl_e6500: 2813 ivor_mask = 0x000003FF0000FFFFULL; 2814 break; 2815 } 2816 register_BookE_sprs(env, ivor_mask); 2817 2818 spr_register(env, SPR_USPRG3, "USPRG3", 2819 &spr_read_ureg, SPR_NOACCESS, 2820 &spr_read_ureg, SPR_NOACCESS, 2821 0x00000000); 2822 2823 /* Processor identification */ 2824 spr_register(env, SPR_BOOKE_PIR, "PIR", 2825 SPR_NOACCESS, SPR_NOACCESS, 2826 &spr_read_generic, &spr_write_pir, 2827 0x00000000); 2828 2829 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2830 &spr_read_spefscr, &spr_write_spefscr, 2831 &spr_read_spefscr, &spr_write_spefscr, 2832 0x00000000); 2833 #if !defined(CONFIG_USER_ONLY) 2834 /* Memory management */ 2835 env->nb_pids = 3; 2836 env->nb_ways = 2; 2837 env->id_tlbs = 0; 2838 switch (version) { 2839 case fsl_e500v1: 2840 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2841 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2842 break; 2843 case fsl_e500v2: 2844 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2845 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2846 break; 2847 case fsl_e500mc: 2848 case fsl_e5500: 2849 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2850 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2851 break; 2852 case fsl_e6500: 2853 mmucfg = 0x6510B45; 2854 env->nb_pids = 1; 2855 tlbncfg[0] = 0x08052400; 2856 tlbncfg[1] = 0x40028040; 2857 break; 2858 default: 2859 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2860 env->spr[SPR_PVR]); 2861 } 2862 #endif 2863 /* Cache sizes */ 2864 switch (version) { 2865 case fsl_e500v1: 2866 case fsl_e500v2: 2867 env->dcache_line_size = 32; 2868 env->icache_line_size = 32; 2869 break; 2870 case fsl_e500mc: 2871 case fsl_e5500: 2872 env->dcache_line_size = 64; 2873 env->icache_line_size = 64; 2874 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2875 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2876 break; 2877 case fsl_e6500: 2878 env->dcache_line_size = 32; 2879 env->icache_line_size = 32; 2880 l1cfg0 |= 0x0F83820; 2881 l1cfg1 |= 0x0B83820; 2882 break; 2883 default: 2884 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2885 env->spr[SPR_PVR]); 2886 } 2887 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2888 register_usprgh_sprs(env); 2889 2890 spr_register(env, SPR_HID0, "HID0", 2891 SPR_NOACCESS, SPR_NOACCESS, 2892 &spr_read_generic, &spr_write_generic, 2893 0x00000000); 2894 2895 spr_register(env, SPR_HID1, "HID1", 2896 SPR_NOACCESS, SPR_NOACCESS, 2897 &spr_read_generic, &spr_write_generic, 2898 0x00000000); 2899 2900 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2901 SPR_NOACCESS, SPR_NOACCESS, 2902 &spr_read_generic, &spr_write_generic, 2903 0x00000000); 2904 2905 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2906 SPR_NOACCESS, SPR_NOACCESS, 2907 &spr_read_generic, &spr_write_generic, 2908 0x00000000); 2909 2910 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2911 SPR_NOACCESS, SPR_NOACCESS, 2912 &spr_read_generic, &spr_write_generic, 2913 0x00000000); 2914 2915 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2916 SPR_NOACCESS, SPR_NOACCESS, 2917 &spr_read_generic, &spr_write_generic, 2918 0x00000000); 2919 2920 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2921 SPR_NOACCESS, SPR_NOACCESS, 2922 &spr_read_generic, &spr_write_generic, 2923 0x00000000); 2924 2925 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2926 SPR_NOACCESS, SPR_NOACCESS, 2927 &spr_read_generic, &spr_write_generic, 2928 0x00000000); 2929 2930 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2931 &spr_read_generic, SPR_NOACCESS, 2932 &spr_read_generic, SPR_NOACCESS, 2933 l1cfg0); 2934 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2935 &spr_read_generic, SPR_NOACCESS, 2936 &spr_read_generic, SPR_NOACCESS, 2937 l1cfg1); 2938 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2939 SPR_NOACCESS, SPR_NOACCESS, 2940 &spr_read_generic, &spr_write_e500_l1csr0, 2941 0x00000000); 2942 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2943 SPR_NOACCESS, SPR_NOACCESS, 2944 &spr_read_generic, &spr_write_e500_l1csr1, 2945 0x00000000); 2946 if (version != fsl_e500v1 && version != fsl_e500v2) { 2947 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2948 SPR_NOACCESS, SPR_NOACCESS, 2949 &spr_read_generic, &spr_write_e500_l2csr0, 2950 0x00000000); 2951 } 2952 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2953 SPR_NOACCESS, SPR_NOACCESS, 2954 &spr_read_generic, &spr_write_generic, 2955 0x00000000); 2956 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2957 SPR_NOACCESS, SPR_NOACCESS, 2958 &spr_read_generic, &spr_write_generic, 2959 0x00000000); 2960 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2961 SPR_NOACCESS, SPR_NOACCESS, 2962 &spr_read_generic, &spr_write_booke206_mmucsr0, 2963 0x00000000); 2964 spr_register(env, SPR_BOOKE_EPR, "EPR", 2965 SPR_NOACCESS, SPR_NOACCESS, 2966 &spr_read_generic, SPR_NOACCESS, 2967 0x00000000); 2968 /* XXX better abstract into Emb.xxx features */ 2969 if ((version == fsl_e5500) || (version == fsl_e6500)) { 2970 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 2971 SPR_NOACCESS, SPR_NOACCESS, 2972 &spr_read_generic, &spr_write_generic, 2973 0x00000000); 2974 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 2975 SPR_NOACCESS, SPR_NOACCESS, 2976 &spr_read_mas73, &spr_write_mas73, 2977 0x00000000); 2978 ivpr_mask = (target_ulong)~0xFFFFULL; 2979 } 2980 2981 if (version == fsl_e6500) { 2982 /* Thread identification */ 2983 spr_register(env, SPR_TIR, "TIR", 2984 SPR_NOACCESS, SPR_NOACCESS, 2985 &spr_read_generic, SPR_NOACCESS, 2986 0x00000000); 2987 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 2988 SPR_NOACCESS, SPR_NOACCESS, 2989 &spr_read_generic, SPR_NOACCESS, 2990 0x00000004); 2991 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 2992 SPR_NOACCESS, SPR_NOACCESS, 2993 &spr_read_generic, SPR_NOACCESS, 2994 0x7FFFFFFC); 2995 } 2996 2997 #if !defined(CONFIG_USER_ONLY) 2998 env->nb_tlb = 0; 2999 env->tlb_type = TLB_MAS; 3000 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3001 env->nb_tlb += booke206_tlb_size(env, i); 3002 } 3003 #endif 3004 3005 init_excp_e200(env, ivpr_mask); 3006 /* Allocate hardware IRQ controller */ 3007 ppce500_irq_init(env_archcpu(env)); 3008 } 3009 3010 static void init_proc_e500v1(CPUPPCState *env) 3011 { 3012 init_proc_e500(env, fsl_e500v1); 3013 } 3014 3015 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3016 { 3017 DeviceClass *dc = DEVICE_CLASS(oc); 3018 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3019 3020 dc->desc = "e500v1 core"; 3021 pcc->init_proc = init_proc_e500v1; 3022 pcc->check_pow = check_pow_hid0; 3023 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3024 PPC_SPE | PPC_SPE_SINGLE | 3025 PPC_WRTEE | PPC_RFDI | 3026 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3027 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3028 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3029 pcc->insns_flags2 = PPC2_BOOKE206; 3030 pcc->msr_mask = (1ull << MSR_UCLE) | 3031 (1ull << MSR_SPE) | 3032 (1ull << MSR_POW) | 3033 (1ull << MSR_CE) | 3034 (1ull << MSR_EE) | 3035 (1ull << MSR_PR) | 3036 (1ull << MSR_FP) | 3037 (1ull << MSR_ME) | 3038 (1ull << MSR_FE0) | 3039 (1ull << MSR_DWE) | 3040 (1ull << MSR_DE) | 3041 (1ull << MSR_FE1) | 3042 (1ull << MSR_IR) | 3043 (1ull << MSR_DR); 3044 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3045 pcc->excp_model = POWERPC_EXCP_BOOKE; 3046 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3047 pcc->bfd_mach = bfd_mach_ppc_860; 3048 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3049 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3050 POWERPC_FLAG_BUS_CLK; 3051 } 3052 3053 static void init_proc_e500v2(CPUPPCState *env) 3054 { 3055 init_proc_e500(env, fsl_e500v2); 3056 } 3057 3058 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3059 { 3060 DeviceClass *dc = DEVICE_CLASS(oc); 3061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3062 3063 dc->desc = "e500v2 core"; 3064 pcc->init_proc = init_proc_e500v2; 3065 pcc->check_pow = check_pow_hid0; 3066 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3067 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3068 PPC_WRTEE | PPC_RFDI | 3069 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3070 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3071 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3072 pcc->insns_flags2 = PPC2_BOOKE206; 3073 pcc->msr_mask = (1ull << MSR_UCLE) | 3074 (1ull << MSR_SPE) | 3075 (1ull << MSR_POW) | 3076 (1ull << MSR_CE) | 3077 (1ull << MSR_EE) | 3078 (1ull << MSR_PR) | 3079 (1ull << MSR_FP) | 3080 (1ull << MSR_ME) | 3081 (1ull << MSR_FE0) | 3082 (1ull << MSR_DWE) | 3083 (1ull << MSR_DE) | 3084 (1ull << MSR_FE1) | 3085 (1ull << MSR_IR) | 3086 (1ull << MSR_DR); 3087 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3088 pcc->excp_model = POWERPC_EXCP_BOOKE; 3089 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3090 pcc->bfd_mach = bfd_mach_ppc_860; 3091 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3092 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3093 POWERPC_FLAG_BUS_CLK; 3094 } 3095 3096 static void init_proc_e500mc(CPUPPCState *env) 3097 { 3098 init_proc_e500(env, fsl_e500mc); 3099 } 3100 3101 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3102 { 3103 DeviceClass *dc = DEVICE_CLASS(oc); 3104 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3105 3106 dc->desc = "e500mc core"; 3107 pcc->init_proc = init_proc_e500mc; 3108 pcc->check_pow = check_pow_none; 3109 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3110 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3111 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3112 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3113 PPC_FLOAT | PPC_FLOAT_FRES | 3114 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3115 PPC_FLOAT_STFIWX | PPC_WAIT | 3116 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3117 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3118 pcc->msr_mask = (1ull << MSR_GS) | 3119 (1ull << MSR_UCLE) | 3120 (1ull << MSR_CE) | 3121 (1ull << MSR_EE) | 3122 (1ull << MSR_PR) | 3123 (1ull << MSR_FP) | 3124 (1ull << MSR_ME) | 3125 (1ull << MSR_FE0) | 3126 (1ull << MSR_DE) | 3127 (1ull << MSR_FE1) | 3128 (1ull << MSR_IR) | 3129 (1ull << MSR_DR) | 3130 (1ull << MSR_PX) | 3131 (1ull << MSR_RI); 3132 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3133 pcc->excp_model = POWERPC_EXCP_BOOKE; 3134 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3135 /* FIXME: figure out the correct flag for e500mc */ 3136 pcc->bfd_mach = bfd_mach_ppc_e500; 3137 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3138 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3139 } 3140 3141 #ifdef TARGET_PPC64 3142 static void init_proc_e5500(CPUPPCState *env) 3143 { 3144 init_proc_e500(env, fsl_e5500); 3145 } 3146 3147 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3148 { 3149 DeviceClass *dc = DEVICE_CLASS(oc); 3150 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3151 3152 dc->desc = "e5500 core"; 3153 pcc->init_proc = init_proc_e5500; 3154 pcc->check_pow = check_pow_none; 3155 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3156 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3157 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3158 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3159 PPC_FLOAT | PPC_FLOAT_FRES | 3160 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3161 PPC_FLOAT_STFIWX | PPC_WAIT | 3162 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3163 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3164 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3165 PPC2_FP_CVT_S64; 3166 pcc->msr_mask = (1ull << MSR_CM) | 3167 (1ull << MSR_GS) | 3168 (1ull << MSR_UCLE) | 3169 (1ull << MSR_CE) | 3170 (1ull << MSR_EE) | 3171 (1ull << MSR_PR) | 3172 (1ull << MSR_FP) | 3173 (1ull << MSR_ME) | 3174 (1ull << MSR_FE0) | 3175 (1ull << MSR_DE) | 3176 (1ull << MSR_FE1) | 3177 (1ull << MSR_IR) | 3178 (1ull << MSR_DR) | 3179 (1ull << MSR_PX) | 3180 (1ull << MSR_RI); 3181 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3182 pcc->excp_model = POWERPC_EXCP_BOOKE; 3183 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3184 /* FIXME: figure out the correct flag for e5500 */ 3185 pcc->bfd_mach = bfd_mach_ppc_e500; 3186 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3187 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3188 } 3189 3190 static void init_proc_e6500(CPUPPCState *env) 3191 { 3192 init_proc_e500(env, fsl_e6500); 3193 } 3194 3195 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3196 { 3197 DeviceClass *dc = DEVICE_CLASS(oc); 3198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3199 3200 dc->desc = "e6500 core"; 3201 pcc->init_proc = init_proc_e6500; 3202 pcc->check_pow = check_pow_none; 3203 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3204 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3205 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3206 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3207 PPC_FLOAT | PPC_FLOAT_FRES | 3208 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3209 PPC_FLOAT_STFIWX | PPC_WAIT | 3210 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3211 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3212 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3213 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3214 pcc->msr_mask = (1ull << MSR_CM) | 3215 (1ull << MSR_GS) | 3216 (1ull << MSR_UCLE) | 3217 (1ull << MSR_CE) | 3218 (1ull << MSR_EE) | 3219 (1ull << MSR_PR) | 3220 (1ull << MSR_FP) | 3221 (1ull << MSR_ME) | 3222 (1ull << MSR_FE0) | 3223 (1ull << MSR_DE) | 3224 (1ull << MSR_FE1) | 3225 (1ull << MSR_IS) | 3226 (1ull << MSR_DS) | 3227 (1ull << MSR_PX) | 3228 (1ull << MSR_RI) | 3229 (1ull << MSR_VR); 3230 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3231 pcc->excp_model = POWERPC_EXCP_BOOKE; 3232 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3233 pcc->bfd_mach = bfd_mach_ppc_e500; 3234 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3235 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3236 } 3237 3238 #endif 3239 3240 /* Non-embedded PowerPC */ 3241 static void init_proc_603(CPUPPCState *env) 3242 { 3243 register_non_embedded_sprs(env); 3244 register_sdr1_sprs(env); 3245 register_603_sprs(env); 3246 3247 /* Memory management */ 3248 register_low_BATs(env); 3249 register_6xx_7xx_soft_tlb(env, 64, 2); 3250 init_excp_603(env); 3251 env->dcache_line_size = 32; 3252 env->icache_line_size = 32; 3253 /* Allocate hardware IRQ controller */ 3254 ppc6xx_irq_init(env_archcpu(env)); 3255 } 3256 3257 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3258 { 3259 DeviceClass *dc = DEVICE_CLASS(oc); 3260 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3261 3262 dc->desc = "PowerPC 603"; 3263 pcc->init_proc = init_proc_603; 3264 pcc->check_pow = check_pow_hid0; 3265 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3267 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3268 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3269 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3270 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3271 PPC_SEGMENT | PPC_EXTERN; 3272 pcc->msr_mask = (1ull << MSR_POW) | 3273 (1ull << MSR_TGPR) | 3274 (1ull << MSR_ILE) | 3275 (1ull << MSR_EE) | 3276 (1ull << MSR_PR) | 3277 (1ull << MSR_FP) | 3278 (1ull << MSR_ME) | 3279 (1ull << MSR_FE0) | 3280 (1ull << MSR_SE) | 3281 (1ull << MSR_DE) | 3282 (1ull << MSR_FE1) | 3283 (1ull << MSR_EP) | 3284 (1ull << MSR_IR) | 3285 (1ull << MSR_DR) | 3286 (1ull << MSR_RI) | 3287 (1ull << MSR_LE); 3288 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3289 pcc->excp_model = POWERPC_EXCP_6xx; 3290 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3291 pcc->bfd_mach = bfd_mach_ppc_603; 3292 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3293 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3294 } 3295 3296 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3297 { 3298 DeviceClass *dc = DEVICE_CLASS(oc); 3299 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3300 3301 dc->desc = "PowerPC 603e"; 3302 pcc->init_proc = init_proc_603; 3303 pcc->check_pow = check_pow_hid0; 3304 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3305 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3306 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3307 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3308 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3309 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3310 PPC_SEGMENT | PPC_EXTERN; 3311 pcc->msr_mask = (1ull << MSR_POW) | 3312 (1ull << MSR_TGPR) | 3313 (1ull << MSR_ILE) | 3314 (1ull << MSR_EE) | 3315 (1ull << MSR_PR) | 3316 (1ull << MSR_FP) | 3317 (1ull << MSR_ME) | 3318 (1ull << MSR_FE0) | 3319 (1ull << MSR_SE) | 3320 (1ull << MSR_DE) | 3321 (1ull << MSR_FE1) | 3322 (1ull << MSR_EP) | 3323 (1ull << MSR_IR) | 3324 (1ull << MSR_DR) | 3325 (1ull << MSR_RI) | 3326 (1ull << MSR_LE); 3327 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3328 pcc->excp_model = POWERPC_EXCP_6xx; 3329 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3330 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3331 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3332 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3333 } 3334 3335 static void init_proc_e300(CPUPPCState *env) 3336 { 3337 init_proc_603(env); 3338 register_e300_sprs(env); 3339 } 3340 3341 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3342 { 3343 DeviceClass *dc = DEVICE_CLASS(oc); 3344 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3345 3346 dc->desc = "e300 core"; 3347 pcc->init_proc = init_proc_e300; 3348 pcc->check_pow = check_pow_hid0; 3349 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3350 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3351 PPC_FLOAT_STFIWX | 3352 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3353 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3354 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3355 PPC_SEGMENT | PPC_EXTERN; 3356 pcc->msr_mask = (1ull << MSR_POW) | 3357 (1ull << MSR_TGPR) | 3358 (1ull << MSR_ILE) | 3359 (1ull << MSR_EE) | 3360 (1ull << MSR_PR) | 3361 (1ull << MSR_FP) | 3362 (1ull << MSR_ME) | 3363 (1ull << MSR_FE0) | 3364 (1ull << MSR_SE) | 3365 (1ull << MSR_DE) | 3366 (1ull << MSR_FE1) | 3367 (1ull << MSR_AL) | 3368 (1ull << MSR_EP) | 3369 (1ull << MSR_IR) | 3370 (1ull << MSR_DR) | 3371 (1ull << MSR_RI) | 3372 (1ull << MSR_LE); 3373 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3374 pcc->excp_model = POWERPC_EXCP_6xx; 3375 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3376 pcc->bfd_mach = bfd_mach_ppc_603; 3377 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3378 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3379 } 3380 3381 static void init_proc_604(CPUPPCState *env) 3382 { 3383 register_non_embedded_sprs(env); 3384 register_sdr1_sprs(env); 3385 register_604_sprs(env); 3386 3387 /* Memory management */ 3388 register_low_BATs(env); 3389 init_excp_604(env); 3390 env->dcache_line_size = 32; 3391 env->icache_line_size = 32; 3392 /* Allocate hardware IRQ controller */ 3393 ppc6xx_irq_init(env_archcpu(env)); 3394 } 3395 3396 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3397 { 3398 DeviceClass *dc = DEVICE_CLASS(oc); 3399 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3400 3401 dc->desc = "PowerPC 604"; 3402 pcc->init_proc = init_proc_604; 3403 pcc->check_pow = check_pow_nocheck; 3404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3405 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3406 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3407 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3408 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3409 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3410 PPC_SEGMENT | PPC_EXTERN; 3411 pcc->msr_mask = (1ull << MSR_POW) | 3412 (1ull << MSR_ILE) | 3413 (1ull << MSR_EE) | 3414 (1ull << MSR_PR) | 3415 (1ull << MSR_FP) | 3416 (1ull << MSR_ME) | 3417 (1ull << MSR_FE0) | 3418 (1ull << MSR_SE) | 3419 (1ull << MSR_DE) | 3420 (1ull << MSR_FE1) | 3421 (1ull << MSR_EP) | 3422 (1ull << MSR_IR) | 3423 (1ull << MSR_DR) | 3424 (1ull << MSR_PMM) | 3425 (1ull << MSR_RI) | 3426 (1ull << MSR_LE); 3427 pcc->mmu_model = POWERPC_MMU_32B; 3428 pcc->excp_model = POWERPC_EXCP_6xx; 3429 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3430 pcc->bfd_mach = bfd_mach_ppc_604; 3431 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3432 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3433 } 3434 3435 static void init_proc_604E(CPUPPCState *env) 3436 { 3437 init_proc_604(env); 3438 register_604e_sprs(env); 3439 } 3440 3441 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3442 { 3443 DeviceClass *dc = DEVICE_CLASS(oc); 3444 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3445 3446 dc->desc = "PowerPC 604E"; 3447 pcc->init_proc = init_proc_604E; 3448 pcc->check_pow = check_pow_nocheck; 3449 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3450 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3451 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3452 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3453 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3454 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3455 PPC_SEGMENT | PPC_EXTERN; 3456 pcc->msr_mask = (1ull << MSR_POW) | 3457 (1ull << MSR_ILE) | 3458 (1ull << MSR_EE) | 3459 (1ull << MSR_PR) | 3460 (1ull << MSR_FP) | 3461 (1ull << MSR_ME) | 3462 (1ull << MSR_FE0) | 3463 (1ull << MSR_SE) | 3464 (1ull << MSR_DE) | 3465 (1ull << MSR_FE1) | 3466 (1ull << MSR_EP) | 3467 (1ull << MSR_IR) | 3468 (1ull << MSR_DR) | 3469 (1ull << MSR_PMM) | 3470 (1ull << MSR_RI) | 3471 (1ull << MSR_LE); 3472 pcc->mmu_model = POWERPC_MMU_32B; 3473 pcc->excp_model = POWERPC_EXCP_6xx; 3474 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3475 pcc->bfd_mach = bfd_mach_ppc_604; 3476 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3477 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3478 } 3479 3480 static void init_proc_740(CPUPPCState *env) 3481 { 3482 register_non_embedded_sprs(env); 3483 register_sdr1_sprs(env); 3484 register_7xx_sprs(env); 3485 /* Thermal management */ 3486 register_thrm_sprs(env); 3487 3488 /* Memory management */ 3489 register_low_BATs(env); 3490 init_excp_7x0(env); 3491 env->dcache_line_size = 32; 3492 env->icache_line_size = 32; 3493 /* Allocate hardware IRQ controller */ 3494 ppc6xx_irq_init(env_archcpu(env)); 3495 } 3496 3497 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3498 { 3499 DeviceClass *dc = DEVICE_CLASS(oc); 3500 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3501 3502 dc->desc = "PowerPC 740"; 3503 pcc->init_proc = init_proc_740; 3504 pcc->check_pow = check_pow_hid0; 3505 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3506 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3507 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3508 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3509 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3510 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3511 PPC_SEGMENT | PPC_EXTERN; 3512 pcc->msr_mask = (1ull << MSR_POW) | 3513 (1ull << MSR_ILE) | 3514 (1ull << MSR_EE) | 3515 (1ull << MSR_PR) | 3516 (1ull << MSR_FP) | 3517 (1ull << MSR_ME) | 3518 (1ull << MSR_FE0) | 3519 (1ull << MSR_SE) | 3520 (1ull << MSR_DE) | 3521 (1ull << MSR_FE1) | 3522 (1ull << MSR_EP) | 3523 (1ull << MSR_IR) | 3524 (1ull << MSR_DR) | 3525 (1ull << MSR_PMM) | 3526 (1ull << MSR_RI) | 3527 (1ull << MSR_LE); 3528 pcc->mmu_model = POWERPC_MMU_32B; 3529 pcc->excp_model = POWERPC_EXCP_7xx; 3530 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3531 pcc->bfd_mach = bfd_mach_ppc_750; 3532 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3533 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3534 } 3535 3536 static void init_proc_750(CPUPPCState *env) 3537 { 3538 register_non_embedded_sprs(env); 3539 register_sdr1_sprs(env); 3540 register_7xx_sprs(env); 3541 3542 spr_register(env, SPR_L2CR, "L2CR", 3543 SPR_NOACCESS, SPR_NOACCESS, 3544 &spr_read_generic, spr_access_nop, 3545 0x00000000); 3546 /* Thermal management */ 3547 register_thrm_sprs(env); 3548 3549 /* Memory management */ 3550 register_low_BATs(env); 3551 /* 3552 * XXX: high BATs are also present but are known to be bugged on 3553 * die version 1.x 3554 */ 3555 init_excp_7x0(env); 3556 env->dcache_line_size = 32; 3557 env->icache_line_size = 32; 3558 /* Allocate hardware IRQ controller */ 3559 ppc6xx_irq_init(env_archcpu(env)); 3560 } 3561 3562 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3563 { 3564 DeviceClass *dc = DEVICE_CLASS(oc); 3565 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3566 3567 dc->desc = "PowerPC 750"; 3568 pcc->init_proc = init_proc_750; 3569 pcc->check_pow = check_pow_hid0; 3570 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3571 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3572 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3573 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3574 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3575 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3576 PPC_SEGMENT | PPC_EXTERN; 3577 pcc->msr_mask = (1ull << MSR_POW) | 3578 (1ull << MSR_ILE) | 3579 (1ull << MSR_EE) | 3580 (1ull << MSR_PR) | 3581 (1ull << MSR_FP) | 3582 (1ull << MSR_ME) | 3583 (1ull << MSR_FE0) | 3584 (1ull << MSR_SE) | 3585 (1ull << MSR_DE) | 3586 (1ull << MSR_FE1) | 3587 (1ull << MSR_EP) | 3588 (1ull << MSR_IR) | 3589 (1ull << MSR_DR) | 3590 (1ull << MSR_PMM) | 3591 (1ull << MSR_RI) | 3592 (1ull << MSR_LE); 3593 pcc->mmu_model = POWERPC_MMU_32B; 3594 pcc->excp_model = POWERPC_EXCP_7xx; 3595 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3596 pcc->bfd_mach = bfd_mach_ppc_750; 3597 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3598 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3599 } 3600 3601 static void init_proc_750cl(CPUPPCState *env) 3602 { 3603 register_non_embedded_sprs(env); 3604 register_sdr1_sprs(env); 3605 register_7xx_sprs(env); 3606 3607 spr_register(env, SPR_L2CR, "L2CR", 3608 SPR_NOACCESS, SPR_NOACCESS, 3609 &spr_read_generic, spr_access_nop, 3610 0x00000000); 3611 /* Thermal management */ 3612 /* Those registers are fake on 750CL */ 3613 spr_register(env, SPR_THRM1, "THRM1", 3614 SPR_NOACCESS, SPR_NOACCESS, 3615 &spr_read_generic, &spr_write_generic, 3616 0x00000000); 3617 spr_register(env, SPR_THRM2, "THRM2", 3618 SPR_NOACCESS, SPR_NOACCESS, 3619 &spr_read_generic, &spr_write_generic, 3620 0x00000000); 3621 spr_register(env, SPR_THRM3, "THRM3", 3622 SPR_NOACCESS, SPR_NOACCESS, 3623 &spr_read_generic, &spr_write_generic, 3624 0x00000000); 3625 3626 spr_register(env, SPR_750_TDCL, "TDCL", 3627 SPR_NOACCESS, SPR_NOACCESS, 3628 &spr_read_generic, &spr_write_generic, 3629 0x00000000); 3630 spr_register(env, SPR_750_TDCH, "TDCH", 3631 SPR_NOACCESS, SPR_NOACCESS, 3632 &spr_read_generic, &spr_write_generic, 3633 0x00000000); 3634 /* DMA */ 3635 spr_register(env, SPR_750_WPAR, "WPAR", 3636 SPR_NOACCESS, SPR_NOACCESS, 3637 &spr_read_generic, &spr_write_generic, 3638 0x00000000); 3639 spr_register(env, SPR_750_DMAL, "DMAL", 3640 SPR_NOACCESS, SPR_NOACCESS, 3641 &spr_read_generic, &spr_write_generic, 3642 0x00000000); 3643 spr_register(env, SPR_750_DMAU, "DMAU", 3644 SPR_NOACCESS, SPR_NOACCESS, 3645 &spr_read_generic, &spr_write_generic, 3646 0x00000000); 3647 /* Hardware implementation registers */ 3648 spr_register(env, SPR_750CL_HID2, "HID2", 3649 SPR_NOACCESS, SPR_NOACCESS, 3650 &spr_read_generic, &spr_write_generic, 3651 0x00000000); 3652 3653 spr_register(env, SPR_750CL_HID4, "HID4", 3654 SPR_NOACCESS, SPR_NOACCESS, 3655 &spr_read_generic, &spr_write_generic, 3656 0x00000000); 3657 /* Quantization registers */ 3658 spr_register(env, SPR_750_GQR0, "GQR0", 3659 SPR_NOACCESS, SPR_NOACCESS, 3660 &spr_read_generic, &spr_write_generic, 3661 0x00000000); 3662 3663 spr_register(env, SPR_750_GQR1, "GQR1", 3664 SPR_NOACCESS, SPR_NOACCESS, 3665 &spr_read_generic, &spr_write_generic, 3666 0x00000000); 3667 3668 spr_register(env, SPR_750_GQR2, "GQR2", 3669 SPR_NOACCESS, SPR_NOACCESS, 3670 &spr_read_generic, &spr_write_generic, 3671 0x00000000); 3672 3673 spr_register(env, SPR_750_GQR3, "GQR3", 3674 SPR_NOACCESS, SPR_NOACCESS, 3675 &spr_read_generic, &spr_write_generic, 3676 0x00000000); 3677 3678 spr_register(env, SPR_750_GQR4, "GQR4", 3679 SPR_NOACCESS, SPR_NOACCESS, 3680 &spr_read_generic, &spr_write_generic, 3681 0x00000000); 3682 3683 spr_register(env, SPR_750_GQR5, "GQR5", 3684 SPR_NOACCESS, SPR_NOACCESS, 3685 &spr_read_generic, &spr_write_generic, 3686 0x00000000); 3687 3688 spr_register(env, SPR_750_GQR6, "GQR6", 3689 SPR_NOACCESS, SPR_NOACCESS, 3690 &spr_read_generic, &spr_write_generic, 3691 0x00000000); 3692 3693 spr_register(env, SPR_750_GQR7, "GQR7", 3694 SPR_NOACCESS, SPR_NOACCESS, 3695 &spr_read_generic, &spr_write_generic, 3696 0x00000000); 3697 /* Memory management */ 3698 register_low_BATs(env); 3699 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3700 register_high_BATs(env); 3701 init_excp_750cl(env); 3702 env->dcache_line_size = 32; 3703 env->icache_line_size = 32; 3704 /* Allocate hardware IRQ controller */ 3705 ppc6xx_irq_init(env_archcpu(env)); 3706 } 3707 3708 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3709 { 3710 DeviceClass *dc = DEVICE_CLASS(oc); 3711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3712 3713 dc->desc = "PowerPC 750 CL"; 3714 pcc->init_proc = init_proc_750cl; 3715 pcc->check_pow = check_pow_hid0; 3716 /* 3717 * XXX: not implemented: 3718 * cache lock instructions: 3719 * dcbz_l 3720 * floating point paired instructions 3721 * psq_lux 3722 * psq_lx 3723 * psq_stux 3724 * psq_stx 3725 * ps_abs 3726 * ps_add 3727 * ps_cmpo0 3728 * ps_cmpo1 3729 * ps_cmpu0 3730 * ps_cmpu1 3731 * ps_div 3732 * ps_madd 3733 * ps_madds0 3734 * ps_madds1 3735 * ps_merge00 3736 * ps_merge01 3737 * ps_merge10 3738 * ps_merge11 3739 * ps_mr 3740 * ps_msub 3741 * ps_mul 3742 * ps_muls0 3743 * ps_muls1 3744 * ps_nabs 3745 * ps_neg 3746 * ps_nmadd 3747 * ps_nmsub 3748 * ps_res 3749 * ps_rsqrte 3750 * ps_sel 3751 * ps_sub 3752 * ps_sum0 3753 * ps_sum1 3754 */ 3755 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3756 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3757 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3758 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3759 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3760 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3761 PPC_SEGMENT | PPC_EXTERN; 3762 pcc->msr_mask = (1ull << MSR_POW) | 3763 (1ull << MSR_ILE) | 3764 (1ull << MSR_EE) | 3765 (1ull << MSR_PR) | 3766 (1ull << MSR_FP) | 3767 (1ull << MSR_ME) | 3768 (1ull << MSR_FE0) | 3769 (1ull << MSR_SE) | 3770 (1ull << MSR_DE) | 3771 (1ull << MSR_FE1) | 3772 (1ull << MSR_EP) | 3773 (1ull << MSR_IR) | 3774 (1ull << MSR_DR) | 3775 (1ull << MSR_PMM) | 3776 (1ull << MSR_RI) | 3777 (1ull << MSR_LE); 3778 pcc->mmu_model = POWERPC_MMU_32B; 3779 pcc->excp_model = POWERPC_EXCP_7xx; 3780 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3781 pcc->bfd_mach = bfd_mach_ppc_750; 3782 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3783 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3784 } 3785 3786 static void init_proc_750cx(CPUPPCState *env) 3787 { 3788 register_non_embedded_sprs(env); 3789 register_sdr1_sprs(env); 3790 register_7xx_sprs(env); 3791 3792 spr_register(env, SPR_L2CR, "L2CR", 3793 SPR_NOACCESS, SPR_NOACCESS, 3794 &spr_read_generic, spr_access_nop, 3795 0x00000000); 3796 /* Thermal management */ 3797 register_thrm_sprs(env); 3798 3799 spr_register(env, SPR_SDA, "SDA", 3800 SPR_NOACCESS, SPR_NOACCESS, 3801 &spr_read_generic, &spr_write_generic, 3802 0x00000000); 3803 3804 /* Memory management */ 3805 register_low_BATs(env); 3806 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3807 register_high_BATs(env); 3808 init_excp_750cx(env); 3809 env->dcache_line_size = 32; 3810 env->icache_line_size = 32; 3811 /* Allocate hardware IRQ controller */ 3812 ppc6xx_irq_init(env_archcpu(env)); 3813 } 3814 3815 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3816 { 3817 DeviceClass *dc = DEVICE_CLASS(oc); 3818 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3819 3820 dc->desc = "PowerPC 750CX"; 3821 pcc->init_proc = init_proc_750cx; 3822 pcc->check_pow = check_pow_hid0; 3823 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3824 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3825 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3826 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3827 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3828 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3829 PPC_SEGMENT | PPC_EXTERN; 3830 pcc->msr_mask = (1ull << MSR_POW) | 3831 (1ull << MSR_ILE) | 3832 (1ull << MSR_EE) | 3833 (1ull << MSR_PR) | 3834 (1ull << MSR_FP) | 3835 (1ull << MSR_ME) | 3836 (1ull << MSR_FE0) | 3837 (1ull << MSR_SE) | 3838 (1ull << MSR_DE) | 3839 (1ull << MSR_FE1) | 3840 (1ull << MSR_EP) | 3841 (1ull << MSR_IR) | 3842 (1ull << MSR_DR) | 3843 (1ull << MSR_PMM) | 3844 (1ull << MSR_RI) | 3845 (1ull << MSR_LE); 3846 pcc->mmu_model = POWERPC_MMU_32B; 3847 pcc->excp_model = POWERPC_EXCP_7xx; 3848 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3849 pcc->bfd_mach = bfd_mach_ppc_750; 3850 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3851 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3852 } 3853 3854 static void init_proc_750fx(CPUPPCState *env) 3855 { 3856 register_non_embedded_sprs(env); 3857 register_sdr1_sprs(env); 3858 register_7xx_sprs(env); 3859 3860 spr_register(env, SPR_L2CR, "L2CR", 3861 SPR_NOACCESS, SPR_NOACCESS, 3862 &spr_read_generic, spr_access_nop, 3863 0x00000000); 3864 /* Thermal management */ 3865 register_thrm_sprs(env); 3866 3867 spr_register(env, SPR_750_THRM4, "THRM4", 3868 SPR_NOACCESS, SPR_NOACCESS, 3869 &spr_read_generic, &spr_write_generic, 3870 0x00000000); 3871 /* Hardware implementation registers */ 3872 spr_register(env, SPR_750FX_HID2, "HID2", 3873 SPR_NOACCESS, SPR_NOACCESS, 3874 &spr_read_generic, &spr_write_generic, 3875 0x00000000); 3876 /* Memory management */ 3877 register_low_BATs(env); 3878 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3879 register_high_BATs(env); 3880 init_excp_7x0(env); 3881 env->dcache_line_size = 32; 3882 env->icache_line_size = 32; 3883 /* Allocate hardware IRQ controller */ 3884 ppc6xx_irq_init(env_archcpu(env)); 3885 } 3886 3887 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3888 { 3889 DeviceClass *dc = DEVICE_CLASS(oc); 3890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3891 3892 dc->desc = "PowerPC 750FX"; 3893 pcc->init_proc = init_proc_750fx; 3894 pcc->check_pow = check_pow_hid0; 3895 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3896 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3897 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3898 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3899 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3900 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3901 PPC_SEGMENT | PPC_EXTERN; 3902 pcc->msr_mask = (1ull << MSR_POW) | 3903 (1ull << MSR_ILE) | 3904 (1ull << MSR_EE) | 3905 (1ull << MSR_PR) | 3906 (1ull << MSR_FP) | 3907 (1ull << MSR_ME) | 3908 (1ull << MSR_FE0) | 3909 (1ull << MSR_SE) | 3910 (1ull << MSR_DE) | 3911 (1ull << MSR_FE1) | 3912 (1ull << MSR_EP) | 3913 (1ull << MSR_IR) | 3914 (1ull << MSR_DR) | 3915 (1ull << MSR_PMM) | 3916 (1ull << MSR_RI) | 3917 (1ull << MSR_LE); 3918 pcc->mmu_model = POWERPC_MMU_32B; 3919 pcc->excp_model = POWERPC_EXCP_7xx; 3920 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3921 pcc->bfd_mach = bfd_mach_ppc_750; 3922 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3923 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3924 } 3925 3926 static void init_proc_750gx(CPUPPCState *env) 3927 { 3928 register_non_embedded_sprs(env); 3929 register_sdr1_sprs(env); 3930 register_7xx_sprs(env); 3931 3932 spr_register(env, SPR_L2CR, "L2CR", 3933 SPR_NOACCESS, SPR_NOACCESS, 3934 &spr_read_generic, spr_access_nop, 3935 0x00000000); 3936 /* Thermal management */ 3937 register_thrm_sprs(env); 3938 3939 spr_register(env, SPR_750_THRM4, "THRM4", 3940 SPR_NOACCESS, SPR_NOACCESS, 3941 &spr_read_generic, &spr_write_generic, 3942 0x00000000); 3943 /* Hardware implementation registers */ 3944 spr_register(env, SPR_750FX_HID2, "HID2", 3945 SPR_NOACCESS, SPR_NOACCESS, 3946 &spr_read_generic, &spr_write_generic, 3947 0x00000000); 3948 /* Memory management */ 3949 register_low_BATs(env); 3950 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3951 register_high_BATs(env); 3952 init_excp_7x0(env); 3953 env->dcache_line_size = 32; 3954 env->icache_line_size = 32; 3955 /* Allocate hardware IRQ controller */ 3956 ppc6xx_irq_init(env_archcpu(env)); 3957 } 3958 3959 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 3960 { 3961 DeviceClass *dc = DEVICE_CLASS(oc); 3962 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3963 3964 dc->desc = "PowerPC 750GX"; 3965 pcc->init_proc = init_proc_750gx; 3966 pcc->check_pow = check_pow_hid0; 3967 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3968 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3969 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3970 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3971 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3972 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3973 PPC_SEGMENT | PPC_EXTERN; 3974 pcc->msr_mask = (1ull << MSR_POW) | 3975 (1ull << MSR_ILE) | 3976 (1ull << MSR_EE) | 3977 (1ull << MSR_PR) | 3978 (1ull << MSR_FP) | 3979 (1ull << MSR_ME) | 3980 (1ull << MSR_FE0) | 3981 (1ull << MSR_SE) | 3982 (1ull << MSR_DE) | 3983 (1ull << MSR_FE1) | 3984 (1ull << MSR_EP) | 3985 (1ull << MSR_IR) | 3986 (1ull << MSR_DR) | 3987 (1ull << MSR_PMM) | 3988 (1ull << MSR_RI) | 3989 (1ull << MSR_LE); 3990 pcc->mmu_model = POWERPC_MMU_32B; 3991 pcc->excp_model = POWERPC_EXCP_7xx; 3992 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3993 pcc->bfd_mach = bfd_mach_ppc_750; 3994 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3995 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3996 } 3997 3998 static void init_proc_745(CPUPPCState *env) 3999 { 4000 register_non_embedded_sprs(env); 4001 register_sdr1_sprs(env); 4002 register_7xx_sprs(env); 4003 register_745_sprs(env); 4004 /* Thermal management */ 4005 register_thrm_sprs(env); 4006 4007 /* Memory management */ 4008 register_low_BATs(env); 4009 register_high_BATs(env); 4010 register_6xx_7xx_soft_tlb(env, 64, 2); 4011 init_excp_7x5(env); 4012 env->dcache_line_size = 32; 4013 env->icache_line_size = 32; 4014 /* Allocate hardware IRQ controller */ 4015 ppc6xx_irq_init(env_archcpu(env)); 4016 } 4017 4018 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4019 { 4020 DeviceClass *dc = DEVICE_CLASS(oc); 4021 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4022 4023 dc->desc = "PowerPC 745"; 4024 pcc->init_proc = init_proc_745; 4025 pcc->check_pow = check_pow_hid0; 4026 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4027 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4028 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4029 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4030 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4031 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4032 PPC_SEGMENT | PPC_EXTERN; 4033 pcc->msr_mask = (1ull << MSR_POW) | 4034 (1ull << MSR_ILE) | 4035 (1ull << MSR_EE) | 4036 (1ull << MSR_PR) | 4037 (1ull << MSR_FP) | 4038 (1ull << MSR_ME) | 4039 (1ull << MSR_FE0) | 4040 (1ull << MSR_SE) | 4041 (1ull << MSR_DE) | 4042 (1ull << MSR_FE1) | 4043 (1ull << MSR_EP) | 4044 (1ull << MSR_IR) | 4045 (1ull << MSR_DR) | 4046 (1ull << MSR_PMM) | 4047 (1ull << MSR_RI) | 4048 (1ull << MSR_LE); 4049 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4050 pcc->excp_model = POWERPC_EXCP_7xx; 4051 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4052 pcc->bfd_mach = bfd_mach_ppc_750; 4053 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4054 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4055 } 4056 4057 static void init_proc_755(CPUPPCState *env) 4058 { 4059 init_proc_745(env); 4060 register_755_sprs(env); 4061 } 4062 4063 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4064 { 4065 DeviceClass *dc = DEVICE_CLASS(oc); 4066 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4067 4068 dc->desc = "PowerPC 755"; 4069 pcc->init_proc = init_proc_755; 4070 pcc->check_pow = check_pow_hid0; 4071 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4073 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4074 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4075 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4077 PPC_SEGMENT | PPC_EXTERN; 4078 pcc->msr_mask = (1ull << MSR_POW) | 4079 (1ull << MSR_ILE) | 4080 (1ull << MSR_EE) | 4081 (1ull << MSR_PR) | 4082 (1ull << MSR_FP) | 4083 (1ull << MSR_ME) | 4084 (1ull << MSR_FE0) | 4085 (1ull << MSR_SE) | 4086 (1ull << MSR_DE) | 4087 (1ull << MSR_FE1) | 4088 (1ull << MSR_EP) | 4089 (1ull << MSR_IR) | 4090 (1ull << MSR_DR) | 4091 (1ull << MSR_PMM) | 4092 (1ull << MSR_RI) | 4093 (1ull << MSR_LE); 4094 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4095 pcc->excp_model = POWERPC_EXCP_7xx; 4096 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4097 pcc->bfd_mach = bfd_mach_ppc_750; 4098 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4099 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4100 } 4101 4102 static void init_proc_7400(CPUPPCState *env) 4103 { 4104 register_non_embedded_sprs(env); 4105 register_sdr1_sprs(env); 4106 register_74xx_sprs(env); 4107 vscr_init(env, 0x00010000); 4108 4109 spr_register(env, SPR_UBAMR, "UBAMR", 4110 &spr_read_ureg, SPR_NOACCESS, 4111 &spr_read_ureg, SPR_NOACCESS, 4112 0x00000000); 4113 4114 spr_register(env, SPR_MSSCR1, "MSSCR1", 4115 SPR_NOACCESS, SPR_NOACCESS, 4116 &spr_read_generic, &spr_write_generic, 4117 0x00000000); 4118 /* Thermal management */ 4119 register_thrm_sprs(env); 4120 /* Memory management */ 4121 register_low_BATs(env); 4122 init_excp_7400(env); 4123 env->dcache_line_size = 32; 4124 env->icache_line_size = 32; 4125 /* Allocate hardware IRQ controller */ 4126 ppc6xx_irq_init(env_archcpu(env)); 4127 } 4128 4129 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4130 { 4131 DeviceClass *dc = DEVICE_CLASS(oc); 4132 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4133 4134 dc->desc = "PowerPC 7400 (aka G4)"; 4135 pcc->init_proc = init_proc_7400; 4136 pcc->check_pow = check_pow_hid0; 4137 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4138 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4139 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4140 PPC_FLOAT_STFIWX | 4141 PPC_CACHE | PPC_CACHE_ICBI | 4142 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4143 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4144 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4145 PPC_MEM_TLBIA | 4146 PPC_SEGMENT | PPC_EXTERN | 4147 PPC_ALTIVEC; 4148 pcc->msr_mask = (1ull << MSR_VR) | 4149 (1ull << MSR_POW) | 4150 (1ull << MSR_ILE) | 4151 (1ull << MSR_EE) | 4152 (1ull << MSR_PR) | 4153 (1ull << MSR_FP) | 4154 (1ull << MSR_ME) | 4155 (1ull << MSR_FE0) | 4156 (1ull << MSR_SE) | 4157 (1ull << MSR_DE) | 4158 (1ull << MSR_FE1) | 4159 (1ull << MSR_EP) | 4160 (1ull << MSR_IR) | 4161 (1ull << MSR_DR) | 4162 (1ull << MSR_PMM) | 4163 (1ull << MSR_RI) | 4164 (1ull << MSR_LE); 4165 pcc->mmu_model = POWERPC_MMU_32B; 4166 pcc->excp_model = POWERPC_EXCP_74xx; 4167 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4168 pcc->bfd_mach = bfd_mach_ppc_7400; 4169 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4170 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4171 POWERPC_FLAG_BUS_CLK; 4172 } 4173 4174 static void init_proc_7410(CPUPPCState *env) 4175 { 4176 register_non_embedded_sprs(env); 4177 register_sdr1_sprs(env); 4178 register_74xx_sprs(env); 4179 vscr_init(env, 0x00010000); 4180 4181 spr_register(env, SPR_UBAMR, "UBAMR", 4182 &spr_read_ureg, SPR_NOACCESS, 4183 &spr_read_ureg, SPR_NOACCESS, 4184 0x00000000); 4185 /* Thermal management */ 4186 register_thrm_sprs(env); 4187 /* L2PMCR */ 4188 4189 spr_register(env, SPR_L2PMCR, "L2PMCR", 4190 SPR_NOACCESS, SPR_NOACCESS, 4191 &spr_read_generic, &spr_write_generic, 4192 0x00000000); 4193 /* LDSTDB */ 4194 4195 spr_register(env, SPR_LDSTDB, "LDSTDB", 4196 SPR_NOACCESS, SPR_NOACCESS, 4197 &spr_read_generic, &spr_write_generic, 4198 0x00000000); 4199 /* Memory management */ 4200 register_low_BATs(env); 4201 init_excp_7400(env); 4202 env->dcache_line_size = 32; 4203 env->icache_line_size = 32; 4204 /* Allocate hardware IRQ controller */ 4205 ppc6xx_irq_init(env_archcpu(env)); 4206 } 4207 4208 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4209 { 4210 DeviceClass *dc = DEVICE_CLASS(oc); 4211 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4212 4213 dc->desc = "PowerPC 7410 (aka G4)"; 4214 pcc->init_proc = init_proc_7410; 4215 pcc->check_pow = check_pow_hid0; 4216 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4217 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4218 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4219 PPC_FLOAT_STFIWX | 4220 PPC_CACHE | PPC_CACHE_ICBI | 4221 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4222 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4223 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4224 PPC_MEM_TLBIA | 4225 PPC_SEGMENT | PPC_EXTERN | 4226 PPC_ALTIVEC; 4227 pcc->msr_mask = (1ull << MSR_VR) | 4228 (1ull << MSR_POW) | 4229 (1ull << MSR_ILE) | 4230 (1ull << MSR_EE) | 4231 (1ull << MSR_PR) | 4232 (1ull << MSR_FP) | 4233 (1ull << MSR_ME) | 4234 (1ull << MSR_FE0) | 4235 (1ull << MSR_SE) | 4236 (1ull << MSR_DE) | 4237 (1ull << MSR_FE1) | 4238 (1ull << MSR_EP) | 4239 (1ull << MSR_IR) | 4240 (1ull << MSR_DR) | 4241 (1ull << MSR_PMM) | 4242 (1ull << MSR_RI) | 4243 (1ull << MSR_LE); 4244 pcc->mmu_model = POWERPC_MMU_32B; 4245 pcc->excp_model = POWERPC_EXCP_74xx; 4246 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4247 pcc->bfd_mach = bfd_mach_ppc_7400; 4248 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4249 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4250 POWERPC_FLAG_BUS_CLK; 4251 } 4252 4253 static void init_proc_7440(CPUPPCState *env) 4254 { 4255 register_non_embedded_sprs(env); 4256 register_sdr1_sprs(env); 4257 register_74xx_sprs(env); 4258 vscr_init(env, 0x00010000); 4259 4260 spr_register(env, SPR_UBAMR, "UBAMR", 4261 &spr_read_ureg, SPR_NOACCESS, 4262 &spr_read_ureg, SPR_NOACCESS, 4263 0x00000000); 4264 /* LDSTCR */ 4265 spr_register(env, SPR_LDSTCR, "LDSTCR", 4266 SPR_NOACCESS, SPR_NOACCESS, 4267 &spr_read_generic, &spr_write_generic, 4268 0x00000000); 4269 /* ICTRL */ 4270 spr_register(env, SPR_ICTRL, "ICTRL", 4271 SPR_NOACCESS, SPR_NOACCESS, 4272 &spr_read_generic, &spr_write_generic, 4273 0x00000000); 4274 /* MSSSR0 */ 4275 spr_register(env, SPR_MSSSR0, "MSSSR0", 4276 SPR_NOACCESS, SPR_NOACCESS, 4277 &spr_read_generic, &spr_write_generic, 4278 0x00000000); 4279 /* PMC */ 4280 spr_register(env, SPR_7XX_PMC5, "PMC5", 4281 SPR_NOACCESS, SPR_NOACCESS, 4282 &spr_read_generic, &spr_write_generic, 4283 0x00000000); 4284 4285 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4286 &spr_read_ureg, SPR_NOACCESS, 4287 &spr_read_ureg, SPR_NOACCESS, 4288 0x00000000); 4289 4290 spr_register(env, SPR_7XX_PMC6, "PMC6", 4291 SPR_NOACCESS, SPR_NOACCESS, 4292 &spr_read_generic, &spr_write_generic, 4293 0x00000000); 4294 4295 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4296 &spr_read_ureg, SPR_NOACCESS, 4297 &spr_read_ureg, SPR_NOACCESS, 4298 0x00000000); 4299 /* Memory management */ 4300 register_low_BATs(env); 4301 init_excp_7450(env); 4302 env->dcache_line_size = 32; 4303 env->icache_line_size = 32; 4304 /* Allocate hardware IRQ controller */ 4305 ppc6xx_irq_init(env_archcpu(env)); 4306 } 4307 4308 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4309 { 4310 DeviceClass *dc = DEVICE_CLASS(oc); 4311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4312 4313 dc->desc = "PowerPC 7440 (aka G4)"; 4314 pcc->init_proc = init_proc_7440; 4315 pcc->check_pow = check_pow_hid0_74xx; 4316 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4317 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4318 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4319 PPC_FLOAT_STFIWX | 4320 PPC_CACHE | PPC_CACHE_ICBI | 4321 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4322 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4323 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4324 PPC_MEM_TLBIA | 4325 PPC_SEGMENT | PPC_EXTERN | 4326 PPC_ALTIVEC; 4327 pcc->msr_mask = (1ull << MSR_VR) | 4328 (1ull << MSR_POW) | 4329 (1ull << MSR_ILE) | 4330 (1ull << MSR_EE) | 4331 (1ull << MSR_PR) | 4332 (1ull << MSR_FP) | 4333 (1ull << MSR_ME) | 4334 (1ull << MSR_FE0) | 4335 (1ull << MSR_SE) | 4336 (1ull << MSR_DE) | 4337 (1ull << MSR_FE1) | 4338 (1ull << MSR_EP) | 4339 (1ull << MSR_IR) | 4340 (1ull << MSR_DR) | 4341 (1ull << MSR_PMM) | 4342 (1ull << MSR_RI) | 4343 (1ull << MSR_LE); 4344 pcc->mmu_model = POWERPC_MMU_32B; 4345 pcc->excp_model = POWERPC_EXCP_74xx; 4346 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4347 pcc->bfd_mach = bfd_mach_ppc_7400; 4348 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4349 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4350 POWERPC_FLAG_BUS_CLK; 4351 } 4352 4353 static void init_proc_7450(CPUPPCState *env) 4354 { 4355 register_non_embedded_sprs(env); 4356 register_sdr1_sprs(env); 4357 register_74xx_sprs(env); 4358 vscr_init(env, 0x00010000); 4359 /* Level 3 cache control */ 4360 register_l3_ctrl(env); 4361 /* L3ITCR1 */ 4362 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4363 SPR_NOACCESS, SPR_NOACCESS, 4364 &spr_read_generic, &spr_write_generic, 4365 0x00000000); 4366 /* L3ITCR2 */ 4367 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4368 SPR_NOACCESS, SPR_NOACCESS, 4369 &spr_read_generic, &spr_write_generic, 4370 0x00000000); 4371 /* L3ITCR3 */ 4372 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4373 SPR_NOACCESS, SPR_NOACCESS, 4374 &spr_read_generic, &spr_write_generic, 4375 0x00000000); 4376 /* L3OHCR */ 4377 spr_register(env, SPR_L3OHCR, "L3OHCR", 4378 SPR_NOACCESS, SPR_NOACCESS, 4379 &spr_read_generic, &spr_write_generic, 4380 0x00000000); 4381 4382 spr_register(env, SPR_UBAMR, "UBAMR", 4383 &spr_read_ureg, SPR_NOACCESS, 4384 &spr_read_ureg, SPR_NOACCESS, 4385 0x00000000); 4386 /* LDSTCR */ 4387 spr_register(env, SPR_LDSTCR, "LDSTCR", 4388 SPR_NOACCESS, SPR_NOACCESS, 4389 &spr_read_generic, &spr_write_generic, 4390 0x00000000); 4391 /* ICTRL */ 4392 spr_register(env, SPR_ICTRL, "ICTRL", 4393 SPR_NOACCESS, SPR_NOACCESS, 4394 &spr_read_generic, &spr_write_generic, 4395 0x00000000); 4396 /* MSSSR0 */ 4397 spr_register(env, SPR_MSSSR0, "MSSSR0", 4398 SPR_NOACCESS, SPR_NOACCESS, 4399 &spr_read_generic, &spr_write_generic, 4400 0x00000000); 4401 /* PMC */ 4402 spr_register(env, SPR_7XX_PMC5, "PMC5", 4403 SPR_NOACCESS, SPR_NOACCESS, 4404 &spr_read_generic, &spr_write_generic, 4405 0x00000000); 4406 4407 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4408 &spr_read_ureg, SPR_NOACCESS, 4409 &spr_read_ureg, SPR_NOACCESS, 4410 0x00000000); 4411 4412 spr_register(env, SPR_7XX_PMC6, "PMC6", 4413 SPR_NOACCESS, SPR_NOACCESS, 4414 &spr_read_generic, &spr_write_generic, 4415 0x00000000); 4416 4417 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4418 &spr_read_ureg, SPR_NOACCESS, 4419 &spr_read_ureg, SPR_NOACCESS, 4420 0x00000000); 4421 /* Memory management */ 4422 register_low_BATs(env); 4423 init_excp_7450(env); 4424 env->dcache_line_size = 32; 4425 env->icache_line_size = 32; 4426 /* Allocate hardware IRQ controller */ 4427 ppc6xx_irq_init(env_archcpu(env)); 4428 } 4429 4430 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4431 { 4432 DeviceClass *dc = DEVICE_CLASS(oc); 4433 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4434 4435 dc->desc = "PowerPC 7450 (aka G4)"; 4436 pcc->init_proc = init_proc_7450; 4437 pcc->check_pow = check_pow_hid0_74xx; 4438 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4439 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4440 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4441 PPC_FLOAT_STFIWX | 4442 PPC_CACHE | PPC_CACHE_ICBI | 4443 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4444 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4445 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4446 PPC_MEM_TLBIA | 4447 PPC_SEGMENT | PPC_EXTERN | 4448 PPC_ALTIVEC; 4449 pcc->msr_mask = (1ull << MSR_VR) | 4450 (1ull << MSR_POW) | 4451 (1ull << MSR_ILE) | 4452 (1ull << MSR_EE) | 4453 (1ull << MSR_PR) | 4454 (1ull << MSR_FP) | 4455 (1ull << MSR_ME) | 4456 (1ull << MSR_FE0) | 4457 (1ull << MSR_SE) | 4458 (1ull << MSR_DE) | 4459 (1ull << MSR_FE1) | 4460 (1ull << MSR_EP) | 4461 (1ull << MSR_IR) | 4462 (1ull << MSR_DR) | 4463 (1ull << MSR_PMM) | 4464 (1ull << MSR_RI) | 4465 (1ull << MSR_LE); 4466 pcc->mmu_model = POWERPC_MMU_32B; 4467 pcc->excp_model = POWERPC_EXCP_74xx; 4468 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4469 pcc->bfd_mach = bfd_mach_ppc_7400; 4470 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4471 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4472 POWERPC_FLAG_BUS_CLK; 4473 } 4474 4475 static void init_proc_7445(CPUPPCState *env) 4476 { 4477 register_non_embedded_sprs(env); 4478 register_sdr1_sprs(env); 4479 register_74xx_sprs(env); 4480 vscr_init(env, 0x00010000); 4481 /* LDSTCR */ 4482 spr_register(env, SPR_LDSTCR, "LDSTCR", 4483 SPR_NOACCESS, SPR_NOACCESS, 4484 &spr_read_generic, &spr_write_generic, 4485 0x00000000); 4486 /* ICTRL */ 4487 spr_register(env, SPR_ICTRL, "ICTRL", 4488 SPR_NOACCESS, SPR_NOACCESS, 4489 &spr_read_generic, &spr_write_generic, 4490 0x00000000); 4491 /* MSSSR0 */ 4492 spr_register(env, SPR_MSSSR0, "MSSSR0", 4493 SPR_NOACCESS, SPR_NOACCESS, 4494 &spr_read_generic, &spr_write_generic, 4495 0x00000000); 4496 /* PMC */ 4497 spr_register(env, SPR_7XX_PMC5, "PMC5", 4498 SPR_NOACCESS, SPR_NOACCESS, 4499 &spr_read_generic, &spr_write_generic, 4500 0x00000000); 4501 4502 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4503 &spr_read_ureg, SPR_NOACCESS, 4504 &spr_read_ureg, SPR_NOACCESS, 4505 0x00000000); 4506 4507 spr_register(env, SPR_7XX_PMC6, "PMC6", 4508 SPR_NOACCESS, SPR_NOACCESS, 4509 &spr_read_generic, &spr_write_generic, 4510 0x00000000); 4511 4512 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4513 &spr_read_ureg, SPR_NOACCESS, 4514 &spr_read_ureg, SPR_NOACCESS, 4515 0x00000000); 4516 /* SPRGs */ 4517 spr_register(env, SPR_SPRG4, "SPRG4", 4518 SPR_NOACCESS, SPR_NOACCESS, 4519 &spr_read_generic, &spr_write_generic, 4520 0x00000000); 4521 spr_register(env, SPR_USPRG4, "USPRG4", 4522 &spr_read_ureg, SPR_NOACCESS, 4523 &spr_read_ureg, SPR_NOACCESS, 4524 0x00000000); 4525 spr_register(env, SPR_SPRG5, "SPRG5", 4526 SPR_NOACCESS, SPR_NOACCESS, 4527 &spr_read_generic, &spr_write_generic, 4528 0x00000000); 4529 spr_register(env, SPR_USPRG5, "USPRG5", 4530 &spr_read_ureg, SPR_NOACCESS, 4531 &spr_read_ureg, SPR_NOACCESS, 4532 0x00000000); 4533 spr_register(env, SPR_SPRG6, "SPRG6", 4534 SPR_NOACCESS, SPR_NOACCESS, 4535 &spr_read_generic, &spr_write_generic, 4536 0x00000000); 4537 spr_register(env, SPR_USPRG6, "USPRG6", 4538 &spr_read_ureg, SPR_NOACCESS, 4539 &spr_read_ureg, SPR_NOACCESS, 4540 0x00000000); 4541 spr_register(env, SPR_SPRG7, "SPRG7", 4542 SPR_NOACCESS, SPR_NOACCESS, 4543 &spr_read_generic, &spr_write_generic, 4544 0x00000000); 4545 spr_register(env, SPR_USPRG7, "USPRG7", 4546 &spr_read_ureg, SPR_NOACCESS, 4547 &spr_read_ureg, SPR_NOACCESS, 4548 0x00000000); 4549 /* Memory management */ 4550 register_low_BATs(env); 4551 register_high_BATs(env); 4552 init_excp_7450(env); 4553 env->dcache_line_size = 32; 4554 env->icache_line_size = 32; 4555 /* Allocate hardware IRQ controller */ 4556 ppc6xx_irq_init(env_archcpu(env)); 4557 } 4558 4559 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4560 { 4561 DeviceClass *dc = DEVICE_CLASS(oc); 4562 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4563 4564 dc->desc = "PowerPC 7445 (aka G4)"; 4565 pcc->init_proc = init_proc_7445; 4566 pcc->check_pow = check_pow_hid0_74xx; 4567 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4568 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4569 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4570 PPC_FLOAT_STFIWX | 4571 PPC_CACHE | PPC_CACHE_ICBI | 4572 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4573 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4574 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4575 PPC_MEM_TLBIA | 4576 PPC_SEGMENT | PPC_EXTERN | 4577 PPC_ALTIVEC; 4578 pcc->msr_mask = (1ull << MSR_VR) | 4579 (1ull << MSR_POW) | 4580 (1ull << MSR_ILE) | 4581 (1ull << MSR_EE) | 4582 (1ull << MSR_PR) | 4583 (1ull << MSR_FP) | 4584 (1ull << MSR_ME) | 4585 (1ull << MSR_FE0) | 4586 (1ull << MSR_SE) | 4587 (1ull << MSR_DE) | 4588 (1ull << MSR_FE1) | 4589 (1ull << MSR_EP) | 4590 (1ull << MSR_IR) | 4591 (1ull << MSR_DR) | 4592 (1ull << MSR_PMM) | 4593 (1ull << MSR_RI) | 4594 (1ull << MSR_LE); 4595 pcc->mmu_model = POWERPC_MMU_32B; 4596 pcc->excp_model = POWERPC_EXCP_74xx; 4597 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4598 pcc->bfd_mach = bfd_mach_ppc_7400; 4599 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4600 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4601 POWERPC_FLAG_BUS_CLK; 4602 } 4603 4604 static void init_proc_7455(CPUPPCState *env) 4605 { 4606 register_non_embedded_sprs(env); 4607 register_sdr1_sprs(env); 4608 register_74xx_sprs(env); 4609 vscr_init(env, 0x00010000); 4610 /* Level 3 cache control */ 4611 register_l3_ctrl(env); 4612 /* LDSTCR */ 4613 spr_register(env, SPR_LDSTCR, "LDSTCR", 4614 SPR_NOACCESS, SPR_NOACCESS, 4615 &spr_read_generic, &spr_write_generic, 4616 0x00000000); 4617 /* ICTRL */ 4618 spr_register(env, SPR_ICTRL, "ICTRL", 4619 SPR_NOACCESS, SPR_NOACCESS, 4620 &spr_read_generic, &spr_write_generic, 4621 0x00000000); 4622 /* MSSSR0 */ 4623 spr_register(env, SPR_MSSSR0, "MSSSR0", 4624 SPR_NOACCESS, SPR_NOACCESS, 4625 &spr_read_generic, &spr_write_generic, 4626 0x00000000); 4627 /* PMC */ 4628 spr_register(env, SPR_7XX_PMC5, "PMC5", 4629 SPR_NOACCESS, SPR_NOACCESS, 4630 &spr_read_generic, &spr_write_generic, 4631 0x00000000); 4632 4633 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4634 &spr_read_ureg, SPR_NOACCESS, 4635 &spr_read_ureg, SPR_NOACCESS, 4636 0x00000000); 4637 4638 spr_register(env, SPR_7XX_PMC6, "PMC6", 4639 SPR_NOACCESS, SPR_NOACCESS, 4640 &spr_read_generic, &spr_write_generic, 4641 0x00000000); 4642 4643 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4644 &spr_read_ureg, SPR_NOACCESS, 4645 &spr_read_ureg, SPR_NOACCESS, 4646 0x00000000); 4647 /* SPRGs */ 4648 spr_register(env, SPR_SPRG4, "SPRG4", 4649 SPR_NOACCESS, SPR_NOACCESS, 4650 &spr_read_generic, &spr_write_generic, 4651 0x00000000); 4652 spr_register(env, SPR_USPRG4, "USPRG4", 4653 &spr_read_ureg, SPR_NOACCESS, 4654 &spr_read_ureg, SPR_NOACCESS, 4655 0x00000000); 4656 spr_register(env, SPR_SPRG5, "SPRG5", 4657 SPR_NOACCESS, SPR_NOACCESS, 4658 &spr_read_generic, &spr_write_generic, 4659 0x00000000); 4660 spr_register(env, SPR_USPRG5, "USPRG5", 4661 &spr_read_ureg, SPR_NOACCESS, 4662 &spr_read_ureg, SPR_NOACCESS, 4663 0x00000000); 4664 spr_register(env, SPR_SPRG6, "SPRG6", 4665 SPR_NOACCESS, SPR_NOACCESS, 4666 &spr_read_generic, &spr_write_generic, 4667 0x00000000); 4668 spr_register(env, SPR_USPRG6, "USPRG6", 4669 &spr_read_ureg, SPR_NOACCESS, 4670 &spr_read_ureg, SPR_NOACCESS, 4671 0x00000000); 4672 spr_register(env, SPR_SPRG7, "SPRG7", 4673 SPR_NOACCESS, SPR_NOACCESS, 4674 &spr_read_generic, &spr_write_generic, 4675 0x00000000); 4676 spr_register(env, SPR_USPRG7, "USPRG7", 4677 &spr_read_ureg, SPR_NOACCESS, 4678 &spr_read_ureg, SPR_NOACCESS, 4679 0x00000000); 4680 /* Memory management */ 4681 register_low_BATs(env); 4682 register_high_BATs(env); 4683 init_excp_7450(env); 4684 env->dcache_line_size = 32; 4685 env->icache_line_size = 32; 4686 /* Allocate hardware IRQ controller */ 4687 ppc6xx_irq_init(env_archcpu(env)); 4688 } 4689 4690 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4691 { 4692 DeviceClass *dc = DEVICE_CLASS(oc); 4693 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4694 4695 dc->desc = "PowerPC 7455 (aka G4)"; 4696 pcc->init_proc = init_proc_7455; 4697 pcc->check_pow = check_pow_hid0_74xx; 4698 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4699 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4700 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4701 PPC_FLOAT_STFIWX | 4702 PPC_CACHE | PPC_CACHE_ICBI | 4703 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4704 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4705 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4706 PPC_MEM_TLBIA | 4707 PPC_SEGMENT | PPC_EXTERN | 4708 PPC_ALTIVEC; 4709 pcc->msr_mask = (1ull << MSR_VR) | 4710 (1ull << MSR_POW) | 4711 (1ull << MSR_ILE) | 4712 (1ull << MSR_EE) | 4713 (1ull << MSR_PR) | 4714 (1ull << MSR_FP) | 4715 (1ull << MSR_ME) | 4716 (1ull << MSR_FE0) | 4717 (1ull << MSR_SE) | 4718 (1ull << MSR_DE) | 4719 (1ull << MSR_FE1) | 4720 (1ull << MSR_EP) | 4721 (1ull << MSR_IR) | 4722 (1ull << MSR_DR) | 4723 (1ull << MSR_PMM) | 4724 (1ull << MSR_RI) | 4725 (1ull << MSR_LE); 4726 pcc->mmu_model = POWERPC_MMU_32B; 4727 pcc->excp_model = POWERPC_EXCP_74xx; 4728 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4729 pcc->bfd_mach = bfd_mach_ppc_7400; 4730 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4731 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4732 POWERPC_FLAG_BUS_CLK; 4733 } 4734 4735 static void init_proc_7457(CPUPPCState *env) 4736 { 4737 register_non_embedded_sprs(env); 4738 register_sdr1_sprs(env); 4739 register_74xx_sprs(env); 4740 vscr_init(env, 0x00010000); 4741 /* Level 3 cache control */ 4742 register_l3_ctrl(env); 4743 /* L3ITCR1 */ 4744 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4745 SPR_NOACCESS, SPR_NOACCESS, 4746 &spr_read_generic, &spr_write_generic, 4747 0x00000000); 4748 /* L3ITCR2 */ 4749 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4750 SPR_NOACCESS, SPR_NOACCESS, 4751 &spr_read_generic, &spr_write_generic, 4752 0x00000000); 4753 /* L3ITCR3 */ 4754 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4755 SPR_NOACCESS, SPR_NOACCESS, 4756 &spr_read_generic, &spr_write_generic, 4757 0x00000000); 4758 /* L3OHCR */ 4759 spr_register(env, SPR_L3OHCR, "L3OHCR", 4760 SPR_NOACCESS, SPR_NOACCESS, 4761 &spr_read_generic, &spr_write_generic, 4762 0x00000000); 4763 /* LDSTCR */ 4764 spr_register(env, SPR_LDSTCR, "LDSTCR", 4765 SPR_NOACCESS, SPR_NOACCESS, 4766 &spr_read_generic, &spr_write_generic, 4767 0x00000000); 4768 /* ICTRL */ 4769 spr_register(env, SPR_ICTRL, "ICTRL", 4770 SPR_NOACCESS, SPR_NOACCESS, 4771 &spr_read_generic, &spr_write_generic, 4772 0x00000000); 4773 /* MSSSR0 */ 4774 spr_register(env, SPR_MSSSR0, "MSSSR0", 4775 SPR_NOACCESS, SPR_NOACCESS, 4776 &spr_read_generic, &spr_write_generic, 4777 0x00000000); 4778 /* PMC */ 4779 spr_register(env, SPR_7XX_PMC5, "PMC5", 4780 SPR_NOACCESS, SPR_NOACCESS, 4781 &spr_read_generic, &spr_write_generic, 4782 0x00000000); 4783 4784 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4785 &spr_read_ureg, SPR_NOACCESS, 4786 &spr_read_ureg, SPR_NOACCESS, 4787 0x00000000); 4788 4789 spr_register(env, SPR_7XX_PMC6, "PMC6", 4790 SPR_NOACCESS, SPR_NOACCESS, 4791 &spr_read_generic, &spr_write_generic, 4792 0x00000000); 4793 4794 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4795 &spr_read_ureg, SPR_NOACCESS, 4796 &spr_read_ureg, SPR_NOACCESS, 4797 0x00000000); 4798 /* SPRGs */ 4799 spr_register(env, SPR_SPRG4, "SPRG4", 4800 SPR_NOACCESS, SPR_NOACCESS, 4801 &spr_read_generic, &spr_write_generic, 4802 0x00000000); 4803 spr_register(env, SPR_USPRG4, "USPRG4", 4804 &spr_read_ureg, SPR_NOACCESS, 4805 &spr_read_ureg, SPR_NOACCESS, 4806 0x00000000); 4807 spr_register(env, SPR_SPRG5, "SPRG5", 4808 SPR_NOACCESS, SPR_NOACCESS, 4809 &spr_read_generic, &spr_write_generic, 4810 0x00000000); 4811 spr_register(env, SPR_USPRG5, "USPRG5", 4812 &spr_read_ureg, SPR_NOACCESS, 4813 &spr_read_ureg, SPR_NOACCESS, 4814 0x00000000); 4815 spr_register(env, SPR_SPRG6, "SPRG6", 4816 SPR_NOACCESS, SPR_NOACCESS, 4817 &spr_read_generic, &spr_write_generic, 4818 0x00000000); 4819 spr_register(env, SPR_USPRG6, "USPRG6", 4820 &spr_read_ureg, SPR_NOACCESS, 4821 &spr_read_ureg, SPR_NOACCESS, 4822 0x00000000); 4823 spr_register(env, SPR_SPRG7, "SPRG7", 4824 SPR_NOACCESS, SPR_NOACCESS, 4825 &spr_read_generic, &spr_write_generic, 4826 0x00000000); 4827 spr_register(env, SPR_USPRG7, "USPRG7", 4828 &spr_read_ureg, SPR_NOACCESS, 4829 &spr_read_ureg, SPR_NOACCESS, 4830 0x00000000); 4831 /* Memory management */ 4832 register_low_BATs(env); 4833 register_high_BATs(env); 4834 init_excp_7450(env); 4835 env->dcache_line_size = 32; 4836 env->icache_line_size = 32; 4837 /* Allocate hardware IRQ controller */ 4838 ppc6xx_irq_init(env_archcpu(env)); 4839 } 4840 4841 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4842 { 4843 DeviceClass *dc = DEVICE_CLASS(oc); 4844 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4845 4846 dc->desc = "PowerPC 7457 (aka G4)"; 4847 pcc->init_proc = init_proc_7457; 4848 pcc->check_pow = check_pow_hid0_74xx; 4849 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4850 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4851 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4852 PPC_FLOAT_STFIWX | 4853 PPC_CACHE | PPC_CACHE_ICBI | 4854 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4855 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4856 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4857 PPC_MEM_TLBIA | 4858 PPC_SEGMENT | PPC_EXTERN | 4859 PPC_ALTIVEC; 4860 pcc->msr_mask = (1ull << MSR_VR) | 4861 (1ull << MSR_POW) | 4862 (1ull << MSR_ILE) | 4863 (1ull << MSR_EE) | 4864 (1ull << MSR_PR) | 4865 (1ull << MSR_FP) | 4866 (1ull << MSR_ME) | 4867 (1ull << MSR_FE0) | 4868 (1ull << MSR_SE) | 4869 (1ull << MSR_DE) | 4870 (1ull << MSR_FE1) | 4871 (1ull << MSR_EP) | 4872 (1ull << MSR_IR) | 4873 (1ull << MSR_DR) | 4874 (1ull << MSR_PMM) | 4875 (1ull << MSR_RI) | 4876 (1ull << MSR_LE); 4877 pcc->mmu_model = POWERPC_MMU_32B; 4878 pcc->excp_model = POWERPC_EXCP_74xx; 4879 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4880 pcc->bfd_mach = bfd_mach_ppc_7400; 4881 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4882 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4883 POWERPC_FLAG_BUS_CLK; 4884 } 4885 4886 static void init_proc_e600(CPUPPCState *env) 4887 { 4888 register_non_embedded_sprs(env); 4889 register_sdr1_sprs(env); 4890 register_74xx_sprs(env); 4891 vscr_init(env, 0x00010000); 4892 4893 spr_register(env, SPR_UBAMR, "UBAMR", 4894 &spr_read_ureg, SPR_NOACCESS, 4895 &spr_read_ureg, SPR_NOACCESS, 4896 0x00000000); 4897 4898 spr_register(env, SPR_LDSTCR, "LDSTCR", 4899 SPR_NOACCESS, SPR_NOACCESS, 4900 &spr_read_generic, &spr_write_generic, 4901 0x00000000); 4902 4903 spr_register(env, SPR_ICTRL, "ICTRL", 4904 SPR_NOACCESS, SPR_NOACCESS, 4905 &spr_read_generic, &spr_write_generic, 4906 0x00000000); 4907 4908 spr_register(env, SPR_MSSSR0, "MSSSR0", 4909 SPR_NOACCESS, SPR_NOACCESS, 4910 &spr_read_generic, &spr_write_generic, 4911 0x00000000); 4912 4913 spr_register(env, SPR_7XX_PMC5, "PMC5", 4914 SPR_NOACCESS, SPR_NOACCESS, 4915 &spr_read_generic, &spr_write_generic, 4916 0x00000000); 4917 4918 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4919 &spr_read_ureg, SPR_NOACCESS, 4920 &spr_read_ureg, SPR_NOACCESS, 4921 0x00000000); 4922 4923 spr_register(env, SPR_7XX_PMC6, "PMC6", 4924 SPR_NOACCESS, SPR_NOACCESS, 4925 &spr_read_generic, &spr_write_generic, 4926 0x00000000); 4927 4928 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4929 &spr_read_ureg, SPR_NOACCESS, 4930 &spr_read_ureg, SPR_NOACCESS, 4931 0x00000000); 4932 /* SPRGs */ 4933 spr_register(env, SPR_SPRG4, "SPRG4", 4934 SPR_NOACCESS, SPR_NOACCESS, 4935 &spr_read_generic, &spr_write_generic, 4936 0x00000000); 4937 spr_register(env, SPR_USPRG4, "USPRG4", 4938 &spr_read_ureg, SPR_NOACCESS, 4939 &spr_read_ureg, SPR_NOACCESS, 4940 0x00000000); 4941 spr_register(env, SPR_SPRG5, "SPRG5", 4942 SPR_NOACCESS, SPR_NOACCESS, 4943 &spr_read_generic, &spr_write_generic, 4944 0x00000000); 4945 spr_register(env, SPR_USPRG5, "USPRG5", 4946 &spr_read_ureg, SPR_NOACCESS, 4947 &spr_read_ureg, SPR_NOACCESS, 4948 0x00000000); 4949 spr_register(env, SPR_SPRG6, "SPRG6", 4950 SPR_NOACCESS, SPR_NOACCESS, 4951 &spr_read_generic, &spr_write_generic, 4952 0x00000000); 4953 spr_register(env, SPR_USPRG6, "USPRG6", 4954 &spr_read_ureg, SPR_NOACCESS, 4955 &spr_read_ureg, SPR_NOACCESS, 4956 0x00000000); 4957 spr_register(env, SPR_SPRG7, "SPRG7", 4958 SPR_NOACCESS, SPR_NOACCESS, 4959 &spr_read_generic, &spr_write_generic, 4960 0x00000000); 4961 spr_register(env, SPR_USPRG7, "USPRG7", 4962 &spr_read_ureg, SPR_NOACCESS, 4963 &spr_read_ureg, SPR_NOACCESS, 4964 0x00000000); 4965 /* Memory management */ 4966 register_low_BATs(env); 4967 register_high_BATs(env); 4968 init_excp_7450(env); 4969 env->dcache_line_size = 32; 4970 env->icache_line_size = 32; 4971 /* Allocate hardware IRQ controller */ 4972 ppc6xx_irq_init(env_archcpu(env)); 4973 } 4974 4975 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 4976 { 4977 DeviceClass *dc = DEVICE_CLASS(oc); 4978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4979 4980 dc->desc = "PowerPC e600"; 4981 pcc->init_proc = init_proc_e600; 4982 pcc->check_pow = check_pow_hid0_74xx; 4983 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4984 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4985 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4986 PPC_FLOAT_STFIWX | 4987 PPC_CACHE | PPC_CACHE_ICBI | 4988 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4989 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4990 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4991 PPC_MEM_TLBIA | 4992 PPC_SEGMENT | PPC_EXTERN | 4993 PPC_ALTIVEC; 4994 pcc->insns_flags2 = PPC_NONE; 4995 pcc->msr_mask = (1ull << MSR_VR) | 4996 (1ull << MSR_POW) | 4997 (1ull << MSR_ILE) | 4998 (1ull << MSR_EE) | 4999 (1ull << MSR_PR) | 5000 (1ull << MSR_FP) | 5001 (1ull << MSR_ME) | 5002 (1ull << MSR_FE0) | 5003 (1ull << MSR_SE) | 5004 (1ull << MSR_DE) | 5005 (1ull << MSR_FE1) | 5006 (1ull << MSR_EP) | 5007 (1ull << MSR_IR) | 5008 (1ull << MSR_DR) | 5009 (1ull << MSR_PMM) | 5010 (1ull << MSR_RI) | 5011 (1ull << MSR_LE); 5012 pcc->mmu_model = POWERPC_MMU_32B; 5013 pcc->excp_model = POWERPC_EXCP_74xx; 5014 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5015 pcc->bfd_mach = bfd_mach_ppc_7400; 5016 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5017 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5018 POWERPC_FLAG_BUS_CLK; 5019 } 5020 5021 #if defined(TARGET_PPC64) 5022 #if defined(CONFIG_USER_ONLY) 5023 #define POWERPC970_HID5_INIT 0x00000080 5024 #else 5025 #define POWERPC970_HID5_INIT 0x00000000 5026 #endif 5027 5028 static int check_pow_970(CPUPPCState *env) 5029 { 5030 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5031 return 1; 5032 } 5033 5034 return 0; 5035 } 5036 5037 static void register_970_hid_sprs(CPUPPCState *env) 5038 { 5039 /* Hardware implementation registers */ 5040 spr_register(env, SPR_HID0, "HID0", 5041 SPR_NOACCESS, SPR_NOACCESS, 5042 &spr_read_generic, &spr_write_clear, 5043 0x60000000); 5044 spr_register(env, SPR_HID1, "HID1", 5045 SPR_NOACCESS, SPR_NOACCESS, 5046 &spr_read_generic, &spr_write_generic, 5047 0x00000000); 5048 spr_register(env, SPR_970_HID5, "HID5", 5049 SPR_NOACCESS, SPR_NOACCESS, 5050 &spr_read_generic, &spr_write_generic, 5051 POWERPC970_HID5_INIT); 5052 } 5053 5054 static void register_970_hior_sprs(CPUPPCState *env) 5055 { 5056 spr_register(env, SPR_HIOR, "SPR_HIOR", 5057 SPR_NOACCESS, SPR_NOACCESS, 5058 &spr_read_hior, &spr_write_hior, 5059 0x00000000); 5060 } 5061 5062 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5063 { 5064 spr_register(env, SPR_CTRL, "SPR_CTRL", 5065 SPR_NOACCESS, SPR_NOACCESS, 5066 SPR_NOACCESS, &spr_write_CTRL, 5067 0x00000000); 5068 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5069 &spr_read_ureg, SPR_NOACCESS, 5070 &spr_read_ureg, SPR_NOACCESS, 5071 0x00000000); 5072 } 5073 5074 static void register_book3s_altivec_sprs(CPUPPCState *env) 5075 { 5076 if (!(env->insns_flags & PPC_ALTIVEC)) { 5077 return; 5078 } 5079 5080 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5081 &spr_read_generic, &spr_write_generic, 5082 &spr_read_generic, &spr_write_generic, 5083 KVM_REG_PPC_VRSAVE, 0x00000000); 5084 5085 } 5086 5087 static void register_book3s_dbg_sprs(CPUPPCState *env) 5088 { 5089 /* 5090 * TODO: different specs define different scopes for these, 5091 * will have to address this: 5092 * 970: super/write and super/read 5093 * powerisa 2.03..2.04: hypv/write and super/read. 5094 * powerisa 2.05 and newer: hypv/write and hypv/read. 5095 */ 5096 spr_register_kvm(env, SPR_DABR, "DABR", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_generic, &spr_write_generic, 5099 KVM_REG_PPC_DABR, 0x00000000); 5100 spr_register_kvm(env, SPR_DABRX, "DABRX", 5101 SPR_NOACCESS, SPR_NOACCESS, 5102 &spr_read_generic, &spr_write_generic, 5103 KVM_REG_PPC_DABRX, 0x00000000); 5104 } 5105 5106 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5107 { 5108 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5109 SPR_NOACCESS, SPR_NOACCESS, 5110 SPR_NOACCESS, SPR_NOACCESS, 5111 &spr_read_generic, &spr_write_generic, 5112 KVM_REG_PPC_DAWR, 0x00000000); 5113 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5114 SPR_NOACCESS, SPR_NOACCESS, 5115 SPR_NOACCESS, SPR_NOACCESS, 5116 &spr_read_generic, &spr_write_generic, 5117 KVM_REG_PPC_DAWRX, 0x00000000); 5118 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5119 SPR_NOACCESS, SPR_NOACCESS, 5120 SPR_NOACCESS, SPR_NOACCESS, 5121 &spr_read_generic, &spr_write_generic, 5122 KVM_REG_PPC_CIABR, 0x00000000); 5123 } 5124 5125 static void register_970_dbg_sprs(CPUPPCState *env) 5126 { 5127 /* Breakpoints */ 5128 spr_register(env, SPR_IABR, "IABR", 5129 SPR_NOACCESS, SPR_NOACCESS, 5130 &spr_read_generic, &spr_write_generic, 5131 0x00000000); 5132 } 5133 5134 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5135 { 5136 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5137 SPR_NOACCESS, SPR_NOACCESS, 5138 &spr_read_generic, &spr_write_MMCR0, 5139 KVM_REG_PPC_MMCR0, 0x80000000); 5140 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5141 SPR_NOACCESS, SPR_NOACCESS, 5142 &spr_read_generic, &spr_write_MMCR1, 5143 KVM_REG_PPC_MMCR1, 0x00000000); 5144 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5145 SPR_NOACCESS, SPR_NOACCESS, 5146 &spr_read_generic, &spr_write_generic, 5147 KVM_REG_PPC_MMCRA, 0x00000000); 5148 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5149 SPR_NOACCESS, SPR_NOACCESS, 5150 &spr_read_PMC, &spr_write_PMC, 5151 KVM_REG_PPC_PMC1, 0x00000000); 5152 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5153 SPR_NOACCESS, SPR_NOACCESS, 5154 &spr_read_PMC, &spr_write_PMC, 5155 KVM_REG_PPC_PMC2, 0x00000000); 5156 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5157 SPR_NOACCESS, SPR_NOACCESS, 5158 &spr_read_PMC, &spr_write_PMC, 5159 KVM_REG_PPC_PMC3, 0x00000000); 5160 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5161 SPR_NOACCESS, SPR_NOACCESS, 5162 &spr_read_PMC, &spr_write_PMC, 5163 KVM_REG_PPC_PMC4, 0x00000000); 5164 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5165 SPR_NOACCESS, SPR_NOACCESS, 5166 &spr_read_PMC, &spr_write_PMC, 5167 KVM_REG_PPC_PMC5, 0x00000000); 5168 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_PMC, &spr_write_PMC, 5171 KVM_REG_PPC_PMC6, 0x00000000); 5172 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5173 SPR_NOACCESS, SPR_NOACCESS, 5174 &spr_read_generic, &spr_write_generic, 5175 KVM_REG_PPC_SIAR, 0x00000000); 5176 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5177 SPR_NOACCESS, SPR_NOACCESS, 5178 &spr_read_generic, &spr_write_generic, 5179 KVM_REG_PPC_SDAR, 0x00000000); 5180 } 5181 5182 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5183 { 5184 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5185 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5186 &spr_read_ureg, &spr_write_ureg, 5187 0x80000000); 5188 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5189 &spr_read_ureg, SPR_NOACCESS, 5190 &spr_read_ureg, &spr_write_ureg, 5191 0x00000000); 5192 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5193 &spr_read_ureg, SPR_NOACCESS, 5194 &spr_read_ureg, &spr_write_ureg, 5195 0x00000000); 5196 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5197 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5198 &spr_read_ureg, &spr_write_ureg, 5199 0x00000000); 5200 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5201 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5202 &spr_read_ureg, &spr_write_ureg, 5203 0x00000000); 5204 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5205 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5206 &spr_read_ureg, &spr_write_ureg, 5207 0x00000000); 5208 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5209 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5210 &spr_read_ureg, &spr_write_ureg, 5211 0x00000000); 5212 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5213 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5214 &spr_read_ureg, &spr_write_ureg, 5215 0x00000000); 5216 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5217 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5218 &spr_read_ureg, &spr_write_ureg, 5219 0x00000000); 5220 spr_register(env, SPR_POWER_USIAR, "USIAR", 5221 &spr_read_ureg, SPR_NOACCESS, 5222 &spr_read_ureg, &spr_write_ureg, 5223 0x00000000); 5224 spr_register(env, SPR_POWER_USDAR, "USDAR", 5225 &spr_read_ureg, SPR_NOACCESS, 5226 &spr_read_ureg, &spr_write_ureg, 5227 0x00000000); 5228 } 5229 5230 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5231 { 5232 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5233 SPR_NOACCESS, SPR_NOACCESS, 5234 &spr_read_generic, &spr_write_generic, 5235 KVM_REG_PPC_PMC7, 0x00000000); 5236 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5237 SPR_NOACCESS, SPR_NOACCESS, 5238 &spr_read_generic, &spr_write_generic, 5239 KVM_REG_PPC_PMC8, 0x00000000); 5240 } 5241 5242 static void register_970_pmu_user_sprs(CPUPPCState *env) 5243 { 5244 spr_register(env, SPR_970_UPMC7, "UPMC7", 5245 &spr_read_ureg, SPR_NOACCESS, 5246 &spr_read_ureg, &spr_write_ureg, 5247 0x00000000); 5248 spr_register(env, SPR_970_UPMC8, "UPMC8", 5249 &spr_read_ureg, SPR_NOACCESS, 5250 &spr_read_ureg, &spr_write_ureg, 5251 0x00000000); 5252 } 5253 5254 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5255 { 5256 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5257 SPR_NOACCESS, SPR_NOACCESS, 5258 &spr_read_generic, &spr_write_generic, 5259 KVM_REG_PPC_MMCR2, 0x00000000); 5260 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5261 SPR_NOACCESS, SPR_NOACCESS, 5262 &spr_read_generic, &spr_write_generic, 5263 KVM_REG_PPC_MMCRS, 0x00000000); 5264 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5265 SPR_NOACCESS, SPR_NOACCESS, 5266 &spr_read_generic, &spr_write_generic, 5267 KVM_REG_PPC_SIER, 0x00000000); 5268 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5269 SPR_NOACCESS, SPR_NOACCESS, 5270 &spr_read_generic, &spr_write_generic, 5271 KVM_REG_PPC_SPMC1, 0x00000000); 5272 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5273 SPR_NOACCESS, SPR_NOACCESS, 5274 &spr_read_generic, &spr_write_generic, 5275 KVM_REG_PPC_SPMC2, 0x00000000); 5276 spr_register_kvm(env, SPR_TACR, "TACR", 5277 SPR_NOACCESS, SPR_NOACCESS, 5278 &spr_read_generic, &spr_write_generic, 5279 KVM_REG_PPC_TACR, 0x00000000); 5280 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5281 SPR_NOACCESS, SPR_NOACCESS, 5282 &spr_read_generic, &spr_write_generic, 5283 KVM_REG_PPC_TCSCR, 0x00000000); 5284 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5285 SPR_NOACCESS, SPR_NOACCESS, 5286 &spr_read_generic, &spr_write_generic, 5287 KVM_REG_PPC_CSIGR, 0x00000000); 5288 } 5289 5290 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5291 { 5292 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5293 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5294 &spr_read_ureg, &spr_write_ureg, 5295 0x00000000); 5296 spr_register(env, SPR_POWER_USIER, "USIER", 5297 &spr_read_generic, SPR_NOACCESS, 5298 &spr_read_generic, &spr_write_generic, 5299 0x00000000); 5300 } 5301 5302 static void register_power5p_ear_sprs(CPUPPCState *env) 5303 { 5304 /* External access control */ 5305 spr_register(env, SPR_EAR, "EAR", 5306 SPR_NOACCESS, SPR_NOACCESS, 5307 &spr_read_generic, &spr_write_generic, 5308 0x00000000); 5309 } 5310 5311 static void register_power5p_tb_sprs(CPUPPCState *env) 5312 { 5313 /* TBU40 (High 40 bits of the Timebase register */ 5314 spr_register_hv(env, SPR_TBU40, "TBU40", 5315 SPR_NOACCESS, SPR_NOACCESS, 5316 SPR_NOACCESS, SPR_NOACCESS, 5317 SPR_NOACCESS, &spr_write_tbu40, 5318 0x00000000); 5319 } 5320 5321 static void register_970_lpar_sprs(CPUPPCState *env) 5322 { 5323 #if !defined(CONFIG_USER_ONLY) 5324 /* 5325 * PPC970: HID4 covers things later controlled by the LPCR and 5326 * RMOR in later CPUs, but with a different encoding. We only 5327 * support the 970 in "Apple mode" which has all hypervisor 5328 * facilities disabled by strapping, so we can basically just 5329 * ignore it 5330 */ 5331 spr_register(env, SPR_970_HID4, "HID4", 5332 SPR_NOACCESS, SPR_NOACCESS, 5333 &spr_read_generic, &spr_write_generic, 5334 0x00000000); 5335 #endif 5336 } 5337 5338 static void register_power5p_lpar_sprs(CPUPPCState *env) 5339 { 5340 #if !defined(CONFIG_USER_ONLY) 5341 /* Logical partitionning */ 5342 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5343 SPR_NOACCESS, SPR_NOACCESS, 5344 SPR_NOACCESS, SPR_NOACCESS, 5345 &spr_read_generic, &spr_write_lpcr, 5346 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5347 spr_register_hv(env, SPR_HDEC, "HDEC", 5348 SPR_NOACCESS, SPR_NOACCESS, 5349 SPR_NOACCESS, SPR_NOACCESS, 5350 &spr_read_hdecr, &spr_write_hdecr, 0); 5351 #endif 5352 } 5353 5354 static void register_book3s_ids_sprs(CPUPPCState *env) 5355 { 5356 /* FIXME: Will need to deal with thread vs core only SPRs */ 5357 5358 /* Processor identification */ 5359 spr_register_hv(env, SPR_PIR, "PIR", 5360 SPR_NOACCESS, SPR_NOACCESS, 5361 &spr_read_generic, SPR_NOACCESS, 5362 &spr_read_generic, NULL, 5363 0x00000000); 5364 spr_register_hv(env, SPR_HID0, "HID0", 5365 SPR_NOACCESS, SPR_NOACCESS, 5366 SPR_NOACCESS, SPR_NOACCESS, 5367 &spr_read_generic, &spr_write_generic, 5368 0x00000000); 5369 spr_register_hv(env, SPR_TSCR, "TSCR", 5370 SPR_NOACCESS, SPR_NOACCESS, 5371 SPR_NOACCESS, SPR_NOACCESS, 5372 &spr_read_generic, &spr_write_generic, 5373 0x00000000); 5374 spr_register_hv(env, SPR_HMER, "HMER", 5375 SPR_NOACCESS, SPR_NOACCESS, 5376 SPR_NOACCESS, SPR_NOACCESS, 5377 &spr_read_generic, &spr_write_hmer, 5378 0x00000000); 5379 spr_register_hv(env, SPR_HMEER, "HMEER", 5380 SPR_NOACCESS, SPR_NOACCESS, 5381 SPR_NOACCESS, SPR_NOACCESS, 5382 &spr_read_generic, &spr_write_generic, 5383 0x00000000); 5384 spr_register_hv(env, SPR_TFMR, "TFMR", 5385 SPR_NOACCESS, SPR_NOACCESS, 5386 SPR_NOACCESS, SPR_NOACCESS, 5387 &spr_read_generic, &spr_write_generic, 5388 0x00000000); 5389 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5390 SPR_NOACCESS, SPR_NOACCESS, 5391 SPR_NOACCESS, SPR_NOACCESS, 5392 &spr_read_generic, &spr_write_lpidr, 5393 0x00000000); 5394 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5395 SPR_NOACCESS, SPR_NOACCESS, 5396 SPR_NOACCESS, SPR_NOACCESS, 5397 &spr_read_generic, &spr_write_generic, 5398 0x00000000); 5399 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5400 SPR_NOACCESS, SPR_NOACCESS, 5401 SPR_NOACCESS, SPR_NOACCESS, 5402 &spr_read_generic, &spr_write_generic, 5403 0x00000000); 5404 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5405 SPR_NOACCESS, SPR_NOACCESS, 5406 SPR_NOACCESS, SPR_NOACCESS, 5407 &spr_read_generic, &spr_write_generic, 5408 0x00000000); 5409 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5410 SPR_NOACCESS, SPR_NOACCESS, 5411 SPR_NOACCESS, SPR_NOACCESS, 5412 &spr_read_generic, &spr_write_generic, 5413 0x00000000); 5414 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5415 SPR_NOACCESS, SPR_NOACCESS, 5416 SPR_NOACCESS, SPR_NOACCESS, 5417 &spr_read_generic, &spr_write_generic, 5418 0x00000000); 5419 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5420 SPR_NOACCESS, SPR_NOACCESS, 5421 SPR_NOACCESS, SPR_NOACCESS, 5422 &spr_read_generic, &spr_write_generic, 5423 0x00000000); 5424 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5425 SPR_NOACCESS, SPR_NOACCESS, 5426 SPR_NOACCESS, SPR_NOACCESS, 5427 &spr_read_generic, &spr_write_generic, 5428 0x00000000); 5429 spr_register_hv(env, SPR_HDAR, "HDAR", 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 SPR_NOACCESS, SPR_NOACCESS, 5432 &spr_read_generic, &spr_write_generic, 5433 0x00000000); 5434 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5435 SPR_NOACCESS, SPR_NOACCESS, 5436 SPR_NOACCESS, SPR_NOACCESS, 5437 &spr_read_generic, &spr_write_generic, 5438 0x00000000); 5439 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5440 SPR_NOACCESS, SPR_NOACCESS, 5441 SPR_NOACCESS, SPR_NOACCESS, 5442 &spr_read_generic, &spr_write_generic, 5443 0x00000000); 5444 } 5445 5446 static void register_rmor_sprs(CPUPPCState *env) 5447 { 5448 spr_register_hv(env, SPR_RMOR, "RMOR", 5449 SPR_NOACCESS, SPR_NOACCESS, 5450 SPR_NOACCESS, SPR_NOACCESS, 5451 &spr_read_generic, &spr_write_generic, 5452 0x00000000); 5453 } 5454 5455 static void register_power8_ids_sprs(CPUPPCState *env) 5456 { 5457 /* Thread identification */ 5458 spr_register(env, SPR_TIR, "TIR", 5459 SPR_NOACCESS, SPR_NOACCESS, 5460 &spr_read_generic, SPR_NOACCESS, 5461 0x00000000); 5462 } 5463 5464 static void register_book3s_purr_sprs(CPUPPCState *env) 5465 { 5466 #if !defined(CONFIG_USER_ONLY) 5467 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5468 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5469 &spr_read_purr, SPR_NOACCESS, 5470 &spr_read_purr, SPR_NOACCESS, 5471 &spr_read_purr, &spr_write_purr, 5472 KVM_REG_PPC_PURR, 0x00000000); 5473 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5474 &spr_read_purr, SPR_NOACCESS, 5475 &spr_read_purr, SPR_NOACCESS, 5476 &spr_read_purr, &spr_write_purr, 5477 KVM_REG_PPC_SPURR, 0x00000000); 5478 #endif 5479 } 5480 5481 static void register_power6_dbg_sprs(CPUPPCState *env) 5482 { 5483 #if !defined(CONFIG_USER_ONLY) 5484 spr_register(env, SPR_CFAR, "SPR_CFAR", 5485 SPR_NOACCESS, SPR_NOACCESS, 5486 &spr_read_cfar, &spr_write_cfar, 5487 0x00000000); 5488 #endif 5489 } 5490 5491 static void register_power5p_common_sprs(CPUPPCState *env) 5492 { 5493 spr_register_kvm(env, SPR_PPR, "PPR", 5494 &spr_read_generic, &spr_write_generic, 5495 &spr_read_generic, &spr_write_generic, 5496 KVM_REG_PPC_PPR, 0x00000000); 5497 } 5498 5499 static void register_power6_common_sprs(CPUPPCState *env) 5500 { 5501 #if !defined(CONFIG_USER_ONLY) 5502 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 5503 SPR_NOACCESS, SPR_NOACCESS, 5504 &spr_read_generic, &spr_write_generic, 5505 KVM_REG_PPC_DSCR, 0x00000000); 5506 #endif 5507 /* 5508 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5509 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5510 */ 5511 spr_register_hv(env, SPR_PCR, "PCR", 5512 SPR_NOACCESS, SPR_NOACCESS, 5513 SPR_NOACCESS, SPR_NOACCESS, 5514 &spr_read_generic, &spr_write_pcr, 5515 0x00000000); 5516 } 5517 5518 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5519 { 5520 spr_register_kvm(env, SPR_TAR, "TAR", 5521 &spr_read_tar, &spr_write_tar, 5522 &spr_read_generic, &spr_write_generic, 5523 KVM_REG_PPC_TAR, 0x00000000); 5524 } 5525 5526 static void register_power8_tm_sprs(CPUPPCState *env) 5527 { 5528 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5529 &spr_read_tm, &spr_write_tm, 5530 &spr_read_tm, &spr_write_tm, 5531 KVM_REG_PPC_TFHAR, 0x00000000); 5532 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5533 &spr_read_tm, &spr_write_tm, 5534 &spr_read_tm, &spr_write_tm, 5535 KVM_REG_PPC_TFIAR, 0x00000000); 5536 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5537 &spr_read_tm, &spr_write_tm, 5538 &spr_read_tm, &spr_write_tm, 5539 KVM_REG_PPC_TEXASR, 0x00000000); 5540 spr_register(env, SPR_TEXASRU, "TEXASRU", 5541 &spr_read_tm_upper32, &spr_write_tm_upper32, 5542 &spr_read_tm_upper32, &spr_write_tm_upper32, 5543 0x00000000); 5544 } 5545 5546 static void register_power8_ebb_sprs(CPUPPCState *env) 5547 { 5548 spr_register(env, SPR_BESCRS, "BESCRS", 5549 &spr_read_ebb, &spr_write_ebb, 5550 &spr_read_generic, &spr_write_generic, 5551 0x00000000); 5552 spr_register(env, SPR_BESCRSU, "BESCRSU", 5553 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5554 &spr_read_prev_upper32, &spr_write_prev_upper32, 5555 0x00000000); 5556 spr_register(env, SPR_BESCRR, "BESCRR", 5557 &spr_read_ebb, &spr_write_ebb, 5558 &spr_read_generic, &spr_write_generic, 5559 0x00000000); 5560 spr_register(env, SPR_BESCRRU, "BESCRRU", 5561 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5562 &spr_read_prev_upper32, &spr_write_prev_upper32, 5563 0x00000000); 5564 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5565 &spr_read_ebb, &spr_write_ebb, 5566 &spr_read_generic, &spr_write_generic, 5567 KVM_REG_PPC_EBBHR, 0x00000000); 5568 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5569 &spr_read_ebb, &spr_write_ebb, 5570 &spr_read_generic, &spr_write_generic, 5571 KVM_REG_PPC_EBBRR, 0x00000000); 5572 spr_register_kvm(env, SPR_BESCR, "BESCR", 5573 &spr_read_ebb, &spr_write_ebb, 5574 &spr_read_generic, &spr_write_generic, 5575 KVM_REG_PPC_BESCR, 0x00000000); 5576 } 5577 5578 /* Virtual Time Base */ 5579 static void register_vtb_sprs(CPUPPCState *env) 5580 { 5581 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5582 SPR_NOACCESS, SPR_NOACCESS, 5583 &spr_read_vtb, SPR_NOACCESS, 5584 &spr_read_vtb, &spr_write_vtb, 5585 KVM_REG_PPC_VTB, 0x00000000); 5586 } 5587 5588 static void register_power8_fscr_sprs(CPUPPCState *env) 5589 { 5590 #if defined(CONFIG_USER_ONLY) 5591 target_ulong initval = 1ULL << FSCR_TAR; 5592 #else 5593 target_ulong initval = 0; 5594 #endif 5595 spr_register_kvm(env, SPR_FSCR, "FSCR", 5596 SPR_NOACCESS, SPR_NOACCESS, 5597 &spr_read_generic, &spr_write_generic, 5598 KVM_REG_PPC_FSCR, initval); 5599 } 5600 5601 static void register_power8_pspb_sprs(CPUPPCState *env) 5602 { 5603 spr_register_kvm(env, SPR_PSPB, "PSPB", 5604 SPR_NOACCESS, SPR_NOACCESS, 5605 &spr_read_generic, &spr_write_generic32, 5606 KVM_REG_PPC_PSPB, 0); 5607 } 5608 5609 static void register_power8_dpdes_sprs(CPUPPCState *env) 5610 { 5611 #if !defined(CONFIG_USER_ONLY) 5612 /* Directed Privileged Door-bell Exception State, used for IPI */ 5613 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5614 SPR_NOACCESS, SPR_NOACCESS, 5615 &spr_read_dpdes, SPR_NOACCESS, 5616 &spr_read_dpdes, &spr_write_dpdes, 5617 KVM_REG_PPC_DPDES, 0x00000000); 5618 #endif 5619 } 5620 5621 static void register_power8_ic_sprs(CPUPPCState *env) 5622 { 5623 #if !defined(CONFIG_USER_ONLY) 5624 spr_register_hv(env, SPR_IC, "IC", 5625 SPR_NOACCESS, SPR_NOACCESS, 5626 &spr_read_generic, SPR_NOACCESS, 5627 &spr_read_generic, &spr_write_generic, 5628 0); 5629 #endif 5630 } 5631 5632 static void register_power8_book4_sprs(CPUPPCState *env) 5633 { 5634 /* Add a number of P8 book4 registers */ 5635 #if !defined(CONFIG_USER_ONLY) 5636 spr_register_kvm(env, SPR_ACOP, "ACOP", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_generic, &spr_write_generic, 5639 KVM_REG_PPC_ACOP, 0); 5640 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 5641 SPR_NOACCESS, SPR_NOACCESS, 5642 &spr_read_generic, &spr_write_pidr, 5643 KVM_REG_PPC_PID, 0); 5644 spr_register_kvm(env, SPR_WORT, "WORT", 5645 SPR_NOACCESS, SPR_NOACCESS, 5646 &spr_read_generic, &spr_write_generic, 5647 KVM_REG_PPC_WORT, 0); 5648 #endif 5649 } 5650 5651 static void register_power7_book4_sprs(CPUPPCState *env) 5652 { 5653 /* Add a number of P7 book4 registers */ 5654 #if !defined(CONFIG_USER_ONLY) 5655 spr_register_kvm(env, SPR_ACOP, "ACOP", 5656 SPR_NOACCESS, SPR_NOACCESS, 5657 &spr_read_generic, &spr_write_generic, 5658 KVM_REG_PPC_ACOP, 0); 5659 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 5660 SPR_NOACCESS, SPR_NOACCESS, 5661 &spr_read_generic, &spr_write_generic, 5662 KVM_REG_PPC_PID, 0); 5663 #endif 5664 } 5665 5666 static void register_power8_rpr_sprs(CPUPPCState *env) 5667 { 5668 #if !defined(CONFIG_USER_ONLY) 5669 spr_register_hv(env, SPR_RPR, "RPR", 5670 SPR_NOACCESS, SPR_NOACCESS, 5671 SPR_NOACCESS, SPR_NOACCESS, 5672 &spr_read_generic, &spr_write_generic, 5673 0x00000103070F1F3F); 5674 #endif 5675 } 5676 5677 static void register_power9_mmu_sprs(CPUPPCState *env) 5678 { 5679 #if !defined(CONFIG_USER_ONLY) 5680 /* Partition Table Control */ 5681 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5682 SPR_NOACCESS, SPR_NOACCESS, 5683 SPR_NOACCESS, SPR_NOACCESS, 5684 &spr_read_generic, &spr_write_ptcr, 5685 KVM_REG_PPC_PTCR, 0x00000000); 5686 /* Address Segment Descriptor Register */ 5687 spr_register_hv(env, SPR_ASDR, "ASDR", 5688 SPR_NOACCESS, SPR_NOACCESS, 5689 SPR_NOACCESS, SPR_NOACCESS, 5690 &spr_read_generic, &spr_write_generic, 5691 0x0000000000000000); 5692 #endif 5693 } 5694 5695 /* 5696 * Initialize PMU counter overflow timers for Power8 and 5697 * newer Power chips when using TCG. 5698 */ 5699 static void init_tcg_pmu_power8(CPUPPCState *env) 5700 { 5701 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 5702 /* Init PMU overflow timers */ 5703 if (!kvm_enabled()) { 5704 cpu_ppc_pmu_init(env); 5705 } 5706 #endif 5707 } 5708 5709 static void init_proc_book3s_common(CPUPPCState *env) 5710 { 5711 register_non_embedded_sprs(env); 5712 register_book3s_altivec_sprs(env); 5713 register_book3s_pmu_sup_sprs(env); 5714 register_book3s_pmu_user_sprs(env); 5715 register_book3s_ctrl_sprs(env); 5716 /* 5717 * Can't find information on what this should be on reset. This 5718 * value is the one used by 74xx processors. 5719 */ 5720 vscr_init(env, 0x00010000); 5721 5722 spr_register(env, SPR_USPRG3, "USPRG3", 5723 &spr_read_ureg, SPR_NOACCESS, 5724 &spr_read_ureg, SPR_NOACCESS, 5725 0x00000000); 5726 } 5727 5728 static void init_proc_970(CPUPPCState *env) 5729 { 5730 /* Common Registers */ 5731 init_proc_book3s_common(env); 5732 register_sdr1_sprs(env); 5733 register_book3s_dbg_sprs(env); 5734 5735 /* 970 Specific Registers */ 5736 register_970_hid_sprs(env); 5737 register_970_hior_sprs(env); 5738 register_low_BATs(env); 5739 register_970_pmu_sup_sprs(env); 5740 register_970_pmu_user_sprs(env); 5741 register_970_lpar_sprs(env); 5742 register_970_dbg_sprs(env); 5743 5744 /* env variables */ 5745 env->dcache_line_size = 128; 5746 env->icache_line_size = 128; 5747 5748 /* Allocate hardware IRQ controller */ 5749 init_excp_970(env); 5750 ppc970_irq_init(env_archcpu(env)); 5751 } 5752 5753 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5754 { 5755 DeviceClass *dc = DEVICE_CLASS(oc); 5756 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5757 5758 dc->desc = "PowerPC 970"; 5759 pcc->init_proc = init_proc_970; 5760 pcc->check_pow = check_pow_970; 5761 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5762 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5763 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5764 PPC_FLOAT_STFIWX | 5765 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5766 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5767 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5768 PPC_64B | PPC_ALTIVEC | 5769 PPC_SEGMENT_64B | PPC_SLBI; 5770 pcc->insns_flags2 = PPC2_FP_CVT_S64; 5771 pcc->msr_mask = (1ull << MSR_SF) | 5772 (1ull << MSR_VR) | 5773 (1ull << MSR_POW) | 5774 (1ull << MSR_EE) | 5775 (1ull << MSR_PR) | 5776 (1ull << MSR_FP) | 5777 (1ull << MSR_ME) | 5778 (1ull << MSR_FE0) | 5779 (1ull << MSR_SE) | 5780 (1ull << MSR_DE) | 5781 (1ull << MSR_FE1) | 5782 (1ull << MSR_IR) | 5783 (1ull << MSR_DR) | 5784 (1ull << MSR_PMM) | 5785 (1ull << MSR_RI); 5786 pcc->mmu_model = POWERPC_MMU_64B; 5787 #if defined(CONFIG_SOFTMMU) 5788 pcc->hash64_opts = &ppc_hash64_opts_basic; 5789 #endif 5790 pcc->excp_model = POWERPC_EXCP_970; 5791 pcc->bus_model = PPC_FLAGS_INPUT_970; 5792 pcc->bfd_mach = bfd_mach_ppc64; 5793 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5794 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5795 POWERPC_FLAG_BUS_CLK; 5796 pcc->l1_dcache_size = 0x8000; 5797 pcc->l1_icache_size = 0x10000; 5798 } 5799 5800 static void init_proc_power5plus(CPUPPCState *env) 5801 { 5802 /* Common Registers */ 5803 init_proc_book3s_common(env); 5804 register_sdr1_sprs(env); 5805 register_book3s_dbg_sprs(env); 5806 5807 /* POWER5+ Specific Registers */ 5808 register_970_hid_sprs(env); 5809 register_970_hior_sprs(env); 5810 register_low_BATs(env); 5811 register_970_pmu_sup_sprs(env); 5812 register_970_pmu_user_sprs(env); 5813 register_power5p_common_sprs(env); 5814 register_power5p_lpar_sprs(env); 5815 register_power5p_ear_sprs(env); 5816 register_power5p_tb_sprs(env); 5817 5818 /* env variables */ 5819 env->dcache_line_size = 128; 5820 env->icache_line_size = 128; 5821 5822 /* Allocate hardware IRQ controller */ 5823 init_excp_970(env); 5824 ppc970_irq_init(env_archcpu(env)); 5825 } 5826 5827 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 5828 { 5829 DeviceClass *dc = DEVICE_CLASS(oc); 5830 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5831 5832 dc->fw_name = "PowerPC,POWER5"; 5833 dc->desc = "POWER5+"; 5834 pcc->init_proc = init_proc_power5plus; 5835 pcc->check_pow = check_pow_970; 5836 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5837 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5838 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5839 PPC_FLOAT_STFIWX | 5840 PPC_FLOAT_EXT | 5841 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5842 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5843 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5844 PPC_64B | 5845 PPC_POPCNTB | 5846 PPC_SEGMENT_64B | PPC_SLBI; 5847 pcc->insns_flags2 = PPC2_FP_CVT_S64; 5848 pcc->msr_mask = (1ull << MSR_SF) | 5849 (1ull << MSR_VR) | 5850 (1ull << MSR_POW) | 5851 (1ull << MSR_EE) | 5852 (1ull << MSR_PR) | 5853 (1ull << MSR_FP) | 5854 (1ull << MSR_ME) | 5855 (1ull << MSR_FE0) | 5856 (1ull << MSR_SE) | 5857 (1ull << MSR_DE) | 5858 (1ull << MSR_FE1) | 5859 (1ull << MSR_IR) | 5860 (1ull << MSR_DR) | 5861 (1ull << MSR_PMM) | 5862 (1ull << MSR_RI); 5863 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 5864 LPCR_RMI | LPCR_HDICE; 5865 pcc->mmu_model = POWERPC_MMU_2_03; 5866 #if defined(CONFIG_SOFTMMU) 5867 pcc->hash64_opts = &ppc_hash64_opts_basic; 5868 pcc->lrg_decr_bits = 32; 5869 #endif 5870 pcc->excp_model = POWERPC_EXCP_970; 5871 pcc->bus_model = PPC_FLAGS_INPUT_970; 5872 pcc->bfd_mach = bfd_mach_ppc64; 5873 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5874 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5875 POWERPC_FLAG_BUS_CLK; 5876 pcc->l1_dcache_size = 0x8000; 5877 pcc->l1_icache_size = 0x10000; 5878 } 5879 5880 static void init_proc_POWER7(CPUPPCState *env) 5881 { 5882 /* Common Registers */ 5883 init_proc_book3s_common(env); 5884 register_sdr1_sprs(env); 5885 register_book3s_dbg_sprs(env); 5886 5887 /* POWER7 Specific Registers */ 5888 register_book3s_ids_sprs(env); 5889 register_rmor_sprs(env); 5890 register_amr_sprs(env); 5891 register_book3s_purr_sprs(env); 5892 register_power5p_common_sprs(env); 5893 register_power5p_lpar_sprs(env); 5894 register_power5p_ear_sprs(env); 5895 register_power5p_tb_sprs(env); 5896 register_power6_common_sprs(env); 5897 register_power6_dbg_sprs(env); 5898 register_power7_book4_sprs(env); 5899 5900 /* env variables */ 5901 env->dcache_line_size = 128; 5902 env->icache_line_size = 128; 5903 5904 /* Allocate hardware IRQ controller */ 5905 init_excp_POWER7(env); 5906 ppcPOWER7_irq_init(env_archcpu(env)); 5907 } 5908 5909 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 5910 { 5911 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 5912 return true; 5913 } 5914 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 5915 return true; 5916 } 5917 return false; 5918 } 5919 5920 static bool cpu_has_work_POWER7(CPUState *cs) 5921 { 5922 PowerPCCPU *cpu = POWERPC_CPU(cs); 5923 CPUPPCState *env = &cpu->env; 5924 5925 if (cs->halted) { 5926 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 5927 return false; 5928 } 5929 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 5930 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 5931 return true; 5932 } 5933 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 5934 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 5935 return true; 5936 } 5937 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 5938 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 5939 return true; 5940 } 5941 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 5942 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 5943 return true; 5944 } 5945 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 5946 return true; 5947 } 5948 return false; 5949 } else { 5950 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 5951 } 5952 } 5953 5954 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 5955 { 5956 DeviceClass *dc = DEVICE_CLASS(oc); 5957 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5958 CPUClass *cc = CPU_CLASS(oc); 5959 5960 dc->fw_name = "PowerPC,POWER7"; 5961 dc->desc = "POWER7"; 5962 pcc->pvr_match = ppc_pvr_match_power7; 5963 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 5964 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 5965 pcc->init_proc = init_proc_POWER7; 5966 pcc->check_pow = check_pow_nocheck; 5967 cc->has_work = cpu_has_work_POWER7; 5968 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 5969 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5970 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5971 PPC_FLOAT_FRSQRTES | 5972 PPC_FLOAT_STFIWX | 5973 PPC_FLOAT_EXT | 5974 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5975 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5976 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5977 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 5978 PPC_SEGMENT_64B | PPC_SLBI | 5979 PPC_POPCNTB | PPC_POPCNTWD | 5980 PPC_CILDST; 5981 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 5982 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 5983 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 5984 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 5985 PPC2_PM_ISA206; 5986 pcc->msr_mask = (1ull << MSR_SF) | 5987 (1ull << MSR_VR) | 5988 (1ull << MSR_VSX) | 5989 (1ull << MSR_EE) | 5990 (1ull << MSR_PR) | 5991 (1ull << MSR_FP) | 5992 (1ull << MSR_ME) | 5993 (1ull << MSR_FE0) | 5994 (1ull << MSR_SE) | 5995 (1ull << MSR_DE) | 5996 (1ull << MSR_FE1) | 5997 (1ull << MSR_IR) | 5998 (1ull << MSR_DR) | 5999 (1ull << MSR_PMM) | 6000 (1ull << MSR_RI) | 6001 (1ull << MSR_LE); 6002 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6003 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6004 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6005 LPCR_MER | LPCR_TC | 6006 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6007 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6008 pcc->mmu_model = POWERPC_MMU_2_06; 6009 #if defined(CONFIG_SOFTMMU) 6010 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6011 pcc->lrg_decr_bits = 32; 6012 #endif 6013 pcc->excp_model = POWERPC_EXCP_POWER7; 6014 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6015 pcc->bfd_mach = bfd_mach_ppc64; 6016 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6017 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6018 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6019 POWERPC_FLAG_VSX; 6020 pcc->l1_dcache_size = 0x8000; 6021 pcc->l1_icache_size = 0x8000; 6022 } 6023 6024 static void init_proc_POWER8(CPUPPCState *env) 6025 { 6026 /* Common Registers */ 6027 init_proc_book3s_common(env); 6028 register_sdr1_sprs(env); 6029 register_book3s_207_dbg_sprs(env); 6030 6031 /* Common TCG PMU */ 6032 init_tcg_pmu_power8(env); 6033 6034 /* POWER8 Specific Registers */ 6035 register_book3s_ids_sprs(env); 6036 register_rmor_sprs(env); 6037 register_amr_sprs(env); 6038 register_iamr_sprs(env); 6039 register_book3s_purr_sprs(env); 6040 register_power5p_common_sprs(env); 6041 register_power5p_lpar_sprs(env); 6042 register_power5p_ear_sprs(env); 6043 register_power5p_tb_sprs(env); 6044 register_power6_common_sprs(env); 6045 register_power6_dbg_sprs(env); 6046 register_power8_tce_address_control_sprs(env); 6047 register_power8_ids_sprs(env); 6048 register_power8_ebb_sprs(env); 6049 register_power8_fscr_sprs(env); 6050 register_power8_pmu_sup_sprs(env); 6051 register_power8_pmu_user_sprs(env); 6052 register_power8_tm_sprs(env); 6053 register_power8_pspb_sprs(env); 6054 register_power8_dpdes_sprs(env); 6055 register_vtb_sprs(env); 6056 register_power8_ic_sprs(env); 6057 register_power8_book4_sprs(env); 6058 register_power8_rpr_sprs(env); 6059 6060 /* env variables */ 6061 env->dcache_line_size = 128; 6062 env->icache_line_size = 128; 6063 6064 /* Allocate hardware IRQ controller */ 6065 init_excp_POWER8(env); 6066 ppcPOWER7_irq_init(env_archcpu(env)); 6067 } 6068 6069 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6070 { 6071 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6072 return true; 6073 } 6074 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6075 return true; 6076 } 6077 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6078 return true; 6079 } 6080 return false; 6081 } 6082 6083 static bool cpu_has_work_POWER8(CPUState *cs) 6084 { 6085 PowerPCCPU *cpu = POWERPC_CPU(cs); 6086 CPUPPCState *env = &cpu->env; 6087 6088 if (cs->halted) { 6089 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6090 return false; 6091 } 6092 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6093 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6094 return true; 6095 } 6096 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6097 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6098 return true; 6099 } 6100 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6101 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6102 return true; 6103 } 6104 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6105 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6106 return true; 6107 } 6108 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6109 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6110 return true; 6111 } 6112 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6113 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6114 return true; 6115 } 6116 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6117 return true; 6118 } 6119 return false; 6120 } else { 6121 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6122 } 6123 } 6124 6125 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6126 { 6127 DeviceClass *dc = DEVICE_CLASS(oc); 6128 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6129 CPUClass *cc = CPU_CLASS(oc); 6130 6131 dc->fw_name = "PowerPC,POWER8"; 6132 dc->desc = "POWER8"; 6133 pcc->pvr_match = ppc_pvr_match_power8; 6134 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6135 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6136 pcc->init_proc = init_proc_POWER8; 6137 pcc->check_pow = check_pow_nocheck; 6138 cc->has_work = cpu_has_work_POWER8; 6139 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6140 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6141 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6142 PPC_FLOAT_FRSQRTES | 6143 PPC_FLOAT_STFIWX | 6144 PPC_FLOAT_EXT | 6145 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6146 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6147 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6148 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6149 PPC_SEGMENT_64B | PPC_SLBI | 6150 PPC_POPCNTB | PPC_POPCNTWD | 6151 PPC_CILDST; 6152 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6153 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6154 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6155 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6156 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6157 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6158 PPC2_TM | PPC2_PM_ISA206; 6159 pcc->msr_mask = (1ull << MSR_SF) | 6160 (1ull << MSR_HV) | 6161 (1ull << MSR_TM) | 6162 (1ull << MSR_VR) | 6163 (1ull << MSR_VSX) | 6164 (1ull << MSR_EE) | 6165 (1ull << MSR_PR) | 6166 (1ull << MSR_FP) | 6167 (1ull << MSR_ME) | 6168 (1ull << MSR_FE0) | 6169 (1ull << MSR_SE) | 6170 (1ull << MSR_DE) | 6171 (1ull << MSR_FE1) | 6172 (1ull << MSR_IR) | 6173 (1ull << MSR_DR) | 6174 (1ull << MSR_PMM) | 6175 (1ull << MSR_RI) | 6176 (1ull << MSR_TS0) | 6177 (1ull << MSR_TS1) | 6178 (1ull << MSR_LE); 6179 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6180 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6181 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6182 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6183 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6184 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6185 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6186 pcc->mmu_model = POWERPC_MMU_2_07; 6187 #if defined(CONFIG_SOFTMMU) 6188 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6189 pcc->lrg_decr_bits = 32; 6190 pcc->n_host_threads = 8; 6191 #endif 6192 pcc->excp_model = POWERPC_EXCP_POWER8; 6193 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6194 pcc->bfd_mach = bfd_mach_ppc64; 6195 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6196 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6197 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6198 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6199 pcc->l1_dcache_size = 0x8000; 6200 pcc->l1_icache_size = 0x8000; 6201 } 6202 6203 #ifdef CONFIG_SOFTMMU 6204 /* 6205 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6206 * Encoded as array of int_32s in the form: 6207 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6208 * x -> AP encoding 6209 * y -> radix mode supported page size (encoded as a shift) 6210 */ 6211 static struct ppc_radix_page_info POWER9_radix_page_info = { 6212 .count = 4, 6213 .entries = { 6214 0x0000000c, /* 4K - enc: 0x0 */ 6215 0xa0000010, /* 64K - enc: 0x5 */ 6216 0x20000015, /* 2M - enc: 0x1 */ 6217 0x4000001e /* 1G - enc: 0x2 */ 6218 } 6219 }; 6220 #endif /* CONFIG_SOFTMMU */ 6221 6222 static void init_proc_POWER9(CPUPPCState *env) 6223 { 6224 /* Common Registers */ 6225 init_proc_book3s_common(env); 6226 register_book3s_207_dbg_sprs(env); 6227 6228 /* Common TCG PMU */ 6229 init_tcg_pmu_power8(env); 6230 6231 /* POWER8 Specific Registers */ 6232 register_book3s_ids_sprs(env); 6233 register_amr_sprs(env); 6234 register_iamr_sprs(env); 6235 register_book3s_purr_sprs(env); 6236 register_power5p_common_sprs(env); 6237 register_power5p_lpar_sprs(env); 6238 register_power5p_ear_sprs(env); 6239 register_power5p_tb_sprs(env); 6240 register_power6_common_sprs(env); 6241 register_power6_dbg_sprs(env); 6242 register_power8_tce_address_control_sprs(env); 6243 register_power8_ids_sprs(env); 6244 register_power8_ebb_sprs(env); 6245 register_power8_fscr_sprs(env); 6246 register_power8_pmu_sup_sprs(env); 6247 register_power8_pmu_user_sprs(env); 6248 register_power8_tm_sprs(env); 6249 register_power8_pspb_sprs(env); 6250 register_power8_dpdes_sprs(env); 6251 register_vtb_sprs(env); 6252 register_power8_ic_sprs(env); 6253 register_power8_book4_sprs(env); 6254 register_power8_rpr_sprs(env); 6255 register_power9_mmu_sprs(env); 6256 6257 /* POWER9 Specific registers */ 6258 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6259 spr_read_generic, spr_write_generic, 6260 KVM_REG_PPC_TIDR, 0); 6261 6262 /* FIXME: Filter fields properly based on privilege level */ 6263 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6264 spr_read_generic, spr_write_generic, 6265 KVM_REG_PPC_PSSCR, 0); 6266 6267 /* env variables */ 6268 env->dcache_line_size = 128; 6269 env->icache_line_size = 128; 6270 6271 /* Allocate hardware IRQ controller */ 6272 init_excp_POWER9(env); 6273 ppcPOWER9_irq_init(env_archcpu(env)); 6274 } 6275 6276 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6277 { 6278 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6279 return true; 6280 } 6281 return false; 6282 } 6283 6284 static bool cpu_has_work_POWER9(CPUState *cs) 6285 { 6286 PowerPCCPU *cpu = POWERPC_CPU(cs); 6287 CPUPPCState *env = &cpu->env; 6288 6289 if (cs->halted) { 6290 uint64_t psscr = env->spr[SPR_PSSCR]; 6291 6292 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6293 return false; 6294 } 6295 6296 /* If EC is clear, just return true on any pending interrupt */ 6297 if (!(psscr & PSSCR_EC)) { 6298 return true; 6299 } 6300 /* External Exception */ 6301 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6302 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6303 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6304 if (heic == 0 || !msr_hv || msr_pr) { 6305 return true; 6306 } 6307 } 6308 /* Decrementer Exception */ 6309 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6310 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6311 return true; 6312 } 6313 /* Machine Check or Hypervisor Maintenance Exception */ 6314 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6315 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6316 return true; 6317 } 6318 /* Privileged Doorbell Exception */ 6319 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6320 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6321 return true; 6322 } 6323 /* Hypervisor Doorbell Exception */ 6324 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6325 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6326 return true; 6327 } 6328 /* Hypervisor virtualization exception */ 6329 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6330 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6331 return true; 6332 } 6333 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6334 return true; 6335 } 6336 return false; 6337 } else { 6338 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6339 } 6340 } 6341 6342 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6343 { 6344 DeviceClass *dc = DEVICE_CLASS(oc); 6345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6346 CPUClass *cc = CPU_CLASS(oc); 6347 6348 dc->fw_name = "PowerPC,POWER9"; 6349 dc->desc = "POWER9"; 6350 pcc->pvr_match = ppc_pvr_match_power9; 6351 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6352 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6353 PCR_COMPAT_2_05; 6354 pcc->init_proc = init_proc_POWER9; 6355 pcc->check_pow = check_pow_nocheck; 6356 cc->has_work = cpu_has_work_POWER9; 6357 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6358 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6359 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6360 PPC_FLOAT_FRSQRTES | 6361 PPC_FLOAT_STFIWX | 6362 PPC_FLOAT_EXT | 6363 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6364 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6365 PPC_MEM_TLBSYNC | 6366 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6367 PPC_SEGMENT_64B | PPC_SLBI | 6368 PPC_POPCNTB | PPC_POPCNTWD | 6369 PPC_CILDST; 6370 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6371 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6372 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6373 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6374 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6375 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6376 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6377 pcc->msr_mask = (1ull << MSR_SF) | 6378 (1ull << MSR_HV) | 6379 (1ull << MSR_TM) | 6380 (1ull << MSR_VR) | 6381 (1ull << MSR_VSX) | 6382 (1ull << MSR_EE) | 6383 (1ull << MSR_PR) | 6384 (1ull << MSR_FP) | 6385 (1ull << MSR_ME) | 6386 (1ull << MSR_FE0) | 6387 (1ull << MSR_SE) | 6388 (1ull << MSR_DE) | 6389 (1ull << MSR_FE1) | 6390 (1ull << MSR_IR) | 6391 (1ull << MSR_DR) | 6392 (1ull << MSR_PMM) | 6393 (1ull << MSR_RI) | 6394 (1ull << MSR_LE); 6395 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6396 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6397 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6398 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6399 LPCR_DEE | LPCR_OEE)) 6400 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6401 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6402 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6403 pcc->mmu_model = POWERPC_MMU_3_00; 6404 #if defined(CONFIG_SOFTMMU) 6405 /* segment page size remain the same */ 6406 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6407 pcc->radix_page_info = &POWER9_radix_page_info; 6408 pcc->lrg_decr_bits = 56; 6409 pcc->n_host_threads = 4; 6410 #endif 6411 pcc->excp_model = POWERPC_EXCP_POWER9; 6412 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6413 pcc->bfd_mach = bfd_mach_ppc64; 6414 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6415 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6416 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6417 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6418 pcc->l1_dcache_size = 0x8000; 6419 pcc->l1_icache_size = 0x8000; 6420 } 6421 6422 #ifdef CONFIG_SOFTMMU 6423 /* 6424 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6425 * Encoded as array of int_32s in the form: 6426 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6427 * x -> AP encoding 6428 * y -> radix mode supported page size (encoded as a shift) 6429 */ 6430 static struct ppc_radix_page_info POWER10_radix_page_info = { 6431 .count = 4, 6432 .entries = { 6433 0x0000000c, /* 4K - enc: 0x0 */ 6434 0xa0000010, /* 64K - enc: 0x5 */ 6435 0x20000015, /* 2M - enc: 0x1 */ 6436 0x4000001e /* 1G - enc: 0x2 */ 6437 } 6438 }; 6439 #endif /* CONFIG_SOFTMMU */ 6440 6441 static void init_proc_POWER10(CPUPPCState *env) 6442 { 6443 /* Common Registers */ 6444 init_proc_book3s_common(env); 6445 register_book3s_207_dbg_sprs(env); 6446 6447 /* Common TCG PMU */ 6448 init_tcg_pmu_power8(env); 6449 6450 /* POWER8 Specific Registers */ 6451 register_book3s_ids_sprs(env); 6452 register_amr_sprs(env); 6453 register_iamr_sprs(env); 6454 register_book3s_purr_sprs(env); 6455 register_power5p_common_sprs(env); 6456 register_power5p_lpar_sprs(env); 6457 register_power5p_ear_sprs(env); 6458 register_power6_common_sprs(env); 6459 register_power6_dbg_sprs(env); 6460 register_power8_tce_address_control_sprs(env); 6461 register_power8_ids_sprs(env); 6462 register_power8_ebb_sprs(env); 6463 register_power8_fscr_sprs(env); 6464 register_power8_pmu_sup_sprs(env); 6465 register_power8_pmu_user_sprs(env); 6466 register_power8_tm_sprs(env); 6467 register_power8_pspb_sprs(env); 6468 register_vtb_sprs(env); 6469 register_power8_ic_sprs(env); 6470 register_power8_book4_sprs(env); 6471 register_power8_rpr_sprs(env); 6472 register_power9_mmu_sprs(env); 6473 6474 /* FIXME: Filter fields properly based on privilege level */ 6475 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6476 spr_read_generic, spr_write_generic, 6477 KVM_REG_PPC_PSSCR, 0); 6478 6479 /* env variables */ 6480 env->dcache_line_size = 128; 6481 env->icache_line_size = 128; 6482 6483 /* Allocate hardware IRQ controller */ 6484 init_excp_POWER10(env); 6485 ppcPOWER9_irq_init(env_archcpu(env)); 6486 } 6487 6488 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 6489 { 6490 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 6491 return true; 6492 } 6493 return false; 6494 } 6495 6496 static bool cpu_has_work_POWER10(CPUState *cs) 6497 { 6498 PowerPCCPU *cpu = POWERPC_CPU(cs); 6499 CPUPPCState *env = &cpu->env; 6500 6501 if (cs->halted) { 6502 uint64_t psscr = env->spr[SPR_PSSCR]; 6503 6504 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6505 return false; 6506 } 6507 6508 /* If EC is clear, just return true on any pending interrupt */ 6509 if (!(psscr & PSSCR_EC)) { 6510 return true; 6511 } 6512 /* External Exception */ 6513 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6514 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6515 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6516 if (heic == 0 || !msr_hv || msr_pr) { 6517 return true; 6518 } 6519 } 6520 /* Decrementer Exception */ 6521 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6522 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6523 return true; 6524 } 6525 /* Machine Check or Hypervisor Maintenance Exception */ 6526 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6527 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6528 return true; 6529 } 6530 /* Privileged Doorbell Exception */ 6531 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6532 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6533 return true; 6534 } 6535 /* Hypervisor Doorbell Exception */ 6536 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6537 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6538 return true; 6539 } 6540 /* Hypervisor virtualization exception */ 6541 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6542 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6543 return true; 6544 } 6545 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6546 return true; 6547 } 6548 return false; 6549 } else { 6550 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6551 } 6552 } 6553 6554 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6555 { 6556 DeviceClass *dc = DEVICE_CLASS(oc); 6557 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6558 CPUClass *cc = CPU_CLASS(oc); 6559 6560 dc->fw_name = "PowerPC,POWER10"; 6561 dc->desc = "POWER10"; 6562 pcc->pvr_match = ppc_pvr_match_power10; 6563 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 6564 PCR_COMPAT_3_00; 6565 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 6566 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6567 pcc->init_proc = init_proc_POWER10; 6568 pcc->check_pow = check_pow_nocheck; 6569 cc->has_work = cpu_has_work_POWER10; 6570 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6571 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6572 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6573 PPC_FLOAT_FRSQRTES | 6574 PPC_FLOAT_STFIWX | 6575 PPC_FLOAT_EXT | 6576 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6577 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6578 PPC_MEM_TLBSYNC | 6579 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6580 PPC_SEGMENT_64B | PPC_SLBI | 6581 PPC_POPCNTB | PPC_POPCNTWD | 6582 PPC_CILDST; 6583 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6584 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6585 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6586 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6587 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6588 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6589 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 6590 pcc->msr_mask = (1ull << MSR_SF) | 6591 (1ull << MSR_HV) | 6592 (1ull << MSR_TM) | 6593 (1ull << MSR_VR) | 6594 (1ull << MSR_VSX) | 6595 (1ull << MSR_EE) | 6596 (1ull << MSR_PR) | 6597 (1ull << MSR_FP) | 6598 (1ull << MSR_ME) | 6599 (1ull << MSR_FE0) | 6600 (1ull << MSR_SE) | 6601 (1ull << MSR_DE) | 6602 (1ull << MSR_FE1) | 6603 (1ull << MSR_IR) | 6604 (1ull << MSR_DR) | 6605 (1ull << MSR_PMM) | 6606 (1ull << MSR_RI) | 6607 (1ull << MSR_LE); 6608 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6609 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6610 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6611 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6612 LPCR_DEE | LPCR_OEE)) 6613 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6614 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6615 /* DD2 adds an extra HAIL bit */ 6616 pcc->lpcr_mask |= LPCR_HAIL; 6617 6618 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6619 pcc->mmu_model = POWERPC_MMU_3_00; 6620 #if defined(CONFIG_SOFTMMU) 6621 /* segment page size remain the same */ 6622 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6623 pcc->radix_page_info = &POWER10_radix_page_info; 6624 pcc->lrg_decr_bits = 56; 6625 #endif 6626 pcc->excp_model = POWERPC_EXCP_POWER10; 6627 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6628 pcc->bfd_mach = bfd_mach_ppc64; 6629 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6630 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6631 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6632 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6633 pcc->l1_dcache_size = 0x8000; 6634 pcc->l1_icache_size = 0x8000; 6635 } 6636 6637 #if !defined(CONFIG_USER_ONLY) 6638 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6639 { 6640 CPUPPCState *env = &cpu->env; 6641 6642 cpu->vhyp = vhyp; 6643 6644 /* 6645 * With a virtual hypervisor mode we never allow the CPU to go 6646 * hypervisor mode itself 6647 */ 6648 env->msr_mask &= ~MSR_HVB; 6649 } 6650 6651 #endif /* !defined(CONFIG_USER_ONLY) */ 6652 6653 #endif /* defined(TARGET_PPC64) */ 6654 6655 /*****************************************************************************/ 6656 /* Generic CPU instantiation routine */ 6657 static void init_ppc_proc(PowerPCCPU *cpu) 6658 { 6659 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6660 CPUPPCState *env = &cpu->env; 6661 #if !defined(CONFIG_USER_ONLY) 6662 int i; 6663 6664 env->irq_inputs = NULL; 6665 /* Set all exception vectors to an invalid address */ 6666 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6667 env->excp_vectors[i] = (target_ulong)(-1ULL); 6668 } 6669 env->ivor_mask = 0x00000000; 6670 env->ivpr_mask = 0x00000000; 6671 /* Default MMU definitions */ 6672 env->nb_BATs = 0; 6673 env->nb_tlb = 0; 6674 env->nb_ways = 0; 6675 env->tlb_type = TLB_NONE; 6676 #endif 6677 /* Register SPR common to all PowerPC implementations */ 6678 register_generic_sprs(cpu); 6679 6680 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6681 (*pcc->init_proc)(env); 6682 6683 #if !defined(CONFIG_USER_ONLY) 6684 ppc_gdb_gen_spr_xml(cpu); 6685 #endif 6686 6687 /* MSR bits & flags consistency checks */ 6688 if (env->msr_mask & (1 << 25)) { 6689 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6690 case POWERPC_FLAG_SPE: 6691 case POWERPC_FLAG_VRE: 6692 break; 6693 default: 6694 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6695 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6696 exit(1); 6697 } 6698 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6699 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6700 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6701 exit(1); 6702 } 6703 if (env->msr_mask & (1 << 17)) { 6704 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6705 case POWERPC_FLAG_TGPR: 6706 case POWERPC_FLAG_CE: 6707 break; 6708 default: 6709 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6710 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6711 exit(1); 6712 } 6713 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6714 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6715 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6716 exit(1); 6717 } 6718 if (env->msr_mask & (1 << 10)) { 6719 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6720 POWERPC_FLAG_UBLE)) { 6721 case POWERPC_FLAG_SE: 6722 case POWERPC_FLAG_DWE: 6723 case POWERPC_FLAG_UBLE: 6724 break; 6725 default: 6726 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6727 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6728 "POWERPC_FLAG_UBLE\n"); 6729 exit(1); 6730 } 6731 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6732 POWERPC_FLAG_UBLE)) { 6733 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6734 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6735 "POWERPC_FLAG_UBLE\n"); 6736 exit(1); 6737 } 6738 if (env->msr_mask & (1 << 9)) { 6739 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6740 case POWERPC_FLAG_BE: 6741 case POWERPC_FLAG_DE: 6742 break; 6743 default: 6744 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6745 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6746 exit(1); 6747 } 6748 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6749 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6750 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6751 exit(1); 6752 } 6753 if (env->msr_mask & (1 << 2)) { 6754 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6755 case POWERPC_FLAG_PX: 6756 case POWERPC_FLAG_PMM: 6757 break; 6758 default: 6759 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6760 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6761 exit(1); 6762 } 6763 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6764 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6765 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6766 exit(1); 6767 } 6768 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6769 fprintf(stderr, "PowerPC flags inconsistency\n" 6770 "Should define the time-base and decrementer clock source\n"); 6771 exit(1); 6772 } 6773 /* Allocate TLBs buffer when needed */ 6774 #if !defined(CONFIG_USER_ONLY) 6775 if (env->nb_tlb != 0) { 6776 int nb_tlb = env->nb_tlb; 6777 if (env->id_tlbs != 0) { 6778 nb_tlb *= 2; 6779 } 6780 switch (env->tlb_type) { 6781 case TLB_6XX: 6782 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 6783 break; 6784 case TLB_EMB: 6785 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 6786 break; 6787 case TLB_MAS: 6788 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 6789 break; 6790 } 6791 /* Pre-compute some useful values */ 6792 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6793 } 6794 if (env->irq_inputs == NULL) { 6795 warn_report("no internal IRQ controller registered." 6796 " Attempt QEMU to crash very soon !"); 6797 } 6798 #endif 6799 if (env->check_pow == NULL) { 6800 warn_report("no power management check handler registered." 6801 " Attempt QEMU to crash very soon !"); 6802 } 6803 } 6804 6805 6806 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6807 { 6808 CPUState *cs = CPU(dev); 6809 PowerPCCPU *cpu = POWERPC_CPU(dev); 6810 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6811 Error *local_err = NULL; 6812 6813 cpu_exec_realizefn(cs, &local_err); 6814 if (local_err != NULL) { 6815 error_propagate(errp, local_err); 6816 return; 6817 } 6818 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6819 cpu->vcpu_id = cs->cpu_index; 6820 } 6821 6822 if (tcg_enabled()) { 6823 if (ppc_fixup_cpu(cpu) != 0) { 6824 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6825 goto unrealize; 6826 } 6827 } 6828 6829 create_ppc_opcodes(cpu, &local_err); 6830 if (local_err != NULL) { 6831 error_propagate(errp, local_err); 6832 goto unrealize; 6833 } 6834 init_ppc_proc(cpu); 6835 6836 ppc_gdb_init(cs, pcc); 6837 qemu_init_vcpu(cs); 6838 6839 pcc->parent_realize(dev, errp); 6840 6841 return; 6842 6843 unrealize: 6844 cpu_exec_unrealizefn(cs); 6845 } 6846 6847 static void ppc_cpu_unrealize(DeviceState *dev) 6848 { 6849 PowerPCCPU *cpu = POWERPC_CPU(dev); 6850 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6851 6852 pcc->parent_unrealize(dev); 6853 6854 cpu_remove_sync(CPU(cpu)); 6855 6856 destroy_ppc_opcodes(cpu); 6857 } 6858 6859 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6860 { 6861 ObjectClass *oc = (ObjectClass *)a; 6862 uint32_t pvr = *(uint32_t *)b; 6863 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6864 6865 /* -cpu host does a PVR lookup during construction */ 6866 if (unlikely(strcmp(object_class_get_name(oc), 6867 TYPE_HOST_POWERPC_CPU) == 0)) { 6868 return -1; 6869 } 6870 6871 return pcc->pvr == pvr ? 0 : -1; 6872 } 6873 6874 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 6875 { 6876 GSList *list, *item; 6877 PowerPCCPUClass *pcc = NULL; 6878 6879 list = object_class_get_list(TYPE_POWERPC_CPU, false); 6880 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 6881 if (item != NULL) { 6882 pcc = POWERPC_CPU_CLASS(item->data); 6883 } 6884 g_slist_free(list); 6885 6886 return pcc; 6887 } 6888 6889 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 6890 { 6891 ObjectClass *oc = (ObjectClass *)a; 6892 uint32_t pvr = *(uint32_t *)b; 6893 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6894 6895 /* -cpu host does a PVR lookup during construction */ 6896 if (unlikely(strcmp(object_class_get_name(oc), 6897 TYPE_HOST_POWERPC_CPU) == 0)) { 6898 return -1; 6899 } 6900 6901 if (pcc->pvr_match(pcc, pvr)) { 6902 return 0; 6903 } 6904 6905 return -1; 6906 } 6907 6908 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 6909 { 6910 GSList *list, *item; 6911 PowerPCCPUClass *pcc = NULL; 6912 6913 list = object_class_get_list(TYPE_POWERPC_CPU, true); 6914 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 6915 if (item != NULL) { 6916 pcc = POWERPC_CPU_CLASS(item->data); 6917 } 6918 g_slist_free(list); 6919 6920 return pcc; 6921 } 6922 6923 static const char *ppc_cpu_lookup_alias(const char *alias) 6924 { 6925 int ai; 6926 6927 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 6928 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 6929 return ppc_cpu_aliases[ai].model; 6930 } 6931 } 6932 6933 return NULL; 6934 } 6935 6936 static ObjectClass *ppc_cpu_class_by_name(const char *name) 6937 { 6938 char *cpu_model, *typename; 6939 ObjectClass *oc; 6940 const char *p; 6941 unsigned long pvr; 6942 6943 /* 6944 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 6945 * 0x prefix if present) 6946 */ 6947 if (!qemu_strtoul(name, &p, 16, &pvr)) { 6948 int len = p - name; 6949 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 6950 if ((len == 8) && (*p == '\0')) { 6951 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 6952 } 6953 } 6954 6955 cpu_model = g_ascii_strdown(name, -1); 6956 p = ppc_cpu_lookup_alias(cpu_model); 6957 if (p) { 6958 g_free(cpu_model); 6959 cpu_model = g_strdup(p); 6960 } 6961 6962 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 6963 oc = object_class_by_name(typename); 6964 g_free(typename); 6965 g_free(cpu_model); 6966 6967 return oc; 6968 } 6969 6970 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 6971 { 6972 ObjectClass *oc = OBJECT_CLASS(pcc); 6973 6974 while (oc && !object_class_is_abstract(oc)) { 6975 oc = object_class_get_parent(oc); 6976 } 6977 assert(oc); 6978 6979 return POWERPC_CPU_CLASS(oc); 6980 } 6981 6982 /* Sort by PVR, ordering special case "host" last. */ 6983 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 6984 { 6985 ObjectClass *oc_a = (ObjectClass *)a; 6986 ObjectClass *oc_b = (ObjectClass *)b; 6987 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 6988 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 6989 const char *name_a = object_class_get_name(oc_a); 6990 const char *name_b = object_class_get_name(oc_b); 6991 6992 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 6993 return 1; 6994 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 6995 return -1; 6996 } else { 6997 /* Avoid an integer overflow during subtraction */ 6998 if (pcc_a->pvr < pcc_b->pvr) { 6999 return -1; 7000 } else if (pcc_a->pvr > pcc_b->pvr) { 7001 return 1; 7002 } else { 7003 return 0; 7004 } 7005 } 7006 } 7007 7008 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7009 { 7010 ObjectClass *oc = data; 7011 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7012 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7013 const char *typename = object_class_get_name(oc); 7014 char *name; 7015 int i; 7016 7017 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7018 return; 7019 } 7020 7021 name = g_strndup(typename, 7022 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7023 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7024 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7025 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7026 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7027 7028 if (alias_oc != oc) { 7029 continue; 7030 } 7031 /* 7032 * If running with KVM, we might update the family alias later, so 7033 * avoid printing the wrong alias here and use "preferred" instead 7034 */ 7035 if (strcmp(alias->alias, family->desc) == 0) { 7036 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7037 alias->alias, family->desc); 7038 } else { 7039 qemu_printf("PowerPC %-16s (alias for %s)\n", 7040 alias->alias, name); 7041 } 7042 } 7043 g_free(name); 7044 } 7045 7046 void ppc_cpu_list(void) 7047 { 7048 GSList *list; 7049 7050 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7051 list = g_slist_sort(list, ppc_cpu_list_compare); 7052 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7053 g_slist_free(list); 7054 7055 #ifdef CONFIG_KVM 7056 qemu_printf("\n"); 7057 qemu_printf("PowerPC %s\n", "host"); 7058 #endif 7059 } 7060 7061 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7062 { 7063 ObjectClass *oc = data; 7064 CpuDefinitionInfoList **first = user_data; 7065 const char *typename; 7066 CpuDefinitionInfo *info; 7067 7068 typename = object_class_get_name(oc); 7069 info = g_malloc0(sizeof(*info)); 7070 info->name = g_strndup(typename, 7071 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7072 7073 QAPI_LIST_PREPEND(*first, info); 7074 } 7075 7076 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7077 { 7078 CpuDefinitionInfoList *cpu_list = NULL; 7079 GSList *list; 7080 int i; 7081 7082 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7083 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7084 g_slist_free(list); 7085 7086 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7087 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7088 ObjectClass *oc; 7089 CpuDefinitionInfo *info; 7090 7091 oc = ppc_cpu_class_by_name(alias->model); 7092 if (oc == NULL) { 7093 continue; 7094 } 7095 7096 info = g_malloc0(sizeof(*info)); 7097 info->name = g_strdup(alias->alias); 7098 info->q_typename = g_strdup(object_class_get_name(oc)); 7099 7100 QAPI_LIST_PREPEND(cpu_list, info); 7101 } 7102 7103 return cpu_list; 7104 } 7105 7106 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7107 { 7108 PowerPCCPU *cpu = POWERPC_CPU(cs); 7109 7110 cpu->env.nip = value; 7111 } 7112 7113 static bool ppc_cpu_has_work(CPUState *cs) 7114 { 7115 PowerPCCPU *cpu = POWERPC_CPU(cs); 7116 CPUPPCState *env = &cpu->env; 7117 7118 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7119 } 7120 7121 static void ppc_cpu_reset(DeviceState *dev) 7122 { 7123 CPUState *s = CPU(dev); 7124 PowerPCCPU *cpu = POWERPC_CPU(s); 7125 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7126 CPUPPCState *env = &cpu->env; 7127 target_ulong msr; 7128 int i; 7129 7130 pcc->parent_reset(dev); 7131 7132 msr = (target_ulong)0; 7133 msr |= (target_ulong)MSR_HVB; 7134 msr |= (target_ulong)1 << MSR_EP; 7135 #if defined(DO_SINGLE_STEP) && 0 7136 /* Single step trace mode */ 7137 msr |= (target_ulong)1 << MSR_SE; 7138 msr |= (target_ulong)1 << MSR_BE; 7139 #endif 7140 #if defined(CONFIG_USER_ONLY) 7141 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7142 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7143 msr |= (target_ulong)1 << MSR_FE1; 7144 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7145 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7146 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7147 msr |= (target_ulong)1 << MSR_PR; 7148 #if defined(TARGET_PPC64) 7149 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7150 #endif 7151 #if !defined(TARGET_WORDS_BIGENDIAN) 7152 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7153 if (!((env->msr_mask >> MSR_LE) & 1)) { 7154 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7155 exit(1); 7156 } 7157 #endif 7158 #endif 7159 7160 #if defined(TARGET_PPC64) 7161 if (mmu_is_64bit(env->mmu_model)) { 7162 msr |= (1ULL << MSR_SF); 7163 } 7164 #endif 7165 7166 hreg_store_msr(env, msr, 1); 7167 7168 #if !defined(CONFIG_USER_ONLY) 7169 env->nip = env->hreset_vector | env->excp_prefix; 7170 #if defined(CONFIG_TCG) 7171 if (env->mmu_model != POWERPC_MMU_REAL) { 7172 ppc_tlb_invalidate_all(env); 7173 } 7174 #endif /* CONFIG_TCG */ 7175 #endif 7176 7177 pmu_update_summaries(env); 7178 hreg_compute_hflags(env); 7179 env->reserve_addr = (target_ulong)-1ULL; 7180 /* Be sure no exception or interrupt is pending */ 7181 env->pending_interrupts = 0; 7182 s->exception_index = POWERPC_EXCP_NONE; 7183 env->error_code = 0; 7184 ppc_irq_reset(cpu); 7185 7186 /* tininess for underflow is detected before rounding */ 7187 set_float_detect_tininess(float_tininess_before_rounding, 7188 &env->fp_status); 7189 7190 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7191 ppc_spr_t *spr = &env->spr_cb[i]; 7192 7193 if (!spr->name) { 7194 continue; 7195 } 7196 env->spr[i] = spr->default_value; 7197 } 7198 } 7199 7200 #ifndef CONFIG_USER_ONLY 7201 7202 static bool ppc_cpu_is_big_endian(CPUState *cs) 7203 { 7204 PowerPCCPU *cpu = POWERPC_CPU(cs); 7205 CPUPPCState *env = &cpu->env; 7206 7207 cpu_synchronize_state(cs); 7208 7209 return !msr_le; 7210 } 7211 7212 #ifdef CONFIG_TCG 7213 static void ppc_cpu_exec_enter(CPUState *cs) 7214 { 7215 PowerPCCPU *cpu = POWERPC_CPU(cs); 7216 7217 if (cpu->vhyp) { 7218 PPCVirtualHypervisorClass *vhc = 7219 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7220 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7221 } 7222 } 7223 7224 static void ppc_cpu_exec_exit(CPUState *cs) 7225 { 7226 PowerPCCPU *cpu = POWERPC_CPU(cs); 7227 7228 if (cpu->vhyp) { 7229 PPCVirtualHypervisorClass *vhc = 7230 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7231 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7232 } 7233 } 7234 #endif /* CONFIG_TCG */ 7235 7236 #endif /* !CONFIG_USER_ONLY */ 7237 7238 static void ppc_cpu_instance_init(Object *obj) 7239 { 7240 PowerPCCPU *cpu = POWERPC_CPU(obj); 7241 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7242 CPUPPCState *env = &cpu->env; 7243 7244 cpu_set_cpustate_pointers(cpu); 7245 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7246 7247 env->msr_mask = pcc->msr_mask; 7248 env->mmu_model = pcc->mmu_model; 7249 env->excp_model = pcc->excp_model; 7250 env->bus_model = pcc->bus_model; 7251 env->insns_flags = pcc->insns_flags; 7252 env->insns_flags2 = pcc->insns_flags2; 7253 env->flags = pcc->flags; 7254 env->bfd_mach = pcc->bfd_mach; 7255 env->check_pow = pcc->check_pow; 7256 7257 /* 7258 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7259 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7260 * mode support will remain, thus enforcing that we cannot use 7261 * priv. instructions in guest in PAPR mode. For 970 we currently 7262 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7263 * 970. If we ever want to support 970 HV mode, we'll have to add 7264 * a processor attribute of some sort. 7265 */ 7266 #if !defined(CONFIG_USER_ONLY) 7267 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7268 #endif 7269 7270 ppc_hash64_init(cpu); 7271 } 7272 7273 static void ppc_cpu_instance_finalize(Object *obj) 7274 { 7275 PowerPCCPU *cpu = POWERPC_CPU(obj); 7276 7277 ppc_hash64_finalize(cpu); 7278 } 7279 7280 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7281 { 7282 return pcc->pvr == pvr; 7283 } 7284 7285 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7286 { 7287 PowerPCCPU *cpu = POWERPC_CPU(cs); 7288 CPUPPCState *env = &cpu->env; 7289 7290 if ((env->hflags >> MSR_LE) & 1) { 7291 info->endian = BFD_ENDIAN_LITTLE; 7292 } 7293 info->mach = env->bfd_mach; 7294 if (!env->bfd_mach) { 7295 #ifdef TARGET_PPC64 7296 info->mach = bfd_mach_ppc64; 7297 #else 7298 info->mach = bfd_mach_ppc; 7299 #endif 7300 } 7301 info->disassembler_options = (char *)"any"; 7302 info->print_insn = print_insn_ppc; 7303 7304 info->cap_arch = CS_ARCH_PPC; 7305 #ifdef TARGET_PPC64 7306 info->cap_mode = CS_MODE_64; 7307 #endif 7308 } 7309 7310 static Property ppc_cpu_properties[] = { 7311 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7312 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7313 false), 7314 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7315 false), 7316 DEFINE_PROP_END_OF_LIST(), 7317 }; 7318 7319 #ifndef CONFIG_USER_ONLY 7320 #include "hw/core/sysemu-cpu-ops.h" 7321 7322 static const struct SysemuCPUOps ppc_sysemu_ops = { 7323 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7324 .write_elf32_note = ppc32_cpu_write_elf32_note, 7325 .write_elf64_note = ppc64_cpu_write_elf64_note, 7326 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7327 .legacy_vmsd = &vmstate_ppc_cpu, 7328 }; 7329 #endif 7330 7331 #ifdef CONFIG_TCG 7332 #include "hw/core/tcg-cpu-ops.h" 7333 7334 static const struct TCGCPUOps ppc_tcg_ops = { 7335 .initialize = ppc_translate_init, 7336 7337 #ifdef CONFIG_USER_ONLY 7338 .record_sigsegv = ppc_cpu_record_sigsegv, 7339 #else 7340 .tlb_fill = ppc_cpu_tlb_fill, 7341 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7342 .do_interrupt = ppc_cpu_do_interrupt, 7343 .cpu_exec_enter = ppc_cpu_exec_enter, 7344 .cpu_exec_exit = ppc_cpu_exec_exit, 7345 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7346 #endif /* !CONFIG_USER_ONLY */ 7347 }; 7348 #endif /* CONFIG_TCG */ 7349 7350 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7351 { 7352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7353 CPUClass *cc = CPU_CLASS(oc); 7354 DeviceClass *dc = DEVICE_CLASS(oc); 7355 7356 device_class_set_parent_realize(dc, ppc_cpu_realize, 7357 &pcc->parent_realize); 7358 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7359 &pcc->parent_unrealize); 7360 pcc->pvr_match = ppc_pvr_match_default; 7361 device_class_set_props(dc, ppc_cpu_properties); 7362 7363 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7364 7365 cc->class_by_name = ppc_cpu_class_by_name; 7366 cc->has_work = ppc_cpu_has_work; 7367 cc->dump_state = ppc_cpu_dump_state; 7368 cc->set_pc = ppc_cpu_set_pc; 7369 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7370 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7371 #ifndef CONFIG_USER_ONLY 7372 cc->sysemu_ops = &ppc_sysemu_ops; 7373 #endif 7374 7375 cc->gdb_num_core_regs = 71; 7376 #ifndef CONFIG_USER_ONLY 7377 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7378 #endif 7379 #ifdef USE_APPLE_GDB 7380 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7381 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7382 cc->gdb_num_core_regs = 71 + 32; 7383 #endif 7384 7385 cc->gdb_arch_name = ppc_gdb_arch_name; 7386 #if defined(TARGET_PPC64) 7387 cc->gdb_core_xml_file = "power64-core.xml"; 7388 #else 7389 cc->gdb_core_xml_file = "power-core.xml"; 7390 #endif 7391 cc->disas_set_info = ppc_disas_set_info; 7392 7393 dc->fw_name = "PowerPC,UNKNOWN"; 7394 7395 #ifdef CONFIG_TCG 7396 cc->tcg_ops = &ppc_tcg_ops; 7397 #endif /* CONFIG_TCG */ 7398 } 7399 7400 static const TypeInfo ppc_cpu_type_info = { 7401 .name = TYPE_POWERPC_CPU, 7402 .parent = TYPE_CPU, 7403 .instance_size = sizeof(PowerPCCPU), 7404 .instance_align = __alignof__(PowerPCCPU), 7405 .instance_init = ppc_cpu_instance_init, 7406 .instance_finalize = ppc_cpu_instance_finalize, 7407 .abstract = true, 7408 .class_size = sizeof(PowerPCCPUClass), 7409 .class_init = ppc_cpu_class_init, 7410 }; 7411 7412 #ifndef CONFIG_USER_ONLY 7413 static const TypeInfo ppc_vhyp_type_info = { 7414 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7415 .parent = TYPE_INTERFACE, 7416 .class_size = sizeof(PPCVirtualHypervisorClass), 7417 }; 7418 #endif 7419 7420 static void ppc_cpu_register_types(void) 7421 { 7422 type_register_static(&ppc_cpu_type_info); 7423 #ifndef CONFIG_USER_ONLY 7424 type_register_static(&ppc_vhyp_type_info); 7425 #endif 7426 } 7427 7428 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7429 { 7430 #define RGPL 4 7431 #define RFPL 4 7432 7433 PowerPCCPU *cpu = POWERPC_CPU(cs); 7434 CPUPPCState *env = &cpu->env; 7435 int i; 7436 7437 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7438 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7439 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7440 cs->cpu_index); 7441 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7442 "%08x iidx %d didx %d\n", 7443 env->msr, env->spr[SPR_HID0], env->hflags, 7444 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7445 #if !defined(NO_TIMER_DUMP) 7446 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7447 #if !defined(CONFIG_USER_ONLY) 7448 " DECR " TARGET_FMT_lu 7449 #endif 7450 "\n", 7451 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7452 #if !defined(CONFIG_USER_ONLY) 7453 , cpu_ppc_load_decr(env) 7454 #endif 7455 ); 7456 #endif 7457 for (i = 0; i < 32; i++) { 7458 if ((i & (RGPL - 1)) == 0) { 7459 qemu_fprintf(f, "GPR%02d", i); 7460 } 7461 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7462 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7463 qemu_fprintf(f, "\n"); 7464 } 7465 } 7466 qemu_fprintf(f, "CR "); 7467 for (i = 0; i < 8; i++) 7468 qemu_fprintf(f, "%01x", env->crf[i]); 7469 qemu_fprintf(f, " ["); 7470 for (i = 0; i < 8; i++) { 7471 char a = '-'; 7472 if (env->crf[i] & 0x08) { 7473 a = 'L'; 7474 } else if (env->crf[i] & 0x04) { 7475 a = 'G'; 7476 } else if (env->crf[i] & 0x02) { 7477 a = 'E'; 7478 } 7479 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7480 } 7481 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7482 env->reserve_addr); 7483 7484 if (flags & CPU_DUMP_FPU) { 7485 for (i = 0; i < 32; i++) { 7486 if ((i & (RFPL - 1)) == 0) { 7487 qemu_fprintf(f, "FPR%02d", i); 7488 } 7489 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7490 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7491 qemu_fprintf(f, "\n"); 7492 } 7493 } 7494 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7495 } 7496 7497 #if !defined(CONFIG_USER_ONLY) 7498 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7499 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7500 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7501 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7502 7503 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7504 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7505 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7506 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7507 7508 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7509 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7510 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7511 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7512 7513 switch (env->excp_model) { 7514 #if defined(TARGET_PPC64) 7515 case POWERPC_EXCP_POWER7: 7516 case POWERPC_EXCP_POWER8: 7517 case POWERPC_EXCP_POWER9: 7518 case POWERPC_EXCP_POWER10: 7519 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7520 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7521 break; 7522 #endif 7523 case POWERPC_EXCP_BOOKE: 7524 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7525 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7526 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7527 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7528 7529 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7530 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7531 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7532 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7533 7534 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7535 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7536 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7537 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7538 7539 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7540 " EPR " TARGET_FMT_lx "\n", 7541 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7542 env->spr[SPR_BOOKE_EPR]); 7543 7544 /* FSL-specific */ 7545 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7546 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7547 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7548 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7549 7550 /* 7551 * IVORs are left out as they are large and do not change often -- 7552 * they can be read with "p $ivor0", "p $ivor1", etc. 7553 */ 7554 break; 7555 case POWERPC_EXCP_40x: 7556 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7557 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7558 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7559 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7560 7561 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7562 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7563 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7564 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7565 break; 7566 default: 7567 break; 7568 } 7569 7570 #if defined(TARGET_PPC64) 7571 if (env->flags & POWERPC_FLAG_CFAR) { 7572 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7573 } 7574 #endif 7575 7576 if (env->spr_cb[SPR_LPCR].name) { 7577 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7578 } 7579 7580 switch (env->mmu_model) { 7581 case POWERPC_MMU_32B: 7582 case POWERPC_MMU_SOFT_6xx: 7583 #if defined(TARGET_PPC64) 7584 case POWERPC_MMU_64B: 7585 case POWERPC_MMU_2_03: 7586 case POWERPC_MMU_2_06: 7587 case POWERPC_MMU_2_07: 7588 case POWERPC_MMU_3_00: 7589 #endif 7590 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7591 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7592 } 7593 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7594 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7595 } 7596 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7597 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7598 break; 7599 case POWERPC_MMU_BOOKE206: 7600 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7601 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7602 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7603 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7604 7605 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7606 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7607 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7608 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7609 7610 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7611 " TLB1CFG " TARGET_FMT_lx "\n", 7612 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7613 env->spr[SPR_BOOKE_TLB1CFG]); 7614 break; 7615 default: 7616 break; 7617 } 7618 #endif 7619 7620 #undef RGPL 7621 #undef RFPL 7622 } 7623 type_init(ppc_cpu_register_types) 7624