1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/arch_init.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/hw_accel.h" 28 #include "sysemu/tcg.h" 29 #include "cpu-models.h" 30 #include "mmu-hash32.h" 31 #include "mmu-hash64.h" 32 #include "qemu/error-report.h" 33 #include "qemu/module.h" 34 #include "qemu/qemu-print.h" 35 #include "qapi/error.h" 36 #include "qapi/qmp/qnull.h" 37 #include "qapi/visitor.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/ppc/ppc.h" 40 #include "mmu-book3s-v3.h" 41 #include "qemu/cutils.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 #include "qapi/qapi-commands-machine-target.h" 45 46 #include "helper_regs.h" 47 #include "internal.h" 48 #include "spr_tcg.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 602 implementation */ 753 static void register_602_sprs(CPUPPCState *env) 754 { 755 /* ESA registers */ 756 /* XXX : not implemented */ 757 spr_register(env, SPR_SER, "SER", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* XXX : not implemented */ 762 spr_register(env, SPR_SEBR, "SEBR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* XXX : not implemented */ 767 spr_register(env, SPR_ESASRR, "ESASRR", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 /* Floating point status */ 772 /* XXX : not implemented */ 773 spr_register(env, SPR_SP, "SP", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* XXX : not implemented */ 778 spr_register(env, SPR_LT, "LT", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 /* Watchdog timer */ 783 /* XXX : not implemented */ 784 spr_register(env, SPR_TCR, "TCR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 /* Interrupt base */ 789 spr_register(env, SPR_IBR, "IBR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* XXX : not implemented */ 794 spr_register(env, SPR_IABR, "IABR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 } 799 800 /* SPR specific to PowerPC 601 implementation */ 801 static void register_601_sprs(CPUPPCState *env) 802 { 803 /* Multiplication/division register */ 804 /* MQ */ 805 spr_register(env, SPR_MQ, "MQ", 806 &spr_read_generic, &spr_write_generic, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 /* RTC registers */ 810 spr_register(env, SPR_601_RTCU, "RTCU", 811 SPR_NOACCESS, SPR_NOACCESS, 812 SPR_NOACCESS, &spr_write_601_rtcu, 813 0x00000000); 814 spr_register(env, SPR_601_VRTCU, "RTCU", 815 &spr_read_601_rtcu, SPR_NOACCESS, 816 &spr_read_601_rtcu, SPR_NOACCESS, 817 0x00000000); 818 spr_register(env, SPR_601_RTCL, "RTCL", 819 SPR_NOACCESS, SPR_NOACCESS, 820 SPR_NOACCESS, &spr_write_601_rtcl, 821 0x00000000); 822 spr_register(env, SPR_601_VRTCL, "RTCL", 823 &spr_read_601_rtcl, SPR_NOACCESS, 824 &spr_read_601_rtcl, SPR_NOACCESS, 825 0x00000000); 826 /* Timer */ 827 #if 0 /* ? */ 828 spr_register(env, SPR_601_UDECR, "UDECR", 829 &spr_read_decr, SPR_NOACCESS, 830 &spr_read_decr, SPR_NOACCESS, 831 0x00000000); 832 #endif 833 /* External access control */ 834 /* XXX : not implemented */ 835 spr_register(env, SPR_EAR, "EAR", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 /* Memory management */ 840 #if !defined(CONFIG_USER_ONLY) 841 spr_register(env, SPR_IBAT0U, "IBAT0U", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_601_ubat, &spr_write_601_ubatu, 844 0x00000000); 845 spr_register(env, SPR_IBAT0L, "IBAT0L", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_601_ubat, &spr_write_601_ubatl, 848 0x00000000); 849 spr_register(env, SPR_IBAT1U, "IBAT1U", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_601_ubat, &spr_write_601_ubatu, 852 0x00000000); 853 spr_register(env, SPR_IBAT1L, "IBAT1L", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_601_ubat, &spr_write_601_ubatl, 856 0x00000000); 857 spr_register(env, SPR_IBAT2U, "IBAT2U", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_601_ubat, &spr_write_601_ubatu, 860 0x00000000); 861 spr_register(env, SPR_IBAT2L, "IBAT2L", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_601_ubat, &spr_write_601_ubatl, 864 0x00000000); 865 spr_register(env, SPR_IBAT3U, "IBAT3U", 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_601_ubat, &spr_write_601_ubatu, 868 0x00000000); 869 spr_register(env, SPR_IBAT3L, "IBAT3L", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_601_ubat, &spr_write_601_ubatl, 872 0x00000000); 873 env->nb_BATs = 4; 874 #endif 875 } 876 877 static void register_74xx_sprs(CPUPPCState *env) 878 { 879 /* Processor identification */ 880 spr_register(env, SPR_PIR, "PIR", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_pir, 883 0x00000000); 884 /* XXX : not implemented */ 885 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 886 SPR_NOACCESS, SPR_NOACCESS, 887 &spr_read_generic, &spr_write_generic, 888 0x00000000); 889 /* XXX : not implemented */ 890 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 891 &spr_read_ureg, SPR_NOACCESS, 892 &spr_read_ureg, SPR_NOACCESS, 893 0x00000000); 894 /* XXX: not implemented */ 895 spr_register(env, SPR_BAMR, "BAMR", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 /* XXX : not implemented */ 900 spr_register(env, SPR_MSSCR0, "MSSCR0", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_generic, 903 0x00000000); 904 /* Hardware implementation registers */ 905 /* XXX : not implemented */ 906 spr_register(env, SPR_HID0, "HID0", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 /* XXX : not implemented */ 911 spr_register(env, SPR_HID1, "HID1", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 /* Altivec */ 916 spr_register(env, SPR_VRSAVE, "VRSAVE", 917 &spr_read_generic, &spr_write_generic, 918 &spr_read_generic, &spr_write_generic, 919 0x00000000); 920 /* XXX : not implemented */ 921 spr_register(env, SPR_L2CR, "L2CR", 922 SPR_NOACCESS, SPR_NOACCESS, 923 &spr_read_generic, spr_access_nop, 924 0x00000000); 925 } 926 927 static void register_l3_ctrl(CPUPPCState *env) 928 { 929 /* L3CR */ 930 /* XXX : not implemented */ 931 spr_register(env, SPR_L3CR, "L3CR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 /* L3ITCR0 */ 936 /* XXX : not implemented */ 937 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 /* L3PM */ 942 /* XXX : not implemented */ 943 spr_register(env, SPR_L3PM, "L3PM", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 } 948 949 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 950 { 951 #if !defined(CONFIG_USER_ONLY) 952 env->nb_tlb = nb_tlbs; 953 env->nb_ways = nb_ways; 954 env->id_tlbs = 1; 955 env->tlb_type = TLB_6XX; 956 /* XXX : not implemented */ 957 spr_register(env, SPR_PTEHI, "PTEHI", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 /* XXX : not implemented */ 962 spr_register(env, SPR_PTELO, "PTELO", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 /* XXX : not implemented */ 967 spr_register(env, SPR_TLBMISS, "TLBMISS", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 #endif 972 } 973 974 static void register_usprg3_sprs(CPUPPCState *env) 975 { 976 spr_register(env, SPR_USPRG3, "USPRG3", 977 &spr_read_ureg, SPR_NOACCESS, 978 &spr_read_ureg, SPR_NOACCESS, 979 0x00000000); 980 } 981 982 static void register_usprgh_sprs(CPUPPCState *env) 983 { 984 spr_register(env, SPR_USPRG4, "USPRG4", 985 &spr_read_ureg, SPR_NOACCESS, 986 &spr_read_ureg, SPR_NOACCESS, 987 0x00000000); 988 spr_register(env, SPR_USPRG5, "USPRG5", 989 &spr_read_ureg, SPR_NOACCESS, 990 &spr_read_ureg, SPR_NOACCESS, 991 0x00000000); 992 spr_register(env, SPR_USPRG6, "USPRG6", 993 &spr_read_ureg, SPR_NOACCESS, 994 &spr_read_ureg, SPR_NOACCESS, 995 0x00000000); 996 spr_register(env, SPR_USPRG7, "USPRG7", 997 &spr_read_ureg, SPR_NOACCESS, 998 &spr_read_ureg, SPR_NOACCESS, 999 0x00000000); 1000 } 1001 1002 /* PowerPC BookE SPR */ 1003 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1004 { 1005 const char *ivor_names[64] = { 1006 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1007 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1008 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1009 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1010 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1011 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1012 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1013 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1014 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1015 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1016 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1017 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1018 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1019 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1020 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1021 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1022 }; 1023 #define SPR_BOOKE_IVORxx (-1) 1024 int ivor_sprn[64] = { 1025 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1026 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1027 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1028 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1029 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1030 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1031 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1032 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1033 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1034 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1035 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1036 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1037 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1038 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1039 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1040 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1041 }; 1042 int i; 1043 1044 /* Interrupt processing */ 1045 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1046 SPR_NOACCESS, SPR_NOACCESS, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1050 SPR_NOACCESS, SPR_NOACCESS, 1051 &spr_read_generic, &spr_write_generic, 1052 0x00000000); 1053 /* Debug */ 1054 /* XXX : not implemented */ 1055 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 /* XXX : not implemented */ 1060 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 /* XXX : not implemented */ 1065 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, &spr_write_generic, 1068 0x00000000); 1069 /* XXX : not implemented */ 1070 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 /* XXX : not implemented */ 1075 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1076 SPR_NOACCESS, SPR_NOACCESS, 1077 &spr_read_generic, &spr_write_40x_dbcr0, 1078 0x00000000); 1079 /* XXX : not implemented */ 1080 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 /* XXX : not implemented */ 1085 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_generic, 1088 0x00000000); 1089 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, &spr_write_generic, 1092 0x00000000); 1093 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, &spr_write_generic, 1096 0x00000000); 1097 /* XXX : not implemented */ 1098 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1099 SPR_NOACCESS, SPR_NOACCESS, 1100 &spr_read_generic, &spr_write_clear, 1101 0x00000000); 1102 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, &spr_write_generic, 1105 0x00000000); 1106 spr_register(env, SPR_BOOKE_ESR, "ESR", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, &spr_write_generic, 1109 0x00000000); 1110 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_excp_prefix, 1113 0x00000000); 1114 /* Exception vectors */ 1115 for (i = 0; i < 64; i++) { 1116 if (ivor_mask & (1ULL << i)) { 1117 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1118 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1119 exit(1); 1120 } 1121 spr_register(env, ivor_sprn[i], ivor_names[i], 1122 SPR_NOACCESS, SPR_NOACCESS, 1123 &spr_read_generic, &spr_write_excp_vector, 1124 0x00000000); 1125 } 1126 } 1127 spr_register(env, SPR_BOOKE_PID, "PID", 1128 SPR_NOACCESS, SPR_NOACCESS, 1129 &spr_read_generic, &spr_write_booke_pid, 1130 0x00000000); 1131 spr_register(env, SPR_BOOKE_TCR, "TCR", 1132 SPR_NOACCESS, SPR_NOACCESS, 1133 &spr_read_generic, &spr_write_booke_tcr, 1134 0x00000000); 1135 spr_register(env, SPR_BOOKE_TSR, "TSR", 1136 SPR_NOACCESS, SPR_NOACCESS, 1137 &spr_read_generic, &spr_write_booke_tsr, 1138 0x00000000); 1139 /* Timer */ 1140 spr_register(env, SPR_DECR, "DECR", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_decr, &spr_write_decr, 1143 0x00000000); 1144 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 SPR_NOACCESS, &spr_write_generic, 1147 0x00000000); 1148 /* SPRGs */ 1149 spr_register(env, SPR_USPRG0, "USPRG0", 1150 &spr_read_generic, &spr_write_generic, 1151 &spr_read_generic, &spr_write_generic, 1152 0x00000000); 1153 spr_register(env, SPR_SPRG4, "SPRG4", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00000000); 1157 spr_register(env, SPR_SPRG5, "SPRG5", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 spr_register(env, SPR_SPRG6, "SPRG6", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 spr_register(env, SPR_SPRG7, "SPRG7", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_generic, 1168 0x00000000); 1169 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1170 SPR_NOACCESS, SPR_NOACCESS, 1171 &spr_read_generic, &spr_write_generic, 1172 0x00000000); 1173 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 } 1178 1179 #if !defined(CONFIG_USER_ONLY) 1180 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1181 uint32_t maxsize, uint32_t flags, 1182 uint32_t nentries) 1183 { 1184 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1185 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1186 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1187 flags | nentries; 1188 } 1189 #endif /* !CONFIG_USER_ONLY */ 1190 1191 /* BookE 2.06 storage control registers */ 1192 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1193 uint32_t *tlbncfg, uint32_t mmucfg) 1194 { 1195 #if !defined(CONFIG_USER_ONLY) 1196 const char *mas_names[8] = { 1197 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1198 }; 1199 int mas_sprn[8] = { 1200 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1201 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1202 }; 1203 int i; 1204 1205 /* TLB assist registers */ 1206 /* XXX : not implemented */ 1207 for (i = 0; i < 8; i++) { 1208 if (mas_mask & (1 << i)) { 1209 spr_register(env, mas_sprn[i], mas_names[i], 1210 SPR_NOACCESS, SPR_NOACCESS, 1211 &spr_read_generic, 1212 (i == 2 && (env->insns_flags & PPC_64B)) 1213 ? &spr_write_generic : &spr_write_generic32, 1214 0x00000000); 1215 } 1216 } 1217 if (env->nb_pids > 1) { 1218 /* XXX : not implemented */ 1219 spr_register(env, SPR_BOOKE_PID1, "PID1", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_booke_pid, 1222 0x00000000); 1223 } 1224 if (env->nb_pids > 2) { 1225 /* XXX : not implemented */ 1226 spr_register(env, SPR_BOOKE_PID2, "PID2", 1227 SPR_NOACCESS, SPR_NOACCESS, 1228 &spr_read_generic, &spr_write_booke_pid, 1229 0x00000000); 1230 } 1231 1232 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_eplc, 1235 0x00000000); 1236 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 &spr_read_generic, &spr_write_epsc, 1239 0x00000000); 1240 1241 /* XXX : not implemented */ 1242 spr_register(env, SPR_MMUCFG, "MMUCFG", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, SPR_NOACCESS, 1245 mmucfg); 1246 switch (env->nb_ways) { 1247 case 4: 1248 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1249 SPR_NOACCESS, SPR_NOACCESS, 1250 &spr_read_generic, SPR_NOACCESS, 1251 tlbncfg[3]); 1252 /* Fallthru */ 1253 case 3: 1254 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 &spr_read_generic, SPR_NOACCESS, 1257 tlbncfg[2]); 1258 /* Fallthru */ 1259 case 2: 1260 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1261 SPR_NOACCESS, SPR_NOACCESS, 1262 &spr_read_generic, SPR_NOACCESS, 1263 tlbncfg[1]); 1264 /* Fallthru */ 1265 case 1: 1266 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, SPR_NOACCESS, 1269 tlbncfg[0]); 1270 /* Fallthru */ 1271 case 0: 1272 default: 1273 break; 1274 } 1275 #endif 1276 1277 register_usprgh_sprs(env); 1278 } 1279 1280 /* SPR specific to PowerPC 440 implementation */ 1281 static void register_440_sprs(CPUPPCState *env) 1282 { 1283 /* Cache control */ 1284 /* XXX : not implemented */ 1285 spr_register(env, SPR_440_DNV0, "DNV0", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_generic, &spr_write_generic, 1288 0x00000000); 1289 /* XXX : not implemented */ 1290 spr_register(env, SPR_440_DNV1, "DNV1", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 /* XXX : not implemented */ 1295 spr_register(env, SPR_440_DNV2, "DNV2", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 /* XXX : not implemented */ 1300 spr_register(env, SPR_440_DNV3, "DNV3", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 /* XXX : not implemented */ 1305 spr_register(env, SPR_440_DTV0, "DTV0", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 /* XXX : not implemented */ 1310 spr_register(env, SPR_440_DTV1, "DTV1", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 /* XXX : not implemented */ 1315 spr_register(env, SPR_440_DTV2, "DTV2", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 /* XXX : not implemented */ 1320 spr_register(env, SPR_440_DTV3, "DTV3", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 /* XXX : not implemented */ 1325 spr_register(env, SPR_440_DVLIM, "DVLIM", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 /* XXX : not implemented */ 1330 spr_register(env, SPR_440_INV0, "INV0", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 /* XXX : not implemented */ 1335 spr_register(env, SPR_440_INV1, "INV1", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 /* XXX : not implemented */ 1340 spr_register(env, SPR_440_INV2, "INV2", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 /* XXX : not implemented */ 1345 spr_register(env, SPR_440_INV3, "INV3", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 /* XXX : not implemented */ 1350 spr_register(env, SPR_440_ITV0, "ITV0", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 /* XXX : not implemented */ 1355 spr_register(env, SPR_440_ITV1, "ITV1", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 /* XXX : not implemented */ 1360 spr_register(env, SPR_440_ITV2, "ITV2", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 /* XXX : not implemented */ 1365 spr_register(env, SPR_440_ITV3, "ITV3", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 /* XXX : not implemented */ 1370 spr_register(env, SPR_440_IVLIM, "IVLIM", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 /* Cache debug */ 1375 /* XXX : not implemented */ 1376 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, SPR_NOACCESS, 1379 0x00000000); 1380 /* XXX : not implemented */ 1381 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, SPR_NOACCESS, 1384 0x00000000); 1385 /* XXX : not implemented */ 1386 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1387 SPR_NOACCESS, SPR_NOACCESS, 1388 &spr_read_generic, SPR_NOACCESS, 1389 0x00000000); 1390 /* XXX : not implemented */ 1391 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1392 SPR_NOACCESS, SPR_NOACCESS, 1393 &spr_read_generic, SPR_NOACCESS, 1394 0x00000000); 1395 /* XXX : not implemented */ 1396 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 &spr_read_generic, SPR_NOACCESS, 1399 0x00000000); 1400 /* XXX : not implemented */ 1401 spr_register(env, SPR_440_DBDR, "DBDR", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 /* Processor control */ 1406 spr_register(env, SPR_4xx_CCR0, "CCR0", 1407 SPR_NOACCESS, SPR_NOACCESS, 1408 &spr_read_generic, &spr_write_generic, 1409 0x00000000); 1410 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, SPR_NOACCESS, 1413 0x00000000); 1414 /* Storage control */ 1415 spr_register(env, SPR_440_MMUCR, "MMUCR", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 0x00000000); 1419 } 1420 1421 /* SPR shared between PowerPC 40x implementations */ 1422 static void register_40x_sprs(CPUPPCState *env) 1423 { 1424 /* Cache */ 1425 /* not emulated, as QEMU do not emulate caches */ 1426 spr_register(env, SPR_40x_DCCR, "DCCR", 1427 SPR_NOACCESS, SPR_NOACCESS, 1428 &spr_read_generic, &spr_write_generic, 1429 0x00000000); 1430 /* not emulated, as QEMU do not emulate caches */ 1431 spr_register(env, SPR_40x_ICCR, "ICCR", 1432 SPR_NOACCESS, SPR_NOACCESS, 1433 &spr_read_generic, &spr_write_generic, 1434 0x00000000); 1435 /* not emulated, as QEMU do not emulate caches */ 1436 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1437 SPR_NOACCESS, SPR_NOACCESS, 1438 &spr_read_generic, SPR_NOACCESS, 1439 0x00000000); 1440 /* Exception */ 1441 spr_register(env, SPR_40x_DEAR, "DEAR", 1442 SPR_NOACCESS, SPR_NOACCESS, 1443 &spr_read_generic, &spr_write_generic, 1444 0x00000000); 1445 spr_register(env, SPR_40x_ESR, "ESR", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 spr_register(env, SPR_40x_EVPR, "EVPR", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, &spr_write_excp_prefix, 1452 0x00000000); 1453 spr_register(env, SPR_40x_SRR2, "SRR2", 1454 &spr_read_generic, &spr_write_generic, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 spr_register(env, SPR_40x_SRR3, "SRR3", 1458 &spr_read_generic, &spr_write_generic, 1459 &spr_read_generic, &spr_write_generic, 1460 0x00000000); 1461 /* Timers */ 1462 spr_register(env, SPR_40x_PIT, "PIT", 1463 SPR_NOACCESS, SPR_NOACCESS, 1464 &spr_read_40x_pit, &spr_write_40x_pit, 1465 0x00000000); 1466 spr_register(env, SPR_40x_TCR, "TCR", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_booke_tcr, 1469 0x00000000); 1470 spr_register(env, SPR_40x_TSR, "TSR", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_booke_tsr, 1473 0x00000000); 1474 } 1475 1476 /* SPR specific to PowerPC 405 implementation */ 1477 static void register_405_sprs(CPUPPCState *env) 1478 { 1479 /* MMU */ 1480 spr_register(env, SPR_40x_PID, "PID", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 spr_register(env, SPR_4xx_CCR0, "CCR0", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, &spr_write_generic, 1487 0x00700000); 1488 /* Debug interface */ 1489 /* XXX : not implemented */ 1490 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_40x_dbcr0, 1493 0x00000000); 1494 /* XXX : not implemented */ 1495 spr_register(env, SPR_405_DBCR1, "DBCR1", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 /* XXX : not implemented */ 1500 spr_register(env, SPR_40x_DBSR, "DBSR", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_clear, 1503 /* Last reset was system reset */ 1504 0x00000300); 1505 /* XXX : not implemented */ 1506 spr_register(env, SPR_40x_DAC1, "DAC1", 1507 SPR_NOACCESS, SPR_NOACCESS, 1508 &spr_read_generic, &spr_write_generic, 1509 0x00000000); 1510 spr_register(env, SPR_40x_DAC2, "DAC2", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 /* XXX : not implemented */ 1515 spr_register(env, SPR_405_DVC1, "DVC1", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 /* XXX : not implemented */ 1520 spr_register(env, SPR_405_DVC2, "DVC2", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 /* XXX : not implemented */ 1525 spr_register(env, SPR_40x_IAC1, "IAC1", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 spr_register(env, SPR_40x_IAC2, "IAC2", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 /* XXX : not implemented */ 1534 spr_register(env, SPR_405_IAC3, "IAC3", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 /* XXX : not implemented */ 1539 spr_register(env, SPR_405_IAC4, "IAC4", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 /* Storage control */ 1544 /* XXX: TODO: not implemented */ 1545 spr_register(env, SPR_405_SLER, "SLER", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_40x_sler, 1548 0x00000000); 1549 spr_register(env, SPR_40x_ZPR, "ZPR", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 /* XXX : not implemented */ 1554 spr_register(env, SPR_405_SU0R, "SU0R", 1555 SPR_NOACCESS, SPR_NOACCESS, 1556 &spr_read_generic, &spr_write_generic, 1557 0x00000000); 1558 /* SPRG */ 1559 spr_register(env, SPR_USPRG0, "USPRG0", 1560 &spr_read_ureg, SPR_NOACCESS, 1561 &spr_read_ureg, SPR_NOACCESS, 1562 0x00000000); 1563 spr_register(env, SPR_SPRG4, "SPRG4", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 spr_register(env, SPR_SPRG5, "SPRG5", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 spr_register(env, SPR_SPRG6, "SPRG6", 1572 SPR_NOACCESS, SPR_NOACCESS, 1573 spr_read_generic, &spr_write_generic, 1574 0x00000000); 1575 spr_register(env, SPR_SPRG7, "SPRG7", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 register_usprgh_sprs(env); 1580 } 1581 1582 /* SPR shared between PowerPC 401 & 403 implementations */ 1583 static void register_401_403_sprs(CPUPPCState *env) 1584 { 1585 /* Time base */ 1586 spr_register(env, SPR_403_VTBL, "TBL", 1587 &spr_read_tbl, SPR_NOACCESS, 1588 &spr_read_tbl, SPR_NOACCESS, 1589 0x00000000); 1590 spr_register(env, SPR_403_TBL, "TBL", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 SPR_NOACCESS, &spr_write_tbl, 1593 0x00000000); 1594 spr_register(env, SPR_403_VTBU, "TBU", 1595 &spr_read_tbu, SPR_NOACCESS, 1596 &spr_read_tbu, SPR_NOACCESS, 1597 0x00000000); 1598 spr_register(env, SPR_403_TBU, "TBU", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 SPR_NOACCESS, &spr_write_tbu, 1601 0x00000000); 1602 /* Debug */ 1603 /* not emulated, as QEMU do not emulate caches */ 1604 spr_register(env, SPR_403_CDBCR, "CDBCR", 1605 SPR_NOACCESS, SPR_NOACCESS, 1606 &spr_read_generic, &spr_write_generic, 1607 0x00000000); 1608 } 1609 1610 /* SPR specific to PowerPC 401 implementation */ 1611 static void register_401_sprs(CPUPPCState *env) 1612 { 1613 /* Debug interface */ 1614 /* XXX : not implemented */ 1615 spr_register(env, SPR_40x_DBCR0, "DBCR", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_40x_dbcr0, 1618 0x00000000); 1619 /* XXX : not implemented */ 1620 spr_register(env, SPR_40x_DBSR, "DBSR", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_generic, &spr_write_clear, 1623 /* Last reset was system reset */ 1624 0x00000300); 1625 /* XXX : not implemented */ 1626 spr_register(env, SPR_40x_DAC1, "DAC", 1627 SPR_NOACCESS, SPR_NOACCESS, 1628 &spr_read_generic, &spr_write_generic, 1629 0x00000000); 1630 /* XXX : not implemented */ 1631 spr_register(env, SPR_40x_IAC1, "IAC", 1632 SPR_NOACCESS, SPR_NOACCESS, 1633 &spr_read_generic, &spr_write_generic, 1634 0x00000000); 1635 /* Storage control */ 1636 /* XXX: TODO: not implemented */ 1637 spr_register(env, SPR_405_SLER, "SLER", 1638 SPR_NOACCESS, SPR_NOACCESS, 1639 &spr_read_generic, &spr_write_40x_sler, 1640 0x00000000); 1641 /* not emulated, as QEMU never does speculative access */ 1642 spr_register(env, SPR_40x_SGR, "SGR", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_generic, &spr_write_generic, 1645 0xFFFFFFFF); 1646 /* not emulated, as QEMU do not emulate caches */ 1647 spr_register(env, SPR_40x_DCWR, "DCWR", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 } 1652 1653 static void register_401x2_sprs(CPUPPCState *env) 1654 { 1655 register_401_sprs(env); 1656 spr_register(env, SPR_40x_PID, "PID", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_generic, 1659 0x00000000); 1660 spr_register(env, SPR_40x_ZPR, "ZPR", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_generic, 1663 0x00000000); 1664 } 1665 1666 /* SPR specific to PowerPC 403 implementation */ 1667 static void register_403_sprs(CPUPPCState *env) 1668 { 1669 /* Debug interface */ 1670 /* XXX : not implemented */ 1671 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_40x_dbcr0, 1674 0x00000000); 1675 /* XXX : not implemented */ 1676 spr_register(env, SPR_40x_DBSR, "DBSR", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_clear, 1679 /* Last reset was system reset */ 1680 0x00000300); 1681 /* XXX : not implemented */ 1682 spr_register(env, SPR_40x_DAC1, "DAC1", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 /* XXX : not implemented */ 1687 spr_register(env, SPR_40x_DAC2, "DAC2", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 /* XXX : not implemented */ 1692 spr_register(env, SPR_40x_IAC1, "IAC1", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 /* XXX : not implemented */ 1697 spr_register(env, SPR_40x_IAC2, "IAC2", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 } 1702 1703 static void register_403_real_sprs(CPUPPCState *env) 1704 { 1705 spr_register(env, SPR_403_PBL1, "PBL1", 1706 SPR_NOACCESS, SPR_NOACCESS, 1707 &spr_read_403_pbr, &spr_write_403_pbr, 1708 0x00000000); 1709 spr_register(env, SPR_403_PBU1, "PBU1", 1710 SPR_NOACCESS, SPR_NOACCESS, 1711 &spr_read_403_pbr, &spr_write_403_pbr, 1712 0x00000000); 1713 spr_register(env, SPR_403_PBL2, "PBL2", 1714 SPR_NOACCESS, SPR_NOACCESS, 1715 &spr_read_403_pbr, &spr_write_403_pbr, 1716 0x00000000); 1717 spr_register(env, SPR_403_PBU2, "PBU2", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_403_pbr, &spr_write_403_pbr, 1720 0x00000000); 1721 } 1722 1723 static void register_403_mmu_sprs(CPUPPCState *env) 1724 { 1725 /* MMU */ 1726 spr_register(env, SPR_40x_PID, "PID", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 spr_register(env, SPR_40x_ZPR, "ZPR", 1731 SPR_NOACCESS, SPR_NOACCESS, 1732 &spr_read_generic, &spr_write_generic, 1733 0x00000000); 1734 } 1735 1736 /* SPR specific to PowerPC compression coprocessor extension */ 1737 static void register_compress_sprs(CPUPPCState *env) 1738 { 1739 /* XXX : not implemented */ 1740 spr_register(env, SPR_401_SKR, "SKR", 1741 SPR_NOACCESS, SPR_NOACCESS, 1742 &spr_read_generic, &spr_write_generic, 1743 0x00000000); 1744 } 1745 1746 static void register_5xx_8xx_sprs(CPUPPCState *env) 1747 { 1748 /* Exception processing */ 1749 spr_register_kvm(env, SPR_DSISR, "DSISR", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 KVM_REG_PPC_DSISR, 0x00000000); 1753 spr_register_kvm(env, SPR_DAR, "DAR", 1754 SPR_NOACCESS, SPR_NOACCESS, 1755 &spr_read_generic, &spr_write_generic, 1756 KVM_REG_PPC_DAR, 0x00000000); 1757 /* Timer */ 1758 spr_register(env, SPR_DECR, "DECR", 1759 SPR_NOACCESS, SPR_NOACCESS, 1760 &spr_read_decr, &spr_write_decr, 1761 0x00000000); 1762 /* XXX : not implemented */ 1763 spr_register(env, SPR_MPC_EIE, "EIE", 1764 SPR_NOACCESS, SPR_NOACCESS, 1765 &spr_read_generic, &spr_write_generic, 1766 0x00000000); 1767 /* XXX : not implemented */ 1768 spr_register(env, SPR_MPC_EID, "EID", 1769 SPR_NOACCESS, SPR_NOACCESS, 1770 &spr_read_generic, &spr_write_generic, 1771 0x00000000); 1772 /* XXX : not implemented */ 1773 spr_register(env, SPR_MPC_NRI, "NRI", 1774 SPR_NOACCESS, SPR_NOACCESS, 1775 &spr_read_generic, &spr_write_generic, 1776 0x00000000); 1777 /* XXX : not implemented */ 1778 spr_register(env, SPR_MPC_CMPA, "CMPA", 1779 SPR_NOACCESS, SPR_NOACCESS, 1780 &spr_read_generic, &spr_write_generic, 1781 0x00000000); 1782 /* XXX : not implemented */ 1783 spr_register(env, SPR_MPC_CMPB, "CMPB", 1784 SPR_NOACCESS, SPR_NOACCESS, 1785 &spr_read_generic, &spr_write_generic, 1786 0x00000000); 1787 /* XXX : not implemented */ 1788 spr_register(env, SPR_MPC_CMPC, "CMPC", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 /* XXX : not implemented */ 1793 spr_register(env, SPR_MPC_CMPD, "CMPD", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 /* XXX : not implemented */ 1798 spr_register(env, SPR_MPC_ECR, "ECR", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 /* XXX : not implemented */ 1803 spr_register(env, SPR_MPC_DER, "DER", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 /* XXX : not implemented */ 1808 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 /* XXX : not implemented */ 1813 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 /* XXX : not implemented */ 1818 spr_register(env, SPR_MPC_CMPE, "CMPE", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 /* XXX : not implemented */ 1823 spr_register(env, SPR_MPC_CMPF, "CMPF", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 /* XXX : not implemented */ 1828 spr_register(env, SPR_MPC_CMPG, "CMPG", 1829 SPR_NOACCESS, SPR_NOACCESS, 1830 &spr_read_generic, &spr_write_generic, 1831 0x00000000); 1832 /* XXX : not implemented */ 1833 spr_register(env, SPR_MPC_CMPH, "CMPH", 1834 SPR_NOACCESS, SPR_NOACCESS, 1835 &spr_read_generic, &spr_write_generic, 1836 0x00000000); 1837 /* XXX : not implemented */ 1838 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1839 SPR_NOACCESS, SPR_NOACCESS, 1840 &spr_read_generic, &spr_write_generic, 1841 0x00000000); 1842 /* XXX : not implemented */ 1843 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1844 SPR_NOACCESS, SPR_NOACCESS, 1845 &spr_read_generic, &spr_write_generic, 1846 0x00000000); 1847 /* XXX : not implemented */ 1848 spr_register(env, SPR_MPC_BAR, "BAR", 1849 SPR_NOACCESS, SPR_NOACCESS, 1850 &spr_read_generic, &spr_write_generic, 1851 0x00000000); 1852 /* XXX : not implemented */ 1853 spr_register(env, SPR_MPC_DPDR, "DPDR", 1854 SPR_NOACCESS, SPR_NOACCESS, 1855 &spr_read_generic, &spr_write_generic, 1856 0x00000000); 1857 /* XXX : not implemented */ 1858 spr_register(env, SPR_MPC_IMMR, "IMMR", 1859 SPR_NOACCESS, SPR_NOACCESS, 1860 &spr_read_generic, &spr_write_generic, 1861 0x00000000); 1862 } 1863 1864 static void register_5xx_sprs(CPUPPCState *env) 1865 { 1866 /* XXX : not implemented */ 1867 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1868 SPR_NOACCESS, SPR_NOACCESS, 1869 &spr_read_generic, &spr_write_generic, 1870 0x00000000); 1871 /* XXX : not implemented */ 1872 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1873 SPR_NOACCESS, SPR_NOACCESS, 1874 &spr_read_generic, &spr_write_generic, 1875 0x00000000); 1876 /* XXX : not implemented */ 1877 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1878 SPR_NOACCESS, SPR_NOACCESS, 1879 &spr_read_generic, &spr_write_generic, 1880 0x00000000); 1881 /* XXX : not implemented */ 1882 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1883 SPR_NOACCESS, SPR_NOACCESS, 1884 &spr_read_generic, &spr_write_generic, 1885 0x00000000); 1886 /* XXX : not implemented */ 1887 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1888 SPR_NOACCESS, SPR_NOACCESS, 1889 &spr_read_generic, &spr_write_generic, 1890 0x00000000); 1891 /* XXX : not implemented */ 1892 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1893 SPR_NOACCESS, SPR_NOACCESS, 1894 &spr_read_generic, &spr_write_generic, 1895 0x00000000); 1896 /* XXX : not implemented */ 1897 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1898 SPR_NOACCESS, SPR_NOACCESS, 1899 &spr_read_generic, &spr_write_generic, 1900 0x00000000); 1901 /* XXX : not implemented */ 1902 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1903 SPR_NOACCESS, SPR_NOACCESS, 1904 &spr_read_generic, &spr_write_generic, 1905 0x00000000); 1906 /* XXX : not implemented */ 1907 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1908 SPR_NOACCESS, SPR_NOACCESS, 1909 &spr_read_generic, &spr_write_generic, 1910 0x00000000); 1911 /* XXX : not implemented */ 1912 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1913 SPR_NOACCESS, SPR_NOACCESS, 1914 &spr_read_generic, &spr_write_generic, 1915 0x00000000); 1916 /* XXX : not implemented */ 1917 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1918 SPR_NOACCESS, SPR_NOACCESS, 1919 &spr_read_generic, &spr_write_generic, 1920 0x00000000); 1921 /* XXX : not implemented */ 1922 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1923 SPR_NOACCESS, SPR_NOACCESS, 1924 &spr_read_generic, &spr_write_generic, 1925 0x00000000); 1926 /* XXX : not implemented */ 1927 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1928 SPR_NOACCESS, SPR_NOACCESS, 1929 &spr_read_generic, &spr_write_generic, 1930 0x00000000); 1931 /* XXX : not implemented */ 1932 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1933 SPR_NOACCESS, SPR_NOACCESS, 1934 &spr_read_generic, &spr_write_generic, 1935 0x00000000); 1936 /* XXX : not implemented */ 1937 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1938 SPR_NOACCESS, SPR_NOACCESS, 1939 &spr_read_generic, &spr_write_generic, 1940 0x00000000); 1941 /* XXX : not implemented */ 1942 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1943 SPR_NOACCESS, SPR_NOACCESS, 1944 &spr_read_generic, &spr_write_generic, 1945 0x00000000); 1946 /* XXX : not implemented */ 1947 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1948 SPR_NOACCESS, SPR_NOACCESS, 1949 &spr_read_generic, &spr_write_generic, 1950 0x00000000); 1951 /* XXX : not implemented */ 1952 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1953 SPR_NOACCESS, SPR_NOACCESS, 1954 &spr_read_generic, &spr_write_generic, 1955 0x00000000); 1956 /* XXX : not implemented */ 1957 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1958 SPR_NOACCESS, SPR_NOACCESS, 1959 &spr_read_generic, &spr_write_generic, 1960 0x00000000); 1961 /* XXX : not implemented */ 1962 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1963 SPR_NOACCESS, SPR_NOACCESS, 1964 &spr_read_generic, &spr_write_generic, 1965 0x00000000); 1966 /* XXX : not implemented */ 1967 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1968 SPR_NOACCESS, SPR_NOACCESS, 1969 &spr_read_generic, &spr_write_generic, 1970 0x00000000); 1971 } 1972 1973 static void register_8xx_sprs(CPUPPCState *env) 1974 { 1975 /* XXX : not implemented */ 1976 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1977 SPR_NOACCESS, SPR_NOACCESS, 1978 &spr_read_generic, &spr_write_generic, 1979 0x00000000); 1980 /* XXX : not implemented */ 1981 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1982 SPR_NOACCESS, SPR_NOACCESS, 1983 &spr_read_generic, &spr_write_generic, 1984 0x00000000); 1985 /* XXX : not implemented */ 1986 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1987 SPR_NOACCESS, SPR_NOACCESS, 1988 &spr_read_generic, &spr_write_generic, 1989 0x00000000); 1990 /* XXX : not implemented */ 1991 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1992 SPR_NOACCESS, SPR_NOACCESS, 1993 &spr_read_generic, &spr_write_generic, 1994 0x00000000); 1995 /* XXX : not implemented */ 1996 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1997 SPR_NOACCESS, SPR_NOACCESS, 1998 &spr_read_generic, &spr_write_generic, 1999 0x00000000); 2000 /* XXX : not implemented */ 2001 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 2002 SPR_NOACCESS, SPR_NOACCESS, 2003 &spr_read_generic, &spr_write_generic, 2004 0x00000000); 2005 /* XXX : not implemented */ 2006 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 2007 SPR_NOACCESS, SPR_NOACCESS, 2008 &spr_read_generic, &spr_write_generic, 2009 0x00000000); 2010 /* XXX : not implemented */ 2011 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 2012 SPR_NOACCESS, SPR_NOACCESS, 2013 &spr_read_generic, &spr_write_generic, 2014 0x00000000); 2015 /* XXX : not implemented */ 2016 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 2017 SPR_NOACCESS, SPR_NOACCESS, 2018 &spr_read_generic, &spr_write_generic, 2019 0x00000000); 2020 /* XXX : not implemented */ 2021 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 2022 SPR_NOACCESS, SPR_NOACCESS, 2023 &spr_read_generic, &spr_write_generic, 2024 0x00000000); 2025 /* XXX : not implemented */ 2026 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 2027 SPR_NOACCESS, SPR_NOACCESS, 2028 &spr_read_generic, &spr_write_generic, 2029 0x00000000); 2030 /* XXX : not implemented */ 2031 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 2032 SPR_NOACCESS, SPR_NOACCESS, 2033 &spr_read_generic, &spr_write_generic, 2034 0x00000000); 2035 /* XXX : not implemented */ 2036 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2037 SPR_NOACCESS, SPR_NOACCESS, 2038 &spr_read_generic, &spr_write_generic, 2039 0x00000000); 2040 /* XXX : not implemented */ 2041 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2042 SPR_NOACCESS, SPR_NOACCESS, 2043 &spr_read_generic, &spr_write_generic, 2044 0x00000000); 2045 /* XXX : not implemented */ 2046 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2047 SPR_NOACCESS, SPR_NOACCESS, 2048 &spr_read_generic, &spr_write_generic, 2049 0x00000000); 2050 /* XXX : not implemented */ 2051 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2052 SPR_NOACCESS, SPR_NOACCESS, 2053 &spr_read_generic, &spr_write_generic, 2054 0x00000000); 2055 /* XXX : not implemented */ 2056 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2057 SPR_NOACCESS, SPR_NOACCESS, 2058 &spr_read_generic, &spr_write_generic, 2059 0x00000000); 2060 /* XXX : not implemented */ 2061 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2062 SPR_NOACCESS, SPR_NOACCESS, 2063 &spr_read_generic, &spr_write_generic, 2064 0x00000000); 2065 /* XXX : not implemented */ 2066 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2067 SPR_NOACCESS, SPR_NOACCESS, 2068 &spr_read_generic, &spr_write_generic, 2069 0x00000000); 2070 /* XXX : not implemented */ 2071 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2072 SPR_NOACCESS, SPR_NOACCESS, 2073 &spr_read_generic, &spr_write_generic, 2074 0x00000000); 2075 /* XXX : not implemented */ 2076 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2077 SPR_NOACCESS, SPR_NOACCESS, 2078 &spr_read_generic, &spr_write_generic, 2079 0x00000000); 2080 /* XXX : not implemented */ 2081 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2082 SPR_NOACCESS, SPR_NOACCESS, 2083 &spr_read_generic, &spr_write_generic, 2084 0x00000000); 2085 /* XXX : not implemented */ 2086 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2087 SPR_NOACCESS, SPR_NOACCESS, 2088 &spr_read_generic, &spr_write_generic, 2089 0x00000000); 2090 /* XXX : not implemented */ 2091 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2092 SPR_NOACCESS, SPR_NOACCESS, 2093 &spr_read_generic, &spr_write_generic, 2094 0x00000000); 2095 /* XXX : not implemented */ 2096 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2097 SPR_NOACCESS, SPR_NOACCESS, 2098 &spr_read_generic, &spr_write_generic, 2099 0x00000000); 2100 } 2101 2102 /* 2103 * AMR => SPR 29 (Power 2.04) 2104 * CTRL => SPR 136 (Power 2.04) 2105 * CTRL => SPR 152 (Power 2.04) 2106 * SCOMC => SPR 276 (64 bits ?) 2107 * SCOMD => SPR 277 (64 bits ?) 2108 * TBU40 => SPR 286 (Power 2.04 hypv) 2109 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2110 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2111 * HDSISR => SPR 306 (Power 2.04 hypv) 2112 * HDAR => SPR 307 (Power 2.04 hypv) 2113 * PURR => SPR 309 (Power 2.04 hypv) 2114 * HDEC => SPR 310 (Power 2.04 hypv) 2115 * HIOR => SPR 311 (hypv) 2116 * RMOR => SPR 312 (970) 2117 * HRMOR => SPR 313 (Power 2.04 hypv) 2118 * HSRR0 => SPR 314 (Power 2.04 hypv) 2119 * HSRR1 => SPR 315 (Power 2.04 hypv) 2120 * LPIDR => SPR 317 (970) 2121 * EPR => SPR 702 (Power 2.04 emb) 2122 * perf => 768-783 (Power 2.04) 2123 * perf => 784-799 (Power 2.04) 2124 * PPR => SPR 896 (Power 2.04) 2125 * DABRX => 1015 (Power 2.04 hypv) 2126 * FPECR => SPR 1022 (?) 2127 * ... and more (thermal management, performance counters, ...) 2128 */ 2129 2130 /*****************************************************************************/ 2131 /* Exception vectors models */ 2132 static void init_excp_4xx_real(CPUPPCState *env) 2133 { 2134 #if !defined(CONFIG_USER_ONLY) 2135 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2136 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2137 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2138 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2139 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2140 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2141 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2142 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2143 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2144 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2145 env->ivor_mask = 0x0000FFF0UL; 2146 env->ivpr_mask = 0xFFFF0000UL; 2147 /* Hardware reset vector */ 2148 env->hreset_vector = 0xFFFFFFFCUL; 2149 #endif 2150 } 2151 2152 static void init_excp_4xx_softmmu(CPUPPCState *env) 2153 { 2154 #if !defined(CONFIG_USER_ONLY) 2155 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2158 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2163 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2164 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2165 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2166 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2167 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2168 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2169 env->ivor_mask = 0x0000FFF0UL; 2170 env->ivpr_mask = 0xFFFF0000UL; 2171 /* Hardware reset vector */ 2172 env->hreset_vector = 0xFFFFFFFCUL; 2173 #endif 2174 } 2175 2176 static void init_excp_MPC5xx(CPUPPCState *env) 2177 { 2178 #if !defined(CONFIG_USER_ONLY) 2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2181 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2182 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2183 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2184 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2185 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2186 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2187 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2188 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2189 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2190 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2191 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2192 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2193 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2194 env->ivor_mask = 0x0000FFF0UL; 2195 env->ivpr_mask = 0xFFFF0000UL; 2196 /* Hardware reset vector */ 2197 env->hreset_vector = 0x00000100UL; 2198 #endif 2199 } 2200 2201 static void init_excp_MPC8xx(CPUPPCState *env) 2202 { 2203 #if !defined(CONFIG_USER_ONLY) 2204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2205 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2206 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2207 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2208 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2209 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2210 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2211 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2212 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2213 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2214 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2215 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2216 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2217 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2218 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2219 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2220 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2221 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2222 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2223 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2224 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2225 env->ivor_mask = 0x0000FFF0UL; 2226 env->ivpr_mask = 0xFFFF0000UL; 2227 /* Hardware reset vector */ 2228 env->hreset_vector = 0x00000100UL; 2229 #endif 2230 } 2231 2232 static void init_excp_G2(CPUPPCState *env) 2233 { 2234 #if !defined(CONFIG_USER_ONLY) 2235 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2236 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2237 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2238 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2239 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2240 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2241 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2242 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2243 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2244 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2245 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2246 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2247 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2248 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2249 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2250 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2251 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2252 /* Hardware reset vector */ 2253 env->hreset_vector = 0x00000100UL; 2254 #endif 2255 } 2256 2257 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2258 { 2259 #if !defined(CONFIG_USER_ONLY) 2260 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2261 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2262 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2263 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2264 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2265 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2266 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2267 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2268 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2269 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2270 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2271 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2272 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2273 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2274 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2275 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2276 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2277 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2278 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2279 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2280 env->ivor_mask = 0x0000FFF7UL; 2281 env->ivpr_mask = ivpr_mask; 2282 /* Hardware reset vector */ 2283 env->hreset_vector = 0xFFFFFFFCUL; 2284 #endif 2285 } 2286 2287 static void init_excp_BookE(CPUPPCState *env) 2288 { 2289 #if !defined(CONFIG_USER_ONLY) 2290 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2291 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2292 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2293 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2294 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2295 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2296 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2297 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2298 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2299 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2300 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2301 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2302 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2303 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2304 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2305 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2306 env->ivor_mask = 0x0000FFF0UL; 2307 env->ivpr_mask = 0xFFFF0000UL; 2308 /* Hardware reset vector */ 2309 env->hreset_vector = 0xFFFFFFFCUL; 2310 #endif 2311 } 2312 2313 static void init_excp_601(CPUPPCState *env) 2314 { 2315 #if !defined(CONFIG_USER_ONLY) 2316 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2317 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2318 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2319 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2320 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2321 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2322 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2323 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2324 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2325 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2326 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2327 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2328 /* Hardware reset vector */ 2329 env->hreset_vector = 0x00000100UL; 2330 #endif 2331 } 2332 2333 static void init_excp_602(CPUPPCState *env) 2334 { 2335 #if !defined(CONFIG_USER_ONLY) 2336 /* XXX: exception prefix has a special behavior on 602 */ 2337 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2338 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2339 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2340 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2341 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2342 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2343 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2344 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2345 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2346 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2347 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2348 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2349 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2350 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2351 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2352 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2353 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 2354 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 2355 /* Hardware reset vector */ 2356 env->hreset_vector = 0x00000100UL; 2357 #endif 2358 } 2359 2360 static void init_excp_603(CPUPPCState *env) 2361 { 2362 #if !defined(CONFIG_USER_ONLY) 2363 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2364 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2365 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2366 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2367 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2368 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2369 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2370 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2371 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2372 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2373 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2374 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2375 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2376 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2377 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2378 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2379 /* Hardware reset vector */ 2380 env->hreset_vector = 0x00000100UL; 2381 #endif 2382 } 2383 2384 static void init_excp_604(CPUPPCState *env) 2385 { 2386 #if !defined(CONFIG_USER_ONLY) 2387 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2388 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2389 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2390 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2391 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2392 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2393 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2394 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2395 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2396 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2397 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2398 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2399 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2400 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2401 /* Hardware reset vector */ 2402 env->hreset_vector = 0x00000100UL; 2403 #endif 2404 } 2405 2406 static void init_excp_7x0(CPUPPCState *env) 2407 { 2408 #if !defined(CONFIG_USER_ONLY) 2409 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2410 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2411 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2412 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2413 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2414 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2415 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2416 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2417 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2418 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2419 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2423 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2424 /* Hardware reset vector */ 2425 env->hreset_vector = 0x00000100UL; 2426 #endif 2427 } 2428 2429 static void init_excp_750cl(CPUPPCState *env) 2430 { 2431 #if !defined(CONFIG_USER_ONLY) 2432 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2433 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2434 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2435 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2436 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2437 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2438 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2439 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2440 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2443 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2444 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2445 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2446 /* Hardware reset vector */ 2447 env->hreset_vector = 0x00000100UL; 2448 #endif 2449 } 2450 2451 static void init_excp_750cx(CPUPPCState *env) 2452 { 2453 #if !defined(CONFIG_USER_ONLY) 2454 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2455 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2456 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2457 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2458 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2459 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2460 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2461 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2462 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2463 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2464 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2465 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2466 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2467 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2468 /* Hardware reset vector */ 2469 env->hreset_vector = 0x00000100UL; 2470 #endif 2471 } 2472 2473 /* XXX: Check if this is correct */ 2474 static void init_excp_7x5(CPUPPCState *env) 2475 { 2476 #if !defined(CONFIG_USER_ONLY) 2477 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2478 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2479 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2480 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2481 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2482 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2483 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2484 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2485 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2486 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2487 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2488 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2489 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2490 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2491 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2492 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2493 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2494 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2495 /* Hardware reset vector */ 2496 env->hreset_vector = 0x00000100UL; 2497 #endif 2498 } 2499 2500 static void init_excp_7400(CPUPPCState *env) 2501 { 2502 #if !defined(CONFIG_USER_ONLY) 2503 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2504 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2505 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2506 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2507 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2508 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2509 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2510 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2511 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2512 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2513 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2514 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2515 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2516 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2517 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2518 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2519 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2520 /* Hardware reset vector */ 2521 env->hreset_vector = 0x00000100UL; 2522 #endif 2523 } 2524 2525 static void init_excp_7450(CPUPPCState *env) 2526 { 2527 #if !defined(CONFIG_USER_ONLY) 2528 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2529 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2530 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2531 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2532 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2533 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2534 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2535 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2536 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2537 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2538 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2539 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2540 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2541 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2542 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2543 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2544 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2545 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2546 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2547 /* Hardware reset vector */ 2548 env->hreset_vector = 0x00000100UL; 2549 #endif 2550 } 2551 2552 #if defined(TARGET_PPC64) 2553 static void init_excp_970(CPUPPCState *env) 2554 { 2555 #if !defined(CONFIG_USER_ONLY) 2556 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2557 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2558 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2559 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2560 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2561 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2562 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2563 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2564 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2565 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2566 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2567 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2568 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2569 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2570 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2571 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2572 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2573 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2574 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2575 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2576 /* Hardware reset vector */ 2577 env->hreset_vector = 0x0000000000000100ULL; 2578 #endif 2579 } 2580 2581 static void init_excp_POWER7(CPUPPCState *env) 2582 { 2583 #if !defined(CONFIG_USER_ONLY) 2584 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2585 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2586 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2587 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2588 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2589 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2590 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2591 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2592 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2593 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2594 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2595 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2596 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2597 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2598 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2599 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2600 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2601 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2602 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2603 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2604 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2605 /* Hardware reset vector */ 2606 env->hreset_vector = 0x0000000000000100ULL; 2607 #endif 2608 } 2609 2610 static void init_excp_POWER8(CPUPPCState *env) 2611 { 2612 init_excp_POWER7(env); 2613 2614 #if !defined(CONFIG_USER_ONLY) 2615 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2616 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2617 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2618 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2619 #endif 2620 } 2621 2622 static void init_excp_POWER9(CPUPPCState *env) 2623 { 2624 init_excp_POWER8(env); 2625 2626 #if !defined(CONFIG_USER_ONLY) 2627 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2628 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2629 #endif 2630 } 2631 2632 static void init_excp_POWER10(CPUPPCState *env) 2633 { 2634 init_excp_POWER9(env); 2635 } 2636 2637 #endif 2638 2639 /*****************************************************************************/ 2640 /* Power management enable checks */ 2641 static int check_pow_none(CPUPPCState *env) 2642 { 2643 return 0; 2644 } 2645 2646 static int check_pow_nocheck(CPUPPCState *env) 2647 { 2648 return 1; 2649 } 2650 2651 static int check_pow_hid0(CPUPPCState *env) 2652 { 2653 if (env->spr[SPR_HID0] & 0x00E00000) { 2654 return 1; 2655 } 2656 2657 return 0; 2658 } 2659 2660 static int check_pow_hid0_74xx(CPUPPCState *env) 2661 { 2662 if (env->spr[SPR_HID0] & 0x00600000) { 2663 return 1; 2664 } 2665 2666 return 0; 2667 } 2668 2669 /*****************************************************************************/ 2670 /* PowerPC implementations definitions */ 2671 2672 #define POWERPC_FAMILY(_name) \ 2673 static void \ 2674 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2675 \ 2676 static const TypeInfo \ 2677 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2678 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2679 .parent = TYPE_POWERPC_CPU, \ 2680 .abstract = true, \ 2681 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2682 }; \ 2683 \ 2684 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2685 { \ 2686 type_register_static( \ 2687 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2688 } \ 2689 \ 2690 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2691 \ 2692 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2693 2694 static void init_proc_401(CPUPPCState *env) 2695 { 2696 register_40x_sprs(env); 2697 register_401_403_sprs(env); 2698 register_401_sprs(env); 2699 init_excp_4xx_real(env); 2700 env->dcache_line_size = 32; 2701 env->icache_line_size = 32; 2702 /* Allocate hardware IRQ controller */ 2703 ppc40x_irq_init(env_archcpu(env)); 2704 2705 SET_FIT_PERIOD(12, 16, 20, 24); 2706 SET_WDT_PERIOD(16, 20, 24, 28); 2707 } 2708 2709 POWERPC_FAMILY(401)(ObjectClass *oc, void *data) 2710 { 2711 DeviceClass *dc = DEVICE_CLASS(oc); 2712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2713 2714 dc->desc = "PowerPC 401"; 2715 pcc->init_proc = init_proc_401; 2716 pcc->check_pow = check_pow_nocheck; 2717 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2718 PPC_WRTEE | PPC_DCR | 2719 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2720 PPC_CACHE_DCBZ | 2721 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2722 PPC_4xx_COMMON | PPC_40x_EXCP; 2723 pcc->msr_mask = (1ull << MSR_KEY) | 2724 (1ull << MSR_POW) | 2725 (1ull << MSR_CE) | 2726 (1ull << MSR_ILE) | 2727 (1ull << MSR_EE) | 2728 (1ull << MSR_PR) | 2729 (1ull << MSR_ME) | 2730 (1ull << MSR_DE) | 2731 (1ull << MSR_LE); 2732 pcc->mmu_model = POWERPC_MMU_REAL; 2733 pcc->excp_model = POWERPC_EXCP_40x; 2734 pcc->bus_model = PPC_FLAGS_INPUT_401; 2735 pcc->bfd_mach = bfd_mach_ppc_403; 2736 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2737 POWERPC_FLAG_BUS_CLK; 2738 } 2739 2740 static void init_proc_401x2(CPUPPCState *env) 2741 { 2742 register_40x_sprs(env); 2743 register_401_403_sprs(env); 2744 register_401x2_sprs(env); 2745 register_compress_sprs(env); 2746 /* Memory management */ 2747 #if !defined(CONFIG_USER_ONLY) 2748 env->nb_tlb = 64; 2749 env->nb_ways = 1; 2750 env->id_tlbs = 0; 2751 env->tlb_type = TLB_EMB; 2752 #endif 2753 init_excp_4xx_softmmu(env); 2754 env->dcache_line_size = 32; 2755 env->icache_line_size = 32; 2756 /* Allocate hardware IRQ controller */ 2757 ppc40x_irq_init(env_archcpu(env)); 2758 2759 SET_FIT_PERIOD(12, 16, 20, 24); 2760 SET_WDT_PERIOD(16, 20, 24, 28); 2761 } 2762 2763 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) 2764 { 2765 DeviceClass *dc = DEVICE_CLASS(oc); 2766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2767 2768 dc->desc = "PowerPC 401x2"; 2769 pcc->init_proc = init_proc_401x2; 2770 pcc->check_pow = check_pow_nocheck; 2771 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2772 PPC_DCR | PPC_WRTEE | 2773 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2775 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2776 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2777 PPC_4xx_COMMON | PPC_40x_EXCP; 2778 pcc->msr_mask = (1ull << 20) | 2779 (1ull << MSR_KEY) | 2780 (1ull << MSR_POW) | 2781 (1ull << MSR_CE) | 2782 (1ull << MSR_ILE) | 2783 (1ull << MSR_EE) | 2784 (1ull << MSR_PR) | 2785 (1ull << MSR_ME) | 2786 (1ull << MSR_DE) | 2787 (1ull << MSR_IR) | 2788 (1ull << MSR_DR) | 2789 (1ull << MSR_LE); 2790 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2791 pcc->excp_model = POWERPC_EXCP_40x; 2792 pcc->bus_model = PPC_FLAGS_INPUT_401; 2793 pcc->bfd_mach = bfd_mach_ppc_403; 2794 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2795 POWERPC_FLAG_BUS_CLK; 2796 } 2797 2798 static void init_proc_401x3(CPUPPCState *env) 2799 { 2800 register_40x_sprs(env); 2801 register_401_403_sprs(env); 2802 register_401_sprs(env); 2803 register_401x2_sprs(env); 2804 register_compress_sprs(env); 2805 init_excp_4xx_softmmu(env); 2806 env->dcache_line_size = 32; 2807 env->icache_line_size = 32; 2808 /* Allocate hardware IRQ controller */ 2809 ppc40x_irq_init(env_archcpu(env)); 2810 2811 SET_FIT_PERIOD(12, 16, 20, 24); 2812 SET_WDT_PERIOD(16, 20, 24, 28); 2813 } 2814 2815 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) 2816 { 2817 DeviceClass *dc = DEVICE_CLASS(oc); 2818 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2819 2820 dc->desc = "PowerPC 401x3"; 2821 pcc->init_proc = init_proc_401x3; 2822 pcc->check_pow = check_pow_nocheck; 2823 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2824 PPC_DCR | PPC_WRTEE | 2825 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2826 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2827 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2828 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2829 PPC_4xx_COMMON | PPC_40x_EXCP; 2830 pcc->msr_mask = (1ull << 20) | 2831 (1ull << MSR_KEY) | 2832 (1ull << MSR_POW) | 2833 (1ull << MSR_CE) | 2834 (1ull << MSR_ILE) | 2835 (1ull << MSR_EE) | 2836 (1ull << MSR_PR) | 2837 (1ull << MSR_ME) | 2838 (1ull << MSR_DWE) | 2839 (1ull << MSR_DE) | 2840 (1ull << MSR_IR) | 2841 (1ull << MSR_DR) | 2842 (1ull << MSR_LE); 2843 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2844 pcc->excp_model = POWERPC_EXCP_40x; 2845 pcc->bus_model = PPC_FLAGS_INPUT_401; 2846 pcc->bfd_mach = bfd_mach_ppc_403; 2847 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2848 POWERPC_FLAG_BUS_CLK; 2849 } 2850 2851 static void init_proc_IOP480(CPUPPCState *env) 2852 { 2853 register_40x_sprs(env); 2854 register_401_403_sprs(env); 2855 register_401x2_sprs(env); 2856 register_compress_sprs(env); 2857 /* Memory management */ 2858 #if !defined(CONFIG_USER_ONLY) 2859 env->nb_tlb = 64; 2860 env->nb_ways = 1; 2861 env->id_tlbs = 0; 2862 env->tlb_type = TLB_EMB; 2863 #endif 2864 init_excp_4xx_softmmu(env); 2865 env->dcache_line_size = 32; 2866 env->icache_line_size = 32; 2867 /* Allocate hardware IRQ controller */ 2868 ppc40x_irq_init(env_archcpu(env)); 2869 2870 SET_FIT_PERIOD(8, 12, 16, 20); 2871 SET_WDT_PERIOD(16, 20, 24, 28); 2872 } 2873 2874 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) 2875 { 2876 DeviceClass *dc = DEVICE_CLASS(oc); 2877 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2878 2879 dc->desc = "IOP480"; 2880 pcc->init_proc = init_proc_IOP480; 2881 pcc->check_pow = check_pow_nocheck; 2882 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2883 PPC_DCR | PPC_WRTEE | 2884 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2885 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2886 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2887 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2888 PPC_4xx_COMMON | PPC_40x_EXCP; 2889 pcc->msr_mask = (1ull << 20) | 2890 (1ull << MSR_KEY) | 2891 (1ull << MSR_POW) | 2892 (1ull << MSR_CE) | 2893 (1ull << MSR_ILE) | 2894 (1ull << MSR_EE) | 2895 (1ull << MSR_PR) | 2896 (1ull << MSR_ME) | 2897 (1ull << MSR_DE) | 2898 (1ull << MSR_IR) | 2899 (1ull << MSR_DR) | 2900 (1ull << MSR_LE); 2901 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2902 pcc->excp_model = POWERPC_EXCP_40x; 2903 pcc->bus_model = PPC_FLAGS_INPUT_401; 2904 pcc->bfd_mach = bfd_mach_ppc_403; 2905 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2906 POWERPC_FLAG_BUS_CLK; 2907 } 2908 2909 static void init_proc_403(CPUPPCState *env) 2910 { 2911 register_40x_sprs(env); 2912 register_401_403_sprs(env); 2913 register_403_sprs(env); 2914 register_403_real_sprs(env); 2915 init_excp_4xx_real(env); 2916 env->dcache_line_size = 32; 2917 env->icache_line_size = 32; 2918 /* Allocate hardware IRQ controller */ 2919 ppc40x_irq_init(env_archcpu(env)); 2920 2921 SET_FIT_PERIOD(8, 12, 16, 20); 2922 SET_WDT_PERIOD(16, 20, 24, 28); 2923 } 2924 2925 POWERPC_FAMILY(403)(ObjectClass *oc, void *data) 2926 { 2927 DeviceClass *dc = DEVICE_CLASS(oc); 2928 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2929 2930 dc->desc = "PowerPC 403"; 2931 pcc->init_proc = init_proc_403; 2932 pcc->check_pow = check_pow_nocheck; 2933 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2934 PPC_DCR | PPC_WRTEE | 2935 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2936 PPC_CACHE_DCBZ | 2937 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2938 PPC_4xx_COMMON | PPC_40x_EXCP; 2939 pcc->msr_mask = (1ull << MSR_POW) | 2940 (1ull << MSR_CE) | 2941 (1ull << MSR_ILE) | 2942 (1ull << MSR_EE) | 2943 (1ull << MSR_PR) | 2944 (1ull << MSR_ME) | 2945 (1ull << MSR_PE) | 2946 (1ull << MSR_PX) | 2947 (1ull << MSR_LE); 2948 pcc->mmu_model = POWERPC_MMU_REAL; 2949 pcc->excp_model = POWERPC_EXCP_40x; 2950 pcc->bus_model = PPC_FLAGS_INPUT_401; 2951 pcc->bfd_mach = bfd_mach_ppc_403; 2952 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 2953 POWERPC_FLAG_BUS_CLK; 2954 } 2955 2956 static void init_proc_403GCX(CPUPPCState *env) 2957 { 2958 register_40x_sprs(env); 2959 register_401_403_sprs(env); 2960 register_403_sprs(env); 2961 register_403_real_sprs(env); 2962 register_403_mmu_sprs(env); 2963 /* Bus access control */ 2964 /* not emulated, as QEMU never does speculative access */ 2965 spr_register(env, SPR_40x_SGR, "SGR", 2966 SPR_NOACCESS, SPR_NOACCESS, 2967 &spr_read_generic, &spr_write_generic, 2968 0xFFFFFFFF); 2969 /* not emulated, as QEMU do not emulate caches */ 2970 spr_register(env, SPR_40x_DCWR, "DCWR", 2971 SPR_NOACCESS, SPR_NOACCESS, 2972 &spr_read_generic, &spr_write_generic, 2973 0x00000000); 2974 /* Memory management */ 2975 #if !defined(CONFIG_USER_ONLY) 2976 env->nb_tlb = 64; 2977 env->nb_ways = 1; 2978 env->id_tlbs = 0; 2979 env->tlb_type = TLB_EMB; 2980 #endif 2981 init_excp_4xx_softmmu(env); 2982 env->dcache_line_size = 32; 2983 env->icache_line_size = 32; 2984 /* Allocate hardware IRQ controller */ 2985 ppc40x_irq_init(env_archcpu(env)); 2986 2987 SET_FIT_PERIOD(8, 12, 16, 20); 2988 SET_WDT_PERIOD(16, 20, 24, 28); 2989 } 2990 2991 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) 2992 { 2993 DeviceClass *dc = DEVICE_CLASS(oc); 2994 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2995 2996 dc->desc = "PowerPC 403 GCX"; 2997 pcc->init_proc = init_proc_403GCX; 2998 pcc->check_pow = check_pow_nocheck; 2999 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3000 PPC_DCR | PPC_WRTEE | 3001 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3002 PPC_CACHE_DCBZ | 3003 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3004 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3005 PPC_4xx_COMMON | PPC_40x_EXCP; 3006 pcc->msr_mask = (1ull << MSR_POW) | 3007 (1ull << MSR_CE) | 3008 (1ull << MSR_ILE) | 3009 (1ull << MSR_EE) | 3010 (1ull << MSR_PR) | 3011 (1ull << MSR_ME) | 3012 (1ull << MSR_PE) | 3013 (1ull << MSR_PX) | 3014 (1ull << MSR_LE); 3015 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3016 pcc->excp_model = POWERPC_EXCP_40x; 3017 pcc->bus_model = PPC_FLAGS_INPUT_401; 3018 pcc->bfd_mach = bfd_mach_ppc_403; 3019 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3020 POWERPC_FLAG_BUS_CLK; 3021 } 3022 3023 static void init_proc_405(CPUPPCState *env) 3024 { 3025 /* Time base */ 3026 register_tbl(env); 3027 register_40x_sprs(env); 3028 register_405_sprs(env); 3029 /* Bus access control */ 3030 /* not emulated, as QEMU never does speculative access */ 3031 spr_register(env, SPR_40x_SGR, "SGR", 3032 SPR_NOACCESS, SPR_NOACCESS, 3033 &spr_read_generic, &spr_write_generic, 3034 0xFFFFFFFF); 3035 /* not emulated, as QEMU do not emulate caches */ 3036 spr_register(env, SPR_40x_DCWR, "DCWR", 3037 SPR_NOACCESS, SPR_NOACCESS, 3038 &spr_read_generic, &spr_write_generic, 3039 0x00000000); 3040 /* Memory management */ 3041 #if !defined(CONFIG_USER_ONLY) 3042 env->nb_tlb = 64; 3043 env->nb_ways = 1; 3044 env->id_tlbs = 0; 3045 env->tlb_type = TLB_EMB; 3046 #endif 3047 init_excp_4xx_softmmu(env); 3048 env->dcache_line_size = 32; 3049 env->icache_line_size = 32; 3050 /* Allocate hardware IRQ controller */ 3051 ppc40x_irq_init(env_archcpu(env)); 3052 3053 SET_FIT_PERIOD(8, 12, 16, 20); 3054 SET_WDT_PERIOD(16, 20, 24, 28); 3055 } 3056 3057 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 3058 { 3059 DeviceClass *dc = DEVICE_CLASS(oc); 3060 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3061 3062 dc->desc = "PowerPC 405"; 3063 pcc->init_proc = init_proc_405; 3064 pcc->check_pow = check_pow_nocheck; 3065 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3066 PPC_DCR | PPC_WRTEE | 3067 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3068 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3069 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3070 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3071 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 3072 pcc->msr_mask = (1ull << MSR_POW) | 3073 (1ull << MSR_CE) | 3074 (1ull << MSR_EE) | 3075 (1ull << MSR_PR) | 3076 (1ull << MSR_FP) | 3077 (1ull << MSR_DWE) | 3078 (1ull << MSR_DE) | 3079 (1ull << MSR_IR) | 3080 (1ull << MSR_DR); 3081 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 3082 pcc->excp_model = POWERPC_EXCP_40x; 3083 pcc->bus_model = PPC_FLAGS_INPUT_405; 3084 pcc->bfd_mach = bfd_mach_ppc_403; 3085 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3086 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3087 } 3088 3089 static void init_proc_440EP(CPUPPCState *env) 3090 { 3091 /* Time base */ 3092 register_tbl(env); 3093 register_BookE_sprs(env, 0x000000000000FFFFULL); 3094 register_440_sprs(env); 3095 register_usprgh_sprs(env); 3096 /* Processor identification */ 3097 spr_register(env, SPR_BOOKE_PIR, "PIR", 3098 SPR_NOACCESS, SPR_NOACCESS, 3099 &spr_read_generic, &spr_write_pir, 3100 0x00000000); 3101 /* XXX : not implemented */ 3102 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3103 SPR_NOACCESS, SPR_NOACCESS, 3104 &spr_read_generic, &spr_write_generic, 3105 0x00000000); 3106 /* XXX : not implemented */ 3107 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3108 SPR_NOACCESS, SPR_NOACCESS, 3109 &spr_read_generic, &spr_write_generic, 3110 0x00000000); 3111 /* XXX : not implemented */ 3112 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3113 SPR_NOACCESS, SPR_NOACCESS, 3114 &spr_read_generic, &spr_write_generic, 3115 0x00000000); 3116 /* XXX : not implemented */ 3117 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3118 SPR_NOACCESS, SPR_NOACCESS, 3119 &spr_read_generic, &spr_write_generic, 3120 0x00000000); 3121 /* XXX : not implemented */ 3122 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3123 SPR_NOACCESS, SPR_NOACCESS, 3124 &spr_read_generic, &spr_write_generic, 3125 0x00000000); 3126 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3127 SPR_NOACCESS, SPR_NOACCESS, 3128 &spr_read_generic, &spr_write_generic, 3129 0x00000000); 3130 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3131 SPR_NOACCESS, SPR_NOACCESS, 3132 &spr_read_generic, &spr_write_generic, 3133 0x00000000); 3134 /* XXX : not implemented */ 3135 spr_register(env, SPR_440_CCR1, "CCR1", 3136 SPR_NOACCESS, SPR_NOACCESS, 3137 &spr_read_generic, &spr_write_generic, 3138 0x00000000); 3139 /* Memory management */ 3140 #if !defined(CONFIG_USER_ONLY) 3141 env->nb_tlb = 64; 3142 env->nb_ways = 1; 3143 env->id_tlbs = 0; 3144 env->tlb_type = TLB_EMB; 3145 #endif 3146 init_excp_BookE(env); 3147 env->dcache_line_size = 32; 3148 env->icache_line_size = 32; 3149 ppc40x_irq_init(env_archcpu(env)); 3150 3151 SET_FIT_PERIOD(12, 16, 20, 24); 3152 SET_WDT_PERIOD(20, 24, 28, 32); 3153 } 3154 3155 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 3156 { 3157 DeviceClass *dc = DEVICE_CLASS(oc); 3158 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3159 3160 dc->desc = "PowerPC 440 EP"; 3161 pcc->init_proc = init_proc_440EP; 3162 pcc->check_pow = check_pow_nocheck; 3163 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3164 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3165 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3166 PPC_FLOAT_STFIWX | 3167 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3168 PPC_CACHE | PPC_CACHE_ICBI | 3169 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3170 PPC_MEM_TLBSYNC | PPC_MFTB | 3171 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3172 PPC_440_SPEC; 3173 pcc->msr_mask = (1ull << MSR_POW) | 3174 (1ull << MSR_CE) | 3175 (1ull << MSR_EE) | 3176 (1ull << MSR_PR) | 3177 (1ull << MSR_FP) | 3178 (1ull << MSR_ME) | 3179 (1ull << MSR_FE0) | 3180 (1ull << MSR_DWE) | 3181 (1ull << MSR_DE) | 3182 (1ull << MSR_FE1) | 3183 (1ull << MSR_IR) | 3184 (1ull << MSR_DR); 3185 pcc->mmu_model = POWERPC_MMU_BOOKE; 3186 pcc->excp_model = POWERPC_EXCP_BOOKE; 3187 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3188 pcc->bfd_mach = bfd_mach_ppc_403; 3189 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3190 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3191 } 3192 3193 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 3194 { 3195 DeviceClass *dc = DEVICE_CLASS(oc); 3196 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3197 3198 dc->desc = "PowerPC 460 EX"; 3199 pcc->init_proc = init_proc_440EP; 3200 pcc->check_pow = check_pow_nocheck; 3201 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3202 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3203 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3204 PPC_FLOAT_STFIWX | 3205 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 3206 PPC_CACHE | PPC_CACHE_ICBI | 3207 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3208 PPC_MEM_TLBSYNC | PPC_MFTB | 3209 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3210 PPC_440_SPEC; 3211 pcc->msr_mask = (1ull << MSR_POW) | 3212 (1ull << MSR_CE) | 3213 (1ull << MSR_EE) | 3214 (1ull << MSR_PR) | 3215 (1ull << MSR_FP) | 3216 (1ull << MSR_ME) | 3217 (1ull << MSR_FE0) | 3218 (1ull << MSR_DWE) | 3219 (1ull << MSR_DE) | 3220 (1ull << MSR_FE1) | 3221 (1ull << MSR_IR) | 3222 (1ull << MSR_DR); 3223 pcc->mmu_model = POWERPC_MMU_BOOKE; 3224 pcc->excp_model = POWERPC_EXCP_BOOKE; 3225 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3226 pcc->bfd_mach = bfd_mach_ppc_403; 3227 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3228 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3229 } 3230 3231 static void init_proc_440GP(CPUPPCState *env) 3232 { 3233 /* Time base */ 3234 register_tbl(env); 3235 register_BookE_sprs(env, 0x000000000000FFFFULL); 3236 register_440_sprs(env); 3237 register_usprgh_sprs(env); 3238 /* Processor identification */ 3239 spr_register(env, SPR_BOOKE_PIR, "PIR", 3240 SPR_NOACCESS, SPR_NOACCESS, 3241 &spr_read_generic, &spr_write_pir, 3242 0x00000000); 3243 /* XXX : not implemented */ 3244 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3245 SPR_NOACCESS, SPR_NOACCESS, 3246 &spr_read_generic, &spr_write_generic, 3247 0x00000000); 3248 /* XXX : not implemented */ 3249 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3250 SPR_NOACCESS, SPR_NOACCESS, 3251 &spr_read_generic, &spr_write_generic, 3252 0x00000000); 3253 /* XXX : not implemented */ 3254 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3255 SPR_NOACCESS, SPR_NOACCESS, 3256 &spr_read_generic, &spr_write_generic, 3257 0x00000000); 3258 /* XXX : not implemented */ 3259 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3260 SPR_NOACCESS, SPR_NOACCESS, 3261 &spr_read_generic, &spr_write_generic, 3262 0x00000000); 3263 /* Memory management */ 3264 #if !defined(CONFIG_USER_ONLY) 3265 env->nb_tlb = 64; 3266 env->nb_ways = 1; 3267 env->id_tlbs = 0; 3268 env->tlb_type = TLB_EMB; 3269 #endif 3270 init_excp_BookE(env); 3271 env->dcache_line_size = 32; 3272 env->icache_line_size = 32; 3273 /* XXX: TODO: allocate internal IRQ controller */ 3274 3275 SET_FIT_PERIOD(12, 16, 20, 24); 3276 SET_WDT_PERIOD(20, 24, 28, 32); 3277 } 3278 3279 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 3280 { 3281 DeviceClass *dc = DEVICE_CLASS(oc); 3282 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3283 3284 dc->desc = "PowerPC 440 GP"; 3285 pcc->init_proc = init_proc_440GP; 3286 pcc->check_pow = check_pow_nocheck; 3287 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3288 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 3289 PPC_CACHE | PPC_CACHE_ICBI | 3290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3291 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 3292 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3293 PPC_440_SPEC; 3294 pcc->msr_mask = (1ull << MSR_POW) | 3295 (1ull << MSR_CE) | 3296 (1ull << MSR_EE) | 3297 (1ull << MSR_PR) | 3298 (1ull << MSR_FP) | 3299 (1ull << MSR_ME) | 3300 (1ull << MSR_FE0) | 3301 (1ull << MSR_DWE) | 3302 (1ull << MSR_DE) | 3303 (1ull << MSR_FE1) | 3304 (1ull << MSR_IR) | 3305 (1ull << MSR_DR); 3306 pcc->mmu_model = POWERPC_MMU_BOOKE; 3307 pcc->excp_model = POWERPC_EXCP_BOOKE; 3308 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3309 pcc->bfd_mach = bfd_mach_ppc_403; 3310 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3311 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3312 } 3313 3314 static void init_proc_440x4(CPUPPCState *env) 3315 { 3316 /* Time base */ 3317 register_tbl(env); 3318 register_BookE_sprs(env, 0x000000000000FFFFULL); 3319 register_440_sprs(env); 3320 register_usprgh_sprs(env); 3321 /* Processor identification */ 3322 spr_register(env, SPR_BOOKE_PIR, "PIR", 3323 SPR_NOACCESS, SPR_NOACCESS, 3324 &spr_read_generic, &spr_write_pir, 3325 0x00000000); 3326 /* XXX : not implemented */ 3327 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3328 SPR_NOACCESS, SPR_NOACCESS, 3329 &spr_read_generic, &spr_write_generic, 3330 0x00000000); 3331 /* XXX : not implemented */ 3332 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3333 SPR_NOACCESS, SPR_NOACCESS, 3334 &spr_read_generic, &spr_write_generic, 3335 0x00000000); 3336 /* XXX : not implemented */ 3337 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3338 SPR_NOACCESS, SPR_NOACCESS, 3339 &spr_read_generic, &spr_write_generic, 3340 0x00000000); 3341 /* XXX : not implemented */ 3342 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_generic, 3345 0x00000000); 3346 /* Memory management */ 3347 #if !defined(CONFIG_USER_ONLY) 3348 env->nb_tlb = 64; 3349 env->nb_ways = 1; 3350 env->id_tlbs = 0; 3351 env->tlb_type = TLB_EMB; 3352 #endif 3353 init_excp_BookE(env); 3354 env->dcache_line_size = 32; 3355 env->icache_line_size = 32; 3356 /* XXX: TODO: allocate internal IRQ controller */ 3357 3358 SET_FIT_PERIOD(12, 16, 20, 24); 3359 SET_WDT_PERIOD(20, 24, 28, 32); 3360 } 3361 3362 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 3363 { 3364 DeviceClass *dc = DEVICE_CLASS(oc); 3365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3366 3367 dc->desc = "PowerPC 440x4"; 3368 pcc->init_proc = init_proc_440x4; 3369 pcc->check_pow = check_pow_nocheck; 3370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3371 PPC_DCR | PPC_WRTEE | 3372 PPC_CACHE | PPC_CACHE_ICBI | 3373 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3374 PPC_MEM_TLBSYNC | PPC_MFTB | 3375 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3376 PPC_440_SPEC; 3377 pcc->msr_mask = (1ull << MSR_POW) | 3378 (1ull << MSR_CE) | 3379 (1ull << MSR_EE) | 3380 (1ull << MSR_PR) | 3381 (1ull << MSR_FP) | 3382 (1ull << MSR_ME) | 3383 (1ull << MSR_FE0) | 3384 (1ull << MSR_DWE) | 3385 (1ull << MSR_DE) | 3386 (1ull << MSR_FE1) | 3387 (1ull << MSR_IR) | 3388 (1ull << MSR_DR); 3389 pcc->mmu_model = POWERPC_MMU_BOOKE; 3390 pcc->excp_model = POWERPC_EXCP_BOOKE; 3391 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3392 pcc->bfd_mach = bfd_mach_ppc_403; 3393 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3394 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3395 } 3396 3397 static void init_proc_440x5(CPUPPCState *env) 3398 { 3399 /* Time base */ 3400 register_tbl(env); 3401 register_BookE_sprs(env, 0x000000000000FFFFULL); 3402 register_440_sprs(env); 3403 register_usprgh_sprs(env); 3404 /* Processor identification */ 3405 spr_register(env, SPR_BOOKE_PIR, "PIR", 3406 SPR_NOACCESS, SPR_NOACCESS, 3407 &spr_read_generic, &spr_write_pir, 3408 0x00000000); 3409 /* XXX : not implemented */ 3410 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3411 SPR_NOACCESS, SPR_NOACCESS, 3412 &spr_read_generic, &spr_write_generic, 3413 0x00000000); 3414 /* XXX : not implemented */ 3415 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3416 SPR_NOACCESS, SPR_NOACCESS, 3417 &spr_read_generic, &spr_write_generic, 3418 0x00000000); 3419 /* XXX : not implemented */ 3420 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3421 SPR_NOACCESS, SPR_NOACCESS, 3422 &spr_read_generic, &spr_write_generic, 3423 0x00000000); 3424 /* XXX : not implemented */ 3425 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3426 SPR_NOACCESS, SPR_NOACCESS, 3427 &spr_read_generic, &spr_write_generic, 3428 0x00000000); 3429 /* XXX : not implemented */ 3430 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3431 SPR_NOACCESS, SPR_NOACCESS, 3432 &spr_read_generic, &spr_write_generic, 3433 0x00000000); 3434 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3435 SPR_NOACCESS, SPR_NOACCESS, 3436 &spr_read_generic, &spr_write_generic, 3437 0x00000000); 3438 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3439 SPR_NOACCESS, SPR_NOACCESS, 3440 &spr_read_generic, &spr_write_generic, 3441 0x00000000); 3442 /* XXX : not implemented */ 3443 spr_register(env, SPR_440_CCR1, "CCR1", 3444 SPR_NOACCESS, SPR_NOACCESS, 3445 &spr_read_generic, &spr_write_generic, 3446 0x00000000); 3447 /* Memory management */ 3448 #if !defined(CONFIG_USER_ONLY) 3449 env->nb_tlb = 64; 3450 env->nb_ways = 1; 3451 env->id_tlbs = 0; 3452 env->tlb_type = TLB_EMB; 3453 #endif 3454 init_excp_BookE(env); 3455 env->dcache_line_size = 32; 3456 env->icache_line_size = 32; 3457 ppc40x_irq_init(env_archcpu(env)); 3458 3459 SET_FIT_PERIOD(12, 16, 20, 24); 3460 SET_WDT_PERIOD(20, 24, 28, 32); 3461 } 3462 3463 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 3464 { 3465 DeviceClass *dc = DEVICE_CLASS(oc); 3466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3467 3468 dc->desc = "PowerPC 440x5"; 3469 pcc->init_proc = init_proc_440x5; 3470 pcc->check_pow = check_pow_nocheck; 3471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3472 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3473 PPC_CACHE | PPC_CACHE_ICBI | 3474 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3475 PPC_MEM_TLBSYNC | PPC_MFTB | 3476 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3477 PPC_440_SPEC; 3478 pcc->msr_mask = (1ull << MSR_POW) | 3479 (1ull << MSR_CE) | 3480 (1ull << MSR_EE) | 3481 (1ull << MSR_PR) | 3482 (1ull << MSR_FP) | 3483 (1ull << MSR_ME) | 3484 (1ull << MSR_FE0) | 3485 (1ull << MSR_DWE) | 3486 (1ull << MSR_DE) | 3487 (1ull << MSR_FE1) | 3488 (1ull << MSR_IR) | 3489 (1ull << MSR_DR); 3490 pcc->mmu_model = POWERPC_MMU_BOOKE; 3491 pcc->excp_model = POWERPC_EXCP_BOOKE; 3492 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3493 pcc->bfd_mach = bfd_mach_ppc_403; 3494 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3495 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3496 } 3497 3498 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 3499 { 3500 DeviceClass *dc = DEVICE_CLASS(oc); 3501 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3502 3503 dc->desc = "PowerPC 440x5 with double precision FPU"; 3504 pcc->init_proc = init_proc_440x5; 3505 pcc->check_pow = check_pow_nocheck; 3506 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3507 PPC_FLOAT | PPC_FLOAT_FSQRT | 3508 PPC_FLOAT_STFIWX | 3509 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3510 PPC_CACHE | PPC_CACHE_ICBI | 3511 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3512 PPC_MEM_TLBSYNC | PPC_MFTB | 3513 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3514 PPC_440_SPEC; 3515 pcc->insns_flags2 = PPC2_FP_CVT_S64; 3516 pcc->msr_mask = (1ull << MSR_POW) | 3517 (1ull << MSR_CE) | 3518 (1ull << MSR_EE) | 3519 (1ull << MSR_PR) | 3520 (1ull << MSR_FP) | 3521 (1ull << MSR_ME) | 3522 (1ull << MSR_FE0) | 3523 (1ull << MSR_DWE) | 3524 (1ull << MSR_DE) | 3525 (1ull << MSR_FE1) | 3526 (1ull << MSR_IR) | 3527 (1ull << MSR_DR); 3528 pcc->mmu_model = POWERPC_MMU_BOOKE; 3529 pcc->excp_model = POWERPC_EXCP_BOOKE; 3530 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3531 pcc->bfd_mach = bfd_mach_ppc_403; 3532 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3533 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3534 } 3535 3536 static void init_proc_MPC5xx(CPUPPCState *env) 3537 { 3538 /* Time base */ 3539 register_tbl(env); 3540 register_5xx_8xx_sprs(env); 3541 register_5xx_sprs(env); 3542 init_excp_MPC5xx(env); 3543 env->dcache_line_size = 32; 3544 env->icache_line_size = 32; 3545 /* XXX: TODO: allocate internal IRQ controller */ 3546 } 3547 3548 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 3549 { 3550 DeviceClass *dc = DEVICE_CLASS(oc); 3551 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3552 3553 dc->desc = "Freescale 5xx cores (aka RCPU)"; 3554 pcc->init_proc = init_proc_MPC5xx; 3555 pcc->check_pow = check_pow_none; 3556 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3557 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3558 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 3559 PPC_MFTB; 3560 pcc->msr_mask = (1ull << MSR_ILE) | 3561 (1ull << MSR_EE) | 3562 (1ull << MSR_PR) | 3563 (1ull << MSR_FP) | 3564 (1ull << MSR_ME) | 3565 (1ull << MSR_FE0) | 3566 (1ull << MSR_SE) | 3567 (1ull << MSR_DE) | 3568 (1ull << MSR_FE1) | 3569 (1ull << MSR_EP) | 3570 (1ull << MSR_RI) | 3571 (1ull << MSR_LE); 3572 pcc->mmu_model = POWERPC_MMU_REAL; 3573 pcc->excp_model = POWERPC_EXCP_603; 3574 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3575 pcc->bfd_mach = bfd_mach_ppc_505; 3576 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3577 POWERPC_FLAG_BUS_CLK; 3578 } 3579 3580 static void init_proc_MPC8xx(CPUPPCState *env) 3581 { 3582 /* Time base */ 3583 register_tbl(env); 3584 register_5xx_8xx_sprs(env); 3585 register_8xx_sprs(env); 3586 init_excp_MPC8xx(env); 3587 env->dcache_line_size = 32; 3588 env->icache_line_size = 32; 3589 /* XXX: TODO: allocate internal IRQ controller */ 3590 } 3591 3592 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 3593 { 3594 DeviceClass *dc = DEVICE_CLASS(oc); 3595 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3596 3597 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 3598 pcc->init_proc = init_proc_MPC8xx; 3599 pcc->check_pow = check_pow_none; 3600 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3601 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3602 PPC_CACHE_ICBI | PPC_MFTB; 3603 pcc->msr_mask = (1ull << MSR_ILE) | 3604 (1ull << MSR_EE) | 3605 (1ull << MSR_PR) | 3606 (1ull << MSR_FP) | 3607 (1ull << MSR_ME) | 3608 (1ull << MSR_SE) | 3609 (1ull << MSR_DE) | 3610 (1ull << MSR_EP) | 3611 (1ull << MSR_IR) | 3612 (1ull << MSR_DR) | 3613 (1ull << MSR_RI) | 3614 (1ull << MSR_LE); 3615 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3616 pcc->excp_model = POWERPC_EXCP_603; 3617 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3618 pcc->bfd_mach = bfd_mach_ppc_860; 3619 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3620 POWERPC_FLAG_BUS_CLK; 3621 } 3622 3623 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3624 3625 static void init_proc_G2(CPUPPCState *env) 3626 { 3627 register_ne_601_sprs(env); 3628 register_sdr1_sprs(env); 3629 register_G2_755_sprs(env); 3630 register_G2_sprs(env); 3631 /* Time base */ 3632 register_tbl(env); 3633 /* External access control */ 3634 /* XXX : not implemented */ 3635 spr_register(env, SPR_EAR, "EAR", 3636 SPR_NOACCESS, SPR_NOACCESS, 3637 &spr_read_generic, &spr_write_generic, 3638 0x00000000); 3639 /* Hardware implementation register */ 3640 /* XXX : not implemented */ 3641 spr_register(env, SPR_HID0, "HID0", 3642 SPR_NOACCESS, SPR_NOACCESS, 3643 &spr_read_generic, &spr_write_generic, 3644 0x00000000); 3645 /* XXX : not implemented */ 3646 spr_register(env, SPR_HID1, "HID1", 3647 SPR_NOACCESS, SPR_NOACCESS, 3648 &spr_read_generic, &spr_write_generic, 3649 0x00000000); 3650 /* XXX : not implemented */ 3651 spr_register(env, SPR_HID2, "HID2", 3652 SPR_NOACCESS, SPR_NOACCESS, 3653 &spr_read_generic, &spr_write_generic, 3654 0x00000000); 3655 /* Memory management */ 3656 register_low_BATs(env); 3657 register_high_BATs(env); 3658 register_6xx_7xx_soft_tlb(env, 64, 2); 3659 init_excp_G2(env); 3660 env->dcache_line_size = 32; 3661 env->icache_line_size = 32; 3662 /* Allocate hardware IRQ controller */ 3663 ppc6xx_irq_init(env_archcpu(env)); 3664 } 3665 3666 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3667 { 3668 DeviceClass *dc = DEVICE_CLASS(oc); 3669 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3670 3671 dc->desc = "PowerPC G2"; 3672 pcc->init_proc = init_proc_G2; 3673 pcc->check_pow = check_pow_hid0; 3674 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3675 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3676 PPC_FLOAT_STFIWX | 3677 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3678 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3679 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3680 PPC_SEGMENT | PPC_EXTERN; 3681 pcc->msr_mask = (1ull << MSR_POW) | 3682 (1ull << MSR_TGPR) | 3683 (1ull << MSR_EE) | 3684 (1ull << MSR_PR) | 3685 (1ull << MSR_FP) | 3686 (1ull << MSR_ME) | 3687 (1ull << MSR_FE0) | 3688 (1ull << MSR_SE) | 3689 (1ull << MSR_DE) | 3690 (1ull << MSR_FE1) | 3691 (1ull << MSR_AL) | 3692 (1ull << MSR_EP) | 3693 (1ull << MSR_IR) | 3694 (1ull << MSR_DR) | 3695 (1ull << MSR_RI); 3696 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3697 pcc->excp_model = POWERPC_EXCP_G2; 3698 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3699 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3700 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3701 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3702 } 3703 3704 static void init_proc_G2LE(CPUPPCState *env) 3705 { 3706 register_ne_601_sprs(env); 3707 register_sdr1_sprs(env); 3708 register_G2_755_sprs(env); 3709 register_G2_sprs(env); 3710 /* Time base */ 3711 register_tbl(env); 3712 /* External access control */ 3713 /* XXX : not implemented */ 3714 spr_register(env, SPR_EAR, "EAR", 3715 SPR_NOACCESS, SPR_NOACCESS, 3716 &spr_read_generic, &spr_write_generic, 3717 0x00000000); 3718 /* Hardware implementation register */ 3719 /* XXX : not implemented */ 3720 spr_register(env, SPR_HID0, "HID0", 3721 SPR_NOACCESS, SPR_NOACCESS, 3722 &spr_read_generic, &spr_write_generic, 3723 0x00000000); 3724 /* XXX : not implemented */ 3725 spr_register(env, SPR_HID1, "HID1", 3726 SPR_NOACCESS, SPR_NOACCESS, 3727 &spr_read_generic, &spr_write_generic, 3728 0x00000000); 3729 /* XXX : not implemented */ 3730 spr_register(env, SPR_HID2, "HID2", 3731 SPR_NOACCESS, SPR_NOACCESS, 3732 &spr_read_generic, &spr_write_generic, 3733 0x00000000); 3734 3735 /* Memory management */ 3736 register_low_BATs(env); 3737 register_high_BATs(env); 3738 register_6xx_7xx_soft_tlb(env, 64, 2); 3739 init_excp_G2(env); 3740 env->dcache_line_size = 32; 3741 env->icache_line_size = 32; 3742 /* Allocate hardware IRQ controller */ 3743 ppc6xx_irq_init(env_archcpu(env)); 3744 } 3745 3746 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3747 { 3748 DeviceClass *dc = DEVICE_CLASS(oc); 3749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3750 3751 dc->desc = "PowerPC G2LE"; 3752 pcc->init_proc = init_proc_G2LE; 3753 pcc->check_pow = check_pow_hid0; 3754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3755 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3756 PPC_FLOAT_STFIWX | 3757 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3758 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3759 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3760 PPC_SEGMENT | PPC_EXTERN; 3761 pcc->msr_mask = (1ull << MSR_POW) | 3762 (1ull << MSR_TGPR) | 3763 (1ull << MSR_ILE) | 3764 (1ull << MSR_EE) | 3765 (1ull << MSR_PR) | 3766 (1ull << MSR_FP) | 3767 (1ull << MSR_ME) | 3768 (1ull << MSR_FE0) | 3769 (1ull << MSR_SE) | 3770 (1ull << MSR_DE) | 3771 (1ull << MSR_FE1) | 3772 (1ull << MSR_AL) | 3773 (1ull << MSR_EP) | 3774 (1ull << MSR_IR) | 3775 (1ull << MSR_DR) | 3776 (1ull << MSR_RI) | 3777 (1ull << MSR_LE); 3778 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3779 pcc->excp_model = POWERPC_EXCP_G2; 3780 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3781 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3782 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3783 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3784 } 3785 3786 static void init_proc_e200(CPUPPCState *env) 3787 { 3788 /* Time base */ 3789 register_tbl(env); 3790 register_BookE_sprs(env, 0x000000070000FFFFULL); 3791 /* XXX : not implemented */ 3792 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3793 &spr_read_spefscr, &spr_write_spefscr, 3794 &spr_read_spefscr, &spr_write_spefscr, 3795 0x00000000); 3796 /* Memory management */ 3797 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3798 /* XXX : not implemented */ 3799 spr_register(env, SPR_HID0, "HID0", 3800 SPR_NOACCESS, SPR_NOACCESS, 3801 &spr_read_generic, &spr_write_generic, 3802 0x00000000); 3803 /* XXX : not implemented */ 3804 spr_register(env, SPR_HID1, "HID1", 3805 SPR_NOACCESS, SPR_NOACCESS, 3806 &spr_read_generic, &spr_write_generic, 3807 0x00000000); 3808 /* XXX : not implemented */ 3809 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3810 SPR_NOACCESS, SPR_NOACCESS, 3811 &spr_read_generic, &spr_write_generic, 3812 0x00000000); 3813 /* XXX : not implemented */ 3814 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3815 SPR_NOACCESS, SPR_NOACCESS, 3816 &spr_read_generic, &spr_write_generic, 3817 0x00000000); 3818 /* XXX : not implemented */ 3819 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3820 SPR_NOACCESS, SPR_NOACCESS, 3821 &spr_read_generic, &spr_write_generic, 3822 0x00000000); 3823 /* XXX : not implemented */ 3824 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3825 SPR_NOACCESS, SPR_NOACCESS, 3826 &spr_read_generic, &spr_write_generic, 3827 0x00000000); 3828 /* XXX : not implemented */ 3829 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3830 SPR_NOACCESS, SPR_NOACCESS, 3831 &spr_read_generic, &spr_write_generic, 3832 0x00000000); 3833 /* XXX : not implemented */ 3834 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3835 &spr_read_generic, SPR_NOACCESS, 3836 &spr_read_generic, SPR_NOACCESS, 3837 0x00000000); 3838 /* XXX : not implemented */ 3839 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3840 SPR_NOACCESS, SPR_NOACCESS, 3841 &spr_read_generic, &spr_write_generic, 3842 0x00000000); 3843 /* XXX : not implemented */ 3844 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3845 SPR_NOACCESS, SPR_NOACCESS, 3846 &spr_read_generic, &spr_write_generic, 3847 0x00000000); 3848 /* XXX : not implemented */ 3849 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3850 SPR_NOACCESS, SPR_NOACCESS, 3851 &spr_read_generic, &spr_write_generic, 3852 0x00000000); 3853 /* XXX : not implemented */ 3854 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3855 SPR_NOACCESS, SPR_NOACCESS, 3856 &spr_read_generic, &spr_write_generic, 3857 0x00000000); 3858 /* XXX : not implemented */ 3859 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3860 SPR_NOACCESS, SPR_NOACCESS, 3861 &spr_read_generic, &spr_write_generic, 3862 0x00000000); 3863 /* XXX : not implemented */ 3864 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3865 SPR_NOACCESS, SPR_NOACCESS, 3866 &spr_read_generic, &spr_write_generic, 3867 0x00000000); 3868 /* XXX : not implemented */ 3869 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3870 SPR_NOACCESS, SPR_NOACCESS, 3871 &spr_read_generic, &spr_write_generic, 3872 0x00000000); /* TOFIX */ 3873 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3874 SPR_NOACCESS, SPR_NOACCESS, 3875 &spr_read_generic, &spr_write_generic, 3876 0x00000000); 3877 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3878 SPR_NOACCESS, SPR_NOACCESS, 3879 &spr_read_generic, &spr_write_generic, 3880 0x00000000); 3881 #if !defined(CONFIG_USER_ONLY) 3882 env->nb_tlb = 64; 3883 env->nb_ways = 1; 3884 env->id_tlbs = 0; 3885 env->tlb_type = TLB_EMB; 3886 #endif 3887 init_excp_e200(env, 0xFFFF0000UL); 3888 env->dcache_line_size = 32; 3889 env->icache_line_size = 32; 3890 /* XXX: TODO: allocate internal IRQ controller */ 3891 } 3892 3893 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3894 { 3895 DeviceClass *dc = DEVICE_CLASS(oc); 3896 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3897 3898 dc->desc = "e200 core"; 3899 pcc->init_proc = init_proc_e200; 3900 pcc->check_pow = check_pow_hid0; 3901 /* 3902 * XXX: unimplemented instructions: 3903 * dcblc 3904 * dcbtlst 3905 * dcbtstls 3906 * icblc 3907 * icbtls 3908 * tlbivax 3909 * all SPE multiply-accumulate instructions 3910 */ 3911 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3912 PPC_SPE | PPC_SPE_SINGLE | 3913 PPC_WRTEE | PPC_RFDI | 3914 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3915 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3916 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3917 PPC_BOOKE; 3918 pcc->msr_mask = (1ull << MSR_UCLE) | 3919 (1ull << MSR_SPE) | 3920 (1ull << MSR_POW) | 3921 (1ull << MSR_CE) | 3922 (1ull << MSR_EE) | 3923 (1ull << MSR_PR) | 3924 (1ull << MSR_FP) | 3925 (1ull << MSR_ME) | 3926 (1ull << MSR_FE0) | 3927 (1ull << MSR_DWE) | 3928 (1ull << MSR_DE) | 3929 (1ull << MSR_FE1) | 3930 (1ull << MSR_IR) | 3931 (1ull << MSR_DR); 3932 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3933 pcc->excp_model = POWERPC_EXCP_BOOKE; 3934 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3935 pcc->bfd_mach = bfd_mach_ppc_860; 3936 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3937 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3938 POWERPC_FLAG_BUS_CLK; 3939 } 3940 3941 static void init_proc_e300(CPUPPCState *env) 3942 { 3943 register_ne_601_sprs(env); 3944 register_sdr1_sprs(env); 3945 register_603_sprs(env); 3946 /* Time base */ 3947 register_tbl(env); 3948 /* hardware implementation registers */ 3949 /* XXX : not implemented */ 3950 spr_register(env, SPR_HID0, "HID0", 3951 SPR_NOACCESS, SPR_NOACCESS, 3952 &spr_read_generic, &spr_write_generic, 3953 0x00000000); 3954 /* XXX : not implemented */ 3955 spr_register(env, SPR_HID1, "HID1", 3956 SPR_NOACCESS, SPR_NOACCESS, 3957 &spr_read_generic, &spr_write_generic, 3958 0x00000000); 3959 /* XXX : not implemented */ 3960 spr_register(env, SPR_HID2, "HID2", 3961 SPR_NOACCESS, SPR_NOACCESS, 3962 &spr_read_generic, &spr_write_generic, 3963 0x00000000); 3964 /* Breakpoints */ 3965 /* XXX : not implemented */ 3966 spr_register(env, SPR_DABR, "DABR", 3967 SPR_NOACCESS, SPR_NOACCESS, 3968 &spr_read_generic, &spr_write_generic, 3969 0x00000000); 3970 /* XXX : not implemented */ 3971 spr_register(env, SPR_DABR2, "DABR2", 3972 SPR_NOACCESS, SPR_NOACCESS, 3973 &spr_read_generic, &spr_write_generic, 3974 0x00000000); 3975 /* XXX : not implemented */ 3976 spr_register(env, SPR_IABR2, "IABR2", 3977 SPR_NOACCESS, SPR_NOACCESS, 3978 &spr_read_generic, &spr_write_generic, 3979 0x00000000); 3980 /* XXX : not implemented */ 3981 spr_register(env, SPR_IBCR, "IBCR", 3982 SPR_NOACCESS, SPR_NOACCESS, 3983 &spr_read_generic, &spr_write_generic, 3984 0x00000000); 3985 /* XXX : not implemented */ 3986 spr_register(env, SPR_DBCR, "DBCR", 3987 SPR_NOACCESS, SPR_NOACCESS, 3988 &spr_read_generic, &spr_write_generic, 3989 0x00000000); 3990 /* Memory management */ 3991 register_low_BATs(env); 3992 register_high_BATs(env); 3993 register_6xx_7xx_soft_tlb(env, 64, 2); 3994 init_excp_603(env); 3995 env->dcache_line_size = 32; 3996 env->icache_line_size = 32; 3997 /* Allocate hardware IRQ controller */ 3998 ppc6xx_irq_init(env_archcpu(env)); 3999 } 4000 4001 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 4002 { 4003 DeviceClass *dc = DEVICE_CLASS(oc); 4004 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4005 4006 dc->desc = "e300 core"; 4007 pcc->init_proc = init_proc_e300; 4008 pcc->check_pow = check_pow_hid0; 4009 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4010 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4011 PPC_FLOAT_STFIWX | 4012 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4013 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4014 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4015 PPC_SEGMENT | PPC_EXTERN; 4016 pcc->msr_mask = (1ull << MSR_POW) | 4017 (1ull << MSR_TGPR) | 4018 (1ull << MSR_ILE) | 4019 (1ull << MSR_EE) | 4020 (1ull << MSR_PR) | 4021 (1ull << MSR_FP) | 4022 (1ull << MSR_ME) | 4023 (1ull << MSR_FE0) | 4024 (1ull << MSR_SE) | 4025 (1ull << MSR_DE) | 4026 (1ull << MSR_FE1) | 4027 (1ull << MSR_AL) | 4028 (1ull << MSR_EP) | 4029 (1ull << MSR_IR) | 4030 (1ull << MSR_DR) | 4031 (1ull << MSR_RI) | 4032 (1ull << MSR_LE); 4033 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4034 pcc->excp_model = POWERPC_EXCP_603; 4035 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4036 pcc->bfd_mach = bfd_mach_ppc_603; 4037 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4038 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4039 } 4040 4041 enum fsl_e500_version { 4042 fsl_e500v1, 4043 fsl_e500v2, 4044 fsl_e500mc, 4045 fsl_e5500, 4046 fsl_e6500, 4047 }; 4048 4049 static void init_proc_e500(CPUPPCState *env, int version) 4050 { 4051 uint32_t tlbncfg[2]; 4052 uint64_t ivor_mask; 4053 uint64_t ivpr_mask = 0xFFFF0000ULL; 4054 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 4055 | 0x0020; /* 32 kb */ 4056 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 4057 | 0x0020; /* 32 kb */ 4058 uint32_t mmucfg = 0; 4059 #if !defined(CONFIG_USER_ONLY) 4060 int i; 4061 #endif 4062 4063 /* Time base */ 4064 register_tbl(env); 4065 /* 4066 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 4067 * complain when accessing them. 4068 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 4069 */ 4070 switch (version) { 4071 case fsl_e500v1: 4072 case fsl_e500v2: 4073 default: 4074 ivor_mask = 0x0000000F0000FFFFULL; 4075 break; 4076 case fsl_e500mc: 4077 case fsl_e5500: 4078 ivor_mask = 0x000003FE0000FFFFULL; 4079 break; 4080 case fsl_e6500: 4081 ivor_mask = 0x000003FF0000FFFFULL; 4082 break; 4083 } 4084 register_BookE_sprs(env, ivor_mask); 4085 register_usprg3_sprs(env); 4086 /* Processor identification */ 4087 spr_register(env, SPR_BOOKE_PIR, "PIR", 4088 SPR_NOACCESS, SPR_NOACCESS, 4089 &spr_read_generic, &spr_write_pir, 4090 0x00000000); 4091 /* XXX : not implemented */ 4092 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4093 &spr_read_spefscr, &spr_write_spefscr, 4094 &spr_read_spefscr, &spr_write_spefscr, 4095 0x00000000); 4096 #if !defined(CONFIG_USER_ONLY) 4097 /* Memory management */ 4098 env->nb_pids = 3; 4099 env->nb_ways = 2; 4100 env->id_tlbs = 0; 4101 switch (version) { 4102 case fsl_e500v1: 4103 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 4104 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4105 break; 4106 case fsl_e500v2: 4107 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4108 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4109 break; 4110 case fsl_e500mc: 4111 case fsl_e5500: 4112 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4113 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 4114 break; 4115 case fsl_e6500: 4116 mmucfg = 0x6510B45; 4117 env->nb_pids = 1; 4118 tlbncfg[0] = 0x08052400; 4119 tlbncfg[1] = 0x40028040; 4120 break; 4121 default: 4122 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4123 env->spr[SPR_PVR]); 4124 } 4125 #endif 4126 /* Cache sizes */ 4127 switch (version) { 4128 case fsl_e500v1: 4129 case fsl_e500v2: 4130 env->dcache_line_size = 32; 4131 env->icache_line_size = 32; 4132 break; 4133 case fsl_e500mc: 4134 case fsl_e5500: 4135 env->dcache_line_size = 64; 4136 env->icache_line_size = 64; 4137 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 4138 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 4139 break; 4140 case fsl_e6500: 4141 env->dcache_line_size = 32; 4142 env->icache_line_size = 32; 4143 l1cfg0 |= 0x0F83820; 4144 l1cfg1 |= 0x0B83820; 4145 break; 4146 default: 4147 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4148 env->spr[SPR_PVR]); 4149 } 4150 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 4151 /* XXX : not implemented */ 4152 spr_register(env, SPR_HID0, "HID0", 4153 SPR_NOACCESS, SPR_NOACCESS, 4154 &spr_read_generic, &spr_write_generic, 4155 0x00000000); 4156 /* XXX : not implemented */ 4157 spr_register(env, SPR_HID1, "HID1", 4158 SPR_NOACCESS, SPR_NOACCESS, 4159 &spr_read_generic, &spr_write_generic, 4160 0x00000000); 4161 /* XXX : not implemented */ 4162 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 4163 SPR_NOACCESS, SPR_NOACCESS, 4164 &spr_read_generic, &spr_write_generic, 4165 0x00000000); 4166 /* XXX : not implemented */ 4167 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 4168 SPR_NOACCESS, SPR_NOACCESS, 4169 &spr_read_generic, &spr_write_generic, 4170 0x00000000); 4171 /* XXX : not implemented */ 4172 spr_register(env, SPR_Exxx_MCAR, "MCAR", 4173 SPR_NOACCESS, SPR_NOACCESS, 4174 &spr_read_generic, &spr_write_generic, 4175 0x00000000); 4176 /* XXX : not implemented */ 4177 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 4178 SPR_NOACCESS, SPR_NOACCESS, 4179 &spr_read_generic, &spr_write_generic, 4180 0x00000000); 4181 /* XXX : not implemented */ 4182 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 4183 SPR_NOACCESS, SPR_NOACCESS, 4184 &spr_read_generic, &spr_write_generic, 4185 0x00000000); 4186 /* XXX : not implemented */ 4187 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 4188 SPR_NOACCESS, SPR_NOACCESS, 4189 &spr_read_generic, &spr_write_generic, 4190 0x00000000); 4191 /* XXX : not implemented */ 4192 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 4193 &spr_read_generic, SPR_NOACCESS, 4194 &spr_read_generic, SPR_NOACCESS, 4195 l1cfg0); 4196 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 4197 &spr_read_generic, SPR_NOACCESS, 4198 &spr_read_generic, SPR_NOACCESS, 4199 l1cfg1); 4200 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 4201 SPR_NOACCESS, SPR_NOACCESS, 4202 &spr_read_generic, &spr_write_e500_l1csr0, 4203 0x00000000); 4204 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 4205 SPR_NOACCESS, SPR_NOACCESS, 4206 &spr_read_generic, &spr_write_e500_l1csr1, 4207 0x00000000); 4208 if (version != fsl_e500v1 && version != fsl_e500v2) { 4209 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 4210 SPR_NOACCESS, SPR_NOACCESS, 4211 &spr_read_generic, &spr_write_e500_l2csr0, 4212 0x00000000); 4213 } 4214 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 4215 SPR_NOACCESS, SPR_NOACCESS, 4216 &spr_read_generic, &spr_write_generic, 4217 0x00000000); 4218 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 4219 SPR_NOACCESS, SPR_NOACCESS, 4220 &spr_read_generic, &spr_write_generic, 4221 0x00000000); 4222 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 4223 SPR_NOACCESS, SPR_NOACCESS, 4224 &spr_read_generic, &spr_write_booke206_mmucsr0, 4225 0x00000000); 4226 spr_register(env, SPR_BOOKE_EPR, "EPR", 4227 SPR_NOACCESS, SPR_NOACCESS, 4228 &spr_read_generic, SPR_NOACCESS, 4229 0x00000000); 4230 /* XXX better abstract into Emb.xxx features */ 4231 if ((version == fsl_e5500) || (version == fsl_e6500)) { 4232 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 4233 SPR_NOACCESS, SPR_NOACCESS, 4234 &spr_read_generic, &spr_write_generic, 4235 0x00000000); 4236 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 4237 SPR_NOACCESS, SPR_NOACCESS, 4238 &spr_read_mas73, &spr_write_mas73, 4239 0x00000000); 4240 ivpr_mask = (target_ulong)~0xFFFFULL; 4241 } 4242 4243 if (version == fsl_e6500) { 4244 /* Thread identification */ 4245 spr_register(env, SPR_TIR, "TIR", 4246 SPR_NOACCESS, SPR_NOACCESS, 4247 &spr_read_generic, SPR_NOACCESS, 4248 0x00000000); 4249 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 4250 SPR_NOACCESS, SPR_NOACCESS, 4251 &spr_read_generic, SPR_NOACCESS, 4252 0x00000004); 4253 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 4254 SPR_NOACCESS, SPR_NOACCESS, 4255 &spr_read_generic, SPR_NOACCESS, 4256 0x7FFFFFFC); 4257 } 4258 4259 #if !defined(CONFIG_USER_ONLY) 4260 env->nb_tlb = 0; 4261 env->tlb_type = TLB_MAS; 4262 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 4263 env->nb_tlb += booke206_tlb_size(env, i); 4264 } 4265 #endif 4266 4267 init_excp_e200(env, ivpr_mask); 4268 /* Allocate hardware IRQ controller */ 4269 ppce500_irq_init(env_archcpu(env)); 4270 } 4271 4272 static void init_proc_e500v1(CPUPPCState *env) 4273 { 4274 init_proc_e500(env, fsl_e500v1); 4275 } 4276 4277 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 4278 { 4279 DeviceClass *dc = DEVICE_CLASS(oc); 4280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4281 4282 dc->desc = "e500v1 core"; 4283 pcc->init_proc = init_proc_e500v1; 4284 pcc->check_pow = check_pow_hid0; 4285 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4286 PPC_SPE | PPC_SPE_SINGLE | 4287 PPC_WRTEE | PPC_RFDI | 4288 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4289 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4290 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4291 pcc->insns_flags2 = PPC2_BOOKE206; 4292 pcc->msr_mask = (1ull << MSR_UCLE) | 4293 (1ull << MSR_SPE) | 4294 (1ull << MSR_POW) | 4295 (1ull << MSR_CE) | 4296 (1ull << MSR_EE) | 4297 (1ull << MSR_PR) | 4298 (1ull << MSR_FP) | 4299 (1ull << MSR_ME) | 4300 (1ull << MSR_FE0) | 4301 (1ull << MSR_DWE) | 4302 (1ull << MSR_DE) | 4303 (1ull << MSR_FE1) | 4304 (1ull << MSR_IR) | 4305 (1ull << MSR_DR); 4306 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4307 pcc->excp_model = POWERPC_EXCP_BOOKE; 4308 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4309 pcc->bfd_mach = bfd_mach_ppc_860; 4310 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4311 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4312 POWERPC_FLAG_BUS_CLK; 4313 } 4314 4315 static void init_proc_e500v2(CPUPPCState *env) 4316 { 4317 init_proc_e500(env, fsl_e500v2); 4318 } 4319 4320 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 4321 { 4322 DeviceClass *dc = DEVICE_CLASS(oc); 4323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4324 4325 dc->desc = "e500v2 core"; 4326 pcc->init_proc = init_proc_e500v2; 4327 pcc->check_pow = check_pow_hid0; 4328 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4329 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 4330 PPC_WRTEE | PPC_RFDI | 4331 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4332 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4333 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4334 pcc->insns_flags2 = PPC2_BOOKE206; 4335 pcc->msr_mask = (1ull << MSR_UCLE) | 4336 (1ull << MSR_SPE) | 4337 (1ull << MSR_POW) | 4338 (1ull << MSR_CE) | 4339 (1ull << MSR_EE) | 4340 (1ull << MSR_PR) | 4341 (1ull << MSR_FP) | 4342 (1ull << MSR_ME) | 4343 (1ull << MSR_FE0) | 4344 (1ull << MSR_DWE) | 4345 (1ull << MSR_DE) | 4346 (1ull << MSR_FE1) | 4347 (1ull << MSR_IR) | 4348 (1ull << MSR_DR); 4349 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4350 pcc->excp_model = POWERPC_EXCP_BOOKE; 4351 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4352 pcc->bfd_mach = bfd_mach_ppc_860; 4353 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4354 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4355 POWERPC_FLAG_BUS_CLK; 4356 } 4357 4358 static void init_proc_e500mc(CPUPPCState *env) 4359 { 4360 init_proc_e500(env, fsl_e500mc); 4361 } 4362 4363 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 4364 { 4365 DeviceClass *dc = DEVICE_CLASS(oc); 4366 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4367 4368 dc->desc = "e500mc core"; 4369 pcc->init_proc = init_proc_e500mc; 4370 pcc->check_pow = check_pow_none; 4371 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4372 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4373 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4374 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4375 PPC_FLOAT | PPC_FLOAT_FRES | 4376 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4377 PPC_FLOAT_STFIWX | PPC_WAIT | 4378 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4379 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 4380 pcc->msr_mask = (1ull << MSR_GS) | 4381 (1ull << MSR_UCLE) | 4382 (1ull << MSR_CE) | 4383 (1ull << MSR_EE) | 4384 (1ull << MSR_PR) | 4385 (1ull << MSR_FP) | 4386 (1ull << MSR_ME) | 4387 (1ull << MSR_FE0) | 4388 (1ull << MSR_DE) | 4389 (1ull << MSR_FE1) | 4390 (1ull << MSR_IR) | 4391 (1ull << MSR_DR) | 4392 (1ull << MSR_PX) | 4393 (1ull << MSR_RI); 4394 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4395 pcc->excp_model = POWERPC_EXCP_BOOKE; 4396 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4397 /* FIXME: figure out the correct flag for e500mc */ 4398 pcc->bfd_mach = bfd_mach_ppc_e500; 4399 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4400 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4401 } 4402 4403 #ifdef TARGET_PPC64 4404 static void init_proc_e5500(CPUPPCState *env) 4405 { 4406 init_proc_e500(env, fsl_e5500); 4407 } 4408 4409 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 4410 { 4411 DeviceClass *dc = DEVICE_CLASS(oc); 4412 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4413 4414 dc->desc = "e5500 core"; 4415 pcc->init_proc = init_proc_e5500; 4416 pcc->check_pow = check_pow_none; 4417 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4418 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4419 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4420 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4421 PPC_FLOAT | PPC_FLOAT_FRES | 4422 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4423 PPC_FLOAT_STFIWX | PPC_WAIT | 4424 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4425 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 4426 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4427 PPC2_FP_CVT_S64; 4428 pcc->msr_mask = (1ull << MSR_CM) | 4429 (1ull << MSR_GS) | 4430 (1ull << MSR_UCLE) | 4431 (1ull << MSR_CE) | 4432 (1ull << MSR_EE) | 4433 (1ull << MSR_PR) | 4434 (1ull << MSR_FP) | 4435 (1ull << MSR_ME) | 4436 (1ull << MSR_FE0) | 4437 (1ull << MSR_DE) | 4438 (1ull << MSR_FE1) | 4439 (1ull << MSR_IR) | 4440 (1ull << MSR_DR) | 4441 (1ull << MSR_PX) | 4442 (1ull << MSR_RI); 4443 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4444 pcc->excp_model = POWERPC_EXCP_BOOKE; 4445 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4446 /* FIXME: figure out the correct flag for e5500 */ 4447 pcc->bfd_mach = bfd_mach_ppc_e500; 4448 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4449 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4450 } 4451 4452 static void init_proc_e6500(CPUPPCState *env) 4453 { 4454 init_proc_e500(env, fsl_e6500); 4455 } 4456 4457 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 4458 { 4459 DeviceClass *dc = DEVICE_CLASS(oc); 4460 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4461 4462 dc->desc = "e6500 core"; 4463 pcc->init_proc = init_proc_e6500; 4464 pcc->check_pow = check_pow_none; 4465 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4466 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4467 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4468 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4469 PPC_FLOAT | PPC_FLOAT_FRES | 4470 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4471 PPC_FLOAT_STFIWX | PPC_WAIT | 4472 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4473 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 4474 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4475 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 4476 pcc->msr_mask = (1ull << MSR_CM) | 4477 (1ull << MSR_GS) | 4478 (1ull << MSR_UCLE) | 4479 (1ull << MSR_CE) | 4480 (1ull << MSR_EE) | 4481 (1ull << MSR_PR) | 4482 (1ull << MSR_FP) | 4483 (1ull << MSR_ME) | 4484 (1ull << MSR_FE0) | 4485 (1ull << MSR_DE) | 4486 (1ull << MSR_FE1) | 4487 (1ull << MSR_IS) | 4488 (1ull << MSR_DS) | 4489 (1ull << MSR_PX) | 4490 (1ull << MSR_RI) | 4491 (1ull << MSR_VR); 4492 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4493 pcc->excp_model = POWERPC_EXCP_BOOKE; 4494 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4495 pcc->bfd_mach = bfd_mach_ppc_e500; 4496 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4497 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 4498 } 4499 4500 #endif 4501 4502 /* Non-embedded PowerPC */ 4503 4504 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 4505 4506 static void init_proc_601(CPUPPCState *env) 4507 { 4508 register_ne_601_sprs(env); 4509 register_sdr1_sprs(env); 4510 register_601_sprs(env); 4511 /* Hardware implementation registers */ 4512 /* XXX : not implemented */ 4513 spr_register(env, SPR_HID0, "HID0", 4514 SPR_NOACCESS, SPR_NOACCESS, 4515 &spr_read_generic, &spr_write_hid0_601, 4516 0x80010080); 4517 /* XXX : not implemented */ 4518 spr_register(env, SPR_HID1, "HID1", 4519 SPR_NOACCESS, SPR_NOACCESS, 4520 &spr_read_generic, &spr_write_generic, 4521 0x00000000); 4522 /* XXX : not implemented */ 4523 spr_register(env, SPR_601_HID2, "HID2", 4524 SPR_NOACCESS, SPR_NOACCESS, 4525 &spr_read_generic, &spr_write_generic, 4526 0x00000000); 4527 /* XXX : not implemented */ 4528 spr_register(env, SPR_601_HID5, "HID5", 4529 SPR_NOACCESS, SPR_NOACCESS, 4530 &spr_read_generic, &spr_write_generic, 4531 0x00000000); 4532 /* Memory management */ 4533 init_excp_601(env); 4534 /* 4535 * XXX: beware that dcache line size is 64 4536 * but dcbz uses 32 bytes "sectors" 4537 * XXX: this breaks clcs instruction ! 4538 */ 4539 env->dcache_line_size = 32; 4540 env->icache_line_size = 64; 4541 /* Allocate hardware IRQ controller */ 4542 ppc6xx_irq_init(env_archcpu(env)); 4543 } 4544 4545 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 4546 { 4547 DeviceClass *dc = DEVICE_CLASS(oc); 4548 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4549 4550 dc->desc = "PowerPC 601"; 4551 pcc->init_proc = init_proc_601; 4552 pcc->check_pow = check_pow_none; 4553 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4554 PPC_FLOAT | 4555 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4556 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4557 PPC_SEGMENT | PPC_EXTERN; 4558 pcc->msr_mask = (1ull << MSR_EE) | 4559 (1ull << MSR_PR) | 4560 (1ull << MSR_FP) | 4561 (1ull << MSR_ME) | 4562 (1ull << MSR_FE0) | 4563 (1ull << MSR_SE) | 4564 (1ull << MSR_FE1) | 4565 (1ull << MSR_EP) | 4566 (1ull << MSR_IR) | 4567 (1ull << MSR_DR); 4568 pcc->mmu_model = POWERPC_MMU_601; 4569 #if defined(CONFIG_SOFTMMU) 4570 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4571 #endif 4572 pcc->excp_model = POWERPC_EXCP_601; 4573 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4574 pcc->bfd_mach = bfd_mach_ppc_601; 4575 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4576 } 4577 4578 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 4579 4580 static void init_proc_601v(CPUPPCState *env) 4581 { 4582 init_proc_601(env); 4583 /* XXX : not implemented */ 4584 spr_register(env, SPR_601_HID15, "HID15", 4585 SPR_NOACCESS, SPR_NOACCESS, 4586 &spr_read_generic, &spr_write_generic, 4587 0x00000000); 4588 } 4589 4590 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 4591 { 4592 DeviceClass *dc = DEVICE_CLASS(oc); 4593 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4594 4595 dc->desc = "PowerPC 601v"; 4596 pcc->init_proc = init_proc_601v; 4597 pcc->check_pow = check_pow_none; 4598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4599 PPC_FLOAT | 4600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4601 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4602 PPC_SEGMENT | PPC_EXTERN; 4603 pcc->msr_mask = (1ull << MSR_EE) | 4604 (1ull << MSR_PR) | 4605 (1ull << MSR_FP) | 4606 (1ull << MSR_ME) | 4607 (1ull << MSR_FE0) | 4608 (1ull << MSR_SE) | 4609 (1ull << MSR_FE1) | 4610 (1ull << MSR_EP) | 4611 (1ull << MSR_IR) | 4612 (1ull << MSR_DR); 4613 pcc->mmu_model = POWERPC_MMU_601; 4614 #if defined(CONFIG_SOFTMMU) 4615 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4616 #endif 4617 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4618 pcc->bfd_mach = bfd_mach_ppc_601; 4619 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4620 } 4621 4622 static void init_proc_602(CPUPPCState *env) 4623 { 4624 register_ne_601_sprs(env); 4625 register_sdr1_sprs(env); 4626 register_602_sprs(env); 4627 /* Time base */ 4628 register_tbl(env); 4629 /* hardware implementation registers */ 4630 /* XXX : not implemented */ 4631 spr_register(env, SPR_HID0, "HID0", 4632 SPR_NOACCESS, SPR_NOACCESS, 4633 &spr_read_generic, &spr_write_generic, 4634 0x00000000); 4635 /* XXX : not implemented */ 4636 spr_register(env, SPR_HID1, "HID1", 4637 SPR_NOACCESS, SPR_NOACCESS, 4638 &spr_read_generic, &spr_write_generic, 4639 0x00000000); 4640 /* Memory management */ 4641 register_low_BATs(env); 4642 register_6xx_7xx_soft_tlb(env, 64, 2); 4643 init_excp_602(env); 4644 env->dcache_line_size = 32; 4645 env->icache_line_size = 32; 4646 /* Allocate hardware IRQ controller */ 4647 ppc6xx_irq_init(env_archcpu(env)); 4648 } 4649 4650 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 4651 { 4652 DeviceClass *dc = DEVICE_CLASS(oc); 4653 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4654 4655 dc->desc = "PowerPC 602"; 4656 pcc->init_proc = init_proc_602; 4657 pcc->check_pow = check_pow_hid0; 4658 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4659 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4660 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4661 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4662 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4663 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 4664 PPC_SEGMENT | PPC_602_SPEC; 4665 pcc->msr_mask = (1ull << MSR_VSX) | 4666 (1ull << MSR_SA) | 4667 (1ull << MSR_POW) | 4668 (1ull << MSR_TGPR) | 4669 (1ull << MSR_ILE) | 4670 (1ull << MSR_EE) | 4671 (1ull << MSR_PR) | 4672 (1ull << MSR_FP) | 4673 (1ull << MSR_ME) | 4674 (1ull << MSR_FE0) | 4675 (1ull << MSR_SE) | 4676 (1ull << MSR_DE) | 4677 (1ull << MSR_FE1) | 4678 (1ull << MSR_EP) | 4679 (1ull << MSR_IR) | 4680 (1ull << MSR_DR) | 4681 (1ull << MSR_RI) | 4682 (1ull << MSR_LE); 4683 /* XXX: 602 MMU is quite specific. Should add a special case */ 4684 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4685 pcc->excp_model = POWERPC_EXCP_602; 4686 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4687 pcc->bfd_mach = bfd_mach_ppc_602; 4688 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4689 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4690 } 4691 4692 static void init_proc_603(CPUPPCState *env) 4693 { 4694 register_ne_601_sprs(env); 4695 register_sdr1_sprs(env); 4696 register_603_sprs(env); 4697 /* Time base */ 4698 register_tbl(env); 4699 /* hardware implementation registers */ 4700 /* XXX : not implemented */ 4701 spr_register(env, SPR_HID0, "HID0", 4702 SPR_NOACCESS, SPR_NOACCESS, 4703 &spr_read_generic, &spr_write_generic, 4704 0x00000000); 4705 /* XXX : not implemented */ 4706 spr_register(env, SPR_HID1, "HID1", 4707 SPR_NOACCESS, SPR_NOACCESS, 4708 &spr_read_generic, &spr_write_generic, 4709 0x00000000); 4710 /* Memory management */ 4711 register_low_BATs(env); 4712 register_6xx_7xx_soft_tlb(env, 64, 2); 4713 init_excp_603(env); 4714 env->dcache_line_size = 32; 4715 env->icache_line_size = 32; 4716 /* Allocate hardware IRQ controller */ 4717 ppc6xx_irq_init(env_archcpu(env)); 4718 } 4719 4720 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4721 { 4722 DeviceClass *dc = DEVICE_CLASS(oc); 4723 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4724 4725 dc->desc = "PowerPC 603"; 4726 pcc->init_proc = init_proc_603; 4727 pcc->check_pow = check_pow_hid0; 4728 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4729 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4730 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4731 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4732 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4733 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4734 PPC_SEGMENT | PPC_EXTERN; 4735 pcc->msr_mask = (1ull << MSR_POW) | 4736 (1ull << MSR_TGPR) | 4737 (1ull << MSR_ILE) | 4738 (1ull << MSR_EE) | 4739 (1ull << MSR_PR) | 4740 (1ull << MSR_FP) | 4741 (1ull << MSR_ME) | 4742 (1ull << MSR_FE0) | 4743 (1ull << MSR_SE) | 4744 (1ull << MSR_DE) | 4745 (1ull << MSR_FE1) | 4746 (1ull << MSR_EP) | 4747 (1ull << MSR_IR) | 4748 (1ull << MSR_DR) | 4749 (1ull << MSR_RI) | 4750 (1ull << MSR_LE); 4751 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4752 pcc->excp_model = POWERPC_EXCP_603; 4753 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4754 pcc->bfd_mach = bfd_mach_ppc_603; 4755 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4756 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4757 } 4758 4759 static void init_proc_603E(CPUPPCState *env) 4760 { 4761 register_ne_601_sprs(env); 4762 register_sdr1_sprs(env); 4763 register_603_sprs(env); 4764 /* Time base */ 4765 register_tbl(env); 4766 /* hardware implementation registers */ 4767 /* XXX : not implemented */ 4768 spr_register(env, SPR_HID0, "HID0", 4769 SPR_NOACCESS, SPR_NOACCESS, 4770 &spr_read_generic, &spr_write_generic, 4771 0x00000000); 4772 /* XXX : not implemented */ 4773 spr_register(env, SPR_HID1, "HID1", 4774 SPR_NOACCESS, SPR_NOACCESS, 4775 &spr_read_generic, &spr_write_generic, 4776 0x00000000); 4777 /* Memory management */ 4778 register_low_BATs(env); 4779 register_6xx_7xx_soft_tlb(env, 64, 2); 4780 init_excp_603(env); 4781 env->dcache_line_size = 32; 4782 env->icache_line_size = 32; 4783 /* Allocate hardware IRQ controller */ 4784 ppc6xx_irq_init(env_archcpu(env)); 4785 } 4786 4787 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4788 { 4789 DeviceClass *dc = DEVICE_CLASS(oc); 4790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4791 4792 dc->desc = "PowerPC 603e"; 4793 pcc->init_proc = init_proc_603E; 4794 pcc->check_pow = check_pow_hid0; 4795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4796 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4797 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4798 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4799 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4801 PPC_SEGMENT | PPC_EXTERN; 4802 pcc->msr_mask = (1ull << MSR_POW) | 4803 (1ull << MSR_TGPR) | 4804 (1ull << MSR_ILE) | 4805 (1ull << MSR_EE) | 4806 (1ull << MSR_PR) | 4807 (1ull << MSR_FP) | 4808 (1ull << MSR_ME) | 4809 (1ull << MSR_FE0) | 4810 (1ull << MSR_SE) | 4811 (1ull << MSR_DE) | 4812 (1ull << MSR_FE1) | 4813 (1ull << MSR_EP) | 4814 (1ull << MSR_IR) | 4815 (1ull << MSR_DR) | 4816 (1ull << MSR_RI) | 4817 (1ull << MSR_LE); 4818 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4819 pcc->excp_model = POWERPC_EXCP_603E; 4820 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4821 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4822 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4823 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4824 } 4825 4826 static void init_proc_604(CPUPPCState *env) 4827 { 4828 register_ne_601_sprs(env); 4829 register_sdr1_sprs(env); 4830 register_604_sprs(env); 4831 /* Time base */ 4832 register_tbl(env); 4833 /* Hardware implementation registers */ 4834 /* XXX : not implemented */ 4835 spr_register(env, SPR_HID0, "HID0", 4836 SPR_NOACCESS, SPR_NOACCESS, 4837 &spr_read_generic, &spr_write_generic, 4838 0x00000000); 4839 /* Memory management */ 4840 register_low_BATs(env); 4841 init_excp_604(env); 4842 env->dcache_line_size = 32; 4843 env->icache_line_size = 32; 4844 /* Allocate hardware IRQ controller */ 4845 ppc6xx_irq_init(env_archcpu(env)); 4846 } 4847 4848 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4849 { 4850 DeviceClass *dc = DEVICE_CLASS(oc); 4851 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4852 4853 dc->desc = "PowerPC 604"; 4854 pcc->init_proc = init_proc_604; 4855 pcc->check_pow = check_pow_nocheck; 4856 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4857 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4858 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4859 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4860 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4861 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4862 PPC_SEGMENT | PPC_EXTERN; 4863 pcc->msr_mask = (1ull << MSR_POW) | 4864 (1ull << MSR_ILE) | 4865 (1ull << MSR_EE) | 4866 (1ull << MSR_PR) | 4867 (1ull << MSR_FP) | 4868 (1ull << MSR_ME) | 4869 (1ull << MSR_FE0) | 4870 (1ull << MSR_SE) | 4871 (1ull << MSR_DE) | 4872 (1ull << MSR_FE1) | 4873 (1ull << MSR_EP) | 4874 (1ull << MSR_IR) | 4875 (1ull << MSR_DR) | 4876 (1ull << MSR_PMM) | 4877 (1ull << MSR_RI) | 4878 (1ull << MSR_LE); 4879 pcc->mmu_model = POWERPC_MMU_32B; 4880 #if defined(CONFIG_SOFTMMU) 4881 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4882 #endif 4883 pcc->excp_model = POWERPC_EXCP_604; 4884 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4885 pcc->bfd_mach = bfd_mach_ppc_604; 4886 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4887 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4888 } 4889 4890 static void init_proc_604E(CPUPPCState *env) 4891 { 4892 register_ne_601_sprs(env); 4893 register_sdr1_sprs(env); 4894 register_604_sprs(env); 4895 /* XXX : not implemented */ 4896 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4897 SPR_NOACCESS, SPR_NOACCESS, 4898 &spr_read_generic, &spr_write_generic, 4899 0x00000000); 4900 /* XXX : not implemented */ 4901 spr_register(env, SPR_7XX_PMC3, "PMC3", 4902 SPR_NOACCESS, SPR_NOACCESS, 4903 &spr_read_generic, &spr_write_generic, 4904 0x00000000); 4905 /* XXX : not implemented */ 4906 spr_register(env, SPR_7XX_PMC4, "PMC4", 4907 SPR_NOACCESS, SPR_NOACCESS, 4908 &spr_read_generic, &spr_write_generic, 4909 0x00000000); 4910 /* Time base */ 4911 register_tbl(env); 4912 /* Hardware implementation registers */ 4913 /* XXX : not implemented */ 4914 spr_register(env, SPR_HID0, "HID0", 4915 SPR_NOACCESS, SPR_NOACCESS, 4916 &spr_read_generic, &spr_write_generic, 4917 0x00000000); 4918 /* XXX : not implemented */ 4919 spr_register(env, SPR_HID1, "HID1", 4920 SPR_NOACCESS, SPR_NOACCESS, 4921 &spr_read_generic, &spr_write_generic, 4922 0x00000000); 4923 /* Memory management */ 4924 register_low_BATs(env); 4925 init_excp_604(env); 4926 env->dcache_line_size = 32; 4927 env->icache_line_size = 32; 4928 /* Allocate hardware IRQ controller */ 4929 ppc6xx_irq_init(env_archcpu(env)); 4930 } 4931 4932 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4933 { 4934 DeviceClass *dc = DEVICE_CLASS(oc); 4935 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4936 4937 dc->desc = "PowerPC 604E"; 4938 pcc->init_proc = init_proc_604E; 4939 pcc->check_pow = check_pow_nocheck; 4940 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4941 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4942 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4943 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4944 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4945 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4946 PPC_SEGMENT | PPC_EXTERN; 4947 pcc->msr_mask = (1ull << MSR_POW) | 4948 (1ull << MSR_ILE) | 4949 (1ull << MSR_EE) | 4950 (1ull << MSR_PR) | 4951 (1ull << MSR_FP) | 4952 (1ull << MSR_ME) | 4953 (1ull << MSR_FE0) | 4954 (1ull << MSR_SE) | 4955 (1ull << MSR_DE) | 4956 (1ull << MSR_FE1) | 4957 (1ull << MSR_EP) | 4958 (1ull << MSR_IR) | 4959 (1ull << MSR_DR) | 4960 (1ull << MSR_PMM) | 4961 (1ull << MSR_RI) | 4962 (1ull << MSR_LE); 4963 pcc->mmu_model = POWERPC_MMU_32B; 4964 #if defined(CONFIG_SOFTMMU) 4965 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4966 #endif 4967 pcc->excp_model = POWERPC_EXCP_604; 4968 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4969 pcc->bfd_mach = bfd_mach_ppc_604; 4970 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4971 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4972 } 4973 4974 static void init_proc_740(CPUPPCState *env) 4975 { 4976 register_ne_601_sprs(env); 4977 register_sdr1_sprs(env); 4978 register_7xx_sprs(env); 4979 /* Time base */ 4980 register_tbl(env); 4981 /* Thermal management */ 4982 register_thrm_sprs(env); 4983 /* Hardware implementation registers */ 4984 /* XXX : not implemented */ 4985 spr_register(env, SPR_HID0, "HID0", 4986 SPR_NOACCESS, SPR_NOACCESS, 4987 &spr_read_generic, &spr_write_generic, 4988 0x00000000); 4989 /* XXX : not implemented */ 4990 spr_register(env, SPR_HID1, "HID1", 4991 SPR_NOACCESS, SPR_NOACCESS, 4992 &spr_read_generic, &spr_write_generic, 4993 0x00000000); 4994 /* Memory management */ 4995 register_low_BATs(env); 4996 init_excp_7x0(env); 4997 env->dcache_line_size = 32; 4998 env->icache_line_size = 32; 4999 /* Allocate hardware IRQ controller */ 5000 ppc6xx_irq_init(env_archcpu(env)); 5001 } 5002 5003 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 5004 { 5005 DeviceClass *dc = DEVICE_CLASS(oc); 5006 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5007 5008 dc->desc = "PowerPC 740"; 5009 pcc->init_proc = init_proc_740; 5010 pcc->check_pow = check_pow_hid0; 5011 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5012 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5013 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5014 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5015 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5016 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5017 PPC_SEGMENT | PPC_EXTERN; 5018 pcc->msr_mask = (1ull << MSR_POW) | 5019 (1ull << MSR_ILE) | 5020 (1ull << MSR_EE) | 5021 (1ull << MSR_PR) | 5022 (1ull << MSR_FP) | 5023 (1ull << MSR_ME) | 5024 (1ull << MSR_FE0) | 5025 (1ull << MSR_SE) | 5026 (1ull << MSR_DE) | 5027 (1ull << MSR_FE1) | 5028 (1ull << MSR_EP) | 5029 (1ull << MSR_IR) | 5030 (1ull << MSR_DR) | 5031 (1ull << MSR_PMM) | 5032 (1ull << MSR_RI) | 5033 (1ull << MSR_LE); 5034 pcc->mmu_model = POWERPC_MMU_32B; 5035 #if defined(CONFIG_SOFTMMU) 5036 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5037 #endif 5038 pcc->excp_model = POWERPC_EXCP_7x0; 5039 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5040 pcc->bfd_mach = bfd_mach_ppc_750; 5041 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5042 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5043 } 5044 5045 static void init_proc_750(CPUPPCState *env) 5046 { 5047 register_ne_601_sprs(env); 5048 register_sdr1_sprs(env); 5049 register_7xx_sprs(env); 5050 /* XXX : not implemented */ 5051 spr_register(env, SPR_L2CR, "L2CR", 5052 SPR_NOACCESS, SPR_NOACCESS, 5053 &spr_read_generic, spr_access_nop, 5054 0x00000000); 5055 /* Time base */ 5056 register_tbl(env); 5057 /* Thermal management */ 5058 register_thrm_sprs(env); 5059 /* Hardware implementation registers */ 5060 /* XXX : not implemented */ 5061 spr_register(env, SPR_HID0, "HID0", 5062 SPR_NOACCESS, SPR_NOACCESS, 5063 &spr_read_generic, &spr_write_generic, 5064 0x00000000); 5065 /* XXX : not implemented */ 5066 spr_register(env, SPR_HID1, "HID1", 5067 SPR_NOACCESS, SPR_NOACCESS, 5068 &spr_read_generic, &spr_write_generic, 5069 0x00000000); 5070 /* Memory management */ 5071 register_low_BATs(env); 5072 /* 5073 * XXX: high BATs are also present but are known to be bugged on 5074 * die version 1.x 5075 */ 5076 init_excp_7x0(env); 5077 env->dcache_line_size = 32; 5078 env->icache_line_size = 32; 5079 /* Allocate hardware IRQ controller */ 5080 ppc6xx_irq_init(env_archcpu(env)); 5081 } 5082 5083 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 5084 { 5085 DeviceClass *dc = DEVICE_CLASS(oc); 5086 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5087 5088 dc->desc = "PowerPC 750"; 5089 pcc->init_proc = init_proc_750; 5090 pcc->check_pow = check_pow_hid0; 5091 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5092 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5093 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5094 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5095 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5096 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5097 PPC_SEGMENT | PPC_EXTERN; 5098 pcc->msr_mask = (1ull << MSR_POW) | 5099 (1ull << MSR_ILE) | 5100 (1ull << MSR_EE) | 5101 (1ull << MSR_PR) | 5102 (1ull << MSR_FP) | 5103 (1ull << MSR_ME) | 5104 (1ull << MSR_FE0) | 5105 (1ull << MSR_SE) | 5106 (1ull << MSR_DE) | 5107 (1ull << MSR_FE1) | 5108 (1ull << MSR_EP) | 5109 (1ull << MSR_IR) | 5110 (1ull << MSR_DR) | 5111 (1ull << MSR_PMM) | 5112 (1ull << MSR_RI) | 5113 (1ull << MSR_LE); 5114 pcc->mmu_model = POWERPC_MMU_32B; 5115 #if defined(CONFIG_SOFTMMU) 5116 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5117 #endif 5118 pcc->excp_model = POWERPC_EXCP_7x0; 5119 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5120 pcc->bfd_mach = bfd_mach_ppc_750; 5121 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5122 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5123 } 5124 5125 static void init_proc_750cl(CPUPPCState *env) 5126 { 5127 register_ne_601_sprs(env); 5128 register_sdr1_sprs(env); 5129 register_7xx_sprs(env); 5130 /* XXX : not implemented */ 5131 spr_register(env, SPR_L2CR, "L2CR", 5132 SPR_NOACCESS, SPR_NOACCESS, 5133 &spr_read_generic, spr_access_nop, 5134 0x00000000); 5135 /* Time base */ 5136 register_tbl(env); 5137 /* Thermal management */ 5138 /* Those registers are fake on 750CL */ 5139 spr_register(env, SPR_THRM1, "THRM1", 5140 SPR_NOACCESS, SPR_NOACCESS, 5141 &spr_read_generic, &spr_write_generic, 5142 0x00000000); 5143 spr_register(env, SPR_THRM2, "THRM2", 5144 SPR_NOACCESS, SPR_NOACCESS, 5145 &spr_read_generic, &spr_write_generic, 5146 0x00000000); 5147 spr_register(env, SPR_THRM3, "THRM3", 5148 SPR_NOACCESS, SPR_NOACCESS, 5149 &spr_read_generic, &spr_write_generic, 5150 0x00000000); 5151 /* XXX: not implemented */ 5152 spr_register(env, SPR_750_TDCL, "TDCL", 5153 SPR_NOACCESS, SPR_NOACCESS, 5154 &spr_read_generic, &spr_write_generic, 5155 0x00000000); 5156 spr_register(env, SPR_750_TDCH, "TDCH", 5157 SPR_NOACCESS, SPR_NOACCESS, 5158 &spr_read_generic, &spr_write_generic, 5159 0x00000000); 5160 /* DMA */ 5161 /* XXX : not implemented */ 5162 spr_register(env, SPR_750_WPAR, "WPAR", 5163 SPR_NOACCESS, SPR_NOACCESS, 5164 &spr_read_generic, &spr_write_generic, 5165 0x00000000); 5166 spr_register(env, SPR_750_DMAL, "DMAL", 5167 SPR_NOACCESS, SPR_NOACCESS, 5168 &spr_read_generic, &spr_write_generic, 5169 0x00000000); 5170 spr_register(env, SPR_750_DMAU, "DMAU", 5171 SPR_NOACCESS, SPR_NOACCESS, 5172 &spr_read_generic, &spr_write_generic, 5173 0x00000000); 5174 /* Hardware implementation registers */ 5175 /* XXX : not implemented */ 5176 spr_register(env, SPR_HID0, "HID0", 5177 SPR_NOACCESS, SPR_NOACCESS, 5178 &spr_read_generic, &spr_write_generic, 5179 0x00000000); 5180 /* XXX : not implemented */ 5181 spr_register(env, SPR_HID1, "HID1", 5182 SPR_NOACCESS, SPR_NOACCESS, 5183 &spr_read_generic, &spr_write_generic, 5184 0x00000000); 5185 /* XXX : not implemented */ 5186 spr_register(env, SPR_750CL_HID2, "HID2", 5187 SPR_NOACCESS, SPR_NOACCESS, 5188 &spr_read_generic, &spr_write_generic, 5189 0x00000000); 5190 /* XXX : not implemented */ 5191 spr_register(env, SPR_750CL_HID4, "HID4", 5192 SPR_NOACCESS, SPR_NOACCESS, 5193 &spr_read_generic, &spr_write_generic, 5194 0x00000000); 5195 /* Quantization registers */ 5196 /* XXX : not implemented */ 5197 spr_register(env, SPR_750_GQR0, "GQR0", 5198 SPR_NOACCESS, SPR_NOACCESS, 5199 &spr_read_generic, &spr_write_generic, 5200 0x00000000); 5201 /* XXX : not implemented */ 5202 spr_register(env, SPR_750_GQR1, "GQR1", 5203 SPR_NOACCESS, SPR_NOACCESS, 5204 &spr_read_generic, &spr_write_generic, 5205 0x00000000); 5206 /* XXX : not implemented */ 5207 spr_register(env, SPR_750_GQR2, "GQR2", 5208 SPR_NOACCESS, SPR_NOACCESS, 5209 &spr_read_generic, &spr_write_generic, 5210 0x00000000); 5211 /* XXX : not implemented */ 5212 spr_register(env, SPR_750_GQR3, "GQR3", 5213 SPR_NOACCESS, SPR_NOACCESS, 5214 &spr_read_generic, &spr_write_generic, 5215 0x00000000); 5216 /* XXX : not implemented */ 5217 spr_register(env, SPR_750_GQR4, "GQR4", 5218 SPR_NOACCESS, SPR_NOACCESS, 5219 &spr_read_generic, &spr_write_generic, 5220 0x00000000); 5221 /* XXX : not implemented */ 5222 spr_register(env, SPR_750_GQR5, "GQR5", 5223 SPR_NOACCESS, SPR_NOACCESS, 5224 &spr_read_generic, &spr_write_generic, 5225 0x00000000); 5226 /* XXX : not implemented */ 5227 spr_register(env, SPR_750_GQR6, "GQR6", 5228 SPR_NOACCESS, SPR_NOACCESS, 5229 &spr_read_generic, &spr_write_generic, 5230 0x00000000); 5231 /* XXX : not implemented */ 5232 spr_register(env, SPR_750_GQR7, "GQR7", 5233 SPR_NOACCESS, SPR_NOACCESS, 5234 &spr_read_generic, &spr_write_generic, 5235 0x00000000); 5236 /* Memory management */ 5237 register_low_BATs(env); 5238 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 5239 register_high_BATs(env); 5240 init_excp_750cl(env); 5241 env->dcache_line_size = 32; 5242 env->icache_line_size = 32; 5243 /* Allocate hardware IRQ controller */ 5244 ppc6xx_irq_init(env_archcpu(env)); 5245 } 5246 5247 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 5248 { 5249 DeviceClass *dc = DEVICE_CLASS(oc); 5250 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5251 5252 dc->desc = "PowerPC 750 CL"; 5253 pcc->init_proc = init_proc_750cl; 5254 pcc->check_pow = check_pow_hid0; 5255 /* 5256 * XXX: not implemented: 5257 * cache lock instructions: 5258 * dcbz_l 5259 * floating point paired instructions 5260 * psq_lux 5261 * psq_lx 5262 * psq_stux 5263 * psq_stx 5264 * ps_abs 5265 * ps_add 5266 * ps_cmpo0 5267 * ps_cmpo1 5268 * ps_cmpu0 5269 * ps_cmpu1 5270 * ps_div 5271 * ps_madd 5272 * ps_madds0 5273 * ps_madds1 5274 * ps_merge00 5275 * ps_merge01 5276 * ps_merge10 5277 * ps_merge11 5278 * ps_mr 5279 * ps_msub 5280 * ps_mul 5281 * ps_muls0 5282 * ps_muls1 5283 * ps_nabs 5284 * ps_neg 5285 * ps_nmadd 5286 * ps_nmsub 5287 * ps_res 5288 * ps_rsqrte 5289 * ps_sel 5290 * ps_sub 5291 * ps_sum0 5292 * ps_sum1 5293 */ 5294 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5295 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5296 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5297 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5298 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5299 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5300 PPC_SEGMENT | PPC_EXTERN; 5301 pcc->msr_mask = (1ull << MSR_POW) | 5302 (1ull << MSR_ILE) | 5303 (1ull << MSR_EE) | 5304 (1ull << MSR_PR) | 5305 (1ull << MSR_FP) | 5306 (1ull << MSR_ME) | 5307 (1ull << MSR_FE0) | 5308 (1ull << MSR_SE) | 5309 (1ull << MSR_DE) | 5310 (1ull << MSR_FE1) | 5311 (1ull << MSR_EP) | 5312 (1ull << MSR_IR) | 5313 (1ull << MSR_DR) | 5314 (1ull << MSR_PMM) | 5315 (1ull << MSR_RI) | 5316 (1ull << MSR_LE); 5317 pcc->mmu_model = POWERPC_MMU_32B; 5318 #if defined(CONFIG_SOFTMMU) 5319 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5320 #endif 5321 pcc->excp_model = POWERPC_EXCP_7x0; 5322 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5323 pcc->bfd_mach = bfd_mach_ppc_750; 5324 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5325 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5326 } 5327 5328 static void init_proc_750cx(CPUPPCState *env) 5329 { 5330 register_ne_601_sprs(env); 5331 register_sdr1_sprs(env); 5332 register_7xx_sprs(env); 5333 /* XXX : not implemented */ 5334 spr_register(env, SPR_L2CR, "L2CR", 5335 SPR_NOACCESS, SPR_NOACCESS, 5336 &spr_read_generic, spr_access_nop, 5337 0x00000000); 5338 /* Time base */ 5339 register_tbl(env); 5340 /* Thermal management */ 5341 register_thrm_sprs(env); 5342 /* This register is not implemented but is present for compatibility */ 5343 spr_register(env, SPR_SDA, "SDA", 5344 SPR_NOACCESS, SPR_NOACCESS, 5345 &spr_read_generic, &spr_write_generic, 5346 0x00000000); 5347 /* Hardware implementation registers */ 5348 /* XXX : not implemented */ 5349 spr_register(env, SPR_HID0, "HID0", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 0x00000000); 5353 /* XXX : not implemented */ 5354 spr_register(env, SPR_HID1, "HID1", 5355 SPR_NOACCESS, SPR_NOACCESS, 5356 &spr_read_generic, &spr_write_generic, 5357 0x00000000); 5358 /* Memory management */ 5359 register_low_BATs(env); 5360 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 5361 register_high_BATs(env); 5362 init_excp_750cx(env); 5363 env->dcache_line_size = 32; 5364 env->icache_line_size = 32; 5365 /* Allocate hardware IRQ controller */ 5366 ppc6xx_irq_init(env_archcpu(env)); 5367 } 5368 5369 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 5370 { 5371 DeviceClass *dc = DEVICE_CLASS(oc); 5372 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5373 5374 dc->desc = "PowerPC 750CX"; 5375 pcc->init_proc = init_proc_750cx; 5376 pcc->check_pow = check_pow_hid0; 5377 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5378 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5379 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5380 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5381 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5382 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5383 PPC_SEGMENT | PPC_EXTERN; 5384 pcc->msr_mask = (1ull << MSR_POW) | 5385 (1ull << MSR_ILE) | 5386 (1ull << MSR_EE) | 5387 (1ull << MSR_PR) | 5388 (1ull << MSR_FP) | 5389 (1ull << MSR_ME) | 5390 (1ull << MSR_FE0) | 5391 (1ull << MSR_SE) | 5392 (1ull << MSR_DE) | 5393 (1ull << MSR_FE1) | 5394 (1ull << MSR_EP) | 5395 (1ull << MSR_IR) | 5396 (1ull << MSR_DR) | 5397 (1ull << MSR_PMM) | 5398 (1ull << MSR_RI) | 5399 (1ull << MSR_LE); 5400 pcc->mmu_model = POWERPC_MMU_32B; 5401 #if defined(CONFIG_SOFTMMU) 5402 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5403 #endif 5404 pcc->excp_model = POWERPC_EXCP_7x0; 5405 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5406 pcc->bfd_mach = bfd_mach_ppc_750; 5407 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5408 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5409 } 5410 5411 static void init_proc_750fx(CPUPPCState *env) 5412 { 5413 register_ne_601_sprs(env); 5414 register_sdr1_sprs(env); 5415 register_7xx_sprs(env); 5416 /* XXX : not implemented */ 5417 spr_register(env, SPR_L2CR, "L2CR", 5418 SPR_NOACCESS, SPR_NOACCESS, 5419 &spr_read_generic, spr_access_nop, 5420 0x00000000); 5421 /* Time base */ 5422 register_tbl(env); 5423 /* Thermal management */ 5424 register_thrm_sprs(env); 5425 /* XXX : not implemented */ 5426 spr_register(env, SPR_750_THRM4, "THRM4", 5427 SPR_NOACCESS, SPR_NOACCESS, 5428 &spr_read_generic, &spr_write_generic, 5429 0x00000000); 5430 /* Hardware implementation registers */ 5431 /* XXX : not implemented */ 5432 spr_register(env, SPR_HID0, "HID0", 5433 SPR_NOACCESS, SPR_NOACCESS, 5434 &spr_read_generic, &spr_write_generic, 5435 0x00000000); 5436 /* XXX : not implemented */ 5437 spr_register(env, SPR_HID1, "HID1", 5438 SPR_NOACCESS, SPR_NOACCESS, 5439 &spr_read_generic, &spr_write_generic, 5440 0x00000000); 5441 /* XXX : not implemented */ 5442 spr_register(env, SPR_750FX_HID2, "HID2", 5443 SPR_NOACCESS, SPR_NOACCESS, 5444 &spr_read_generic, &spr_write_generic, 5445 0x00000000); 5446 /* Memory management */ 5447 register_low_BATs(env); 5448 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5449 register_high_BATs(env); 5450 init_excp_7x0(env); 5451 env->dcache_line_size = 32; 5452 env->icache_line_size = 32; 5453 /* Allocate hardware IRQ controller */ 5454 ppc6xx_irq_init(env_archcpu(env)); 5455 } 5456 5457 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 5458 { 5459 DeviceClass *dc = DEVICE_CLASS(oc); 5460 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5461 5462 dc->desc = "PowerPC 750FX"; 5463 pcc->init_proc = init_proc_750fx; 5464 pcc->check_pow = check_pow_hid0; 5465 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5467 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5468 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5469 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5470 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5471 PPC_SEGMENT | PPC_EXTERN; 5472 pcc->msr_mask = (1ull << MSR_POW) | 5473 (1ull << MSR_ILE) | 5474 (1ull << MSR_EE) | 5475 (1ull << MSR_PR) | 5476 (1ull << MSR_FP) | 5477 (1ull << MSR_ME) | 5478 (1ull << MSR_FE0) | 5479 (1ull << MSR_SE) | 5480 (1ull << MSR_DE) | 5481 (1ull << MSR_FE1) | 5482 (1ull << MSR_EP) | 5483 (1ull << MSR_IR) | 5484 (1ull << MSR_DR) | 5485 (1ull << MSR_PMM) | 5486 (1ull << MSR_RI) | 5487 (1ull << MSR_LE); 5488 pcc->mmu_model = POWERPC_MMU_32B; 5489 #if defined(CONFIG_SOFTMMU) 5490 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5491 #endif 5492 pcc->excp_model = POWERPC_EXCP_7x0; 5493 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5494 pcc->bfd_mach = bfd_mach_ppc_750; 5495 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5496 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5497 } 5498 5499 static void init_proc_750gx(CPUPPCState *env) 5500 { 5501 register_ne_601_sprs(env); 5502 register_sdr1_sprs(env); 5503 register_7xx_sprs(env); 5504 /* XXX : not implemented (XXX: different from 750fx) */ 5505 spr_register(env, SPR_L2CR, "L2CR", 5506 SPR_NOACCESS, SPR_NOACCESS, 5507 &spr_read_generic, spr_access_nop, 5508 0x00000000); 5509 /* Time base */ 5510 register_tbl(env); 5511 /* Thermal management */ 5512 register_thrm_sprs(env); 5513 /* XXX : not implemented */ 5514 spr_register(env, SPR_750_THRM4, "THRM4", 5515 SPR_NOACCESS, SPR_NOACCESS, 5516 &spr_read_generic, &spr_write_generic, 5517 0x00000000); 5518 /* Hardware implementation registers */ 5519 /* XXX : not implemented (XXX: different from 750fx) */ 5520 spr_register(env, SPR_HID0, "HID0", 5521 SPR_NOACCESS, SPR_NOACCESS, 5522 &spr_read_generic, &spr_write_generic, 5523 0x00000000); 5524 /* XXX : not implemented */ 5525 spr_register(env, SPR_HID1, "HID1", 5526 SPR_NOACCESS, SPR_NOACCESS, 5527 &spr_read_generic, &spr_write_generic, 5528 0x00000000); 5529 /* XXX : not implemented (XXX: different from 750fx) */ 5530 spr_register(env, SPR_750FX_HID2, "HID2", 5531 SPR_NOACCESS, SPR_NOACCESS, 5532 &spr_read_generic, &spr_write_generic, 5533 0x00000000); 5534 /* Memory management */ 5535 register_low_BATs(env); 5536 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5537 register_high_BATs(env); 5538 init_excp_7x0(env); 5539 env->dcache_line_size = 32; 5540 env->icache_line_size = 32; 5541 /* Allocate hardware IRQ controller */ 5542 ppc6xx_irq_init(env_archcpu(env)); 5543 } 5544 5545 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 5546 { 5547 DeviceClass *dc = DEVICE_CLASS(oc); 5548 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5549 5550 dc->desc = "PowerPC 750GX"; 5551 pcc->init_proc = init_proc_750gx; 5552 pcc->check_pow = check_pow_hid0; 5553 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5554 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5555 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5556 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5557 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5558 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5559 PPC_SEGMENT | PPC_EXTERN; 5560 pcc->msr_mask = (1ull << MSR_POW) | 5561 (1ull << MSR_ILE) | 5562 (1ull << MSR_EE) | 5563 (1ull << MSR_PR) | 5564 (1ull << MSR_FP) | 5565 (1ull << MSR_ME) | 5566 (1ull << MSR_FE0) | 5567 (1ull << MSR_SE) | 5568 (1ull << MSR_DE) | 5569 (1ull << MSR_FE1) | 5570 (1ull << MSR_EP) | 5571 (1ull << MSR_IR) | 5572 (1ull << MSR_DR) | 5573 (1ull << MSR_PMM) | 5574 (1ull << MSR_RI) | 5575 (1ull << MSR_LE); 5576 pcc->mmu_model = POWERPC_MMU_32B; 5577 #if defined(CONFIG_SOFTMMU) 5578 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5579 #endif 5580 pcc->excp_model = POWERPC_EXCP_7x0; 5581 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5582 pcc->bfd_mach = bfd_mach_ppc_750; 5583 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5584 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5585 } 5586 5587 static void init_proc_745(CPUPPCState *env) 5588 { 5589 register_ne_601_sprs(env); 5590 register_sdr1_sprs(env); 5591 register_7xx_sprs(env); 5592 register_G2_755_sprs(env); 5593 /* Time base */ 5594 register_tbl(env); 5595 /* Thermal management */ 5596 register_thrm_sprs(env); 5597 /* Hardware implementation registers */ 5598 /* XXX : not implemented */ 5599 spr_register(env, SPR_HID0, "HID0", 5600 SPR_NOACCESS, SPR_NOACCESS, 5601 &spr_read_generic, &spr_write_generic, 5602 0x00000000); 5603 /* XXX : not implemented */ 5604 spr_register(env, SPR_HID1, "HID1", 5605 SPR_NOACCESS, SPR_NOACCESS, 5606 &spr_read_generic, &spr_write_generic, 5607 0x00000000); 5608 /* XXX : not implemented */ 5609 spr_register(env, SPR_HID2, "HID2", 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 &spr_read_generic, &spr_write_generic, 5612 0x00000000); 5613 /* Memory management */ 5614 register_low_BATs(env); 5615 register_high_BATs(env); 5616 register_6xx_7xx_soft_tlb(env, 64, 2); 5617 init_excp_7x5(env); 5618 env->dcache_line_size = 32; 5619 env->icache_line_size = 32; 5620 /* Allocate hardware IRQ controller */ 5621 ppc6xx_irq_init(env_archcpu(env)); 5622 } 5623 5624 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 5625 { 5626 DeviceClass *dc = DEVICE_CLASS(oc); 5627 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5628 5629 dc->desc = "PowerPC 745"; 5630 pcc->init_proc = init_proc_745; 5631 pcc->check_pow = check_pow_hid0; 5632 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5633 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5634 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5635 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5636 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5637 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5638 PPC_SEGMENT | PPC_EXTERN; 5639 pcc->msr_mask = (1ull << MSR_POW) | 5640 (1ull << MSR_ILE) | 5641 (1ull << MSR_EE) | 5642 (1ull << MSR_PR) | 5643 (1ull << MSR_FP) | 5644 (1ull << MSR_ME) | 5645 (1ull << MSR_FE0) | 5646 (1ull << MSR_SE) | 5647 (1ull << MSR_DE) | 5648 (1ull << MSR_FE1) | 5649 (1ull << MSR_EP) | 5650 (1ull << MSR_IR) | 5651 (1ull << MSR_DR) | 5652 (1ull << MSR_PMM) | 5653 (1ull << MSR_RI) | 5654 (1ull << MSR_LE); 5655 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5656 pcc->excp_model = POWERPC_EXCP_7x5; 5657 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5658 pcc->bfd_mach = bfd_mach_ppc_750; 5659 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5660 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5661 } 5662 5663 static void init_proc_755(CPUPPCState *env) 5664 { 5665 register_ne_601_sprs(env); 5666 register_sdr1_sprs(env); 5667 register_7xx_sprs(env); 5668 register_G2_755_sprs(env); 5669 /* Time base */ 5670 register_tbl(env); 5671 /* L2 cache control */ 5672 /* XXX : not implemented */ 5673 spr_register(env, SPR_L2CR, "L2CR", 5674 SPR_NOACCESS, SPR_NOACCESS, 5675 &spr_read_generic, spr_access_nop, 5676 0x00000000); 5677 /* XXX : not implemented */ 5678 spr_register(env, SPR_L2PMCR, "L2PMCR", 5679 SPR_NOACCESS, SPR_NOACCESS, 5680 &spr_read_generic, &spr_write_generic, 5681 0x00000000); 5682 /* Thermal management */ 5683 register_thrm_sprs(env); 5684 /* Hardware implementation registers */ 5685 /* XXX : not implemented */ 5686 spr_register(env, SPR_HID0, "HID0", 5687 SPR_NOACCESS, SPR_NOACCESS, 5688 &spr_read_generic, &spr_write_generic, 5689 0x00000000); 5690 /* XXX : not implemented */ 5691 spr_register(env, SPR_HID1, "HID1", 5692 SPR_NOACCESS, SPR_NOACCESS, 5693 &spr_read_generic, &spr_write_generic, 5694 0x00000000); 5695 /* XXX : not implemented */ 5696 spr_register(env, SPR_HID2, "HID2", 5697 SPR_NOACCESS, SPR_NOACCESS, 5698 &spr_read_generic, &spr_write_generic, 5699 0x00000000); 5700 /* Memory management */ 5701 register_low_BATs(env); 5702 register_high_BATs(env); 5703 register_6xx_7xx_soft_tlb(env, 64, 2); 5704 init_excp_7x5(env); 5705 env->dcache_line_size = 32; 5706 env->icache_line_size = 32; 5707 /* Allocate hardware IRQ controller */ 5708 ppc6xx_irq_init(env_archcpu(env)); 5709 } 5710 5711 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 5712 { 5713 DeviceClass *dc = DEVICE_CLASS(oc); 5714 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5715 5716 dc->desc = "PowerPC 755"; 5717 pcc->init_proc = init_proc_755; 5718 pcc->check_pow = check_pow_hid0; 5719 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5720 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5721 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5722 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5723 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5724 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5725 PPC_SEGMENT | PPC_EXTERN; 5726 pcc->msr_mask = (1ull << MSR_POW) | 5727 (1ull << MSR_ILE) | 5728 (1ull << MSR_EE) | 5729 (1ull << MSR_PR) | 5730 (1ull << MSR_FP) | 5731 (1ull << MSR_ME) | 5732 (1ull << MSR_FE0) | 5733 (1ull << MSR_SE) | 5734 (1ull << MSR_DE) | 5735 (1ull << MSR_FE1) | 5736 (1ull << MSR_EP) | 5737 (1ull << MSR_IR) | 5738 (1ull << MSR_DR) | 5739 (1ull << MSR_PMM) | 5740 (1ull << MSR_RI) | 5741 (1ull << MSR_LE); 5742 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5743 pcc->excp_model = POWERPC_EXCP_7x5; 5744 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5745 pcc->bfd_mach = bfd_mach_ppc_750; 5746 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5747 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5748 } 5749 5750 static void init_proc_7400(CPUPPCState *env) 5751 { 5752 register_ne_601_sprs(env); 5753 register_sdr1_sprs(env); 5754 register_7xx_sprs(env); 5755 /* Time base */ 5756 register_tbl(env); 5757 /* 74xx specific SPR */ 5758 register_74xx_sprs(env); 5759 vscr_init(env, 0x00010000); 5760 /* XXX : not implemented */ 5761 spr_register(env, SPR_UBAMR, "UBAMR", 5762 &spr_read_ureg, SPR_NOACCESS, 5763 &spr_read_ureg, SPR_NOACCESS, 5764 0x00000000); 5765 /* XXX: this seems not implemented on all revisions. */ 5766 /* XXX : not implemented */ 5767 spr_register(env, SPR_MSSCR1, "MSSCR1", 5768 SPR_NOACCESS, SPR_NOACCESS, 5769 &spr_read_generic, &spr_write_generic, 5770 0x00000000); 5771 /* Thermal management */ 5772 register_thrm_sprs(env); 5773 /* Memory management */ 5774 register_low_BATs(env); 5775 init_excp_7400(env); 5776 env->dcache_line_size = 32; 5777 env->icache_line_size = 32; 5778 /* Allocate hardware IRQ controller */ 5779 ppc6xx_irq_init(env_archcpu(env)); 5780 } 5781 5782 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5783 { 5784 DeviceClass *dc = DEVICE_CLASS(oc); 5785 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5786 5787 dc->desc = "PowerPC 7400 (aka G4)"; 5788 pcc->init_proc = init_proc_7400; 5789 pcc->check_pow = check_pow_hid0; 5790 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5791 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5792 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5793 PPC_FLOAT_STFIWX | 5794 PPC_CACHE | PPC_CACHE_ICBI | 5795 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5796 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5797 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5798 PPC_MEM_TLBIA | 5799 PPC_SEGMENT | PPC_EXTERN | 5800 PPC_ALTIVEC; 5801 pcc->msr_mask = (1ull << MSR_VR) | 5802 (1ull << MSR_POW) | 5803 (1ull << MSR_ILE) | 5804 (1ull << MSR_EE) | 5805 (1ull << MSR_PR) | 5806 (1ull << MSR_FP) | 5807 (1ull << MSR_ME) | 5808 (1ull << MSR_FE0) | 5809 (1ull << MSR_SE) | 5810 (1ull << MSR_DE) | 5811 (1ull << MSR_FE1) | 5812 (1ull << MSR_EP) | 5813 (1ull << MSR_IR) | 5814 (1ull << MSR_DR) | 5815 (1ull << MSR_PMM) | 5816 (1ull << MSR_RI) | 5817 (1ull << MSR_LE); 5818 pcc->mmu_model = POWERPC_MMU_32B; 5819 #if defined(CONFIG_SOFTMMU) 5820 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5821 #endif 5822 pcc->excp_model = POWERPC_EXCP_74xx; 5823 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5824 pcc->bfd_mach = bfd_mach_ppc_7400; 5825 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5826 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5827 POWERPC_FLAG_BUS_CLK; 5828 } 5829 5830 static void init_proc_7410(CPUPPCState *env) 5831 { 5832 register_ne_601_sprs(env); 5833 register_sdr1_sprs(env); 5834 register_7xx_sprs(env); 5835 /* Time base */ 5836 register_tbl(env); 5837 /* 74xx specific SPR */ 5838 register_74xx_sprs(env); 5839 vscr_init(env, 0x00010000); 5840 /* XXX : not implemented */ 5841 spr_register(env, SPR_UBAMR, "UBAMR", 5842 &spr_read_ureg, SPR_NOACCESS, 5843 &spr_read_ureg, SPR_NOACCESS, 5844 0x00000000); 5845 /* Thermal management */ 5846 register_thrm_sprs(env); 5847 /* L2PMCR */ 5848 /* XXX : not implemented */ 5849 spr_register(env, SPR_L2PMCR, "L2PMCR", 5850 SPR_NOACCESS, SPR_NOACCESS, 5851 &spr_read_generic, &spr_write_generic, 5852 0x00000000); 5853 /* LDSTDB */ 5854 /* XXX : not implemented */ 5855 spr_register(env, SPR_LDSTDB, "LDSTDB", 5856 SPR_NOACCESS, SPR_NOACCESS, 5857 &spr_read_generic, &spr_write_generic, 5858 0x00000000); 5859 /* Memory management */ 5860 register_low_BATs(env); 5861 init_excp_7400(env); 5862 env->dcache_line_size = 32; 5863 env->icache_line_size = 32; 5864 /* Allocate hardware IRQ controller */ 5865 ppc6xx_irq_init(env_archcpu(env)); 5866 } 5867 5868 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5869 { 5870 DeviceClass *dc = DEVICE_CLASS(oc); 5871 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5872 5873 dc->desc = "PowerPC 7410 (aka G4)"; 5874 pcc->init_proc = init_proc_7410; 5875 pcc->check_pow = check_pow_hid0; 5876 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5877 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5878 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5879 PPC_FLOAT_STFIWX | 5880 PPC_CACHE | PPC_CACHE_ICBI | 5881 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5882 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5883 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5884 PPC_MEM_TLBIA | 5885 PPC_SEGMENT | PPC_EXTERN | 5886 PPC_ALTIVEC; 5887 pcc->msr_mask = (1ull << MSR_VR) | 5888 (1ull << MSR_POW) | 5889 (1ull << MSR_ILE) | 5890 (1ull << MSR_EE) | 5891 (1ull << MSR_PR) | 5892 (1ull << MSR_FP) | 5893 (1ull << MSR_ME) | 5894 (1ull << MSR_FE0) | 5895 (1ull << MSR_SE) | 5896 (1ull << MSR_DE) | 5897 (1ull << MSR_FE1) | 5898 (1ull << MSR_EP) | 5899 (1ull << MSR_IR) | 5900 (1ull << MSR_DR) | 5901 (1ull << MSR_PMM) | 5902 (1ull << MSR_RI) | 5903 (1ull << MSR_LE); 5904 pcc->mmu_model = POWERPC_MMU_32B; 5905 #if defined(CONFIG_SOFTMMU) 5906 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5907 #endif 5908 pcc->excp_model = POWERPC_EXCP_74xx; 5909 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5910 pcc->bfd_mach = bfd_mach_ppc_7400; 5911 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5912 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5913 POWERPC_FLAG_BUS_CLK; 5914 } 5915 5916 static void init_proc_7440(CPUPPCState *env) 5917 { 5918 register_ne_601_sprs(env); 5919 register_sdr1_sprs(env); 5920 register_7xx_sprs(env); 5921 /* Time base */ 5922 register_tbl(env); 5923 /* 74xx specific SPR */ 5924 register_74xx_sprs(env); 5925 vscr_init(env, 0x00010000); 5926 /* XXX : not implemented */ 5927 spr_register(env, SPR_UBAMR, "UBAMR", 5928 &spr_read_ureg, SPR_NOACCESS, 5929 &spr_read_ureg, SPR_NOACCESS, 5930 0x00000000); 5931 /* LDSTCR */ 5932 /* XXX : not implemented */ 5933 spr_register(env, SPR_LDSTCR, "LDSTCR", 5934 SPR_NOACCESS, SPR_NOACCESS, 5935 &spr_read_generic, &spr_write_generic, 5936 0x00000000); 5937 /* ICTRL */ 5938 /* XXX : not implemented */ 5939 spr_register(env, SPR_ICTRL, "ICTRL", 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 &spr_read_generic, &spr_write_generic, 5942 0x00000000); 5943 /* MSSSR0 */ 5944 /* XXX : not implemented */ 5945 spr_register(env, SPR_MSSSR0, "MSSSR0", 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 &spr_read_generic, &spr_write_generic, 5948 0x00000000); 5949 /* PMC */ 5950 /* XXX : not implemented */ 5951 spr_register(env, SPR_7XX_PMC5, "PMC5", 5952 SPR_NOACCESS, SPR_NOACCESS, 5953 &spr_read_generic, &spr_write_generic, 5954 0x00000000); 5955 /* XXX : not implemented */ 5956 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5957 &spr_read_ureg, SPR_NOACCESS, 5958 &spr_read_ureg, SPR_NOACCESS, 5959 0x00000000); 5960 /* XXX : not implemented */ 5961 spr_register(env, SPR_7XX_PMC6, "PMC6", 5962 SPR_NOACCESS, SPR_NOACCESS, 5963 &spr_read_generic, &spr_write_generic, 5964 0x00000000); 5965 /* XXX : not implemented */ 5966 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5967 &spr_read_ureg, SPR_NOACCESS, 5968 &spr_read_ureg, SPR_NOACCESS, 5969 0x00000000); 5970 /* Memory management */ 5971 register_low_BATs(env); 5972 register_74xx_soft_tlb(env, 128, 2); 5973 init_excp_7450(env); 5974 env->dcache_line_size = 32; 5975 env->icache_line_size = 32; 5976 /* Allocate hardware IRQ controller */ 5977 ppc6xx_irq_init(env_archcpu(env)); 5978 } 5979 5980 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5981 { 5982 DeviceClass *dc = DEVICE_CLASS(oc); 5983 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5984 5985 dc->desc = "PowerPC 7440 (aka G4)"; 5986 pcc->init_proc = init_proc_7440; 5987 pcc->check_pow = check_pow_hid0_74xx; 5988 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5990 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5991 PPC_FLOAT_STFIWX | 5992 PPC_CACHE | PPC_CACHE_ICBI | 5993 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5994 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5995 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5996 PPC_MEM_TLBIA | PPC_74xx_TLB | 5997 PPC_SEGMENT | PPC_EXTERN | 5998 PPC_ALTIVEC; 5999 pcc->msr_mask = (1ull << MSR_VR) | 6000 (1ull << MSR_POW) | 6001 (1ull << MSR_ILE) | 6002 (1ull << MSR_EE) | 6003 (1ull << MSR_PR) | 6004 (1ull << MSR_FP) | 6005 (1ull << MSR_ME) | 6006 (1ull << MSR_FE0) | 6007 (1ull << MSR_SE) | 6008 (1ull << MSR_DE) | 6009 (1ull << MSR_FE1) | 6010 (1ull << MSR_EP) | 6011 (1ull << MSR_IR) | 6012 (1ull << MSR_DR) | 6013 (1ull << MSR_PMM) | 6014 (1ull << MSR_RI) | 6015 (1ull << MSR_LE); 6016 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6017 pcc->excp_model = POWERPC_EXCP_74xx; 6018 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6019 pcc->bfd_mach = bfd_mach_ppc_7400; 6020 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6021 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6022 POWERPC_FLAG_BUS_CLK; 6023 } 6024 6025 static void init_proc_7450(CPUPPCState *env) 6026 { 6027 register_ne_601_sprs(env); 6028 register_sdr1_sprs(env); 6029 register_7xx_sprs(env); 6030 /* Time base */ 6031 register_tbl(env); 6032 /* 74xx specific SPR */ 6033 register_74xx_sprs(env); 6034 vscr_init(env, 0x00010000); 6035 /* Level 3 cache control */ 6036 register_l3_ctrl(env); 6037 /* L3ITCR1 */ 6038 /* XXX : not implemented */ 6039 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6040 SPR_NOACCESS, SPR_NOACCESS, 6041 &spr_read_generic, &spr_write_generic, 6042 0x00000000); 6043 /* L3ITCR2 */ 6044 /* XXX : not implemented */ 6045 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6046 SPR_NOACCESS, SPR_NOACCESS, 6047 &spr_read_generic, &spr_write_generic, 6048 0x00000000); 6049 /* L3ITCR3 */ 6050 /* XXX : not implemented */ 6051 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6052 SPR_NOACCESS, SPR_NOACCESS, 6053 &spr_read_generic, &spr_write_generic, 6054 0x00000000); 6055 /* L3OHCR */ 6056 /* XXX : not implemented */ 6057 spr_register(env, SPR_L3OHCR, "L3OHCR", 6058 SPR_NOACCESS, SPR_NOACCESS, 6059 &spr_read_generic, &spr_write_generic, 6060 0x00000000); 6061 /* XXX : not implemented */ 6062 spr_register(env, SPR_UBAMR, "UBAMR", 6063 &spr_read_ureg, SPR_NOACCESS, 6064 &spr_read_ureg, SPR_NOACCESS, 6065 0x00000000); 6066 /* LDSTCR */ 6067 /* XXX : not implemented */ 6068 spr_register(env, SPR_LDSTCR, "LDSTCR", 6069 SPR_NOACCESS, SPR_NOACCESS, 6070 &spr_read_generic, &spr_write_generic, 6071 0x00000000); 6072 /* ICTRL */ 6073 /* XXX : not implemented */ 6074 spr_register(env, SPR_ICTRL, "ICTRL", 6075 SPR_NOACCESS, SPR_NOACCESS, 6076 &spr_read_generic, &spr_write_generic, 6077 0x00000000); 6078 /* MSSSR0 */ 6079 /* XXX : not implemented */ 6080 spr_register(env, SPR_MSSSR0, "MSSSR0", 6081 SPR_NOACCESS, SPR_NOACCESS, 6082 &spr_read_generic, &spr_write_generic, 6083 0x00000000); 6084 /* PMC */ 6085 /* XXX : not implemented */ 6086 spr_register(env, SPR_7XX_PMC5, "PMC5", 6087 SPR_NOACCESS, SPR_NOACCESS, 6088 &spr_read_generic, &spr_write_generic, 6089 0x00000000); 6090 /* XXX : not implemented */ 6091 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6092 &spr_read_ureg, SPR_NOACCESS, 6093 &spr_read_ureg, SPR_NOACCESS, 6094 0x00000000); 6095 /* XXX : not implemented */ 6096 spr_register(env, SPR_7XX_PMC6, "PMC6", 6097 SPR_NOACCESS, SPR_NOACCESS, 6098 &spr_read_generic, &spr_write_generic, 6099 0x00000000); 6100 /* XXX : not implemented */ 6101 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6102 &spr_read_ureg, SPR_NOACCESS, 6103 &spr_read_ureg, SPR_NOACCESS, 6104 0x00000000); 6105 /* Memory management */ 6106 register_low_BATs(env); 6107 register_74xx_soft_tlb(env, 128, 2); 6108 init_excp_7450(env); 6109 env->dcache_line_size = 32; 6110 env->icache_line_size = 32; 6111 /* Allocate hardware IRQ controller */ 6112 ppc6xx_irq_init(env_archcpu(env)); 6113 } 6114 6115 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 6116 { 6117 DeviceClass *dc = DEVICE_CLASS(oc); 6118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6119 6120 dc->desc = "PowerPC 7450 (aka G4)"; 6121 pcc->init_proc = init_proc_7450; 6122 pcc->check_pow = check_pow_hid0_74xx; 6123 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6124 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6125 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6126 PPC_FLOAT_STFIWX | 6127 PPC_CACHE | PPC_CACHE_ICBI | 6128 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6129 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6130 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6131 PPC_MEM_TLBIA | PPC_74xx_TLB | 6132 PPC_SEGMENT | PPC_EXTERN | 6133 PPC_ALTIVEC; 6134 pcc->msr_mask = (1ull << MSR_VR) | 6135 (1ull << MSR_POW) | 6136 (1ull << MSR_ILE) | 6137 (1ull << MSR_EE) | 6138 (1ull << MSR_PR) | 6139 (1ull << MSR_FP) | 6140 (1ull << MSR_ME) | 6141 (1ull << MSR_FE0) | 6142 (1ull << MSR_SE) | 6143 (1ull << MSR_DE) | 6144 (1ull << MSR_FE1) | 6145 (1ull << MSR_EP) | 6146 (1ull << MSR_IR) | 6147 (1ull << MSR_DR) | 6148 (1ull << MSR_PMM) | 6149 (1ull << MSR_RI) | 6150 (1ull << MSR_LE); 6151 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6152 pcc->excp_model = POWERPC_EXCP_74xx; 6153 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6154 pcc->bfd_mach = bfd_mach_ppc_7400; 6155 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6156 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6157 POWERPC_FLAG_BUS_CLK; 6158 } 6159 6160 static void init_proc_7445(CPUPPCState *env) 6161 { 6162 register_ne_601_sprs(env); 6163 register_sdr1_sprs(env); 6164 register_7xx_sprs(env); 6165 /* Time base */ 6166 register_tbl(env); 6167 /* 74xx specific SPR */ 6168 register_74xx_sprs(env); 6169 vscr_init(env, 0x00010000); 6170 /* LDSTCR */ 6171 /* XXX : not implemented */ 6172 spr_register(env, SPR_LDSTCR, "LDSTCR", 6173 SPR_NOACCESS, SPR_NOACCESS, 6174 &spr_read_generic, &spr_write_generic, 6175 0x00000000); 6176 /* ICTRL */ 6177 /* XXX : not implemented */ 6178 spr_register(env, SPR_ICTRL, "ICTRL", 6179 SPR_NOACCESS, SPR_NOACCESS, 6180 &spr_read_generic, &spr_write_generic, 6181 0x00000000); 6182 /* MSSSR0 */ 6183 /* XXX : not implemented */ 6184 spr_register(env, SPR_MSSSR0, "MSSSR0", 6185 SPR_NOACCESS, SPR_NOACCESS, 6186 &spr_read_generic, &spr_write_generic, 6187 0x00000000); 6188 /* PMC */ 6189 /* XXX : not implemented */ 6190 spr_register(env, SPR_7XX_PMC5, "PMC5", 6191 SPR_NOACCESS, SPR_NOACCESS, 6192 &spr_read_generic, &spr_write_generic, 6193 0x00000000); 6194 /* XXX : not implemented */ 6195 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6196 &spr_read_ureg, SPR_NOACCESS, 6197 &spr_read_ureg, SPR_NOACCESS, 6198 0x00000000); 6199 /* XXX : not implemented */ 6200 spr_register(env, SPR_7XX_PMC6, "PMC6", 6201 SPR_NOACCESS, SPR_NOACCESS, 6202 &spr_read_generic, &spr_write_generic, 6203 0x00000000); 6204 /* XXX : not implemented */ 6205 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6206 &spr_read_ureg, SPR_NOACCESS, 6207 &spr_read_ureg, SPR_NOACCESS, 6208 0x00000000); 6209 /* SPRGs */ 6210 spr_register(env, SPR_SPRG4, "SPRG4", 6211 SPR_NOACCESS, SPR_NOACCESS, 6212 &spr_read_generic, &spr_write_generic, 6213 0x00000000); 6214 spr_register(env, SPR_USPRG4, "USPRG4", 6215 &spr_read_ureg, SPR_NOACCESS, 6216 &spr_read_ureg, SPR_NOACCESS, 6217 0x00000000); 6218 spr_register(env, SPR_SPRG5, "SPRG5", 6219 SPR_NOACCESS, SPR_NOACCESS, 6220 &spr_read_generic, &spr_write_generic, 6221 0x00000000); 6222 spr_register(env, SPR_USPRG5, "USPRG5", 6223 &spr_read_ureg, SPR_NOACCESS, 6224 &spr_read_ureg, SPR_NOACCESS, 6225 0x00000000); 6226 spr_register(env, SPR_SPRG6, "SPRG6", 6227 SPR_NOACCESS, SPR_NOACCESS, 6228 &spr_read_generic, &spr_write_generic, 6229 0x00000000); 6230 spr_register(env, SPR_USPRG6, "USPRG6", 6231 &spr_read_ureg, SPR_NOACCESS, 6232 &spr_read_ureg, SPR_NOACCESS, 6233 0x00000000); 6234 spr_register(env, SPR_SPRG7, "SPRG7", 6235 SPR_NOACCESS, SPR_NOACCESS, 6236 &spr_read_generic, &spr_write_generic, 6237 0x00000000); 6238 spr_register(env, SPR_USPRG7, "USPRG7", 6239 &spr_read_ureg, SPR_NOACCESS, 6240 &spr_read_ureg, SPR_NOACCESS, 6241 0x00000000); 6242 /* Memory management */ 6243 register_low_BATs(env); 6244 register_high_BATs(env); 6245 register_74xx_soft_tlb(env, 128, 2); 6246 init_excp_7450(env); 6247 env->dcache_line_size = 32; 6248 env->icache_line_size = 32; 6249 /* Allocate hardware IRQ controller */ 6250 ppc6xx_irq_init(env_archcpu(env)); 6251 } 6252 6253 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 6254 { 6255 DeviceClass *dc = DEVICE_CLASS(oc); 6256 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6257 6258 dc->desc = "PowerPC 7445 (aka G4)"; 6259 pcc->init_proc = init_proc_7445; 6260 pcc->check_pow = check_pow_hid0_74xx; 6261 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6262 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6263 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6264 PPC_FLOAT_STFIWX | 6265 PPC_CACHE | PPC_CACHE_ICBI | 6266 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6267 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6268 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6269 PPC_MEM_TLBIA | PPC_74xx_TLB | 6270 PPC_SEGMENT | PPC_EXTERN | 6271 PPC_ALTIVEC; 6272 pcc->msr_mask = (1ull << MSR_VR) | 6273 (1ull << MSR_POW) | 6274 (1ull << MSR_ILE) | 6275 (1ull << MSR_EE) | 6276 (1ull << MSR_PR) | 6277 (1ull << MSR_FP) | 6278 (1ull << MSR_ME) | 6279 (1ull << MSR_FE0) | 6280 (1ull << MSR_SE) | 6281 (1ull << MSR_DE) | 6282 (1ull << MSR_FE1) | 6283 (1ull << MSR_EP) | 6284 (1ull << MSR_IR) | 6285 (1ull << MSR_DR) | 6286 (1ull << MSR_PMM) | 6287 (1ull << MSR_RI) | 6288 (1ull << MSR_LE); 6289 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6290 pcc->excp_model = POWERPC_EXCP_74xx; 6291 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6292 pcc->bfd_mach = bfd_mach_ppc_7400; 6293 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6294 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6295 POWERPC_FLAG_BUS_CLK; 6296 } 6297 6298 static void init_proc_7455(CPUPPCState *env) 6299 { 6300 register_ne_601_sprs(env); 6301 register_sdr1_sprs(env); 6302 register_7xx_sprs(env); 6303 /* Time base */ 6304 register_tbl(env); 6305 /* 74xx specific SPR */ 6306 register_74xx_sprs(env); 6307 vscr_init(env, 0x00010000); 6308 /* Level 3 cache control */ 6309 register_l3_ctrl(env); 6310 /* LDSTCR */ 6311 /* XXX : not implemented */ 6312 spr_register(env, SPR_LDSTCR, "LDSTCR", 6313 SPR_NOACCESS, SPR_NOACCESS, 6314 &spr_read_generic, &spr_write_generic, 6315 0x00000000); 6316 /* ICTRL */ 6317 /* XXX : not implemented */ 6318 spr_register(env, SPR_ICTRL, "ICTRL", 6319 SPR_NOACCESS, SPR_NOACCESS, 6320 &spr_read_generic, &spr_write_generic, 6321 0x00000000); 6322 /* MSSSR0 */ 6323 /* XXX : not implemented */ 6324 spr_register(env, SPR_MSSSR0, "MSSSR0", 6325 SPR_NOACCESS, SPR_NOACCESS, 6326 &spr_read_generic, &spr_write_generic, 6327 0x00000000); 6328 /* PMC */ 6329 /* XXX : not implemented */ 6330 spr_register(env, SPR_7XX_PMC5, "PMC5", 6331 SPR_NOACCESS, SPR_NOACCESS, 6332 &spr_read_generic, &spr_write_generic, 6333 0x00000000); 6334 /* XXX : not implemented */ 6335 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6336 &spr_read_ureg, SPR_NOACCESS, 6337 &spr_read_ureg, SPR_NOACCESS, 6338 0x00000000); 6339 /* XXX : not implemented */ 6340 spr_register(env, SPR_7XX_PMC6, "PMC6", 6341 SPR_NOACCESS, SPR_NOACCESS, 6342 &spr_read_generic, &spr_write_generic, 6343 0x00000000); 6344 /* XXX : not implemented */ 6345 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6346 &spr_read_ureg, SPR_NOACCESS, 6347 &spr_read_ureg, SPR_NOACCESS, 6348 0x00000000); 6349 /* SPRGs */ 6350 spr_register(env, SPR_SPRG4, "SPRG4", 6351 SPR_NOACCESS, SPR_NOACCESS, 6352 &spr_read_generic, &spr_write_generic, 6353 0x00000000); 6354 spr_register(env, SPR_USPRG4, "USPRG4", 6355 &spr_read_ureg, SPR_NOACCESS, 6356 &spr_read_ureg, SPR_NOACCESS, 6357 0x00000000); 6358 spr_register(env, SPR_SPRG5, "SPRG5", 6359 SPR_NOACCESS, SPR_NOACCESS, 6360 &spr_read_generic, &spr_write_generic, 6361 0x00000000); 6362 spr_register(env, SPR_USPRG5, "USPRG5", 6363 &spr_read_ureg, SPR_NOACCESS, 6364 &spr_read_ureg, SPR_NOACCESS, 6365 0x00000000); 6366 spr_register(env, SPR_SPRG6, "SPRG6", 6367 SPR_NOACCESS, SPR_NOACCESS, 6368 &spr_read_generic, &spr_write_generic, 6369 0x00000000); 6370 spr_register(env, SPR_USPRG6, "USPRG6", 6371 &spr_read_ureg, SPR_NOACCESS, 6372 &spr_read_ureg, SPR_NOACCESS, 6373 0x00000000); 6374 spr_register(env, SPR_SPRG7, "SPRG7", 6375 SPR_NOACCESS, SPR_NOACCESS, 6376 &spr_read_generic, &spr_write_generic, 6377 0x00000000); 6378 spr_register(env, SPR_USPRG7, "USPRG7", 6379 &spr_read_ureg, SPR_NOACCESS, 6380 &spr_read_ureg, SPR_NOACCESS, 6381 0x00000000); 6382 /* Memory management */ 6383 register_low_BATs(env); 6384 register_high_BATs(env); 6385 register_74xx_soft_tlb(env, 128, 2); 6386 init_excp_7450(env); 6387 env->dcache_line_size = 32; 6388 env->icache_line_size = 32; 6389 /* Allocate hardware IRQ controller */ 6390 ppc6xx_irq_init(env_archcpu(env)); 6391 } 6392 6393 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 6394 { 6395 DeviceClass *dc = DEVICE_CLASS(oc); 6396 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6397 6398 dc->desc = "PowerPC 7455 (aka G4)"; 6399 pcc->init_proc = init_proc_7455; 6400 pcc->check_pow = check_pow_hid0_74xx; 6401 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6402 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6403 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6404 PPC_FLOAT_STFIWX | 6405 PPC_CACHE | PPC_CACHE_ICBI | 6406 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6407 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6408 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6409 PPC_MEM_TLBIA | PPC_74xx_TLB | 6410 PPC_SEGMENT | PPC_EXTERN | 6411 PPC_ALTIVEC; 6412 pcc->msr_mask = (1ull << MSR_VR) | 6413 (1ull << MSR_POW) | 6414 (1ull << MSR_ILE) | 6415 (1ull << MSR_EE) | 6416 (1ull << MSR_PR) | 6417 (1ull << MSR_FP) | 6418 (1ull << MSR_ME) | 6419 (1ull << MSR_FE0) | 6420 (1ull << MSR_SE) | 6421 (1ull << MSR_DE) | 6422 (1ull << MSR_FE1) | 6423 (1ull << MSR_EP) | 6424 (1ull << MSR_IR) | 6425 (1ull << MSR_DR) | 6426 (1ull << MSR_PMM) | 6427 (1ull << MSR_RI) | 6428 (1ull << MSR_LE); 6429 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6430 pcc->excp_model = POWERPC_EXCP_74xx; 6431 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6432 pcc->bfd_mach = bfd_mach_ppc_7400; 6433 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6434 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6435 POWERPC_FLAG_BUS_CLK; 6436 } 6437 6438 static void init_proc_7457(CPUPPCState *env) 6439 { 6440 register_ne_601_sprs(env); 6441 register_sdr1_sprs(env); 6442 register_7xx_sprs(env); 6443 /* Time base */ 6444 register_tbl(env); 6445 /* 74xx specific SPR */ 6446 register_74xx_sprs(env); 6447 vscr_init(env, 0x00010000); 6448 /* Level 3 cache control */ 6449 register_l3_ctrl(env); 6450 /* L3ITCR1 */ 6451 /* XXX : not implemented */ 6452 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6453 SPR_NOACCESS, SPR_NOACCESS, 6454 &spr_read_generic, &spr_write_generic, 6455 0x00000000); 6456 /* L3ITCR2 */ 6457 /* XXX : not implemented */ 6458 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6459 SPR_NOACCESS, SPR_NOACCESS, 6460 &spr_read_generic, &spr_write_generic, 6461 0x00000000); 6462 /* L3ITCR3 */ 6463 /* XXX : not implemented */ 6464 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6465 SPR_NOACCESS, SPR_NOACCESS, 6466 &spr_read_generic, &spr_write_generic, 6467 0x00000000); 6468 /* L3OHCR */ 6469 /* XXX : not implemented */ 6470 spr_register(env, SPR_L3OHCR, "L3OHCR", 6471 SPR_NOACCESS, SPR_NOACCESS, 6472 &spr_read_generic, &spr_write_generic, 6473 0x00000000); 6474 /* LDSTCR */ 6475 /* XXX : not implemented */ 6476 spr_register(env, SPR_LDSTCR, "LDSTCR", 6477 SPR_NOACCESS, SPR_NOACCESS, 6478 &spr_read_generic, &spr_write_generic, 6479 0x00000000); 6480 /* ICTRL */ 6481 /* XXX : not implemented */ 6482 spr_register(env, SPR_ICTRL, "ICTRL", 6483 SPR_NOACCESS, SPR_NOACCESS, 6484 &spr_read_generic, &spr_write_generic, 6485 0x00000000); 6486 /* MSSSR0 */ 6487 /* XXX : not implemented */ 6488 spr_register(env, SPR_MSSSR0, "MSSSR0", 6489 SPR_NOACCESS, SPR_NOACCESS, 6490 &spr_read_generic, &spr_write_generic, 6491 0x00000000); 6492 /* PMC */ 6493 /* XXX : not implemented */ 6494 spr_register(env, SPR_7XX_PMC5, "PMC5", 6495 SPR_NOACCESS, SPR_NOACCESS, 6496 &spr_read_generic, &spr_write_generic, 6497 0x00000000); 6498 /* XXX : not implemented */ 6499 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6500 &spr_read_ureg, SPR_NOACCESS, 6501 &spr_read_ureg, SPR_NOACCESS, 6502 0x00000000); 6503 /* XXX : not implemented */ 6504 spr_register(env, SPR_7XX_PMC6, "PMC6", 6505 SPR_NOACCESS, SPR_NOACCESS, 6506 &spr_read_generic, &spr_write_generic, 6507 0x00000000); 6508 /* XXX : not implemented */ 6509 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6510 &spr_read_ureg, SPR_NOACCESS, 6511 &spr_read_ureg, SPR_NOACCESS, 6512 0x00000000); 6513 /* SPRGs */ 6514 spr_register(env, SPR_SPRG4, "SPRG4", 6515 SPR_NOACCESS, SPR_NOACCESS, 6516 &spr_read_generic, &spr_write_generic, 6517 0x00000000); 6518 spr_register(env, SPR_USPRG4, "USPRG4", 6519 &spr_read_ureg, SPR_NOACCESS, 6520 &spr_read_ureg, SPR_NOACCESS, 6521 0x00000000); 6522 spr_register(env, SPR_SPRG5, "SPRG5", 6523 SPR_NOACCESS, SPR_NOACCESS, 6524 &spr_read_generic, &spr_write_generic, 6525 0x00000000); 6526 spr_register(env, SPR_USPRG5, "USPRG5", 6527 &spr_read_ureg, SPR_NOACCESS, 6528 &spr_read_ureg, SPR_NOACCESS, 6529 0x00000000); 6530 spr_register(env, SPR_SPRG6, "SPRG6", 6531 SPR_NOACCESS, SPR_NOACCESS, 6532 &spr_read_generic, &spr_write_generic, 6533 0x00000000); 6534 spr_register(env, SPR_USPRG6, "USPRG6", 6535 &spr_read_ureg, SPR_NOACCESS, 6536 &spr_read_ureg, SPR_NOACCESS, 6537 0x00000000); 6538 spr_register(env, SPR_SPRG7, "SPRG7", 6539 SPR_NOACCESS, SPR_NOACCESS, 6540 &spr_read_generic, &spr_write_generic, 6541 0x00000000); 6542 spr_register(env, SPR_USPRG7, "USPRG7", 6543 &spr_read_ureg, SPR_NOACCESS, 6544 &spr_read_ureg, SPR_NOACCESS, 6545 0x00000000); 6546 /* Memory management */ 6547 register_low_BATs(env); 6548 register_high_BATs(env); 6549 register_74xx_soft_tlb(env, 128, 2); 6550 init_excp_7450(env); 6551 env->dcache_line_size = 32; 6552 env->icache_line_size = 32; 6553 /* Allocate hardware IRQ controller */ 6554 ppc6xx_irq_init(env_archcpu(env)); 6555 } 6556 6557 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 6558 { 6559 DeviceClass *dc = DEVICE_CLASS(oc); 6560 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6561 6562 dc->desc = "PowerPC 7457 (aka G4)"; 6563 pcc->init_proc = init_proc_7457; 6564 pcc->check_pow = check_pow_hid0_74xx; 6565 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6566 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6567 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6568 PPC_FLOAT_STFIWX | 6569 PPC_CACHE | PPC_CACHE_ICBI | 6570 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6571 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6572 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6573 PPC_MEM_TLBIA | PPC_74xx_TLB | 6574 PPC_SEGMENT | PPC_EXTERN | 6575 PPC_ALTIVEC; 6576 pcc->msr_mask = (1ull << MSR_VR) | 6577 (1ull << MSR_POW) | 6578 (1ull << MSR_ILE) | 6579 (1ull << MSR_EE) | 6580 (1ull << MSR_PR) | 6581 (1ull << MSR_FP) | 6582 (1ull << MSR_ME) | 6583 (1ull << MSR_FE0) | 6584 (1ull << MSR_SE) | 6585 (1ull << MSR_DE) | 6586 (1ull << MSR_FE1) | 6587 (1ull << MSR_EP) | 6588 (1ull << MSR_IR) | 6589 (1ull << MSR_DR) | 6590 (1ull << MSR_PMM) | 6591 (1ull << MSR_RI) | 6592 (1ull << MSR_LE); 6593 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6594 pcc->excp_model = POWERPC_EXCP_74xx; 6595 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6596 pcc->bfd_mach = bfd_mach_ppc_7400; 6597 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6598 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6599 POWERPC_FLAG_BUS_CLK; 6600 } 6601 6602 static void init_proc_e600(CPUPPCState *env) 6603 { 6604 register_ne_601_sprs(env); 6605 register_sdr1_sprs(env); 6606 register_7xx_sprs(env); 6607 /* Time base */ 6608 register_tbl(env); 6609 /* 74xx specific SPR */ 6610 register_74xx_sprs(env); 6611 vscr_init(env, 0x00010000); 6612 /* XXX : not implemented */ 6613 spr_register(env, SPR_UBAMR, "UBAMR", 6614 &spr_read_ureg, SPR_NOACCESS, 6615 &spr_read_ureg, SPR_NOACCESS, 6616 0x00000000); 6617 /* XXX : not implemented */ 6618 spr_register(env, SPR_LDSTCR, "LDSTCR", 6619 SPR_NOACCESS, SPR_NOACCESS, 6620 &spr_read_generic, &spr_write_generic, 6621 0x00000000); 6622 /* XXX : not implemented */ 6623 spr_register(env, SPR_ICTRL, "ICTRL", 6624 SPR_NOACCESS, SPR_NOACCESS, 6625 &spr_read_generic, &spr_write_generic, 6626 0x00000000); 6627 /* XXX : not implemented */ 6628 spr_register(env, SPR_MSSSR0, "MSSSR0", 6629 SPR_NOACCESS, SPR_NOACCESS, 6630 &spr_read_generic, &spr_write_generic, 6631 0x00000000); 6632 /* XXX : not implemented */ 6633 spr_register(env, SPR_7XX_PMC5, "PMC5", 6634 SPR_NOACCESS, SPR_NOACCESS, 6635 &spr_read_generic, &spr_write_generic, 6636 0x00000000); 6637 /* XXX : not implemented */ 6638 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6639 &spr_read_ureg, SPR_NOACCESS, 6640 &spr_read_ureg, SPR_NOACCESS, 6641 0x00000000); 6642 /* XXX : not implemented */ 6643 spr_register(env, SPR_7XX_PMC6, "PMC6", 6644 SPR_NOACCESS, SPR_NOACCESS, 6645 &spr_read_generic, &spr_write_generic, 6646 0x00000000); 6647 /* XXX : not implemented */ 6648 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6649 &spr_read_ureg, SPR_NOACCESS, 6650 &spr_read_ureg, SPR_NOACCESS, 6651 0x00000000); 6652 /* SPRGs */ 6653 spr_register(env, SPR_SPRG4, "SPRG4", 6654 SPR_NOACCESS, SPR_NOACCESS, 6655 &spr_read_generic, &spr_write_generic, 6656 0x00000000); 6657 spr_register(env, SPR_USPRG4, "USPRG4", 6658 &spr_read_ureg, SPR_NOACCESS, 6659 &spr_read_ureg, SPR_NOACCESS, 6660 0x00000000); 6661 spr_register(env, SPR_SPRG5, "SPRG5", 6662 SPR_NOACCESS, SPR_NOACCESS, 6663 &spr_read_generic, &spr_write_generic, 6664 0x00000000); 6665 spr_register(env, SPR_USPRG5, "USPRG5", 6666 &spr_read_ureg, SPR_NOACCESS, 6667 &spr_read_ureg, SPR_NOACCESS, 6668 0x00000000); 6669 spr_register(env, SPR_SPRG6, "SPRG6", 6670 SPR_NOACCESS, SPR_NOACCESS, 6671 &spr_read_generic, &spr_write_generic, 6672 0x00000000); 6673 spr_register(env, SPR_USPRG6, "USPRG6", 6674 &spr_read_ureg, SPR_NOACCESS, 6675 &spr_read_ureg, SPR_NOACCESS, 6676 0x00000000); 6677 spr_register(env, SPR_SPRG7, "SPRG7", 6678 SPR_NOACCESS, SPR_NOACCESS, 6679 &spr_read_generic, &spr_write_generic, 6680 0x00000000); 6681 spr_register(env, SPR_USPRG7, "USPRG7", 6682 &spr_read_ureg, SPR_NOACCESS, 6683 &spr_read_ureg, SPR_NOACCESS, 6684 0x00000000); 6685 /* Memory management */ 6686 register_low_BATs(env); 6687 register_high_BATs(env); 6688 register_74xx_soft_tlb(env, 128, 2); 6689 init_excp_7450(env); 6690 env->dcache_line_size = 32; 6691 env->icache_line_size = 32; 6692 /* Allocate hardware IRQ controller */ 6693 ppc6xx_irq_init(env_archcpu(env)); 6694 } 6695 6696 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 6697 { 6698 DeviceClass *dc = DEVICE_CLASS(oc); 6699 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6700 6701 dc->desc = "PowerPC e600"; 6702 pcc->init_proc = init_proc_e600; 6703 pcc->check_pow = check_pow_hid0_74xx; 6704 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6705 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6706 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6707 PPC_FLOAT_STFIWX | 6708 PPC_CACHE | PPC_CACHE_ICBI | 6709 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6710 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6711 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6712 PPC_MEM_TLBIA | PPC_74xx_TLB | 6713 PPC_SEGMENT | PPC_EXTERN | 6714 PPC_ALTIVEC; 6715 pcc->insns_flags2 = PPC_NONE; 6716 pcc->msr_mask = (1ull << MSR_VR) | 6717 (1ull << MSR_POW) | 6718 (1ull << MSR_ILE) | 6719 (1ull << MSR_EE) | 6720 (1ull << MSR_PR) | 6721 (1ull << MSR_FP) | 6722 (1ull << MSR_ME) | 6723 (1ull << MSR_FE0) | 6724 (1ull << MSR_SE) | 6725 (1ull << MSR_DE) | 6726 (1ull << MSR_FE1) | 6727 (1ull << MSR_EP) | 6728 (1ull << MSR_IR) | 6729 (1ull << MSR_DR) | 6730 (1ull << MSR_PMM) | 6731 (1ull << MSR_RI) | 6732 (1ull << MSR_LE); 6733 pcc->mmu_model = POWERPC_MMU_32B; 6734 #if defined(CONFIG_SOFTMMU) 6735 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6736 #endif 6737 pcc->excp_model = POWERPC_EXCP_74xx; 6738 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6739 pcc->bfd_mach = bfd_mach_ppc_7400; 6740 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6741 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6742 POWERPC_FLAG_BUS_CLK; 6743 } 6744 6745 #if defined(TARGET_PPC64) 6746 #if defined(CONFIG_USER_ONLY) 6747 #define POWERPC970_HID5_INIT 0x00000080 6748 #else 6749 #define POWERPC970_HID5_INIT 0x00000000 6750 #endif 6751 6752 static int check_pow_970(CPUPPCState *env) 6753 { 6754 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6755 return 1; 6756 } 6757 6758 return 0; 6759 } 6760 6761 static void register_970_hid_sprs(CPUPPCState *env) 6762 { 6763 /* Hardware implementation registers */ 6764 /* XXX : not implemented */ 6765 spr_register(env, SPR_HID0, "HID0", 6766 SPR_NOACCESS, SPR_NOACCESS, 6767 &spr_read_generic, &spr_write_clear, 6768 0x60000000); 6769 spr_register(env, SPR_HID1, "HID1", 6770 SPR_NOACCESS, SPR_NOACCESS, 6771 &spr_read_generic, &spr_write_generic, 6772 0x00000000); 6773 spr_register(env, SPR_970_HID5, "HID5", 6774 SPR_NOACCESS, SPR_NOACCESS, 6775 &spr_read_generic, &spr_write_generic, 6776 POWERPC970_HID5_INIT); 6777 } 6778 6779 static void register_970_hior_sprs(CPUPPCState *env) 6780 { 6781 spr_register(env, SPR_HIOR, "SPR_HIOR", 6782 SPR_NOACCESS, SPR_NOACCESS, 6783 &spr_read_hior, &spr_write_hior, 6784 0x00000000); 6785 } 6786 6787 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6788 { 6789 spr_register(env, SPR_CTRL, "SPR_CTRL", 6790 SPR_NOACCESS, SPR_NOACCESS, 6791 SPR_NOACCESS, &spr_write_generic, 6792 0x00000000); 6793 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6794 &spr_read_ureg, SPR_NOACCESS, 6795 &spr_read_ureg, SPR_NOACCESS, 6796 0x00000000); 6797 } 6798 6799 static void register_book3s_altivec_sprs(CPUPPCState *env) 6800 { 6801 if (!(env->insns_flags & PPC_ALTIVEC)) { 6802 return; 6803 } 6804 6805 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6806 &spr_read_generic, &spr_write_generic, 6807 &spr_read_generic, &spr_write_generic, 6808 KVM_REG_PPC_VRSAVE, 0x00000000); 6809 6810 } 6811 6812 static void register_book3s_dbg_sprs(CPUPPCState *env) 6813 { 6814 /* 6815 * TODO: different specs define different scopes for these, 6816 * will have to address this: 6817 * 970: super/write and super/read 6818 * powerisa 2.03..2.04: hypv/write and super/read. 6819 * powerisa 2.05 and newer: hypv/write and hypv/read. 6820 */ 6821 spr_register_kvm(env, SPR_DABR, "DABR", 6822 SPR_NOACCESS, SPR_NOACCESS, 6823 &spr_read_generic, &spr_write_generic, 6824 KVM_REG_PPC_DABR, 0x00000000); 6825 spr_register_kvm(env, SPR_DABRX, "DABRX", 6826 SPR_NOACCESS, SPR_NOACCESS, 6827 &spr_read_generic, &spr_write_generic, 6828 KVM_REG_PPC_DABRX, 0x00000000); 6829 } 6830 6831 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6832 { 6833 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6834 SPR_NOACCESS, SPR_NOACCESS, 6835 SPR_NOACCESS, SPR_NOACCESS, 6836 &spr_read_generic, &spr_write_generic, 6837 KVM_REG_PPC_DAWR, 0x00000000); 6838 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6839 SPR_NOACCESS, SPR_NOACCESS, 6840 SPR_NOACCESS, SPR_NOACCESS, 6841 &spr_read_generic, &spr_write_generic, 6842 KVM_REG_PPC_DAWRX, 0x00000000); 6843 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6844 SPR_NOACCESS, SPR_NOACCESS, 6845 SPR_NOACCESS, SPR_NOACCESS, 6846 &spr_read_generic, &spr_write_generic, 6847 KVM_REG_PPC_CIABR, 0x00000000); 6848 } 6849 6850 static void register_970_dbg_sprs(CPUPPCState *env) 6851 { 6852 /* Breakpoints */ 6853 spr_register(env, SPR_IABR, "IABR", 6854 SPR_NOACCESS, SPR_NOACCESS, 6855 &spr_read_generic, &spr_write_generic, 6856 0x00000000); 6857 } 6858 6859 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6860 { 6861 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6862 SPR_NOACCESS, SPR_NOACCESS, 6863 &spr_read_generic, &spr_write_generic, 6864 KVM_REG_PPC_MMCR0, 0x00000000); 6865 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6866 SPR_NOACCESS, SPR_NOACCESS, 6867 &spr_read_generic, &spr_write_generic, 6868 KVM_REG_PPC_MMCR1, 0x00000000); 6869 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6870 SPR_NOACCESS, SPR_NOACCESS, 6871 &spr_read_generic, &spr_write_generic, 6872 KVM_REG_PPC_MMCRA, 0x00000000); 6873 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6874 SPR_NOACCESS, SPR_NOACCESS, 6875 &spr_read_generic, &spr_write_generic, 6876 KVM_REG_PPC_PMC1, 0x00000000); 6877 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6878 SPR_NOACCESS, SPR_NOACCESS, 6879 &spr_read_generic, &spr_write_generic, 6880 KVM_REG_PPC_PMC2, 0x00000000); 6881 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6882 SPR_NOACCESS, SPR_NOACCESS, 6883 &spr_read_generic, &spr_write_generic, 6884 KVM_REG_PPC_PMC3, 0x00000000); 6885 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6886 SPR_NOACCESS, SPR_NOACCESS, 6887 &spr_read_generic, &spr_write_generic, 6888 KVM_REG_PPC_PMC4, 0x00000000); 6889 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6890 SPR_NOACCESS, SPR_NOACCESS, 6891 &spr_read_generic, &spr_write_generic, 6892 KVM_REG_PPC_PMC5, 0x00000000); 6893 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6894 SPR_NOACCESS, SPR_NOACCESS, 6895 &spr_read_generic, &spr_write_generic, 6896 KVM_REG_PPC_PMC6, 0x00000000); 6897 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6898 SPR_NOACCESS, SPR_NOACCESS, 6899 &spr_read_generic, &spr_write_generic, 6900 KVM_REG_PPC_SIAR, 0x00000000); 6901 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6902 SPR_NOACCESS, SPR_NOACCESS, 6903 &spr_read_generic, &spr_write_generic, 6904 KVM_REG_PPC_SDAR, 0x00000000); 6905 } 6906 6907 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6908 { 6909 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6910 &spr_read_ureg, SPR_NOACCESS, 6911 &spr_read_ureg, &spr_write_ureg, 6912 0x00000000); 6913 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6914 &spr_read_ureg, SPR_NOACCESS, 6915 &spr_read_ureg, &spr_write_ureg, 6916 0x00000000); 6917 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6918 &spr_read_ureg, SPR_NOACCESS, 6919 &spr_read_ureg, &spr_write_ureg, 6920 0x00000000); 6921 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6922 &spr_read_ureg, SPR_NOACCESS, 6923 &spr_read_ureg, &spr_write_ureg, 6924 0x00000000); 6925 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6926 &spr_read_ureg, SPR_NOACCESS, 6927 &spr_read_ureg, &spr_write_ureg, 6928 0x00000000); 6929 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6930 &spr_read_ureg, SPR_NOACCESS, 6931 &spr_read_ureg, &spr_write_ureg, 6932 0x00000000); 6933 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6934 &spr_read_ureg, SPR_NOACCESS, 6935 &spr_read_ureg, &spr_write_ureg, 6936 0x00000000); 6937 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6938 &spr_read_ureg, SPR_NOACCESS, 6939 &spr_read_ureg, &spr_write_ureg, 6940 0x00000000); 6941 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6942 &spr_read_ureg, SPR_NOACCESS, 6943 &spr_read_ureg, &spr_write_ureg, 6944 0x00000000); 6945 spr_register(env, SPR_POWER_USIAR, "USIAR", 6946 &spr_read_ureg, SPR_NOACCESS, 6947 &spr_read_ureg, &spr_write_ureg, 6948 0x00000000); 6949 spr_register(env, SPR_POWER_USDAR, "USDAR", 6950 &spr_read_ureg, SPR_NOACCESS, 6951 &spr_read_ureg, &spr_write_ureg, 6952 0x00000000); 6953 } 6954 6955 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6956 { 6957 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6958 SPR_NOACCESS, SPR_NOACCESS, 6959 &spr_read_generic, &spr_write_generic, 6960 KVM_REG_PPC_PMC7, 0x00000000); 6961 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6962 SPR_NOACCESS, SPR_NOACCESS, 6963 &spr_read_generic, &spr_write_generic, 6964 KVM_REG_PPC_PMC8, 0x00000000); 6965 } 6966 6967 static void register_970_pmu_user_sprs(CPUPPCState *env) 6968 { 6969 spr_register(env, SPR_970_UPMC7, "UPMC7", 6970 &spr_read_ureg, SPR_NOACCESS, 6971 &spr_read_ureg, &spr_write_ureg, 6972 0x00000000); 6973 spr_register(env, SPR_970_UPMC8, "UPMC8", 6974 &spr_read_ureg, SPR_NOACCESS, 6975 &spr_read_ureg, &spr_write_ureg, 6976 0x00000000); 6977 } 6978 6979 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6980 { 6981 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6982 SPR_NOACCESS, SPR_NOACCESS, 6983 &spr_read_generic, &spr_write_generic, 6984 KVM_REG_PPC_MMCR2, 0x00000000); 6985 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6986 SPR_NOACCESS, SPR_NOACCESS, 6987 &spr_read_generic, &spr_write_generic, 6988 KVM_REG_PPC_MMCRS, 0x00000000); 6989 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 6990 SPR_NOACCESS, SPR_NOACCESS, 6991 &spr_read_generic, &spr_write_generic, 6992 KVM_REG_PPC_SIER, 0x00000000); 6993 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 6994 SPR_NOACCESS, SPR_NOACCESS, 6995 &spr_read_generic, &spr_write_generic, 6996 KVM_REG_PPC_SPMC1, 0x00000000); 6997 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 6998 SPR_NOACCESS, SPR_NOACCESS, 6999 &spr_read_generic, &spr_write_generic, 7000 KVM_REG_PPC_SPMC2, 0x00000000); 7001 spr_register_kvm(env, SPR_TACR, "TACR", 7002 SPR_NOACCESS, SPR_NOACCESS, 7003 &spr_read_generic, &spr_write_generic, 7004 KVM_REG_PPC_TACR, 0x00000000); 7005 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 7006 SPR_NOACCESS, SPR_NOACCESS, 7007 &spr_read_generic, &spr_write_generic, 7008 KVM_REG_PPC_TCSCR, 0x00000000); 7009 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 7010 SPR_NOACCESS, SPR_NOACCESS, 7011 &spr_read_generic, &spr_write_generic, 7012 KVM_REG_PPC_CSIGR, 0x00000000); 7013 } 7014 7015 static void register_power8_pmu_user_sprs(CPUPPCState *env) 7016 { 7017 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 7018 &spr_read_ureg, SPR_NOACCESS, 7019 &spr_read_ureg, &spr_write_ureg, 7020 0x00000000); 7021 spr_register(env, SPR_POWER_USIER, "USIER", 7022 &spr_read_generic, SPR_NOACCESS, 7023 &spr_read_generic, &spr_write_generic, 7024 0x00000000); 7025 } 7026 7027 static void register_power5p_ear_sprs(CPUPPCState *env) 7028 { 7029 /* External access control */ 7030 spr_register(env, SPR_EAR, "EAR", 7031 SPR_NOACCESS, SPR_NOACCESS, 7032 &spr_read_generic, &spr_write_generic, 7033 0x00000000); 7034 } 7035 7036 static void register_power5p_tb_sprs(CPUPPCState *env) 7037 { 7038 /* TBU40 (High 40 bits of the Timebase register */ 7039 spr_register_hv(env, SPR_TBU40, "TBU40", 7040 SPR_NOACCESS, SPR_NOACCESS, 7041 SPR_NOACCESS, SPR_NOACCESS, 7042 SPR_NOACCESS, &spr_write_tbu40, 7043 0x00000000); 7044 } 7045 7046 static void register_970_lpar_sprs(CPUPPCState *env) 7047 { 7048 #if !defined(CONFIG_USER_ONLY) 7049 /* 7050 * PPC970: HID4 covers things later controlled by the LPCR and 7051 * RMOR in later CPUs, but with a different encoding. We only 7052 * support the 970 in "Apple mode" which has all hypervisor 7053 * facilities disabled by strapping, so we can basically just 7054 * ignore it 7055 */ 7056 spr_register(env, SPR_970_HID4, "HID4", 7057 SPR_NOACCESS, SPR_NOACCESS, 7058 &spr_read_generic, &spr_write_generic, 7059 0x00000000); 7060 #endif 7061 } 7062 7063 static void register_power5p_lpar_sprs(CPUPPCState *env) 7064 { 7065 #if !defined(CONFIG_USER_ONLY) 7066 /* Logical partitionning */ 7067 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 7068 SPR_NOACCESS, SPR_NOACCESS, 7069 SPR_NOACCESS, SPR_NOACCESS, 7070 &spr_read_generic, &spr_write_lpcr, 7071 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 7072 spr_register_hv(env, SPR_HDEC, "HDEC", 7073 SPR_NOACCESS, SPR_NOACCESS, 7074 SPR_NOACCESS, SPR_NOACCESS, 7075 &spr_read_hdecr, &spr_write_hdecr, 0); 7076 #endif 7077 } 7078 7079 static void register_book3s_ids_sprs(CPUPPCState *env) 7080 { 7081 /* FIXME: Will need to deal with thread vs core only SPRs */ 7082 7083 /* Processor identification */ 7084 spr_register_hv(env, SPR_PIR, "PIR", 7085 SPR_NOACCESS, SPR_NOACCESS, 7086 &spr_read_generic, SPR_NOACCESS, 7087 &spr_read_generic, NULL, 7088 0x00000000); 7089 spr_register_hv(env, SPR_HID0, "HID0", 7090 SPR_NOACCESS, SPR_NOACCESS, 7091 SPR_NOACCESS, SPR_NOACCESS, 7092 &spr_read_generic, &spr_write_generic, 7093 0x00000000); 7094 spr_register_hv(env, SPR_TSCR, "TSCR", 7095 SPR_NOACCESS, SPR_NOACCESS, 7096 SPR_NOACCESS, SPR_NOACCESS, 7097 &spr_read_generic, &spr_write_generic, 7098 0x00000000); 7099 spr_register_hv(env, SPR_HMER, "HMER", 7100 SPR_NOACCESS, SPR_NOACCESS, 7101 SPR_NOACCESS, SPR_NOACCESS, 7102 &spr_read_generic, &spr_write_hmer, 7103 0x00000000); 7104 spr_register_hv(env, SPR_HMEER, "HMEER", 7105 SPR_NOACCESS, SPR_NOACCESS, 7106 SPR_NOACCESS, SPR_NOACCESS, 7107 &spr_read_generic, &spr_write_generic, 7108 0x00000000); 7109 spr_register_hv(env, SPR_TFMR, "TFMR", 7110 SPR_NOACCESS, SPR_NOACCESS, 7111 SPR_NOACCESS, SPR_NOACCESS, 7112 &spr_read_generic, &spr_write_generic, 7113 0x00000000); 7114 spr_register_hv(env, SPR_LPIDR, "LPIDR", 7115 SPR_NOACCESS, SPR_NOACCESS, 7116 SPR_NOACCESS, SPR_NOACCESS, 7117 &spr_read_generic, &spr_write_lpidr, 7118 0x00000000); 7119 spr_register_hv(env, SPR_HFSCR, "HFSCR", 7120 SPR_NOACCESS, SPR_NOACCESS, 7121 SPR_NOACCESS, SPR_NOACCESS, 7122 &spr_read_generic, &spr_write_generic, 7123 0x00000000); 7124 spr_register_hv(env, SPR_MMCRC, "MMCRC", 7125 SPR_NOACCESS, SPR_NOACCESS, 7126 SPR_NOACCESS, SPR_NOACCESS, 7127 &spr_read_generic, &spr_write_generic, 7128 0x00000000); 7129 spr_register_hv(env, SPR_MMCRH, "MMCRH", 7130 SPR_NOACCESS, SPR_NOACCESS, 7131 SPR_NOACCESS, SPR_NOACCESS, 7132 &spr_read_generic, &spr_write_generic, 7133 0x00000000); 7134 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 7135 SPR_NOACCESS, SPR_NOACCESS, 7136 SPR_NOACCESS, SPR_NOACCESS, 7137 &spr_read_generic, &spr_write_generic, 7138 0x00000000); 7139 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 7140 SPR_NOACCESS, SPR_NOACCESS, 7141 SPR_NOACCESS, SPR_NOACCESS, 7142 &spr_read_generic, &spr_write_generic, 7143 0x00000000); 7144 spr_register_hv(env, SPR_HSRR0, "HSRR0", 7145 SPR_NOACCESS, SPR_NOACCESS, 7146 SPR_NOACCESS, SPR_NOACCESS, 7147 &spr_read_generic, &spr_write_generic, 7148 0x00000000); 7149 spr_register_hv(env, SPR_HSRR1, "HSRR1", 7150 SPR_NOACCESS, SPR_NOACCESS, 7151 SPR_NOACCESS, SPR_NOACCESS, 7152 &spr_read_generic, &spr_write_generic, 7153 0x00000000); 7154 spr_register_hv(env, SPR_HDAR, "HDAR", 7155 SPR_NOACCESS, SPR_NOACCESS, 7156 SPR_NOACCESS, SPR_NOACCESS, 7157 &spr_read_generic, &spr_write_generic, 7158 0x00000000); 7159 spr_register_hv(env, SPR_HDSISR, "HDSISR", 7160 SPR_NOACCESS, SPR_NOACCESS, 7161 SPR_NOACCESS, SPR_NOACCESS, 7162 &spr_read_generic, &spr_write_generic, 7163 0x00000000); 7164 spr_register_hv(env, SPR_HRMOR, "HRMOR", 7165 SPR_NOACCESS, SPR_NOACCESS, 7166 SPR_NOACCESS, SPR_NOACCESS, 7167 &spr_read_generic, &spr_write_generic, 7168 0x00000000); 7169 } 7170 7171 static void register_rmor_sprs(CPUPPCState *env) 7172 { 7173 spr_register_hv(env, SPR_RMOR, "RMOR", 7174 SPR_NOACCESS, SPR_NOACCESS, 7175 SPR_NOACCESS, SPR_NOACCESS, 7176 &spr_read_generic, &spr_write_generic, 7177 0x00000000); 7178 } 7179 7180 static void register_power8_ids_sprs(CPUPPCState *env) 7181 { 7182 /* Thread identification */ 7183 spr_register(env, SPR_TIR, "TIR", 7184 SPR_NOACCESS, SPR_NOACCESS, 7185 &spr_read_generic, SPR_NOACCESS, 7186 0x00000000); 7187 } 7188 7189 static void register_book3s_purr_sprs(CPUPPCState *env) 7190 { 7191 #if !defined(CONFIG_USER_ONLY) 7192 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 7193 spr_register_kvm_hv(env, SPR_PURR, "PURR", 7194 &spr_read_purr, SPR_NOACCESS, 7195 &spr_read_purr, SPR_NOACCESS, 7196 &spr_read_purr, &spr_write_purr, 7197 KVM_REG_PPC_PURR, 0x00000000); 7198 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 7199 &spr_read_purr, SPR_NOACCESS, 7200 &spr_read_purr, SPR_NOACCESS, 7201 &spr_read_purr, &spr_write_purr, 7202 KVM_REG_PPC_SPURR, 0x00000000); 7203 #endif 7204 } 7205 7206 static void register_power6_dbg_sprs(CPUPPCState *env) 7207 { 7208 #if !defined(CONFIG_USER_ONLY) 7209 spr_register(env, SPR_CFAR, "SPR_CFAR", 7210 SPR_NOACCESS, SPR_NOACCESS, 7211 &spr_read_cfar, &spr_write_cfar, 7212 0x00000000); 7213 #endif 7214 } 7215 7216 static void register_power5p_common_sprs(CPUPPCState *env) 7217 { 7218 spr_register_kvm(env, SPR_PPR, "PPR", 7219 &spr_read_generic, &spr_write_generic, 7220 &spr_read_generic, &spr_write_generic, 7221 KVM_REG_PPC_PPR, 0x00000000); 7222 } 7223 7224 static void register_power6_common_sprs(CPUPPCState *env) 7225 { 7226 #if !defined(CONFIG_USER_ONLY) 7227 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 7228 SPR_NOACCESS, SPR_NOACCESS, 7229 &spr_read_generic, &spr_write_generic, 7230 KVM_REG_PPC_DSCR, 0x00000000); 7231 #endif 7232 /* 7233 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 7234 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 7235 */ 7236 spr_register_hv(env, SPR_PCR, "PCR", 7237 SPR_NOACCESS, SPR_NOACCESS, 7238 SPR_NOACCESS, SPR_NOACCESS, 7239 &spr_read_generic, &spr_write_pcr, 7240 0x00000000); 7241 } 7242 7243 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 7244 { 7245 spr_register_kvm(env, SPR_TAR, "TAR", 7246 &spr_read_tar, &spr_write_tar, 7247 &spr_read_generic, &spr_write_generic, 7248 KVM_REG_PPC_TAR, 0x00000000); 7249 } 7250 7251 static void register_power8_tm_sprs(CPUPPCState *env) 7252 { 7253 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 7254 &spr_read_tm, &spr_write_tm, 7255 &spr_read_tm, &spr_write_tm, 7256 KVM_REG_PPC_TFHAR, 0x00000000); 7257 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 7258 &spr_read_tm, &spr_write_tm, 7259 &spr_read_tm, &spr_write_tm, 7260 KVM_REG_PPC_TFIAR, 0x00000000); 7261 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 7262 &spr_read_tm, &spr_write_tm, 7263 &spr_read_tm, &spr_write_tm, 7264 KVM_REG_PPC_TEXASR, 0x00000000); 7265 spr_register(env, SPR_TEXASRU, "TEXASRU", 7266 &spr_read_tm_upper32, &spr_write_tm_upper32, 7267 &spr_read_tm_upper32, &spr_write_tm_upper32, 7268 0x00000000); 7269 } 7270 7271 static void register_power8_ebb_sprs(CPUPPCState *env) 7272 { 7273 spr_register(env, SPR_BESCRS, "BESCRS", 7274 &spr_read_ebb, &spr_write_ebb, 7275 &spr_read_generic, &spr_write_generic, 7276 0x00000000); 7277 spr_register(env, SPR_BESCRSU, "BESCRSU", 7278 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7279 &spr_read_prev_upper32, &spr_write_prev_upper32, 7280 0x00000000); 7281 spr_register(env, SPR_BESCRR, "BESCRR", 7282 &spr_read_ebb, &spr_write_ebb, 7283 &spr_read_generic, &spr_write_generic, 7284 0x00000000); 7285 spr_register(env, SPR_BESCRRU, "BESCRRU", 7286 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7287 &spr_read_prev_upper32, &spr_write_prev_upper32, 7288 0x00000000); 7289 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 7290 &spr_read_ebb, &spr_write_ebb, 7291 &spr_read_generic, &spr_write_generic, 7292 KVM_REG_PPC_EBBHR, 0x00000000); 7293 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 7294 &spr_read_ebb, &spr_write_ebb, 7295 &spr_read_generic, &spr_write_generic, 7296 KVM_REG_PPC_EBBRR, 0x00000000); 7297 spr_register_kvm(env, SPR_BESCR, "BESCR", 7298 &spr_read_ebb, &spr_write_ebb, 7299 &spr_read_generic, &spr_write_generic, 7300 KVM_REG_PPC_BESCR, 0x00000000); 7301 } 7302 7303 /* Virtual Time Base */ 7304 static void register_vtb_sprs(CPUPPCState *env) 7305 { 7306 spr_register_kvm_hv(env, SPR_VTB, "VTB", 7307 SPR_NOACCESS, SPR_NOACCESS, 7308 &spr_read_vtb, SPR_NOACCESS, 7309 &spr_read_vtb, &spr_write_vtb, 7310 KVM_REG_PPC_VTB, 0x00000000); 7311 } 7312 7313 static void register_power8_fscr_sprs(CPUPPCState *env) 7314 { 7315 #if defined(CONFIG_USER_ONLY) 7316 target_ulong initval = 1ULL << FSCR_TAR; 7317 #else 7318 target_ulong initval = 0; 7319 #endif 7320 spr_register_kvm(env, SPR_FSCR, "FSCR", 7321 SPR_NOACCESS, SPR_NOACCESS, 7322 &spr_read_generic, &spr_write_generic, 7323 KVM_REG_PPC_FSCR, initval); 7324 } 7325 7326 static void register_power8_pspb_sprs(CPUPPCState *env) 7327 { 7328 spr_register_kvm(env, SPR_PSPB, "PSPB", 7329 SPR_NOACCESS, SPR_NOACCESS, 7330 &spr_read_generic, &spr_write_generic32, 7331 KVM_REG_PPC_PSPB, 0); 7332 } 7333 7334 static void register_power8_dpdes_sprs(CPUPPCState *env) 7335 { 7336 #if !defined(CONFIG_USER_ONLY) 7337 /* Directed Privileged Door-bell Exception State, used for IPI */ 7338 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 7339 SPR_NOACCESS, SPR_NOACCESS, 7340 &spr_read_dpdes, SPR_NOACCESS, 7341 &spr_read_dpdes, &spr_write_dpdes, 7342 KVM_REG_PPC_DPDES, 0x00000000); 7343 #endif 7344 } 7345 7346 static void register_power8_ic_sprs(CPUPPCState *env) 7347 { 7348 #if !defined(CONFIG_USER_ONLY) 7349 spr_register_hv(env, SPR_IC, "IC", 7350 SPR_NOACCESS, SPR_NOACCESS, 7351 &spr_read_generic, SPR_NOACCESS, 7352 &spr_read_generic, &spr_write_generic, 7353 0); 7354 #endif 7355 } 7356 7357 static void register_power8_book4_sprs(CPUPPCState *env) 7358 { 7359 /* Add a number of P8 book4 registers */ 7360 #if !defined(CONFIG_USER_ONLY) 7361 spr_register_kvm(env, SPR_ACOP, "ACOP", 7362 SPR_NOACCESS, SPR_NOACCESS, 7363 &spr_read_generic, &spr_write_generic, 7364 KVM_REG_PPC_ACOP, 0); 7365 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7366 SPR_NOACCESS, SPR_NOACCESS, 7367 &spr_read_generic, &spr_write_pidr, 7368 KVM_REG_PPC_PID, 0); 7369 spr_register_kvm(env, SPR_WORT, "WORT", 7370 SPR_NOACCESS, SPR_NOACCESS, 7371 &spr_read_generic, &spr_write_generic, 7372 KVM_REG_PPC_WORT, 0); 7373 #endif 7374 } 7375 7376 static void register_power7_book4_sprs(CPUPPCState *env) 7377 { 7378 /* Add a number of P7 book4 registers */ 7379 #if !defined(CONFIG_USER_ONLY) 7380 spr_register_kvm(env, SPR_ACOP, "ACOP", 7381 SPR_NOACCESS, SPR_NOACCESS, 7382 &spr_read_generic, &spr_write_generic, 7383 KVM_REG_PPC_ACOP, 0); 7384 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7385 SPR_NOACCESS, SPR_NOACCESS, 7386 &spr_read_generic, &spr_write_generic, 7387 KVM_REG_PPC_PID, 0); 7388 #endif 7389 } 7390 7391 static void register_power8_rpr_sprs(CPUPPCState *env) 7392 { 7393 #if !defined(CONFIG_USER_ONLY) 7394 spr_register_hv(env, SPR_RPR, "RPR", 7395 SPR_NOACCESS, SPR_NOACCESS, 7396 SPR_NOACCESS, SPR_NOACCESS, 7397 &spr_read_generic, &spr_write_generic, 7398 0x00000103070F1F3F); 7399 #endif 7400 } 7401 7402 static void register_power9_mmu_sprs(CPUPPCState *env) 7403 { 7404 #if !defined(CONFIG_USER_ONLY) 7405 /* Partition Table Control */ 7406 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 7407 SPR_NOACCESS, SPR_NOACCESS, 7408 SPR_NOACCESS, SPR_NOACCESS, 7409 &spr_read_generic, &spr_write_ptcr, 7410 KVM_REG_PPC_PTCR, 0x00000000); 7411 /* Address Segment Descriptor Register */ 7412 spr_register_hv(env, SPR_ASDR, "ASDR", 7413 SPR_NOACCESS, SPR_NOACCESS, 7414 SPR_NOACCESS, SPR_NOACCESS, 7415 &spr_read_generic, &spr_write_generic, 7416 0x0000000000000000); 7417 #endif 7418 } 7419 7420 static void init_proc_book3s_common(CPUPPCState *env) 7421 { 7422 register_ne_601_sprs(env); 7423 register_tbl(env); 7424 register_usprg3_sprs(env); 7425 register_book3s_altivec_sprs(env); 7426 register_book3s_pmu_sup_sprs(env); 7427 register_book3s_pmu_user_sprs(env); 7428 register_book3s_ctrl_sprs(env); 7429 /* 7430 * Can't find information on what this should be on reset. This 7431 * value is the one used by 74xx processors. 7432 */ 7433 vscr_init(env, 0x00010000); 7434 } 7435 7436 static void init_proc_970(CPUPPCState *env) 7437 { 7438 /* Common Registers */ 7439 init_proc_book3s_common(env); 7440 register_sdr1_sprs(env); 7441 register_book3s_dbg_sprs(env); 7442 7443 /* 970 Specific Registers */ 7444 register_970_hid_sprs(env); 7445 register_970_hior_sprs(env); 7446 register_low_BATs(env); 7447 register_970_pmu_sup_sprs(env); 7448 register_970_pmu_user_sprs(env); 7449 register_970_lpar_sprs(env); 7450 register_970_dbg_sprs(env); 7451 7452 /* env variables */ 7453 env->dcache_line_size = 128; 7454 env->icache_line_size = 128; 7455 7456 /* Allocate hardware IRQ controller */ 7457 init_excp_970(env); 7458 ppc970_irq_init(env_archcpu(env)); 7459 } 7460 7461 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 7462 { 7463 DeviceClass *dc = DEVICE_CLASS(oc); 7464 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7465 7466 dc->desc = "PowerPC 970"; 7467 pcc->init_proc = init_proc_970; 7468 pcc->check_pow = check_pow_970; 7469 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7470 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7471 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7472 PPC_FLOAT_STFIWX | 7473 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7474 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7475 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7476 PPC_64B | PPC_ALTIVEC | 7477 PPC_SEGMENT_64B | PPC_SLBI; 7478 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7479 pcc->msr_mask = (1ull << MSR_SF) | 7480 (1ull << MSR_VR) | 7481 (1ull << MSR_POW) | 7482 (1ull << MSR_EE) | 7483 (1ull << MSR_PR) | 7484 (1ull << MSR_FP) | 7485 (1ull << MSR_ME) | 7486 (1ull << MSR_FE0) | 7487 (1ull << MSR_SE) | 7488 (1ull << MSR_DE) | 7489 (1ull << MSR_FE1) | 7490 (1ull << MSR_IR) | 7491 (1ull << MSR_DR) | 7492 (1ull << MSR_PMM) | 7493 (1ull << MSR_RI); 7494 pcc->mmu_model = POWERPC_MMU_64B; 7495 #if defined(CONFIG_SOFTMMU) 7496 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7497 pcc->hash64_opts = &ppc_hash64_opts_basic; 7498 #endif 7499 pcc->excp_model = POWERPC_EXCP_970; 7500 pcc->bus_model = PPC_FLAGS_INPUT_970; 7501 pcc->bfd_mach = bfd_mach_ppc64; 7502 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7503 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7504 POWERPC_FLAG_BUS_CLK; 7505 pcc->l1_dcache_size = 0x8000; 7506 pcc->l1_icache_size = 0x10000; 7507 } 7508 7509 static void init_proc_power5plus(CPUPPCState *env) 7510 { 7511 /* Common Registers */ 7512 init_proc_book3s_common(env); 7513 register_sdr1_sprs(env); 7514 register_book3s_dbg_sprs(env); 7515 7516 /* POWER5+ Specific Registers */ 7517 register_970_hid_sprs(env); 7518 register_970_hior_sprs(env); 7519 register_low_BATs(env); 7520 register_970_pmu_sup_sprs(env); 7521 register_970_pmu_user_sprs(env); 7522 register_power5p_common_sprs(env); 7523 register_power5p_lpar_sprs(env); 7524 register_power5p_ear_sprs(env); 7525 register_power5p_tb_sprs(env); 7526 7527 /* env variables */ 7528 env->dcache_line_size = 128; 7529 env->icache_line_size = 128; 7530 7531 /* Allocate hardware IRQ controller */ 7532 init_excp_970(env); 7533 ppc970_irq_init(env_archcpu(env)); 7534 } 7535 7536 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 7537 { 7538 DeviceClass *dc = DEVICE_CLASS(oc); 7539 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7540 7541 dc->fw_name = "PowerPC,POWER5"; 7542 dc->desc = "POWER5+"; 7543 pcc->init_proc = init_proc_power5plus; 7544 pcc->check_pow = check_pow_970; 7545 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7546 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7547 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7548 PPC_FLOAT_STFIWX | 7549 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7550 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7551 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7552 PPC_64B | 7553 PPC_SEGMENT_64B | PPC_SLBI; 7554 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7555 pcc->msr_mask = (1ull << MSR_SF) | 7556 (1ull << MSR_VR) | 7557 (1ull << MSR_POW) | 7558 (1ull << MSR_EE) | 7559 (1ull << MSR_PR) | 7560 (1ull << MSR_FP) | 7561 (1ull << MSR_ME) | 7562 (1ull << MSR_FE0) | 7563 (1ull << MSR_SE) | 7564 (1ull << MSR_DE) | 7565 (1ull << MSR_FE1) | 7566 (1ull << MSR_IR) | 7567 (1ull << MSR_DR) | 7568 (1ull << MSR_PMM) | 7569 (1ull << MSR_RI); 7570 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 7571 LPCR_RMI | LPCR_HDICE; 7572 pcc->mmu_model = POWERPC_MMU_2_03; 7573 #if defined(CONFIG_SOFTMMU) 7574 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7575 pcc->hash64_opts = &ppc_hash64_opts_basic; 7576 pcc->lrg_decr_bits = 32; 7577 #endif 7578 pcc->excp_model = POWERPC_EXCP_970; 7579 pcc->bus_model = PPC_FLAGS_INPUT_970; 7580 pcc->bfd_mach = bfd_mach_ppc64; 7581 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7582 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7583 POWERPC_FLAG_BUS_CLK; 7584 pcc->l1_dcache_size = 0x8000; 7585 pcc->l1_icache_size = 0x10000; 7586 } 7587 7588 static void init_proc_POWER7(CPUPPCState *env) 7589 { 7590 /* Common Registers */ 7591 init_proc_book3s_common(env); 7592 register_sdr1_sprs(env); 7593 register_book3s_dbg_sprs(env); 7594 7595 /* POWER7 Specific Registers */ 7596 register_book3s_ids_sprs(env); 7597 register_rmor_sprs(env); 7598 register_amr_sprs(env); 7599 register_book3s_purr_sprs(env); 7600 register_power5p_common_sprs(env); 7601 register_power5p_lpar_sprs(env); 7602 register_power5p_ear_sprs(env); 7603 register_power5p_tb_sprs(env); 7604 register_power6_common_sprs(env); 7605 register_power6_dbg_sprs(env); 7606 register_power7_book4_sprs(env); 7607 7608 /* env variables */ 7609 env->dcache_line_size = 128; 7610 env->icache_line_size = 128; 7611 7612 /* Allocate hardware IRQ controller */ 7613 init_excp_POWER7(env); 7614 ppcPOWER7_irq_init(env_archcpu(env)); 7615 } 7616 7617 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 7618 { 7619 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 7620 return true; 7621 } 7622 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 7623 return true; 7624 } 7625 return false; 7626 } 7627 7628 static bool cpu_has_work_POWER7(CPUState *cs) 7629 { 7630 PowerPCCPU *cpu = POWERPC_CPU(cs); 7631 CPUPPCState *env = &cpu->env; 7632 7633 if (cs->halted) { 7634 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7635 return false; 7636 } 7637 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7638 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 7639 return true; 7640 } 7641 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7642 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 7643 return true; 7644 } 7645 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7646 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7647 return true; 7648 } 7649 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7650 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7651 return true; 7652 } 7653 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7654 return true; 7655 } 7656 return false; 7657 } else { 7658 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7659 } 7660 } 7661 7662 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 7663 { 7664 DeviceClass *dc = DEVICE_CLASS(oc); 7665 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7666 CPUClass *cc = CPU_CLASS(oc); 7667 7668 dc->fw_name = "PowerPC,POWER7"; 7669 dc->desc = "POWER7"; 7670 pcc->pvr_match = ppc_pvr_match_power7; 7671 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 7672 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7673 pcc->init_proc = init_proc_POWER7; 7674 pcc->check_pow = check_pow_nocheck; 7675 cc->has_work = cpu_has_work_POWER7; 7676 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7677 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7678 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7679 PPC_FLOAT_FRSQRTES | 7680 PPC_FLOAT_STFIWX | 7681 PPC_FLOAT_EXT | 7682 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7683 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7684 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7685 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7686 PPC_SEGMENT_64B | PPC_SLBI | 7687 PPC_POPCNTB | PPC_POPCNTWD | 7688 PPC_CILDST; 7689 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 7690 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7691 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7692 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 7693 PPC2_PM_ISA206; 7694 pcc->msr_mask = (1ull << MSR_SF) | 7695 (1ull << MSR_VR) | 7696 (1ull << MSR_VSX) | 7697 (1ull << MSR_EE) | 7698 (1ull << MSR_PR) | 7699 (1ull << MSR_FP) | 7700 (1ull << MSR_ME) | 7701 (1ull << MSR_FE0) | 7702 (1ull << MSR_SE) | 7703 (1ull << MSR_DE) | 7704 (1ull << MSR_FE1) | 7705 (1ull << MSR_IR) | 7706 (1ull << MSR_DR) | 7707 (1ull << MSR_PMM) | 7708 (1ull << MSR_RI) | 7709 (1ull << MSR_LE); 7710 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 7711 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7712 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 7713 LPCR_MER | LPCR_TC | 7714 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 7715 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 7716 pcc->mmu_model = POWERPC_MMU_2_06; 7717 #if defined(CONFIG_SOFTMMU) 7718 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7719 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7720 pcc->lrg_decr_bits = 32; 7721 #endif 7722 pcc->excp_model = POWERPC_EXCP_POWER7; 7723 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7724 pcc->bfd_mach = bfd_mach_ppc64; 7725 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7726 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7727 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7728 POWERPC_FLAG_VSX; 7729 pcc->l1_dcache_size = 0x8000; 7730 pcc->l1_icache_size = 0x8000; 7731 } 7732 7733 static void init_proc_POWER8(CPUPPCState *env) 7734 { 7735 /* Common Registers */ 7736 init_proc_book3s_common(env); 7737 register_sdr1_sprs(env); 7738 register_book3s_207_dbg_sprs(env); 7739 7740 /* POWER8 Specific Registers */ 7741 register_book3s_ids_sprs(env); 7742 register_rmor_sprs(env); 7743 register_amr_sprs(env); 7744 register_iamr_sprs(env); 7745 register_book3s_purr_sprs(env); 7746 register_power5p_common_sprs(env); 7747 register_power5p_lpar_sprs(env); 7748 register_power5p_ear_sprs(env); 7749 register_power5p_tb_sprs(env); 7750 register_power6_common_sprs(env); 7751 register_power6_dbg_sprs(env); 7752 register_power8_tce_address_control_sprs(env); 7753 register_power8_ids_sprs(env); 7754 register_power8_ebb_sprs(env); 7755 register_power8_fscr_sprs(env); 7756 register_power8_pmu_sup_sprs(env); 7757 register_power8_pmu_user_sprs(env); 7758 register_power8_tm_sprs(env); 7759 register_power8_pspb_sprs(env); 7760 register_power8_dpdes_sprs(env); 7761 register_vtb_sprs(env); 7762 register_power8_ic_sprs(env); 7763 register_power8_book4_sprs(env); 7764 register_power8_rpr_sprs(env); 7765 7766 /* env variables */ 7767 env->dcache_line_size = 128; 7768 env->icache_line_size = 128; 7769 7770 /* Allocate hardware IRQ controller */ 7771 init_excp_POWER8(env); 7772 ppcPOWER7_irq_init(env_archcpu(env)); 7773 } 7774 7775 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7776 { 7777 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7778 return true; 7779 } 7780 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7781 return true; 7782 } 7783 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7784 return true; 7785 } 7786 return false; 7787 } 7788 7789 static bool cpu_has_work_POWER8(CPUState *cs) 7790 { 7791 PowerPCCPU *cpu = POWERPC_CPU(cs); 7792 CPUPPCState *env = &cpu->env; 7793 7794 if (cs->halted) { 7795 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7796 return false; 7797 } 7798 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7799 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7800 return true; 7801 } 7802 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7803 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7804 return true; 7805 } 7806 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7807 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7808 return true; 7809 } 7810 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7811 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7812 return true; 7813 } 7814 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7815 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7816 return true; 7817 } 7818 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7819 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7820 return true; 7821 } 7822 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7823 return true; 7824 } 7825 return false; 7826 } else { 7827 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7828 } 7829 } 7830 7831 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7832 { 7833 DeviceClass *dc = DEVICE_CLASS(oc); 7834 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7835 CPUClass *cc = CPU_CLASS(oc); 7836 7837 dc->fw_name = "PowerPC,POWER8"; 7838 dc->desc = "POWER8"; 7839 pcc->pvr_match = ppc_pvr_match_power8; 7840 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7841 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7842 pcc->init_proc = init_proc_POWER8; 7843 pcc->check_pow = check_pow_nocheck; 7844 cc->has_work = cpu_has_work_POWER8; 7845 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7846 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7847 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7848 PPC_FLOAT_FRSQRTES | 7849 PPC_FLOAT_STFIWX | 7850 PPC_FLOAT_EXT | 7851 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7852 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7853 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7854 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7855 PPC_SEGMENT_64B | PPC_SLBI | 7856 PPC_POPCNTB | PPC_POPCNTWD | 7857 PPC_CILDST; 7858 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7859 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7860 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7861 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7862 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7863 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7864 PPC2_TM | PPC2_PM_ISA206; 7865 pcc->msr_mask = (1ull << MSR_SF) | 7866 (1ull << MSR_HV) | 7867 (1ull << MSR_TM) | 7868 (1ull << MSR_VR) | 7869 (1ull << MSR_VSX) | 7870 (1ull << MSR_EE) | 7871 (1ull << MSR_PR) | 7872 (1ull << MSR_FP) | 7873 (1ull << MSR_ME) | 7874 (1ull << MSR_FE0) | 7875 (1ull << MSR_SE) | 7876 (1ull << MSR_DE) | 7877 (1ull << MSR_FE1) | 7878 (1ull << MSR_IR) | 7879 (1ull << MSR_DR) | 7880 (1ull << MSR_PMM) | 7881 (1ull << MSR_RI) | 7882 (1ull << MSR_TS0) | 7883 (1ull << MSR_TS1) | 7884 (1ull << MSR_LE); 7885 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7886 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7887 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7888 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7889 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7890 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7891 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7892 pcc->mmu_model = POWERPC_MMU_2_07; 7893 #if defined(CONFIG_SOFTMMU) 7894 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7895 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7896 pcc->lrg_decr_bits = 32; 7897 pcc->n_host_threads = 8; 7898 #endif 7899 pcc->excp_model = POWERPC_EXCP_POWER8; 7900 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7901 pcc->bfd_mach = bfd_mach_ppc64; 7902 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7903 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7904 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7905 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7906 pcc->l1_dcache_size = 0x8000; 7907 pcc->l1_icache_size = 0x8000; 7908 } 7909 7910 #ifdef CONFIG_SOFTMMU 7911 /* 7912 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7913 * Encoded as array of int_32s in the form: 7914 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7915 * x -> AP encoding 7916 * y -> radix mode supported page size (encoded as a shift) 7917 */ 7918 static struct ppc_radix_page_info POWER9_radix_page_info = { 7919 .count = 4, 7920 .entries = { 7921 0x0000000c, /* 4K - enc: 0x0 */ 7922 0xa0000010, /* 64K - enc: 0x5 */ 7923 0x20000015, /* 2M - enc: 0x1 */ 7924 0x4000001e /* 1G - enc: 0x2 */ 7925 } 7926 }; 7927 #endif /* CONFIG_SOFTMMU */ 7928 7929 static void init_proc_POWER9(CPUPPCState *env) 7930 { 7931 /* Common Registers */ 7932 init_proc_book3s_common(env); 7933 register_book3s_207_dbg_sprs(env); 7934 7935 /* POWER8 Specific Registers */ 7936 register_book3s_ids_sprs(env); 7937 register_amr_sprs(env); 7938 register_iamr_sprs(env); 7939 register_book3s_purr_sprs(env); 7940 register_power5p_common_sprs(env); 7941 register_power5p_lpar_sprs(env); 7942 register_power5p_ear_sprs(env); 7943 register_power5p_tb_sprs(env); 7944 register_power6_common_sprs(env); 7945 register_power6_dbg_sprs(env); 7946 register_power8_tce_address_control_sprs(env); 7947 register_power8_ids_sprs(env); 7948 register_power8_ebb_sprs(env); 7949 register_power8_fscr_sprs(env); 7950 register_power8_pmu_sup_sprs(env); 7951 register_power8_pmu_user_sprs(env); 7952 register_power8_tm_sprs(env); 7953 register_power8_pspb_sprs(env); 7954 register_power8_dpdes_sprs(env); 7955 register_vtb_sprs(env); 7956 register_power8_ic_sprs(env); 7957 register_power8_book4_sprs(env); 7958 register_power8_rpr_sprs(env); 7959 register_power9_mmu_sprs(env); 7960 7961 /* POWER9 Specific registers */ 7962 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7963 spr_read_generic, spr_write_generic, 7964 KVM_REG_PPC_TIDR, 0); 7965 7966 /* FIXME: Filter fields properly based on privilege level */ 7967 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7968 spr_read_generic, spr_write_generic, 7969 KVM_REG_PPC_PSSCR, 0); 7970 7971 /* env variables */ 7972 env->dcache_line_size = 128; 7973 env->icache_line_size = 128; 7974 7975 /* Allocate hardware IRQ controller */ 7976 init_excp_POWER9(env); 7977 ppcPOWER9_irq_init(env_archcpu(env)); 7978 } 7979 7980 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7981 { 7982 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7983 return true; 7984 } 7985 return false; 7986 } 7987 7988 static bool cpu_has_work_POWER9(CPUState *cs) 7989 { 7990 PowerPCCPU *cpu = POWERPC_CPU(cs); 7991 CPUPPCState *env = &cpu->env; 7992 7993 if (cs->halted) { 7994 uint64_t psscr = env->spr[SPR_PSSCR]; 7995 7996 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7997 return false; 7998 } 7999 8000 /* If EC is clear, just return true on any pending interrupt */ 8001 if (!(psscr & PSSCR_EC)) { 8002 return true; 8003 } 8004 /* External Exception */ 8005 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8006 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8007 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8008 if (heic == 0 || !msr_hv || msr_pr) { 8009 return true; 8010 } 8011 } 8012 /* Decrementer Exception */ 8013 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8014 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8015 return true; 8016 } 8017 /* Machine Check or Hypervisor Maintenance Exception */ 8018 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8019 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8020 return true; 8021 } 8022 /* Privileged Doorbell Exception */ 8023 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8024 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8025 return true; 8026 } 8027 /* Hypervisor Doorbell Exception */ 8028 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8029 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8030 return true; 8031 } 8032 /* Hypervisor virtualization exception */ 8033 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8034 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8035 return true; 8036 } 8037 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8038 return true; 8039 } 8040 return false; 8041 } else { 8042 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8043 } 8044 } 8045 8046 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 8047 { 8048 DeviceClass *dc = DEVICE_CLASS(oc); 8049 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8050 CPUClass *cc = CPU_CLASS(oc); 8051 8052 dc->fw_name = "PowerPC,POWER9"; 8053 dc->desc = "POWER9"; 8054 pcc->pvr_match = ppc_pvr_match_power9; 8055 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 8056 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 8057 PCR_COMPAT_2_05; 8058 pcc->init_proc = init_proc_POWER9; 8059 pcc->check_pow = check_pow_nocheck; 8060 cc->has_work = cpu_has_work_POWER9; 8061 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8062 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8063 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8064 PPC_FLOAT_FRSQRTES | 8065 PPC_FLOAT_STFIWX | 8066 PPC_FLOAT_EXT | 8067 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8068 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8069 PPC_MEM_TLBSYNC | 8070 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8071 PPC_SEGMENT_64B | PPC_SLBI | 8072 PPC_POPCNTB | PPC_POPCNTWD | 8073 PPC_CILDST; 8074 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8075 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8076 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8077 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8078 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8079 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8080 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 8081 pcc->msr_mask = (1ull << MSR_SF) | 8082 (1ull << MSR_HV) | 8083 (1ull << MSR_TM) | 8084 (1ull << MSR_VR) | 8085 (1ull << MSR_VSX) | 8086 (1ull << MSR_EE) | 8087 (1ull << MSR_PR) | 8088 (1ull << MSR_FP) | 8089 (1ull << MSR_ME) | 8090 (1ull << MSR_FE0) | 8091 (1ull << MSR_SE) | 8092 (1ull << MSR_DE) | 8093 (1ull << MSR_FE1) | 8094 (1ull << MSR_IR) | 8095 (1ull << MSR_DR) | 8096 (1ull << MSR_PMM) | 8097 (1ull << MSR_RI) | 8098 (1ull << MSR_LE); 8099 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8100 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8101 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8102 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8103 LPCR_DEE | LPCR_OEE)) 8104 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8105 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8106 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8107 pcc->mmu_model = POWERPC_MMU_3_00; 8108 #if defined(CONFIG_SOFTMMU) 8109 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8110 /* segment page size remain the same */ 8111 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8112 pcc->radix_page_info = &POWER9_radix_page_info; 8113 pcc->lrg_decr_bits = 56; 8114 pcc->n_host_threads = 4; 8115 #endif 8116 pcc->excp_model = POWERPC_EXCP_POWER9; 8117 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8118 pcc->bfd_mach = bfd_mach_ppc64; 8119 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8120 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8121 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8122 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8123 pcc->l1_dcache_size = 0x8000; 8124 pcc->l1_icache_size = 0x8000; 8125 } 8126 8127 #ifdef CONFIG_SOFTMMU 8128 /* 8129 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 8130 * Encoded as array of int_32s in the form: 8131 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 8132 * x -> AP encoding 8133 * y -> radix mode supported page size (encoded as a shift) 8134 */ 8135 static struct ppc_radix_page_info POWER10_radix_page_info = { 8136 .count = 4, 8137 .entries = { 8138 0x0000000c, /* 4K - enc: 0x0 */ 8139 0xa0000010, /* 64K - enc: 0x5 */ 8140 0x20000015, /* 2M - enc: 0x1 */ 8141 0x4000001e /* 1G - enc: 0x2 */ 8142 } 8143 }; 8144 #endif /* CONFIG_SOFTMMU */ 8145 8146 static void init_proc_POWER10(CPUPPCState *env) 8147 { 8148 /* Common Registers */ 8149 init_proc_book3s_common(env); 8150 register_book3s_207_dbg_sprs(env); 8151 8152 /* POWER8 Specific Registers */ 8153 register_book3s_ids_sprs(env); 8154 register_amr_sprs(env); 8155 register_iamr_sprs(env); 8156 register_book3s_purr_sprs(env); 8157 register_power5p_common_sprs(env); 8158 register_power5p_lpar_sprs(env); 8159 register_power5p_ear_sprs(env); 8160 register_power6_common_sprs(env); 8161 register_power6_dbg_sprs(env); 8162 register_power8_tce_address_control_sprs(env); 8163 register_power8_ids_sprs(env); 8164 register_power8_ebb_sprs(env); 8165 register_power8_fscr_sprs(env); 8166 register_power8_pmu_sup_sprs(env); 8167 register_power8_pmu_user_sprs(env); 8168 register_power8_tm_sprs(env); 8169 register_power8_pspb_sprs(env); 8170 register_vtb_sprs(env); 8171 register_power8_ic_sprs(env); 8172 register_power8_book4_sprs(env); 8173 register_power8_rpr_sprs(env); 8174 register_power9_mmu_sprs(env); 8175 8176 /* FIXME: Filter fields properly based on privilege level */ 8177 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 8178 spr_read_generic, spr_write_generic, 8179 KVM_REG_PPC_PSSCR, 0); 8180 8181 /* env variables */ 8182 env->dcache_line_size = 128; 8183 env->icache_line_size = 128; 8184 8185 /* Allocate hardware IRQ controller */ 8186 init_excp_POWER10(env); 8187 ppcPOWER9_irq_init(env_archcpu(env)); 8188 } 8189 8190 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 8191 { 8192 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 8193 return true; 8194 } 8195 return false; 8196 } 8197 8198 static bool cpu_has_work_POWER10(CPUState *cs) 8199 { 8200 PowerPCCPU *cpu = POWERPC_CPU(cs); 8201 CPUPPCState *env = &cpu->env; 8202 8203 if (cs->halted) { 8204 uint64_t psscr = env->spr[SPR_PSSCR]; 8205 8206 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8207 return false; 8208 } 8209 8210 /* If EC is clear, just return true on any pending interrupt */ 8211 if (!(psscr & PSSCR_EC)) { 8212 return true; 8213 } 8214 /* External Exception */ 8215 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8216 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8217 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8218 if (heic == 0 || !msr_hv || msr_pr) { 8219 return true; 8220 } 8221 } 8222 /* Decrementer Exception */ 8223 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8224 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8225 return true; 8226 } 8227 /* Machine Check or Hypervisor Maintenance Exception */ 8228 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8229 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8230 return true; 8231 } 8232 /* Privileged Doorbell Exception */ 8233 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8234 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8235 return true; 8236 } 8237 /* Hypervisor Doorbell Exception */ 8238 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8239 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8240 return true; 8241 } 8242 /* Hypervisor virtualization exception */ 8243 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8244 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8245 return true; 8246 } 8247 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8248 return true; 8249 } 8250 return false; 8251 } else { 8252 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8253 } 8254 } 8255 8256 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 8257 { 8258 DeviceClass *dc = DEVICE_CLASS(oc); 8259 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8260 CPUClass *cc = CPU_CLASS(oc); 8261 8262 dc->fw_name = "PowerPC,POWER10"; 8263 dc->desc = "POWER10"; 8264 pcc->pvr_match = ppc_pvr_match_power10; 8265 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 8266 PCR_COMPAT_3_00; 8267 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 8268 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8269 pcc->init_proc = init_proc_POWER10; 8270 pcc->check_pow = check_pow_nocheck; 8271 cc->has_work = cpu_has_work_POWER10; 8272 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8273 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8274 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8275 PPC_FLOAT_FRSQRTES | 8276 PPC_FLOAT_STFIWX | 8277 PPC_FLOAT_EXT | 8278 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8279 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8280 PPC_MEM_TLBSYNC | 8281 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8282 PPC_SEGMENT_64B | PPC_SLBI | 8283 PPC_POPCNTB | PPC_POPCNTWD | 8284 PPC_CILDST; 8285 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8286 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8287 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8288 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8289 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8290 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8291 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 8292 pcc->msr_mask = (1ull << MSR_SF) | 8293 (1ull << MSR_HV) | 8294 (1ull << MSR_TM) | 8295 (1ull << MSR_VR) | 8296 (1ull << MSR_VSX) | 8297 (1ull << MSR_EE) | 8298 (1ull << MSR_PR) | 8299 (1ull << MSR_FP) | 8300 (1ull << MSR_ME) | 8301 (1ull << MSR_FE0) | 8302 (1ull << MSR_SE) | 8303 (1ull << MSR_DE) | 8304 (1ull << MSR_FE1) | 8305 (1ull << MSR_IR) | 8306 (1ull << MSR_DR) | 8307 (1ull << MSR_PMM) | 8308 (1ull << MSR_RI) | 8309 (1ull << MSR_LE); 8310 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8311 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8312 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8313 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8314 LPCR_DEE | LPCR_OEE)) 8315 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8316 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8317 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8318 pcc->mmu_model = POWERPC_MMU_3_00; 8319 #if defined(CONFIG_SOFTMMU) 8320 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8321 /* segment page size remain the same */ 8322 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8323 pcc->radix_page_info = &POWER10_radix_page_info; 8324 pcc->lrg_decr_bits = 56; 8325 #endif 8326 pcc->excp_model = POWERPC_EXCP_POWER10; 8327 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8328 pcc->bfd_mach = bfd_mach_ppc64; 8329 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8330 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8331 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8332 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8333 pcc->l1_dcache_size = 0x8000; 8334 pcc->l1_icache_size = 0x8000; 8335 } 8336 8337 #if !defined(CONFIG_USER_ONLY) 8338 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 8339 { 8340 CPUPPCState *env = &cpu->env; 8341 8342 cpu->vhyp = vhyp; 8343 8344 /* 8345 * With a virtual hypervisor mode we never allow the CPU to go 8346 * hypervisor mode itself 8347 */ 8348 env->msr_mask &= ~MSR_HVB; 8349 } 8350 8351 #endif /* !defined(CONFIG_USER_ONLY) */ 8352 8353 #endif /* defined(TARGET_PPC64) */ 8354 8355 /*****************************************************************************/ 8356 /* Generic CPU instantiation routine */ 8357 static void init_ppc_proc(PowerPCCPU *cpu) 8358 { 8359 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8360 CPUPPCState *env = &cpu->env; 8361 #if !defined(CONFIG_USER_ONLY) 8362 int i; 8363 8364 env->irq_inputs = NULL; 8365 /* Set all exception vectors to an invalid address */ 8366 for (i = 0; i < POWERPC_EXCP_NB; i++) { 8367 env->excp_vectors[i] = (target_ulong)(-1ULL); 8368 } 8369 env->ivor_mask = 0x00000000; 8370 env->ivpr_mask = 0x00000000; 8371 /* Default MMU definitions */ 8372 env->nb_BATs = 0; 8373 env->nb_tlb = 0; 8374 env->nb_ways = 0; 8375 env->tlb_type = TLB_NONE; 8376 #endif 8377 /* Register SPR common to all PowerPC implementations */ 8378 register_generic_sprs(env); 8379 spr_register(env, SPR_PVR, "PVR", 8380 /* Linux permits userspace to read PVR */ 8381 #if defined(CONFIG_LINUX_USER) 8382 &spr_read_generic, 8383 #else 8384 SPR_NOACCESS, 8385 #endif 8386 SPR_NOACCESS, 8387 &spr_read_generic, SPR_NOACCESS, 8388 pcc->pvr); 8389 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 8390 if (pcc->svr != POWERPC_SVR_NONE) { 8391 if (pcc->svr & POWERPC_SVR_E500) { 8392 spr_register(env, SPR_E500_SVR, "SVR", 8393 SPR_NOACCESS, SPR_NOACCESS, 8394 &spr_read_generic, SPR_NOACCESS, 8395 pcc->svr & ~POWERPC_SVR_E500); 8396 } else { 8397 spr_register(env, SPR_SVR, "SVR", 8398 SPR_NOACCESS, SPR_NOACCESS, 8399 &spr_read_generic, SPR_NOACCESS, 8400 pcc->svr); 8401 } 8402 } 8403 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 8404 (*pcc->init_proc)(env); 8405 8406 #if !defined(CONFIG_USER_ONLY) 8407 ppc_gdb_gen_spr_xml(cpu); 8408 #endif 8409 8410 /* MSR bits & flags consistency checks */ 8411 if (env->msr_mask & (1 << 25)) { 8412 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8413 case POWERPC_FLAG_SPE: 8414 case POWERPC_FLAG_VRE: 8415 break; 8416 default: 8417 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8418 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 8419 exit(1); 8420 } 8421 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8422 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8423 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 8424 exit(1); 8425 } 8426 if (env->msr_mask & (1 << 17)) { 8427 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8428 case POWERPC_FLAG_TGPR: 8429 case POWERPC_FLAG_CE: 8430 break; 8431 default: 8432 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8433 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 8434 exit(1); 8435 } 8436 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8437 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8438 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 8439 exit(1); 8440 } 8441 if (env->msr_mask & (1 << 10)) { 8442 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8443 POWERPC_FLAG_UBLE)) { 8444 case POWERPC_FLAG_SE: 8445 case POWERPC_FLAG_DWE: 8446 case POWERPC_FLAG_UBLE: 8447 break; 8448 default: 8449 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8450 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 8451 "POWERPC_FLAG_UBLE\n"); 8452 exit(1); 8453 } 8454 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8455 POWERPC_FLAG_UBLE)) { 8456 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8457 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 8458 "POWERPC_FLAG_UBLE\n"); 8459 exit(1); 8460 } 8461 if (env->msr_mask & (1 << 9)) { 8462 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8463 case POWERPC_FLAG_BE: 8464 case POWERPC_FLAG_DE: 8465 break; 8466 default: 8467 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8468 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 8469 exit(1); 8470 } 8471 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8472 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8473 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 8474 exit(1); 8475 } 8476 if (env->msr_mask & (1 << 2)) { 8477 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8478 case POWERPC_FLAG_PX: 8479 case POWERPC_FLAG_PMM: 8480 break; 8481 default: 8482 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8483 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 8484 exit(1); 8485 } 8486 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8487 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8488 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 8489 exit(1); 8490 } 8491 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 8492 fprintf(stderr, "PowerPC flags inconsistency\n" 8493 "Should define the time-base and decrementer clock source\n"); 8494 exit(1); 8495 } 8496 /* Allocate TLBs buffer when needed */ 8497 #if !defined(CONFIG_USER_ONLY) 8498 if (env->nb_tlb != 0) { 8499 int nb_tlb = env->nb_tlb; 8500 if (env->id_tlbs != 0) { 8501 nb_tlb *= 2; 8502 } 8503 switch (env->tlb_type) { 8504 case TLB_6XX: 8505 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 8506 break; 8507 case TLB_EMB: 8508 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 8509 break; 8510 case TLB_MAS: 8511 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 8512 break; 8513 } 8514 /* Pre-compute some useful values */ 8515 env->tlb_per_way = env->nb_tlb / env->nb_ways; 8516 } 8517 if (env->irq_inputs == NULL) { 8518 warn_report("no internal IRQ controller registered." 8519 " Attempt QEMU to crash very soon !"); 8520 } 8521 #endif 8522 if (env->check_pow == NULL) { 8523 warn_report("no power management check handler registered." 8524 " Attempt QEMU to crash very soon !"); 8525 } 8526 } 8527 8528 8529 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 8530 { 8531 CPUState *cs = CPU(dev); 8532 PowerPCCPU *cpu = POWERPC_CPU(dev); 8533 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8534 Error *local_err = NULL; 8535 8536 cpu_exec_realizefn(cs, &local_err); 8537 if (local_err != NULL) { 8538 error_propagate(errp, local_err); 8539 return; 8540 } 8541 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 8542 cpu->vcpu_id = cs->cpu_index; 8543 } 8544 8545 if (tcg_enabled()) { 8546 if (ppc_fixup_cpu(cpu) != 0) { 8547 error_setg(errp, "Unable to emulate selected CPU with TCG"); 8548 goto unrealize; 8549 } 8550 } 8551 8552 create_ppc_opcodes(cpu, &local_err); 8553 if (local_err != NULL) { 8554 error_propagate(errp, local_err); 8555 goto unrealize; 8556 } 8557 init_ppc_proc(cpu); 8558 8559 ppc_gdb_init(cs, pcc); 8560 qemu_init_vcpu(cs); 8561 8562 pcc->parent_realize(dev, errp); 8563 8564 return; 8565 8566 unrealize: 8567 cpu_exec_unrealizefn(cs); 8568 } 8569 8570 static void ppc_cpu_unrealize(DeviceState *dev) 8571 { 8572 PowerPCCPU *cpu = POWERPC_CPU(dev); 8573 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8574 8575 pcc->parent_unrealize(dev); 8576 8577 cpu_remove_sync(CPU(cpu)); 8578 8579 destroy_ppc_opcodes(cpu); 8580 } 8581 8582 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 8583 { 8584 ObjectClass *oc = (ObjectClass *)a; 8585 uint32_t pvr = *(uint32_t *)b; 8586 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8587 8588 /* -cpu host does a PVR lookup during construction */ 8589 if (unlikely(strcmp(object_class_get_name(oc), 8590 TYPE_HOST_POWERPC_CPU) == 0)) { 8591 return -1; 8592 } 8593 8594 return pcc->pvr == pvr ? 0 : -1; 8595 } 8596 8597 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 8598 { 8599 GSList *list, *item; 8600 PowerPCCPUClass *pcc = NULL; 8601 8602 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8603 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 8604 if (item != NULL) { 8605 pcc = POWERPC_CPU_CLASS(item->data); 8606 } 8607 g_slist_free(list); 8608 8609 return pcc; 8610 } 8611 8612 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 8613 { 8614 ObjectClass *oc = (ObjectClass *)a; 8615 uint32_t pvr = *(uint32_t *)b; 8616 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8617 8618 /* -cpu host does a PVR lookup during construction */ 8619 if (unlikely(strcmp(object_class_get_name(oc), 8620 TYPE_HOST_POWERPC_CPU) == 0)) { 8621 return -1; 8622 } 8623 8624 if (pcc->pvr_match(pcc, pvr)) { 8625 return 0; 8626 } 8627 8628 return -1; 8629 } 8630 8631 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 8632 { 8633 GSList *list, *item; 8634 PowerPCCPUClass *pcc = NULL; 8635 8636 list = object_class_get_list(TYPE_POWERPC_CPU, true); 8637 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 8638 if (item != NULL) { 8639 pcc = POWERPC_CPU_CLASS(item->data); 8640 } 8641 g_slist_free(list); 8642 8643 return pcc; 8644 } 8645 8646 static const char *ppc_cpu_lookup_alias(const char *alias) 8647 { 8648 int ai; 8649 8650 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 8651 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 8652 return ppc_cpu_aliases[ai].model; 8653 } 8654 } 8655 8656 return NULL; 8657 } 8658 8659 static ObjectClass *ppc_cpu_class_by_name(const char *name) 8660 { 8661 char *cpu_model, *typename; 8662 ObjectClass *oc; 8663 const char *p; 8664 unsigned long pvr; 8665 8666 /* 8667 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 8668 * 0x prefix if present) 8669 */ 8670 if (!qemu_strtoul(name, &p, 16, &pvr)) { 8671 int len = p - name; 8672 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 8673 if ((len == 8) && (*p == '\0')) { 8674 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 8675 } 8676 } 8677 8678 cpu_model = g_ascii_strdown(name, -1); 8679 p = ppc_cpu_lookup_alias(cpu_model); 8680 if (p) { 8681 g_free(cpu_model); 8682 cpu_model = g_strdup(p); 8683 } 8684 8685 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 8686 oc = object_class_by_name(typename); 8687 g_free(typename); 8688 g_free(cpu_model); 8689 8690 return oc; 8691 } 8692 8693 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 8694 { 8695 ObjectClass *oc = OBJECT_CLASS(pcc); 8696 8697 while (oc && !object_class_is_abstract(oc)) { 8698 oc = object_class_get_parent(oc); 8699 } 8700 assert(oc); 8701 8702 return POWERPC_CPU_CLASS(oc); 8703 } 8704 8705 /* Sort by PVR, ordering special case "host" last. */ 8706 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 8707 { 8708 ObjectClass *oc_a = (ObjectClass *)a; 8709 ObjectClass *oc_b = (ObjectClass *)b; 8710 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 8711 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 8712 const char *name_a = object_class_get_name(oc_a); 8713 const char *name_b = object_class_get_name(oc_b); 8714 8715 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 8716 return 1; 8717 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 8718 return -1; 8719 } else { 8720 /* Avoid an integer overflow during subtraction */ 8721 if (pcc_a->pvr < pcc_b->pvr) { 8722 return -1; 8723 } else if (pcc_a->pvr > pcc_b->pvr) { 8724 return 1; 8725 } else { 8726 return 0; 8727 } 8728 } 8729 } 8730 8731 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8732 { 8733 ObjectClass *oc = data; 8734 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8735 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8736 const char *typename = object_class_get_name(oc); 8737 char *name; 8738 int i; 8739 8740 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8741 return; 8742 } 8743 8744 name = g_strndup(typename, 8745 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8746 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8747 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8748 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8749 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8750 8751 if (alias_oc != oc) { 8752 continue; 8753 } 8754 /* 8755 * If running with KVM, we might update the family alias later, so 8756 * avoid printing the wrong alias here and use "preferred" instead 8757 */ 8758 if (strcmp(alias->alias, family->desc) == 0) { 8759 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8760 alias->alias, family->desc); 8761 } else { 8762 qemu_printf("PowerPC %-16s (alias for %s)\n", 8763 alias->alias, name); 8764 } 8765 } 8766 g_free(name); 8767 } 8768 8769 void ppc_cpu_list(void) 8770 { 8771 GSList *list; 8772 8773 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8774 list = g_slist_sort(list, ppc_cpu_list_compare); 8775 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 8776 g_slist_free(list); 8777 8778 #ifdef CONFIG_KVM 8779 qemu_printf("\n"); 8780 qemu_printf("PowerPC %-16s\n", "host"); 8781 #endif 8782 } 8783 8784 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 8785 { 8786 ObjectClass *oc = data; 8787 CpuDefinitionInfoList **first = user_data; 8788 const char *typename; 8789 CpuDefinitionInfo *info; 8790 8791 typename = object_class_get_name(oc); 8792 info = g_malloc0(sizeof(*info)); 8793 info->name = g_strndup(typename, 8794 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8795 8796 QAPI_LIST_PREPEND(*first, info); 8797 } 8798 8799 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8800 { 8801 CpuDefinitionInfoList *cpu_list = NULL; 8802 GSList *list; 8803 int i; 8804 8805 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8806 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 8807 g_slist_free(list); 8808 8809 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8810 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8811 ObjectClass *oc; 8812 CpuDefinitionInfo *info; 8813 8814 oc = ppc_cpu_class_by_name(alias->model); 8815 if (oc == NULL) { 8816 continue; 8817 } 8818 8819 info = g_malloc0(sizeof(*info)); 8820 info->name = g_strdup(alias->alias); 8821 info->q_typename = g_strdup(object_class_get_name(oc)); 8822 8823 QAPI_LIST_PREPEND(cpu_list, info); 8824 } 8825 8826 return cpu_list; 8827 } 8828 8829 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8830 { 8831 PowerPCCPU *cpu = POWERPC_CPU(cs); 8832 8833 cpu->env.nip = value; 8834 } 8835 8836 static bool ppc_cpu_has_work(CPUState *cs) 8837 { 8838 PowerPCCPU *cpu = POWERPC_CPU(cs); 8839 CPUPPCState *env = &cpu->env; 8840 8841 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8842 } 8843 8844 static void ppc_cpu_reset(DeviceState *dev) 8845 { 8846 CPUState *s = CPU(dev); 8847 PowerPCCPU *cpu = POWERPC_CPU(s); 8848 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8849 CPUPPCState *env = &cpu->env; 8850 target_ulong msr; 8851 int i; 8852 8853 pcc->parent_reset(dev); 8854 8855 msr = (target_ulong)0; 8856 msr |= (target_ulong)MSR_HVB; 8857 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 8858 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 8859 msr |= (target_ulong)1 << MSR_EP; 8860 #if defined(DO_SINGLE_STEP) && 0 8861 /* Single step trace mode */ 8862 msr |= (target_ulong)1 << MSR_SE; 8863 msr |= (target_ulong)1 << MSR_BE; 8864 #endif 8865 #if defined(CONFIG_USER_ONLY) 8866 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8867 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8868 msr |= (target_ulong)1 << MSR_FE1; 8869 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8870 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8871 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8872 msr |= (target_ulong)1 << MSR_PR; 8873 #if defined(TARGET_PPC64) 8874 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8875 #endif 8876 #if !defined(TARGET_WORDS_BIGENDIAN) 8877 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8878 if (!((env->msr_mask >> MSR_LE) & 1)) { 8879 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8880 exit(1); 8881 } 8882 #endif 8883 #endif 8884 8885 #if defined(TARGET_PPC64) 8886 if (mmu_is_64bit(env->mmu_model)) { 8887 msr |= (1ULL << MSR_SF); 8888 } 8889 #endif 8890 8891 hreg_store_msr(env, msr, 1); 8892 8893 #if !defined(CONFIG_USER_ONLY) 8894 env->nip = env->hreset_vector | env->excp_prefix; 8895 if (env->mmu_model != POWERPC_MMU_REAL) { 8896 ppc_tlb_invalidate_all(env); 8897 } 8898 #endif 8899 8900 hreg_compute_hflags(env); 8901 env->reserve_addr = (target_ulong)-1ULL; 8902 /* Be sure no exception or interrupt is pending */ 8903 env->pending_interrupts = 0; 8904 s->exception_index = POWERPC_EXCP_NONE; 8905 env->error_code = 0; 8906 ppc_irq_reset(cpu); 8907 8908 /* tininess for underflow is detected before rounding */ 8909 set_float_detect_tininess(float_tininess_before_rounding, 8910 &env->fp_status); 8911 8912 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8913 ppc_spr_t *spr = &env->spr_cb[i]; 8914 8915 if (!spr->name) { 8916 continue; 8917 } 8918 env->spr[i] = spr->default_value; 8919 } 8920 } 8921 8922 #ifndef CONFIG_USER_ONLY 8923 8924 static bool ppc_cpu_is_big_endian(CPUState *cs) 8925 { 8926 PowerPCCPU *cpu = POWERPC_CPU(cs); 8927 CPUPPCState *env = &cpu->env; 8928 8929 cpu_synchronize_state(cs); 8930 8931 return !msr_le; 8932 } 8933 8934 #ifdef CONFIG_TCG 8935 static void ppc_cpu_exec_enter(CPUState *cs) 8936 { 8937 PowerPCCPU *cpu = POWERPC_CPU(cs); 8938 8939 if (cpu->vhyp) { 8940 PPCVirtualHypervisorClass *vhc = 8941 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8942 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8943 } 8944 } 8945 8946 static void ppc_cpu_exec_exit(CPUState *cs) 8947 { 8948 PowerPCCPU *cpu = POWERPC_CPU(cs); 8949 8950 if (cpu->vhyp) { 8951 PPCVirtualHypervisorClass *vhc = 8952 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8953 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8954 } 8955 } 8956 #endif /* CONFIG_TCG */ 8957 8958 #endif /* !CONFIG_USER_ONLY */ 8959 8960 static void ppc_cpu_instance_init(Object *obj) 8961 { 8962 PowerPCCPU *cpu = POWERPC_CPU(obj); 8963 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8964 CPUPPCState *env = &cpu->env; 8965 8966 cpu_set_cpustate_pointers(cpu); 8967 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8968 8969 env->msr_mask = pcc->msr_mask; 8970 env->mmu_model = pcc->mmu_model; 8971 env->excp_model = pcc->excp_model; 8972 env->bus_model = pcc->bus_model; 8973 env->insns_flags = pcc->insns_flags; 8974 env->insns_flags2 = pcc->insns_flags2; 8975 env->flags = pcc->flags; 8976 env->bfd_mach = pcc->bfd_mach; 8977 env->check_pow = pcc->check_pow; 8978 8979 /* 8980 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8981 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8982 * mode support will remain, thus enforcing that we cannot use 8983 * priv. instructions in guest in PAPR mode. For 970 we currently 8984 * simply don't set HV in msr_mask thus simulating an "Apple mode" 8985 * 970. If we ever want to support 970 HV mode, we'll have to add 8986 * a processor attribute of some sort. 8987 */ 8988 #if !defined(CONFIG_USER_ONLY) 8989 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 8990 #endif 8991 8992 ppc_hash64_init(cpu); 8993 } 8994 8995 static void ppc_cpu_instance_finalize(Object *obj) 8996 { 8997 PowerPCCPU *cpu = POWERPC_CPU(obj); 8998 8999 ppc_hash64_finalize(cpu); 9000 } 9001 9002 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 9003 { 9004 return pcc->pvr == pvr; 9005 } 9006 9007 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 9008 { 9009 PowerPCCPU *cpu = POWERPC_CPU(cs); 9010 CPUPPCState *env = &cpu->env; 9011 9012 if ((env->hflags >> MSR_LE) & 1) { 9013 info->endian = BFD_ENDIAN_LITTLE; 9014 } 9015 info->mach = env->bfd_mach; 9016 if (!env->bfd_mach) { 9017 #ifdef TARGET_PPC64 9018 info->mach = bfd_mach_ppc64; 9019 #else 9020 info->mach = bfd_mach_ppc; 9021 #endif 9022 } 9023 info->disassembler_options = (char *)"any"; 9024 info->print_insn = print_insn_ppc; 9025 9026 info->cap_arch = CS_ARCH_PPC; 9027 #ifdef TARGET_PPC64 9028 info->cap_mode = CS_MODE_64; 9029 #endif 9030 } 9031 9032 static Property ppc_cpu_properties[] = { 9033 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 9034 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 9035 false), 9036 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 9037 false), 9038 DEFINE_PROP_END_OF_LIST(), 9039 }; 9040 9041 #ifndef CONFIG_USER_ONLY 9042 #include "hw/core/sysemu-cpu-ops.h" 9043 9044 static const struct SysemuCPUOps ppc_sysemu_ops = { 9045 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 9046 .write_elf32_note = ppc32_cpu_write_elf32_note, 9047 .write_elf64_note = ppc64_cpu_write_elf64_note, 9048 .virtio_is_big_endian = ppc_cpu_is_big_endian, 9049 .legacy_vmsd = &vmstate_ppc_cpu, 9050 }; 9051 #endif 9052 9053 #ifdef CONFIG_TCG 9054 #include "hw/core/tcg-cpu-ops.h" 9055 9056 static const struct TCGCPUOps ppc_tcg_ops = { 9057 .initialize = ppc_translate_init, 9058 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 9059 .tlb_fill = ppc_cpu_tlb_fill, 9060 9061 #ifndef CONFIG_USER_ONLY 9062 .do_interrupt = ppc_cpu_do_interrupt, 9063 .cpu_exec_enter = ppc_cpu_exec_enter, 9064 .cpu_exec_exit = ppc_cpu_exec_exit, 9065 .do_unaligned_access = ppc_cpu_do_unaligned_access, 9066 #endif /* !CONFIG_USER_ONLY */ 9067 }; 9068 #endif /* CONFIG_TCG */ 9069 9070 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 9071 { 9072 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9073 CPUClass *cc = CPU_CLASS(oc); 9074 DeviceClass *dc = DEVICE_CLASS(oc); 9075 9076 device_class_set_parent_realize(dc, ppc_cpu_realize, 9077 &pcc->parent_realize); 9078 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 9079 &pcc->parent_unrealize); 9080 pcc->pvr_match = ppc_pvr_match_default; 9081 device_class_set_props(dc, ppc_cpu_properties); 9082 9083 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 9084 9085 cc->class_by_name = ppc_cpu_class_by_name; 9086 cc->has_work = ppc_cpu_has_work; 9087 cc->dump_state = ppc_cpu_dump_state; 9088 cc->set_pc = ppc_cpu_set_pc; 9089 cc->gdb_read_register = ppc_cpu_gdb_read_register; 9090 cc->gdb_write_register = ppc_cpu_gdb_write_register; 9091 #ifndef CONFIG_USER_ONLY 9092 cc->sysemu_ops = &ppc_sysemu_ops; 9093 #endif 9094 9095 cc->gdb_num_core_regs = 71; 9096 #ifndef CONFIG_USER_ONLY 9097 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 9098 #endif 9099 #ifdef USE_APPLE_GDB 9100 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 9101 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 9102 cc->gdb_num_core_regs = 71 + 32; 9103 #endif 9104 9105 cc->gdb_arch_name = ppc_gdb_arch_name; 9106 #if defined(TARGET_PPC64) 9107 cc->gdb_core_xml_file = "power64-core.xml"; 9108 #else 9109 cc->gdb_core_xml_file = "power-core.xml"; 9110 #endif 9111 cc->disas_set_info = ppc_disas_set_info; 9112 9113 dc->fw_name = "PowerPC,UNKNOWN"; 9114 9115 #ifdef CONFIG_TCG 9116 cc->tcg_ops = &ppc_tcg_ops; 9117 #endif /* CONFIG_TCG */ 9118 } 9119 9120 static const TypeInfo ppc_cpu_type_info = { 9121 .name = TYPE_POWERPC_CPU, 9122 .parent = TYPE_CPU, 9123 .instance_size = sizeof(PowerPCCPU), 9124 .instance_align = __alignof__(PowerPCCPU), 9125 .instance_init = ppc_cpu_instance_init, 9126 .instance_finalize = ppc_cpu_instance_finalize, 9127 .abstract = true, 9128 .class_size = sizeof(PowerPCCPUClass), 9129 .class_init = ppc_cpu_class_init, 9130 }; 9131 9132 #ifndef CONFIG_USER_ONLY 9133 static const TypeInfo ppc_vhyp_type_info = { 9134 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 9135 .parent = TYPE_INTERFACE, 9136 .class_size = sizeof(PPCVirtualHypervisorClass), 9137 }; 9138 #endif 9139 9140 static void ppc_cpu_register_types(void) 9141 { 9142 type_register_static(&ppc_cpu_type_info); 9143 #ifndef CONFIG_USER_ONLY 9144 type_register_static(&ppc_vhyp_type_info); 9145 #endif 9146 } 9147 9148 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 9149 { 9150 #define RGPL 4 9151 #define RFPL 4 9152 9153 PowerPCCPU *cpu = POWERPC_CPU(cs); 9154 CPUPPCState *env = &cpu->env; 9155 int i; 9156 9157 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 9158 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 9159 env->nip, env->lr, env->ctr, cpu_read_xer(env), 9160 cs->cpu_index); 9161 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 9162 "%08x iidx %d didx %d\n", 9163 env->msr, env->spr[SPR_HID0], env->hflags, 9164 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 9165 #if !defined(NO_TIMER_DUMP) 9166 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 9167 #if !defined(CONFIG_USER_ONLY) 9168 " DECR " TARGET_FMT_lu 9169 #endif 9170 "\n", 9171 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 9172 #if !defined(CONFIG_USER_ONLY) 9173 , cpu_ppc_load_decr(env) 9174 #endif 9175 ); 9176 #endif 9177 for (i = 0; i < 32; i++) { 9178 if ((i & (RGPL - 1)) == 0) { 9179 qemu_fprintf(f, "GPR%02d", i); 9180 } 9181 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 9182 if ((i & (RGPL - 1)) == (RGPL - 1)) { 9183 qemu_fprintf(f, "\n"); 9184 } 9185 } 9186 qemu_fprintf(f, "CR "); 9187 for (i = 0; i < 8; i++) 9188 qemu_fprintf(f, "%01x", env->crf[i]); 9189 qemu_fprintf(f, " ["); 9190 for (i = 0; i < 8; i++) { 9191 char a = '-'; 9192 if (env->crf[i] & 0x08) { 9193 a = 'L'; 9194 } else if (env->crf[i] & 0x04) { 9195 a = 'G'; 9196 } else if (env->crf[i] & 0x02) { 9197 a = 'E'; 9198 } 9199 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 9200 } 9201 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 9202 env->reserve_addr); 9203 9204 if (flags & CPU_DUMP_FPU) { 9205 for (i = 0; i < 32; i++) { 9206 if ((i & (RFPL - 1)) == 0) { 9207 qemu_fprintf(f, "FPR%02d", i); 9208 } 9209 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 9210 if ((i & (RFPL - 1)) == (RFPL - 1)) { 9211 qemu_fprintf(f, "\n"); 9212 } 9213 } 9214 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 9215 } 9216 9217 #if !defined(CONFIG_USER_ONLY) 9218 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 9219 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 9220 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 9221 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 9222 9223 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 9224 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 9225 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 9226 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 9227 9228 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 9229 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 9230 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 9231 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 9232 9233 #if defined(TARGET_PPC64) 9234 if (env->excp_model == POWERPC_EXCP_POWER7 || 9235 env->excp_model == POWERPC_EXCP_POWER8 || 9236 env->excp_model == POWERPC_EXCP_POWER9 || 9237 env->excp_model == POWERPC_EXCP_POWER10) { 9238 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 9239 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 9240 } 9241 #endif 9242 if (env->excp_model == POWERPC_EXCP_BOOKE) { 9243 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 9244 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 9245 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 9246 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 9247 9248 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 9249 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 9250 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 9251 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 9252 9253 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 9254 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 9255 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 9256 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 9257 9258 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 9259 " EPR " TARGET_FMT_lx "\n", 9260 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 9261 env->spr[SPR_BOOKE_EPR]); 9262 9263 /* FSL-specific */ 9264 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 9265 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 9266 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 9267 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 9268 9269 /* 9270 * IVORs are left out as they are large and do not change often -- 9271 * they can be read with "p $ivor0", "p $ivor1", etc. 9272 */ 9273 } 9274 9275 #if defined(TARGET_PPC64) 9276 if (env->flags & POWERPC_FLAG_CFAR) { 9277 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 9278 } 9279 #endif 9280 9281 if (env->spr_cb[SPR_LPCR].name) { 9282 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 9283 } 9284 9285 switch (env->mmu_model) { 9286 case POWERPC_MMU_32B: 9287 case POWERPC_MMU_601: 9288 case POWERPC_MMU_SOFT_6xx: 9289 case POWERPC_MMU_SOFT_74xx: 9290 #if defined(TARGET_PPC64) 9291 case POWERPC_MMU_64B: 9292 case POWERPC_MMU_2_03: 9293 case POWERPC_MMU_2_06: 9294 case POWERPC_MMU_2_07: 9295 case POWERPC_MMU_3_00: 9296 #endif 9297 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 9298 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 9299 } 9300 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 9301 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 9302 } 9303 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 9304 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 9305 break; 9306 case POWERPC_MMU_BOOKE206: 9307 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 9308 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 9309 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 9310 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 9311 9312 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 9313 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 9314 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 9315 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 9316 9317 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 9318 " TLB1CFG " TARGET_FMT_lx "\n", 9319 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 9320 env->spr[SPR_BOOKE_TLB1CFG]); 9321 break; 9322 default: 9323 break; 9324 } 9325 #endif 9326 9327 #undef RGPL 9328 #undef RFPL 9329 } 9330 type_init(ppc_cpu_register_types) 9331