1 2 /* 3 * PowerPC CPU initialization for qemu. 4 * 5 * Copyright (c) 2003-2007 Jocelyn Mayer 6 * Copyright 2011 Freescale Semiconductor, Inc. 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 #include "gdbstub/helpers.h" 25 #include "system/cpus.h" 26 #include "system/hw_accel.h" 27 #include "system/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qobject/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 44 #include "helper_regs.h" 45 #include "internal.h" 46 #include "spr_common.h" 47 #include "power8-pmu.h" 48 49 #ifndef CONFIG_USER_ONLY 50 #include "hw/boards.h" 51 #include "hw/intc/intc.h" 52 #include "kvm_ppc.h" 53 #endif 54 55 #include "cpu_init.h" 56 /* #define PPC_DEBUG_SPR */ 57 /* #define USE_APPLE_GDB */ 58 59 static inline void vscr_init(CPUPPCState *env, uint32_t val) 60 { 61 /* Altivec always uses round-to-nearest */ 62 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 63 ppc_store_vscr(env, val); 64 } 65 66 static void register_745_sprs(CPUPPCState *env) 67 { 68 /* SGPRs */ 69 spr_register(env, SPR_SPRG4, "SPRG4", 70 SPR_NOACCESS, SPR_NOACCESS, 71 &spr_read_generic, &spr_write_generic, 72 0x00000000); 73 spr_register(env, SPR_SPRG5, "SPRG5", 74 SPR_NOACCESS, SPR_NOACCESS, 75 &spr_read_generic, &spr_write_generic, 76 0x00000000); 77 spr_register(env, SPR_SPRG6, "SPRG6", 78 SPR_NOACCESS, SPR_NOACCESS, 79 &spr_read_generic, &spr_write_generic, 80 0x00000000); 81 spr_register(env, SPR_SPRG7, "SPRG7", 82 SPR_NOACCESS, SPR_NOACCESS, 83 &spr_read_generic, &spr_write_generic, 84 0x00000000); 85 86 /* Hardware implementation registers */ 87 spr_register(env, SPR_HID0, "HID0", 88 SPR_NOACCESS, SPR_NOACCESS, 89 &spr_read_generic, &spr_write_generic, 90 0x00000000); 91 92 spr_register(env, SPR_HID1, "HID1", 93 SPR_NOACCESS, SPR_NOACCESS, 94 &spr_read_generic, &spr_write_generic, 95 0x00000000); 96 97 spr_register(env, SPR_HID2, "HID2", 98 SPR_NOACCESS, SPR_NOACCESS, 99 &spr_read_generic, &spr_write_generic, 100 0x00000000); 101 } 102 103 static void register_755_sprs(CPUPPCState *env) 104 { 105 /* L2 cache control */ 106 spr_register(env, SPR_L2CR, "L2CR", 107 SPR_NOACCESS, SPR_NOACCESS, 108 &spr_read_generic, spr_access_nop, 109 0x00000000); 110 111 spr_register(env, SPR_L2PMCR, "L2PMCR", 112 SPR_NOACCESS, SPR_NOACCESS, 113 &spr_read_generic, &spr_write_generic, 114 0x00000000); 115 } 116 117 /* SPR common to all 7xx PowerPC implementations */ 118 static void register_7xx_sprs(CPUPPCState *env) 119 { 120 /* Breakpoints */ 121 spr_register_kvm(env, SPR_DABR, "DABR", 122 SPR_NOACCESS, SPR_NOACCESS, 123 &spr_read_generic, &spr_write_generic, 124 KVM_REG_PPC_DABR, 0x00000000); 125 126 spr_register(env, SPR_IABR, "IABR", 127 SPR_NOACCESS, SPR_NOACCESS, 128 &spr_read_generic, &spr_write_generic, 129 0x00000000); 130 /* Cache management */ 131 spr_register(env, SPR_ICTC, "ICTC", 132 SPR_NOACCESS, SPR_NOACCESS, 133 &spr_read_generic, &spr_write_generic, 134 0x00000000); 135 /* Performance monitors */ 136 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 137 SPR_NOACCESS, SPR_NOACCESS, 138 &spr_read_generic, &spr_write_generic, 139 0x00000000); 140 141 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 142 SPR_NOACCESS, SPR_NOACCESS, 143 &spr_read_generic, &spr_write_generic, 144 0x00000000); 145 146 spr_register(env, SPR_7XX_PMC1, "PMC1", 147 SPR_NOACCESS, SPR_NOACCESS, 148 &spr_read_generic, &spr_write_generic, 149 0x00000000); 150 151 spr_register(env, SPR_7XX_PMC2, "PMC2", 152 SPR_NOACCESS, SPR_NOACCESS, 153 &spr_read_generic, &spr_write_generic, 154 0x00000000); 155 156 spr_register(env, SPR_7XX_PMC3, "PMC3", 157 SPR_NOACCESS, SPR_NOACCESS, 158 &spr_read_generic, &spr_write_generic, 159 0x00000000); 160 161 spr_register(env, SPR_7XX_PMC4, "PMC4", 162 SPR_NOACCESS, SPR_NOACCESS, 163 &spr_read_generic, &spr_write_generic, 164 0x00000000); 165 166 spr_register(env, SPR_7XX_SIAR, "SIAR", 167 SPR_NOACCESS, SPR_NOACCESS, 168 &spr_read_generic, SPR_NOACCESS, 169 0x00000000); 170 171 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 172 &spr_read_ureg, SPR_NOACCESS, 173 &spr_read_ureg, SPR_NOACCESS, 174 0x00000000); 175 176 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 177 &spr_read_ureg, SPR_NOACCESS, 178 &spr_read_ureg, SPR_NOACCESS, 179 0x00000000); 180 181 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 182 &spr_read_ureg, SPR_NOACCESS, 183 &spr_read_ureg, SPR_NOACCESS, 184 0x00000000); 185 186 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 187 &spr_read_ureg, SPR_NOACCESS, 188 &spr_read_ureg, SPR_NOACCESS, 189 0x00000000); 190 191 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 192 &spr_read_ureg, SPR_NOACCESS, 193 &spr_read_ureg, SPR_NOACCESS, 194 0x00000000); 195 196 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 197 &spr_read_ureg, SPR_NOACCESS, 198 &spr_read_ureg, SPR_NOACCESS, 199 0x00000000); 200 201 spr_register(env, SPR_7XX_USIAR, "USIAR", 202 &spr_read_ureg, SPR_NOACCESS, 203 &spr_read_ureg, SPR_NOACCESS, 204 0x00000000); 205 /* External access control */ 206 spr_register(env, SPR_EAR, "EAR", 207 SPR_NOACCESS, SPR_NOACCESS, 208 &spr_read_generic, &spr_write_generic, 209 0x00000000); 210 211 /* Hardware implementation registers */ 212 spr_register(env, SPR_HID0, "HID0", 213 SPR_NOACCESS, SPR_NOACCESS, 214 &spr_read_generic, &spr_write_generic, 215 0x00000000); 216 217 spr_register(env, SPR_HID1, "HID1", 218 SPR_NOACCESS, SPR_NOACCESS, 219 &spr_read_generic, &spr_write_generic, 220 0x00000000); 221 } 222 223 #ifdef TARGET_PPC64 224 static void register_amr_sprs(CPUPPCState *env) 225 { 226 #ifndef CONFIG_USER_ONLY 227 /* 228 * Virtual Page Class Key protection 229 * 230 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 231 * userspace accessible, 29 is privileged. So we only need to set 232 * the kvm ONE_REG id on one of them, we use 29 233 */ 234 spr_register(env, SPR_UAMR, "UAMR", 235 &spr_read_generic, &spr_write_amr, 236 &spr_read_generic, &spr_write_amr, 237 0); 238 spr_register_kvm_hv(env, SPR_AMR, "AMR", 239 SPR_NOACCESS, SPR_NOACCESS, 240 &spr_read_generic, &spr_write_amr, 241 &spr_read_generic, &spr_write_generic, 242 KVM_REG_PPC_AMR, 0); 243 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_generic, &spr_write_uamor, 246 &spr_read_generic, &spr_write_generic, 247 KVM_REG_PPC_UAMOR, 0); 248 spr_register_hv(env, SPR_AMOR, "AMOR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 SPR_NOACCESS, SPR_NOACCESS, 251 &spr_read_generic, &spr_core_lpar_write_generic, 252 0); 253 #endif /* !CONFIG_USER_ONLY */ 254 } 255 256 static void register_iamr_sprs(CPUPPCState *env) 257 { 258 #ifndef CONFIG_USER_ONLY 259 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_generic, &spr_write_iamr, 262 &spr_read_generic, &spr_write_generic, 263 KVM_REG_PPC_IAMR, 0); 264 #endif /* !CONFIG_USER_ONLY */ 265 } 266 #endif /* TARGET_PPC64 */ 267 268 /* SPR specific to PowerPC 604 implementation */ 269 static void register_604_sprs(CPUPPCState *env) 270 { 271 /* Processor identification */ 272 spr_register(env, SPR_PIR, "PIR", 273 SPR_NOACCESS, SPR_NOACCESS, 274 &spr_read_generic, &spr_write_pir, 275 0x00000000); 276 /* Breakpoints */ 277 spr_register(env, SPR_IABR, "IABR", 278 SPR_NOACCESS, SPR_NOACCESS, 279 &spr_read_generic, &spr_write_generic, 280 0x00000000); 281 282 spr_register_kvm(env, SPR_DABR, "DABR", 283 SPR_NOACCESS, SPR_NOACCESS, 284 &spr_read_generic, &spr_write_generic, 285 KVM_REG_PPC_DABR, 0x00000000); 286 /* Performance counters */ 287 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_generic, &spr_write_generic, 290 0x00000000); 291 292 spr_register(env, SPR_7XX_PMC1, "PMC1", 293 SPR_NOACCESS, SPR_NOACCESS, 294 &spr_read_generic, &spr_write_generic, 295 0x00000000); 296 297 spr_register(env, SPR_7XX_PMC2, "PMC2", 298 SPR_NOACCESS, SPR_NOACCESS, 299 &spr_read_generic, &spr_write_generic, 300 0x00000000); 301 302 spr_register(env, SPR_7XX_SIAR, "SIAR", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_generic, SPR_NOACCESS, 305 0x00000000); 306 307 spr_register(env, SPR_SDA, "SDA", 308 SPR_NOACCESS, SPR_NOACCESS, 309 &spr_read_generic, SPR_NOACCESS, 310 0x00000000); 311 /* External access control */ 312 spr_register(env, SPR_EAR, "EAR", 313 SPR_NOACCESS, SPR_NOACCESS, 314 &spr_read_generic, &spr_write_generic, 315 0x00000000); 316 317 /* Hardware implementation registers */ 318 spr_register(env, SPR_HID0, "HID0", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_generic, &spr_write_generic, 321 0x00000000); 322 } 323 324 static void register_604e_sprs(CPUPPCState *env) 325 { 326 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_generic, &spr_write_generic, 329 0x00000000); 330 331 spr_register(env, SPR_7XX_PMC3, "PMC3", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_generic, &spr_write_generic, 334 0x00000000); 335 336 spr_register(env, SPR_7XX_PMC4, "PMC4", 337 SPR_NOACCESS, SPR_NOACCESS, 338 &spr_read_generic, &spr_write_generic, 339 0x00000000); 340 /* Hardware implementation registers */ 341 spr_register(env, SPR_HID1, "HID1", 342 SPR_NOACCESS, SPR_NOACCESS, 343 &spr_read_generic, &spr_write_generic, 344 0x00000000); 345 } 346 347 /* SPR specific to PowerPC 603 implementation */ 348 static void register_603_sprs(CPUPPCState *env) 349 { 350 /* External access control */ 351 spr_register(env, SPR_EAR, "EAR", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_generic, &spr_write_generic, 354 0x00000000); 355 /* Breakpoints */ 356 spr_register(env, SPR_IABR, "IABR", 357 SPR_NOACCESS, SPR_NOACCESS, 358 &spr_read_generic, &spr_write_generic, 359 0x00000000); 360 361 spr_register(env, SPR_HID0, "HID0", 362 SPR_NOACCESS, SPR_NOACCESS, 363 &spr_read_generic, &spr_write_generic, 364 0x00000000); 365 366 spr_register(env, SPR_HID1, "HID1", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_generic, &spr_write_generic, 369 0x00000000); 370 } 371 372 static void register_e300_sprs(CPUPPCState *env) 373 { 374 /* hardware implementation registers */ 375 spr_register(env, SPR_HID2, "HID2", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_generic, &spr_write_generic, 378 0x00000000); 379 /* Breakpoints */ 380 spr_register(env, SPR_DABR, "DABR", 381 SPR_NOACCESS, SPR_NOACCESS, 382 &spr_read_generic, &spr_write_generic, 383 0x00000000); 384 385 spr_register(env, SPR_DABR2, "DABR2", 386 SPR_NOACCESS, SPR_NOACCESS, 387 &spr_read_generic, &spr_write_generic, 388 0x00000000); 389 390 spr_register(env, SPR_IABR2, "IABR2", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, &spr_write_generic, 393 0x00000000); 394 395 spr_register(env, SPR_IBCR, "IBCR", 396 SPR_NOACCESS, SPR_NOACCESS, 397 &spr_read_generic, &spr_write_generic, 398 0x00000000); 399 400 spr_register(env, SPR_DBCR, "DBCR", 401 SPR_NOACCESS, SPR_NOACCESS, 402 &spr_read_generic, &spr_write_generic, 403 0x00000000); 404 } 405 406 /* SPR specific to PowerPC G2 implementation */ 407 static void register_G2_sprs(CPUPPCState *env) 408 { 409 /* Memory base address */ 410 /* MBAR */ 411 spr_register(env, SPR_MBAR, "MBAR", 412 SPR_NOACCESS, SPR_NOACCESS, 413 &spr_read_generic, &spr_write_generic, 414 0x00000000); 415 /* Exception processing */ 416 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, &spr_write_generic, 419 0x00000000); 420 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, &spr_write_generic, 423 0x00000000); 424 /* Breakpoints */ 425 spr_register(env, SPR_DABR, "DABR", 426 SPR_NOACCESS, SPR_NOACCESS, 427 &spr_read_generic, &spr_write_generic, 428 0x00000000); 429 430 spr_register(env, SPR_DABR2, "DABR2", 431 SPR_NOACCESS, SPR_NOACCESS, 432 &spr_read_generic, &spr_write_generic, 433 0x00000000); 434 435 spr_register(env, SPR_IABR, "IABR", 436 SPR_NOACCESS, SPR_NOACCESS, 437 &spr_read_generic, &spr_write_generic, 438 0x00000000); 439 440 spr_register(env, SPR_IABR2, "IABR2", 441 SPR_NOACCESS, SPR_NOACCESS, 442 &spr_read_generic, &spr_write_generic, 443 0x00000000); 444 445 spr_register(env, SPR_IBCR, "IBCR", 446 SPR_NOACCESS, SPR_NOACCESS, 447 &spr_read_generic, &spr_write_generic, 448 0x00000000); 449 450 spr_register(env, SPR_DBCR, "DBCR", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, &spr_write_generic, 453 0x00000000); 454 455 /* External access control */ 456 spr_register(env, SPR_EAR, "EAR", 457 SPR_NOACCESS, SPR_NOACCESS, 458 &spr_read_generic, &spr_write_generic, 459 0x00000000); 460 /* Hardware implementation register */ 461 spr_register(env, SPR_HID0, "HID0", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, &spr_write_generic, 464 0x00000000); 465 466 spr_register(env, SPR_HID1, "HID1", 467 SPR_NOACCESS, SPR_NOACCESS, 468 &spr_read_generic, &spr_write_generic, 469 0x00000000); 470 471 spr_register(env, SPR_HID2, "HID2", 472 SPR_NOACCESS, SPR_NOACCESS, 473 &spr_read_generic, &spr_write_generic, 474 0x00000000); 475 476 /* SGPRs */ 477 spr_register(env, SPR_SPRG4, "SPRG4", 478 SPR_NOACCESS, SPR_NOACCESS, 479 &spr_read_generic, &spr_write_generic, 480 0x00000000); 481 spr_register(env, SPR_SPRG5, "SPRG5", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 spr_register(env, SPR_SPRG6, "SPRG6", 486 SPR_NOACCESS, SPR_NOACCESS, 487 &spr_read_generic, &spr_write_generic, 488 0x00000000); 489 spr_register(env, SPR_SPRG7, "SPRG7", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 } 494 495 static void register_74xx_sprs(CPUPPCState *env) 496 { 497 /* Breakpoints */ 498 spr_register_kvm(env, SPR_DABR, "DABR", 499 SPR_NOACCESS, SPR_NOACCESS, 500 &spr_read_generic, &spr_write_generic, 501 KVM_REG_PPC_DABR, 0x00000000); 502 503 spr_register(env, SPR_IABR, "IABR", 504 SPR_NOACCESS, SPR_NOACCESS, 505 &spr_read_generic, &spr_write_generic, 506 0x00000000); 507 /* Cache management */ 508 spr_register(env, SPR_ICTC, "ICTC", 509 SPR_NOACCESS, SPR_NOACCESS, 510 &spr_read_generic, &spr_write_generic, 511 0x00000000); 512 /* Performance monitors */ 513 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_generic, &spr_write_generic, 516 0x00000000); 517 518 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 519 SPR_NOACCESS, SPR_NOACCESS, 520 &spr_read_generic, &spr_write_generic, 521 0x00000000); 522 523 spr_register(env, SPR_7XX_PMC1, "PMC1", 524 SPR_NOACCESS, SPR_NOACCESS, 525 &spr_read_generic, &spr_write_generic, 526 0x00000000); 527 528 spr_register(env, SPR_7XX_PMC2, "PMC2", 529 SPR_NOACCESS, SPR_NOACCESS, 530 &spr_read_generic, &spr_write_generic, 531 0x00000000); 532 533 spr_register(env, SPR_7XX_PMC3, "PMC3", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_generic, &spr_write_generic, 536 0x00000000); 537 538 spr_register(env, SPR_7XX_PMC4, "PMC4", 539 SPR_NOACCESS, SPR_NOACCESS, 540 &spr_read_generic, &spr_write_generic, 541 0x00000000); 542 543 spr_register(env, SPR_7XX_SIAR, "SIAR", 544 SPR_NOACCESS, SPR_NOACCESS, 545 &spr_read_generic, SPR_NOACCESS, 546 0x00000000); 547 548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 549 &spr_read_ureg, SPR_NOACCESS, 550 &spr_read_ureg, SPR_NOACCESS, 551 0x00000000); 552 553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 554 &spr_read_ureg, SPR_NOACCESS, 555 &spr_read_ureg, SPR_NOACCESS, 556 0x00000000); 557 558 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 559 &spr_read_ureg, SPR_NOACCESS, 560 &spr_read_ureg, SPR_NOACCESS, 561 0x00000000); 562 563 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 564 &spr_read_ureg, SPR_NOACCESS, 565 &spr_read_ureg, SPR_NOACCESS, 566 0x00000000); 567 568 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 569 &spr_read_ureg, SPR_NOACCESS, 570 &spr_read_ureg, SPR_NOACCESS, 571 0x00000000); 572 573 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 574 &spr_read_ureg, SPR_NOACCESS, 575 &spr_read_ureg, SPR_NOACCESS, 576 0x00000000); 577 578 spr_register(env, SPR_7XX_USIAR, "USIAR", 579 &spr_read_ureg, SPR_NOACCESS, 580 &spr_read_ureg, SPR_NOACCESS, 581 0x00000000); 582 /* External access control */ 583 spr_register(env, SPR_EAR, "EAR", 584 SPR_NOACCESS, SPR_NOACCESS, 585 &spr_read_generic, &spr_write_generic, 586 0x00000000); 587 588 /* Processor identification */ 589 spr_register(env, SPR_PIR, "PIR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 &spr_read_generic, &spr_write_pir, 592 0x00000000); 593 594 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 595 SPR_NOACCESS, SPR_NOACCESS, 596 &spr_read_generic, &spr_write_generic, 597 0x00000000); 598 599 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 600 &spr_read_ureg, SPR_NOACCESS, 601 &spr_read_ureg, SPR_NOACCESS, 602 0x00000000); 603 604 spr_register(env, SPR_BAMR, "BAMR", 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_generic, 607 0x00000000); 608 609 spr_register(env, SPR_MSSCR0, "MSSCR0", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_generic, &spr_write_generic, 612 0x00000000); 613 /* Hardware implementation registers */ 614 spr_register(env, SPR_HID0, "HID0", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_generic, 617 0x00000000); 618 619 spr_register(env, SPR_HID1, "HID1", 620 SPR_NOACCESS, SPR_NOACCESS, 621 &spr_read_generic, &spr_write_generic, 622 0x00000000); 623 /* Altivec */ 624 spr_register(env, SPR_VRSAVE, "VRSAVE", 625 &spr_read_generic, &spr_write_generic, 626 &spr_read_generic, &spr_write_generic, 627 0x00000000); 628 629 spr_register(env, SPR_L2CR, "L2CR", 630 SPR_NOACCESS, SPR_NOACCESS, 631 &spr_read_generic, spr_access_nop, 632 0x00000000); 633 } 634 635 static void register_l3_ctrl(CPUPPCState *env) 636 { 637 /* L3CR */ 638 spr_register(env, SPR_L3CR, "L3CR", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 0x00000000); 642 /* L3ITCR0 */ 643 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_generic, &spr_write_generic, 646 0x00000000); 647 /* L3PM */ 648 spr_register(env, SPR_L3PM, "L3PM", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_generic, 651 0x00000000); 652 } 653 654 /* PowerPC BookE SPR */ 655 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 656 { 657 const char *ivor_names[64] = { 658 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 659 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 660 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 661 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 662 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 663 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 664 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 665 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 666 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 667 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 668 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 669 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 670 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 671 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 672 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 673 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 674 }; 675 #define SPR_BOOKE_IVORxx (-1) 676 int ivor_sprn[64] = { 677 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 678 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 679 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 680 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 685 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 686 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 687 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 693 }; 694 int i; 695 696 /* Interrupt processing */ 697 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 698 SPR_NOACCESS, SPR_NOACCESS, 699 &spr_read_generic, &spr_write_generic, 700 0x00000000); 701 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 702 SPR_NOACCESS, SPR_NOACCESS, 703 &spr_read_generic, &spr_write_generic, 704 0x00000000); 705 /* Debug */ 706 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 711 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 716 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 717 SPR_NOACCESS, SPR_NOACCESS, 718 &spr_read_generic, &spr_write_generic, 719 0x00000000); 720 721 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 726 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_40x_dbcr0, 729 0x00000000); 730 731 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 736 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 745 SPR_NOACCESS, SPR_NOACCESS, 746 &spr_read_generic, &spr_write_generic, 747 0x00000000); 748 749 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_clear, 752 0x00000000); 753 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 754 SPR_NOACCESS, SPR_NOACCESS, 755 &spr_read_generic, &spr_write_generic, 756 0x00000000); 757 spr_register(env, SPR_BOOKE_ESR, "ESR", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 762 SPR_NOACCESS, SPR_NOACCESS, 763 &spr_read_generic, &spr_write_excp_prefix, 764 0x00000000); 765 /* Exception vectors */ 766 for (i = 0; i < 64; i++) { 767 if (ivor_mask & (1ULL << i)) { 768 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 769 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 770 exit(1); 771 } 772 spr_register(env, ivor_sprn[i], ivor_names[i], 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_excp_vector, 775 0x00000000); 776 } 777 } 778 spr_register(env, SPR_BOOKE_PID, "PID", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_booke_pid, 781 0x00000000); 782 spr_register(env, SPR_BOOKE_TCR, "TCR", 783 SPR_NOACCESS, SPR_NOACCESS, 784 &spr_read_generic, &spr_write_booke_tcr, 785 0x00000000); 786 spr_register(env, SPR_BOOKE_TSR, "TSR", 787 SPR_NOACCESS, SPR_NOACCESS, 788 &spr_read_generic, &spr_write_booke_tsr, 789 0x00000000); 790 /* Timer */ 791 spr_register(env, SPR_DECR, "DECR", 792 SPR_NOACCESS, SPR_NOACCESS, 793 &spr_read_decr, &spr_write_decr, 794 0x00000000); 795 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 796 SPR_NOACCESS, SPR_NOACCESS, 797 SPR_NOACCESS, &spr_write_generic32, 798 0x00000000); 799 /* SPRGs */ 800 spr_register(env, SPR_USPRG0, "USPRG0", 801 &spr_read_generic, &spr_write_generic, 802 &spr_read_generic, &spr_write_generic, 803 0x00000000); 804 spr_register(env, SPR_SPRG4, "SPRG4", 805 SPR_NOACCESS, SPR_NOACCESS, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 spr_register(env, SPR_SPRG5, "SPRG5", 809 SPR_NOACCESS, SPR_NOACCESS, 810 &spr_read_generic, &spr_write_generic, 811 0x00000000); 812 spr_register(env, SPR_SPRG6, "SPRG6", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, &spr_write_generic, 815 0x00000000); 816 spr_register(env, SPR_SPRG7, "SPRG7", 817 SPR_NOACCESS, SPR_NOACCESS, 818 &spr_read_generic, &spr_write_generic, 819 0x00000000); 820 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 821 SPR_NOACCESS, SPR_NOACCESS, 822 &spr_read_generic, &spr_write_generic, 823 0x00000000); 824 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 825 SPR_NOACCESS, SPR_NOACCESS, 826 &spr_read_generic, &spr_write_generic, 827 0x00000000); 828 } 829 830 #if !defined(CONFIG_USER_ONLY) 831 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 832 uint32_t maxsize, uint32_t flags, 833 uint32_t nentries) 834 { 835 return (assoc << TLBnCFG_ASSOC_SHIFT) | 836 (minsize << TLBnCFG_MINSIZE_SHIFT) | 837 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 838 flags | nentries; 839 } 840 #endif /* !CONFIG_USER_ONLY */ 841 842 /* BookE 2.06 storage control registers */ 843 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 844 uint32_t *tlbncfg, uint32_t mmucfg) 845 { 846 #if !defined(CONFIG_USER_ONLY) 847 const char *mas_names[8] = { 848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 849 }; 850 int mas_sprn[8] = { 851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 853 }; 854 int i; 855 856 /* TLB assist registers */ 857 for (i = 0; i < 8; i++) { 858 if (mas_mask & (1 << i)) { 859 spr_register(env, mas_sprn[i], mas_names[i], 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, 862 (i == 2 && (env->insns_flags & PPC_64B)) 863 ? &spr_write_generic : &spr_write_generic32, 864 0x00000000); 865 } 866 } 867 if (env->nb_pids > 1) { 868 spr_register(env, SPR_BOOKE_PID1, "PID1", 869 SPR_NOACCESS, SPR_NOACCESS, 870 &spr_read_generic, &spr_write_booke_pid, 871 0x00000000); 872 } 873 if (env->nb_pids > 2) { 874 spr_register(env, SPR_BOOKE_PID2, "PID2", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_booke_pid, 877 0x00000000); 878 } 879 880 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_eplc, 883 0x00000000); 884 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 885 SPR_NOACCESS, SPR_NOACCESS, 886 &spr_read_generic, &spr_write_epsc, 887 0x00000000); 888 889 spr_register(env, SPR_MMUCFG, "MMUCFG", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, SPR_NOACCESS, 892 mmucfg); 893 switch (env->nb_ways) { 894 case 4: 895 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, SPR_NOACCESS, 898 tlbncfg[3]); 899 /* Fallthru */ 900 case 3: 901 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 902 SPR_NOACCESS, SPR_NOACCESS, 903 &spr_read_generic, SPR_NOACCESS, 904 tlbncfg[2]); 905 /* Fallthru */ 906 case 2: 907 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, SPR_NOACCESS, 910 tlbncfg[1]); 911 /* Fallthru */ 912 case 1: 913 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, SPR_NOACCESS, 916 tlbncfg[0]); 917 /* Fallthru */ 918 case 0: 919 default: 920 break; 921 } 922 #endif 923 } 924 925 /* SPR specific to PowerPC 440 implementation */ 926 static void register_440_sprs(CPUPPCState *env) 927 { 928 /* Cache control */ 929 spr_register(env, SPR_440_DNV0, "DNV0", 930 SPR_NOACCESS, SPR_NOACCESS, 931 &spr_read_generic, &spr_write_generic, 932 0x00000000); 933 934 spr_register(env, SPR_440_DNV1, "DNV1", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_generic, &spr_write_generic, 937 0x00000000); 938 939 spr_register(env, SPR_440_DNV2, "DNV2", 940 SPR_NOACCESS, SPR_NOACCESS, 941 &spr_read_generic, &spr_write_generic, 942 0x00000000); 943 944 spr_register(env, SPR_440_DNV3, "DNV3", 945 SPR_NOACCESS, SPR_NOACCESS, 946 &spr_read_generic, &spr_write_generic, 947 0x00000000); 948 949 spr_register(env, SPR_440_DTV0, "DTV0", 950 SPR_NOACCESS, SPR_NOACCESS, 951 &spr_read_generic, &spr_write_generic, 952 0x00000000); 953 954 spr_register(env, SPR_440_DTV1, "DTV1", 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_generic, &spr_write_generic, 957 0x00000000); 958 959 spr_register(env, SPR_440_DTV2, "DTV2", 960 SPR_NOACCESS, SPR_NOACCESS, 961 &spr_read_generic, &spr_write_generic, 962 0x00000000); 963 964 spr_register(env, SPR_440_DTV3, "DTV3", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_generic, &spr_write_generic, 967 0x00000000); 968 969 spr_register(env, SPR_440_DVLIM, "DVLIM", 970 SPR_NOACCESS, SPR_NOACCESS, 971 &spr_read_generic, &spr_write_generic, 972 0x00000000); 973 974 spr_register(env, SPR_440_INV0, "INV0", 975 SPR_NOACCESS, SPR_NOACCESS, 976 &spr_read_generic, &spr_write_generic, 977 0x00000000); 978 979 spr_register(env, SPR_440_INV1, "INV1", 980 SPR_NOACCESS, SPR_NOACCESS, 981 &spr_read_generic, &spr_write_generic, 982 0x00000000); 983 984 spr_register(env, SPR_440_INV2, "INV2", 985 SPR_NOACCESS, SPR_NOACCESS, 986 &spr_read_generic, &spr_write_generic, 987 0x00000000); 988 989 spr_register(env, SPR_440_INV3, "INV3", 990 SPR_NOACCESS, SPR_NOACCESS, 991 &spr_read_generic, &spr_write_generic, 992 0x00000000); 993 994 spr_register(env, SPR_440_ITV0, "ITV0", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_generic, &spr_write_generic, 997 0x00000000); 998 999 spr_register(env, SPR_440_ITV1, "ITV1", 1000 SPR_NOACCESS, SPR_NOACCESS, 1001 &spr_read_generic, &spr_write_generic, 1002 0x00000000); 1003 1004 spr_register(env, SPR_440_ITV2, "ITV2", 1005 SPR_NOACCESS, SPR_NOACCESS, 1006 &spr_read_generic, &spr_write_generic, 1007 0x00000000); 1008 1009 spr_register(env, SPR_440_ITV3, "ITV3", 1010 SPR_NOACCESS, SPR_NOACCESS, 1011 &spr_read_generic, &spr_write_generic, 1012 0x00000000); 1013 1014 spr_register(env, SPR_440_IVLIM, "IVLIM", 1015 SPR_NOACCESS, SPR_NOACCESS, 1016 &spr_read_generic, &spr_write_generic, 1017 0x00000000); 1018 /* Cache debug */ 1019 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1020 SPR_NOACCESS, SPR_NOACCESS, 1021 &spr_read_generic, SPR_NOACCESS, 1022 0x00000000); 1023 1024 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1025 SPR_NOACCESS, SPR_NOACCESS, 1026 &spr_read_generic, SPR_NOACCESS, 1027 0x00000000); 1028 1029 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1030 SPR_NOACCESS, SPR_NOACCESS, 1031 &spr_read_generic, SPR_NOACCESS, 1032 0x00000000); 1033 1034 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1035 SPR_NOACCESS, SPR_NOACCESS, 1036 &spr_read_generic, SPR_NOACCESS, 1037 0x00000000); 1038 1039 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1040 SPR_NOACCESS, SPR_NOACCESS, 1041 &spr_read_generic, SPR_NOACCESS, 1042 0x00000000); 1043 1044 spr_register(env, SPR_440_DBDR, "DBDR", 1045 SPR_NOACCESS, SPR_NOACCESS, 1046 &spr_read_generic, &spr_write_generic, 1047 0x00000000); 1048 /* Processor control */ 1049 spr_register(env, SPR_4xx_CCR0, "CCR0", 1050 SPR_NOACCESS, SPR_NOACCESS, 1051 &spr_read_generic, &spr_write_generic, 1052 0x00000000); 1053 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1054 SPR_NOACCESS, SPR_NOACCESS, 1055 &spr_read_generic, SPR_NOACCESS, 1056 0x00000000); 1057 /* Storage control */ 1058 spr_register(env, SPR_440_MMUCR, "MMUCR", 1059 SPR_NOACCESS, SPR_NOACCESS, 1060 &spr_read_generic, &spr_write_generic, 1061 0x00000000); 1062 1063 /* Processor identification */ 1064 spr_register(env, SPR_BOOKE_PIR, "PIR", 1065 SPR_NOACCESS, SPR_NOACCESS, 1066 &spr_read_generic, &spr_write_pir, 1067 0x00000000); 1068 1069 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1070 SPR_NOACCESS, SPR_NOACCESS, 1071 &spr_read_generic, &spr_write_generic, 1072 0x00000000); 1073 1074 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1075 SPR_NOACCESS, SPR_NOACCESS, 1076 &spr_read_generic, &spr_write_generic, 1077 0x00000000); 1078 1079 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1080 SPR_NOACCESS, SPR_NOACCESS, 1081 &spr_read_generic, &spr_write_generic, 1082 0x00000000); 1083 1084 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1085 SPR_NOACCESS, SPR_NOACCESS, 1086 &spr_read_generic, &spr_write_generic, 1087 0x00000000); 1088 } 1089 1090 /* SPR shared between PowerPC 40x implementations */ 1091 static void register_40x_sprs(CPUPPCState *env) 1092 { 1093 /* Cache */ 1094 /* not emulated, as QEMU do not emulate caches */ 1095 spr_register(env, SPR_40x_DCCR, "DCCR", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, &spr_write_generic, 1098 0x00000000); 1099 /* not emulated, as QEMU do not emulate caches */ 1100 spr_register(env, SPR_40x_ICCR, "ICCR", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 /* not emulated, as QEMU do not emulate caches */ 1105 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, SPR_NOACCESS, 1108 0x00000000); 1109 /* Exception */ 1110 spr_register(env, SPR_40x_DEAR, "DEAR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_generic, 1113 0x00000000); 1114 spr_register(env, SPR_40x_ESR, "ESR", 1115 SPR_NOACCESS, SPR_NOACCESS, 1116 &spr_read_generic, &spr_write_generic, 1117 0x00000000); 1118 spr_register(env, SPR_40x_EVPR, "EVPR", 1119 SPR_NOACCESS, SPR_NOACCESS, 1120 &spr_read_generic, &spr_write_excp_prefix, 1121 0x00000000); 1122 spr_register(env, SPR_40x_SRR2, "SRR2", 1123 &spr_read_generic, &spr_write_generic, 1124 &spr_read_generic, &spr_write_generic, 1125 0x00000000); 1126 spr_register(env, SPR_40x_SRR3, "SRR3", 1127 &spr_read_generic, &spr_write_generic, 1128 &spr_read_generic, &spr_write_generic, 1129 0x00000000); 1130 /* Timers */ 1131 spr_register(env, SPR_40x_PIT, "PIT", 1132 SPR_NOACCESS, SPR_NOACCESS, 1133 &spr_read_40x_pit, &spr_write_40x_pit, 1134 0x00000000); 1135 spr_register(env, SPR_40x_TCR, "TCR", 1136 SPR_NOACCESS, SPR_NOACCESS, 1137 &spr_read_generic, &spr_write_40x_tcr, 1138 0x00000000); 1139 spr_register(env, SPR_40x_TSR, "TSR", 1140 SPR_NOACCESS, SPR_NOACCESS, 1141 &spr_read_generic, &spr_write_40x_tsr, 1142 0x00000000); 1143 } 1144 1145 /* SPR specific to PowerPC 405 implementation */ 1146 static void register_405_sprs(CPUPPCState *env) 1147 { 1148 /* MMU */ 1149 spr_register(env, SPR_40x_PID, "PID", 1150 SPR_NOACCESS, SPR_NOACCESS, 1151 &spr_read_generic, &spr_write_40x_pid, 1152 0x00000000); 1153 spr_register(env, SPR_4xx_CCR0, "CCR0", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00700000); 1157 /* Debug interface */ 1158 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1159 SPR_NOACCESS, SPR_NOACCESS, 1160 &spr_read_generic, &spr_write_40x_dbcr0, 1161 0x00000000); 1162 1163 spr_register(env, SPR_405_DBCR1, "DBCR1", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_generic, 1166 0x00000000); 1167 1168 spr_register(env, SPR_40x_DBSR, "DBSR", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_clear, 1171 /* Last reset was system reset */ 1172 0x00000300); 1173 1174 spr_register(env, SPR_40x_DAC1, "DAC1", 1175 SPR_NOACCESS, SPR_NOACCESS, 1176 &spr_read_generic, &spr_write_generic, 1177 0x00000000); 1178 spr_register(env, SPR_40x_DAC2, "DAC2", 1179 SPR_NOACCESS, SPR_NOACCESS, 1180 &spr_read_generic, &spr_write_generic, 1181 0x00000000); 1182 1183 spr_register(env, SPR_405_DVC1, "DVC1", 1184 SPR_NOACCESS, SPR_NOACCESS, 1185 &spr_read_generic, &spr_write_generic, 1186 0x00000000); 1187 1188 spr_register(env, SPR_405_DVC2, "DVC2", 1189 SPR_NOACCESS, SPR_NOACCESS, 1190 &spr_read_generic, &spr_write_generic, 1191 0x00000000); 1192 1193 spr_register(env, SPR_40x_IAC1, "IAC1", 1194 SPR_NOACCESS, SPR_NOACCESS, 1195 &spr_read_generic, &spr_write_generic, 1196 0x00000000); 1197 spr_register(env, SPR_40x_IAC2, "IAC2", 1198 SPR_NOACCESS, SPR_NOACCESS, 1199 &spr_read_generic, &spr_write_generic, 1200 0x00000000); 1201 1202 spr_register(env, SPR_405_IAC3, "IAC3", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_generic, 1205 0x00000000); 1206 1207 spr_register(env, SPR_405_IAC4, "IAC4", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_generic, 1210 0x00000000); 1211 /* Storage control */ 1212 spr_register(env, SPR_405_SLER, "SLER", 1213 SPR_NOACCESS, SPR_NOACCESS, 1214 &spr_read_generic, &spr_write_40x_sler, 1215 0x00000000); 1216 spr_register(env, SPR_40x_ZPR, "ZPR", 1217 SPR_NOACCESS, SPR_NOACCESS, 1218 &spr_read_generic, &spr_write_generic, 1219 0x00000000); 1220 1221 spr_register(env, SPR_405_SU0R, "SU0R", 1222 SPR_NOACCESS, SPR_NOACCESS, 1223 &spr_read_generic, &spr_write_generic, 1224 0x00000000); 1225 /* SPRG */ 1226 spr_register(env, SPR_USPRG0, "USPRG0", 1227 &spr_read_ureg, SPR_NOACCESS, 1228 &spr_read_ureg, SPR_NOACCESS, 1229 0x00000000); 1230 spr_register(env, SPR_SPRG4, "SPRG4", 1231 SPR_NOACCESS, SPR_NOACCESS, 1232 &spr_read_generic, &spr_write_generic, 1233 0x00000000); 1234 spr_register(env, SPR_SPRG5, "SPRG5", 1235 SPR_NOACCESS, SPR_NOACCESS, 1236 spr_read_generic, &spr_write_generic, 1237 0x00000000); 1238 spr_register(env, SPR_SPRG6, "SPRG6", 1239 SPR_NOACCESS, SPR_NOACCESS, 1240 spr_read_generic, &spr_write_generic, 1241 0x00000000); 1242 spr_register(env, SPR_SPRG7, "SPRG7", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 1247 /* Bus access control */ 1248 /* not emulated, as QEMU never does speculative access */ 1249 spr_register(env, SPR_40x_SGR, "SGR", 1250 SPR_NOACCESS, SPR_NOACCESS, 1251 &spr_read_generic, &spr_write_generic, 1252 0xFFFFFFFF); 1253 /* not emulated, as QEMU do not emulate caches */ 1254 spr_register(env, SPR_40x_DCWR, "DCWR", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 &spr_read_generic, &spr_write_generic, 1257 0x00000000); 1258 } 1259 1260 1261 static void register_5xx_8xx_sprs(CPUPPCState *env) 1262 { 1263 /* Exception processing */ 1264 spr_register_kvm(env, SPR_DSISR, "DSISR", 1265 SPR_NOACCESS, SPR_NOACCESS, 1266 &spr_read_generic, &spr_write_generic, 1267 KVM_REG_PPC_DSISR, 0x00000000); 1268 spr_register_kvm(env, SPR_DAR, "DAR", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, &spr_write_generic, 1271 KVM_REG_PPC_DAR, 0x00000000); 1272 /* Timer */ 1273 spr_register(env, SPR_DECR, "DECR", 1274 SPR_NOACCESS, SPR_NOACCESS, 1275 &spr_read_decr, &spr_write_decr, 1276 0x00000000); 1277 1278 spr_register(env, SPR_MPC_EIE, "EIE", 1279 SPR_NOACCESS, SPR_NOACCESS, 1280 &spr_read_generic, &spr_write_generic, 1281 0x00000000); 1282 1283 spr_register(env, SPR_MPC_EID, "EID", 1284 SPR_NOACCESS, SPR_NOACCESS, 1285 &spr_read_generic, &spr_write_generic, 1286 0x00000000); 1287 1288 spr_register(env, SPR_MPC_NRI, "NRI", 1289 SPR_NOACCESS, SPR_NOACCESS, 1290 &spr_read_generic, &spr_write_generic, 1291 0x00000000); 1292 1293 spr_register(env, SPR_MPC_CMPA, "CMPA", 1294 SPR_NOACCESS, SPR_NOACCESS, 1295 &spr_read_generic, &spr_write_generic, 1296 0x00000000); 1297 1298 spr_register(env, SPR_MPC_CMPB, "CMPB", 1299 SPR_NOACCESS, SPR_NOACCESS, 1300 &spr_read_generic, &spr_write_generic, 1301 0x00000000); 1302 1303 spr_register(env, SPR_MPC_CMPC, "CMPC", 1304 SPR_NOACCESS, SPR_NOACCESS, 1305 &spr_read_generic, &spr_write_generic, 1306 0x00000000); 1307 1308 spr_register(env, SPR_MPC_CMPD, "CMPD", 1309 SPR_NOACCESS, SPR_NOACCESS, 1310 &spr_read_generic, &spr_write_generic, 1311 0x00000000); 1312 1313 spr_register(env, SPR_MPC_ECR, "ECR", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_generic, &spr_write_generic, 1316 0x00000000); 1317 1318 spr_register(env, SPR_MPC_DER, "DER", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, &spr_write_generic, 1321 0x00000000); 1322 1323 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, &spr_write_generic, 1326 0x00000000); 1327 1328 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 1333 spr_register(env, SPR_MPC_CMPE, "CMPE", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 1338 spr_register(env, SPR_MPC_CMPF, "CMPF", 1339 SPR_NOACCESS, SPR_NOACCESS, 1340 &spr_read_generic, &spr_write_generic, 1341 0x00000000); 1342 1343 spr_register(env, SPR_MPC_CMPG, "CMPG", 1344 SPR_NOACCESS, SPR_NOACCESS, 1345 &spr_read_generic, &spr_write_generic, 1346 0x00000000); 1347 1348 spr_register(env, SPR_MPC_CMPH, "CMPH", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, &spr_write_generic, 1351 0x00000000); 1352 1353 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 1358 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 1363 spr_register(env, SPR_MPC_BAR, "BAR", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, &spr_write_generic, 1366 0x00000000); 1367 1368 spr_register(env, SPR_MPC_DPDR, "DPDR", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 1373 spr_register(env, SPR_MPC_IMMR, "IMMR", 1374 SPR_NOACCESS, SPR_NOACCESS, 1375 &spr_read_generic, &spr_write_generic, 1376 0x00000000); 1377 } 1378 1379 static void register_5xx_sprs(CPUPPCState *env) 1380 { 1381 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, &spr_write_generic, 1384 0x00000000); 1385 1386 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1387 SPR_NOACCESS, SPR_NOACCESS, 1388 &spr_read_generic, &spr_write_generic, 1389 0x00000000); 1390 1391 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1392 SPR_NOACCESS, SPR_NOACCESS, 1393 &spr_read_generic, &spr_write_generic, 1394 0x00000000); 1395 1396 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 &spr_read_generic, &spr_write_generic, 1399 0x00000000); 1400 1401 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 1406 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1407 SPR_NOACCESS, SPR_NOACCESS, 1408 &spr_read_generic, &spr_write_generic, 1409 0x00000000); 1410 1411 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, &spr_write_generic, 1414 0x00000000); 1415 1416 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 &spr_read_generic, &spr_write_generic, 1419 0x00000000); 1420 1421 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1422 SPR_NOACCESS, SPR_NOACCESS, 1423 &spr_read_generic, &spr_write_generic, 1424 0x00000000); 1425 1426 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1427 SPR_NOACCESS, SPR_NOACCESS, 1428 &spr_read_generic, &spr_write_generic, 1429 0x00000000); 1430 1431 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1432 SPR_NOACCESS, SPR_NOACCESS, 1433 &spr_read_generic, &spr_write_generic, 1434 0x00000000); 1435 1436 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1437 SPR_NOACCESS, SPR_NOACCESS, 1438 &spr_read_generic, &spr_write_generic, 1439 0x00000000); 1440 1441 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1442 SPR_NOACCESS, SPR_NOACCESS, 1443 &spr_read_generic, &spr_write_generic, 1444 0x00000000); 1445 1446 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1447 SPR_NOACCESS, SPR_NOACCESS, 1448 &spr_read_generic, &spr_write_generic, 1449 0x00000000); 1450 1451 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1452 SPR_NOACCESS, SPR_NOACCESS, 1453 &spr_read_generic, &spr_write_generic, 1454 0x00000000); 1455 1456 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1457 SPR_NOACCESS, SPR_NOACCESS, 1458 &spr_read_generic, &spr_write_generic, 1459 0x00000000); 1460 1461 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1462 SPR_NOACCESS, SPR_NOACCESS, 1463 &spr_read_generic, &spr_write_generic, 1464 0x00000000); 1465 1466 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_generic, 1469 0x00000000); 1470 1471 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1472 SPR_NOACCESS, SPR_NOACCESS, 1473 &spr_read_generic, &spr_write_generic, 1474 0x00000000); 1475 1476 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1477 SPR_NOACCESS, SPR_NOACCESS, 1478 &spr_read_generic, &spr_write_generic, 1479 0x00000000); 1480 1481 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1482 SPR_NOACCESS, SPR_NOACCESS, 1483 &spr_read_generic, &spr_write_generic, 1484 0x00000000); 1485 } 1486 1487 static void register_8xx_sprs(CPUPPCState *env) 1488 { 1489 1490 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 1495 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 1500 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 1505 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 1510 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 1515 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 1525 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 1530 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1531 SPR_NOACCESS, SPR_NOACCESS, 1532 &spr_read_generic, &spr_write_generic, 1533 0x00000000); 1534 1535 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1536 SPR_NOACCESS, SPR_NOACCESS, 1537 &spr_read_generic, &spr_write_generic, 1538 0x00000000); 1539 1540 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1541 SPR_NOACCESS, SPR_NOACCESS, 1542 &spr_read_generic, &spr_write_generic, 1543 0x00000000); 1544 1545 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_generic, 1548 0x00000000); 1549 1550 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 &spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 1555 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1556 SPR_NOACCESS, SPR_NOACCESS, 1557 &spr_read_generic, &spr_write_generic, 1558 0x00000000); 1559 1560 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1561 SPR_NOACCESS, SPR_NOACCESS, 1562 &spr_read_generic, &spr_write_generic, 1563 0x00000000); 1564 1565 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1566 SPR_NOACCESS, SPR_NOACCESS, 1567 &spr_read_generic, &spr_write_generic, 1568 0x00000000); 1569 1570 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1571 SPR_NOACCESS, SPR_NOACCESS, 1572 &spr_read_generic, &spr_write_generic, 1573 0x00000000); 1574 1575 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 &spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 1580 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1581 SPR_NOACCESS, SPR_NOACCESS, 1582 &spr_read_generic, &spr_write_generic, 1583 0x00000000); 1584 1585 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1586 SPR_NOACCESS, SPR_NOACCESS, 1587 &spr_read_generic, &spr_write_generic, 1588 0x00000000); 1589 1590 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 &spr_read_generic, &spr_write_generic, 1593 0x00000000); 1594 1595 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1596 SPR_NOACCESS, SPR_NOACCESS, 1597 &spr_read_generic, &spr_write_generic, 1598 0x00000000); 1599 1600 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1601 SPR_NOACCESS, SPR_NOACCESS, 1602 &spr_read_generic, &spr_write_generic, 1603 0x00000000); 1604 1605 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1606 SPR_NOACCESS, SPR_NOACCESS, 1607 &spr_read_generic, &spr_write_generic, 1608 0x00000000); 1609 1610 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 &spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 } 1615 1616 /* 1617 * AMR => SPR 29 (Power 2.04) 1618 * CTRL => SPR 136 (Power 2.04) 1619 * CTRL => SPR 152 (Power 2.04) 1620 * SCOMC => SPR 276 (64 bits ?) 1621 * SCOMD => SPR 277 (64 bits ?) 1622 * TBU40 => SPR 286 (Power 2.04 hypv) 1623 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1624 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1625 * HDSISR => SPR 306 (Power 2.04 hypv) 1626 * HDAR => SPR 307 (Power 2.04 hypv) 1627 * PURR => SPR 309 (Power 2.04 hypv) 1628 * HDEC => SPR 310 (Power 2.04 hypv) 1629 * HIOR => SPR 311 (hypv) 1630 * RMOR => SPR 312 (970) 1631 * HRMOR => SPR 313 (Power 2.04 hypv) 1632 * HSRR0 => SPR 314 (Power 2.04 hypv) 1633 * HSRR1 => SPR 315 (Power 2.04 hypv) 1634 * LPIDR => SPR 317 (970) 1635 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1636 * EPR => SPR 702 (Power 2.04 emb) 1637 * perf => 768-783 (Power 2.04) 1638 * perf => 784-799 (Power 2.04) 1639 * PPR => SPR 896 (Power 2.04) 1640 * DABRX => 1015 (Power 2.04 hypv) 1641 * FPECR => SPR 1022 (?) 1642 * ... and more (thermal management, performance counters, ...) 1643 */ 1644 1645 /*****************************************************************************/ 1646 /* Exception vectors models */ 1647 static void init_excp_4xx(CPUPPCState *env) 1648 { 1649 #if !defined(CONFIG_USER_ONLY) 1650 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1651 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1652 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1653 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1654 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1655 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1656 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1657 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1658 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1659 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1660 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1661 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1662 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1663 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1664 env->ivor_mask = 0x0000FFF0UL; 1665 env->ivpr_mask = 0xFFFF0000UL; 1666 /* Hardware reset vector */ 1667 env->hreset_vector = 0xFFFFFFFCUL; 1668 #endif 1669 } 1670 1671 static void init_excp_MPC5xx(CPUPPCState *env) 1672 { 1673 #if !defined(CONFIG_USER_ONLY) 1674 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1675 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1676 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1677 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1678 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1679 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1680 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1681 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1682 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1683 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1684 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1685 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1686 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1687 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1688 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1689 env->ivor_mask = 0x0000FFF0UL; 1690 env->ivpr_mask = 0xFFFF0000UL; 1691 /* Hardware reset vector */ 1692 env->hreset_vector = 0x00000100UL; 1693 #endif 1694 } 1695 1696 static void init_excp_MPC8xx(CPUPPCState *env) 1697 { 1698 #if !defined(CONFIG_USER_ONLY) 1699 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1700 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1701 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1702 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1703 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1704 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1705 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1706 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1707 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1709 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1710 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1711 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1713 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1714 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1715 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1716 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1717 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1718 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1719 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1720 env->ivor_mask = 0x0000FFF0UL; 1721 env->ivpr_mask = 0xFFFF0000UL; 1722 /* Hardware reset vector */ 1723 env->hreset_vector = 0x00000100UL; 1724 #endif 1725 } 1726 1727 static void init_excp_G2(CPUPPCState *env) 1728 { 1729 #if !defined(CONFIG_USER_ONLY) 1730 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1731 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1732 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1733 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1734 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1735 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1736 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1737 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1738 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1739 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1740 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1741 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1742 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1743 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1744 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1745 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1746 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1747 /* Hardware reset vector */ 1748 env->hreset_vector = 0x00000100UL; 1749 #endif 1750 } 1751 1752 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1753 { 1754 #if !defined(CONFIG_USER_ONLY) 1755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1772 /* 1773 * These two are the same IVOR as POWERPC_EXCP_VPU and 1774 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1775 * powerpc_excp(). 1776 */ 1777 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1778 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1779 1780 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1781 env->ivor_mask = 0x0000FFF7UL; 1782 env->ivpr_mask = ivpr_mask; 1783 /* Hardware reset vector */ 1784 env->hreset_vector = 0xFFFFFFFCUL; 1785 #endif 1786 } 1787 1788 static void init_excp_BookE(CPUPPCState *env) 1789 { 1790 #if !defined(CONFIG_USER_ONLY) 1791 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1792 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1793 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1794 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1795 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1796 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1797 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1798 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1799 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1800 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1801 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1802 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1803 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1805 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1806 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1807 env->ivor_mask = 0x0000FFF0UL; 1808 env->ivpr_mask = 0xFFFF0000UL; 1809 /* Hardware reset vector */ 1810 env->hreset_vector = 0xFFFFFFFCUL; 1811 #endif 1812 } 1813 1814 static void init_excp_603(CPUPPCState *env) 1815 { 1816 #if !defined(CONFIG_USER_ONLY) 1817 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1818 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1819 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1820 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1821 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1822 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1823 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1824 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1825 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1826 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1827 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1828 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1829 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1830 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1831 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1832 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1833 /* Hardware reset vector */ 1834 env->hreset_vector = 0x00000100UL; 1835 #endif 1836 } 1837 1838 static void init_excp_604(CPUPPCState *env) 1839 { 1840 #if !defined(CONFIG_USER_ONLY) 1841 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1849 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1850 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1851 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1852 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1853 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1854 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1855 /* Hardware reset vector */ 1856 env->hreset_vector = 0x00000100UL; 1857 #endif 1858 } 1859 1860 static void init_excp_7x0(CPUPPCState *env) 1861 { 1862 #if !defined(CONFIG_USER_ONLY) 1863 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1864 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1865 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1866 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1867 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1868 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1869 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1870 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1871 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1872 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1873 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1874 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1875 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1876 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1877 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1878 /* Hardware reset vector */ 1879 env->hreset_vector = 0x00000100UL; 1880 #endif 1881 } 1882 1883 static void init_excp_750cl(CPUPPCState *env) 1884 { 1885 #if !defined(CONFIG_USER_ONLY) 1886 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1887 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1888 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1889 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1890 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1891 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1892 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1893 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1894 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1895 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1896 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1897 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1900 /* Hardware reset vector */ 1901 env->hreset_vector = 0x00000100UL; 1902 #endif 1903 } 1904 1905 static void init_excp_750cx(CPUPPCState *env) 1906 { 1907 #if !defined(CONFIG_USER_ONLY) 1908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1918 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1919 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1920 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1921 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1922 /* Hardware reset vector */ 1923 env->hreset_vector = 0x00000100UL; 1924 #endif 1925 } 1926 1927 /* XXX: Check if this is correct */ 1928 static void init_excp_7x5(CPUPPCState *env) 1929 { 1930 #if !defined(CONFIG_USER_ONLY) 1931 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1932 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1933 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1934 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1935 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1936 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1937 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1938 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1939 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1940 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1941 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1942 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1943 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1944 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1945 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1946 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1947 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1948 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1949 /* Hardware reset vector */ 1950 env->hreset_vector = 0x00000100UL; 1951 #endif 1952 } 1953 1954 static void init_excp_7400(CPUPPCState *env) 1955 { 1956 #if !defined(CONFIG_USER_ONLY) 1957 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1958 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1959 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1960 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1961 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1962 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1963 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1964 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1965 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1966 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1967 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1968 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1969 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1970 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1971 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1972 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1973 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1974 /* Hardware reset vector */ 1975 env->hreset_vector = 0x00000100UL; 1976 #endif 1977 } 1978 1979 static void init_excp_7450(CPUPPCState *env) 1980 { 1981 #if !defined(CONFIG_USER_ONLY) 1982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1994 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1998 /* Hardware reset vector */ 1999 env->hreset_vector = 0x00000100UL; 2000 #endif 2001 } 2002 2003 #if defined(TARGET_PPC64) 2004 static void init_excp_970(CPUPPCState *env) 2005 { 2006 #if !defined(CONFIG_USER_ONLY) 2007 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2008 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2009 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2010 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2012 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2018 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2021 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2022 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2024 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2025 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2026 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2027 /* Hardware reset vector */ 2028 env->hreset_vector = 0x0000000000000100ULL; 2029 #endif 2030 } 2031 2032 static void init_excp_POWER7(CPUPPCState *env) 2033 { 2034 #if !defined(CONFIG_USER_ONLY) 2035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2049 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2050 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2051 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2052 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2053 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2054 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2055 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2056 /* Hardware reset vector */ 2057 env->hreset_vector = 0x0000000000000100ULL; 2058 #endif 2059 } 2060 2061 static void init_excp_POWER8(CPUPPCState *env) 2062 { 2063 init_excp_POWER7(env); 2064 2065 #if !defined(CONFIG_USER_ONLY) 2066 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2067 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2068 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2069 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2070 2071 /* Userland exceptions without vector value in PowerISA v3.1 */ 2072 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2073 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2074 #endif 2075 } 2076 2077 static void init_excp_POWER9(CPUPPCState *env) 2078 { 2079 init_excp_POWER8(env); 2080 2081 #if !defined(CONFIG_USER_ONLY) 2082 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2083 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2084 #endif 2085 } 2086 2087 static void init_excp_POWER10(CPUPPCState *env) 2088 { 2089 init_excp_POWER9(env); 2090 } 2091 2092 #endif 2093 2094 static int check_pow_hid0(CPUPPCState *env) 2095 { 2096 if (env->spr[SPR_HID0] & 0x00E00000) { 2097 return 1; 2098 } 2099 2100 return 0; 2101 } 2102 2103 static int check_pow_hid0_74xx(CPUPPCState *env) 2104 { 2105 if (env->spr[SPR_HID0] & 0x00600000) { 2106 return 1; 2107 } 2108 2109 return 0; 2110 } 2111 2112 #if defined(TARGET_PPC64) 2113 static int check_attn_hid0(CPUPPCState *env) 2114 { 2115 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2116 return 1; 2117 } 2118 2119 return 0; 2120 } 2121 2122 static int check_attn_hid0_power9(CPUPPCState *env) 2123 { 2124 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2125 return 1; 2126 } 2127 2128 return 0; 2129 } 2130 #endif 2131 2132 static void init_tlbs_emb(CPUPPCState *env) 2133 { 2134 #ifndef CONFIG_USER_ONLY 2135 env->nb_tlb = 64; 2136 env->nb_ways = 1; 2137 env->tlb_type = TLB_EMB; 2138 #endif 2139 } 2140 2141 static void init_proc_405(CPUPPCState *env) 2142 { 2143 register_40x_sprs(env); 2144 register_405_sprs(env); 2145 register_usprgh_sprs(env); 2146 2147 init_tlbs_emb(env); 2148 init_excp_4xx(env); 2149 env->dcache_line_size = 32; 2150 env->icache_line_size = 32; 2151 /* Allocate hardware IRQ controller */ 2152 ppc40x_irq_init(env_archcpu(env)); 2153 2154 SET_FIT_PERIOD(8, 12, 16, 20); 2155 SET_WDT_PERIOD(16, 20, 24, 28); 2156 } 2157 2158 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2159 { 2160 DeviceClass *dc = DEVICE_CLASS(oc); 2161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2162 2163 dc->desc = "PowerPC 405"; 2164 pcc->init_proc = init_proc_405; 2165 pcc->check_pow = check_pow_nocheck; 2166 pcc->check_attn = check_attn_none; 2167 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2168 PPC_DCR | PPC_WRTEE | 2169 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2170 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2171 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2172 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2173 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2174 pcc->msr_mask = (1ull << MSR_WE) | 2175 (1ull << MSR_CE) | 2176 (1ull << MSR_EE) | 2177 (1ull << MSR_PR) | 2178 (1ull << MSR_FP) | 2179 (1ull << MSR_ME) | 2180 (1ull << MSR_DWE) | 2181 (1ull << MSR_DE) | 2182 (1ull << MSR_IR) | 2183 (1ull << MSR_DR); 2184 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2185 pcc->excp_model = POWERPC_EXCP_40x; 2186 pcc->bus_model = PPC_FLAGS_INPUT_405; 2187 pcc->bfd_mach = bfd_mach_ppc_403; 2188 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2189 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2190 } 2191 2192 static void init_proc_440EP(CPUPPCState *env) 2193 { 2194 register_BookE_sprs(env, 0x000000000000FFFFULL); 2195 register_440_sprs(env); 2196 register_usprgh_sprs(env); 2197 2198 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2199 SPR_NOACCESS, SPR_NOACCESS, 2200 &spr_read_generic, &spr_write_generic, 2201 0x00000000); 2202 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2203 SPR_NOACCESS, SPR_NOACCESS, 2204 &spr_read_generic, &spr_write_generic, 2205 0x00000000); 2206 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2207 SPR_NOACCESS, SPR_NOACCESS, 2208 &spr_read_generic, &spr_write_generic, 2209 0x00000000); 2210 2211 spr_register(env, SPR_440_CCR1, "CCR1", 2212 SPR_NOACCESS, SPR_NOACCESS, 2213 &spr_read_generic, &spr_write_generic, 2214 0x00000000); 2215 2216 init_tlbs_emb(env); 2217 init_excp_BookE(env); 2218 env->dcache_line_size = 32; 2219 env->icache_line_size = 32; 2220 ppc40x_irq_init(env_archcpu(env)); 2221 2222 SET_FIT_PERIOD(12, 16, 20, 24); 2223 SET_WDT_PERIOD(20, 24, 28, 32); 2224 } 2225 2226 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2227 { 2228 DeviceClass *dc = DEVICE_CLASS(oc); 2229 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2230 2231 dc->desc = "PowerPC 440 EP"; 2232 pcc->init_proc = init_proc_440EP; 2233 pcc->check_pow = check_pow_nocheck; 2234 pcc->check_attn = check_attn_none; 2235 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2236 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2237 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2238 PPC_FLOAT_STFIWX | 2239 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2240 PPC_CACHE | PPC_CACHE_ICBI | 2241 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2242 PPC_MEM_TLBSYNC | PPC_MFTB | 2243 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2244 PPC_440_SPEC; 2245 pcc->msr_mask = (1ull << MSR_POW) | 2246 (1ull << MSR_CE) | 2247 (1ull << MSR_EE) | 2248 (1ull << MSR_PR) | 2249 (1ull << MSR_FP) | 2250 (1ull << MSR_ME) | 2251 (1ull << MSR_FE0) | 2252 (1ull << MSR_DWE) | 2253 (1ull << MSR_DE) | 2254 (1ull << MSR_FE1) | 2255 (1ull << MSR_IR) | 2256 (1ull << MSR_DR); 2257 pcc->mmu_model = POWERPC_MMU_BOOKE; 2258 pcc->excp_model = POWERPC_EXCP_BOOKE; 2259 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2260 pcc->bfd_mach = bfd_mach_ppc_403; 2261 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2262 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2263 } 2264 2265 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2266 { 2267 DeviceClass *dc = DEVICE_CLASS(oc); 2268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2269 2270 dc->desc = "PowerPC 460 EX"; 2271 pcc->init_proc = init_proc_440EP; 2272 pcc->check_pow = check_pow_nocheck; 2273 pcc->check_attn = check_attn_none; 2274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2275 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2276 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2277 PPC_FLOAT_STFIWX | 2278 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2279 PPC_CACHE | PPC_CACHE_ICBI | 2280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2281 PPC_MEM_TLBSYNC | PPC_MFTB | 2282 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2283 PPC_440_SPEC; 2284 pcc->msr_mask = (1ull << MSR_POW) | 2285 (1ull << MSR_CE) | 2286 (1ull << MSR_EE) | 2287 (1ull << MSR_PR) | 2288 (1ull << MSR_FP) | 2289 (1ull << MSR_ME) | 2290 (1ull << MSR_FE0) | 2291 (1ull << MSR_DWE) | 2292 (1ull << MSR_DE) | 2293 (1ull << MSR_FE1) | 2294 (1ull << MSR_IR) | 2295 (1ull << MSR_DR); 2296 pcc->mmu_model = POWERPC_MMU_BOOKE; 2297 pcc->excp_model = POWERPC_EXCP_BOOKE; 2298 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2299 pcc->bfd_mach = bfd_mach_ppc_403; 2300 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2301 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2302 } 2303 2304 static void init_proc_440GP(CPUPPCState *env) 2305 { 2306 register_BookE_sprs(env, 0x000000000000FFFFULL); 2307 register_440_sprs(env); 2308 register_usprgh_sprs(env); 2309 2310 init_tlbs_emb(env); 2311 init_excp_BookE(env); 2312 env->dcache_line_size = 32; 2313 env->icache_line_size = 32; 2314 /* XXX: TODO: allocate internal IRQ controller */ 2315 2316 SET_FIT_PERIOD(12, 16, 20, 24); 2317 SET_WDT_PERIOD(20, 24, 28, 32); 2318 } 2319 2320 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2321 { 2322 DeviceClass *dc = DEVICE_CLASS(oc); 2323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2324 2325 dc->desc = "PowerPC 440 GP"; 2326 pcc->init_proc = init_proc_440GP; 2327 pcc->check_pow = check_pow_nocheck; 2328 pcc->check_attn = check_attn_none; 2329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2330 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2331 PPC_CACHE | PPC_CACHE_ICBI | 2332 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2333 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2334 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2335 PPC_440_SPEC; 2336 pcc->msr_mask = (1ull << MSR_POW) | 2337 (1ull << MSR_CE) | 2338 (1ull << MSR_EE) | 2339 (1ull << MSR_PR) | 2340 (1ull << MSR_FP) | 2341 (1ull << MSR_ME) | 2342 (1ull << MSR_FE0) | 2343 (1ull << MSR_DWE) | 2344 (1ull << MSR_DE) | 2345 (1ull << MSR_FE1) | 2346 (1ull << MSR_IR) | 2347 (1ull << MSR_DR); 2348 pcc->mmu_model = POWERPC_MMU_BOOKE; 2349 pcc->excp_model = POWERPC_EXCP_BOOKE; 2350 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2351 pcc->bfd_mach = bfd_mach_ppc_403; 2352 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2353 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2354 } 2355 2356 static void init_proc_440x5(CPUPPCState *env) 2357 { 2358 register_BookE_sprs(env, 0x000000000000FFFFULL); 2359 register_440_sprs(env); 2360 register_usprgh_sprs(env); 2361 2362 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2363 SPR_NOACCESS, SPR_NOACCESS, 2364 &spr_read_generic, &spr_write_generic, 2365 0x00000000); 2366 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2367 SPR_NOACCESS, SPR_NOACCESS, 2368 &spr_read_generic, &spr_write_generic, 2369 0x00000000); 2370 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2371 SPR_NOACCESS, SPR_NOACCESS, 2372 &spr_read_generic, &spr_write_generic, 2373 0x00000000); 2374 2375 spr_register(env, SPR_440_CCR1, "CCR1", 2376 SPR_NOACCESS, SPR_NOACCESS, 2377 &spr_read_generic, &spr_write_generic, 2378 0x00000000); 2379 2380 init_tlbs_emb(env); 2381 init_excp_BookE(env); 2382 env->dcache_line_size = 32; 2383 env->icache_line_size = 32; 2384 ppc40x_irq_init(env_archcpu(env)); 2385 2386 SET_FIT_PERIOD(12, 16, 20, 24); 2387 SET_WDT_PERIOD(20, 24, 28, 32); 2388 } 2389 2390 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2391 { 2392 DeviceClass *dc = DEVICE_CLASS(oc); 2393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2394 2395 dc->desc = "PowerPC 440x5"; 2396 pcc->init_proc = init_proc_440x5; 2397 pcc->check_pow = check_pow_nocheck; 2398 pcc->check_attn = check_attn_none; 2399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2400 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2401 PPC_CACHE | PPC_CACHE_ICBI | 2402 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2403 PPC_MEM_TLBSYNC | PPC_MFTB | 2404 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2405 PPC_440_SPEC; 2406 pcc->msr_mask = (1ull << MSR_POW) | 2407 (1ull << MSR_CE) | 2408 (1ull << MSR_EE) | 2409 (1ull << MSR_PR) | 2410 (1ull << MSR_FP) | 2411 (1ull << MSR_ME) | 2412 (1ull << MSR_FE0) | 2413 (1ull << MSR_DWE) | 2414 (1ull << MSR_DE) | 2415 (1ull << MSR_FE1) | 2416 (1ull << MSR_IR) | 2417 (1ull << MSR_DR); 2418 pcc->mmu_model = POWERPC_MMU_BOOKE; 2419 pcc->excp_model = POWERPC_EXCP_BOOKE; 2420 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2421 pcc->bfd_mach = bfd_mach_ppc_403; 2422 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2423 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2424 } 2425 2426 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2427 { 2428 DeviceClass *dc = DEVICE_CLASS(oc); 2429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2430 2431 dc->desc = "PowerPC 440x5 with double precision FPU"; 2432 pcc->init_proc = init_proc_440x5; 2433 pcc->check_pow = check_pow_nocheck; 2434 pcc->check_attn = check_attn_none; 2435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2436 PPC_FLOAT | PPC_FLOAT_FSQRT | 2437 PPC_FLOAT_STFIWX | 2438 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2439 PPC_CACHE | PPC_CACHE_ICBI | 2440 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2441 PPC_MEM_TLBSYNC | PPC_MFTB | 2442 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2443 PPC_440_SPEC; 2444 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2445 pcc->msr_mask = (1ull << MSR_POW) | 2446 (1ull << MSR_CE) | 2447 (1ull << MSR_EE) | 2448 (1ull << MSR_PR) | 2449 (1ull << MSR_FP) | 2450 (1ull << MSR_ME) | 2451 (1ull << MSR_FE0) | 2452 (1ull << MSR_DWE) | 2453 (1ull << MSR_DE) | 2454 (1ull << MSR_FE1) | 2455 (1ull << MSR_IR) | 2456 (1ull << MSR_DR); 2457 pcc->mmu_model = POWERPC_MMU_BOOKE; 2458 pcc->excp_model = POWERPC_EXCP_BOOKE; 2459 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2460 pcc->bfd_mach = bfd_mach_ppc_403; 2461 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2462 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2463 } 2464 2465 static void init_proc_MPC5xx(CPUPPCState *env) 2466 { 2467 register_5xx_8xx_sprs(env); 2468 register_5xx_sprs(env); 2469 init_excp_MPC5xx(env); 2470 env->dcache_line_size = 32; 2471 env->icache_line_size = 32; 2472 /* XXX: TODO: allocate internal IRQ controller */ 2473 } 2474 2475 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2476 { 2477 DeviceClass *dc = DEVICE_CLASS(oc); 2478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2479 2480 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2481 pcc->init_proc = init_proc_MPC5xx; 2482 pcc->check_pow = check_pow_none; 2483 pcc->check_attn = check_attn_none; 2484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2485 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2486 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2487 PPC_MFTB; 2488 pcc->msr_mask = (1ull << MSR_ILE) | 2489 (1ull << MSR_EE) | 2490 (1ull << MSR_PR) | 2491 (1ull << MSR_FP) | 2492 (1ull << MSR_ME) | 2493 (1ull << MSR_FE0) | 2494 (1ull << MSR_SE) | 2495 (1ull << MSR_DE) | 2496 (1ull << MSR_FE1) | 2497 (1ull << MSR_EP) | 2498 (1ull << MSR_RI) | 2499 (1ull << MSR_LE); 2500 pcc->mmu_model = POWERPC_MMU_REAL; 2501 pcc->excp_model = POWERPC_EXCP_6xx; 2502 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2503 pcc->bfd_mach = bfd_mach_ppc_505; 2504 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2505 POWERPC_FLAG_BUS_CLK; 2506 } 2507 2508 static void init_proc_MPC8xx(CPUPPCState *env) 2509 { 2510 register_5xx_8xx_sprs(env); 2511 register_8xx_sprs(env); 2512 init_excp_MPC8xx(env); 2513 env->dcache_line_size = 32; 2514 env->icache_line_size = 32; 2515 /* XXX: TODO: allocate internal IRQ controller */ 2516 } 2517 2518 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2519 { 2520 DeviceClass *dc = DEVICE_CLASS(oc); 2521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2522 2523 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2524 pcc->init_proc = init_proc_MPC8xx; 2525 pcc->check_pow = check_pow_none; 2526 pcc->check_attn = check_attn_none; 2527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2528 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2529 PPC_CACHE_ICBI | PPC_MFTB; 2530 pcc->msr_mask = (1ull << MSR_ILE) | 2531 (1ull << MSR_EE) | 2532 (1ull << MSR_PR) | 2533 (1ull << MSR_FP) | 2534 (1ull << MSR_ME) | 2535 (1ull << MSR_SE) | 2536 (1ull << MSR_DE) | 2537 (1ull << MSR_EP) | 2538 (1ull << MSR_IR) | 2539 (1ull << MSR_DR) | 2540 (1ull << MSR_RI) | 2541 (1ull << MSR_LE); 2542 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2543 pcc->excp_model = POWERPC_EXCP_6xx; 2544 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2545 pcc->bfd_mach = bfd_mach_ppc_860; 2546 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2547 POWERPC_FLAG_BUS_CLK; 2548 } 2549 2550 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2551 2552 static void init_proc_G2(CPUPPCState *env) 2553 { 2554 register_non_embedded_sprs(env); 2555 register_sdr1_sprs(env); 2556 register_G2_sprs(env); 2557 2558 /* Memory management */ 2559 register_low_BATs(env); 2560 register_high_BATs(env); 2561 register_6xx_7xx_soft_tlb(env, 64, 2); 2562 init_excp_G2(env); 2563 env->dcache_line_size = 32; 2564 env->icache_line_size = 32; 2565 /* Allocate hardware IRQ controller */ 2566 ppc6xx_irq_init(env_archcpu(env)); 2567 } 2568 2569 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2570 { 2571 DeviceClass *dc = DEVICE_CLASS(oc); 2572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2573 2574 dc->desc = "PowerPC G2"; 2575 pcc->init_proc = init_proc_G2; 2576 pcc->check_pow = check_pow_hid0; 2577 pcc->check_attn = check_attn_none; 2578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2580 PPC_FLOAT_STFIWX | 2581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2582 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2584 PPC_SEGMENT | PPC_EXTERN; 2585 pcc->msr_mask = (1ull << MSR_POW) | 2586 (1ull << MSR_TGPR) | 2587 (1ull << MSR_EE) | 2588 (1ull << MSR_PR) | 2589 (1ull << MSR_FP) | 2590 (1ull << MSR_ME) | 2591 (1ull << MSR_FE0) | 2592 (1ull << MSR_SE) | 2593 (1ull << MSR_DE) | 2594 (1ull << MSR_FE1) | 2595 (1ull << MSR_AL) | 2596 (1ull << MSR_EP) | 2597 (1ull << MSR_IR) | 2598 (1ull << MSR_DR) | 2599 (1ull << MSR_RI); 2600 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2601 pcc->excp_model = POWERPC_EXCP_6xx; 2602 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2603 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2604 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2605 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2606 } 2607 2608 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2609 { 2610 DeviceClass *dc = DEVICE_CLASS(oc); 2611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2612 2613 dc->desc = "PowerPC G2LE"; 2614 pcc->init_proc = init_proc_G2; 2615 pcc->check_pow = check_pow_hid0; 2616 pcc->check_attn = check_attn_none; 2617 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2618 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2619 PPC_FLOAT_STFIWX | 2620 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2621 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2622 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2623 PPC_SEGMENT | PPC_EXTERN; 2624 pcc->msr_mask = (1ull << MSR_POW) | 2625 (1ull << MSR_TGPR) | 2626 (1ull << MSR_ILE) | 2627 (1ull << MSR_EE) | 2628 (1ull << MSR_PR) | 2629 (1ull << MSR_FP) | 2630 (1ull << MSR_ME) | 2631 (1ull << MSR_FE0) | 2632 (1ull << MSR_SE) | 2633 (1ull << MSR_DE) | 2634 (1ull << MSR_FE1) | 2635 (1ull << MSR_AL) | 2636 (1ull << MSR_EP) | 2637 (1ull << MSR_IR) | 2638 (1ull << MSR_DR) | 2639 (1ull << MSR_RI) | 2640 (1ull << MSR_LE); 2641 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2642 pcc->excp_model = POWERPC_EXCP_6xx; 2643 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2644 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2645 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2646 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2647 } 2648 2649 static void init_proc_e200(CPUPPCState *env) 2650 { 2651 register_BookE_sprs(env, 0x000000070000FFFFULL); 2652 2653 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2654 &spr_read_spefscr, &spr_write_spefscr, 2655 &spr_read_spefscr, &spr_write_spefscr, 2656 0x00000000); 2657 /* Memory management */ 2658 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2659 register_usprgh_sprs(env); 2660 2661 spr_register(env, SPR_HID0, "HID0", 2662 SPR_NOACCESS, SPR_NOACCESS, 2663 &spr_read_generic, &spr_write_generic, 2664 0x00000000); 2665 2666 spr_register(env, SPR_HID1, "HID1", 2667 SPR_NOACCESS, SPR_NOACCESS, 2668 &spr_read_generic, &spr_write_generic, 2669 0x00000000); 2670 2671 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2672 SPR_NOACCESS, SPR_NOACCESS, 2673 &spr_read_generic, &spr_write_generic, 2674 0x00000000); 2675 2676 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2677 SPR_NOACCESS, SPR_NOACCESS, 2678 &spr_read_generic, &spr_write_generic, 2679 0x00000000); 2680 2681 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2682 SPR_NOACCESS, SPR_NOACCESS, 2683 &spr_read_generic, &spr_write_generic, 2684 0x00000000); 2685 2686 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2687 SPR_NOACCESS, SPR_NOACCESS, 2688 &spr_read_generic, &spr_write_generic, 2689 0x00000000); 2690 2691 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2692 SPR_NOACCESS, SPR_NOACCESS, 2693 &spr_read_generic, &spr_write_generic, 2694 0x00000000); 2695 2696 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2697 &spr_read_generic, SPR_NOACCESS, 2698 &spr_read_generic, SPR_NOACCESS, 2699 0x00000000); 2700 2701 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2702 SPR_NOACCESS, SPR_NOACCESS, 2703 &spr_read_generic, &spr_write_generic, 2704 0x00000000); 2705 2706 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2707 SPR_NOACCESS, SPR_NOACCESS, 2708 &spr_read_generic, &spr_write_generic, 2709 0x00000000); 2710 2711 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2712 SPR_NOACCESS, SPR_NOACCESS, 2713 &spr_read_generic, &spr_write_generic, 2714 0x00000000); 2715 2716 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2717 SPR_NOACCESS, SPR_NOACCESS, 2718 &spr_read_generic, &spr_write_generic, 2719 0x00000000); 2720 2721 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2722 SPR_NOACCESS, SPR_NOACCESS, 2723 &spr_read_generic, &spr_write_generic, 2724 0x00000000); 2725 2726 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2727 SPR_NOACCESS, SPR_NOACCESS, 2728 &spr_read_generic, &spr_write_generic, 2729 0x00000000); 2730 2731 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2732 SPR_NOACCESS, SPR_NOACCESS, 2733 &spr_read_generic, &spr_write_generic, 2734 0x00000000); /* TOFIX */ 2735 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2736 SPR_NOACCESS, SPR_NOACCESS, 2737 &spr_read_generic, &spr_write_generic, 2738 0x00000000); 2739 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2740 SPR_NOACCESS, SPR_NOACCESS, 2741 &spr_read_generic, &spr_write_generic, 2742 0x00000000); 2743 2744 init_tlbs_emb(env); 2745 init_excp_e200(env, 0xFFFF0000UL); 2746 env->dcache_line_size = 32; 2747 env->icache_line_size = 32; 2748 /* XXX: TODO: allocate internal IRQ controller */ 2749 } 2750 2751 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2752 { 2753 DeviceClass *dc = DEVICE_CLASS(oc); 2754 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2755 2756 dc->desc = "e200 core"; 2757 pcc->init_proc = init_proc_e200; 2758 pcc->check_pow = check_pow_hid0; 2759 pcc->check_attn = check_attn_none; 2760 /* 2761 * XXX: unimplemented instructions: 2762 * dcblc 2763 * dcbtlst 2764 * dcbtstls 2765 * icblc 2766 * icbtls 2767 * tlbivax 2768 * all SPE multiply-accumulate instructions 2769 */ 2770 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2771 PPC_SPE | PPC_SPE_SINGLE | 2772 PPC_WRTEE | PPC_RFDI | 2773 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2775 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2776 PPC_BOOKE; 2777 pcc->msr_mask = (1ull << MSR_UCLE) | 2778 (1ull << MSR_SPE) | 2779 (1ull << MSR_POW) | 2780 (1ull << MSR_CE) | 2781 (1ull << MSR_EE) | 2782 (1ull << MSR_PR) | 2783 (1ull << MSR_FP) | 2784 (1ull << MSR_ME) | 2785 (1ull << MSR_FE0) | 2786 (1ull << MSR_DWE) | 2787 (1ull << MSR_DE) | 2788 (1ull << MSR_FE1) | 2789 (1ull << MSR_IR) | 2790 (1ull << MSR_DR); 2791 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2792 pcc->excp_model = POWERPC_EXCP_BOOKE; 2793 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2794 pcc->bfd_mach = bfd_mach_ppc_860; 2795 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2796 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2797 POWERPC_FLAG_BUS_CLK; 2798 } 2799 2800 enum fsl_e500_version { 2801 fsl_e500v1, 2802 fsl_e500v2, 2803 fsl_e500mc, 2804 fsl_e5500, 2805 fsl_e6500, 2806 }; 2807 2808 static void init_proc_e500(CPUPPCState *env, int version) 2809 { 2810 uint32_t tlbncfg[2]; 2811 uint64_t ivor_mask; 2812 uint64_t ivpr_mask = 0xFFFF0000ULL; 2813 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2814 | 0x0020; /* 32 kb */ 2815 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2816 | 0x0020; /* 32 kb */ 2817 uint32_t mmucfg = 0; 2818 #if !defined(CONFIG_USER_ONLY) 2819 int i; 2820 #endif 2821 2822 /* 2823 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2824 * complain when accessing them. 2825 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2826 */ 2827 switch (version) { 2828 case fsl_e500v1: 2829 case fsl_e500v2: 2830 default: 2831 ivor_mask = 0x0000000F0000FFFFULL; 2832 break; 2833 case fsl_e500mc: 2834 case fsl_e5500: 2835 ivor_mask = 0x000003FE0000FFFFULL; 2836 break; 2837 case fsl_e6500: 2838 ivor_mask = 0x000003FF0000FFFFULL; 2839 break; 2840 } 2841 register_BookE_sprs(env, ivor_mask); 2842 2843 spr_register(env, SPR_USPRG3, "USPRG3", 2844 &spr_read_ureg, SPR_NOACCESS, 2845 &spr_read_ureg, SPR_NOACCESS, 2846 0x00000000); 2847 2848 /* Processor identification */ 2849 spr_register(env, SPR_BOOKE_PIR, "PIR", 2850 SPR_NOACCESS, SPR_NOACCESS, 2851 &spr_read_generic, &spr_write_pir, 2852 0x00000000); 2853 2854 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2855 &spr_read_spefscr, &spr_write_spefscr, 2856 &spr_read_spefscr, &spr_write_spefscr, 2857 0x00000000); 2858 #if !defined(CONFIG_USER_ONLY) 2859 /* Memory management */ 2860 env->nb_pids = 3; 2861 env->nb_ways = 2; 2862 switch (version) { 2863 case fsl_e500v1: 2864 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2865 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2866 break; 2867 case fsl_e500v2: 2868 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2869 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2870 break; 2871 case fsl_e500mc: 2872 case fsl_e5500: 2873 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2874 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2875 break; 2876 case fsl_e6500: 2877 mmucfg = 0x6510B45; 2878 env->nb_pids = 1; 2879 tlbncfg[0] = 0x08052400; 2880 tlbncfg[1] = 0x40028040; 2881 break; 2882 default: 2883 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2884 env->spr[SPR_PVR]); 2885 } 2886 #endif 2887 /* Cache sizes */ 2888 switch (version) { 2889 case fsl_e500v1: 2890 case fsl_e500v2: 2891 env->dcache_line_size = 32; 2892 env->icache_line_size = 32; 2893 break; 2894 case fsl_e500mc: 2895 case fsl_e5500: 2896 env->dcache_line_size = 64; 2897 env->icache_line_size = 64; 2898 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2899 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2900 break; 2901 case fsl_e6500: 2902 env->dcache_line_size = 32; 2903 env->icache_line_size = 32; 2904 l1cfg0 |= 0x0F83820; 2905 l1cfg1 |= 0x0B83820; 2906 break; 2907 default: 2908 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2909 env->spr[SPR_PVR]); 2910 } 2911 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2912 register_usprgh_sprs(env); 2913 2914 spr_register(env, SPR_HID0, "HID0", 2915 SPR_NOACCESS, SPR_NOACCESS, 2916 &spr_read_generic, &spr_write_generic, 2917 0x00000000); 2918 2919 spr_register(env, SPR_HID1, "HID1", 2920 SPR_NOACCESS, SPR_NOACCESS, 2921 &spr_read_generic, &spr_write_generic, 2922 0x00000000); 2923 2924 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2925 SPR_NOACCESS, SPR_NOACCESS, 2926 &spr_read_generic, &spr_write_generic, 2927 0x00000000); 2928 2929 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2930 SPR_NOACCESS, SPR_NOACCESS, 2931 &spr_read_generic, &spr_write_generic, 2932 0x00000000); 2933 2934 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2935 SPR_NOACCESS, SPR_NOACCESS, 2936 &spr_read_generic, &spr_write_generic, 2937 0x00000000); 2938 2939 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2940 SPR_NOACCESS, SPR_NOACCESS, 2941 &spr_read_generic, &spr_write_generic, 2942 0x00000000); 2943 2944 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2945 SPR_NOACCESS, SPR_NOACCESS, 2946 &spr_read_generic, &spr_write_generic, 2947 0x00000000); 2948 2949 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2950 SPR_NOACCESS, SPR_NOACCESS, 2951 &spr_read_generic, &spr_write_generic, 2952 0x00000000); 2953 2954 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2955 &spr_read_generic, SPR_NOACCESS, 2956 &spr_read_generic, SPR_NOACCESS, 2957 l1cfg0); 2958 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2959 &spr_read_generic, SPR_NOACCESS, 2960 &spr_read_generic, SPR_NOACCESS, 2961 l1cfg1); 2962 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2963 SPR_NOACCESS, SPR_NOACCESS, 2964 &spr_read_generic, &spr_write_e500_l1csr0, 2965 0x00000000); 2966 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2967 SPR_NOACCESS, SPR_NOACCESS, 2968 &spr_read_generic, &spr_write_e500_l1csr1, 2969 0x00000000); 2970 if (version != fsl_e500v1 && version != fsl_e500v2) { 2971 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2972 SPR_NOACCESS, SPR_NOACCESS, 2973 &spr_read_generic, &spr_write_e500_l2csr0, 2974 0x00000000); 2975 } 2976 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2977 SPR_NOACCESS, SPR_NOACCESS, 2978 &spr_read_generic, &spr_write_generic, 2979 0x00000000); 2980 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2981 SPR_NOACCESS, SPR_NOACCESS, 2982 &spr_read_generic, &spr_write_generic, 2983 0x00000000); 2984 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2985 SPR_NOACCESS, SPR_NOACCESS, 2986 &spr_read_generic, &spr_write_booke206_mmucsr0, 2987 0x00000000); 2988 spr_register(env, SPR_BOOKE_EPR, "EPR", 2989 SPR_NOACCESS, SPR_NOACCESS, 2990 &spr_read_generic, SPR_NOACCESS, 2991 0x00000000); 2992 /* XXX better abstract into Emb.xxx features */ 2993 if ((version == fsl_e5500) || (version == fsl_e6500)) { 2994 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 2995 SPR_NOACCESS, SPR_NOACCESS, 2996 &spr_read_generic, &spr_write_generic, 2997 0x00000000); 2998 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 2999 SPR_NOACCESS, SPR_NOACCESS, 3000 &spr_read_mas73, &spr_write_mas73, 3001 0x00000000); 3002 ivpr_mask = (target_ulong)~0xFFFFULL; 3003 } 3004 3005 if (version == fsl_e6500) { 3006 /* Thread identification */ 3007 spr_register(env, SPR_TIR, "TIR", 3008 SPR_NOACCESS, SPR_NOACCESS, 3009 &spr_read_generic, SPR_NOACCESS, 3010 0x00000000); 3011 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3012 SPR_NOACCESS, SPR_NOACCESS, 3013 &spr_read_generic, SPR_NOACCESS, 3014 0x00000004); 3015 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3016 SPR_NOACCESS, SPR_NOACCESS, 3017 &spr_read_generic, SPR_NOACCESS, 3018 0x7FFFFFFC); 3019 } 3020 3021 #if !defined(CONFIG_USER_ONLY) 3022 env->nb_tlb = 0; 3023 env->tlb_type = TLB_MAS; 3024 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3025 env->nb_tlb += booke206_tlb_size(env, i); 3026 } 3027 #endif 3028 3029 init_excp_e200(env, ivpr_mask); 3030 /* Allocate hardware IRQ controller */ 3031 ppce500_irq_init(env_archcpu(env)); 3032 } 3033 3034 static void init_proc_e500v1(CPUPPCState *env) 3035 { 3036 init_proc_e500(env, fsl_e500v1); 3037 } 3038 3039 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3040 { 3041 DeviceClass *dc = DEVICE_CLASS(oc); 3042 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3043 3044 dc->desc = "e500v1 core"; 3045 pcc->init_proc = init_proc_e500v1; 3046 pcc->check_pow = check_pow_hid0; 3047 pcc->check_attn = check_attn_none; 3048 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3049 PPC_SPE | PPC_SPE_SINGLE | 3050 PPC_WRTEE | PPC_RFDI | 3051 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3052 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3053 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3054 pcc->insns_flags2 = PPC2_BOOKE206; 3055 pcc->msr_mask = (1ull << MSR_UCLE) | 3056 (1ull << MSR_SPE) | 3057 (1ull << MSR_POW) | 3058 (1ull << MSR_CE) | 3059 (1ull << MSR_EE) | 3060 (1ull << MSR_PR) | 3061 (1ull << MSR_FP) | 3062 (1ull << MSR_ME) | 3063 (1ull << MSR_FE0) | 3064 (1ull << MSR_DWE) | 3065 (1ull << MSR_DE) | 3066 (1ull << MSR_FE1) | 3067 (1ull << MSR_IR) | 3068 (1ull << MSR_DR); 3069 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3070 pcc->excp_model = POWERPC_EXCP_BOOKE; 3071 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3072 pcc->bfd_mach = bfd_mach_ppc_860; 3073 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3074 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3075 POWERPC_FLAG_BUS_CLK; 3076 } 3077 3078 static void init_proc_e500v2(CPUPPCState *env) 3079 { 3080 init_proc_e500(env, fsl_e500v2); 3081 } 3082 3083 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3084 { 3085 DeviceClass *dc = DEVICE_CLASS(oc); 3086 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3087 3088 dc->desc = "e500v2 core"; 3089 pcc->init_proc = init_proc_e500v2; 3090 pcc->check_pow = check_pow_hid0; 3091 pcc->check_attn = check_attn_none; 3092 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3093 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3094 PPC_WRTEE | PPC_RFDI | 3095 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3096 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3097 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3098 pcc->insns_flags2 = PPC2_BOOKE206; 3099 pcc->msr_mask = (1ull << MSR_UCLE) | 3100 (1ull << MSR_SPE) | 3101 (1ull << MSR_POW) | 3102 (1ull << MSR_CE) | 3103 (1ull << MSR_EE) | 3104 (1ull << MSR_PR) | 3105 (1ull << MSR_FP) | 3106 (1ull << MSR_ME) | 3107 (1ull << MSR_FE0) | 3108 (1ull << MSR_DWE) | 3109 (1ull << MSR_DE) | 3110 (1ull << MSR_FE1) | 3111 (1ull << MSR_IR) | 3112 (1ull << MSR_DR); 3113 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3114 pcc->excp_model = POWERPC_EXCP_BOOKE; 3115 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3116 pcc->bfd_mach = bfd_mach_ppc_860; 3117 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3118 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3119 POWERPC_FLAG_BUS_CLK; 3120 } 3121 3122 static void init_proc_e500mc(CPUPPCState *env) 3123 { 3124 init_proc_e500(env, fsl_e500mc); 3125 } 3126 3127 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3128 { 3129 DeviceClass *dc = DEVICE_CLASS(oc); 3130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3131 3132 dc->desc = "e500mc core"; 3133 pcc->init_proc = init_proc_e500mc; 3134 pcc->check_pow = check_pow_none; 3135 pcc->check_attn = check_attn_none; 3136 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3137 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3138 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3139 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3140 PPC_FLOAT | PPC_FLOAT_FRES | 3141 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3142 PPC_FLOAT_STFIWX | PPC_WAIT | 3143 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3144 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3145 pcc->msr_mask = (1ull << MSR_GS) | 3146 (1ull << MSR_UCLE) | 3147 (1ull << MSR_CE) | 3148 (1ull << MSR_EE) | 3149 (1ull << MSR_PR) | 3150 (1ull << MSR_FP) | 3151 (1ull << MSR_ME) | 3152 (1ull << MSR_FE0) | 3153 (1ull << MSR_DE) | 3154 (1ull << MSR_FE1) | 3155 (1ull << MSR_IR) | 3156 (1ull << MSR_DR) | 3157 (1ull << MSR_PX) | 3158 (1ull << MSR_RI); 3159 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3160 pcc->excp_model = POWERPC_EXCP_BOOKE; 3161 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3162 /* FIXME: figure out the correct flag for e500mc */ 3163 pcc->bfd_mach = bfd_mach_ppc_e500; 3164 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3165 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3166 } 3167 3168 #ifdef TARGET_PPC64 3169 static void init_proc_e5500(CPUPPCState *env) 3170 { 3171 init_proc_e500(env, fsl_e5500); 3172 } 3173 3174 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3175 { 3176 DeviceClass *dc = DEVICE_CLASS(oc); 3177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3178 3179 dc->desc = "e5500 core"; 3180 pcc->init_proc = init_proc_e5500; 3181 pcc->check_pow = check_pow_none; 3182 pcc->check_attn = check_attn_none; 3183 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3184 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3185 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3186 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3187 PPC_FLOAT | PPC_FLOAT_FRES | 3188 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3189 PPC_FLOAT_STFIWX | PPC_WAIT | 3190 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3191 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3192 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3193 PPC2_FP_CVT_S64; 3194 pcc->msr_mask = (1ull << MSR_CM) | 3195 (1ull << MSR_GS) | 3196 (1ull << MSR_UCLE) | 3197 (1ull << MSR_CE) | 3198 (1ull << MSR_EE) | 3199 (1ull << MSR_PR) | 3200 (1ull << MSR_FP) | 3201 (1ull << MSR_ME) | 3202 (1ull << MSR_FE0) | 3203 (1ull << MSR_DE) | 3204 (1ull << MSR_FE1) | 3205 (1ull << MSR_IR) | 3206 (1ull << MSR_DR) | 3207 (1ull << MSR_PX) | 3208 (1ull << MSR_RI); 3209 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3210 pcc->excp_model = POWERPC_EXCP_BOOKE; 3211 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3212 /* FIXME: figure out the correct flag for e5500 */ 3213 pcc->bfd_mach = bfd_mach_ppc_e500; 3214 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3215 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3216 } 3217 3218 static void init_proc_e6500(CPUPPCState *env) 3219 { 3220 init_proc_e500(env, fsl_e6500); 3221 } 3222 3223 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3224 { 3225 DeviceClass *dc = DEVICE_CLASS(oc); 3226 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3227 3228 dc->desc = "e6500 core"; 3229 pcc->init_proc = init_proc_e6500; 3230 pcc->check_pow = check_pow_none; 3231 pcc->check_attn = check_attn_none; 3232 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3233 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3234 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3235 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3236 PPC_FLOAT | PPC_FLOAT_FRES | 3237 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3238 PPC_FLOAT_STFIWX | PPC_WAIT | 3239 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3240 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3241 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3242 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3243 pcc->msr_mask = (1ull << MSR_CM) | 3244 (1ull << MSR_GS) | 3245 (1ull << MSR_UCLE) | 3246 (1ull << MSR_CE) | 3247 (1ull << MSR_EE) | 3248 (1ull << MSR_PR) | 3249 (1ull << MSR_FP) | 3250 (1ull << MSR_ME) | 3251 (1ull << MSR_FE0) | 3252 (1ull << MSR_DE) | 3253 (1ull << MSR_FE1) | 3254 (1ull << MSR_IS) | 3255 (1ull << MSR_DS) | 3256 (1ull << MSR_PX) | 3257 (1ull << MSR_RI) | 3258 (1ull << MSR_VR); 3259 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3260 pcc->excp_model = POWERPC_EXCP_BOOKE; 3261 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3262 pcc->bfd_mach = bfd_mach_ppc_e500; 3263 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3264 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3265 } 3266 3267 #endif 3268 3269 /* Non-embedded PowerPC */ 3270 static void init_proc_603(CPUPPCState *env) 3271 { 3272 register_non_embedded_sprs(env); 3273 register_sdr1_sprs(env); 3274 register_603_sprs(env); 3275 3276 /* Memory management */ 3277 register_low_BATs(env); 3278 register_6xx_7xx_soft_tlb(env, 64, 2); 3279 init_excp_603(env); 3280 env->dcache_line_size = 32; 3281 env->icache_line_size = 32; 3282 /* Allocate hardware IRQ controller */ 3283 ppc6xx_irq_init(env_archcpu(env)); 3284 } 3285 3286 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3287 { 3288 DeviceClass *dc = DEVICE_CLASS(oc); 3289 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3290 3291 dc->desc = "PowerPC 603"; 3292 pcc->init_proc = init_proc_603; 3293 pcc->check_pow = check_pow_hid0; 3294 pcc->check_attn = check_attn_none; 3295 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3296 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3297 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3298 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3299 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3300 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3301 PPC_SEGMENT | PPC_EXTERN; 3302 pcc->msr_mask = (1ull << MSR_POW) | 3303 (1ull << MSR_TGPR) | 3304 (1ull << MSR_ILE) | 3305 (1ull << MSR_EE) | 3306 (1ull << MSR_PR) | 3307 (1ull << MSR_FP) | 3308 (1ull << MSR_ME) | 3309 (1ull << MSR_FE0) | 3310 (1ull << MSR_SE) | 3311 (1ull << MSR_DE) | 3312 (1ull << MSR_FE1) | 3313 (1ull << MSR_EP) | 3314 (1ull << MSR_IR) | 3315 (1ull << MSR_DR) | 3316 (1ull << MSR_RI) | 3317 (1ull << MSR_LE); 3318 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3319 pcc->excp_model = POWERPC_EXCP_6xx; 3320 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3321 pcc->bfd_mach = bfd_mach_ppc_603; 3322 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3323 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3324 } 3325 3326 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3327 { 3328 DeviceClass *dc = DEVICE_CLASS(oc); 3329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3330 3331 dc->desc = "PowerPC 603e"; 3332 pcc->init_proc = init_proc_603; 3333 pcc->check_pow = check_pow_hid0; 3334 pcc->check_attn = check_attn_none; 3335 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3336 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3337 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3338 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3339 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3340 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3341 PPC_SEGMENT | PPC_EXTERN; 3342 pcc->msr_mask = (1ull << MSR_POW) | 3343 (1ull << MSR_TGPR) | 3344 (1ull << MSR_ILE) | 3345 (1ull << MSR_EE) | 3346 (1ull << MSR_PR) | 3347 (1ull << MSR_FP) | 3348 (1ull << MSR_ME) | 3349 (1ull << MSR_FE0) | 3350 (1ull << MSR_SE) | 3351 (1ull << MSR_DE) | 3352 (1ull << MSR_FE1) | 3353 (1ull << MSR_EP) | 3354 (1ull << MSR_IR) | 3355 (1ull << MSR_DR) | 3356 (1ull << MSR_RI) | 3357 (1ull << MSR_LE); 3358 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3359 pcc->excp_model = POWERPC_EXCP_6xx; 3360 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3361 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3362 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3363 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3364 } 3365 3366 static void init_proc_e300(CPUPPCState *env) 3367 { 3368 init_proc_603(env); 3369 register_e300_sprs(env); 3370 } 3371 3372 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3373 { 3374 DeviceClass *dc = DEVICE_CLASS(oc); 3375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3376 3377 dc->desc = "e300 core"; 3378 pcc->init_proc = init_proc_e300; 3379 pcc->check_pow = check_pow_hid0; 3380 pcc->check_attn = check_attn_none; 3381 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3382 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3383 PPC_FLOAT_STFIWX | 3384 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3385 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3386 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3387 PPC_SEGMENT | PPC_EXTERN; 3388 pcc->msr_mask = (1ull << MSR_POW) | 3389 (1ull << MSR_TGPR) | 3390 (1ull << MSR_ILE) | 3391 (1ull << MSR_EE) | 3392 (1ull << MSR_PR) | 3393 (1ull << MSR_FP) | 3394 (1ull << MSR_ME) | 3395 (1ull << MSR_FE0) | 3396 (1ull << MSR_SE) | 3397 (1ull << MSR_DE) | 3398 (1ull << MSR_FE1) | 3399 (1ull << MSR_AL) | 3400 (1ull << MSR_EP) | 3401 (1ull << MSR_IR) | 3402 (1ull << MSR_DR) | 3403 (1ull << MSR_RI) | 3404 (1ull << MSR_LE); 3405 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3406 pcc->excp_model = POWERPC_EXCP_6xx; 3407 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3408 pcc->bfd_mach = bfd_mach_ppc_603; 3409 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3410 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3411 } 3412 3413 static void init_proc_604(CPUPPCState *env) 3414 { 3415 register_non_embedded_sprs(env); 3416 register_sdr1_sprs(env); 3417 register_604_sprs(env); 3418 3419 /* Memory management */ 3420 register_low_BATs(env); 3421 init_excp_604(env); 3422 env->dcache_line_size = 32; 3423 env->icache_line_size = 32; 3424 /* Allocate hardware IRQ controller */ 3425 ppc6xx_irq_init(env_archcpu(env)); 3426 } 3427 3428 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3429 { 3430 DeviceClass *dc = DEVICE_CLASS(oc); 3431 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3432 3433 dc->desc = "PowerPC 604"; 3434 pcc->init_proc = init_proc_604; 3435 pcc->check_pow = check_pow_nocheck; 3436 pcc->check_attn = check_attn_none; 3437 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3438 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3439 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3440 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3441 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3442 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3443 PPC_SEGMENT | PPC_EXTERN; 3444 pcc->msr_mask = (1ull << MSR_POW) | 3445 (1ull << MSR_ILE) | 3446 (1ull << MSR_EE) | 3447 (1ull << MSR_PR) | 3448 (1ull << MSR_FP) | 3449 (1ull << MSR_ME) | 3450 (1ull << MSR_FE0) | 3451 (1ull << MSR_SE) | 3452 (1ull << MSR_DE) | 3453 (1ull << MSR_FE1) | 3454 (1ull << MSR_EP) | 3455 (1ull << MSR_IR) | 3456 (1ull << MSR_DR) | 3457 (1ull << MSR_PMM) | 3458 (1ull << MSR_RI) | 3459 (1ull << MSR_LE); 3460 pcc->mmu_model = POWERPC_MMU_32B; 3461 pcc->excp_model = POWERPC_EXCP_6xx; 3462 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3463 pcc->bfd_mach = bfd_mach_ppc_604; 3464 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3465 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3466 } 3467 3468 static void init_proc_604E(CPUPPCState *env) 3469 { 3470 init_proc_604(env); 3471 register_604e_sprs(env); 3472 } 3473 3474 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3475 { 3476 DeviceClass *dc = DEVICE_CLASS(oc); 3477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3478 3479 dc->desc = "PowerPC 604E"; 3480 pcc->init_proc = init_proc_604E; 3481 pcc->check_pow = check_pow_nocheck; 3482 pcc->check_attn = check_attn_none; 3483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3484 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3485 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3486 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3487 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3488 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3489 PPC_SEGMENT | PPC_EXTERN; 3490 pcc->msr_mask = (1ull << MSR_POW) | 3491 (1ull << MSR_ILE) | 3492 (1ull << MSR_EE) | 3493 (1ull << MSR_PR) | 3494 (1ull << MSR_FP) | 3495 (1ull << MSR_ME) | 3496 (1ull << MSR_FE0) | 3497 (1ull << MSR_SE) | 3498 (1ull << MSR_DE) | 3499 (1ull << MSR_FE1) | 3500 (1ull << MSR_EP) | 3501 (1ull << MSR_IR) | 3502 (1ull << MSR_DR) | 3503 (1ull << MSR_PMM) | 3504 (1ull << MSR_RI) | 3505 (1ull << MSR_LE); 3506 pcc->mmu_model = POWERPC_MMU_32B; 3507 pcc->excp_model = POWERPC_EXCP_6xx; 3508 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3509 pcc->bfd_mach = bfd_mach_ppc_604; 3510 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3511 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3512 } 3513 3514 static void init_proc_740(CPUPPCState *env) 3515 { 3516 register_non_embedded_sprs(env); 3517 register_sdr1_sprs(env); 3518 register_7xx_sprs(env); 3519 /* Thermal management */ 3520 register_thrm_sprs(env); 3521 3522 /* Memory management */ 3523 register_low_BATs(env); 3524 init_excp_7x0(env); 3525 env->dcache_line_size = 32; 3526 env->icache_line_size = 32; 3527 /* Allocate hardware IRQ controller */ 3528 ppc6xx_irq_init(env_archcpu(env)); 3529 } 3530 3531 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3532 { 3533 DeviceClass *dc = DEVICE_CLASS(oc); 3534 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3535 3536 dc->desc = "PowerPC 740"; 3537 pcc->init_proc = init_proc_740; 3538 pcc->check_pow = check_pow_hid0; 3539 pcc->check_attn = check_attn_none; 3540 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3541 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3542 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3543 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3544 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3545 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3546 PPC_SEGMENT | PPC_EXTERN; 3547 pcc->msr_mask = (1ull << MSR_POW) | 3548 (1ull << MSR_ILE) | 3549 (1ull << MSR_EE) | 3550 (1ull << MSR_PR) | 3551 (1ull << MSR_FP) | 3552 (1ull << MSR_ME) | 3553 (1ull << MSR_FE0) | 3554 (1ull << MSR_SE) | 3555 (1ull << MSR_DE) | 3556 (1ull << MSR_FE1) | 3557 (1ull << MSR_EP) | 3558 (1ull << MSR_IR) | 3559 (1ull << MSR_DR) | 3560 (1ull << MSR_PMM) | 3561 (1ull << MSR_RI) | 3562 (1ull << MSR_LE); 3563 pcc->mmu_model = POWERPC_MMU_32B; 3564 pcc->excp_model = POWERPC_EXCP_7xx; 3565 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3566 pcc->bfd_mach = bfd_mach_ppc_750; 3567 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3568 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3569 } 3570 3571 static void init_proc_750(CPUPPCState *env) 3572 { 3573 register_non_embedded_sprs(env); 3574 register_sdr1_sprs(env); 3575 register_7xx_sprs(env); 3576 3577 spr_register(env, SPR_L2CR, "L2CR", 3578 SPR_NOACCESS, SPR_NOACCESS, 3579 &spr_read_generic, spr_access_nop, 3580 0x00000000); 3581 /* Thermal management */ 3582 register_thrm_sprs(env); 3583 3584 /* Memory management */ 3585 register_low_BATs(env); 3586 /* 3587 * XXX: high BATs are also present but are known to be bugged on 3588 * die version 1.x 3589 */ 3590 init_excp_7x0(env); 3591 env->dcache_line_size = 32; 3592 env->icache_line_size = 32; 3593 /* Allocate hardware IRQ controller */ 3594 ppc6xx_irq_init(env_archcpu(env)); 3595 } 3596 3597 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3598 { 3599 DeviceClass *dc = DEVICE_CLASS(oc); 3600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3601 3602 dc->desc = "PowerPC 750"; 3603 pcc->init_proc = init_proc_750; 3604 pcc->check_pow = check_pow_hid0; 3605 pcc->check_attn = check_attn_none; 3606 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3608 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3609 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3610 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3611 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3612 PPC_SEGMENT | PPC_EXTERN; 3613 pcc->msr_mask = (1ull << MSR_POW) | 3614 (1ull << MSR_ILE) | 3615 (1ull << MSR_EE) | 3616 (1ull << MSR_PR) | 3617 (1ull << MSR_FP) | 3618 (1ull << MSR_ME) | 3619 (1ull << MSR_FE0) | 3620 (1ull << MSR_SE) | 3621 (1ull << MSR_DE) | 3622 (1ull << MSR_FE1) | 3623 (1ull << MSR_EP) | 3624 (1ull << MSR_IR) | 3625 (1ull << MSR_DR) | 3626 (1ull << MSR_PMM) | 3627 (1ull << MSR_RI) | 3628 (1ull << MSR_LE); 3629 pcc->mmu_model = POWERPC_MMU_32B; 3630 pcc->excp_model = POWERPC_EXCP_7xx; 3631 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3632 pcc->bfd_mach = bfd_mach_ppc_750; 3633 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3634 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3635 } 3636 3637 static void init_proc_750cl(CPUPPCState *env) 3638 { 3639 register_non_embedded_sprs(env); 3640 register_sdr1_sprs(env); 3641 register_7xx_sprs(env); 3642 3643 spr_register(env, SPR_L2CR, "L2CR", 3644 SPR_NOACCESS, SPR_NOACCESS, 3645 &spr_read_generic, spr_access_nop, 3646 0x00000000); 3647 /* Thermal management */ 3648 /* Those registers are fake on 750CL */ 3649 spr_register(env, SPR_THRM1, "THRM1", 3650 SPR_NOACCESS, SPR_NOACCESS, 3651 &spr_read_generic, &spr_write_generic, 3652 0x00000000); 3653 spr_register(env, SPR_THRM2, "THRM2", 3654 SPR_NOACCESS, SPR_NOACCESS, 3655 &spr_read_generic, &spr_write_generic, 3656 0x00000000); 3657 spr_register(env, SPR_THRM3, "THRM3", 3658 SPR_NOACCESS, SPR_NOACCESS, 3659 &spr_read_generic, &spr_write_generic, 3660 0x00000000); 3661 3662 spr_register(env, SPR_750_TDCL, "TDCL", 3663 SPR_NOACCESS, SPR_NOACCESS, 3664 &spr_read_generic, &spr_write_generic, 3665 0x00000000); 3666 spr_register(env, SPR_750_TDCH, "TDCH", 3667 SPR_NOACCESS, SPR_NOACCESS, 3668 &spr_read_generic, &spr_write_generic, 3669 0x00000000); 3670 /* DMA */ 3671 spr_register(env, SPR_750_WPAR, "WPAR", 3672 SPR_NOACCESS, SPR_NOACCESS, 3673 &spr_read_generic, &spr_write_generic, 3674 0x00000000); 3675 spr_register(env, SPR_750_DMAL, "DMAL", 3676 SPR_NOACCESS, SPR_NOACCESS, 3677 &spr_read_generic, &spr_write_generic, 3678 0x00000000); 3679 spr_register(env, SPR_750_DMAU, "DMAU", 3680 SPR_NOACCESS, SPR_NOACCESS, 3681 &spr_read_generic, &spr_write_generic, 3682 0x00000000); 3683 /* Hardware implementation registers */ 3684 spr_register(env, SPR_750CL_HID2, "HID2", 3685 SPR_NOACCESS, SPR_NOACCESS, 3686 &spr_read_generic, &spr_write_generic, 3687 0x00000000); 3688 3689 spr_register(env, SPR_750CL_HID4, "HID4", 3690 SPR_NOACCESS, SPR_NOACCESS, 3691 &spr_read_generic, &spr_write_generic, 3692 0x00000000); 3693 /* Quantization registers */ 3694 spr_register(env, SPR_750_GQR0, "GQR0", 3695 SPR_NOACCESS, SPR_NOACCESS, 3696 &spr_read_generic, &spr_write_generic, 3697 0x00000000); 3698 3699 spr_register(env, SPR_750_GQR1, "GQR1", 3700 SPR_NOACCESS, SPR_NOACCESS, 3701 &spr_read_generic, &spr_write_generic, 3702 0x00000000); 3703 3704 spr_register(env, SPR_750_GQR2, "GQR2", 3705 SPR_NOACCESS, SPR_NOACCESS, 3706 &spr_read_generic, &spr_write_generic, 3707 0x00000000); 3708 3709 spr_register(env, SPR_750_GQR3, "GQR3", 3710 SPR_NOACCESS, SPR_NOACCESS, 3711 &spr_read_generic, &spr_write_generic, 3712 0x00000000); 3713 3714 spr_register(env, SPR_750_GQR4, "GQR4", 3715 SPR_NOACCESS, SPR_NOACCESS, 3716 &spr_read_generic, &spr_write_generic, 3717 0x00000000); 3718 3719 spr_register(env, SPR_750_GQR5, "GQR5", 3720 SPR_NOACCESS, SPR_NOACCESS, 3721 &spr_read_generic, &spr_write_generic, 3722 0x00000000); 3723 3724 spr_register(env, SPR_750_GQR6, "GQR6", 3725 SPR_NOACCESS, SPR_NOACCESS, 3726 &spr_read_generic, &spr_write_generic, 3727 0x00000000); 3728 3729 spr_register(env, SPR_750_GQR7, "GQR7", 3730 SPR_NOACCESS, SPR_NOACCESS, 3731 &spr_read_generic, &spr_write_generic, 3732 0x00000000); 3733 /* Memory management */ 3734 register_low_BATs(env); 3735 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3736 register_high_BATs(env); 3737 init_excp_750cl(env); 3738 env->dcache_line_size = 32; 3739 env->icache_line_size = 32; 3740 /* Allocate hardware IRQ controller */ 3741 ppc6xx_irq_init(env_archcpu(env)); 3742 } 3743 3744 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3745 { 3746 DeviceClass *dc = DEVICE_CLASS(oc); 3747 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3748 3749 dc->desc = "PowerPC 750 CL"; 3750 pcc->init_proc = init_proc_750cl; 3751 pcc->check_pow = check_pow_hid0; 3752 pcc->check_attn = check_attn_none; 3753 /* 3754 * XXX: not implemented: 3755 * cache lock instructions: 3756 * dcbz_l 3757 * floating point paired instructions 3758 * psq_lux 3759 * psq_lx 3760 * psq_stux 3761 * psq_stx 3762 * ps_abs 3763 * ps_add 3764 * ps_cmpo0 3765 * ps_cmpo1 3766 * ps_cmpu0 3767 * ps_cmpu1 3768 * ps_div 3769 * ps_madd 3770 * ps_madds0 3771 * ps_madds1 3772 * ps_merge00 3773 * ps_merge01 3774 * ps_merge10 3775 * ps_merge11 3776 * ps_mr 3777 * ps_msub 3778 * ps_mul 3779 * ps_muls0 3780 * ps_muls1 3781 * ps_nabs 3782 * ps_neg 3783 * ps_nmadd 3784 * ps_nmsub 3785 * ps_res 3786 * ps_rsqrte 3787 * ps_sel 3788 * ps_sub 3789 * ps_sum0 3790 * ps_sum1 3791 */ 3792 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3794 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3795 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3796 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3797 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3798 PPC_SEGMENT | PPC_EXTERN; 3799 pcc->msr_mask = (1ull << MSR_POW) | 3800 (1ull << MSR_ILE) | 3801 (1ull << MSR_EE) | 3802 (1ull << MSR_PR) | 3803 (1ull << MSR_FP) | 3804 (1ull << MSR_ME) | 3805 (1ull << MSR_FE0) | 3806 (1ull << MSR_SE) | 3807 (1ull << MSR_DE) | 3808 (1ull << MSR_FE1) | 3809 (1ull << MSR_EP) | 3810 (1ull << MSR_IR) | 3811 (1ull << MSR_DR) | 3812 (1ull << MSR_PMM) | 3813 (1ull << MSR_RI) | 3814 (1ull << MSR_LE); 3815 pcc->mmu_model = POWERPC_MMU_32B; 3816 pcc->excp_model = POWERPC_EXCP_7xx; 3817 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3818 pcc->bfd_mach = bfd_mach_ppc_750; 3819 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3820 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3821 } 3822 3823 static void init_proc_750cx(CPUPPCState *env) 3824 { 3825 register_non_embedded_sprs(env); 3826 register_sdr1_sprs(env); 3827 register_7xx_sprs(env); 3828 3829 spr_register(env, SPR_L2CR, "L2CR", 3830 SPR_NOACCESS, SPR_NOACCESS, 3831 &spr_read_generic, spr_access_nop, 3832 0x00000000); 3833 /* Thermal management */ 3834 register_thrm_sprs(env); 3835 3836 spr_register(env, SPR_SDA, "SDA", 3837 SPR_NOACCESS, SPR_NOACCESS, 3838 &spr_read_generic, &spr_write_generic, 3839 0x00000000); 3840 3841 /* Memory management */ 3842 register_low_BATs(env); 3843 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3844 register_high_BATs(env); 3845 init_excp_750cx(env); 3846 env->dcache_line_size = 32; 3847 env->icache_line_size = 32; 3848 /* Allocate hardware IRQ controller */ 3849 ppc6xx_irq_init(env_archcpu(env)); 3850 } 3851 3852 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3853 { 3854 DeviceClass *dc = DEVICE_CLASS(oc); 3855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3856 3857 dc->desc = "PowerPC 750CX"; 3858 pcc->init_proc = init_proc_750cx; 3859 pcc->check_pow = check_pow_hid0; 3860 pcc->check_attn = check_attn_none; 3861 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3862 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3863 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3865 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3867 PPC_SEGMENT | PPC_EXTERN; 3868 pcc->msr_mask = (1ull << MSR_POW) | 3869 (1ull << MSR_ILE) | 3870 (1ull << MSR_EE) | 3871 (1ull << MSR_PR) | 3872 (1ull << MSR_FP) | 3873 (1ull << MSR_ME) | 3874 (1ull << MSR_FE0) | 3875 (1ull << MSR_SE) | 3876 (1ull << MSR_DE) | 3877 (1ull << MSR_FE1) | 3878 (1ull << MSR_EP) | 3879 (1ull << MSR_IR) | 3880 (1ull << MSR_DR) | 3881 (1ull << MSR_PMM) | 3882 (1ull << MSR_RI) | 3883 (1ull << MSR_LE); 3884 pcc->mmu_model = POWERPC_MMU_32B; 3885 pcc->excp_model = POWERPC_EXCP_7xx; 3886 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3887 pcc->bfd_mach = bfd_mach_ppc_750; 3888 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3889 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3890 } 3891 3892 static void init_proc_750fx(CPUPPCState *env) 3893 { 3894 register_non_embedded_sprs(env); 3895 register_sdr1_sprs(env); 3896 register_7xx_sprs(env); 3897 3898 spr_register(env, SPR_L2CR, "L2CR", 3899 SPR_NOACCESS, SPR_NOACCESS, 3900 &spr_read_generic, spr_access_nop, 3901 0x00000000); 3902 /* Thermal management */ 3903 register_thrm_sprs(env); 3904 3905 spr_register(env, SPR_750_THRM4, "THRM4", 3906 SPR_NOACCESS, SPR_NOACCESS, 3907 &spr_read_generic, &spr_write_generic, 3908 0x00000000); 3909 /* Hardware implementation registers */ 3910 spr_register(env, SPR_750FX_HID2, "HID2", 3911 SPR_NOACCESS, SPR_NOACCESS, 3912 &spr_read_generic, &spr_write_generic, 3913 0x00000000); 3914 /* Memory management */ 3915 register_low_BATs(env); 3916 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3917 register_high_BATs(env); 3918 init_excp_7x0(env); 3919 env->dcache_line_size = 32; 3920 env->icache_line_size = 32; 3921 /* Allocate hardware IRQ controller */ 3922 ppc6xx_irq_init(env_archcpu(env)); 3923 } 3924 3925 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3926 { 3927 DeviceClass *dc = DEVICE_CLASS(oc); 3928 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3929 3930 dc->desc = "PowerPC 750FX"; 3931 pcc->init_proc = init_proc_750fx; 3932 pcc->check_pow = check_pow_hid0; 3933 pcc->check_attn = check_attn_none; 3934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3938 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3940 PPC_SEGMENT | PPC_EXTERN; 3941 pcc->msr_mask = (1ull << MSR_POW) | 3942 (1ull << MSR_ILE) | 3943 (1ull << MSR_EE) | 3944 (1ull << MSR_PR) | 3945 (1ull << MSR_FP) | 3946 (1ull << MSR_ME) | 3947 (1ull << MSR_FE0) | 3948 (1ull << MSR_SE) | 3949 (1ull << MSR_DE) | 3950 (1ull << MSR_FE1) | 3951 (1ull << MSR_EP) | 3952 (1ull << MSR_IR) | 3953 (1ull << MSR_DR) | 3954 (1ull << MSR_PMM) | 3955 (1ull << MSR_RI) | 3956 (1ull << MSR_LE); 3957 pcc->mmu_model = POWERPC_MMU_32B; 3958 pcc->excp_model = POWERPC_EXCP_7xx; 3959 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3960 pcc->bfd_mach = bfd_mach_ppc_750; 3961 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3962 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3963 } 3964 3965 static void init_proc_750gx(CPUPPCState *env) 3966 { 3967 register_non_embedded_sprs(env); 3968 register_sdr1_sprs(env); 3969 register_7xx_sprs(env); 3970 3971 spr_register(env, SPR_L2CR, "L2CR", 3972 SPR_NOACCESS, SPR_NOACCESS, 3973 &spr_read_generic, spr_access_nop, 3974 0x00000000); 3975 /* Thermal management */ 3976 register_thrm_sprs(env); 3977 3978 spr_register(env, SPR_750_THRM4, "THRM4", 3979 SPR_NOACCESS, SPR_NOACCESS, 3980 &spr_read_generic, &spr_write_generic, 3981 0x00000000); 3982 /* Hardware implementation registers */ 3983 spr_register(env, SPR_750FX_HID2, "HID2", 3984 SPR_NOACCESS, SPR_NOACCESS, 3985 &spr_read_generic, &spr_write_generic, 3986 0x00000000); 3987 /* Memory management */ 3988 register_low_BATs(env); 3989 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3990 register_high_BATs(env); 3991 init_excp_7x0(env); 3992 env->dcache_line_size = 32; 3993 env->icache_line_size = 32; 3994 /* Allocate hardware IRQ controller */ 3995 ppc6xx_irq_init(env_archcpu(env)); 3996 } 3997 3998 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 3999 { 4000 DeviceClass *dc = DEVICE_CLASS(oc); 4001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4002 4003 dc->desc = "PowerPC 750GX"; 4004 pcc->init_proc = init_proc_750gx; 4005 pcc->check_pow = check_pow_hid0; 4006 pcc->check_attn = check_attn_none; 4007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4009 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4011 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4013 PPC_SEGMENT | PPC_EXTERN; 4014 pcc->msr_mask = (1ull << MSR_POW) | 4015 (1ull << MSR_ILE) | 4016 (1ull << MSR_EE) | 4017 (1ull << MSR_PR) | 4018 (1ull << MSR_FP) | 4019 (1ull << MSR_ME) | 4020 (1ull << MSR_FE0) | 4021 (1ull << MSR_SE) | 4022 (1ull << MSR_DE) | 4023 (1ull << MSR_FE1) | 4024 (1ull << MSR_EP) | 4025 (1ull << MSR_IR) | 4026 (1ull << MSR_DR) | 4027 (1ull << MSR_PMM) | 4028 (1ull << MSR_RI) | 4029 (1ull << MSR_LE); 4030 pcc->mmu_model = POWERPC_MMU_32B; 4031 pcc->excp_model = POWERPC_EXCP_7xx; 4032 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4033 pcc->bfd_mach = bfd_mach_ppc_750; 4034 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4035 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4036 } 4037 4038 static void init_proc_745(CPUPPCState *env) 4039 { 4040 register_non_embedded_sprs(env); 4041 register_sdr1_sprs(env); 4042 register_7xx_sprs(env); 4043 register_745_sprs(env); 4044 /* Thermal management */ 4045 register_thrm_sprs(env); 4046 4047 /* Memory management */ 4048 register_low_BATs(env); 4049 register_high_BATs(env); 4050 register_6xx_7xx_soft_tlb(env, 64, 2); 4051 init_excp_7x5(env); 4052 env->dcache_line_size = 32; 4053 env->icache_line_size = 32; 4054 /* Allocate hardware IRQ controller */ 4055 ppc6xx_irq_init(env_archcpu(env)); 4056 } 4057 4058 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4059 { 4060 DeviceClass *dc = DEVICE_CLASS(oc); 4061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4062 4063 dc->desc = "PowerPC 745"; 4064 pcc->init_proc = init_proc_745; 4065 pcc->check_pow = check_pow_hid0; 4066 pcc->check_attn = check_attn_none; 4067 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4068 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4069 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4070 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4071 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4072 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4073 PPC_SEGMENT | PPC_EXTERN; 4074 pcc->msr_mask = (1ull << MSR_POW) | 4075 (1ull << MSR_ILE) | 4076 (1ull << MSR_EE) | 4077 (1ull << MSR_PR) | 4078 (1ull << MSR_FP) | 4079 (1ull << MSR_ME) | 4080 (1ull << MSR_FE0) | 4081 (1ull << MSR_SE) | 4082 (1ull << MSR_DE) | 4083 (1ull << MSR_FE1) | 4084 (1ull << MSR_EP) | 4085 (1ull << MSR_IR) | 4086 (1ull << MSR_DR) | 4087 (1ull << MSR_PMM) | 4088 (1ull << MSR_RI) | 4089 (1ull << MSR_LE); 4090 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4091 pcc->excp_model = POWERPC_EXCP_7xx; 4092 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4093 pcc->bfd_mach = bfd_mach_ppc_750; 4094 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4095 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4096 } 4097 4098 static void init_proc_755(CPUPPCState *env) 4099 { 4100 init_proc_745(env); 4101 register_755_sprs(env); 4102 } 4103 4104 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4105 { 4106 DeviceClass *dc = DEVICE_CLASS(oc); 4107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4108 4109 dc->desc = "PowerPC 755"; 4110 pcc->init_proc = init_proc_755; 4111 pcc->check_pow = check_pow_hid0; 4112 pcc->check_attn = check_attn_none; 4113 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4114 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4115 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4116 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4117 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4118 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4119 PPC_SEGMENT | PPC_EXTERN; 4120 pcc->msr_mask = (1ull << MSR_POW) | 4121 (1ull << MSR_ILE) | 4122 (1ull << MSR_EE) | 4123 (1ull << MSR_PR) | 4124 (1ull << MSR_FP) | 4125 (1ull << MSR_ME) | 4126 (1ull << MSR_FE0) | 4127 (1ull << MSR_SE) | 4128 (1ull << MSR_DE) | 4129 (1ull << MSR_FE1) | 4130 (1ull << MSR_EP) | 4131 (1ull << MSR_IR) | 4132 (1ull << MSR_DR) | 4133 (1ull << MSR_PMM) | 4134 (1ull << MSR_RI) | 4135 (1ull << MSR_LE); 4136 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4137 pcc->excp_model = POWERPC_EXCP_7xx; 4138 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4139 pcc->bfd_mach = bfd_mach_ppc_750; 4140 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4141 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4142 } 4143 4144 static void init_proc_7400(CPUPPCState *env) 4145 { 4146 register_non_embedded_sprs(env); 4147 register_sdr1_sprs(env); 4148 register_74xx_sprs(env); 4149 vscr_init(env, 0x00010000); 4150 4151 spr_register(env, SPR_UBAMR, "UBAMR", 4152 &spr_read_ureg, SPR_NOACCESS, 4153 &spr_read_ureg, SPR_NOACCESS, 4154 0x00000000); 4155 4156 spr_register(env, SPR_MSSCR1, "MSSCR1", 4157 SPR_NOACCESS, SPR_NOACCESS, 4158 &spr_read_generic, &spr_write_generic, 4159 0x00000000); 4160 /* Thermal management */ 4161 register_thrm_sprs(env); 4162 /* Memory management */ 4163 register_low_BATs(env); 4164 init_excp_7400(env); 4165 env->dcache_line_size = 32; 4166 env->icache_line_size = 32; 4167 /* Allocate hardware IRQ controller */ 4168 ppc6xx_irq_init(env_archcpu(env)); 4169 } 4170 4171 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4172 { 4173 DeviceClass *dc = DEVICE_CLASS(oc); 4174 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4175 4176 dc->desc = "PowerPC 7400 (aka G4)"; 4177 pcc->init_proc = init_proc_7400; 4178 pcc->check_pow = check_pow_hid0; 4179 pcc->check_attn = check_attn_none; 4180 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4181 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4182 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4183 PPC_FLOAT_STFIWX | 4184 PPC_CACHE | PPC_CACHE_ICBI | 4185 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4186 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4187 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4188 PPC_MEM_TLBIA | 4189 PPC_SEGMENT | PPC_EXTERN | 4190 PPC_ALTIVEC; 4191 pcc->msr_mask = (1ull << MSR_VR) | 4192 (1ull << MSR_POW) | 4193 (1ull << MSR_ILE) | 4194 (1ull << MSR_EE) | 4195 (1ull << MSR_PR) | 4196 (1ull << MSR_FP) | 4197 (1ull << MSR_ME) | 4198 (1ull << MSR_FE0) | 4199 (1ull << MSR_SE) | 4200 (1ull << MSR_DE) | 4201 (1ull << MSR_FE1) | 4202 (1ull << MSR_EP) | 4203 (1ull << MSR_IR) | 4204 (1ull << MSR_DR) | 4205 (1ull << MSR_PMM) | 4206 (1ull << MSR_RI) | 4207 (1ull << MSR_LE); 4208 pcc->mmu_model = POWERPC_MMU_32B; 4209 pcc->excp_model = POWERPC_EXCP_74xx; 4210 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4211 pcc->bfd_mach = bfd_mach_ppc_7400; 4212 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4213 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4214 POWERPC_FLAG_BUS_CLK; 4215 } 4216 4217 static void init_proc_7410(CPUPPCState *env) 4218 { 4219 register_non_embedded_sprs(env); 4220 register_sdr1_sprs(env); 4221 register_74xx_sprs(env); 4222 vscr_init(env, 0x00010000); 4223 4224 spr_register(env, SPR_UBAMR, "UBAMR", 4225 &spr_read_ureg, SPR_NOACCESS, 4226 &spr_read_ureg, SPR_NOACCESS, 4227 0x00000000); 4228 /* Thermal management */ 4229 register_thrm_sprs(env); 4230 /* L2PMCR */ 4231 4232 spr_register(env, SPR_L2PMCR, "L2PMCR", 4233 SPR_NOACCESS, SPR_NOACCESS, 4234 &spr_read_generic, &spr_write_generic, 4235 0x00000000); 4236 /* LDSTDB */ 4237 4238 spr_register(env, SPR_LDSTDB, "LDSTDB", 4239 SPR_NOACCESS, SPR_NOACCESS, 4240 &spr_read_generic, &spr_write_generic, 4241 0x00000000); 4242 /* Memory management */ 4243 register_low_BATs(env); 4244 init_excp_7400(env); 4245 env->dcache_line_size = 32; 4246 env->icache_line_size = 32; 4247 /* Allocate hardware IRQ controller */ 4248 ppc6xx_irq_init(env_archcpu(env)); 4249 } 4250 4251 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4252 { 4253 DeviceClass *dc = DEVICE_CLASS(oc); 4254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4255 4256 dc->desc = "PowerPC 7410 (aka G4)"; 4257 pcc->init_proc = init_proc_7410; 4258 pcc->check_pow = check_pow_hid0; 4259 pcc->check_attn = check_attn_none; 4260 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4261 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4262 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4263 PPC_FLOAT_STFIWX | 4264 PPC_CACHE | PPC_CACHE_ICBI | 4265 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4266 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4268 PPC_MEM_TLBIA | 4269 PPC_SEGMENT | PPC_EXTERN | 4270 PPC_ALTIVEC; 4271 pcc->msr_mask = (1ull << MSR_VR) | 4272 (1ull << MSR_POW) | 4273 (1ull << MSR_ILE) | 4274 (1ull << MSR_EE) | 4275 (1ull << MSR_PR) | 4276 (1ull << MSR_FP) | 4277 (1ull << MSR_ME) | 4278 (1ull << MSR_FE0) | 4279 (1ull << MSR_SE) | 4280 (1ull << MSR_DE) | 4281 (1ull << MSR_FE1) | 4282 (1ull << MSR_EP) | 4283 (1ull << MSR_IR) | 4284 (1ull << MSR_DR) | 4285 (1ull << MSR_PMM) | 4286 (1ull << MSR_RI) | 4287 (1ull << MSR_LE); 4288 pcc->mmu_model = POWERPC_MMU_32B; 4289 pcc->excp_model = POWERPC_EXCP_74xx; 4290 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4291 pcc->bfd_mach = bfd_mach_ppc_7400; 4292 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4293 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4294 POWERPC_FLAG_BUS_CLK; 4295 } 4296 4297 static void init_proc_7440(CPUPPCState *env) 4298 { 4299 register_non_embedded_sprs(env); 4300 register_sdr1_sprs(env); 4301 register_74xx_sprs(env); 4302 vscr_init(env, 0x00010000); 4303 4304 spr_register(env, SPR_UBAMR, "UBAMR", 4305 &spr_read_ureg, SPR_NOACCESS, 4306 &spr_read_ureg, SPR_NOACCESS, 4307 0x00000000); 4308 /* LDSTCR */ 4309 spr_register(env, SPR_LDSTCR, "LDSTCR", 4310 SPR_NOACCESS, SPR_NOACCESS, 4311 &spr_read_generic, &spr_write_generic, 4312 0x00000000); 4313 /* ICTRL */ 4314 spr_register(env, SPR_ICTRL, "ICTRL", 4315 SPR_NOACCESS, SPR_NOACCESS, 4316 &spr_read_generic, &spr_write_generic, 4317 0x00000000); 4318 /* MSSSR0 */ 4319 spr_register(env, SPR_MSSSR0, "MSSSR0", 4320 SPR_NOACCESS, SPR_NOACCESS, 4321 &spr_read_generic, &spr_write_generic, 4322 0x00000000); 4323 /* PMC */ 4324 spr_register(env, SPR_7XX_PMC5, "PMC5", 4325 SPR_NOACCESS, SPR_NOACCESS, 4326 &spr_read_generic, &spr_write_generic, 4327 0x00000000); 4328 4329 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4330 &spr_read_ureg, SPR_NOACCESS, 4331 &spr_read_ureg, SPR_NOACCESS, 4332 0x00000000); 4333 4334 spr_register(env, SPR_7XX_PMC6, "PMC6", 4335 SPR_NOACCESS, SPR_NOACCESS, 4336 &spr_read_generic, &spr_write_generic, 4337 0x00000000); 4338 4339 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4340 &spr_read_ureg, SPR_NOACCESS, 4341 &spr_read_ureg, SPR_NOACCESS, 4342 0x00000000); 4343 /* Memory management */ 4344 register_low_BATs(env); 4345 init_excp_7450(env); 4346 env->dcache_line_size = 32; 4347 env->icache_line_size = 32; 4348 /* Allocate hardware IRQ controller */ 4349 ppc6xx_irq_init(env_archcpu(env)); 4350 } 4351 4352 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4353 { 4354 DeviceClass *dc = DEVICE_CLASS(oc); 4355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4356 4357 dc->desc = "PowerPC 7440 (aka G4)"; 4358 pcc->init_proc = init_proc_7440; 4359 pcc->check_pow = check_pow_hid0_74xx; 4360 pcc->check_attn = check_attn_none; 4361 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4362 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4363 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4364 PPC_FLOAT_STFIWX | 4365 PPC_CACHE | PPC_CACHE_ICBI | 4366 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4367 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4368 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4369 PPC_MEM_TLBIA | 4370 PPC_SEGMENT | PPC_EXTERN | 4371 PPC_ALTIVEC; 4372 pcc->msr_mask = (1ull << MSR_VR) | 4373 (1ull << MSR_POW) | 4374 (1ull << MSR_ILE) | 4375 (1ull << MSR_EE) | 4376 (1ull << MSR_PR) | 4377 (1ull << MSR_FP) | 4378 (1ull << MSR_ME) | 4379 (1ull << MSR_FE0) | 4380 (1ull << MSR_SE) | 4381 (1ull << MSR_DE) | 4382 (1ull << MSR_FE1) | 4383 (1ull << MSR_EP) | 4384 (1ull << MSR_IR) | 4385 (1ull << MSR_DR) | 4386 (1ull << MSR_PMM) | 4387 (1ull << MSR_RI) | 4388 (1ull << MSR_LE); 4389 pcc->mmu_model = POWERPC_MMU_32B; 4390 pcc->excp_model = POWERPC_EXCP_74xx; 4391 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4392 pcc->bfd_mach = bfd_mach_ppc_7400; 4393 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4394 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4395 POWERPC_FLAG_BUS_CLK; 4396 } 4397 4398 static void init_proc_7450(CPUPPCState *env) 4399 { 4400 register_non_embedded_sprs(env); 4401 register_sdr1_sprs(env); 4402 register_74xx_sprs(env); 4403 vscr_init(env, 0x00010000); 4404 /* Level 3 cache control */ 4405 register_l3_ctrl(env); 4406 /* L3ITCR1 */ 4407 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4408 SPR_NOACCESS, SPR_NOACCESS, 4409 &spr_read_generic, &spr_write_generic, 4410 0x00000000); 4411 /* L3ITCR2 */ 4412 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4413 SPR_NOACCESS, SPR_NOACCESS, 4414 &spr_read_generic, &spr_write_generic, 4415 0x00000000); 4416 /* L3ITCR3 */ 4417 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4418 SPR_NOACCESS, SPR_NOACCESS, 4419 &spr_read_generic, &spr_write_generic, 4420 0x00000000); 4421 /* L3OHCR */ 4422 spr_register(env, SPR_L3OHCR, "L3OHCR", 4423 SPR_NOACCESS, SPR_NOACCESS, 4424 &spr_read_generic, &spr_write_generic, 4425 0x00000000); 4426 4427 spr_register(env, SPR_UBAMR, "UBAMR", 4428 &spr_read_ureg, SPR_NOACCESS, 4429 &spr_read_ureg, SPR_NOACCESS, 4430 0x00000000); 4431 /* LDSTCR */ 4432 spr_register(env, SPR_LDSTCR, "LDSTCR", 4433 SPR_NOACCESS, SPR_NOACCESS, 4434 &spr_read_generic, &spr_write_generic, 4435 0x00000000); 4436 /* ICTRL */ 4437 spr_register(env, SPR_ICTRL, "ICTRL", 4438 SPR_NOACCESS, SPR_NOACCESS, 4439 &spr_read_generic, &spr_write_generic, 4440 0x00000000); 4441 /* MSSSR0 */ 4442 spr_register(env, SPR_MSSSR0, "MSSSR0", 4443 SPR_NOACCESS, SPR_NOACCESS, 4444 &spr_read_generic, &spr_write_generic, 4445 0x00000000); 4446 /* PMC */ 4447 spr_register(env, SPR_7XX_PMC5, "PMC5", 4448 SPR_NOACCESS, SPR_NOACCESS, 4449 &spr_read_generic, &spr_write_generic, 4450 0x00000000); 4451 4452 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4453 &spr_read_ureg, SPR_NOACCESS, 4454 &spr_read_ureg, SPR_NOACCESS, 4455 0x00000000); 4456 4457 spr_register(env, SPR_7XX_PMC6, "PMC6", 4458 SPR_NOACCESS, SPR_NOACCESS, 4459 &spr_read_generic, &spr_write_generic, 4460 0x00000000); 4461 4462 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4463 &spr_read_ureg, SPR_NOACCESS, 4464 &spr_read_ureg, SPR_NOACCESS, 4465 0x00000000); 4466 /* Memory management */ 4467 register_low_BATs(env); 4468 init_excp_7450(env); 4469 env->dcache_line_size = 32; 4470 env->icache_line_size = 32; 4471 /* Allocate hardware IRQ controller */ 4472 ppc6xx_irq_init(env_archcpu(env)); 4473 } 4474 4475 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4476 { 4477 DeviceClass *dc = DEVICE_CLASS(oc); 4478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4479 4480 dc->desc = "PowerPC 7450 (aka G4)"; 4481 pcc->init_proc = init_proc_7450; 4482 pcc->check_pow = check_pow_hid0_74xx; 4483 pcc->check_attn = check_attn_none; 4484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4485 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4486 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4487 PPC_FLOAT_STFIWX | 4488 PPC_CACHE | PPC_CACHE_ICBI | 4489 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4490 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4491 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4492 PPC_MEM_TLBIA | 4493 PPC_SEGMENT | PPC_EXTERN | 4494 PPC_ALTIVEC; 4495 pcc->msr_mask = (1ull << MSR_VR) | 4496 (1ull << MSR_POW) | 4497 (1ull << MSR_ILE) | 4498 (1ull << MSR_EE) | 4499 (1ull << MSR_PR) | 4500 (1ull << MSR_FP) | 4501 (1ull << MSR_ME) | 4502 (1ull << MSR_FE0) | 4503 (1ull << MSR_SE) | 4504 (1ull << MSR_DE) | 4505 (1ull << MSR_FE1) | 4506 (1ull << MSR_EP) | 4507 (1ull << MSR_IR) | 4508 (1ull << MSR_DR) | 4509 (1ull << MSR_PMM) | 4510 (1ull << MSR_RI) | 4511 (1ull << MSR_LE); 4512 pcc->mmu_model = POWERPC_MMU_32B; 4513 pcc->excp_model = POWERPC_EXCP_74xx; 4514 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4515 pcc->bfd_mach = bfd_mach_ppc_7400; 4516 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4517 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4518 POWERPC_FLAG_BUS_CLK; 4519 } 4520 4521 static void init_proc_7445(CPUPPCState *env) 4522 { 4523 register_non_embedded_sprs(env); 4524 register_sdr1_sprs(env); 4525 register_74xx_sprs(env); 4526 vscr_init(env, 0x00010000); 4527 /* LDSTCR */ 4528 spr_register(env, SPR_LDSTCR, "LDSTCR", 4529 SPR_NOACCESS, SPR_NOACCESS, 4530 &spr_read_generic, &spr_write_generic, 4531 0x00000000); 4532 /* ICTRL */ 4533 spr_register(env, SPR_ICTRL, "ICTRL", 4534 SPR_NOACCESS, SPR_NOACCESS, 4535 &spr_read_generic, &spr_write_generic, 4536 0x00000000); 4537 /* MSSSR0 */ 4538 spr_register(env, SPR_MSSSR0, "MSSSR0", 4539 SPR_NOACCESS, SPR_NOACCESS, 4540 &spr_read_generic, &spr_write_generic, 4541 0x00000000); 4542 /* PMC */ 4543 spr_register(env, SPR_7XX_PMC5, "PMC5", 4544 SPR_NOACCESS, SPR_NOACCESS, 4545 &spr_read_generic, &spr_write_generic, 4546 0x00000000); 4547 4548 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4549 &spr_read_ureg, SPR_NOACCESS, 4550 &spr_read_ureg, SPR_NOACCESS, 4551 0x00000000); 4552 4553 spr_register(env, SPR_7XX_PMC6, "PMC6", 4554 SPR_NOACCESS, SPR_NOACCESS, 4555 &spr_read_generic, &spr_write_generic, 4556 0x00000000); 4557 4558 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4559 &spr_read_ureg, SPR_NOACCESS, 4560 &spr_read_ureg, SPR_NOACCESS, 4561 0x00000000); 4562 /* SPRGs */ 4563 spr_register(env, SPR_SPRG4, "SPRG4", 4564 SPR_NOACCESS, SPR_NOACCESS, 4565 &spr_read_generic, &spr_write_generic, 4566 0x00000000); 4567 spr_register(env, SPR_USPRG4, "USPRG4", 4568 &spr_read_ureg, SPR_NOACCESS, 4569 &spr_read_ureg, SPR_NOACCESS, 4570 0x00000000); 4571 spr_register(env, SPR_SPRG5, "SPRG5", 4572 SPR_NOACCESS, SPR_NOACCESS, 4573 &spr_read_generic, &spr_write_generic, 4574 0x00000000); 4575 spr_register(env, SPR_USPRG5, "USPRG5", 4576 &spr_read_ureg, SPR_NOACCESS, 4577 &spr_read_ureg, SPR_NOACCESS, 4578 0x00000000); 4579 spr_register(env, SPR_SPRG6, "SPRG6", 4580 SPR_NOACCESS, SPR_NOACCESS, 4581 &spr_read_generic, &spr_write_generic, 4582 0x00000000); 4583 spr_register(env, SPR_USPRG6, "USPRG6", 4584 &spr_read_ureg, SPR_NOACCESS, 4585 &spr_read_ureg, SPR_NOACCESS, 4586 0x00000000); 4587 spr_register(env, SPR_SPRG7, "SPRG7", 4588 SPR_NOACCESS, SPR_NOACCESS, 4589 &spr_read_generic, &spr_write_generic, 4590 0x00000000); 4591 spr_register(env, SPR_USPRG7, "USPRG7", 4592 &spr_read_ureg, SPR_NOACCESS, 4593 &spr_read_ureg, SPR_NOACCESS, 4594 0x00000000); 4595 /* Memory management */ 4596 register_low_BATs(env); 4597 register_high_BATs(env); 4598 init_excp_7450(env); 4599 env->dcache_line_size = 32; 4600 env->icache_line_size = 32; 4601 /* Allocate hardware IRQ controller */ 4602 ppc6xx_irq_init(env_archcpu(env)); 4603 } 4604 4605 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4606 { 4607 DeviceClass *dc = DEVICE_CLASS(oc); 4608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4609 4610 dc->desc = "PowerPC 7445 (aka G4)"; 4611 pcc->init_proc = init_proc_7445; 4612 pcc->check_pow = check_pow_hid0_74xx; 4613 pcc->check_attn = check_attn_none; 4614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4616 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4617 PPC_FLOAT_STFIWX | 4618 PPC_CACHE | PPC_CACHE_ICBI | 4619 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4620 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4621 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4622 PPC_MEM_TLBIA | 4623 PPC_SEGMENT | PPC_EXTERN | 4624 PPC_ALTIVEC; 4625 pcc->msr_mask = (1ull << MSR_VR) | 4626 (1ull << MSR_POW) | 4627 (1ull << MSR_ILE) | 4628 (1ull << MSR_EE) | 4629 (1ull << MSR_PR) | 4630 (1ull << MSR_FP) | 4631 (1ull << MSR_ME) | 4632 (1ull << MSR_FE0) | 4633 (1ull << MSR_SE) | 4634 (1ull << MSR_DE) | 4635 (1ull << MSR_FE1) | 4636 (1ull << MSR_EP) | 4637 (1ull << MSR_IR) | 4638 (1ull << MSR_DR) | 4639 (1ull << MSR_PMM) | 4640 (1ull << MSR_RI) | 4641 (1ull << MSR_LE); 4642 pcc->mmu_model = POWERPC_MMU_32B; 4643 pcc->excp_model = POWERPC_EXCP_74xx; 4644 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4645 pcc->bfd_mach = bfd_mach_ppc_7400; 4646 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4647 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4648 POWERPC_FLAG_BUS_CLK; 4649 } 4650 4651 static void init_proc_7455(CPUPPCState *env) 4652 { 4653 register_non_embedded_sprs(env); 4654 register_sdr1_sprs(env); 4655 register_74xx_sprs(env); 4656 vscr_init(env, 0x00010000); 4657 /* Level 3 cache control */ 4658 register_l3_ctrl(env); 4659 /* LDSTCR */ 4660 spr_register(env, SPR_LDSTCR, "LDSTCR", 4661 SPR_NOACCESS, SPR_NOACCESS, 4662 &spr_read_generic, &spr_write_generic, 4663 0x00000000); 4664 /* ICTRL */ 4665 spr_register(env, SPR_ICTRL, "ICTRL", 4666 SPR_NOACCESS, SPR_NOACCESS, 4667 &spr_read_generic, &spr_write_generic, 4668 0x00000000); 4669 /* MSSSR0 */ 4670 spr_register(env, SPR_MSSSR0, "MSSSR0", 4671 SPR_NOACCESS, SPR_NOACCESS, 4672 &spr_read_generic, &spr_write_generic, 4673 0x00000000); 4674 /* PMC */ 4675 spr_register(env, SPR_7XX_PMC5, "PMC5", 4676 SPR_NOACCESS, SPR_NOACCESS, 4677 &spr_read_generic, &spr_write_generic, 4678 0x00000000); 4679 4680 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4681 &spr_read_ureg, SPR_NOACCESS, 4682 &spr_read_ureg, SPR_NOACCESS, 4683 0x00000000); 4684 4685 spr_register(env, SPR_7XX_PMC6, "PMC6", 4686 SPR_NOACCESS, SPR_NOACCESS, 4687 &spr_read_generic, &spr_write_generic, 4688 0x00000000); 4689 4690 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4691 &spr_read_ureg, SPR_NOACCESS, 4692 &spr_read_ureg, SPR_NOACCESS, 4693 0x00000000); 4694 /* SPRGs */ 4695 spr_register(env, SPR_SPRG4, "SPRG4", 4696 SPR_NOACCESS, SPR_NOACCESS, 4697 &spr_read_generic, &spr_write_generic, 4698 0x00000000); 4699 spr_register(env, SPR_USPRG4, "USPRG4", 4700 &spr_read_ureg, SPR_NOACCESS, 4701 &spr_read_ureg, SPR_NOACCESS, 4702 0x00000000); 4703 spr_register(env, SPR_SPRG5, "SPRG5", 4704 SPR_NOACCESS, SPR_NOACCESS, 4705 &spr_read_generic, &spr_write_generic, 4706 0x00000000); 4707 spr_register(env, SPR_USPRG5, "USPRG5", 4708 &spr_read_ureg, SPR_NOACCESS, 4709 &spr_read_ureg, SPR_NOACCESS, 4710 0x00000000); 4711 spr_register(env, SPR_SPRG6, "SPRG6", 4712 SPR_NOACCESS, SPR_NOACCESS, 4713 &spr_read_generic, &spr_write_generic, 4714 0x00000000); 4715 spr_register(env, SPR_USPRG6, "USPRG6", 4716 &spr_read_ureg, SPR_NOACCESS, 4717 &spr_read_ureg, SPR_NOACCESS, 4718 0x00000000); 4719 spr_register(env, SPR_SPRG7, "SPRG7", 4720 SPR_NOACCESS, SPR_NOACCESS, 4721 &spr_read_generic, &spr_write_generic, 4722 0x00000000); 4723 spr_register(env, SPR_USPRG7, "USPRG7", 4724 &spr_read_ureg, SPR_NOACCESS, 4725 &spr_read_ureg, SPR_NOACCESS, 4726 0x00000000); 4727 /* Memory management */ 4728 register_low_BATs(env); 4729 register_high_BATs(env); 4730 init_excp_7450(env); 4731 env->dcache_line_size = 32; 4732 env->icache_line_size = 32; 4733 /* Allocate hardware IRQ controller */ 4734 ppc6xx_irq_init(env_archcpu(env)); 4735 } 4736 4737 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4738 { 4739 DeviceClass *dc = DEVICE_CLASS(oc); 4740 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4741 4742 dc->desc = "PowerPC 7455 (aka G4)"; 4743 pcc->init_proc = init_proc_7455; 4744 pcc->check_pow = check_pow_hid0_74xx; 4745 pcc->check_attn = check_attn_none; 4746 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4747 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4748 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4749 PPC_FLOAT_STFIWX | 4750 PPC_CACHE | PPC_CACHE_ICBI | 4751 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4752 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4753 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4754 PPC_MEM_TLBIA | 4755 PPC_SEGMENT | PPC_EXTERN | 4756 PPC_ALTIVEC; 4757 pcc->msr_mask = (1ull << MSR_VR) | 4758 (1ull << MSR_POW) | 4759 (1ull << MSR_ILE) | 4760 (1ull << MSR_EE) | 4761 (1ull << MSR_PR) | 4762 (1ull << MSR_FP) | 4763 (1ull << MSR_ME) | 4764 (1ull << MSR_FE0) | 4765 (1ull << MSR_SE) | 4766 (1ull << MSR_DE) | 4767 (1ull << MSR_FE1) | 4768 (1ull << MSR_EP) | 4769 (1ull << MSR_IR) | 4770 (1ull << MSR_DR) | 4771 (1ull << MSR_PMM) | 4772 (1ull << MSR_RI) | 4773 (1ull << MSR_LE); 4774 pcc->mmu_model = POWERPC_MMU_32B; 4775 pcc->excp_model = POWERPC_EXCP_74xx; 4776 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4777 pcc->bfd_mach = bfd_mach_ppc_7400; 4778 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4779 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4780 POWERPC_FLAG_BUS_CLK; 4781 } 4782 4783 static void init_proc_7457(CPUPPCState *env) 4784 { 4785 register_non_embedded_sprs(env); 4786 register_sdr1_sprs(env); 4787 register_74xx_sprs(env); 4788 vscr_init(env, 0x00010000); 4789 /* Level 3 cache control */ 4790 register_l3_ctrl(env); 4791 /* L3ITCR1 */ 4792 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4793 SPR_NOACCESS, SPR_NOACCESS, 4794 &spr_read_generic, &spr_write_generic, 4795 0x00000000); 4796 /* L3ITCR2 */ 4797 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4798 SPR_NOACCESS, SPR_NOACCESS, 4799 &spr_read_generic, &spr_write_generic, 4800 0x00000000); 4801 /* L3ITCR3 */ 4802 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4803 SPR_NOACCESS, SPR_NOACCESS, 4804 &spr_read_generic, &spr_write_generic, 4805 0x00000000); 4806 /* L3OHCR */ 4807 spr_register(env, SPR_L3OHCR, "L3OHCR", 4808 SPR_NOACCESS, SPR_NOACCESS, 4809 &spr_read_generic, &spr_write_generic, 4810 0x00000000); 4811 /* LDSTCR */ 4812 spr_register(env, SPR_LDSTCR, "LDSTCR", 4813 SPR_NOACCESS, SPR_NOACCESS, 4814 &spr_read_generic, &spr_write_generic, 4815 0x00000000); 4816 /* ICTRL */ 4817 spr_register(env, SPR_ICTRL, "ICTRL", 4818 SPR_NOACCESS, SPR_NOACCESS, 4819 &spr_read_generic, &spr_write_generic, 4820 0x00000000); 4821 /* MSSSR0 */ 4822 spr_register(env, SPR_MSSSR0, "MSSSR0", 4823 SPR_NOACCESS, SPR_NOACCESS, 4824 &spr_read_generic, &spr_write_generic, 4825 0x00000000); 4826 /* PMC */ 4827 spr_register(env, SPR_7XX_PMC5, "PMC5", 4828 SPR_NOACCESS, SPR_NOACCESS, 4829 &spr_read_generic, &spr_write_generic, 4830 0x00000000); 4831 4832 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4833 &spr_read_ureg, SPR_NOACCESS, 4834 &spr_read_ureg, SPR_NOACCESS, 4835 0x00000000); 4836 4837 spr_register(env, SPR_7XX_PMC6, "PMC6", 4838 SPR_NOACCESS, SPR_NOACCESS, 4839 &spr_read_generic, &spr_write_generic, 4840 0x00000000); 4841 4842 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4843 &spr_read_ureg, SPR_NOACCESS, 4844 &spr_read_ureg, SPR_NOACCESS, 4845 0x00000000); 4846 /* SPRGs */ 4847 spr_register(env, SPR_SPRG4, "SPRG4", 4848 SPR_NOACCESS, SPR_NOACCESS, 4849 &spr_read_generic, &spr_write_generic, 4850 0x00000000); 4851 spr_register(env, SPR_USPRG4, "USPRG4", 4852 &spr_read_ureg, SPR_NOACCESS, 4853 &spr_read_ureg, SPR_NOACCESS, 4854 0x00000000); 4855 spr_register(env, SPR_SPRG5, "SPRG5", 4856 SPR_NOACCESS, SPR_NOACCESS, 4857 &spr_read_generic, &spr_write_generic, 4858 0x00000000); 4859 spr_register(env, SPR_USPRG5, "USPRG5", 4860 &spr_read_ureg, SPR_NOACCESS, 4861 &spr_read_ureg, SPR_NOACCESS, 4862 0x00000000); 4863 spr_register(env, SPR_SPRG6, "SPRG6", 4864 SPR_NOACCESS, SPR_NOACCESS, 4865 &spr_read_generic, &spr_write_generic, 4866 0x00000000); 4867 spr_register(env, SPR_USPRG6, "USPRG6", 4868 &spr_read_ureg, SPR_NOACCESS, 4869 &spr_read_ureg, SPR_NOACCESS, 4870 0x00000000); 4871 spr_register(env, SPR_SPRG7, "SPRG7", 4872 SPR_NOACCESS, SPR_NOACCESS, 4873 &spr_read_generic, &spr_write_generic, 4874 0x00000000); 4875 spr_register(env, SPR_USPRG7, "USPRG7", 4876 &spr_read_ureg, SPR_NOACCESS, 4877 &spr_read_ureg, SPR_NOACCESS, 4878 0x00000000); 4879 /* Memory management */ 4880 register_low_BATs(env); 4881 register_high_BATs(env); 4882 init_excp_7450(env); 4883 env->dcache_line_size = 32; 4884 env->icache_line_size = 32; 4885 /* Allocate hardware IRQ controller */ 4886 ppc6xx_irq_init(env_archcpu(env)); 4887 } 4888 4889 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4890 { 4891 DeviceClass *dc = DEVICE_CLASS(oc); 4892 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4893 4894 dc->desc = "PowerPC 7457 (aka G4)"; 4895 pcc->init_proc = init_proc_7457; 4896 pcc->check_pow = check_pow_hid0_74xx; 4897 pcc->check_attn = check_attn_none; 4898 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4899 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4900 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4901 PPC_FLOAT_STFIWX | 4902 PPC_CACHE | PPC_CACHE_ICBI | 4903 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4904 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4905 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4906 PPC_MEM_TLBIA | 4907 PPC_SEGMENT | PPC_EXTERN | 4908 PPC_ALTIVEC; 4909 pcc->msr_mask = (1ull << MSR_VR) | 4910 (1ull << MSR_POW) | 4911 (1ull << MSR_ILE) | 4912 (1ull << MSR_EE) | 4913 (1ull << MSR_PR) | 4914 (1ull << MSR_FP) | 4915 (1ull << MSR_ME) | 4916 (1ull << MSR_FE0) | 4917 (1ull << MSR_SE) | 4918 (1ull << MSR_DE) | 4919 (1ull << MSR_FE1) | 4920 (1ull << MSR_EP) | 4921 (1ull << MSR_IR) | 4922 (1ull << MSR_DR) | 4923 (1ull << MSR_PMM) | 4924 (1ull << MSR_RI) | 4925 (1ull << MSR_LE); 4926 pcc->mmu_model = POWERPC_MMU_32B; 4927 pcc->excp_model = POWERPC_EXCP_74xx; 4928 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4929 pcc->bfd_mach = bfd_mach_ppc_7400; 4930 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4931 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4932 POWERPC_FLAG_BUS_CLK; 4933 } 4934 4935 static void init_proc_e600(CPUPPCState *env) 4936 { 4937 register_non_embedded_sprs(env); 4938 register_sdr1_sprs(env); 4939 register_74xx_sprs(env); 4940 vscr_init(env, 0x00010000); 4941 4942 spr_register(env, SPR_UBAMR, "UBAMR", 4943 &spr_read_ureg, SPR_NOACCESS, 4944 &spr_read_ureg, SPR_NOACCESS, 4945 0x00000000); 4946 4947 spr_register(env, SPR_LDSTCR, "LDSTCR", 4948 SPR_NOACCESS, SPR_NOACCESS, 4949 &spr_read_generic, &spr_write_generic, 4950 0x00000000); 4951 4952 spr_register(env, SPR_ICTRL, "ICTRL", 4953 SPR_NOACCESS, SPR_NOACCESS, 4954 &spr_read_generic, &spr_write_generic, 4955 0x00000000); 4956 4957 spr_register(env, SPR_MSSSR0, "MSSSR0", 4958 SPR_NOACCESS, SPR_NOACCESS, 4959 &spr_read_generic, &spr_write_generic, 4960 0x00000000); 4961 4962 spr_register(env, SPR_7XX_PMC5, "PMC5", 4963 SPR_NOACCESS, SPR_NOACCESS, 4964 &spr_read_generic, &spr_write_generic, 4965 0x00000000); 4966 4967 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4968 &spr_read_ureg, SPR_NOACCESS, 4969 &spr_read_ureg, SPR_NOACCESS, 4970 0x00000000); 4971 4972 spr_register(env, SPR_7XX_PMC6, "PMC6", 4973 SPR_NOACCESS, SPR_NOACCESS, 4974 &spr_read_generic, &spr_write_generic, 4975 0x00000000); 4976 4977 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4978 &spr_read_ureg, SPR_NOACCESS, 4979 &spr_read_ureg, SPR_NOACCESS, 4980 0x00000000); 4981 /* SPRGs */ 4982 spr_register(env, SPR_SPRG4, "SPRG4", 4983 SPR_NOACCESS, SPR_NOACCESS, 4984 &spr_read_generic, &spr_write_generic, 4985 0x00000000); 4986 spr_register(env, SPR_USPRG4, "USPRG4", 4987 &spr_read_ureg, SPR_NOACCESS, 4988 &spr_read_ureg, SPR_NOACCESS, 4989 0x00000000); 4990 spr_register(env, SPR_SPRG5, "SPRG5", 4991 SPR_NOACCESS, SPR_NOACCESS, 4992 &spr_read_generic, &spr_write_generic, 4993 0x00000000); 4994 spr_register(env, SPR_USPRG5, "USPRG5", 4995 &spr_read_ureg, SPR_NOACCESS, 4996 &spr_read_ureg, SPR_NOACCESS, 4997 0x00000000); 4998 spr_register(env, SPR_SPRG6, "SPRG6", 4999 SPR_NOACCESS, SPR_NOACCESS, 5000 &spr_read_generic, &spr_write_generic, 5001 0x00000000); 5002 spr_register(env, SPR_USPRG6, "USPRG6", 5003 &spr_read_ureg, SPR_NOACCESS, 5004 &spr_read_ureg, SPR_NOACCESS, 5005 0x00000000); 5006 spr_register(env, SPR_SPRG7, "SPRG7", 5007 SPR_NOACCESS, SPR_NOACCESS, 5008 &spr_read_generic, &spr_write_generic, 5009 0x00000000); 5010 spr_register(env, SPR_USPRG7, "USPRG7", 5011 &spr_read_ureg, SPR_NOACCESS, 5012 &spr_read_ureg, SPR_NOACCESS, 5013 0x00000000); 5014 /* Memory management */ 5015 register_low_BATs(env); 5016 register_high_BATs(env); 5017 init_excp_7450(env); 5018 env->dcache_line_size = 32; 5019 env->icache_line_size = 32; 5020 /* Allocate hardware IRQ controller */ 5021 ppc6xx_irq_init(env_archcpu(env)); 5022 } 5023 5024 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5025 { 5026 DeviceClass *dc = DEVICE_CLASS(oc); 5027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5028 5029 dc->desc = "PowerPC e600"; 5030 pcc->init_proc = init_proc_e600; 5031 pcc->check_pow = check_pow_hid0_74xx; 5032 pcc->check_attn = check_attn_none; 5033 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5035 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5036 PPC_FLOAT_STFIWX | 5037 PPC_CACHE | PPC_CACHE_ICBI | 5038 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5039 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5040 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5041 PPC_MEM_TLBIA | 5042 PPC_SEGMENT | PPC_EXTERN | 5043 PPC_ALTIVEC; 5044 pcc->insns_flags2 = PPC_NONE; 5045 pcc->msr_mask = (1ull << MSR_VR) | 5046 (1ull << MSR_POW) | 5047 (1ull << MSR_ILE) | 5048 (1ull << MSR_EE) | 5049 (1ull << MSR_PR) | 5050 (1ull << MSR_FP) | 5051 (1ull << MSR_ME) | 5052 (1ull << MSR_FE0) | 5053 (1ull << MSR_SE) | 5054 (1ull << MSR_DE) | 5055 (1ull << MSR_FE1) | 5056 (1ull << MSR_EP) | 5057 (1ull << MSR_IR) | 5058 (1ull << MSR_DR) | 5059 (1ull << MSR_PMM) | 5060 (1ull << MSR_RI) | 5061 (1ull << MSR_LE); 5062 pcc->mmu_model = POWERPC_MMU_32B; 5063 pcc->excp_model = POWERPC_EXCP_74xx; 5064 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5065 pcc->bfd_mach = bfd_mach_ppc_7400; 5066 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5067 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5068 POWERPC_FLAG_BUS_CLK; 5069 } 5070 5071 #if defined(TARGET_PPC64) 5072 #if defined(CONFIG_USER_ONLY) 5073 #define POWERPC970_HID5_INIT 0x00000080 5074 #else 5075 #define POWERPC970_HID5_INIT 0x00000000 5076 #endif 5077 5078 static int check_pow_970(CPUPPCState *env) 5079 { 5080 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5081 return 1; 5082 } 5083 5084 return 0; 5085 } 5086 5087 static void register_970_hid_sprs(CPUPPCState *env) 5088 { 5089 /* Hardware implementation registers */ 5090 spr_register(env, SPR_HID0, "HID0", 5091 SPR_NOACCESS, SPR_NOACCESS, 5092 &spr_read_generic, &spr_write_clear, 5093 0x60000000); 5094 spr_register(env, SPR_HID1, "HID1", 5095 SPR_NOACCESS, SPR_NOACCESS, 5096 &spr_read_generic, &spr_write_generic, 5097 0x00000000); 5098 spr_register(env, SPR_970_HID5, "HID5", 5099 SPR_NOACCESS, SPR_NOACCESS, 5100 &spr_read_generic, &spr_write_generic, 5101 POWERPC970_HID5_INIT); 5102 } 5103 5104 static void register_970_hior_sprs(CPUPPCState *env) 5105 { 5106 spr_register(env, SPR_HIOR, "HIOR", 5107 SPR_NOACCESS, SPR_NOACCESS, 5108 &spr_read_hior, &spr_write_hior, 5109 0x00000000); 5110 } 5111 5112 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5113 { 5114 spr_register(env, SPR_CTRL, "CTRL", 5115 SPR_NOACCESS, SPR_NOACCESS, 5116 SPR_NOACCESS, &spr_write_CTRL, 5117 0x00000000); 5118 spr_register(env, SPR_UCTRL, "UCTRL", 5119 &spr_read_ureg, SPR_NOACCESS, 5120 &spr_read_ureg, SPR_NOACCESS, 5121 0x00000000); 5122 } 5123 5124 static void register_book3s_altivec_sprs(CPUPPCState *env) 5125 { 5126 if (!(env->insns_flags & PPC_ALTIVEC)) { 5127 return; 5128 } 5129 5130 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5131 &spr_read_generic, &spr_write_generic32, 5132 &spr_read_generic, &spr_write_generic32, 5133 KVM_REG_PPC_VRSAVE, 0x00000000); 5134 5135 } 5136 5137 static void register_book3s_dbg_sprs(CPUPPCState *env) 5138 { 5139 /* 5140 * TODO: different specs define different scopes for these, 5141 * will have to address this: 5142 * 970: super/write and super/read 5143 * powerisa 2.03..2.04: hypv/write and super/read. 5144 * powerisa 2.05 and newer: hypv/write and hypv/read. 5145 */ 5146 spr_register_kvm(env, SPR_DABR, "DABR", 5147 SPR_NOACCESS, SPR_NOACCESS, 5148 &spr_read_generic, &spr_write_generic, 5149 KVM_REG_PPC_DABR, 0x00000000); 5150 spr_register_kvm(env, SPR_DABRX, "DABRX", 5151 SPR_NOACCESS, SPR_NOACCESS, 5152 &spr_read_generic, &spr_write_generic, 5153 KVM_REG_PPC_DABRX, 0x00000000); 5154 } 5155 5156 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5157 { 5158 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5159 SPR_NOACCESS, SPR_NOACCESS, 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_dawr0, 5162 KVM_REG_PPC_DAWR, 0x00000000); 5163 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5164 SPR_NOACCESS, SPR_NOACCESS, 5165 SPR_NOACCESS, SPR_NOACCESS, 5166 &spr_read_generic, &spr_write_dawrx0, 5167 KVM_REG_PPC_DAWRX, 0x00000000); 5168 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 SPR_NOACCESS, SPR_NOACCESS, 5171 &spr_read_generic, &spr_write_ciabr, 5172 KVM_REG_PPC_CIABR, 0x00000000); 5173 } 5174 5175 static void register_book3s_310_dbg_sprs(CPUPPCState *env) 5176 { 5177 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", 5178 SPR_NOACCESS, SPR_NOACCESS, 5179 SPR_NOACCESS, SPR_NOACCESS, 5180 &spr_read_generic, &spr_write_dawr1, 5181 KVM_REG_PPC_DAWR1, 0x00000000); 5182 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", 5183 SPR_NOACCESS, SPR_NOACCESS, 5184 SPR_NOACCESS, SPR_NOACCESS, 5185 &spr_read_generic, &spr_write_dawrx1, 5186 KVM_REG_PPC_DAWRX1, 0x00000000); 5187 } 5188 5189 static void register_970_dbg_sprs(CPUPPCState *env) 5190 { 5191 /* Breakpoints */ 5192 spr_register(env, SPR_IABR, "IABR", 5193 SPR_NOACCESS, SPR_NOACCESS, 5194 &spr_read_generic, &spr_write_generic, 5195 0x00000000); 5196 } 5197 5198 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5199 { 5200 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5201 SPR_NOACCESS, SPR_NOACCESS, 5202 &spr_read_generic, &spr_write_MMCR0, 5203 KVM_REG_PPC_MMCR0, 0x80000000); 5204 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5205 SPR_NOACCESS, SPR_NOACCESS, 5206 &spr_read_generic, &spr_write_MMCR1, 5207 KVM_REG_PPC_MMCR1, 0x00000000); 5208 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5209 SPR_NOACCESS, SPR_NOACCESS, 5210 &spr_read_generic, &spr_write_MMCRA, 5211 KVM_REG_PPC_MMCRA, 0x00000000); 5212 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5213 SPR_NOACCESS, SPR_NOACCESS, 5214 &spr_read_PMC, &spr_write_PMC, 5215 KVM_REG_PPC_PMC1, 0x00000000); 5216 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5217 SPR_NOACCESS, SPR_NOACCESS, 5218 &spr_read_PMC, &spr_write_PMC, 5219 KVM_REG_PPC_PMC2, 0x00000000); 5220 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5221 SPR_NOACCESS, SPR_NOACCESS, 5222 &spr_read_PMC, &spr_write_PMC, 5223 KVM_REG_PPC_PMC3, 0x00000000); 5224 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5225 SPR_NOACCESS, SPR_NOACCESS, 5226 &spr_read_PMC, &spr_write_PMC, 5227 KVM_REG_PPC_PMC4, 0x00000000); 5228 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5229 SPR_NOACCESS, SPR_NOACCESS, 5230 &spr_read_PMC, &spr_write_PMC, 5231 KVM_REG_PPC_PMC5, 0x00000000); 5232 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5233 SPR_NOACCESS, SPR_NOACCESS, 5234 &spr_read_PMC, &spr_write_PMC, 5235 KVM_REG_PPC_PMC6, 0x00000000); 5236 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5237 SPR_NOACCESS, SPR_NOACCESS, 5238 &spr_read_generic, &spr_write_generic, 5239 KVM_REG_PPC_SIAR, 0x00000000); 5240 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5241 SPR_NOACCESS, SPR_NOACCESS, 5242 &spr_read_generic, &spr_write_generic, 5243 KVM_REG_PPC_SDAR, 0x00000000); 5244 } 5245 5246 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5247 { 5248 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5249 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5250 &spr_read_ureg, &spr_write_ureg, 5251 0x80000000); 5252 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5253 &spr_read_ureg, SPR_NOACCESS, 5254 &spr_read_ureg, &spr_write_ureg, 5255 0x00000000); 5256 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5257 &spr_read_ureg, SPR_NOACCESS, 5258 &spr_read_ureg, &spr_write_ureg, 5259 0x00000000); 5260 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5261 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5262 &spr_read_ureg, &spr_write_ureg, 5263 0x00000000); 5264 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5265 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5266 &spr_read_ureg, &spr_write_ureg, 5267 0x00000000); 5268 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5269 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5270 &spr_read_ureg, &spr_write_ureg, 5271 0x00000000); 5272 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5273 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5274 &spr_read_ureg, &spr_write_ureg, 5275 0x00000000); 5276 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5277 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5278 &spr_read_ureg, &spr_write_ureg, 5279 0x00000000); 5280 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5281 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5282 &spr_read_ureg, &spr_write_ureg, 5283 0x00000000); 5284 spr_register(env, SPR_POWER_USIAR, "USIAR", 5285 &spr_read_ureg, SPR_NOACCESS, 5286 &spr_read_ureg, &spr_write_ureg, 5287 0x00000000); 5288 spr_register(env, SPR_POWER_USDAR, "USDAR", 5289 &spr_read_ureg, SPR_NOACCESS, 5290 &spr_read_ureg, &spr_write_ureg, 5291 0x00000000); 5292 } 5293 5294 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5295 { 5296 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5297 SPR_NOACCESS, SPR_NOACCESS, 5298 &spr_read_generic, &spr_write_generic, 5299 KVM_REG_PPC_PMC7, 0x00000000); 5300 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5301 SPR_NOACCESS, SPR_NOACCESS, 5302 &spr_read_generic, &spr_write_generic, 5303 KVM_REG_PPC_PMC8, 0x00000000); 5304 } 5305 5306 static void register_970_pmu_user_sprs(CPUPPCState *env) 5307 { 5308 spr_register(env, SPR_970_UPMC7, "UPMC7", 5309 &spr_read_ureg, SPR_NOACCESS, 5310 &spr_read_ureg, &spr_write_ureg, 5311 0x00000000); 5312 spr_register(env, SPR_970_UPMC8, "UPMC8", 5313 &spr_read_ureg, SPR_NOACCESS, 5314 &spr_read_ureg, &spr_write_ureg, 5315 0x00000000); 5316 } 5317 5318 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5319 { 5320 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5321 SPR_NOACCESS, SPR_NOACCESS, 5322 &spr_read_generic, &spr_write_generic, 5323 KVM_REG_PPC_MMCR2, 0x00000000); 5324 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5325 SPR_NOACCESS, SPR_NOACCESS, 5326 &spr_read_generic, &spr_write_generic, 5327 KVM_REG_PPC_MMCRS, 0x00000000); 5328 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5329 SPR_NOACCESS, SPR_NOACCESS, 5330 &spr_read_generic, &spr_write_generic, 5331 KVM_REG_PPC_SIER, 0x00000000); 5332 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5333 SPR_NOACCESS, SPR_NOACCESS, 5334 &spr_read_generic, &spr_write_generic, 5335 KVM_REG_PPC_SPMC1, 0x00000000); 5336 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5337 SPR_NOACCESS, SPR_NOACCESS, 5338 &spr_read_generic, &spr_write_generic, 5339 KVM_REG_PPC_SPMC2, 0x00000000); 5340 spr_register_kvm(env, SPR_TACR, "TACR", 5341 SPR_NOACCESS, SPR_NOACCESS, 5342 &spr_read_generic, &spr_write_generic, 5343 KVM_REG_PPC_TACR, 0x00000000); 5344 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5345 SPR_NOACCESS, SPR_NOACCESS, 5346 &spr_read_generic, &spr_write_generic, 5347 KVM_REG_PPC_TCSCR, 0x00000000); 5348 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5349 SPR_NOACCESS, SPR_NOACCESS, 5350 &spr_read_generic, &spr_write_generic, 5351 KVM_REG_PPC_CSIGR, 0x00000000); 5352 } 5353 5354 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5355 { 5356 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5357 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5358 &spr_read_ureg, &spr_write_ureg, 5359 0x00000000); 5360 spr_register(env, SPR_POWER_USIER, "USIER", 5361 &spr_read_generic, SPR_NOACCESS, 5362 &spr_read_generic, &spr_write_generic, 5363 0x00000000); 5364 } 5365 5366 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5367 { 5368 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5369 SPR_NOACCESS, SPR_NOACCESS, 5370 &spr_read_generic, &spr_write_generic, 5371 KVM_REG_PPC_MMCR3, 0x00000000); 5372 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5373 SPR_NOACCESS, SPR_NOACCESS, 5374 &spr_read_generic, &spr_write_generic, 5375 KVM_REG_PPC_SIER2, 0x00000000); 5376 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5377 SPR_NOACCESS, SPR_NOACCESS, 5378 &spr_read_generic, &spr_write_generic, 5379 KVM_REG_PPC_SIER3, 0x00000000); 5380 } 5381 5382 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5383 { 5384 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5385 &spr_read_generic, &spr_write_generic, 5386 &spr_read_generic, &spr_write_generic, 5387 0x00000000); 5388 spr_register(env, SPR_POWER_USIER2, "USIER2", 5389 &spr_read_generic, SPR_NOACCESS, 5390 &spr_read_generic, &spr_write_generic, 5391 0x00000000); 5392 spr_register(env, SPR_POWER_USIER3, "USIER3", 5393 &spr_read_generic, SPR_NOACCESS, 5394 &spr_read_generic, &spr_write_generic, 5395 0x00000000); 5396 } 5397 5398 static void register_power5p_ear_sprs(CPUPPCState *env) 5399 { 5400 /* External access control */ 5401 spr_register(env, SPR_EAR, "EAR", 5402 SPR_NOACCESS, SPR_NOACCESS, 5403 &spr_read_generic, &spr_write_generic, 5404 0x00000000); 5405 } 5406 5407 static void register_power5p_tb_sprs(CPUPPCState *env) 5408 { 5409 /* TBU40 (High 40 bits of the Timebase register */ 5410 spr_register_hv(env, SPR_TBU40, "TBU40", 5411 SPR_NOACCESS, SPR_NOACCESS, 5412 SPR_NOACCESS, SPR_NOACCESS, 5413 SPR_NOACCESS, &spr_write_tbu40, 5414 0x00000000); 5415 } 5416 5417 static void register_970_lpar_sprs(CPUPPCState *env) 5418 { 5419 #if !defined(CONFIG_USER_ONLY) 5420 /* 5421 * PPC970: HID4 covers things later controlled by the LPCR and 5422 * RMOR in later CPUs, but with a different encoding. We only 5423 * support the 970 in "Apple mode" which has all hypervisor 5424 * facilities disabled by strapping, so we can basically just 5425 * ignore it 5426 */ 5427 spr_register(env, SPR_970_HID4, "HID4", 5428 SPR_NOACCESS, SPR_NOACCESS, 5429 &spr_read_generic, &spr_write_generic, 5430 0x00000000); 5431 #endif 5432 } 5433 5434 static void register_power5p_lpar_sprs(CPUPPCState *env) 5435 { 5436 #if !defined(CONFIG_USER_ONLY) 5437 /* Logical partitioning */ 5438 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5439 SPR_NOACCESS, SPR_NOACCESS, 5440 SPR_NOACCESS, SPR_NOACCESS, 5441 &spr_read_generic, &spr_write_lpcr, 5442 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5443 spr_register_hv(env, SPR_HDEC, "HDEC", 5444 SPR_NOACCESS, SPR_NOACCESS, 5445 SPR_NOACCESS, SPR_NOACCESS, 5446 &spr_read_hdecr, &spr_write_hdecr, 0); 5447 #endif 5448 } 5449 5450 static void register_book3s_ids_sprs(CPUPPCState *env) 5451 { 5452 /* FIXME: Will need to deal with thread vs core only SPRs */ 5453 5454 /* Processor identification */ 5455 spr_register_hv(env, SPR_PIR, "PIR", 5456 SPR_NOACCESS, SPR_NOACCESS, 5457 &spr_read_generic, SPR_NOACCESS, 5458 &spr_read_generic, NULL, 5459 0x00000000); 5460 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 SPR_NOACCESS, SPR_NOACCESS, 5463 &spr_read_generic, &spr_write_lpidr, 5464 0x00000000); 5465 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5466 SPR_NOACCESS, SPR_NOACCESS, 5467 SPR_NOACCESS, SPR_NOACCESS, 5468 &spr_read_generic, &spr_write_generic, 5469 0x00000000); 5470 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 SPR_NOACCESS, SPR_NOACCESS, 5473 &spr_read_generic, &spr_core_write_generic32, 5474 0x00000000); 5475 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 SPR_NOACCESS, SPR_NOACCESS, 5478 &spr_read_generic, &spr_write_generic, 5479 0x00000000); 5480 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 SPR_NOACCESS, SPR_NOACCESS, 5483 &spr_read_generic, &spr_write_generic, 5484 0x00000000); 5485 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 SPR_NOACCESS, SPR_NOACCESS, 5488 &spr_read_generic, &spr_write_generic, 5489 0x00000000); 5490 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 SPR_NOACCESS, SPR_NOACCESS, 5493 &spr_read_generic, &spr_write_generic, 5494 0x00000000); 5495 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5496 SPR_NOACCESS, SPR_NOACCESS, 5497 SPR_NOACCESS, SPR_NOACCESS, 5498 &spr_read_generic, &spr_write_generic, 5499 0x00000000); 5500 spr_register_hv(env, SPR_HDAR, "HDAR", 5501 SPR_NOACCESS, SPR_NOACCESS, 5502 SPR_NOACCESS, SPR_NOACCESS, 5503 &spr_read_generic, &spr_write_generic, 5504 0x00000000); 5505 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5506 SPR_NOACCESS, SPR_NOACCESS, 5507 SPR_NOACCESS, SPR_NOACCESS, 5508 &spr_read_generic, &spr_write_generic32, 5509 0x00000000); 5510 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5511 SPR_NOACCESS, SPR_NOACCESS, 5512 SPR_NOACCESS, SPR_NOACCESS, 5513 &spr_read_generic, &spr_core_write_generic, 5514 0x00000000); 5515 } 5516 5517 static void register_rmor_sprs(CPUPPCState *env) 5518 { 5519 spr_register_hv(env, SPR_RMOR, "RMOR", 5520 SPR_NOACCESS, SPR_NOACCESS, 5521 SPR_NOACCESS, SPR_NOACCESS, 5522 &spr_read_generic, &spr_write_generic, 5523 0x00000000); 5524 } 5525 5526 static void register_power8_ids_sprs(CPUPPCState *env) 5527 { 5528 /* Thread identification */ 5529 spr_register(env, SPR_TIR, "TIR", 5530 SPR_NOACCESS, SPR_NOACCESS, 5531 &spr_read_generic, SPR_NOACCESS, 5532 0x00000000); 5533 } 5534 5535 static void register_book3s_purr_sprs(CPUPPCState *env) 5536 { 5537 #if !defined(CONFIG_USER_ONLY) 5538 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5539 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5540 &spr_read_purr, SPR_NOACCESS, 5541 &spr_read_purr, SPR_NOACCESS, 5542 &spr_read_purr, &spr_write_purr, 5543 KVM_REG_PPC_PURR, 0x00000000); 5544 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5545 &spr_read_purr, SPR_NOACCESS, 5546 &spr_read_purr, SPR_NOACCESS, 5547 &spr_read_purr, &spr_write_purr, 5548 KVM_REG_PPC_SPURR, 0x00000000); 5549 #endif 5550 } 5551 5552 static void register_power6_dbg_sprs(CPUPPCState *env) 5553 { 5554 #if !defined(CONFIG_USER_ONLY) 5555 spr_register(env, SPR_CFAR, "CFAR", 5556 SPR_NOACCESS, SPR_NOACCESS, 5557 &spr_read_cfar, &spr_write_cfar, 5558 0x00000000); 5559 #endif 5560 } 5561 5562 static void register_power5p_common_sprs(CPUPPCState *env) 5563 { 5564 spr_register_kvm(env, SPR_PPR, "PPR", 5565 &spr_read_generic, &spr_write_generic, 5566 &spr_read_generic, &spr_write_generic, 5567 KVM_REG_PPC_PPR, 0x00000000); 5568 } 5569 5570 static void register_power6_common_sprs(CPUPPCState *env) 5571 { 5572 #if !defined(CONFIG_USER_ONLY) 5573 spr_register_kvm(env, SPR_DSCR, "DSCR", 5574 SPR_NOACCESS, SPR_NOACCESS, 5575 &spr_read_generic, &spr_write_generic, 5576 KVM_REG_PPC_DSCR, 0x00000000); 5577 #endif 5578 /* 5579 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5580 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5581 */ 5582 spr_register_hv(env, SPR_PCR, "PCR", 5583 SPR_NOACCESS, SPR_NOACCESS, 5584 SPR_NOACCESS, SPR_NOACCESS, 5585 &spr_read_generic, &spr_write_pcr, 5586 0x00000000); 5587 } 5588 5589 static void register_HEIR32_spr(CPUPPCState *env) 5590 { 5591 spr_register_hv(env, SPR_HEIR, "HEIR", 5592 SPR_NOACCESS, SPR_NOACCESS, 5593 SPR_NOACCESS, SPR_NOACCESS, 5594 &spr_read_generic, &spr_write_generic32, 5595 0x00000000); 5596 } 5597 5598 static void register_HEIR64_spr(CPUPPCState *env) 5599 { 5600 spr_register_hv(env, SPR_HEIR, "HEIR", 5601 SPR_NOACCESS, SPR_NOACCESS, 5602 SPR_NOACCESS, SPR_NOACCESS, 5603 &spr_read_generic, &spr_write_generic, 5604 0x00000000); 5605 } 5606 5607 static void register_power7_common_sprs(CPUPPCState *env) 5608 { 5609 spr_register(env, SPR_PPR32, "PPR32", 5610 &spr_read_ppr32, &spr_write_ppr32, 5611 &spr_read_ppr32, &spr_write_ppr32, 5612 0x00000000); 5613 } 5614 5615 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5616 { 5617 spr_register_kvm(env, SPR_TAR, "TAR", 5618 &spr_read_tar, &spr_write_tar, 5619 &spr_read_generic, &spr_write_generic, 5620 KVM_REG_PPC_TAR, 0x00000000); 5621 } 5622 5623 static void register_power8_tm_sprs(CPUPPCState *env) 5624 { 5625 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5626 &spr_read_tm, &spr_write_tm, 5627 &spr_read_tm, &spr_write_tm, 5628 KVM_REG_PPC_TFHAR, 0x00000000); 5629 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5630 &spr_read_tm, &spr_write_tm, 5631 &spr_read_tm, &spr_write_tm, 5632 KVM_REG_PPC_TFIAR, 0x00000000); 5633 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5634 &spr_read_tm, &spr_write_tm, 5635 &spr_read_tm, &spr_write_tm, 5636 KVM_REG_PPC_TEXASR, 0x00000000); 5637 spr_register(env, SPR_TEXASRU, "TEXASRU", 5638 &spr_read_tm_upper32, &spr_write_tm_upper32, 5639 &spr_read_tm_upper32, &spr_write_tm_upper32, 5640 0x00000000); 5641 } 5642 5643 static void register_power8_ebb_sprs(CPUPPCState *env) 5644 { 5645 spr_register(env, SPR_BESCRS, "BESCRS", 5646 &spr_read_ebb, &spr_write_ebb, 5647 &spr_read_generic, &spr_write_generic, 5648 0x00000000); 5649 spr_register(env, SPR_BESCRSU, "BESCRSU", 5650 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5651 &spr_read_prev_upper32, &spr_write_prev_upper32, 5652 0x00000000); 5653 spr_register(env, SPR_BESCRR, "BESCRR", 5654 &spr_read_ebb, &spr_write_ebb, 5655 &spr_read_generic, &spr_write_generic, 5656 0x00000000); 5657 spr_register(env, SPR_BESCRRU, "BESCRRU", 5658 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5659 &spr_read_prev_upper32, &spr_write_prev_upper32, 5660 0x00000000); 5661 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5662 &spr_read_ebb, &spr_write_ebb, 5663 &spr_read_generic, &spr_write_generic, 5664 KVM_REG_PPC_EBBHR, 0x00000000); 5665 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5666 &spr_read_ebb, &spr_write_ebb, 5667 &spr_read_generic, &spr_write_generic, 5668 KVM_REG_PPC_EBBRR, 0x00000000); 5669 spr_register_kvm(env, SPR_BESCR, "BESCR", 5670 &spr_read_ebb, &spr_write_ebb, 5671 &spr_read_generic, &spr_write_generic, 5672 KVM_REG_PPC_BESCR, 0x00000000); 5673 } 5674 5675 /* Virtual Time Base */ 5676 static void register_vtb_sprs(CPUPPCState *env) 5677 { 5678 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5679 SPR_NOACCESS, SPR_NOACCESS, 5680 &spr_read_vtb, SPR_NOACCESS, 5681 &spr_read_vtb, &spr_write_vtb, 5682 KVM_REG_PPC_VTB, 0x00000000); 5683 } 5684 5685 static void register_power8_fscr_sprs(CPUPPCState *env) 5686 { 5687 #if defined(CONFIG_USER_ONLY) 5688 target_ulong initval = 1ULL << FSCR_TAR; 5689 #else 5690 target_ulong initval = 0; 5691 #endif 5692 spr_register_kvm(env, SPR_FSCR, "FSCR", 5693 SPR_NOACCESS, SPR_NOACCESS, 5694 &spr_read_generic, &spr_write_generic, 5695 KVM_REG_PPC_FSCR, initval); 5696 } 5697 5698 static void register_power8_pspb_sprs(CPUPPCState *env) 5699 { 5700 spr_register_kvm(env, SPR_PSPB, "PSPB", 5701 SPR_NOACCESS, SPR_NOACCESS, 5702 &spr_read_generic, &spr_write_generic32, 5703 KVM_REG_PPC_PSPB, 0); 5704 } 5705 5706 static void register_power8_dpdes_sprs(CPUPPCState *env) 5707 { 5708 #if !defined(CONFIG_USER_ONLY) 5709 /* Directed Privileged Door-bell Exception State, used for IPI */ 5710 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5711 SPR_NOACCESS, SPR_NOACCESS, 5712 &spr_read_dpdes, SPR_NOACCESS, 5713 &spr_read_dpdes, &spr_write_dpdes, 5714 KVM_REG_PPC_DPDES, 0x00000000); 5715 #endif 5716 } 5717 5718 static void register_power8_ic_sprs(CPUPPCState *env) 5719 { 5720 #if !defined(CONFIG_USER_ONLY) 5721 spr_register_hv(env, SPR_IC, "IC", 5722 SPR_NOACCESS, SPR_NOACCESS, 5723 &spr_read_generic, SPR_NOACCESS, 5724 &spr_read_generic, &spr_write_generic, 5725 0); 5726 #endif 5727 } 5728 5729 /* SPRs specific to IBM POWER CPUs */ 5730 static void register_power_common_book4_sprs(CPUPPCState *env) 5731 { 5732 #if !defined(CONFIG_USER_ONLY) 5733 spr_register_hv(env, SPR_HID0, "HID0", 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 SPR_NOACCESS, SPR_NOACCESS, 5736 &spr_read_generic, &spr_core_write_generic, 5737 0x00000000); 5738 spr_register_hv(env, SPR_TSCR, "TSCR", 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 SPR_NOACCESS, SPR_NOACCESS, 5741 &spr_read_generic, &spr_core_write_generic32, 5742 0x00000000); 5743 spr_register_hv(env, SPR_HMER, "HMER", 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 SPR_NOACCESS, SPR_NOACCESS, 5746 &spr_read_generic, &spr_write_hmer, 5747 0x00000000); 5748 spr_register_hv(env, SPR_HMEER, "HMEER", 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 SPR_NOACCESS, SPR_NOACCESS, 5751 &spr_read_generic, &spr_core_write_generic, 5752 0x00000000); 5753 spr_register_hv(env, SPR_TFMR, "TFMR", 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 SPR_NOACCESS, SPR_NOACCESS, 5756 &spr_read_tfmr, &spr_write_tfmr, 5757 0x00000000); 5758 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_access_nop, &spr_write_generic, 5761 &spr_access_nop, &spr_write_generic, 5762 0x00000000); 5763 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5764 SPR_NOACCESS, SPR_NOACCESS, 5765 &spr_access_nop, &spr_write_generic, 5766 &spr_access_nop, &spr_write_generic, 5767 0x00000000); 5768 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5769 SPR_NOACCESS, SPR_NOACCESS, 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_generic, &spr_core_lpar_write_generic, 5772 0x00000000); 5773 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5774 SPR_NOACCESS, SPR_NOACCESS, 5775 SPR_NOACCESS, SPR_NOACCESS, 5776 &spr_read_generic, &spr_core_write_generic, 5777 0x00000000); 5778 #endif 5779 } 5780 5781 static void register_power9_book4_sprs(CPUPPCState *env) 5782 { 5783 /* Add a number of P9 book4 registers */ 5784 register_power_common_book4_sprs(env); 5785 #if !defined(CONFIG_USER_ONLY) 5786 spr_register_kvm(env, SPR_WORT, "WORT", 5787 SPR_NOACCESS, SPR_NOACCESS, 5788 &spr_read_generic, &spr_write_generic, 5789 KVM_REG_PPC_WORT, 0); 5790 spr_register_hv(env, SPR_RWMR, "RWMR", 5791 SPR_NOACCESS, SPR_NOACCESS, 5792 &spr_read_generic, &spr_write_generic, 5793 &spr_read_generic, &spr_write_generic, 5794 0x00000000); 5795 #endif 5796 } 5797 5798 static void register_power8_book4_sprs(CPUPPCState *env) 5799 { 5800 /* Add a number of P8 book4 registers */ 5801 register_power_common_book4_sprs(env); 5802 #if !defined(CONFIG_USER_ONLY) 5803 spr_register_kvm(env, SPR_ACOP, "ACOP", 5804 SPR_NOACCESS, SPR_NOACCESS, 5805 &spr_read_generic, &spr_write_generic, 5806 KVM_REG_PPC_ACOP, 0); 5807 /* PID is only in BookE in ISA v2.07 */ 5808 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5809 SPR_NOACCESS, SPR_NOACCESS, 5810 &spr_read_generic, &spr_write_pidr, 5811 KVM_REG_PPC_PID, 0); 5812 spr_register_kvm(env, SPR_WORT, "WORT", 5813 SPR_NOACCESS, SPR_NOACCESS, 5814 &spr_read_generic, &spr_write_generic, 5815 KVM_REG_PPC_WORT, 0); 5816 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */ 5817 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5818 SPR_NOACCESS, SPR_NOACCESS, 5819 SPR_NOACCESS, SPR_NOACCESS, 5820 &spr_read_generic, &spr_write_sprc, 5821 0x00000000); 5822 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5823 SPR_NOACCESS, SPR_NOACCESS, 5824 SPR_NOACCESS, SPR_NOACCESS, 5825 &spr_read_sprd, &spr_write_sprd, 5826 0x00000000); 5827 #endif 5828 } 5829 5830 static void register_power7_book4_sprs(CPUPPCState *env) 5831 { 5832 /* Add a number of P7 book4 registers */ 5833 #if !defined(CONFIG_USER_ONLY) 5834 register_power_common_book4_sprs(env); 5835 spr_register_kvm(env, SPR_ACOP, "ACOP", 5836 SPR_NOACCESS, SPR_NOACCESS, 5837 &spr_read_generic, &spr_write_generic, 5838 KVM_REG_PPC_ACOP, 0); 5839 /* PID is only in BookE in ISA v2.06 */ 5840 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_generic, &spr_write_generic32, 5843 KVM_REG_PPC_PID, 0); 5844 #endif 5845 } 5846 5847 static void register_power8_rpr_sprs(CPUPPCState *env) 5848 { 5849 #if !defined(CONFIG_USER_ONLY) 5850 spr_register_hv(env, SPR_RPR, "RPR", 5851 SPR_NOACCESS, SPR_NOACCESS, 5852 SPR_NOACCESS, SPR_NOACCESS, 5853 &spr_read_generic, &spr_core_write_generic, 5854 0x00000103070F1F3F); 5855 #endif 5856 } 5857 5858 static void register_power9_mmu_sprs(CPUPPCState *env) 5859 { 5860 #if !defined(CONFIG_USER_ONLY) 5861 /* Partition Table Control */ 5862 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5863 SPR_NOACCESS, SPR_NOACCESS, 5864 SPR_NOACCESS, SPR_NOACCESS, 5865 &spr_read_generic, &spr_write_ptcr, 5866 KVM_REG_PPC_PTCR, 0x00000000); 5867 /* Address Segment Descriptor Register */ 5868 spr_register_hv(env, SPR_ASDR, "ASDR", 5869 SPR_NOACCESS, SPR_NOACCESS, 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 &spr_read_generic, &spr_write_generic, 5872 0x0000000000000000); 5873 /* PID is part of the BookS ISA from v3.0 */ 5874 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5875 SPR_NOACCESS, SPR_NOACCESS, 5876 &spr_read_generic, &spr_write_pidr, 5877 KVM_REG_PPC_PID, 0); 5878 #endif 5879 } 5880 5881 static void register_power10_hash_sprs(CPUPPCState *env) 5882 { 5883 /* 5884 * it's the OS responsibility to generate a random value for the registers 5885 * in each process' context. So, initialize it with 0 here. 5886 */ 5887 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5888 #if defined(CONFIG_USER_ONLY) 5889 /* in linux-user, setup the hash register with a random value */ 5890 GRand *rand = g_rand_new(); 5891 hashkeyr_initial_value = 5892 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5893 hashpkeyr_initial_value = 5894 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5895 g_rand_free(rand); 5896 #endif 5897 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR", 5898 SPR_NOACCESS, SPR_NOACCESS, 5899 &spr_read_generic, &spr_write_generic, 5900 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value); 5901 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5902 SPR_NOACCESS, SPR_NOACCESS, 5903 SPR_NOACCESS, SPR_NOACCESS, 5904 &spr_read_generic, &spr_write_generic, 5905 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value); 5906 } 5907 5908 static void register_power10_dexcr_sprs(CPUPPCState *env) 5909 { 5910 spr_register_kvm(env, SPR_DEXCR, "DEXCR", 5911 SPR_NOACCESS, SPR_NOACCESS, 5912 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR, 5913 0); 5914 5915 spr_register(env, SPR_UDEXCR, "UDEXCR", 5916 &spr_read_dexcr_ureg, SPR_NOACCESS, 5917 &spr_read_dexcr_ureg, SPR_NOACCESS, 5918 0); 5919 5920 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 SPR_NOACCESS, SPR_NOACCESS, 5923 &spr_read_generic, &spr_write_generic, 5924 0); 5925 5926 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5927 &spr_read_dexcr_ureg, SPR_NOACCESS, 5928 &spr_read_dexcr_ureg, SPR_NOACCESS, 5929 0); 5930 } 5931 5932 /* 5933 * Initialize PMU counter overflow timers for Power8 and 5934 * newer Power chips when using TCG. 5935 */ 5936 static void init_tcg_pmu_power8(CPUPPCState *env) 5937 { 5938 /* Init PMU overflow timers */ 5939 if (tcg_enabled()) { 5940 cpu_ppc_pmu_init(env); 5941 } 5942 } 5943 5944 static void init_proc_book3s_common(CPUPPCState *env) 5945 { 5946 register_non_embedded_sprs(env); 5947 register_book3s_altivec_sprs(env); 5948 register_book3s_pmu_sup_sprs(env); 5949 register_book3s_pmu_user_sprs(env); 5950 register_book3s_ctrl_sprs(env); 5951 /* 5952 * Can't find information on what this should be on reset. This 5953 * value is the one used by 74xx processors. 5954 */ 5955 vscr_init(env, 0x00010000); 5956 5957 spr_register(env, SPR_USPRG3, "USPRG3", 5958 &spr_read_ureg, SPR_NOACCESS, 5959 &spr_read_ureg, SPR_NOACCESS, 5960 0x00000000); 5961 } 5962 5963 static void init_proc_970(CPUPPCState *env) 5964 { 5965 /* Common Registers */ 5966 init_proc_book3s_common(env); 5967 register_sdr1_sprs(env); 5968 register_book3s_dbg_sprs(env); 5969 5970 /* 970 Specific Registers */ 5971 register_970_hid_sprs(env); 5972 register_970_hior_sprs(env); 5973 register_low_BATs(env); 5974 register_970_pmu_sup_sprs(env); 5975 register_970_pmu_user_sprs(env); 5976 register_970_lpar_sprs(env); 5977 register_970_dbg_sprs(env); 5978 5979 /* env variables */ 5980 env->dcache_line_size = 128; 5981 env->icache_line_size = 128; 5982 5983 /* Allocate hardware IRQ controller */ 5984 init_excp_970(env); 5985 ppc970_irq_init(env_archcpu(env)); 5986 } 5987 5988 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5989 { 5990 DeviceClass *dc = DEVICE_CLASS(oc); 5991 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5992 5993 dc->desc = "PowerPC 970"; 5994 pcc->init_proc = init_proc_970; 5995 pcc->check_pow = check_pow_970; 5996 pcc->check_attn = check_attn_hid0; 5997 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5998 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5999 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6000 PPC_FLOAT_STFIWX | 6001 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6002 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6003 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6004 PPC_64B | PPC_ALTIVEC | 6005 PPC_SEGMENT_64B | PPC_SLBI; 6006 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6007 pcc->msr_mask = (1ull << MSR_SF) | 6008 (1ull << MSR_VR) | 6009 (1ull << MSR_POW) | 6010 (1ull << MSR_EE) | 6011 (1ull << MSR_PR) | 6012 (1ull << MSR_FP) | 6013 (1ull << MSR_ME) | 6014 (1ull << MSR_FE0) | 6015 (1ull << MSR_SE) | 6016 (1ull << MSR_DE) | 6017 (1ull << MSR_FE1) | 6018 (1ull << MSR_IR) | 6019 (1ull << MSR_DR) | 6020 (1ull << MSR_PMM) | 6021 (1ull << MSR_RI); 6022 pcc->mmu_model = POWERPC_MMU_64B; 6023 #if !defined(CONFIG_USER_ONLY) 6024 pcc->hash64_opts = &ppc_hash64_opts_basic; 6025 #endif 6026 pcc->excp_model = POWERPC_EXCP_970; 6027 pcc->bus_model = PPC_FLAGS_INPUT_970; 6028 pcc->bfd_mach = bfd_mach_ppc64; 6029 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6030 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6031 POWERPC_FLAG_BUS_CLK; 6032 pcc->l1_dcache_size = 0x8000; 6033 pcc->l1_icache_size = 0x10000; 6034 } 6035 6036 static void init_proc_power5plus(CPUPPCState *env) 6037 { 6038 /* Common Registers */ 6039 init_proc_book3s_common(env); 6040 register_sdr1_sprs(env); 6041 register_book3s_dbg_sprs(env); 6042 6043 /* POWER5+ Specific Registers */ 6044 register_970_hid_sprs(env); 6045 register_970_hior_sprs(env); 6046 register_low_BATs(env); 6047 register_970_pmu_sup_sprs(env); 6048 register_970_pmu_user_sprs(env); 6049 register_power5p_common_sprs(env); 6050 register_power5p_lpar_sprs(env); 6051 register_power5p_ear_sprs(env); 6052 register_power5p_tb_sprs(env); 6053 6054 /* env variables */ 6055 env->dcache_line_size = 128; 6056 env->icache_line_size = 128; 6057 6058 /* Allocate hardware IRQ controller */ 6059 init_excp_970(env); 6060 ppc970_irq_init(env_archcpu(env)); 6061 } 6062 6063 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6064 { 6065 DeviceClass *dc = DEVICE_CLASS(oc); 6066 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6067 6068 dc->fw_name = "PowerPC,POWER5"; 6069 dc->desc = "POWER5+"; 6070 pcc->init_proc = init_proc_power5plus; 6071 pcc->check_pow = check_pow_970; 6072 pcc->check_attn = check_attn_hid0; 6073 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6074 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6075 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6076 PPC_FLOAT_STFIWX | 6077 PPC_FLOAT_EXT | 6078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6079 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6081 PPC_64B | 6082 PPC_POPCNTB | 6083 PPC_SEGMENT_64B | PPC_SLBI; 6084 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6085 pcc->msr_mask = (1ull << MSR_SF) | 6086 (1ull << MSR_VR) | 6087 (1ull << MSR_POW) | 6088 (1ull << MSR_EE) | 6089 (1ull << MSR_PR) | 6090 (1ull << MSR_FP) | 6091 (1ull << MSR_ME) | 6092 (1ull << MSR_FE0) | 6093 (1ull << MSR_SE) | 6094 (1ull << MSR_DE) | 6095 (1ull << MSR_FE1) | 6096 (1ull << MSR_IR) | 6097 (1ull << MSR_DR) | 6098 (1ull << MSR_PMM) | 6099 (1ull << MSR_RI); 6100 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6101 LPCR_RMI | LPCR_HDICE; 6102 pcc->mmu_model = POWERPC_MMU_2_03; 6103 #if !defined(CONFIG_USER_ONLY) 6104 pcc->hash64_opts = &ppc_hash64_opts_basic; 6105 pcc->lrg_decr_bits = 32; 6106 #endif 6107 pcc->excp_model = POWERPC_EXCP_970; 6108 pcc->bus_model = PPC_FLAGS_INPUT_970; 6109 pcc->bfd_mach = bfd_mach_ppc64; 6110 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6111 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6112 POWERPC_FLAG_BUS_CLK; 6113 pcc->l1_dcache_size = 0x8000; 6114 pcc->l1_icache_size = 0x10000; 6115 } 6116 6117 static void init_proc_POWER7(CPUPPCState *env) 6118 { 6119 /* Common Registers */ 6120 init_proc_book3s_common(env); 6121 register_sdr1_sprs(env); 6122 register_book3s_dbg_sprs(env); 6123 6124 /* POWER7 Specific Registers */ 6125 register_book3s_ids_sprs(env); 6126 register_rmor_sprs(env); 6127 register_amr_sprs(env); 6128 register_book3s_purr_sprs(env); 6129 register_power5p_common_sprs(env); 6130 register_power5p_lpar_sprs(env); 6131 register_power5p_ear_sprs(env); 6132 register_power5p_tb_sprs(env); 6133 register_power6_common_sprs(env); 6134 register_HEIR32_spr(env); 6135 register_power6_dbg_sprs(env); 6136 register_power7_common_sprs(env); 6137 register_power7_book4_sprs(env); 6138 6139 /* env variables */ 6140 env->dcache_line_size = 128; 6141 env->icache_line_size = 128; 6142 6143 /* Allocate hardware IRQ controller */ 6144 init_excp_POWER7(env); 6145 ppcPOWER7_irq_init(env_archcpu(env)); 6146 } 6147 6148 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6149 { 6150 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6151 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6152 6153 if (!best) { 6154 if (base == CPU_POWERPC_POWER7_BASE) { 6155 return true; 6156 } 6157 if (base == CPU_POWERPC_POWER7P_BASE) { 6158 return true; 6159 } 6160 } 6161 6162 if (base != pcc_base) { 6163 return false; 6164 } 6165 6166 return true; 6167 } 6168 6169 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6170 { 6171 DeviceClass *dc = DEVICE_CLASS(oc); 6172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6173 6174 dc->fw_name = "PowerPC,POWER7"; 6175 dc->desc = "POWER7"; 6176 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS; 6177 pcc->pvr_match = ppc_pvr_match_power7; 6178 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6179 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6180 pcc->init_proc = init_proc_POWER7; 6181 pcc->check_pow = check_pow_nocheck; 6182 pcc->check_attn = check_attn_hid0; 6183 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6184 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6185 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6186 PPC_FLOAT_FRSQRTES | 6187 PPC_FLOAT_STFIWX | 6188 PPC_FLOAT_EXT | 6189 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6190 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6191 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6192 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6193 PPC_SEGMENT_64B | PPC_SLBI | 6194 PPC_POPCNTB | PPC_POPCNTWD | 6195 PPC_CILDST; 6196 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6197 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6198 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6199 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6200 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6201 pcc->msr_mask = (1ull << MSR_SF) | 6202 (1ull << MSR_VR) | 6203 (1ull << MSR_VSX) | 6204 (1ull << MSR_EE) | 6205 (1ull << MSR_PR) | 6206 (1ull << MSR_FP) | 6207 (1ull << MSR_ME) | 6208 (1ull << MSR_FE0) | 6209 (1ull << MSR_SE) | 6210 (1ull << MSR_DE) | 6211 (1ull << MSR_FE1) | 6212 (1ull << MSR_IR) | 6213 (1ull << MSR_DR) | 6214 (1ull << MSR_PMM) | 6215 (1ull << MSR_RI) | 6216 (1ull << MSR_LE); 6217 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6218 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6219 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6220 LPCR_MER | LPCR_TC | 6221 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6222 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6223 pcc->mmu_model = POWERPC_MMU_2_06; 6224 #if !defined(CONFIG_USER_ONLY) 6225 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6226 pcc->lrg_decr_bits = 32; 6227 #endif 6228 pcc->excp_model = POWERPC_EXCP_POWER7; 6229 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6230 pcc->bfd_mach = bfd_mach_ppc64; 6231 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6232 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6233 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6234 POWERPC_FLAG_VSX; 6235 pcc->l1_dcache_size = 0x8000; 6236 pcc->l1_icache_size = 0x8000; 6237 } 6238 6239 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6240 { 6241 if (env->flags & POWERPC_FLAG_BHRB) { 6242 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6243 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6244 } 6245 env->bhrb_num_entries = 1 << num_entries_log2; 6246 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6247 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6248 } 6249 } 6250 6251 static void bhrb_reset_state(CPUPPCState *env) 6252 { 6253 if (env->flags & POWERPC_FLAG_BHRB) { 6254 env->bhrb_offset = 0; 6255 env->bhrb_filter = 0; 6256 memset(env->bhrb, 0, sizeof(env->bhrb)); 6257 } 6258 } 6259 6260 #define POWER8_BHRB_ENTRIES_LOG2 5 6261 static void init_proc_POWER8(CPUPPCState *env) 6262 { 6263 /* Common Registers */ 6264 init_proc_book3s_common(env); 6265 register_sdr1_sprs(env); 6266 register_book3s_207_dbg_sprs(env); 6267 6268 /* Common TCG PMU */ 6269 init_tcg_pmu_power8(env); 6270 6271 /* POWER8 Specific Registers */ 6272 register_book3s_ids_sprs(env); 6273 register_rmor_sprs(env); 6274 register_amr_sprs(env); 6275 register_iamr_sprs(env); 6276 register_book3s_purr_sprs(env); 6277 register_power5p_common_sprs(env); 6278 register_power5p_lpar_sprs(env); 6279 register_power5p_ear_sprs(env); 6280 register_power5p_tb_sprs(env); 6281 register_power6_common_sprs(env); 6282 register_HEIR32_spr(env); 6283 register_power6_dbg_sprs(env); 6284 register_power7_common_sprs(env); 6285 register_power8_tce_address_control_sprs(env); 6286 register_power8_ids_sprs(env); 6287 register_power8_ebb_sprs(env); 6288 register_power8_fscr_sprs(env); 6289 register_power8_pmu_sup_sprs(env); 6290 register_power8_pmu_user_sprs(env); 6291 register_power8_tm_sprs(env); 6292 register_power8_pspb_sprs(env); 6293 register_power8_dpdes_sprs(env); 6294 register_vtb_sprs(env); 6295 register_power8_ic_sprs(env); 6296 register_power8_book4_sprs(env); 6297 register_power8_rpr_sprs(env); 6298 6299 /* env variables */ 6300 env->dcache_line_size = 128; 6301 env->icache_line_size = 128; 6302 6303 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6304 6305 /* Allocate hardware IRQ controller */ 6306 init_excp_POWER8(env); 6307 ppcPOWER7_irq_init(env_archcpu(env)); 6308 } 6309 6310 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6311 { 6312 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6313 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6314 6315 if (!best) { 6316 if (base == CPU_POWERPC_POWER8_BASE) { 6317 return true; 6318 } 6319 if (base == CPU_POWERPC_POWER8E_BASE) { 6320 return true; 6321 } 6322 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6323 return true; 6324 } 6325 } 6326 if (base != pcc_base) { 6327 return false; 6328 } 6329 6330 return true; 6331 } 6332 6333 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6334 { 6335 DeviceClass *dc = DEVICE_CLASS(oc); 6336 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6337 6338 dc->fw_name = "PowerPC,POWER8"; 6339 dc->desc = "POWER8"; 6340 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07; 6341 pcc->pvr_match = ppc_pvr_match_power8; 6342 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6343 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6344 pcc->init_proc = init_proc_POWER8; 6345 pcc->check_pow = check_pow_nocheck; 6346 pcc->check_attn = check_attn_hid0; 6347 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6348 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6349 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6350 PPC_FLOAT_FRSQRTES | 6351 PPC_FLOAT_STFIWX | 6352 PPC_FLOAT_EXT | 6353 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6354 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6355 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6356 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6357 PPC_SEGMENT_64B | PPC_SLBI | 6358 PPC_POPCNTB | PPC_POPCNTWD | 6359 PPC_CILDST; 6360 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6361 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6362 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6363 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6364 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6365 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6366 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6367 PPC2_BCDA_ISA206; 6368 pcc->msr_mask = (1ull << MSR_SF) | 6369 (1ull << MSR_HV) | 6370 (1ull << MSR_TM) | 6371 (1ull << MSR_VR) | 6372 (1ull << MSR_VSX) | 6373 (1ull << MSR_EE) | 6374 (1ull << MSR_PR) | 6375 (1ull << MSR_FP) | 6376 (1ull << MSR_ME) | 6377 (1ull << MSR_FE0) | 6378 (1ull << MSR_SE) | 6379 (1ull << MSR_DE) | 6380 (1ull << MSR_FE1) | 6381 (1ull << MSR_IR) | 6382 (1ull << MSR_DR) | 6383 (1ull << MSR_PMM) | 6384 (1ull << MSR_RI) | 6385 (1ull << MSR_TS0) | 6386 (1ull << MSR_TS1) | 6387 (1ull << MSR_LE); 6388 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6389 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6390 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6391 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6392 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6393 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6394 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6395 pcc->mmu_model = POWERPC_MMU_2_07; 6396 #if !defined(CONFIG_USER_ONLY) 6397 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6398 pcc->lrg_decr_bits = 32; 6399 pcc->n_host_threads = 8; 6400 #endif 6401 pcc->excp_model = POWERPC_EXCP_POWER8; 6402 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6403 pcc->bfd_mach = bfd_mach_ppc64; 6404 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6405 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6406 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6407 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6408 pcc->l1_dcache_size = 0x8000; 6409 pcc->l1_icache_size = 0x8000; 6410 } 6411 6412 #ifndef CONFIG_USER_ONLY 6413 /* 6414 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6415 * Encoded as array of int_32s in the form: 6416 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6417 * x -> AP encoding 6418 * y -> radix mode supported page size (encoded as a shift) 6419 */ 6420 static struct ppc_radix_page_info POWER9_radix_page_info = { 6421 .count = 4, 6422 .entries = { 6423 0x0000000c, /* 4K - enc: 0x0 */ 6424 0xa0000010, /* 64K - enc: 0x5 */ 6425 0x20000015, /* 2M - enc: 0x1 */ 6426 0x4000001e /* 1G - enc: 0x2 */ 6427 } 6428 }; 6429 #endif /* CONFIG_USER_ONLY */ 6430 6431 #define POWER9_BHRB_ENTRIES_LOG2 5 6432 static void register_power9_common_sprs(CPUPPCState *env) 6433 { 6434 /* Common Registers */ 6435 init_proc_book3s_common(env); 6436 register_book3s_207_dbg_sprs(env); 6437 6438 /* Common TCG PMU */ 6439 init_tcg_pmu_power8(env); 6440 6441 /* POWER8 Specific Registers */ 6442 register_book3s_ids_sprs(env); 6443 register_amr_sprs(env); 6444 register_iamr_sprs(env); 6445 register_book3s_purr_sprs(env); 6446 register_power5p_common_sprs(env); 6447 register_power5p_lpar_sprs(env); 6448 register_power5p_ear_sprs(env); 6449 register_power5p_tb_sprs(env); 6450 register_power6_common_sprs(env); 6451 register_power6_dbg_sprs(env); 6452 register_power7_common_sprs(env); 6453 register_power8_tce_address_control_sprs(env); 6454 register_power8_ids_sprs(env); 6455 register_power8_ebb_sprs(env); 6456 register_power8_fscr_sprs(env); 6457 register_power8_pmu_sup_sprs(env); 6458 register_power8_pmu_user_sprs(env); 6459 register_power8_tm_sprs(env); 6460 register_power8_pspb_sprs(env); 6461 register_power8_dpdes_sprs(env); 6462 register_vtb_sprs(env); 6463 register_power8_ic_sprs(env); 6464 register_power9_book4_sprs(env); 6465 register_power8_rpr_sprs(env); 6466 register_power9_mmu_sprs(env); 6467 6468 /* FIXME: Filter fields properly based on privilege level */ 6469 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6470 spr_read_generic, spr_write_generic, 6471 KVM_REG_PPC_PSSCR, 0); 6472 6473 spr_register_hv(env, SPR_PMSR, "PMSR", 6474 SPR_NOACCESS, SPR_NOACCESS, 6475 SPR_NOACCESS, SPR_NOACCESS, 6476 &spr_read_pmsr, SPR_NOACCESS, 6477 0); 6478 spr_register_hv(env, SPR_PMCR, "PMCR", 6479 SPR_NOACCESS, SPR_NOACCESS, 6480 SPR_NOACCESS, SPR_NOACCESS, 6481 &spr_read_generic, &spr_write_pmcr, 6482 PPC_BIT(63)); /* Version 1 (POWER9/10) */ 6483 6484 } 6485 6486 static void init_proc_POWER9(CPUPPCState *env) 6487 { 6488 register_power9_common_sprs(env); 6489 register_HEIR32_spr(env); 6490 /* POWER9 Specific registers */ 6491 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6492 spr_read_generic, spr_write_generic, 6493 KVM_REG_PPC_TIDR, 0); 6494 /* env variables */ 6495 env->dcache_line_size = 128; 6496 env->icache_line_size = 128; 6497 6498 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6499 6500 /* Allocate hardware IRQ controller */ 6501 init_excp_POWER9(env); 6502 ppcPOWER9_irq_init(env_archcpu(env)); 6503 } 6504 6505 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6506 { 6507 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6508 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6509 6510 if (!best) { 6511 if (base == CPU_POWERPC_POWER9_BASE) { 6512 return true; 6513 } 6514 } 6515 6516 if (base != pcc_base) { 6517 return false; 6518 } 6519 6520 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6521 /* Major DD version does not match */ 6522 return false; 6523 } 6524 6525 if ((pvr & 0x0f00) == 0x200) { 6526 if ((pvr & 0xf) < 2) { 6527 /* DD2.0, DD2.1 match power9_v2.0 */ 6528 if ((pcc->pvr & 0xf) == 0) { 6529 return true; 6530 } 6531 } else { 6532 /* DD2.2, DD2.3 match power9_v2.2 */ 6533 if ((pcc->pvr & 0xf) == 2) { 6534 return true; 6535 } 6536 } 6537 } 6538 6539 return false; 6540 } 6541 6542 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6543 { 6544 DeviceClass *dc = DEVICE_CLASS(oc); 6545 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6546 6547 dc->fw_name = "PowerPC,POWER9"; 6548 dc->desc = "POWER9"; 6549 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00; 6550 pcc->pvr_match = ppc_pvr_match_power9; 6551 pcc->pcr_mask = PPC_PCR_MASK_POWER9; 6552 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; 6553 pcc->init_proc = init_proc_POWER9; 6554 pcc->check_pow = check_pow_nocheck; 6555 pcc->check_attn = check_attn_hid0_power9; 6556 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9; 6557 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9; 6558 pcc->msr_mask = PPC_MSR_MASK_POWER9; 6559 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9; 6560 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6561 pcc->mmu_model = POWERPC_MMU_3_00; 6562 #if !defined(CONFIG_USER_ONLY) 6563 /* segment page size remain the same */ 6564 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6565 pcc->radix_page_info = &POWER9_radix_page_info; 6566 pcc->lrg_decr_bits = 56; 6567 pcc->n_host_threads = 4; 6568 #endif 6569 pcc->excp_model = POWERPC_EXCP_POWER9; 6570 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6571 pcc->bfd_mach = bfd_mach_ppc64; 6572 pcc->flags = POWERPC_FLAGS_POWER9; 6573 pcc->l1_dcache_size = 0x8000; 6574 pcc->l1_icache_size = 0x8000; 6575 } 6576 6577 #ifndef CONFIG_USER_ONLY 6578 /* 6579 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6580 * Encoded as array of int_32s in the form: 6581 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6582 * x -> AP encoding 6583 * y -> radix mode supported page size (encoded as a shift) 6584 */ 6585 static struct ppc_radix_page_info POWER10_radix_page_info = { 6586 .count = 4, 6587 .entries = { 6588 0x0000000c, /* 4K - enc: 0x0 */ 6589 0xa0000010, /* 64K - enc: 0x5 */ 6590 0x20000015, /* 2M - enc: 0x1 */ 6591 0x4000001e /* 1G - enc: 0x2 */ 6592 } 6593 }; 6594 #endif /* !CONFIG_USER_ONLY */ 6595 6596 #define POWER10_BHRB_ENTRIES_LOG2 5 6597 static void init_proc_POWER10(CPUPPCState *env) 6598 { 6599 register_power9_common_sprs(env); 6600 register_HEIR64_spr(env); 6601 register_book3s_310_dbg_sprs(env); 6602 register_power10_hash_sprs(env); 6603 register_power10_dexcr_sprs(env); 6604 register_power10_pmu_sup_sprs(env); 6605 register_power10_pmu_user_sprs(env); 6606 /* env variables */ 6607 env->dcache_line_size = 128; 6608 env->icache_line_size = 128; 6609 6610 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6611 6612 /* Allocate hardware IRQ controller */ 6613 init_excp_POWER10(env); 6614 ppcPOWER9_irq_init(env_archcpu(env)); 6615 } 6616 6617 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6618 { 6619 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6620 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6621 6622 if (!best) { 6623 if (base == CPU_POWERPC_POWER10_BASE) { 6624 return true; 6625 } 6626 } 6627 6628 if (base != pcc_base) { 6629 return false; 6630 } 6631 6632 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6633 /* Major DD version matches power10_v2.0 */ 6634 return true; 6635 } 6636 6637 return false; 6638 } 6639 6640 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6641 { 6642 DeviceClass *dc = DEVICE_CLASS(oc); 6643 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6644 6645 dc->fw_name = "PowerPC,POWER10"; 6646 dc->desc = "POWER10"; 6647 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10; 6648 pcc->pvr_match = ppc_pvr_match_power10; 6649 pcc->pcr_mask = PPC_PCR_MASK_POWER10; 6650 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; 6651 pcc->init_proc = init_proc_POWER10; 6652 pcc->check_pow = check_pow_nocheck; 6653 pcc->check_attn = check_attn_hid0_power9; 6654 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10; 6655 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10; 6656 pcc->msr_mask = PPC_MSR_MASK_POWER10; 6657 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10; 6658 6659 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6660 pcc->mmu_model = POWERPC_MMU_3_00; 6661 #if !defined(CONFIG_USER_ONLY) 6662 /* segment page size remain the same */ 6663 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6664 pcc->radix_page_info = &POWER10_radix_page_info; 6665 pcc->lrg_decr_bits = 56; 6666 #endif 6667 pcc->excp_model = POWERPC_EXCP_POWER10; 6668 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6669 pcc->bfd_mach = bfd_mach_ppc64; 6670 pcc->flags = POWERPC_FLAGS_POWER10; 6671 pcc->l1_dcache_size = 0x8000; 6672 pcc->l1_icache_size = 0x8000; 6673 } 6674 6675 static void init_proc_POWER11(CPUPPCState *env) 6676 { 6677 init_proc_POWER10(env); 6678 } 6679 6680 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6681 { 6682 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6683 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6684 6685 if (!best && (base == CPU_POWERPC_POWER11_BASE)) { 6686 return true; 6687 } 6688 6689 if (base != pcc_base) { 6690 return false; 6691 } 6692 6693 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6694 return true; 6695 } 6696 6697 return false; 6698 } 6699 6700 POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) 6701 { 6702 DeviceClass *dc = DEVICE_CLASS(oc); 6703 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6704 6705 dc->fw_name = "PowerPC,POWER11"; 6706 dc->desc = "POWER11"; 6707 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11; 6708 pcc->pvr_match = ppc_pvr_match_power11; 6709 pcc->pcr_mask = PPC_PCR_MASK_POWER11; 6710 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11; 6711 pcc->init_proc = init_proc_POWER11; 6712 pcc->check_pow = check_pow_nocheck; 6713 pcc->check_attn = check_attn_hid0_power9; 6714 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11; 6715 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11; 6716 pcc->msr_mask = PPC_MSR_MASK_POWER11; 6717 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11; 6718 6719 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6720 pcc->mmu_model = POWERPC_MMU_3_00; 6721 #if !defined(CONFIG_USER_ONLY) 6722 /* segment page size remain the same */ 6723 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6724 pcc->radix_page_info = &POWER10_radix_page_info; 6725 pcc->lrg_decr_bits = 56; 6726 #endif 6727 pcc->excp_model = POWERPC_EXCP_POWER11; 6728 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6729 pcc->bfd_mach = bfd_mach_ppc64; 6730 pcc->flags = POWERPC_FLAGS_POWER11; 6731 pcc->l1_dcache_size = 0x8000; 6732 pcc->l1_icache_size = 0x8000; 6733 } 6734 6735 #if !defined(CONFIG_USER_ONLY) 6736 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6737 { 6738 CPUPPCState *env = &cpu->env; 6739 6740 cpu->vhyp = vhyp; 6741 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6742 6743 /* 6744 * With a virtual hypervisor mode we never allow the CPU to go 6745 * hypervisor mode itself 6746 */ 6747 env->msr_mask &= ~MSR_HVB; 6748 } 6749 6750 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6751 { 6752 CPUPPCState *env = &cpu->env; 6753 6754 /* 6755 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6756 * between threads. powernv be in either mode, and it mostly affects 6757 * supervisor visible registers and instructions. 6758 */ 6759 if (env->flags & POWERPC_FLAG_SMT) { 6760 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6761 } 6762 } 6763 #endif /* !defined(CONFIG_USER_ONLY) */ 6764 6765 #endif /* defined(TARGET_PPC64) */ 6766 6767 /*****************************************************************************/ 6768 /* Generic CPU instantiation routine */ 6769 static void init_ppc_proc(PowerPCCPU *cpu) 6770 { 6771 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6772 CPUPPCState *env = &cpu->env; 6773 #if !defined(CONFIG_USER_ONLY) 6774 int i; 6775 6776 /* Set all exception vectors to an invalid address */ 6777 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6778 env->excp_vectors[i] = (target_ulong)(-1ULL); 6779 } 6780 env->ivor_mask = 0x00000000; 6781 env->ivpr_mask = 0x00000000; 6782 /* Default MMU definitions */ 6783 env->nb_BATs = 0; 6784 env->nb_tlb = 0; 6785 env->nb_ways = 0; 6786 env->tlb_type = TLB_NONE; 6787 #endif 6788 /* Register SPR common to all PowerPC implementations */ 6789 register_generic_sprs(cpu); 6790 6791 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6792 (*pcc->init_proc)(env); 6793 6794 /* MSR bits & flags consistency checks */ 6795 if (env->msr_mask & (1 << 25)) { 6796 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6797 case POWERPC_FLAG_SPE: 6798 case POWERPC_FLAG_VRE: 6799 break; 6800 default: 6801 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6802 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6803 exit(1); 6804 } 6805 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6806 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6807 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6808 exit(1); 6809 } 6810 if (env->msr_mask & (1 << 17)) { 6811 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6812 case POWERPC_FLAG_TGPR: 6813 case POWERPC_FLAG_CE: 6814 break; 6815 default: 6816 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6817 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6818 exit(1); 6819 } 6820 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6821 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6822 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6823 exit(1); 6824 } 6825 if (env->msr_mask & (1 << 10)) { 6826 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6827 POWERPC_FLAG_UBLE)) { 6828 case POWERPC_FLAG_SE: 6829 case POWERPC_FLAG_DWE: 6830 case POWERPC_FLAG_UBLE: 6831 break; 6832 default: 6833 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6834 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6835 "POWERPC_FLAG_UBLE\n"); 6836 exit(1); 6837 } 6838 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6839 POWERPC_FLAG_UBLE)) { 6840 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6841 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6842 "POWERPC_FLAG_UBLE\n"); 6843 exit(1); 6844 } 6845 if (env->msr_mask & (1 << 9)) { 6846 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6847 case POWERPC_FLAG_BE: 6848 case POWERPC_FLAG_DE: 6849 break; 6850 default: 6851 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6852 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6853 exit(1); 6854 } 6855 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6856 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6857 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6858 exit(1); 6859 } 6860 if (env->msr_mask & (1 << 2)) { 6861 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6862 case POWERPC_FLAG_PX: 6863 case POWERPC_FLAG_PMM: 6864 break; 6865 default: 6866 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6867 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6868 exit(1); 6869 } 6870 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6871 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6872 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6873 exit(1); 6874 } 6875 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6876 fprintf(stderr, "PowerPC flags inconsistency\n" 6877 "Should define the time-base and decrementer clock source\n"); 6878 exit(1); 6879 } 6880 /* Allocate TLBs buffer when needed */ 6881 #if !defined(CONFIG_USER_ONLY) 6882 if (env->nb_tlb) { 6883 switch (env->tlb_type) { 6884 case TLB_6XX: 6885 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6886 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6887 break; 6888 case TLB_EMB: 6889 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6890 break; 6891 case TLB_MAS: 6892 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6893 break; 6894 } 6895 /* Pre-compute some useful values */ 6896 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6897 } 6898 #endif 6899 if (env->check_pow == NULL) { 6900 warn_report("no power management check handler registered." 6901 " Attempt QEMU to crash very soon !"); 6902 } 6903 6904 if (env->check_attn == NULL) { 6905 warn_report("no attn check handler registered." 6906 " Attempt QEMU to crash very soon !"); 6907 } 6908 } 6909 6910 6911 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6912 { 6913 CPUState *cs = CPU(dev); 6914 PowerPCCPU *cpu = POWERPC_CPU(dev); 6915 CPUPPCState *env = &cpu->env; 6916 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6917 Error *local_err = NULL; 6918 6919 cpu_exec_realizefn(cs, &local_err); 6920 if (local_err != NULL) { 6921 error_propagate(errp, local_err); 6922 return; 6923 } 6924 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6925 cpu->vcpu_id = cs->cpu_index; 6926 } 6927 6928 if (tcg_enabled()) { 6929 if (ppc_fixup_cpu(cpu) != 0) { 6930 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6931 goto unrealize; 6932 } 6933 } 6934 6935 create_ppc_opcodes(cpu, &local_err); 6936 if (local_err != NULL) { 6937 error_propagate(errp, local_err); 6938 goto unrealize; 6939 } 6940 init_ppc_proc(cpu); 6941 6942 ppc_gdb_init(cs, pcc); 6943 qemu_init_vcpu(cs); 6944 6945 pcc->parent_realize(dev, errp); 6946 6947 if (!ppc_cpu_core_single_threaded(cs)) { 6948 env->flags |= POWERPC_FLAG_SMT; 6949 } 6950 6951 return; 6952 6953 unrealize: 6954 cpu_exec_unrealizefn(cs); 6955 } 6956 6957 static void ppc_cpu_unrealize(DeviceState *dev) 6958 { 6959 PowerPCCPU *cpu = POWERPC_CPU(dev); 6960 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6961 6962 pcc->parent_unrealize(dev); 6963 6964 cpu_remove_sync(CPU(cpu)); 6965 6966 destroy_ppc_opcodes(cpu); 6967 } 6968 6969 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6970 { 6971 ObjectClass *oc = (ObjectClass *)a; 6972 uint32_t pvr = *(uint32_t *)b; 6973 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6974 6975 /* -cpu host does a PVR lookup during construction */ 6976 if (unlikely(strcmp(object_class_get_name(oc), 6977 TYPE_HOST_POWERPC_CPU) == 0)) { 6978 return -1; 6979 } 6980 6981 return pcc->pvr == pvr ? 0 : -1; 6982 } 6983 6984 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 6985 { 6986 GSList *list, *item; 6987 PowerPCCPUClass *pcc = NULL; 6988 6989 list = object_class_get_list(TYPE_POWERPC_CPU, false); 6990 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 6991 if (item != NULL) { 6992 pcc = POWERPC_CPU_CLASS(item->data); 6993 } 6994 g_slist_free(list); 6995 6996 return pcc; 6997 } 6998 6999 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7000 { 7001 ObjectClass *oc = (ObjectClass *)a; 7002 uint32_t pvr = *(uint32_t *)b; 7003 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7004 7005 /* -cpu host does a PVR lookup during construction */ 7006 if (unlikely(strcmp(object_class_get_name(oc), 7007 TYPE_HOST_POWERPC_CPU) == 0)) { 7008 return -1; 7009 } 7010 7011 if (pcc->pvr_match(pcc, pvr, true)) { 7012 return 0; 7013 } 7014 7015 return -1; 7016 } 7017 7018 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7019 { 7020 GSList *list, *item; 7021 PowerPCCPUClass *pcc = NULL; 7022 7023 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7024 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7025 if (item != NULL) { 7026 pcc = POWERPC_CPU_CLASS(item->data); 7027 } 7028 g_slist_free(list); 7029 7030 return pcc; 7031 } 7032 7033 static const char *ppc_cpu_lookup_alias(const char *alias) 7034 { 7035 int ai; 7036 7037 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7038 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7039 return ppc_cpu_aliases[ai].model; 7040 } 7041 } 7042 7043 return NULL; 7044 } 7045 7046 ObjectClass *ppc_cpu_class_by_name(const char *name) 7047 { 7048 char *cpu_model, *typename; 7049 ObjectClass *oc; 7050 const char *p; 7051 unsigned long pvr; 7052 7053 /* 7054 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7055 * 0x prefix if present) 7056 */ 7057 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7058 int len = p - name; 7059 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7060 if ((len == 8) && (*p == '\0')) { 7061 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7062 } 7063 } 7064 7065 /* 7066 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7067 * do not have a "max" CPU with all possible emulated features enabled. 7068 * Return the default CPU type for the machine because that has greater 7069 * chance of being useful as the "max" CPU. 7070 */ 7071 #if !defined(CONFIG_USER_ONLY) 7072 if (strcmp(name, "max") == 0) { 7073 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7074 if (mc) { 7075 return object_class_by_name(mc->default_cpu_type); 7076 } 7077 } 7078 #endif 7079 7080 cpu_model = g_ascii_strdown(name, -1); 7081 p = ppc_cpu_lookup_alias(cpu_model); 7082 if (p) { 7083 g_free(cpu_model); 7084 cpu_model = g_strdup(p); 7085 } 7086 7087 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7088 oc = object_class_by_name(typename); 7089 g_free(typename); 7090 g_free(cpu_model); 7091 7092 return oc; 7093 } 7094 7095 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7096 { 7097 ObjectClass *oc = OBJECT_CLASS(pcc); 7098 7099 while (oc && !object_class_is_abstract(oc)) { 7100 oc = object_class_get_parent(oc); 7101 } 7102 assert(oc); 7103 7104 return POWERPC_CPU_CLASS(oc); 7105 } 7106 7107 /* Sort by PVR, ordering special case "host" last. */ 7108 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7109 { 7110 ObjectClass *oc_a = (ObjectClass *)a; 7111 ObjectClass *oc_b = (ObjectClass *)b; 7112 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7113 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7114 const char *name_a = object_class_get_name(oc_a); 7115 const char *name_b = object_class_get_name(oc_b); 7116 7117 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7118 return 1; 7119 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7120 return -1; 7121 } else { 7122 /* Avoid an integer overflow during subtraction */ 7123 if (pcc_a->pvr < pcc_b->pvr) { 7124 return -1; 7125 } else if (pcc_a->pvr > pcc_b->pvr) { 7126 return 1; 7127 } else { 7128 return 0; 7129 } 7130 } 7131 } 7132 7133 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7134 { 7135 ObjectClass *oc = data; 7136 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7137 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7138 const char *typename = object_class_get_name(oc); 7139 char *name; 7140 int i; 7141 7142 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7143 return; 7144 } 7145 7146 name = cpu_model_from_type(typename); 7147 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7148 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7149 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7150 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7151 7152 if (alias_oc != oc) { 7153 continue; 7154 } 7155 /* 7156 * If running with KVM, we might update the family alias later, so 7157 * avoid printing the wrong alias here and use "preferred" instead 7158 */ 7159 if (strcmp(alias->alias, family->desc) == 0) { 7160 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7161 alias->alias, family->desc); 7162 } else { 7163 qemu_printf(" %-16s (alias for %s)\n", 7164 alias->alias, name); 7165 } 7166 } 7167 g_free(name); 7168 } 7169 7170 void ppc_cpu_list(void) 7171 { 7172 GSList *list; 7173 7174 qemu_printf("Available CPUs:\n"); 7175 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7176 list = g_slist_sort(list, ppc_cpu_list_compare); 7177 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7178 g_slist_free(list); 7179 7180 #ifdef CONFIG_KVM 7181 qemu_printf("\n"); 7182 qemu_printf(" %s\n", "host"); 7183 #endif 7184 } 7185 7186 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7187 { 7188 PowerPCCPU *cpu = POWERPC_CPU(cs); 7189 7190 cpu->env.nip = value; 7191 } 7192 7193 static vaddr ppc_cpu_get_pc(CPUState *cs) 7194 { 7195 PowerPCCPU *cpu = POWERPC_CPU(cs); 7196 7197 return cpu->env.nip; 7198 } 7199 7200 #ifdef CONFIG_TCG 7201 static void ppc_restore_state_to_opc(CPUState *cs, 7202 const TranslationBlock *tb, 7203 const uint64_t *data) 7204 { 7205 PowerPCCPU *cpu = POWERPC_CPU(cs); 7206 7207 cpu->env.nip = data[0]; 7208 } 7209 #endif /* CONFIG_TCG */ 7210 7211 #ifndef CONFIG_USER_ONLY 7212 static bool ppc_cpu_has_work(CPUState *cs) 7213 { 7214 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7215 } 7216 #endif /* !CONFIG_USER_ONLY */ 7217 7218 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7219 { 7220 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7221 } 7222 7223 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7224 { 7225 CPUState *cs = CPU(obj); 7226 PowerPCCPU *cpu = POWERPC_CPU(cs); 7227 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7228 CPUPPCState *env = &cpu->env; 7229 target_ulong msr; 7230 int i; 7231 7232 if (pcc->parent_phases.hold) { 7233 pcc->parent_phases.hold(obj, type); 7234 } 7235 7236 msr = (target_ulong)0; 7237 msr |= (target_ulong)MSR_HVB; 7238 msr |= (target_ulong)1 << MSR_EP; 7239 #if defined(DO_SINGLE_STEP) && 0 7240 /* Single step trace mode */ 7241 msr |= (target_ulong)1 << MSR_SE; 7242 msr |= (target_ulong)1 << MSR_BE; 7243 #endif 7244 #if defined(CONFIG_USER_ONLY) 7245 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7246 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7247 msr |= (target_ulong)1 << MSR_FE1; 7248 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7249 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7250 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7251 msr |= (target_ulong)1 << MSR_PR; 7252 #if defined(TARGET_PPC64) 7253 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7254 #endif 7255 #if !TARGET_BIG_ENDIAN 7256 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7257 if (!((env->msr_mask >> MSR_LE) & 1)) { 7258 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7259 exit(1); 7260 } 7261 #endif 7262 #endif 7263 7264 #if defined(TARGET_PPC64) 7265 if (mmu_is_64bit(env->mmu_model)) { 7266 msr |= (1ULL << MSR_SF); 7267 } 7268 #endif 7269 7270 hreg_store_msr(env, msr, 1); 7271 7272 #if !defined(CONFIG_USER_ONLY) 7273 env->nip = env->hreset_vector | env->excp_prefix; 7274 7275 if (tcg_enabled()) { 7276 cpu_breakpoint_remove_all(cs, BP_CPU); 7277 cpu_watchpoint_remove_all(cs, BP_CPU); 7278 if (env->mmu_model != POWERPC_MMU_REAL) { 7279 ppc_tlb_invalidate_all(env); 7280 } 7281 pmu_mmcr01a_updated(env); 7282 } 7283 7284 /* clean any pending stop state */ 7285 env->resume_as_sreset = 0; 7286 #endif 7287 hreg_compute_hflags(env); 7288 env->reserve_addr = (target_ulong)-1ULL; 7289 /* Be sure no exception or interrupt is pending */ 7290 env->pending_interrupts = 0; 7291 cs->exception_index = POWERPC_EXCP_NONE; 7292 env->error_code = 0; 7293 ppc_irq_reset(cpu); 7294 7295 /* tininess for underflow is detected before rounding */ 7296 set_float_detect_tininess(float_tininess_before_rounding, 7297 &env->fp_status); 7298 /* Similarly for flush-to-zero */ 7299 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 7300 7301 /* 7302 * PowerPC propagation rules: 7303 * 1. A if it sNaN or qNaN 7304 * 2. B if it sNaN or qNaN 7305 * A signaling NaN is always silenced before returning it. 7306 */ 7307 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); 7308 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); 7309 /* 7310 * NaN propagation for fused multiply-add: 7311 * if fRA is a NaN return it; otherwise if fRB is a NaN return it; 7312 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 7313 * whereas QEMU labels the operands as (a * b) + c. 7314 */ 7315 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); 7316 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); 7317 /* 7318 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 7319 * to return an input NaN if we have one (ie c) rather than generating 7320 * a default NaN 7321 */ 7322 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 7323 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); 7324 7325 /* Default NaN: sign bit clear, set frac msb */ 7326 set_float_default_nan_pattern(0b01000000, &env->fp_status); 7327 set_float_default_nan_pattern(0b01000000, &env->vec_status); 7328 7329 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7330 ppc_spr_t *spr = &env->spr_cb[i]; 7331 7332 if (!spr->name) { 7333 continue; 7334 } 7335 env->spr[i] = spr->default_value; 7336 } 7337 7338 #if defined(TARGET_PPC64) 7339 bhrb_reset_state(env); 7340 #endif 7341 } 7342 7343 #ifndef CONFIG_USER_ONLY 7344 7345 static bool ppc_cpu_is_big_endian(CPUState *cs) 7346 { 7347 cpu_synchronize_state(cs); 7348 7349 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7350 } 7351 7352 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7353 uint64_t **irq_counts, unsigned int *nb_irqs) 7354 { 7355 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7356 7357 *irq_counts = env->excp_stats; 7358 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7359 return true; 7360 } 7361 7362 #ifdef CONFIG_TCG 7363 static void ppc_cpu_exec_enter(CPUState *cs) 7364 { 7365 PowerPCCPU *cpu = POWERPC_CPU(cs); 7366 7367 if (cpu->vhyp) { 7368 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7369 } 7370 } 7371 7372 static void ppc_cpu_exec_exit(CPUState *cs) 7373 { 7374 PowerPCCPU *cpu = POWERPC_CPU(cs); 7375 7376 if (cpu->vhyp) { 7377 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7378 } 7379 } 7380 #endif /* CONFIG_TCG */ 7381 7382 #endif /* !CONFIG_USER_ONLY */ 7383 7384 static void ppc_cpu_instance_init(Object *obj) 7385 { 7386 PowerPCCPU *cpu = POWERPC_CPU(obj); 7387 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7388 CPUPPCState *env = &cpu->env; 7389 7390 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7391 7392 env->msr_mask = pcc->msr_mask; 7393 env->mmu_model = pcc->mmu_model; 7394 env->excp_model = pcc->excp_model; 7395 env->bus_model = pcc->bus_model; 7396 env->insns_flags = pcc->insns_flags; 7397 env->insns_flags2 = pcc->insns_flags2; 7398 env->flags = pcc->flags; 7399 env->bfd_mach = pcc->bfd_mach; 7400 env->check_pow = pcc->check_pow; 7401 env->check_attn = pcc->check_attn; 7402 7403 /* 7404 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7405 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7406 * mode support will remain, thus enforcing that we cannot use 7407 * priv. instructions in guest in PAPR mode. For 970 we currently 7408 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7409 * 970. If we ever want to support 970 HV mode, we'll have to add 7410 * a processor attribute of some sort. 7411 */ 7412 #if !defined(CONFIG_USER_ONLY) 7413 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7414 #endif 7415 7416 ppc_hash64_init(cpu); 7417 } 7418 7419 static void ppc_cpu_instance_finalize(Object *obj) 7420 { 7421 PowerPCCPU *cpu = POWERPC_CPU(obj); 7422 7423 ppc_hash64_finalize(cpu); 7424 } 7425 7426 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7427 { 7428 return pcc->pvr == pvr; 7429 } 7430 7431 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7432 { 7433 CPUPPCState *env = cpu_env(cs); 7434 7435 if ((env->hflags >> MSR_LE) & 1) { 7436 info->endian = BFD_ENDIAN_LITTLE; 7437 } else { 7438 info->endian = BFD_ENDIAN_BIG; 7439 } 7440 info->mach = env->bfd_mach; 7441 if (!env->bfd_mach) { 7442 #ifdef TARGET_PPC64 7443 info->mach = bfd_mach_ppc64; 7444 #else 7445 info->mach = bfd_mach_ppc; 7446 #endif 7447 } 7448 7449 info->cap_arch = CS_ARCH_PPC; 7450 #ifdef TARGET_PPC64 7451 info->cap_mode = CS_MODE_64; 7452 #endif 7453 } 7454 7455 #ifndef CONFIG_USER_ONLY 7456 #include "hw/core/sysemu-cpu-ops.h" 7457 7458 static const struct SysemuCPUOps ppc_sysemu_ops = { 7459 .has_work = ppc_cpu_has_work, 7460 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7461 .write_elf32_note = ppc32_cpu_write_elf32_note, 7462 .write_elf64_note = ppc64_cpu_write_elf64_note, 7463 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7464 .legacy_vmsd = &vmstate_ppc_cpu, 7465 }; 7466 #endif 7467 7468 #ifdef CONFIG_TCG 7469 #include "accel/tcg/cpu-ops.h" 7470 7471 static const TCGCPUOps ppc_tcg_ops = { 7472 .initialize = ppc_translate_init, 7473 .translate_code = ppc_translate_code, 7474 .restore_state_to_opc = ppc_restore_state_to_opc, 7475 7476 #ifdef CONFIG_USER_ONLY 7477 .record_sigsegv = ppc_cpu_record_sigsegv, 7478 #else 7479 .tlb_fill = ppc_cpu_tlb_fill, 7480 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7481 .cpu_exec_halt = ppc_cpu_has_work, 7482 .do_interrupt = ppc_cpu_do_interrupt, 7483 .cpu_exec_enter = ppc_cpu_exec_enter, 7484 .cpu_exec_exit = ppc_cpu_exec_exit, 7485 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7486 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7487 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7488 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7489 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7490 #endif /* !CONFIG_USER_ONLY */ 7491 }; 7492 #endif /* CONFIG_TCG */ 7493 7494 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7495 { 7496 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7497 CPUClass *cc = CPU_CLASS(oc); 7498 DeviceClass *dc = DEVICE_CLASS(oc); 7499 ResettableClass *rc = RESETTABLE_CLASS(oc); 7500 7501 device_class_set_parent_realize(dc, ppc_cpu_realize, 7502 &pcc->parent_realize); 7503 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7504 &pcc->parent_unrealize); 7505 pcc->pvr_match = ppc_pvr_match_default; 7506 7507 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7508 &pcc->parent_phases); 7509 7510 cc->class_by_name = ppc_cpu_class_by_name; 7511 cc->mmu_index = ppc_cpu_mmu_index; 7512 cc->dump_state = ppc_cpu_dump_state; 7513 cc->set_pc = ppc_cpu_set_pc; 7514 cc->get_pc = ppc_cpu_get_pc; 7515 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7516 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7517 #ifndef CONFIG_USER_ONLY 7518 cc->sysemu_ops = &ppc_sysemu_ops; 7519 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7520 7521 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7522 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7523 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7524 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7525 #endif 7526 7527 cc->gdb_num_core_regs = 71; 7528 #ifdef USE_APPLE_GDB 7529 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7530 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7531 cc->gdb_num_core_regs = 71 + 32; 7532 #endif 7533 7534 cc->gdb_arch_name = ppc_gdb_arch_name; 7535 #if defined(TARGET_PPC64) 7536 cc->gdb_core_xml_file = "power64-core.xml"; 7537 #else 7538 cc->gdb_core_xml_file = "power-core.xml"; 7539 #endif 7540 cc->disas_set_info = ppc_disas_set_info; 7541 7542 dc->fw_name = "PowerPC,UNKNOWN"; 7543 7544 #ifdef CONFIG_TCG 7545 cc->tcg_ops = &ppc_tcg_ops; 7546 #endif /* CONFIG_TCG */ 7547 } 7548 7549 static const TypeInfo ppc_cpu_type_info = { 7550 .name = TYPE_POWERPC_CPU, 7551 .parent = TYPE_CPU, 7552 .instance_size = sizeof(PowerPCCPU), 7553 .instance_align = __alignof__(PowerPCCPU), 7554 .instance_init = ppc_cpu_instance_init, 7555 .instance_finalize = ppc_cpu_instance_finalize, 7556 .abstract = true, 7557 .class_size = sizeof(PowerPCCPUClass), 7558 .class_init = ppc_cpu_class_init, 7559 #ifndef CONFIG_USER_ONLY 7560 .interfaces = (InterfaceInfo[]) { 7561 { TYPE_INTERRUPT_STATS_PROVIDER }, 7562 { } 7563 }, 7564 #endif 7565 }; 7566 7567 #ifndef CONFIG_USER_ONLY 7568 static const TypeInfo ppc_vhyp_type_info = { 7569 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7570 .parent = TYPE_INTERFACE, 7571 .class_size = sizeof(PPCVirtualHypervisorClass), 7572 }; 7573 #endif 7574 7575 static void ppc_cpu_register_types(void) 7576 { 7577 type_register_static(&ppc_cpu_type_info); 7578 #ifndef CONFIG_USER_ONLY 7579 type_register_static(&ppc_vhyp_type_info); 7580 #endif 7581 } 7582 7583 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7584 { 7585 #define RGPL 4 7586 #define RFPL 4 7587 7588 CPUPPCState *env = cpu_env(cs); 7589 int i; 7590 7591 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7592 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7593 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7594 cs->cpu_index); 7595 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7596 "%08x iidx %d didx %d\n", 7597 env->msr, env->spr[SPR_HID0], env->hflags, 7598 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7599 #if !defined(CONFIG_USER_ONLY) 7600 if (env->tb_env) { 7601 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7602 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7603 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7604 } 7605 #else 7606 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7607 cpu_ppc_load_tbl(env)); 7608 #endif 7609 for (i = 0; i < 32; i++) { 7610 if ((i & (RGPL - 1)) == 0) { 7611 qemu_fprintf(f, "GPR%02d", i); 7612 } 7613 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7614 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7615 qemu_fprintf(f, "\n"); 7616 } 7617 } 7618 qemu_fprintf(f, "CR "); 7619 for (i = 0; i < 8; i++) 7620 qemu_fprintf(f, "%01x", env->crf[i]); 7621 qemu_fprintf(f, " ["); 7622 for (i = 0; i < 8; i++) { 7623 char a = '-'; 7624 if (env->crf[i] & 0x08) { 7625 a = 'L'; 7626 } else if (env->crf[i] & 0x04) { 7627 a = 'G'; 7628 } else if (env->crf[i] & 0x02) { 7629 a = 'E'; 7630 } 7631 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7632 } 7633 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7634 (int)env->reserve_length, env->reserve_addr); 7635 7636 if (flags & CPU_DUMP_FPU) { 7637 for (i = 0; i < 32; i++) { 7638 if ((i & (RFPL - 1)) == 0) { 7639 qemu_fprintf(f, "FPR%02d", i); 7640 } 7641 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7642 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7643 qemu_fprintf(f, "\n"); 7644 } 7645 } 7646 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7647 } 7648 7649 #if !defined(CONFIG_USER_ONLY) 7650 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7651 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7652 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7653 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7654 7655 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7656 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7657 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7658 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7659 7660 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7661 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7662 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7663 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7664 7665 switch (env->excp_model) { 7666 #if defined(TARGET_PPC64) 7667 case POWERPC_EXCP_POWER7: 7668 case POWERPC_EXCP_POWER8: 7669 case POWERPC_EXCP_POWER9: 7670 case POWERPC_EXCP_POWER10: 7671 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7672 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7673 break; 7674 #endif 7675 case POWERPC_EXCP_BOOKE: 7676 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7677 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7678 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7679 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7680 7681 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7682 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7683 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7684 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7685 7686 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7687 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7688 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7689 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7690 7691 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7692 " EPR " TARGET_FMT_lx "\n", 7693 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7694 env->spr[SPR_BOOKE_EPR]); 7695 7696 /* FSL-specific */ 7697 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7698 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7699 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7700 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7701 7702 /* 7703 * IVORs are left out as they are large and do not change often -- 7704 * they can be read with "p $ivor0", "p $ivor1", etc. 7705 */ 7706 break; 7707 case POWERPC_EXCP_40x: 7708 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7709 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7710 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7711 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7712 7713 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7714 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7715 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7716 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7717 break; 7718 default: 7719 break; 7720 } 7721 7722 #if defined(TARGET_PPC64) 7723 if (env->flags & POWERPC_FLAG_CFAR) { 7724 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7725 } 7726 #endif 7727 7728 if (env->spr_cb[SPR_LPCR].name) { 7729 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7730 } 7731 7732 switch (env->mmu_model) { 7733 case POWERPC_MMU_32B: 7734 case POWERPC_MMU_SOFT_6xx: 7735 #if defined(TARGET_PPC64) 7736 case POWERPC_MMU_64B: 7737 case POWERPC_MMU_2_03: 7738 case POWERPC_MMU_2_06: 7739 case POWERPC_MMU_2_07: 7740 case POWERPC_MMU_3_00: 7741 #endif 7742 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7743 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7744 } 7745 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7746 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7747 } 7748 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7749 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7750 break; 7751 case POWERPC_MMU_BOOKE206: 7752 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7753 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7754 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7755 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7756 7757 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7758 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7759 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7760 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7761 7762 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7763 " TLB1CFG " TARGET_FMT_lx "\n", 7764 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7765 env->spr[SPR_BOOKE_TLB1CFG]); 7766 break; 7767 default: 7768 break; 7769 } 7770 #endif 7771 7772 #undef RGPL 7773 #undef RFPL 7774 } 7775 type_init(ppc_cpu_register_types) 7776