1 2 /* 3 * PowerPC CPU initialization for qemu. 4 * 5 * Copyright (c) 2003-2007 Jocelyn Mayer 6 * Copyright 2011 Freescale Semiconductor, Inc. 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 #include "gdbstub/helpers.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 44 #include "helper_regs.h" 45 #include "internal.h" 46 #include "spr_common.h" 47 #include "power8-pmu.h" 48 49 #ifndef CONFIG_USER_ONLY 50 #include "hw/boards.h" 51 #include "hw/intc/intc.h" 52 #include "kvm_ppc.h" 53 #endif 54 55 /* #define PPC_DEBUG_SPR */ 56 /* #define USE_APPLE_GDB */ 57 58 static inline void vscr_init(CPUPPCState *env, uint32_t val) 59 { 60 /* Altivec always uses round-to-nearest */ 61 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 62 ppc_store_vscr(env, val); 63 } 64 65 static void register_745_sprs(CPUPPCState *env) 66 { 67 /* SGPRs */ 68 spr_register(env, SPR_SPRG4, "SPRG4", 69 SPR_NOACCESS, SPR_NOACCESS, 70 &spr_read_generic, &spr_write_generic, 71 0x00000000); 72 spr_register(env, SPR_SPRG5, "SPRG5", 73 SPR_NOACCESS, SPR_NOACCESS, 74 &spr_read_generic, &spr_write_generic, 75 0x00000000); 76 spr_register(env, SPR_SPRG6, "SPRG6", 77 SPR_NOACCESS, SPR_NOACCESS, 78 &spr_read_generic, &spr_write_generic, 79 0x00000000); 80 spr_register(env, SPR_SPRG7, "SPRG7", 81 SPR_NOACCESS, SPR_NOACCESS, 82 &spr_read_generic, &spr_write_generic, 83 0x00000000); 84 85 /* Hardware implementation registers */ 86 spr_register(env, SPR_HID0, "HID0", 87 SPR_NOACCESS, SPR_NOACCESS, 88 &spr_read_generic, &spr_write_generic, 89 0x00000000); 90 91 spr_register(env, SPR_HID1, "HID1", 92 SPR_NOACCESS, SPR_NOACCESS, 93 &spr_read_generic, &spr_write_generic, 94 0x00000000); 95 96 spr_register(env, SPR_HID2, "HID2", 97 SPR_NOACCESS, SPR_NOACCESS, 98 &spr_read_generic, &spr_write_generic, 99 0x00000000); 100 } 101 102 static void register_755_sprs(CPUPPCState *env) 103 { 104 /* L2 cache control */ 105 spr_register(env, SPR_L2CR, "L2CR", 106 SPR_NOACCESS, SPR_NOACCESS, 107 &spr_read_generic, spr_access_nop, 108 0x00000000); 109 110 spr_register(env, SPR_L2PMCR, "L2PMCR", 111 SPR_NOACCESS, SPR_NOACCESS, 112 &spr_read_generic, &spr_write_generic, 113 0x00000000); 114 } 115 116 /* SPR common to all 7xx PowerPC implementations */ 117 static void register_7xx_sprs(CPUPPCState *env) 118 { 119 /* Breakpoints */ 120 spr_register_kvm(env, SPR_DABR, "DABR", 121 SPR_NOACCESS, SPR_NOACCESS, 122 &spr_read_generic, &spr_write_generic, 123 KVM_REG_PPC_DABR, 0x00000000); 124 125 spr_register(env, SPR_IABR, "IABR", 126 SPR_NOACCESS, SPR_NOACCESS, 127 &spr_read_generic, &spr_write_generic, 128 0x00000000); 129 /* Cache management */ 130 spr_register(env, SPR_ICTC, "ICTC", 131 SPR_NOACCESS, SPR_NOACCESS, 132 &spr_read_generic, &spr_write_generic, 133 0x00000000); 134 /* Performance monitors */ 135 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 136 SPR_NOACCESS, SPR_NOACCESS, 137 &spr_read_generic, &spr_write_generic, 138 0x00000000); 139 140 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 141 SPR_NOACCESS, SPR_NOACCESS, 142 &spr_read_generic, &spr_write_generic, 143 0x00000000); 144 145 spr_register(env, SPR_7XX_PMC1, "PMC1", 146 SPR_NOACCESS, SPR_NOACCESS, 147 &spr_read_generic, &spr_write_generic, 148 0x00000000); 149 150 spr_register(env, SPR_7XX_PMC2, "PMC2", 151 SPR_NOACCESS, SPR_NOACCESS, 152 &spr_read_generic, &spr_write_generic, 153 0x00000000); 154 155 spr_register(env, SPR_7XX_PMC3, "PMC3", 156 SPR_NOACCESS, SPR_NOACCESS, 157 &spr_read_generic, &spr_write_generic, 158 0x00000000); 159 160 spr_register(env, SPR_7XX_PMC4, "PMC4", 161 SPR_NOACCESS, SPR_NOACCESS, 162 &spr_read_generic, &spr_write_generic, 163 0x00000000); 164 165 spr_register(env, SPR_7XX_SIAR, "SIAR", 166 SPR_NOACCESS, SPR_NOACCESS, 167 &spr_read_generic, SPR_NOACCESS, 168 0x00000000); 169 170 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 171 &spr_read_ureg, SPR_NOACCESS, 172 &spr_read_ureg, SPR_NOACCESS, 173 0x00000000); 174 175 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 176 &spr_read_ureg, SPR_NOACCESS, 177 &spr_read_ureg, SPR_NOACCESS, 178 0x00000000); 179 180 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 181 &spr_read_ureg, SPR_NOACCESS, 182 &spr_read_ureg, SPR_NOACCESS, 183 0x00000000); 184 185 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 186 &spr_read_ureg, SPR_NOACCESS, 187 &spr_read_ureg, SPR_NOACCESS, 188 0x00000000); 189 190 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 191 &spr_read_ureg, SPR_NOACCESS, 192 &spr_read_ureg, SPR_NOACCESS, 193 0x00000000); 194 195 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 196 &spr_read_ureg, SPR_NOACCESS, 197 &spr_read_ureg, SPR_NOACCESS, 198 0x00000000); 199 200 spr_register(env, SPR_7XX_USIAR, "USIAR", 201 &spr_read_ureg, SPR_NOACCESS, 202 &spr_read_ureg, SPR_NOACCESS, 203 0x00000000); 204 /* External access control */ 205 spr_register(env, SPR_EAR, "EAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 0x00000000); 209 210 /* Hardware implementation registers */ 211 spr_register(env, SPR_HID0, "HID0", 212 SPR_NOACCESS, SPR_NOACCESS, 213 &spr_read_generic, &spr_write_generic, 214 0x00000000); 215 216 spr_register(env, SPR_HID1, "HID1", 217 SPR_NOACCESS, SPR_NOACCESS, 218 &spr_read_generic, &spr_write_generic, 219 0x00000000); 220 } 221 222 #ifdef TARGET_PPC64 223 static void register_amr_sprs(CPUPPCState *env) 224 { 225 #ifndef CONFIG_USER_ONLY 226 /* 227 * Virtual Page Class Key protection 228 * 229 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 230 * userspace accessible, 29 is privileged. So we only need to set 231 * the kvm ONE_REG id on one of them, we use 29 232 */ 233 spr_register(env, SPR_UAMR, "UAMR", 234 &spr_read_generic, &spr_write_amr, 235 &spr_read_generic, &spr_write_amr, 236 0); 237 spr_register_kvm_hv(env, SPR_AMR, "AMR", 238 SPR_NOACCESS, SPR_NOACCESS, 239 &spr_read_generic, &spr_write_amr, 240 &spr_read_generic, &spr_write_generic, 241 KVM_REG_PPC_AMR, 0); 242 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 243 SPR_NOACCESS, SPR_NOACCESS, 244 &spr_read_generic, &spr_write_uamor, 245 &spr_read_generic, &spr_write_generic, 246 KVM_REG_PPC_UAMOR, 0); 247 spr_register_hv(env, SPR_AMOR, "AMOR", 248 SPR_NOACCESS, SPR_NOACCESS, 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_core_lpar_write_generic, 251 0); 252 #endif /* !CONFIG_USER_ONLY */ 253 } 254 255 static void register_iamr_sprs(CPUPPCState *env) 256 { 257 #ifndef CONFIG_USER_ONLY 258 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 259 SPR_NOACCESS, SPR_NOACCESS, 260 &spr_read_generic, &spr_write_iamr, 261 &spr_read_generic, &spr_write_generic, 262 KVM_REG_PPC_IAMR, 0); 263 #endif /* !CONFIG_USER_ONLY */ 264 } 265 #endif /* TARGET_PPC64 */ 266 267 /* SPR specific to PowerPC 604 implementation */ 268 static void register_604_sprs(CPUPPCState *env) 269 { 270 /* Processor identification */ 271 spr_register(env, SPR_PIR, "PIR", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_generic, &spr_write_pir, 274 0x00000000); 275 /* Breakpoints */ 276 spr_register(env, SPR_IABR, "IABR", 277 SPR_NOACCESS, SPR_NOACCESS, 278 &spr_read_generic, &spr_write_generic, 279 0x00000000); 280 281 spr_register_kvm(env, SPR_DABR, "DABR", 282 SPR_NOACCESS, SPR_NOACCESS, 283 &spr_read_generic, &spr_write_generic, 284 KVM_REG_PPC_DABR, 0x00000000); 285 /* Performance counters */ 286 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 287 SPR_NOACCESS, SPR_NOACCESS, 288 &spr_read_generic, &spr_write_generic, 289 0x00000000); 290 291 spr_register(env, SPR_7XX_PMC1, "PMC1", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_generic, &spr_write_generic, 294 0x00000000); 295 296 spr_register(env, SPR_7XX_PMC2, "PMC2", 297 SPR_NOACCESS, SPR_NOACCESS, 298 &spr_read_generic, &spr_write_generic, 299 0x00000000); 300 301 spr_register(env, SPR_7XX_SIAR, "SIAR", 302 SPR_NOACCESS, SPR_NOACCESS, 303 &spr_read_generic, SPR_NOACCESS, 304 0x00000000); 305 306 spr_register(env, SPR_SDA, "SDA", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_generic, SPR_NOACCESS, 309 0x00000000); 310 /* External access control */ 311 spr_register(env, SPR_EAR, "EAR", 312 SPR_NOACCESS, SPR_NOACCESS, 313 &spr_read_generic, &spr_write_generic, 314 0x00000000); 315 316 /* Hardware implementation registers */ 317 spr_register(env, SPR_HID0, "HID0", 318 SPR_NOACCESS, SPR_NOACCESS, 319 &spr_read_generic, &spr_write_generic, 320 0x00000000); 321 } 322 323 static void register_604e_sprs(CPUPPCState *env) 324 { 325 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 326 SPR_NOACCESS, SPR_NOACCESS, 327 &spr_read_generic, &spr_write_generic, 328 0x00000000); 329 330 spr_register(env, SPR_7XX_PMC3, "PMC3", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_generic, &spr_write_generic, 333 0x00000000); 334 335 spr_register(env, SPR_7XX_PMC4, "PMC4", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_generic, &spr_write_generic, 338 0x00000000); 339 /* Hardware implementation registers */ 340 spr_register(env, SPR_HID1, "HID1", 341 SPR_NOACCESS, SPR_NOACCESS, 342 &spr_read_generic, &spr_write_generic, 343 0x00000000); 344 } 345 346 /* SPR specific to PowerPC 603 implementation */ 347 static void register_603_sprs(CPUPPCState *env) 348 { 349 /* External access control */ 350 spr_register(env, SPR_EAR, "EAR", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_generic, &spr_write_generic, 353 0x00000000); 354 /* Breakpoints */ 355 spr_register(env, SPR_IABR, "IABR", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_generic, &spr_write_generic, 358 0x00000000); 359 360 spr_register(env, SPR_HID0, "HID0", 361 SPR_NOACCESS, SPR_NOACCESS, 362 &spr_read_generic, &spr_write_generic, 363 0x00000000); 364 365 spr_register(env, SPR_HID1, "HID1", 366 SPR_NOACCESS, SPR_NOACCESS, 367 &spr_read_generic, &spr_write_generic, 368 0x00000000); 369 } 370 371 static void register_e300_sprs(CPUPPCState *env) 372 { 373 /* hardware implementation registers */ 374 spr_register(env, SPR_HID2, "HID2", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_generic, &spr_write_generic, 377 0x00000000); 378 /* Breakpoints */ 379 spr_register(env, SPR_DABR, "DABR", 380 SPR_NOACCESS, SPR_NOACCESS, 381 &spr_read_generic, &spr_write_generic, 382 0x00000000); 383 384 spr_register(env, SPR_DABR2, "DABR2", 385 SPR_NOACCESS, SPR_NOACCESS, 386 &spr_read_generic, &spr_write_generic, 387 0x00000000); 388 389 spr_register(env, SPR_IABR2, "IABR2", 390 SPR_NOACCESS, SPR_NOACCESS, 391 &spr_read_generic, &spr_write_generic, 392 0x00000000); 393 394 spr_register(env, SPR_IBCR, "IBCR", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, &spr_write_generic, 397 0x00000000); 398 399 spr_register(env, SPR_DBCR, "DBCR", 400 SPR_NOACCESS, SPR_NOACCESS, 401 &spr_read_generic, &spr_write_generic, 402 0x00000000); 403 } 404 405 /* SPR specific to PowerPC G2 implementation */ 406 static void register_G2_sprs(CPUPPCState *env) 407 { 408 /* Memory base address */ 409 /* MBAR */ 410 spr_register(env, SPR_MBAR, "MBAR", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_generic, &spr_write_generic, 413 0x00000000); 414 /* Exception processing */ 415 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 416 SPR_NOACCESS, SPR_NOACCESS, 417 &spr_read_generic, &spr_write_generic, 418 0x00000000); 419 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 420 SPR_NOACCESS, SPR_NOACCESS, 421 &spr_read_generic, &spr_write_generic, 422 0x00000000); 423 /* Breakpoints */ 424 spr_register(env, SPR_DABR, "DABR", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, &spr_write_generic, 427 0x00000000); 428 429 spr_register(env, SPR_DABR2, "DABR2", 430 SPR_NOACCESS, SPR_NOACCESS, 431 &spr_read_generic, &spr_write_generic, 432 0x00000000); 433 434 spr_register(env, SPR_IABR, "IABR", 435 SPR_NOACCESS, SPR_NOACCESS, 436 &spr_read_generic, &spr_write_generic, 437 0x00000000); 438 439 spr_register(env, SPR_IABR2, "IABR2", 440 SPR_NOACCESS, SPR_NOACCESS, 441 &spr_read_generic, &spr_write_generic, 442 0x00000000); 443 444 spr_register(env, SPR_IBCR, "IBCR", 445 SPR_NOACCESS, SPR_NOACCESS, 446 &spr_read_generic, &spr_write_generic, 447 0x00000000); 448 449 spr_register(env, SPR_DBCR, "DBCR", 450 SPR_NOACCESS, SPR_NOACCESS, 451 &spr_read_generic, &spr_write_generic, 452 0x00000000); 453 454 /* External access control */ 455 spr_register(env, SPR_EAR, "EAR", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 /* Hardware implementation register */ 460 spr_register(env, SPR_HID0, "HID0", 461 SPR_NOACCESS, SPR_NOACCESS, 462 &spr_read_generic, &spr_write_generic, 463 0x00000000); 464 465 spr_register(env, SPR_HID1, "HID1", 466 SPR_NOACCESS, SPR_NOACCESS, 467 &spr_read_generic, &spr_write_generic, 468 0x00000000); 469 470 spr_register(env, SPR_HID2, "HID2", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 0x00000000); 474 475 /* SGPRs */ 476 spr_register(env, SPR_SPRG4, "SPRG4", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG5, "SPRG5", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG6, "SPRG6", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 spr_register(env, SPR_SPRG7, "SPRG7", 489 SPR_NOACCESS, SPR_NOACCESS, 490 &spr_read_generic, &spr_write_generic, 491 0x00000000); 492 } 493 494 static void register_74xx_sprs(CPUPPCState *env) 495 { 496 /* Breakpoints */ 497 spr_register_kvm(env, SPR_DABR, "DABR", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 KVM_REG_PPC_DABR, 0x00000000); 501 502 spr_register(env, SPR_IABR, "IABR", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* Cache management */ 507 spr_register(env, SPR_ICTC, "ICTC", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* Performance monitors */ 512 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 517 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, &spr_write_generic, 520 0x00000000); 521 522 spr_register(env, SPR_7XX_PMC1, "PMC1", 523 SPR_NOACCESS, SPR_NOACCESS, 524 &spr_read_generic, &spr_write_generic, 525 0x00000000); 526 527 spr_register(env, SPR_7XX_PMC2, "PMC2", 528 SPR_NOACCESS, SPR_NOACCESS, 529 &spr_read_generic, &spr_write_generic, 530 0x00000000); 531 532 spr_register(env, SPR_7XX_PMC3, "PMC3", 533 SPR_NOACCESS, SPR_NOACCESS, 534 &spr_read_generic, &spr_write_generic, 535 0x00000000); 536 537 spr_register(env, SPR_7XX_PMC4, "PMC4", 538 SPR_NOACCESS, SPR_NOACCESS, 539 &spr_read_generic, &spr_write_generic, 540 0x00000000); 541 542 spr_register(env, SPR_7XX_SIAR, "SIAR", 543 SPR_NOACCESS, SPR_NOACCESS, 544 &spr_read_generic, SPR_NOACCESS, 545 0x00000000); 546 547 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 552 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 557 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 558 &spr_read_ureg, SPR_NOACCESS, 559 &spr_read_ureg, SPR_NOACCESS, 560 0x00000000); 561 562 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 563 &spr_read_ureg, SPR_NOACCESS, 564 &spr_read_ureg, SPR_NOACCESS, 565 0x00000000); 566 567 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 568 &spr_read_ureg, SPR_NOACCESS, 569 &spr_read_ureg, SPR_NOACCESS, 570 0x00000000); 571 572 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 573 &spr_read_ureg, SPR_NOACCESS, 574 &spr_read_ureg, SPR_NOACCESS, 575 0x00000000); 576 577 spr_register(env, SPR_7XX_USIAR, "USIAR", 578 &spr_read_ureg, SPR_NOACCESS, 579 &spr_read_ureg, SPR_NOACCESS, 580 0x00000000); 581 /* External access control */ 582 spr_register(env, SPR_EAR, "EAR", 583 SPR_NOACCESS, SPR_NOACCESS, 584 &spr_read_generic, &spr_write_generic, 585 0x00000000); 586 587 /* Processor identification */ 588 spr_register(env, SPR_PIR, "PIR", 589 SPR_NOACCESS, SPR_NOACCESS, 590 &spr_read_generic, &spr_write_pir, 591 0x00000000); 592 593 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 594 SPR_NOACCESS, SPR_NOACCESS, 595 &spr_read_generic, &spr_write_generic, 596 0x00000000); 597 598 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 599 &spr_read_ureg, SPR_NOACCESS, 600 &spr_read_ureg, SPR_NOACCESS, 601 0x00000000); 602 603 spr_register(env, SPR_BAMR, "BAMR", 604 SPR_NOACCESS, SPR_NOACCESS, 605 &spr_read_generic, &spr_write_generic, 606 0x00000000); 607 608 spr_register(env, SPR_MSSCR0, "MSSCR0", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_generic, &spr_write_generic, 611 0x00000000); 612 /* Hardware implementation registers */ 613 spr_register(env, SPR_HID0, "HID0", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_generic, &spr_write_generic, 616 0x00000000); 617 618 spr_register(env, SPR_HID1, "HID1", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_generic, &spr_write_generic, 621 0x00000000); 622 /* Altivec */ 623 spr_register(env, SPR_VRSAVE, "VRSAVE", 624 &spr_read_generic, &spr_write_generic, 625 &spr_read_generic, &spr_write_generic, 626 0x00000000); 627 628 spr_register(env, SPR_L2CR, "L2CR", 629 SPR_NOACCESS, SPR_NOACCESS, 630 &spr_read_generic, spr_access_nop, 631 0x00000000); 632 } 633 634 static void register_l3_ctrl(CPUPPCState *env) 635 { 636 /* L3CR */ 637 spr_register(env, SPR_L3CR, "L3CR", 638 SPR_NOACCESS, SPR_NOACCESS, 639 &spr_read_generic, &spr_write_generic, 640 0x00000000); 641 /* L3ITCR0 */ 642 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 643 SPR_NOACCESS, SPR_NOACCESS, 644 &spr_read_generic, &spr_write_generic, 645 0x00000000); 646 /* L3PM */ 647 spr_register(env, SPR_L3PM, "L3PM", 648 SPR_NOACCESS, SPR_NOACCESS, 649 &spr_read_generic, &spr_write_generic, 650 0x00000000); 651 } 652 653 /* PowerPC BookE SPR */ 654 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 655 { 656 const char *ivor_names[64] = { 657 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 658 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 659 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 660 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 661 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 662 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 663 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 664 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 665 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 666 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 667 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 668 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 669 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 670 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 671 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 672 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 673 }; 674 #define SPR_BOOKE_IVORxx (-1) 675 int ivor_sprn[64] = { 676 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 677 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 678 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 679 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 685 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 686 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 692 }; 693 int i; 694 695 /* Interrupt processing */ 696 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 697 SPR_NOACCESS, SPR_NOACCESS, 698 &spr_read_generic, &spr_write_generic, 699 0x00000000); 700 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 /* Debug */ 705 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, &spr_write_generic, 713 0x00000000); 714 715 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 720 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 721 SPR_NOACCESS, SPR_NOACCESS, 722 &spr_read_generic, &spr_write_generic, 723 0x00000000); 724 725 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_40x_dbcr0, 728 0x00000000); 729 730 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 735 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 740 SPR_NOACCESS, SPR_NOACCESS, 741 &spr_read_generic, &spr_write_generic, 742 0x00000000); 743 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_generic, 746 0x00000000); 747 748 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_clear, 751 0x00000000); 752 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 753 SPR_NOACCESS, SPR_NOACCESS, 754 &spr_read_generic, &spr_write_generic, 755 0x00000000); 756 spr_register(env, SPR_BOOKE_ESR, "ESR", 757 SPR_NOACCESS, SPR_NOACCESS, 758 &spr_read_generic, &spr_write_generic, 759 0x00000000); 760 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 761 SPR_NOACCESS, SPR_NOACCESS, 762 &spr_read_generic, &spr_write_excp_prefix, 763 0x00000000); 764 /* Exception vectors */ 765 for (i = 0; i < 64; i++) { 766 if (ivor_mask & (1ULL << i)) { 767 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 768 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 769 exit(1); 770 } 771 spr_register(env, ivor_sprn[i], ivor_names[i], 772 SPR_NOACCESS, SPR_NOACCESS, 773 &spr_read_generic, &spr_write_excp_vector, 774 0x00000000); 775 } 776 } 777 spr_register(env, SPR_BOOKE_PID, "PID", 778 SPR_NOACCESS, SPR_NOACCESS, 779 &spr_read_generic, &spr_write_booke_pid, 780 0x00000000); 781 spr_register(env, SPR_BOOKE_TCR, "TCR", 782 SPR_NOACCESS, SPR_NOACCESS, 783 &spr_read_generic, &spr_write_booke_tcr, 784 0x00000000); 785 spr_register(env, SPR_BOOKE_TSR, "TSR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_booke_tsr, 788 0x00000000); 789 /* Timer */ 790 spr_register(env, SPR_DECR, "DECR", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_decr, &spr_write_decr, 793 0x00000000); 794 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 SPR_NOACCESS, &spr_write_generic32, 797 0x00000000); 798 /* SPRGs */ 799 spr_register(env, SPR_USPRG0, "USPRG0", 800 &spr_read_generic, &spr_write_generic, 801 &spr_read_generic, &spr_write_generic, 802 0x00000000); 803 spr_register(env, SPR_SPRG4, "SPRG4", 804 SPR_NOACCESS, SPR_NOACCESS, 805 &spr_read_generic, &spr_write_generic, 806 0x00000000); 807 spr_register(env, SPR_SPRG5, "SPRG5", 808 SPR_NOACCESS, SPR_NOACCESS, 809 &spr_read_generic, &spr_write_generic, 810 0x00000000); 811 spr_register(env, SPR_SPRG6, "SPRG6", 812 SPR_NOACCESS, SPR_NOACCESS, 813 &spr_read_generic, &spr_write_generic, 814 0x00000000); 815 spr_register(env, SPR_SPRG7, "SPRG7", 816 SPR_NOACCESS, SPR_NOACCESS, 817 &spr_read_generic, &spr_write_generic, 818 0x00000000); 819 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 820 SPR_NOACCESS, SPR_NOACCESS, 821 &spr_read_generic, &spr_write_generic, 822 0x00000000); 823 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 824 SPR_NOACCESS, SPR_NOACCESS, 825 &spr_read_generic, &spr_write_generic, 826 0x00000000); 827 } 828 829 #if !defined(CONFIG_USER_ONLY) 830 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 831 uint32_t maxsize, uint32_t flags, 832 uint32_t nentries) 833 { 834 return (assoc << TLBnCFG_ASSOC_SHIFT) | 835 (minsize << TLBnCFG_MINSIZE_SHIFT) | 836 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 837 flags | nentries; 838 } 839 #endif /* !CONFIG_USER_ONLY */ 840 841 /* BookE 2.06 storage control registers */ 842 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 843 uint32_t *tlbncfg, uint32_t mmucfg) 844 { 845 #if !defined(CONFIG_USER_ONLY) 846 const char *mas_names[8] = { 847 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 848 }; 849 int mas_sprn[8] = { 850 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 851 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 852 }; 853 int i; 854 855 /* TLB assist registers */ 856 for (i = 0; i < 8; i++) { 857 if (mas_mask & (1 << i)) { 858 spr_register(env, mas_sprn[i], mas_names[i], 859 SPR_NOACCESS, SPR_NOACCESS, 860 &spr_read_generic, 861 (i == 2 && (env->insns_flags & PPC_64B)) 862 ? &spr_write_generic : &spr_write_generic32, 863 0x00000000); 864 } 865 } 866 if (env->nb_pids > 1) { 867 spr_register(env, SPR_BOOKE_PID1, "PID1", 868 SPR_NOACCESS, SPR_NOACCESS, 869 &spr_read_generic, &spr_write_booke_pid, 870 0x00000000); 871 } 872 if (env->nb_pids > 2) { 873 spr_register(env, SPR_BOOKE_PID2, "PID2", 874 SPR_NOACCESS, SPR_NOACCESS, 875 &spr_read_generic, &spr_write_booke_pid, 876 0x00000000); 877 } 878 879 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 880 SPR_NOACCESS, SPR_NOACCESS, 881 &spr_read_generic, &spr_write_eplc, 882 0x00000000); 883 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_epsc, 886 0x00000000); 887 888 spr_register(env, SPR_MMUCFG, "MMUCFG", 889 SPR_NOACCESS, SPR_NOACCESS, 890 &spr_read_generic, SPR_NOACCESS, 891 mmucfg); 892 switch (env->nb_ways) { 893 case 4: 894 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 895 SPR_NOACCESS, SPR_NOACCESS, 896 &spr_read_generic, SPR_NOACCESS, 897 tlbncfg[3]); 898 /* Fallthru */ 899 case 3: 900 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, SPR_NOACCESS, 903 tlbncfg[2]); 904 /* Fallthru */ 905 case 2: 906 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, SPR_NOACCESS, 909 tlbncfg[1]); 910 /* Fallthru */ 911 case 1: 912 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 913 SPR_NOACCESS, SPR_NOACCESS, 914 &spr_read_generic, SPR_NOACCESS, 915 tlbncfg[0]); 916 /* Fallthru */ 917 case 0: 918 default: 919 break; 920 } 921 #endif 922 } 923 924 /* SPR specific to PowerPC 440 implementation */ 925 static void register_440_sprs(CPUPPCState *env) 926 { 927 /* Cache control */ 928 spr_register(env, SPR_440_DNV0, "DNV0", 929 SPR_NOACCESS, SPR_NOACCESS, 930 &spr_read_generic, &spr_write_generic, 931 0x00000000); 932 933 spr_register(env, SPR_440_DNV1, "DNV1", 934 SPR_NOACCESS, SPR_NOACCESS, 935 &spr_read_generic, &spr_write_generic, 936 0x00000000); 937 938 spr_register(env, SPR_440_DNV2, "DNV2", 939 SPR_NOACCESS, SPR_NOACCESS, 940 &spr_read_generic, &spr_write_generic, 941 0x00000000); 942 943 spr_register(env, SPR_440_DNV3, "DNV3", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 948 spr_register(env, SPR_440_DTV0, "DTV0", 949 SPR_NOACCESS, SPR_NOACCESS, 950 &spr_read_generic, &spr_write_generic, 951 0x00000000); 952 953 spr_register(env, SPR_440_DTV1, "DTV1", 954 SPR_NOACCESS, SPR_NOACCESS, 955 &spr_read_generic, &spr_write_generic, 956 0x00000000); 957 958 spr_register(env, SPR_440_DTV2, "DTV2", 959 SPR_NOACCESS, SPR_NOACCESS, 960 &spr_read_generic, &spr_write_generic, 961 0x00000000); 962 963 spr_register(env, SPR_440_DTV3, "DTV3", 964 SPR_NOACCESS, SPR_NOACCESS, 965 &spr_read_generic, &spr_write_generic, 966 0x00000000); 967 968 spr_register(env, SPR_440_DVLIM, "DVLIM", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_generic, 971 0x00000000); 972 973 spr_register(env, SPR_440_INV0, "INV0", 974 SPR_NOACCESS, SPR_NOACCESS, 975 &spr_read_generic, &spr_write_generic, 976 0x00000000); 977 978 spr_register(env, SPR_440_INV1, "INV1", 979 SPR_NOACCESS, SPR_NOACCESS, 980 &spr_read_generic, &spr_write_generic, 981 0x00000000); 982 983 spr_register(env, SPR_440_INV2, "INV2", 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_generic, 986 0x00000000); 987 988 spr_register(env, SPR_440_INV3, "INV3", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_generic, &spr_write_generic, 991 0x00000000); 992 993 spr_register(env, SPR_440_ITV0, "ITV0", 994 SPR_NOACCESS, SPR_NOACCESS, 995 &spr_read_generic, &spr_write_generic, 996 0x00000000); 997 998 spr_register(env, SPR_440_ITV1, "ITV1", 999 SPR_NOACCESS, SPR_NOACCESS, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 1003 spr_register(env, SPR_440_ITV2, "ITV2", 1004 SPR_NOACCESS, SPR_NOACCESS, 1005 &spr_read_generic, &spr_write_generic, 1006 0x00000000); 1007 1008 spr_register(env, SPR_440_ITV3, "ITV3", 1009 SPR_NOACCESS, SPR_NOACCESS, 1010 &spr_read_generic, &spr_write_generic, 1011 0x00000000); 1012 1013 spr_register(env, SPR_440_IVLIM, "IVLIM", 1014 SPR_NOACCESS, SPR_NOACCESS, 1015 &spr_read_generic, &spr_write_generic, 1016 0x00000000); 1017 /* Cache debug */ 1018 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1019 SPR_NOACCESS, SPR_NOACCESS, 1020 &spr_read_generic, SPR_NOACCESS, 1021 0x00000000); 1022 1023 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1024 SPR_NOACCESS, SPR_NOACCESS, 1025 &spr_read_generic, SPR_NOACCESS, 1026 0x00000000); 1027 1028 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1029 SPR_NOACCESS, SPR_NOACCESS, 1030 &spr_read_generic, SPR_NOACCESS, 1031 0x00000000); 1032 1033 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1034 SPR_NOACCESS, SPR_NOACCESS, 1035 &spr_read_generic, SPR_NOACCESS, 1036 0x00000000); 1037 1038 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1039 SPR_NOACCESS, SPR_NOACCESS, 1040 &spr_read_generic, SPR_NOACCESS, 1041 0x00000000); 1042 1043 spr_register(env, SPR_440_DBDR, "DBDR", 1044 SPR_NOACCESS, SPR_NOACCESS, 1045 &spr_read_generic, &spr_write_generic, 1046 0x00000000); 1047 /* Processor control */ 1048 spr_register(env, SPR_4xx_CCR0, "CCR0", 1049 SPR_NOACCESS, SPR_NOACCESS, 1050 &spr_read_generic, &spr_write_generic, 1051 0x00000000); 1052 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1053 SPR_NOACCESS, SPR_NOACCESS, 1054 &spr_read_generic, SPR_NOACCESS, 1055 0x00000000); 1056 /* Storage control */ 1057 spr_register(env, SPR_440_MMUCR, "MMUCR", 1058 SPR_NOACCESS, SPR_NOACCESS, 1059 &spr_read_generic, &spr_write_generic, 1060 0x00000000); 1061 1062 /* Processor identification */ 1063 spr_register(env, SPR_BOOKE_PIR, "PIR", 1064 SPR_NOACCESS, SPR_NOACCESS, 1065 &spr_read_generic, &spr_write_pir, 1066 0x00000000); 1067 1068 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1069 SPR_NOACCESS, SPR_NOACCESS, 1070 &spr_read_generic, &spr_write_generic, 1071 0x00000000); 1072 1073 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1074 SPR_NOACCESS, SPR_NOACCESS, 1075 &spr_read_generic, &spr_write_generic, 1076 0x00000000); 1077 1078 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1079 SPR_NOACCESS, SPR_NOACCESS, 1080 &spr_read_generic, &spr_write_generic, 1081 0x00000000); 1082 1083 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1084 SPR_NOACCESS, SPR_NOACCESS, 1085 &spr_read_generic, &spr_write_generic, 1086 0x00000000); 1087 } 1088 1089 /* SPR shared between PowerPC 40x implementations */ 1090 static void register_40x_sprs(CPUPPCState *env) 1091 { 1092 /* Cache */ 1093 /* not emulated, as QEMU do not emulate caches */ 1094 spr_register(env, SPR_40x_DCCR, "DCCR", 1095 SPR_NOACCESS, SPR_NOACCESS, 1096 &spr_read_generic, &spr_write_generic, 1097 0x00000000); 1098 /* not emulated, as QEMU do not emulate caches */ 1099 spr_register(env, SPR_40x_ICCR, "ICCR", 1100 SPR_NOACCESS, SPR_NOACCESS, 1101 &spr_read_generic, &spr_write_generic, 1102 0x00000000); 1103 /* not emulated, as QEMU do not emulate caches */ 1104 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1105 SPR_NOACCESS, SPR_NOACCESS, 1106 &spr_read_generic, SPR_NOACCESS, 1107 0x00000000); 1108 /* Exception */ 1109 spr_register(env, SPR_40x_DEAR, "DEAR", 1110 SPR_NOACCESS, SPR_NOACCESS, 1111 &spr_read_generic, &spr_write_generic, 1112 0x00000000); 1113 spr_register(env, SPR_40x_ESR, "ESR", 1114 SPR_NOACCESS, SPR_NOACCESS, 1115 &spr_read_generic, &spr_write_generic, 1116 0x00000000); 1117 spr_register(env, SPR_40x_EVPR, "EVPR", 1118 SPR_NOACCESS, SPR_NOACCESS, 1119 &spr_read_generic, &spr_write_excp_prefix, 1120 0x00000000); 1121 spr_register(env, SPR_40x_SRR2, "SRR2", 1122 &spr_read_generic, &spr_write_generic, 1123 &spr_read_generic, &spr_write_generic, 1124 0x00000000); 1125 spr_register(env, SPR_40x_SRR3, "SRR3", 1126 &spr_read_generic, &spr_write_generic, 1127 &spr_read_generic, &spr_write_generic, 1128 0x00000000); 1129 /* Timers */ 1130 spr_register(env, SPR_40x_PIT, "PIT", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_40x_pit, &spr_write_40x_pit, 1133 0x00000000); 1134 spr_register(env, SPR_40x_TCR, "TCR", 1135 SPR_NOACCESS, SPR_NOACCESS, 1136 &spr_read_generic, &spr_write_40x_tcr, 1137 0x00000000); 1138 spr_register(env, SPR_40x_TSR, "TSR", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_40x_tsr, 1141 0x00000000); 1142 } 1143 1144 /* SPR specific to PowerPC 405 implementation */ 1145 static void register_405_sprs(CPUPPCState *env) 1146 { 1147 /* MMU */ 1148 spr_register(env, SPR_40x_PID, "PID", 1149 SPR_NOACCESS, SPR_NOACCESS, 1150 &spr_read_generic, &spr_write_40x_pid, 1151 0x00000000); 1152 spr_register(env, SPR_4xx_CCR0, "CCR0", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00700000); 1156 /* Debug interface */ 1157 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_40x_dbcr0, 1160 0x00000000); 1161 1162 spr_register(env, SPR_405_DBCR1, "DBCR1", 1163 SPR_NOACCESS, SPR_NOACCESS, 1164 &spr_read_generic, &spr_write_generic, 1165 0x00000000); 1166 1167 spr_register(env, SPR_40x_DBSR, "DBSR", 1168 SPR_NOACCESS, SPR_NOACCESS, 1169 &spr_read_generic, &spr_write_clear, 1170 /* Last reset was system reset */ 1171 0x00000300); 1172 1173 spr_register(env, SPR_40x_DAC1, "DAC1", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 spr_register(env, SPR_40x_DAC2, "DAC2", 1178 SPR_NOACCESS, SPR_NOACCESS, 1179 &spr_read_generic, &spr_write_generic, 1180 0x00000000); 1181 1182 spr_register(env, SPR_405_DVC1, "DVC1", 1183 SPR_NOACCESS, SPR_NOACCESS, 1184 &spr_read_generic, &spr_write_generic, 1185 0x00000000); 1186 1187 spr_register(env, SPR_405_DVC2, "DVC2", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, &spr_write_generic, 1190 0x00000000); 1191 1192 spr_register(env, SPR_40x_IAC1, "IAC1", 1193 SPR_NOACCESS, SPR_NOACCESS, 1194 &spr_read_generic, &spr_write_generic, 1195 0x00000000); 1196 spr_register(env, SPR_40x_IAC2, "IAC2", 1197 SPR_NOACCESS, SPR_NOACCESS, 1198 &spr_read_generic, &spr_write_generic, 1199 0x00000000); 1200 1201 spr_register(env, SPR_405_IAC3, "IAC3", 1202 SPR_NOACCESS, SPR_NOACCESS, 1203 &spr_read_generic, &spr_write_generic, 1204 0x00000000); 1205 1206 spr_register(env, SPR_405_IAC4, "IAC4", 1207 SPR_NOACCESS, SPR_NOACCESS, 1208 &spr_read_generic, &spr_write_generic, 1209 0x00000000); 1210 /* Storage control */ 1211 spr_register(env, SPR_405_SLER, "SLER", 1212 SPR_NOACCESS, SPR_NOACCESS, 1213 &spr_read_generic, &spr_write_40x_sler, 1214 0x00000000); 1215 spr_register(env, SPR_40x_ZPR, "ZPR", 1216 SPR_NOACCESS, SPR_NOACCESS, 1217 &spr_read_generic, &spr_write_generic, 1218 0x00000000); 1219 1220 spr_register(env, SPR_405_SU0R, "SU0R", 1221 SPR_NOACCESS, SPR_NOACCESS, 1222 &spr_read_generic, &spr_write_generic, 1223 0x00000000); 1224 /* SPRG */ 1225 spr_register(env, SPR_USPRG0, "USPRG0", 1226 &spr_read_ureg, SPR_NOACCESS, 1227 &spr_read_ureg, SPR_NOACCESS, 1228 0x00000000); 1229 spr_register(env, SPR_SPRG4, "SPRG4", 1230 SPR_NOACCESS, SPR_NOACCESS, 1231 &spr_read_generic, &spr_write_generic, 1232 0x00000000); 1233 spr_register(env, SPR_SPRG5, "SPRG5", 1234 SPR_NOACCESS, SPR_NOACCESS, 1235 spr_read_generic, &spr_write_generic, 1236 0x00000000); 1237 spr_register(env, SPR_SPRG6, "SPRG6", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 spr_read_generic, &spr_write_generic, 1240 0x00000000); 1241 spr_register(env, SPR_SPRG7, "SPRG7", 1242 SPR_NOACCESS, SPR_NOACCESS, 1243 spr_read_generic, &spr_write_generic, 1244 0x00000000); 1245 1246 /* Bus access control */ 1247 /* not emulated, as QEMU never does speculative access */ 1248 spr_register(env, SPR_40x_SGR, "SGR", 1249 SPR_NOACCESS, SPR_NOACCESS, 1250 &spr_read_generic, &spr_write_generic, 1251 0xFFFFFFFF); 1252 /* not emulated, as QEMU do not emulate caches */ 1253 spr_register(env, SPR_40x_DCWR, "DCWR", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, &spr_write_generic, 1256 0x00000000); 1257 } 1258 1259 1260 static void register_5xx_8xx_sprs(CPUPPCState *env) 1261 { 1262 /* Exception processing */ 1263 spr_register_kvm(env, SPR_DSISR, "DSISR", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, &spr_write_generic, 1266 KVM_REG_PPC_DSISR, 0x00000000); 1267 spr_register_kvm(env, SPR_DAR, "DAR", 1268 SPR_NOACCESS, SPR_NOACCESS, 1269 &spr_read_generic, &spr_write_generic, 1270 KVM_REG_PPC_DAR, 0x00000000); 1271 /* Timer */ 1272 spr_register(env, SPR_DECR, "DECR", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_decr, &spr_write_decr, 1275 0x00000000); 1276 1277 spr_register(env, SPR_MPC_EIE, "EIE", 1278 SPR_NOACCESS, SPR_NOACCESS, 1279 &spr_read_generic, &spr_write_generic, 1280 0x00000000); 1281 1282 spr_register(env, SPR_MPC_EID, "EID", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 1287 spr_register(env, SPR_MPC_NRI, "NRI", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, &spr_write_generic, 1290 0x00000000); 1291 1292 spr_register(env, SPR_MPC_CMPA, "CMPA", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, &spr_write_generic, 1295 0x00000000); 1296 1297 spr_register(env, SPR_MPC_CMPB, "CMPB", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 1302 spr_register(env, SPR_MPC_CMPC, "CMPC", 1303 SPR_NOACCESS, SPR_NOACCESS, 1304 &spr_read_generic, &spr_write_generic, 1305 0x00000000); 1306 1307 spr_register(env, SPR_MPC_CMPD, "CMPD", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, &spr_write_generic, 1310 0x00000000); 1311 1312 spr_register(env, SPR_MPC_ECR, "ECR", 1313 SPR_NOACCESS, SPR_NOACCESS, 1314 &spr_read_generic, &spr_write_generic, 1315 0x00000000); 1316 1317 spr_register(env, SPR_MPC_DER, "DER", 1318 SPR_NOACCESS, SPR_NOACCESS, 1319 &spr_read_generic, &spr_write_generic, 1320 0x00000000); 1321 1322 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1323 SPR_NOACCESS, SPR_NOACCESS, 1324 &spr_read_generic, &spr_write_generic, 1325 0x00000000); 1326 1327 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1328 SPR_NOACCESS, SPR_NOACCESS, 1329 &spr_read_generic, &spr_write_generic, 1330 0x00000000); 1331 1332 spr_register(env, SPR_MPC_CMPE, "CMPE", 1333 SPR_NOACCESS, SPR_NOACCESS, 1334 &spr_read_generic, &spr_write_generic, 1335 0x00000000); 1336 1337 spr_register(env, SPR_MPC_CMPF, "CMPF", 1338 SPR_NOACCESS, SPR_NOACCESS, 1339 &spr_read_generic, &spr_write_generic, 1340 0x00000000); 1341 1342 spr_register(env, SPR_MPC_CMPG, "CMPG", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, &spr_write_generic, 1345 0x00000000); 1346 1347 spr_register(env, SPR_MPC_CMPH, "CMPH", 1348 SPR_NOACCESS, SPR_NOACCESS, 1349 &spr_read_generic, &spr_write_generic, 1350 0x00000000); 1351 1352 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1353 SPR_NOACCESS, SPR_NOACCESS, 1354 &spr_read_generic, &spr_write_generic, 1355 0x00000000); 1356 1357 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1358 SPR_NOACCESS, SPR_NOACCESS, 1359 &spr_read_generic, &spr_write_generic, 1360 0x00000000); 1361 1362 spr_register(env, SPR_MPC_BAR, "BAR", 1363 SPR_NOACCESS, SPR_NOACCESS, 1364 &spr_read_generic, &spr_write_generic, 1365 0x00000000); 1366 1367 spr_register(env, SPR_MPC_DPDR, "DPDR", 1368 SPR_NOACCESS, SPR_NOACCESS, 1369 &spr_read_generic, &spr_write_generic, 1370 0x00000000); 1371 1372 spr_register(env, SPR_MPC_IMMR, "IMMR", 1373 SPR_NOACCESS, SPR_NOACCESS, 1374 &spr_read_generic, &spr_write_generic, 1375 0x00000000); 1376 } 1377 1378 static void register_5xx_sprs(CPUPPCState *env) 1379 { 1380 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 1385 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, &spr_write_generic, 1388 0x00000000); 1389 1390 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_generic, &spr_write_generic, 1393 0x00000000); 1394 1395 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1396 SPR_NOACCESS, SPR_NOACCESS, 1397 &spr_read_generic, &spr_write_generic, 1398 0x00000000); 1399 1400 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 &spr_read_generic, &spr_write_generic, 1403 0x00000000); 1404 1405 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1406 SPR_NOACCESS, SPR_NOACCESS, 1407 &spr_read_generic, &spr_write_generic, 1408 0x00000000); 1409 1410 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, &spr_write_generic, 1413 0x00000000); 1414 1415 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 0x00000000); 1419 1420 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 1425 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 &spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 1430 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1431 SPR_NOACCESS, SPR_NOACCESS, 1432 &spr_read_generic, &spr_write_generic, 1433 0x00000000); 1434 1435 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1436 SPR_NOACCESS, SPR_NOACCESS, 1437 &spr_read_generic, &spr_write_generic, 1438 0x00000000); 1439 1440 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 0x00000000); 1444 1445 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 1450 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 0x00000000); 1454 1455 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 1460 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 1465 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_generic, 1468 0x00000000); 1469 1470 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_generic, 1478 0x00000000); 1479 1480 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 } 1485 1486 static void register_8xx_sprs(CPUPPCState *env) 1487 { 1488 1489 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 1494 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 1499 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, &spr_write_generic, 1502 0x00000000); 1503 1504 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 1509 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 1514 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_generic, 1517 0x00000000); 1518 1519 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1520 SPR_NOACCESS, SPR_NOACCESS, 1521 &spr_read_generic, &spr_write_generic, 1522 0x00000000); 1523 1524 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 1529 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 1534 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 1539 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 1544 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1545 SPR_NOACCESS, SPR_NOACCESS, 1546 &spr_read_generic, &spr_write_generic, 1547 0x00000000); 1548 1549 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 1554 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1555 SPR_NOACCESS, SPR_NOACCESS, 1556 &spr_read_generic, &spr_write_generic, 1557 0x00000000); 1558 1559 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1560 SPR_NOACCESS, SPR_NOACCESS, 1561 &spr_read_generic, &spr_write_generic, 1562 0x00000000); 1563 1564 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1565 SPR_NOACCESS, SPR_NOACCESS, 1566 &spr_read_generic, &spr_write_generic, 1567 0x00000000); 1568 1569 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1570 SPR_NOACCESS, SPR_NOACCESS, 1571 &spr_read_generic, &spr_write_generic, 1572 0x00000000); 1573 1574 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1575 SPR_NOACCESS, SPR_NOACCESS, 1576 &spr_read_generic, &spr_write_generic, 1577 0x00000000); 1578 1579 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1580 SPR_NOACCESS, SPR_NOACCESS, 1581 &spr_read_generic, &spr_write_generic, 1582 0x00000000); 1583 1584 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1585 SPR_NOACCESS, SPR_NOACCESS, 1586 &spr_read_generic, &spr_write_generic, 1587 0x00000000); 1588 1589 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1590 SPR_NOACCESS, SPR_NOACCESS, 1591 &spr_read_generic, &spr_write_generic, 1592 0x00000000); 1593 1594 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1595 SPR_NOACCESS, SPR_NOACCESS, 1596 &spr_read_generic, &spr_write_generic, 1597 0x00000000); 1598 1599 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1600 SPR_NOACCESS, SPR_NOACCESS, 1601 &spr_read_generic, &spr_write_generic, 1602 0x00000000); 1603 1604 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1605 SPR_NOACCESS, SPR_NOACCESS, 1606 &spr_read_generic, &spr_write_generic, 1607 0x00000000); 1608 1609 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1610 SPR_NOACCESS, SPR_NOACCESS, 1611 &spr_read_generic, &spr_write_generic, 1612 0x00000000); 1613 } 1614 1615 /* 1616 * AMR => SPR 29 (Power 2.04) 1617 * CTRL => SPR 136 (Power 2.04) 1618 * CTRL => SPR 152 (Power 2.04) 1619 * SCOMC => SPR 276 (64 bits ?) 1620 * SCOMD => SPR 277 (64 bits ?) 1621 * TBU40 => SPR 286 (Power 2.04 hypv) 1622 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1623 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1624 * HDSISR => SPR 306 (Power 2.04 hypv) 1625 * HDAR => SPR 307 (Power 2.04 hypv) 1626 * PURR => SPR 309 (Power 2.04 hypv) 1627 * HDEC => SPR 310 (Power 2.04 hypv) 1628 * HIOR => SPR 311 (hypv) 1629 * RMOR => SPR 312 (970) 1630 * HRMOR => SPR 313 (Power 2.04 hypv) 1631 * HSRR0 => SPR 314 (Power 2.04 hypv) 1632 * HSRR1 => SPR 315 (Power 2.04 hypv) 1633 * LPIDR => SPR 317 (970) 1634 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1635 * EPR => SPR 702 (Power 2.04 emb) 1636 * perf => 768-783 (Power 2.04) 1637 * perf => 784-799 (Power 2.04) 1638 * PPR => SPR 896 (Power 2.04) 1639 * DABRX => 1015 (Power 2.04 hypv) 1640 * FPECR => SPR 1022 (?) 1641 * ... and more (thermal management, performance counters, ...) 1642 */ 1643 1644 /*****************************************************************************/ 1645 /* Exception vectors models */ 1646 static void init_excp_4xx(CPUPPCState *env) 1647 { 1648 #if !defined(CONFIG_USER_ONLY) 1649 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1650 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1651 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1652 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1653 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1654 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1655 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1656 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1657 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1658 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1659 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1660 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1661 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1662 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1663 env->ivor_mask = 0x0000FFF0UL; 1664 env->ivpr_mask = 0xFFFF0000UL; 1665 /* Hardware reset vector */ 1666 env->hreset_vector = 0xFFFFFFFCUL; 1667 #endif 1668 } 1669 1670 static void init_excp_MPC5xx(CPUPPCState *env) 1671 { 1672 #if !defined(CONFIG_USER_ONLY) 1673 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1674 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1675 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1676 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1677 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1678 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1679 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1680 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1681 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1682 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1683 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1684 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1685 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1686 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1687 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1688 env->ivor_mask = 0x0000FFF0UL; 1689 env->ivpr_mask = 0xFFFF0000UL; 1690 /* Hardware reset vector */ 1691 env->hreset_vector = 0x00000100UL; 1692 #endif 1693 } 1694 1695 static void init_excp_MPC8xx(CPUPPCState *env) 1696 { 1697 #if !defined(CONFIG_USER_ONLY) 1698 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1699 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1700 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1701 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1702 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1703 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1704 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1705 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1706 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1707 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1708 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1709 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1710 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1711 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1712 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1713 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1714 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1715 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1716 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1717 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1718 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1719 env->ivor_mask = 0x0000FFF0UL; 1720 env->ivpr_mask = 0xFFFF0000UL; 1721 /* Hardware reset vector */ 1722 env->hreset_vector = 0x00000100UL; 1723 #endif 1724 } 1725 1726 static void init_excp_G2(CPUPPCState *env) 1727 { 1728 #if !defined(CONFIG_USER_ONLY) 1729 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1730 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1731 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1732 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1733 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1734 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1735 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1736 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1737 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1738 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1739 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1740 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1741 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1742 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1743 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1744 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1745 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1746 /* Hardware reset vector */ 1747 env->hreset_vector = 0x00000100UL; 1748 #endif 1749 } 1750 1751 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1752 { 1753 #if !defined(CONFIG_USER_ONLY) 1754 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1755 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1756 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1757 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1758 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1759 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1760 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1761 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1762 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1763 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1764 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1765 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1766 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1767 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1768 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1770 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1771 /* 1772 * These two are the same IVOR as POWERPC_EXCP_VPU and 1773 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1774 * powerpc_excp(). 1775 */ 1776 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1777 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1778 1779 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1780 env->ivor_mask = 0x0000FFF7UL; 1781 env->ivpr_mask = ivpr_mask; 1782 /* Hardware reset vector */ 1783 env->hreset_vector = 0xFFFFFFFCUL; 1784 #endif 1785 } 1786 1787 static void init_excp_BookE(CPUPPCState *env) 1788 { 1789 #if !defined(CONFIG_USER_ONLY) 1790 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1791 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1792 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1793 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1794 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1795 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1796 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1797 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1798 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1799 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1800 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1801 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1802 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1803 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1805 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1806 env->ivor_mask = 0x0000FFF0UL; 1807 env->ivpr_mask = 0xFFFF0000UL; 1808 /* Hardware reset vector */ 1809 env->hreset_vector = 0xFFFFFFFCUL; 1810 #endif 1811 } 1812 1813 static void init_excp_603(CPUPPCState *env) 1814 { 1815 #if !defined(CONFIG_USER_ONLY) 1816 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1817 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1818 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1819 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1820 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1821 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1822 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1823 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1824 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1825 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1826 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1827 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1828 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1829 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1830 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1831 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1832 /* Hardware reset vector */ 1833 env->hreset_vector = 0x00000100UL; 1834 #endif 1835 } 1836 1837 static void init_excp_604(CPUPPCState *env) 1838 { 1839 #if !defined(CONFIG_USER_ONLY) 1840 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1841 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1842 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1843 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1844 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1845 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1846 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1847 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1848 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1849 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1850 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1851 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1852 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1853 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1854 /* Hardware reset vector */ 1855 env->hreset_vector = 0x00000100UL; 1856 #endif 1857 } 1858 1859 static void init_excp_7x0(CPUPPCState *env) 1860 { 1861 #if !defined(CONFIG_USER_ONLY) 1862 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1863 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1864 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1865 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1866 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1867 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1868 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1869 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1870 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1871 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1872 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1873 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1874 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1875 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1876 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1877 /* Hardware reset vector */ 1878 env->hreset_vector = 0x00000100UL; 1879 #endif 1880 } 1881 1882 static void init_excp_750cl(CPUPPCState *env) 1883 { 1884 #if !defined(CONFIG_USER_ONLY) 1885 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1886 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1887 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1888 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1889 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1890 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1891 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1892 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1893 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1894 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1895 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1896 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1897 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1898 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1899 /* Hardware reset vector */ 1900 env->hreset_vector = 0x00000100UL; 1901 #endif 1902 } 1903 1904 static void init_excp_750cx(CPUPPCState *env) 1905 { 1906 #if !defined(CONFIG_USER_ONLY) 1907 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1908 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1909 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1910 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1911 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1912 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1913 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1914 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1915 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1916 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1917 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1918 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1919 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1920 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1921 /* Hardware reset vector */ 1922 env->hreset_vector = 0x00000100UL; 1923 #endif 1924 } 1925 1926 /* XXX: Check if this is correct */ 1927 static void init_excp_7x5(CPUPPCState *env) 1928 { 1929 #if !defined(CONFIG_USER_ONLY) 1930 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1931 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1932 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1933 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1934 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1935 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1936 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1937 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1938 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1939 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1940 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1941 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1942 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1943 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1944 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1945 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1946 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1947 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1948 /* Hardware reset vector */ 1949 env->hreset_vector = 0x00000100UL; 1950 #endif 1951 } 1952 1953 static void init_excp_7400(CPUPPCState *env) 1954 { 1955 #if !defined(CONFIG_USER_ONLY) 1956 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1957 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1958 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1959 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1960 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1961 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1962 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1963 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1964 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1965 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1966 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1967 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1968 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1969 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1970 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1971 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1972 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1973 /* Hardware reset vector */ 1974 env->hreset_vector = 0x00000100UL; 1975 #endif 1976 } 1977 1978 static void init_excp_7450(CPUPPCState *env) 1979 { 1980 #if !defined(CONFIG_USER_ONLY) 1981 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1982 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1983 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1984 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1985 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1986 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1987 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1988 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1989 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1990 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1991 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1992 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1993 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1994 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1995 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1996 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1997 /* Hardware reset vector */ 1998 env->hreset_vector = 0x00000100UL; 1999 #endif 2000 } 2001 2002 #if defined(TARGET_PPC64) 2003 static void init_excp_970(CPUPPCState *env) 2004 { 2005 #if !defined(CONFIG_USER_ONLY) 2006 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2007 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2008 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2009 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2010 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2011 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2017 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2019 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2020 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2021 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2022 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2023 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2024 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2025 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2026 /* Hardware reset vector */ 2027 env->hreset_vector = 0x0000000000000100ULL; 2028 #endif 2029 } 2030 2031 static void init_excp_POWER7(CPUPPCState *env) 2032 { 2033 #if !defined(CONFIG_USER_ONLY) 2034 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2035 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2036 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2037 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2038 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2039 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2045 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2046 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2047 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2048 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2049 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2050 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2051 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2052 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2053 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2054 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2055 /* Hardware reset vector */ 2056 env->hreset_vector = 0x0000000000000100ULL; 2057 #endif 2058 } 2059 2060 static void init_excp_POWER8(CPUPPCState *env) 2061 { 2062 init_excp_POWER7(env); 2063 2064 #if !defined(CONFIG_USER_ONLY) 2065 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2066 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2067 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2068 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2069 2070 /* Userland exceptions without vector value in PowerISA v3.1 */ 2071 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2072 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2073 #endif 2074 } 2075 2076 static void init_excp_POWER9(CPUPPCState *env) 2077 { 2078 init_excp_POWER8(env); 2079 2080 #if !defined(CONFIG_USER_ONLY) 2081 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2082 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2083 #endif 2084 } 2085 2086 static void init_excp_POWER10(CPUPPCState *env) 2087 { 2088 init_excp_POWER9(env); 2089 } 2090 2091 #endif 2092 2093 static int check_pow_hid0(CPUPPCState *env) 2094 { 2095 if (env->spr[SPR_HID0] & 0x00E00000) { 2096 return 1; 2097 } 2098 2099 return 0; 2100 } 2101 2102 static int check_pow_hid0_74xx(CPUPPCState *env) 2103 { 2104 if (env->spr[SPR_HID0] & 0x00600000) { 2105 return 1; 2106 } 2107 2108 return 0; 2109 } 2110 2111 #if defined(TARGET_PPC64) 2112 static int check_attn_hid0(CPUPPCState *env) 2113 { 2114 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2115 return 1; 2116 } 2117 2118 return 0; 2119 } 2120 2121 static int check_attn_hid0_power9(CPUPPCState *env) 2122 { 2123 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2124 return 1; 2125 } 2126 2127 return 0; 2128 } 2129 #endif 2130 2131 static void init_tlbs_emb(CPUPPCState *env) 2132 { 2133 #ifndef CONFIG_USER_ONLY 2134 env->nb_tlb = 64; 2135 env->nb_ways = 1; 2136 env->tlb_type = TLB_EMB; 2137 #endif 2138 } 2139 2140 static void init_proc_405(CPUPPCState *env) 2141 { 2142 register_40x_sprs(env); 2143 register_405_sprs(env); 2144 register_usprgh_sprs(env); 2145 2146 init_tlbs_emb(env); 2147 init_excp_4xx(env); 2148 env->dcache_line_size = 32; 2149 env->icache_line_size = 32; 2150 /* Allocate hardware IRQ controller */ 2151 ppc40x_irq_init(env_archcpu(env)); 2152 2153 SET_FIT_PERIOD(8, 12, 16, 20); 2154 SET_WDT_PERIOD(16, 20, 24, 28); 2155 } 2156 2157 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2158 { 2159 DeviceClass *dc = DEVICE_CLASS(oc); 2160 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2161 2162 dc->desc = "PowerPC 405"; 2163 pcc->init_proc = init_proc_405; 2164 pcc->check_pow = check_pow_nocheck; 2165 pcc->check_attn = check_attn_none; 2166 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2167 PPC_DCR | PPC_WRTEE | 2168 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2169 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2170 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2171 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2172 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2173 pcc->msr_mask = (1ull << MSR_WE) | 2174 (1ull << MSR_CE) | 2175 (1ull << MSR_EE) | 2176 (1ull << MSR_PR) | 2177 (1ull << MSR_FP) | 2178 (1ull << MSR_ME) | 2179 (1ull << MSR_DWE) | 2180 (1ull << MSR_DE) | 2181 (1ull << MSR_IR) | 2182 (1ull << MSR_DR); 2183 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2184 pcc->excp_model = POWERPC_EXCP_40x; 2185 pcc->bus_model = PPC_FLAGS_INPUT_405; 2186 pcc->bfd_mach = bfd_mach_ppc_403; 2187 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2188 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2189 } 2190 2191 static void init_proc_440EP(CPUPPCState *env) 2192 { 2193 register_BookE_sprs(env, 0x000000000000FFFFULL); 2194 register_440_sprs(env); 2195 register_usprgh_sprs(env); 2196 2197 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2198 SPR_NOACCESS, SPR_NOACCESS, 2199 &spr_read_generic, &spr_write_generic, 2200 0x00000000); 2201 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2202 SPR_NOACCESS, SPR_NOACCESS, 2203 &spr_read_generic, &spr_write_generic, 2204 0x00000000); 2205 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2206 SPR_NOACCESS, SPR_NOACCESS, 2207 &spr_read_generic, &spr_write_generic, 2208 0x00000000); 2209 2210 spr_register(env, SPR_440_CCR1, "CCR1", 2211 SPR_NOACCESS, SPR_NOACCESS, 2212 &spr_read_generic, &spr_write_generic, 2213 0x00000000); 2214 2215 init_tlbs_emb(env); 2216 init_excp_BookE(env); 2217 env->dcache_line_size = 32; 2218 env->icache_line_size = 32; 2219 ppc40x_irq_init(env_archcpu(env)); 2220 2221 SET_FIT_PERIOD(12, 16, 20, 24); 2222 SET_WDT_PERIOD(20, 24, 28, 32); 2223 } 2224 2225 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2226 { 2227 DeviceClass *dc = DEVICE_CLASS(oc); 2228 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2229 2230 dc->desc = "PowerPC 440 EP"; 2231 pcc->init_proc = init_proc_440EP; 2232 pcc->check_pow = check_pow_nocheck; 2233 pcc->check_attn = check_attn_none; 2234 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2235 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2236 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2237 PPC_FLOAT_STFIWX | 2238 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2239 PPC_CACHE | PPC_CACHE_ICBI | 2240 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2241 PPC_MEM_TLBSYNC | PPC_MFTB | 2242 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2243 PPC_440_SPEC; 2244 pcc->msr_mask = (1ull << MSR_POW) | 2245 (1ull << MSR_CE) | 2246 (1ull << MSR_EE) | 2247 (1ull << MSR_PR) | 2248 (1ull << MSR_FP) | 2249 (1ull << MSR_ME) | 2250 (1ull << MSR_FE0) | 2251 (1ull << MSR_DWE) | 2252 (1ull << MSR_DE) | 2253 (1ull << MSR_FE1) | 2254 (1ull << MSR_IR) | 2255 (1ull << MSR_DR); 2256 pcc->mmu_model = POWERPC_MMU_BOOKE; 2257 pcc->excp_model = POWERPC_EXCP_BOOKE; 2258 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2259 pcc->bfd_mach = bfd_mach_ppc_403; 2260 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2261 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2262 } 2263 2264 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2265 { 2266 DeviceClass *dc = DEVICE_CLASS(oc); 2267 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2268 2269 dc->desc = "PowerPC 460 EX"; 2270 pcc->init_proc = init_proc_440EP; 2271 pcc->check_pow = check_pow_nocheck; 2272 pcc->check_attn = check_attn_none; 2273 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2274 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2275 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2276 PPC_FLOAT_STFIWX | 2277 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2278 PPC_CACHE | PPC_CACHE_ICBI | 2279 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2280 PPC_MEM_TLBSYNC | PPC_MFTB | 2281 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2282 PPC_440_SPEC; 2283 pcc->msr_mask = (1ull << MSR_POW) | 2284 (1ull << MSR_CE) | 2285 (1ull << MSR_EE) | 2286 (1ull << MSR_PR) | 2287 (1ull << MSR_FP) | 2288 (1ull << MSR_ME) | 2289 (1ull << MSR_FE0) | 2290 (1ull << MSR_DWE) | 2291 (1ull << MSR_DE) | 2292 (1ull << MSR_FE1) | 2293 (1ull << MSR_IR) | 2294 (1ull << MSR_DR); 2295 pcc->mmu_model = POWERPC_MMU_BOOKE; 2296 pcc->excp_model = POWERPC_EXCP_BOOKE; 2297 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2298 pcc->bfd_mach = bfd_mach_ppc_403; 2299 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2300 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2301 } 2302 2303 static void init_proc_440GP(CPUPPCState *env) 2304 { 2305 register_BookE_sprs(env, 0x000000000000FFFFULL); 2306 register_440_sprs(env); 2307 register_usprgh_sprs(env); 2308 2309 init_tlbs_emb(env); 2310 init_excp_BookE(env); 2311 env->dcache_line_size = 32; 2312 env->icache_line_size = 32; 2313 /* XXX: TODO: allocate internal IRQ controller */ 2314 2315 SET_FIT_PERIOD(12, 16, 20, 24); 2316 SET_WDT_PERIOD(20, 24, 28, 32); 2317 } 2318 2319 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2320 { 2321 DeviceClass *dc = DEVICE_CLASS(oc); 2322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2323 2324 dc->desc = "PowerPC 440 GP"; 2325 pcc->init_proc = init_proc_440GP; 2326 pcc->check_pow = check_pow_nocheck; 2327 pcc->check_attn = check_attn_none; 2328 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2329 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2330 PPC_CACHE | PPC_CACHE_ICBI | 2331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2332 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2333 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2334 PPC_440_SPEC; 2335 pcc->msr_mask = (1ull << MSR_POW) | 2336 (1ull << MSR_CE) | 2337 (1ull << MSR_EE) | 2338 (1ull << MSR_PR) | 2339 (1ull << MSR_FP) | 2340 (1ull << MSR_ME) | 2341 (1ull << MSR_FE0) | 2342 (1ull << MSR_DWE) | 2343 (1ull << MSR_DE) | 2344 (1ull << MSR_FE1) | 2345 (1ull << MSR_IR) | 2346 (1ull << MSR_DR); 2347 pcc->mmu_model = POWERPC_MMU_BOOKE; 2348 pcc->excp_model = POWERPC_EXCP_BOOKE; 2349 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2350 pcc->bfd_mach = bfd_mach_ppc_403; 2351 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2352 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2353 } 2354 2355 static void init_proc_440x5(CPUPPCState *env) 2356 { 2357 register_BookE_sprs(env, 0x000000000000FFFFULL); 2358 register_440_sprs(env); 2359 register_usprgh_sprs(env); 2360 2361 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2362 SPR_NOACCESS, SPR_NOACCESS, 2363 &spr_read_generic, &spr_write_generic, 2364 0x00000000); 2365 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2366 SPR_NOACCESS, SPR_NOACCESS, 2367 &spr_read_generic, &spr_write_generic, 2368 0x00000000); 2369 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2370 SPR_NOACCESS, SPR_NOACCESS, 2371 &spr_read_generic, &spr_write_generic, 2372 0x00000000); 2373 2374 spr_register(env, SPR_440_CCR1, "CCR1", 2375 SPR_NOACCESS, SPR_NOACCESS, 2376 &spr_read_generic, &spr_write_generic, 2377 0x00000000); 2378 2379 init_tlbs_emb(env); 2380 init_excp_BookE(env); 2381 env->dcache_line_size = 32; 2382 env->icache_line_size = 32; 2383 ppc40x_irq_init(env_archcpu(env)); 2384 2385 SET_FIT_PERIOD(12, 16, 20, 24); 2386 SET_WDT_PERIOD(20, 24, 28, 32); 2387 } 2388 2389 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2390 { 2391 DeviceClass *dc = DEVICE_CLASS(oc); 2392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2393 2394 dc->desc = "PowerPC 440x5"; 2395 pcc->init_proc = init_proc_440x5; 2396 pcc->check_pow = check_pow_nocheck; 2397 pcc->check_attn = check_attn_none; 2398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2399 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2400 PPC_CACHE | PPC_CACHE_ICBI | 2401 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2402 PPC_MEM_TLBSYNC | PPC_MFTB | 2403 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2404 PPC_440_SPEC; 2405 pcc->msr_mask = (1ull << MSR_POW) | 2406 (1ull << MSR_CE) | 2407 (1ull << MSR_EE) | 2408 (1ull << MSR_PR) | 2409 (1ull << MSR_FP) | 2410 (1ull << MSR_ME) | 2411 (1ull << MSR_FE0) | 2412 (1ull << MSR_DWE) | 2413 (1ull << MSR_DE) | 2414 (1ull << MSR_FE1) | 2415 (1ull << MSR_IR) | 2416 (1ull << MSR_DR); 2417 pcc->mmu_model = POWERPC_MMU_BOOKE; 2418 pcc->excp_model = POWERPC_EXCP_BOOKE; 2419 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2420 pcc->bfd_mach = bfd_mach_ppc_403; 2421 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2422 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2423 } 2424 2425 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2426 { 2427 DeviceClass *dc = DEVICE_CLASS(oc); 2428 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2429 2430 dc->desc = "PowerPC 440x5 with double precision FPU"; 2431 pcc->init_proc = init_proc_440x5; 2432 pcc->check_pow = check_pow_nocheck; 2433 pcc->check_attn = check_attn_none; 2434 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2435 PPC_FLOAT | PPC_FLOAT_FSQRT | 2436 PPC_FLOAT_STFIWX | 2437 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2438 PPC_CACHE | PPC_CACHE_ICBI | 2439 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2440 PPC_MEM_TLBSYNC | PPC_MFTB | 2441 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2442 PPC_440_SPEC; 2443 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2444 pcc->msr_mask = (1ull << MSR_POW) | 2445 (1ull << MSR_CE) | 2446 (1ull << MSR_EE) | 2447 (1ull << MSR_PR) | 2448 (1ull << MSR_FP) | 2449 (1ull << MSR_ME) | 2450 (1ull << MSR_FE0) | 2451 (1ull << MSR_DWE) | 2452 (1ull << MSR_DE) | 2453 (1ull << MSR_FE1) | 2454 (1ull << MSR_IR) | 2455 (1ull << MSR_DR); 2456 pcc->mmu_model = POWERPC_MMU_BOOKE; 2457 pcc->excp_model = POWERPC_EXCP_BOOKE; 2458 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2459 pcc->bfd_mach = bfd_mach_ppc_403; 2460 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2461 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2462 } 2463 2464 static void init_proc_MPC5xx(CPUPPCState *env) 2465 { 2466 register_5xx_8xx_sprs(env); 2467 register_5xx_sprs(env); 2468 init_excp_MPC5xx(env); 2469 env->dcache_line_size = 32; 2470 env->icache_line_size = 32; 2471 /* XXX: TODO: allocate internal IRQ controller */ 2472 } 2473 2474 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2475 { 2476 DeviceClass *dc = DEVICE_CLASS(oc); 2477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2478 2479 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2480 pcc->init_proc = init_proc_MPC5xx; 2481 pcc->check_pow = check_pow_none; 2482 pcc->check_attn = check_attn_none; 2483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2484 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2485 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2486 PPC_MFTB; 2487 pcc->msr_mask = (1ull << MSR_ILE) | 2488 (1ull << MSR_EE) | 2489 (1ull << MSR_PR) | 2490 (1ull << MSR_FP) | 2491 (1ull << MSR_ME) | 2492 (1ull << MSR_FE0) | 2493 (1ull << MSR_SE) | 2494 (1ull << MSR_DE) | 2495 (1ull << MSR_FE1) | 2496 (1ull << MSR_EP) | 2497 (1ull << MSR_RI) | 2498 (1ull << MSR_LE); 2499 pcc->mmu_model = POWERPC_MMU_REAL; 2500 pcc->excp_model = POWERPC_EXCP_6xx; 2501 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2502 pcc->bfd_mach = bfd_mach_ppc_505; 2503 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2504 POWERPC_FLAG_BUS_CLK; 2505 } 2506 2507 static void init_proc_MPC8xx(CPUPPCState *env) 2508 { 2509 register_5xx_8xx_sprs(env); 2510 register_8xx_sprs(env); 2511 init_excp_MPC8xx(env); 2512 env->dcache_line_size = 32; 2513 env->icache_line_size = 32; 2514 /* XXX: TODO: allocate internal IRQ controller */ 2515 } 2516 2517 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2518 { 2519 DeviceClass *dc = DEVICE_CLASS(oc); 2520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2521 2522 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2523 pcc->init_proc = init_proc_MPC8xx; 2524 pcc->check_pow = check_pow_none; 2525 pcc->check_attn = check_attn_none; 2526 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2527 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2528 PPC_CACHE_ICBI | PPC_MFTB; 2529 pcc->msr_mask = (1ull << MSR_ILE) | 2530 (1ull << MSR_EE) | 2531 (1ull << MSR_PR) | 2532 (1ull << MSR_FP) | 2533 (1ull << MSR_ME) | 2534 (1ull << MSR_SE) | 2535 (1ull << MSR_DE) | 2536 (1ull << MSR_EP) | 2537 (1ull << MSR_IR) | 2538 (1ull << MSR_DR) | 2539 (1ull << MSR_RI) | 2540 (1ull << MSR_LE); 2541 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2542 pcc->excp_model = POWERPC_EXCP_6xx; 2543 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2544 pcc->bfd_mach = bfd_mach_ppc_860; 2545 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2546 POWERPC_FLAG_BUS_CLK; 2547 } 2548 2549 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2550 2551 static void init_proc_G2(CPUPPCState *env) 2552 { 2553 register_non_embedded_sprs(env); 2554 register_sdr1_sprs(env); 2555 register_G2_sprs(env); 2556 2557 /* Memory management */ 2558 register_low_BATs(env); 2559 register_high_BATs(env); 2560 register_6xx_7xx_soft_tlb(env, 64, 2); 2561 init_excp_G2(env); 2562 env->dcache_line_size = 32; 2563 env->icache_line_size = 32; 2564 /* Allocate hardware IRQ controller */ 2565 ppc6xx_irq_init(env_archcpu(env)); 2566 } 2567 2568 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2569 { 2570 DeviceClass *dc = DEVICE_CLASS(oc); 2571 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2572 2573 dc->desc = "PowerPC G2"; 2574 pcc->init_proc = init_proc_G2; 2575 pcc->check_pow = check_pow_hid0; 2576 pcc->check_attn = check_attn_none; 2577 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2579 PPC_FLOAT_STFIWX | 2580 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2581 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2582 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2583 PPC_SEGMENT | PPC_EXTERN; 2584 pcc->msr_mask = (1ull << MSR_POW) | 2585 (1ull << MSR_TGPR) | 2586 (1ull << MSR_EE) | 2587 (1ull << MSR_PR) | 2588 (1ull << MSR_FP) | 2589 (1ull << MSR_ME) | 2590 (1ull << MSR_FE0) | 2591 (1ull << MSR_SE) | 2592 (1ull << MSR_DE) | 2593 (1ull << MSR_FE1) | 2594 (1ull << MSR_AL) | 2595 (1ull << MSR_EP) | 2596 (1ull << MSR_IR) | 2597 (1ull << MSR_DR) | 2598 (1ull << MSR_RI); 2599 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2600 pcc->excp_model = POWERPC_EXCP_6xx; 2601 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2602 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2603 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2604 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2605 } 2606 2607 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2608 { 2609 DeviceClass *dc = DEVICE_CLASS(oc); 2610 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2611 2612 dc->desc = "PowerPC G2LE"; 2613 pcc->init_proc = init_proc_G2; 2614 pcc->check_pow = check_pow_hid0; 2615 pcc->check_attn = check_attn_none; 2616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2617 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2618 PPC_FLOAT_STFIWX | 2619 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2620 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2621 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2622 PPC_SEGMENT | PPC_EXTERN; 2623 pcc->msr_mask = (1ull << MSR_POW) | 2624 (1ull << MSR_TGPR) | 2625 (1ull << MSR_ILE) | 2626 (1ull << MSR_EE) | 2627 (1ull << MSR_PR) | 2628 (1ull << MSR_FP) | 2629 (1ull << MSR_ME) | 2630 (1ull << MSR_FE0) | 2631 (1ull << MSR_SE) | 2632 (1ull << MSR_DE) | 2633 (1ull << MSR_FE1) | 2634 (1ull << MSR_AL) | 2635 (1ull << MSR_EP) | 2636 (1ull << MSR_IR) | 2637 (1ull << MSR_DR) | 2638 (1ull << MSR_RI) | 2639 (1ull << MSR_LE); 2640 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2641 pcc->excp_model = POWERPC_EXCP_6xx; 2642 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2643 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2644 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2645 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2646 } 2647 2648 static void init_proc_e200(CPUPPCState *env) 2649 { 2650 register_BookE_sprs(env, 0x000000070000FFFFULL); 2651 2652 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2653 &spr_read_spefscr, &spr_write_spefscr, 2654 &spr_read_spefscr, &spr_write_spefscr, 2655 0x00000000); 2656 /* Memory management */ 2657 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2658 register_usprgh_sprs(env); 2659 2660 spr_register(env, SPR_HID0, "HID0", 2661 SPR_NOACCESS, SPR_NOACCESS, 2662 &spr_read_generic, &spr_write_generic, 2663 0x00000000); 2664 2665 spr_register(env, SPR_HID1, "HID1", 2666 SPR_NOACCESS, SPR_NOACCESS, 2667 &spr_read_generic, &spr_write_generic, 2668 0x00000000); 2669 2670 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2671 SPR_NOACCESS, SPR_NOACCESS, 2672 &spr_read_generic, &spr_write_generic, 2673 0x00000000); 2674 2675 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2676 SPR_NOACCESS, SPR_NOACCESS, 2677 &spr_read_generic, &spr_write_generic, 2678 0x00000000); 2679 2680 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2681 SPR_NOACCESS, SPR_NOACCESS, 2682 &spr_read_generic, &spr_write_generic, 2683 0x00000000); 2684 2685 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2686 SPR_NOACCESS, SPR_NOACCESS, 2687 &spr_read_generic, &spr_write_generic, 2688 0x00000000); 2689 2690 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2691 SPR_NOACCESS, SPR_NOACCESS, 2692 &spr_read_generic, &spr_write_generic, 2693 0x00000000); 2694 2695 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2696 &spr_read_generic, SPR_NOACCESS, 2697 &spr_read_generic, SPR_NOACCESS, 2698 0x00000000); 2699 2700 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2701 SPR_NOACCESS, SPR_NOACCESS, 2702 &spr_read_generic, &spr_write_generic, 2703 0x00000000); 2704 2705 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2706 SPR_NOACCESS, SPR_NOACCESS, 2707 &spr_read_generic, &spr_write_generic, 2708 0x00000000); 2709 2710 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2711 SPR_NOACCESS, SPR_NOACCESS, 2712 &spr_read_generic, &spr_write_generic, 2713 0x00000000); 2714 2715 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2716 SPR_NOACCESS, SPR_NOACCESS, 2717 &spr_read_generic, &spr_write_generic, 2718 0x00000000); 2719 2720 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2721 SPR_NOACCESS, SPR_NOACCESS, 2722 &spr_read_generic, &spr_write_generic, 2723 0x00000000); 2724 2725 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2726 SPR_NOACCESS, SPR_NOACCESS, 2727 &spr_read_generic, &spr_write_generic, 2728 0x00000000); 2729 2730 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2731 SPR_NOACCESS, SPR_NOACCESS, 2732 &spr_read_generic, &spr_write_generic, 2733 0x00000000); /* TOFIX */ 2734 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2735 SPR_NOACCESS, SPR_NOACCESS, 2736 &spr_read_generic, &spr_write_generic, 2737 0x00000000); 2738 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2739 SPR_NOACCESS, SPR_NOACCESS, 2740 &spr_read_generic, &spr_write_generic, 2741 0x00000000); 2742 2743 init_tlbs_emb(env); 2744 init_excp_e200(env, 0xFFFF0000UL); 2745 env->dcache_line_size = 32; 2746 env->icache_line_size = 32; 2747 /* XXX: TODO: allocate internal IRQ controller */ 2748 } 2749 2750 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2751 { 2752 DeviceClass *dc = DEVICE_CLASS(oc); 2753 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2754 2755 dc->desc = "e200 core"; 2756 pcc->init_proc = init_proc_e200; 2757 pcc->check_pow = check_pow_hid0; 2758 pcc->check_attn = check_attn_none; 2759 /* 2760 * XXX: unimplemented instructions: 2761 * dcblc 2762 * dcbtlst 2763 * dcbtstls 2764 * icblc 2765 * icbtls 2766 * tlbivax 2767 * all SPE multiply-accumulate instructions 2768 */ 2769 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2770 PPC_SPE | PPC_SPE_SINGLE | 2771 PPC_WRTEE | PPC_RFDI | 2772 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2773 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2774 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2775 PPC_BOOKE; 2776 pcc->msr_mask = (1ull << MSR_UCLE) | 2777 (1ull << MSR_SPE) | 2778 (1ull << MSR_POW) | 2779 (1ull << MSR_CE) | 2780 (1ull << MSR_EE) | 2781 (1ull << MSR_PR) | 2782 (1ull << MSR_FP) | 2783 (1ull << MSR_ME) | 2784 (1ull << MSR_FE0) | 2785 (1ull << MSR_DWE) | 2786 (1ull << MSR_DE) | 2787 (1ull << MSR_FE1) | 2788 (1ull << MSR_IR) | 2789 (1ull << MSR_DR); 2790 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2791 pcc->excp_model = POWERPC_EXCP_BOOKE; 2792 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2793 pcc->bfd_mach = bfd_mach_ppc_860; 2794 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2795 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2796 POWERPC_FLAG_BUS_CLK; 2797 } 2798 2799 enum fsl_e500_version { 2800 fsl_e500v1, 2801 fsl_e500v2, 2802 fsl_e500mc, 2803 fsl_e5500, 2804 fsl_e6500, 2805 }; 2806 2807 static void init_proc_e500(CPUPPCState *env, int version) 2808 { 2809 uint32_t tlbncfg[2]; 2810 uint64_t ivor_mask; 2811 uint64_t ivpr_mask = 0xFFFF0000ULL; 2812 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2813 | 0x0020; /* 32 kb */ 2814 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2815 | 0x0020; /* 32 kb */ 2816 uint32_t mmucfg = 0; 2817 #if !defined(CONFIG_USER_ONLY) 2818 int i; 2819 #endif 2820 2821 /* 2822 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2823 * complain when accessing them. 2824 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2825 */ 2826 switch (version) { 2827 case fsl_e500v1: 2828 case fsl_e500v2: 2829 default: 2830 ivor_mask = 0x0000000F0000FFFFULL; 2831 break; 2832 case fsl_e500mc: 2833 case fsl_e5500: 2834 ivor_mask = 0x000003FE0000FFFFULL; 2835 break; 2836 case fsl_e6500: 2837 ivor_mask = 0x000003FF0000FFFFULL; 2838 break; 2839 } 2840 register_BookE_sprs(env, ivor_mask); 2841 2842 spr_register(env, SPR_USPRG3, "USPRG3", 2843 &spr_read_ureg, SPR_NOACCESS, 2844 &spr_read_ureg, SPR_NOACCESS, 2845 0x00000000); 2846 2847 /* Processor identification */ 2848 spr_register(env, SPR_BOOKE_PIR, "PIR", 2849 SPR_NOACCESS, SPR_NOACCESS, 2850 &spr_read_generic, &spr_write_pir, 2851 0x00000000); 2852 2853 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2854 &spr_read_spefscr, &spr_write_spefscr, 2855 &spr_read_spefscr, &spr_write_spefscr, 2856 0x00000000); 2857 #if !defined(CONFIG_USER_ONLY) 2858 /* Memory management */ 2859 env->nb_pids = 3; 2860 env->nb_ways = 2; 2861 switch (version) { 2862 case fsl_e500v1: 2863 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2864 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2865 break; 2866 case fsl_e500v2: 2867 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2868 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2869 break; 2870 case fsl_e500mc: 2871 case fsl_e5500: 2872 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2873 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2874 break; 2875 case fsl_e6500: 2876 mmucfg = 0x6510B45; 2877 env->nb_pids = 1; 2878 tlbncfg[0] = 0x08052400; 2879 tlbncfg[1] = 0x40028040; 2880 break; 2881 default: 2882 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2883 env->spr[SPR_PVR]); 2884 } 2885 #endif 2886 /* Cache sizes */ 2887 switch (version) { 2888 case fsl_e500v1: 2889 case fsl_e500v2: 2890 env->dcache_line_size = 32; 2891 env->icache_line_size = 32; 2892 break; 2893 case fsl_e500mc: 2894 case fsl_e5500: 2895 env->dcache_line_size = 64; 2896 env->icache_line_size = 64; 2897 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2898 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2899 break; 2900 case fsl_e6500: 2901 env->dcache_line_size = 32; 2902 env->icache_line_size = 32; 2903 l1cfg0 |= 0x0F83820; 2904 l1cfg1 |= 0x0B83820; 2905 break; 2906 default: 2907 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2908 env->spr[SPR_PVR]); 2909 } 2910 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2911 register_usprgh_sprs(env); 2912 2913 spr_register(env, SPR_HID0, "HID0", 2914 SPR_NOACCESS, SPR_NOACCESS, 2915 &spr_read_generic, &spr_write_generic, 2916 0x00000000); 2917 2918 spr_register(env, SPR_HID1, "HID1", 2919 SPR_NOACCESS, SPR_NOACCESS, 2920 &spr_read_generic, &spr_write_generic, 2921 0x00000000); 2922 2923 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2924 SPR_NOACCESS, SPR_NOACCESS, 2925 &spr_read_generic, &spr_write_generic, 2926 0x00000000); 2927 2928 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2929 SPR_NOACCESS, SPR_NOACCESS, 2930 &spr_read_generic, &spr_write_generic, 2931 0x00000000); 2932 2933 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2934 SPR_NOACCESS, SPR_NOACCESS, 2935 &spr_read_generic, &spr_write_generic, 2936 0x00000000); 2937 2938 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2939 SPR_NOACCESS, SPR_NOACCESS, 2940 &spr_read_generic, &spr_write_generic, 2941 0x00000000); 2942 2943 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2944 SPR_NOACCESS, SPR_NOACCESS, 2945 &spr_read_generic, &spr_write_generic, 2946 0x00000000); 2947 2948 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2949 SPR_NOACCESS, SPR_NOACCESS, 2950 &spr_read_generic, &spr_write_generic, 2951 0x00000000); 2952 2953 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2954 &spr_read_generic, SPR_NOACCESS, 2955 &spr_read_generic, SPR_NOACCESS, 2956 l1cfg0); 2957 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2958 &spr_read_generic, SPR_NOACCESS, 2959 &spr_read_generic, SPR_NOACCESS, 2960 l1cfg1); 2961 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2962 SPR_NOACCESS, SPR_NOACCESS, 2963 &spr_read_generic, &spr_write_e500_l1csr0, 2964 0x00000000); 2965 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2966 SPR_NOACCESS, SPR_NOACCESS, 2967 &spr_read_generic, &spr_write_e500_l1csr1, 2968 0x00000000); 2969 if (version != fsl_e500v1 && version != fsl_e500v2) { 2970 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2971 SPR_NOACCESS, SPR_NOACCESS, 2972 &spr_read_generic, &spr_write_e500_l2csr0, 2973 0x00000000); 2974 } 2975 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2976 SPR_NOACCESS, SPR_NOACCESS, 2977 &spr_read_generic, &spr_write_generic, 2978 0x00000000); 2979 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2980 SPR_NOACCESS, SPR_NOACCESS, 2981 &spr_read_generic, &spr_write_generic, 2982 0x00000000); 2983 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2984 SPR_NOACCESS, SPR_NOACCESS, 2985 &spr_read_generic, &spr_write_booke206_mmucsr0, 2986 0x00000000); 2987 spr_register(env, SPR_BOOKE_EPR, "EPR", 2988 SPR_NOACCESS, SPR_NOACCESS, 2989 &spr_read_generic, SPR_NOACCESS, 2990 0x00000000); 2991 /* XXX better abstract into Emb.xxx features */ 2992 if ((version == fsl_e5500) || (version == fsl_e6500)) { 2993 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 2994 SPR_NOACCESS, SPR_NOACCESS, 2995 &spr_read_generic, &spr_write_generic, 2996 0x00000000); 2997 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 2998 SPR_NOACCESS, SPR_NOACCESS, 2999 &spr_read_mas73, &spr_write_mas73, 3000 0x00000000); 3001 ivpr_mask = (target_ulong)~0xFFFFULL; 3002 } 3003 3004 if (version == fsl_e6500) { 3005 /* Thread identification */ 3006 spr_register(env, SPR_TIR, "TIR", 3007 SPR_NOACCESS, SPR_NOACCESS, 3008 &spr_read_generic, SPR_NOACCESS, 3009 0x00000000); 3010 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3011 SPR_NOACCESS, SPR_NOACCESS, 3012 &spr_read_generic, SPR_NOACCESS, 3013 0x00000004); 3014 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3015 SPR_NOACCESS, SPR_NOACCESS, 3016 &spr_read_generic, SPR_NOACCESS, 3017 0x7FFFFFFC); 3018 } 3019 3020 #if !defined(CONFIG_USER_ONLY) 3021 env->nb_tlb = 0; 3022 env->tlb_type = TLB_MAS; 3023 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3024 env->nb_tlb += booke206_tlb_size(env, i); 3025 } 3026 #endif 3027 3028 init_excp_e200(env, ivpr_mask); 3029 /* Allocate hardware IRQ controller */ 3030 ppce500_irq_init(env_archcpu(env)); 3031 } 3032 3033 static void init_proc_e500v1(CPUPPCState *env) 3034 { 3035 init_proc_e500(env, fsl_e500v1); 3036 } 3037 3038 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3039 { 3040 DeviceClass *dc = DEVICE_CLASS(oc); 3041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3042 3043 dc->desc = "e500v1 core"; 3044 pcc->init_proc = init_proc_e500v1; 3045 pcc->check_pow = check_pow_hid0; 3046 pcc->check_attn = check_attn_none; 3047 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3048 PPC_SPE | PPC_SPE_SINGLE | 3049 PPC_WRTEE | PPC_RFDI | 3050 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3051 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3052 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3053 pcc->insns_flags2 = PPC2_BOOKE206; 3054 pcc->msr_mask = (1ull << MSR_UCLE) | 3055 (1ull << MSR_SPE) | 3056 (1ull << MSR_POW) | 3057 (1ull << MSR_CE) | 3058 (1ull << MSR_EE) | 3059 (1ull << MSR_PR) | 3060 (1ull << MSR_FP) | 3061 (1ull << MSR_ME) | 3062 (1ull << MSR_FE0) | 3063 (1ull << MSR_DWE) | 3064 (1ull << MSR_DE) | 3065 (1ull << MSR_FE1) | 3066 (1ull << MSR_IR) | 3067 (1ull << MSR_DR); 3068 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3069 pcc->excp_model = POWERPC_EXCP_BOOKE; 3070 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3071 pcc->bfd_mach = bfd_mach_ppc_860; 3072 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3073 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3074 POWERPC_FLAG_BUS_CLK; 3075 } 3076 3077 static void init_proc_e500v2(CPUPPCState *env) 3078 { 3079 init_proc_e500(env, fsl_e500v2); 3080 } 3081 3082 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3083 { 3084 DeviceClass *dc = DEVICE_CLASS(oc); 3085 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3086 3087 dc->desc = "e500v2 core"; 3088 pcc->init_proc = init_proc_e500v2; 3089 pcc->check_pow = check_pow_hid0; 3090 pcc->check_attn = check_attn_none; 3091 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3092 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3093 PPC_WRTEE | PPC_RFDI | 3094 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3095 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3096 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3097 pcc->insns_flags2 = PPC2_BOOKE206; 3098 pcc->msr_mask = (1ull << MSR_UCLE) | 3099 (1ull << MSR_SPE) | 3100 (1ull << MSR_POW) | 3101 (1ull << MSR_CE) | 3102 (1ull << MSR_EE) | 3103 (1ull << MSR_PR) | 3104 (1ull << MSR_FP) | 3105 (1ull << MSR_ME) | 3106 (1ull << MSR_FE0) | 3107 (1ull << MSR_DWE) | 3108 (1ull << MSR_DE) | 3109 (1ull << MSR_FE1) | 3110 (1ull << MSR_IR) | 3111 (1ull << MSR_DR); 3112 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3113 pcc->excp_model = POWERPC_EXCP_BOOKE; 3114 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3115 pcc->bfd_mach = bfd_mach_ppc_860; 3116 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3117 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3118 POWERPC_FLAG_BUS_CLK; 3119 } 3120 3121 static void init_proc_e500mc(CPUPPCState *env) 3122 { 3123 init_proc_e500(env, fsl_e500mc); 3124 } 3125 3126 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3127 { 3128 DeviceClass *dc = DEVICE_CLASS(oc); 3129 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3130 3131 dc->desc = "e500mc core"; 3132 pcc->init_proc = init_proc_e500mc; 3133 pcc->check_pow = check_pow_none; 3134 pcc->check_attn = check_attn_none; 3135 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3136 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3137 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3138 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3139 PPC_FLOAT | PPC_FLOAT_FRES | 3140 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3141 PPC_FLOAT_STFIWX | PPC_WAIT | 3142 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3143 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3144 pcc->msr_mask = (1ull << MSR_GS) | 3145 (1ull << MSR_UCLE) | 3146 (1ull << MSR_CE) | 3147 (1ull << MSR_EE) | 3148 (1ull << MSR_PR) | 3149 (1ull << MSR_FP) | 3150 (1ull << MSR_ME) | 3151 (1ull << MSR_FE0) | 3152 (1ull << MSR_DE) | 3153 (1ull << MSR_FE1) | 3154 (1ull << MSR_IR) | 3155 (1ull << MSR_DR) | 3156 (1ull << MSR_PX) | 3157 (1ull << MSR_RI); 3158 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3159 pcc->excp_model = POWERPC_EXCP_BOOKE; 3160 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3161 /* FIXME: figure out the correct flag for e500mc */ 3162 pcc->bfd_mach = bfd_mach_ppc_e500; 3163 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3164 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3165 } 3166 3167 #ifdef TARGET_PPC64 3168 static void init_proc_e5500(CPUPPCState *env) 3169 { 3170 init_proc_e500(env, fsl_e5500); 3171 } 3172 3173 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3174 { 3175 DeviceClass *dc = DEVICE_CLASS(oc); 3176 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3177 3178 dc->desc = "e5500 core"; 3179 pcc->init_proc = init_proc_e5500; 3180 pcc->check_pow = check_pow_none; 3181 pcc->check_attn = check_attn_none; 3182 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3183 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3184 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3185 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3186 PPC_FLOAT | PPC_FLOAT_FRES | 3187 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3188 PPC_FLOAT_STFIWX | PPC_WAIT | 3189 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3190 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3191 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3192 PPC2_FP_CVT_S64; 3193 pcc->msr_mask = (1ull << MSR_CM) | 3194 (1ull << MSR_GS) | 3195 (1ull << MSR_UCLE) | 3196 (1ull << MSR_CE) | 3197 (1ull << MSR_EE) | 3198 (1ull << MSR_PR) | 3199 (1ull << MSR_FP) | 3200 (1ull << MSR_ME) | 3201 (1ull << MSR_FE0) | 3202 (1ull << MSR_DE) | 3203 (1ull << MSR_FE1) | 3204 (1ull << MSR_IR) | 3205 (1ull << MSR_DR) | 3206 (1ull << MSR_PX) | 3207 (1ull << MSR_RI); 3208 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3209 pcc->excp_model = POWERPC_EXCP_BOOKE; 3210 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3211 /* FIXME: figure out the correct flag for e5500 */ 3212 pcc->bfd_mach = bfd_mach_ppc_e500; 3213 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3214 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3215 } 3216 3217 static void init_proc_e6500(CPUPPCState *env) 3218 { 3219 init_proc_e500(env, fsl_e6500); 3220 } 3221 3222 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3223 { 3224 DeviceClass *dc = DEVICE_CLASS(oc); 3225 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3226 3227 dc->desc = "e6500 core"; 3228 pcc->init_proc = init_proc_e6500; 3229 pcc->check_pow = check_pow_none; 3230 pcc->check_attn = check_attn_none; 3231 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3232 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3233 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3234 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3235 PPC_FLOAT | PPC_FLOAT_FRES | 3236 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3237 PPC_FLOAT_STFIWX | PPC_WAIT | 3238 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3239 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3240 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3241 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3242 pcc->msr_mask = (1ull << MSR_CM) | 3243 (1ull << MSR_GS) | 3244 (1ull << MSR_UCLE) | 3245 (1ull << MSR_CE) | 3246 (1ull << MSR_EE) | 3247 (1ull << MSR_PR) | 3248 (1ull << MSR_FP) | 3249 (1ull << MSR_ME) | 3250 (1ull << MSR_FE0) | 3251 (1ull << MSR_DE) | 3252 (1ull << MSR_FE1) | 3253 (1ull << MSR_IS) | 3254 (1ull << MSR_DS) | 3255 (1ull << MSR_PX) | 3256 (1ull << MSR_RI) | 3257 (1ull << MSR_VR); 3258 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3259 pcc->excp_model = POWERPC_EXCP_BOOKE; 3260 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3261 pcc->bfd_mach = bfd_mach_ppc_e500; 3262 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3263 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3264 } 3265 3266 #endif 3267 3268 /* Non-embedded PowerPC */ 3269 static void init_proc_603(CPUPPCState *env) 3270 { 3271 register_non_embedded_sprs(env); 3272 register_sdr1_sprs(env); 3273 register_603_sprs(env); 3274 3275 /* Memory management */ 3276 register_low_BATs(env); 3277 register_6xx_7xx_soft_tlb(env, 64, 2); 3278 init_excp_603(env); 3279 env->dcache_line_size = 32; 3280 env->icache_line_size = 32; 3281 /* Allocate hardware IRQ controller */ 3282 ppc6xx_irq_init(env_archcpu(env)); 3283 } 3284 3285 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3286 { 3287 DeviceClass *dc = DEVICE_CLASS(oc); 3288 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3289 3290 dc->desc = "PowerPC 603"; 3291 pcc->init_proc = init_proc_603; 3292 pcc->check_pow = check_pow_hid0; 3293 pcc->check_attn = check_attn_none; 3294 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3295 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3296 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3297 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3298 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3299 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3300 PPC_SEGMENT | PPC_EXTERN; 3301 pcc->msr_mask = (1ull << MSR_POW) | 3302 (1ull << MSR_TGPR) | 3303 (1ull << MSR_ILE) | 3304 (1ull << MSR_EE) | 3305 (1ull << MSR_PR) | 3306 (1ull << MSR_FP) | 3307 (1ull << MSR_ME) | 3308 (1ull << MSR_FE0) | 3309 (1ull << MSR_SE) | 3310 (1ull << MSR_DE) | 3311 (1ull << MSR_FE1) | 3312 (1ull << MSR_EP) | 3313 (1ull << MSR_IR) | 3314 (1ull << MSR_DR) | 3315 (1ull << MSR_RI) | 3316 (1ull << MSR_LE); 3317 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3318 pcc->excp_model = POWERPC_EXCP_6xx; 3319 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3320 pcc->bfd_mach = bfd_mach_ppc_603; 3321 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3322 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3323 } 3324 3325 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3326 { 3327 DeviceClass *dc = DEVICE_CLASS(oc); 3328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3329 3330 dc->desc = "PowerPC 603e"; 3331 pcc->init_proc = init_proc_603; 3332 pcc->check_pow = check_pow_hid0; 3333 pcc->check_attn = check_attn_none; 3334 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3335 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3336 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3337 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3338 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3339 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3340 PPC_SEGMENT | PPC_EXTERN; 3341 pcc->msr_mask = (1ull << MSR_POW) | 3342 (1ull << MSR_TGPR) | 3343 (1ull << MSR_ILE) | 3344 (1ull << MSR_EE) | 3345 (1ull << MSR_PR) | 3346 (1ull << MSR_FP) | 3347 (1ull << MSR_ME) | 3348 (1ull << MSR_FE0) | 3349 (1ull << MSR_SE) | 3350 (1ull << MSR_DE) | 3351 (1ull << MSR_FE1) | 3352 (1ull << MSR_EP) | 3353 (1ull << MSR_IR) | 3354 (1ull << MSR_DR) | 3355 (1ull << MSR_RI) | 3356 (1ull << MSR_LE); 3357 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3358 pcc->excp_model = POWERPC_EXCP_6xx; 3359 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3360 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3361 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3362 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3363 } 3364 3365 static void init_proc_e300(CPUPPCState *env) 3366 { 3367 init_proc_603(env); 3368 register_e300_sprs(env); 3369 } 3370 3371 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3372 { 3373 DeviceClass *dc = DEVICE_CLASS(oc); 3374 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3375 3376 dc->desc = "e300 core"; 3377 pcc->init_proc = init_proc_e300; 3378 pcc->check_pow = check_pow_hid0; 3379 pcc->check_attn = check_attn_none; 3380 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3382 PPC_FLOAT_STFIWX | 3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3384 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3386 PPC_SEGMENT | PPC_EXTERN; 3387 pcc->msr_mask = (1ull << MSR_POW) | 3388 (1ull << MSR_TGPR) | 3389 (1ull << MSR_ILE) | 3390 (1ull << MSR_EE) | 3391 (1ull << MSR_PR) | 3392 (1ull << MSR_FP) | 3393 (1ull << MSR_ME) | 3394 (1ull << MSR_FE0) | 3395 (1ull << MSR_SE) | 3396 (1ull << MSR_DE) | 3397 (1ull << MSR_FE1) | 3398 (1ull << MSR_AL) | 3399 (1ull << MSR_EP) | 3400 (1ull << MSR_IR) | 3401 (1ull << MSR_DR) | 3402 (1ull << MSR_RI) | 3403 (1ull << MSR_LE); 3404 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3405 pcc->excp_model = POWERPC_EXCP_6xx; 3406 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3407 pcc->bfd_mach = bfd_mach_ppc_603; 3408 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3409 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3410 } 3411 3412 static void init_proc_604(CPUPPCState *env) 3413 { 3414 register_non_embedded_sprs(env); 3415 register_sdr1_sprs(env); 3416 register_604_sprs(env); 3417 3418 /* Memory management */ 3419 register_low_BATs(env); 3420 init_excp_604(env); 3421 env->dcache_line_size = 32; 3422 env->icache_line_size = 32; 3423 /* Allocate hardware IRQ controller */ 3424 ppc6xx_irq_init(env_archcpu(env)); 3425 } 3426 3427 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3428 { 3429 DeviceClass *dc = DEVICE_CLASS(oc); 3430 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3431 3432 dc->desc = "PowerPC 604"; 3433 pcc->init_proc = init_proc_604; 3434 pcc->check_pow = check_pow_nocheck; 3435 pcc->check_attn = check_attn_none; 3436 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3437 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3438 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3439 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3440 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3441 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3442 PPC_SEGMENT | PPC_EXTERN; 3443 pcc->msr_mask = (1ull << MSR_POW) | 3444 (1ull << MSR_ILE) | 3445 (1ull << MSR_EE) | 3446 (1ull << MSR_PR) | 3447 (1ull << MSR_FP) | 3448 (1ull << MSR_ME) | 3449 (1ull << MSR_FE0) | 3450 (1ull << MSR_SE) | 3451 (1ull << MSR_DE) | 3452 (1ull << MSR_FE1) | 3453 (1ull << MSR_EP) | 3454 (1ull << MSR_IR) | 3455 (1ull << MSR_DR) | 3456 (1ull << MSR_PMM) | 3457 (1ull << MSR_RI) | 3458 (1ull << MSR_LE); 3459 pcc->mmu_model = POWERPC_MMU_32B; 3460 pcc->excp_model = POWERPC_EXCP_6xx; 3461 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3462 pcc->bfd_mach = bfd_mach_ppc_604; 3463 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3464 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3465 } 3466 3467 static void init_proc_604E(CPUPPCState *env) 3468 { 3469 init_proc_604(env); 3470 register_604e_sprs(env); 3471 } 3472 3473 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3474 { 3475 DeviceClass *dc = DEVICE_CLASS(oc); 3476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3477 3478 dc->desc = "PowerPC 604E"; 3479 pcc->init_proc = init_proc_604E; 3480 pcc->check_pow = check_pow_nocheck; 3481 pcc->check_attn = check_attn_none; 3482 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3483 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3484 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3485 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3486 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3487 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3488 PPC_SEGMENT | PPC_EXTERN; 3489 pcc->msr_mask = (1ull << MSR_POW) | 3490 (1ull << MSR_ILE) | 3491 (1ull << MSR_EE) | 3492 (1ull << MSR_PR) | 3493 (1ull << MSR_FP) | 3494 (1ull << MSR_ME) | 3495 (1ull << MSR_FE0) | 3496 (1ull << MSR_SE) | 3497 (1ull << MSR_DE) | 3498 (1ull << MSR_FE1) | 3499 (1ull << MSR_EP) | 3500 (1ull << MSR_IR) | 3501 (1ull << MSR_DR) | 3502 (1ull << MSR_PMM) | 3503 (1ull << MSR_RI) | 3504 (1ull << MSR_LE); 3505 pcc->mmu_model = POWERPC_MMU_32B; 3506 pcc->excp_model = POWERPC_EXCP_6xx; 3507 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3508 pcc->bfd_mach = bfd_mach_ppc_604; 3509 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3510 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3511 } 3512 3513 static void init_proc_740(CPUPPCState *env) 3514 { 3515 register_non_embedded_sprs(env); 3516 register_sdr1_sprs(env); 3517 register_7xx_sprs(env); 3518 /* Thermal management */ 3519 register_thrm_sprs(env); 3520 3521 /* Memory management */ 3522 register_low_BATs(env); 3523 init_excp_7x0(env); 3524 env->dcache_line_size = 32; 3525 env->icache_line_size = 32; 3526 /* Allocate hardware IRQ controller */ 3527 ppc6xx_irq_init(env_archcpu(env)); 3528 } 3529 3530 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3531 { 3532 DeviceClass *dc = DEVICE_CLASS(oc); 3533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3534 3535 dc->desc = "PowerPC 740"; 3536 pcc->init_proc = init_proc_740; 3537 pcc->check_pow = check_pow_hid0; 3538 pcc->check_attn = check_attn_none; 3539 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3540 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3541 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3542 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3543 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3544 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3545 PPC_SEGMENT | PPC_EXTERN; 3546 pcc->msr_mask = (1ull << MSR_POW) | 3547 (1ull << MSR_ILE) | 3548 (1ull << MSR_EE) | 3549 (1ull << MSR_PR) | 3550 (1ull << MSR_FP) | 3551 (1ull << MSR_ME) | 3552 (1ull << MSR_FE0) | 3553 (1ull << MSR_SE) | 3554 (1ull << MSR_DE) | 3555 (1ull << MSR_FE1) | 3556 (1ull << MSR_EP) | 3557 (1ull << MSR_IR) | 3558 (1ull << MSR_DR) | 3559 (1ull << MSR_PMM) | 3560 (1ull << MSR_RI) | 3561 (1ull << MSR_LE); 3562 pcc->mmu_model = POWERPC_MMU_32B; 3563 pcc->excp_model = POWERPC_EXCP_7xx; 3564 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3565 pcc->bfd_mach = bfd_mach_ppc_750; 3566 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3567 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3568 } 3569 3570 static void init_proc_750(CPUPPCState *env) 3571 { 3572 register_non_embedded_sprs(env); 3573 register_sdr1_sprs(env); 3574 register_7xx_sprs(env); 3575 3576 spr_register(env, SPR_L2CR, "L2CR", 3577 SPR_NOACCESS, SPR_NOACCESS, 3578 &spr_read_generic, spr_access_nop, 3579 0x00000000); 3580 /* Thermal management */ 3581 register_thrm_sprs(env); 3582 3583 /* Memory management */ 3584 register_low_BATs(env); 3585 /* 3586 * XXX: high BATs are also present but are known to be bugged on 3587 * die version 1.x 3588 */ 3589 init_excp_7x0(env); 3590 env->dcache_line_size = 32; 3591 env->icache_line_size = 32; 3592 /* Allocate hardware IRQ controller */ 3593 ppc6xx_irq_init(env_archcpu(env)); 3594 } 3595 3596 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3597 { 3598 DeviceClass *dc = DEVICE_CLASS(oc); 3599 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3600 3601 dc->desc = "PowerPC 750"; 3602 pcc->init_proc = init_proc_750; 3603 pcc->check_pow = check_pow_hid0; 3604 pcc->check_attn = check_attn_none; 3605 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3606 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3607 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3608 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3609 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3610 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3611 PPC_SEGMENT | PPC_EXTERN; 3612 pcc->msr_mask = (1ull << MSR_POW) | 3613 (1ull << MSR_ILE) | 3614 (1ull << MSR_EE) | 3615 (1ull << MSR_PR) | 3616 (1ull << MSR_FP) | 3617 (1ull << MSR_ME) | 3618 (1ull << MSR_FE0) | 3619 (1ull << MSR_SE) | 3620 (1ull << MSR_DE) | 3621 (1ull << MSR_FE1) | 3622 (1ull << MSR_EP) | 3623 (1ull << MSR_IR) | 3624 (1ull << MSR_DR) | 3625 (1ull << MSR_PMM) | 3626 (1ull << MSR_RI) | 3627 (1ull << MSR_LE); 3628 pcc->mmu_model = POWERPC_MMU_32B; 3629 pcc->excp_model = POWERPC_EXCP_7xx; 3630 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3631 pcc->bfd_mach = bfd_mach_ppc_750; 3632 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3633 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3634 } 3635 3636 static void init_proc_750cl(CPUPPCState *env) 3637 { 3638 register_non_embedded_sprs(env); 3639 register_sdr1_sprs(env); 3640 register_7xx_sprs(env); 3641 3642 spr_register(env, SPR_L2CR, "L2CR", 3643 SPR_NOACCESS, SPR_NOACCESS, 3644 &spr_read_generic, spr_access_nop, 3645 0x00000000); 3646 /* Thermal management */ 3647 /* Those registers are fake on 750CL */ 3648 spr_register(env, SPR_THRM1, "THRM1", 3649 SPR_NOACCESS, SPR_NOACCESS, 3650 &spr_read_generic, &spr_write_generic, 3651 0x00000000); 3652 spr_register(env, SPR_THRM2, "THRM2", 3653 SPR_NOACCESS, SPR_NOACCESS, 3654 &spr_read_generic, &spr_write_generic, 3655 0x00000000); 3656 spr_register(env, SPR_THRM3, "THRM3", 3657 SPR_NOACCESS, SPR_NOACCESS, 3658 &spr_read_generic, &spr_write_generic, 3659 0x00000000); 3660 3661 spr_register(env, SPR_750_TDCL, "TDCL", 3662 SPR_NOACCESS, SPR_NOACCESS, 3663 &spr_read_generic, &spr_write_generic, 3664 0x00000000); 3665 spr_register(env, SPR_750_TDCH, "TDCH", 3666 SPR_NOACCESS, SPR_NOACCESS, 3667 &spr_read_generic, &spr_write_generic, 3668 0x00000000); 3669 /* DMA */ 3670 spr_register(env, SPR_750_WPAR, "WPAR", 3671 SPR_NOACCESS, SPR_NOACCESS, 3672 &spr_read_generic, &spr_write_generic, 3673 0x00000000); 3674 spr_register(env, SPR_750_DMAL, "DMAL", 3675 SPR_NOACCESS, SPR_NOACCESS, 3676 &spr_read_generic, &spr_write_generic, 3677 0x00000000); 3678 spr_register(env, SPR_750_DMAU, "DMAU", 3679 SPR_NOACCESS, SPR_NOACCESS, 3680 &spr_read_generic, &spr_write_generic, 3681 0x00000000); 3682 /* Hardware implementation registers */ 3683 spr_register(env, SPR_750CL_HID2, "HID2", 3684 SPR_NOACCESS, SPR_NOACCESS, 3685 &spr_read_generic, &spr_write_generic, 3686 0x00000000); 3687 3688 spr_register(env, SPR_750CL_HID4, "HID4", 3689 SPR_NOACCESS, SPR_NOACCESS, 3690 &spr_read_generic, &spr_write_generic, 3691 0x00000000); 3692 /* Quantization registers */ 3693 spr_register(env, SPR_750_GQR0, "GQR0", 3694 SPR_NOACCESS, SPR_NOACCESS, 3695 &spr_read_generic, &spr_write_generic, 3696 0x00000000); 3697 3698 spr_register(env, SPR_750_GQR1, "GQR1", 3699 SPR_NOACCESS, SPR_NOACCESS, 3700 &spr_read_generic, &spr_write_generic, 3701 0x00000000); 3702 3703 spr_register(env, SPR_750_GQR2, "GQR2", 3704 SPR_NOACCESS, SPR_NOACCESS, 3705 &spr_read_generic, &spr_write_generic, 3706 0x00000000); 3707 3708 spr_register(env, SPR_750_GQR3, "GQR3", 3709 SPR_NOACCESS, SPR_NOACCESS, 3710 &spr_read_generic, &spr_write_generic, 3711 0x00000000); 3712 3713 spr_register(env, SPR_750_GQR4, "GQR4", 3714 SPR_NOACCESS, SPR_NOACCESS, 3715 &spr_read_generic, &spr_write_generic, 3716 0x00000000); 3717 3718 spr_register(env, SPR_750_GQR5, "GQR5", 3719 SPR_NOACCESS, SPR_NOACCESS, 3720 &spr_read_generic, &spr_write_generic, 3721 0x00000000); 3722 3723 spr_register(env, SPR_750_GQR6, "GQR6", 3724 SPR_NOACCESS, SPR_NOACCESS, 3725 &spr_read_generic, &spr_write_generic, 3726 0x00000000); 3727 3728 spr_register(env, SPR_750_GQR7, "GQR7", 3729 SPR_NOACCESS, SPR_NOACCESS, 3730 &spr_read_generic, &spr_write_generic, 3731 0x00000000); 3732 /* Memory management */ 3733 register_low_BATs(env); 3734 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3735 register_high_BATs(env); 3736 init_excp_750cl(env); 3737 env->dcache_line_size = 32; 3738 env->icache_line_size = 32; 3739 /* Allocate hardware IRQ controller */ 3740 ppc6xx_irq_init(env_archcpu(env)); 3741 } 3742 3743 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3744 { 3745 DeviceClass *dc = DEVICE_CLASS(oc); 3746 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3747 3748 dc->desc = "PowerPC 750 CL"; 3749 pcc->init_proc = init_proc_750cl; 3750 pcc->check_pow = check_pow_hid0; 3751 pcc->check_attn = check_attn_none; 3752 /* 3753 * XXX: not implemented: 3754 * cache lock instructions: 3755 * dcbz_l 3756 * floating point paired instructions 3757 * psq_lux 3758 * psq_lx 3759 * psq_stux 3760 * psq_stx 3761 * ps_abs 3762 * ps_add 3763 * ps_cmpo0 3764 * ps_cmpo1 3765 * ps_cmpu0 3766 * ps_cmpu1 3767 * ps_div 3768 * ps_madd 3769 * ps_madds0 3770 * ps_madds1 3771 * ps_merge00 3772 * ps_merge01 3773 * ps_merge10 3774 * ps_merge11 3775 * ps_mr 3776 * ps_msub 3777 * ps_mul 3778 * ps_muls0 3779 * ps_muls1 3780 * ps_nabs 3781 * ps_neg 3782 * ps_nmadd 3783 * ps_nmsub 3784 * ps_res 3785 * ps_rsqrte 3786 * ps_sel 3787 * ps_sub 3788 * ps_sum0 3789 * ps_sum1 3790 */ 3791 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3792 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3793 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3794 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3795 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3796 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3797 PPC_SEGMENT | PPC_EXTERN; 3798 pcc->msr_mask = (1ull << MSR_POW) | 3799 (1ull << MSR_ILE) | 3800 (1ull << MSR_EE) | 3801 (1ull << MSR_PR) | 3802 (1ull << MSR_FP) | 3803 (1ull << MSR_ME) | 3804 (1ull << MSR_FE0) | 3805 (1ull << MSR_SE) | 3806 (1ull << MSR_DE) | 3807 (1ull << MSR_FE1) | 3808 (1ull << MSR_EP) | 3809 (1ull << MSR_IR) | 3810 (1ull << MSR_DR) | 3811 (1ull << MSR_PMM) | 3812 (1ull << MSR_RI) | 3813 (1ull << MSR_LE); 3814 pcc->mmu_model = POWERPC_MMU_32B; 3815 pcc->excp_model = POWERPC_EXCP_7xx; 3816 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3817 pcc->bfd_mach = bfd_mach_ppc_750; 3818 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3819 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3820 } 3821 3822 static void init_proc_750cx(CPUPPCState *env) 3823 { 3824 register_non_embedded_sprs(env); 3825 register_sdr1_sprs(env); 3826 register_7xx_sprs(env); 3827 3828 spr_register(env, SPR_L2CR, "L2CR", 3829 SPR_NOACCESS, SPR_NOACCESS, 3830 &spr_read_generic, spr_access_nop, 3831 0x00000000); 3832 /* Thermal management */ 3833 register_thrm_sprs(env); 3834 3835 spr_register(env, SPR_SDA, "SDA", 3836 SPR_NOACCESS, SPR_NOACCESS, 3837 &spr_read_generic, &spr_write_generic, 3838 0x00000000); 3839 3840 /* Memory management */ 3841 register_low_BATs(env); 3842 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3843 register_high_BATs(env); 3844 init_excp_750cx(env); 3845 env->dcache_line_size = 32; 3846 env->icache_line_size = 32; 3847 /* Allocate hardware IRQ controller */ 3848 ppc6xx_irq_init(env_archcpu(env)); 3849 } 3850 3851 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3852 { 3853 DeviceClass *dc = DEVICE_CLASS(oc); 3854 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3855 3856 dc->desc = "PowerPC 750CX"; 3857 pcc->init_proc = init_proc_750cx; 3858 pcc->check_pow = check_pow_hid0; 3859 pcc->check_attn = check_attn_none; 3860 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3861 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3862 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3863 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3864 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3865 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3866 PPC_SEGMENT | PPC_EXTERN; 3867 pcc->msr_mask = (1ull << MSR_POW) | 3868 (1ull << MSR_ILE) | 3869 (1ull << MSR_EE) | 3870 (1ull << MSR_PR) | 3871 (1ull << MSR_FP) | 3872 (1ull << MSR_ME) | 3873 (1ull << MSR_FE0) | 3874 (1ull << MSR_SE) | 3875 (1ull << MSR_DE) | 3876 (1ull << MSR_FE1) | 3877 (1ull << MSR_EP) | 3878 (1ull << MSR_IR) | 3879 (1ull << MSR_DR) | 3880 (1ull << MSR_PMM) | 3881 (1ull << MSR_RI) | 3882 (1ull << MSR_LE); 3883 pcc->mmu_model = POWERPC_MMU_32B; 3884 pcc->excp_model = POWERPC_EXCP_7xx; 3885 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3886 pcc->bfd_mach = bfd_mach_ppc_750; 3887 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3888 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3889 } 3890 3891 static void init_proc_750fx(CPUPPCState *env) 3892 { 3893 register_non_embedded_sprs(env); 3894 register_sdr1_sprs(env); 3895 register_7xx_sprs(env); 3896 3897 spr_register(env, SPR_L2CR, "L2CR", 3898 SPR_NOACCESS, SPR_NOACCESS, 3899 &spr_read_generic, spr_access_nop, 3900 0x00000000); 3901 /* Thermal management */ 3902 register_thrm_sprs(env); 3903 3904 spr_register(env, SPR_750_THRM4, "THRM4", 3905 SPR_NOACCESS, SPR_NOACCESS, 3906 &spr_read_generic, &spr_write_generic, 3907 0x00000000); 3908 /* Hardware implementation registers */ 3909 spr_register(env, SPR_750FX_HID2, "HID2", 3910 SPR_NOACCESS, SPR_NOACCESS, 3911 &spr_read_generic, &spr_write_generic, 3912 0x00000000); 3913 /* Memory management */ 3914 register_low_BATs(env); 3915 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3916 register_high_BATs(env); 3917 init_excp_7x0(env); 3918 env->dcache_line_size = 32; 3919 env->icache_line_size = 32; 3920 /* Allocate hardware IRQ controller */ 3921 ppc6xx_irq_init(env_archcpu(env)); 3922 } 3923 3924 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3925 { 3926 DeviceClass *dc = DEVICE_CLASS(oc); 3927 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3928 3929 dc->desc = "PowerPC 750FX"; 3930 pcc->init_proc = init_proc_750fx; 3931 pcc->check_pow = check_pow_hid0; 3932 pcc->check_attn = check_attn_none; 3933 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3934 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3935 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3936 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3937 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3938 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3939 PPC_SEGMENT | PPC_EXTERN; 3940 pcc->msr_mask = (1ull << MSR_POW) | 3941 (1ull << MSR_ILE) | 3942 (1ull << MSR_EE) | 3943 (1ull << MSR_PR) | 3944 (1ull << MSR_FP) | 3945 (1ull << MSR_ME) | 3946 (1ull << MSR_FE0) | 3947 (1ull << MSR_SE) | 3948 (1ull << MSR_DE) | 3949 (1ull << MSR_FE1) | 3950 (1ull << MSR_EP) | 3951 (1ull << MSR_IR) | 3952 (1ull << MSR_DR) | 3953 (1ull << MSR_PMM) | 3954 (1ull << MSR_RI) | 3955 (1ull << MSR_LE); 3956 pcc->mmu_model = POWERPC_MMU_32B; 3957 pcc->excp_model = POWERPC_EXCP_7xx; 3958 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3959 pcc->bfd_mach = bfd_mach_ppc_750; 3960 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3961 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3962 } 3963 3964 static void init_proc_750gx(CPUPPCState *env) 3965 { 3966 register_non_embedded_sprs(env); 3967 register_sdr1_sprs(env); 3968 register_7xx_sprs(env); 3969 3970 spr_register(env, SPR_L2CR, "L2CR", 3971 SPR_NOACCESS, SPR_NOACCESS, 3972 &spr_read_generic, spr_access_nop, 3973 0x00000000); 3974 /* Thermal management */ 3975 register_thrm_sprs(env); 3976 3977 spr_register(env, SPR_750_THRM4, "THRM4", 3978 SPR_NOACCESS, SPR_NOACCESS, 3979 &spr_read_generic, &spr_write_generic, 3980 0x00000000); 3981 /* Hardware implementation registers */ 3982 spr_register(env, SPR_750FX_HID2, "HID2", 3983 SPR_NOACCESS, SPR_NOACCESS, 3984 &spr_read_generic, &spr_write_generic, 3985 0x00000000); 3986 /* Memory management */ 3987 register_low_BATs(env); 3988 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3989 register_high_BATs(env); 3990 init_excp_7x0(env); 3991 env->dcache_line_size = 32; 3992 env->icache_line_size = 32; 3993 /* Allocate hardware IRQ controller */ 3994 ppc6xx_irq_init(env_archcpu(env)); 3995 } 3996 3997 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 3998 { 3999 DeviceClass *dc = DEVICE_CLASS(oc); 4000 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4001 4002 dc->desc = "PowerPC 750GX"; 4003 pcc->init_proc = init_proc_750gx; 4004 pcc->check_pow = check_pow_hid0; 4005 pcc->check_attn = check_attn_none; 4006 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4007 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4008 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4009 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4010 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4011 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4012 PPC_SEGMENT | PPC_EXTERN; 4013 pcc->msr_mask = (1ull << MSR_POW) | 4014 (1ull << MSR_ILE) | 4015 (1ull << MSR_EE) | 4016 (1ull << MSR_PR) | 4017 (1ull << MSR_FP) | 4018 (1ull << MSR_ME) | 4019 (1ull << MSR_FE0) | 4020 (1ull << MSR_SE) | 4021 (1ull << MSR_DE) | 4022 (1ull << MSR_FE1) | 4023 (1ull << MSR_EP) | 4024 (1ull << MSR_IR) | 4025 (1ull << MSR_DR) | 4026 (1ull << MSR_PMM) | 4027 (1ull << MSR_RI) | 4028 (1ull << MSR_LE); 4029 pcc->mmu_model = POWERPC_MMU_32B; 4030 pcc->excp_model = POWERPC_EXCP_7xx; 4031 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4032 pcc->bfd_mach = bfd_mach_ppc_750; 4033 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4034 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4035 } 4036 4037 static void init_proc_745(CPUPPCState *env) 4038 { 4039 register_non_embedded_sprs(env); 4040 register_sdr1_sprs(env); 4041 register_7xx_sprs(env); 4042 register_745_sprs(env); 4043 /* Thermal management */ 4044 register_thrm_sprs(env); 4045 4046 /* Memory management */ 4047 register_low_BATs(env); 4048 register_high_BATs(env); 4049 register_6xx_7xx_soft_tlb(env, 64, 2); 4050 init_excp_7x5(env); 4051 env->dcache_line_size = 32; 4052 env->icache_line_size = 32; 4053 /* Allocate hardware IRQ controller */ 4054 ppc6xx_irq_init(env_archcpu(env)); 4055 } 4056 4057 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4058 { 4059 DeviceClass *dc = DEVICE_CLASS(oc); 4060 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4061 4062 dc->desc = "PowerPC 745"; 4063 pcc->init_proc = init_proc_745; 4064 pcc->check_pow = check_pow_hid0; 4065 pcc->check_attn = check_attn_none; 4066 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4067 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4068 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4069 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4070 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4071 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4072 PPC_SEGMENT | PPC_EXTERN; 4073 pcc->msr_mask = (1ull << MSR_POW) | 4074 (1ull << MSR_ILE) | 4075 (1ull << MSR_EE) | 4076 (1ull << MSR_PR) | 4077 (1ull << MSR_FP) | 4078 (1ull << MSR_ME) | 4079 (1ull << MSR_FE0) | 4080 (1ull << MSR_SE) | 4081 (1ull << MSR_DE) | 4082 (1ull << MSR_FE1) | 4083 (1ull << MSR_EP) | 4084 (1ull << MSR_IR) | 4085 (1ull << MSR_DR) | 4086 (1ull << MSR_PMM) | 4087 (1ull << MSR_RI) | 4088 (1ull << MSR_LE); 4089 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4090 pcc->excp_model = POWERPC_EXCP_7xx; 4091 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4092 pcc->bfd_mach = bfd_mach_ppc_750; 4093 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4094 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4095 } 4096 4097 static void init_proc_755(CPUPPCState *env) 4098 { 4099 init_proc_745(env); 4100 register_755_sprs(env); 4101 } 4102 4103 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4104 { 4105 DeviceClass *dc = DEVICE_CLASS(oc); 4106 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4107 4108 dc->desc = "PowerPC 755"; 4109 pcc->init_proc = init_proc_755; 4110 pcc->check_pow = check_pow_hid0; 4111 pcc->check_attn = check_attn_none; 4112 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4113 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4114 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4115 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4116 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4117 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4118 PPC_SEGMENT | PPC_EXTERN; 4119 pcc->msr_mask = (1ull << MSR_POW) | 4120 (1ull << MSR_ILE) | 4121 (1ull << MSR_EE) | 4122 (1ull << MSR_PR) | 4123 (1ull << MSR_FP) | 4124 (1ull << MSR_ME) | 4125 (1ull << MSR_FE0) | 4126 (1ull << MSR_SE) | 4127 (1ull << MSR_DE) | 4128 (1ull << MSR_FE1) | 4129 (1ull << MSR_EP) | 4130 (1ull << MSR_IR) | 4131 (1ull << MSR_DR) | 4132 (1ull << MSR_PMM) | 4133 (1ull << MSR_RI) | 4134 (1ull << MSR_LE); 4135 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4136 pcc->excp_model = POWERPC_EXCP_7xx; 4137 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4138 pcc->bfd_mach = bfd_mach_ppc_750; 4139 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4140 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4141 } 4142 4143 static void init_proc_7400(CPUPPCState *env) 4144 { 4145 register_non_embedded_sprs(env); 4146 register_sdr1_sprs(env); 4147 register_74xx_sprs(env); 4148 vscr_init(env, 0x00010000); 4149 4150 spr_register(env, SPR_UBAMR, "UBAMR", 4151 &spr_read_ureg, SPR_NOACCESS, 4152 &spr_read_ureg, SPR_NOACCESS, 4153 0x00000000); 4154 4155 spr_register(env, SPR_MSSCR1, "MSSCR1", 4156 SPR_NOACCESS, SPR_NOACCESS, 4157 &spr_read_generic, &spr_write_generic, 4158 0x00000000); 4159 /* Thermal management */ 4160 register_thrm_sprs(env); 4161 /* Memory management */ 4162 register_low_BATs(env); 4163 init_excp_7400(env); 4164 env->dcache_line_size = 32; 4165 env->icache_line_size = 32; 4166 /* Allocate hardware IRQ controller */ 4167 ppc6xx_irq_init(env_archcpu(env)); 4168 } 4169 4170 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4171 { 4172 DeviceClass *dc = DEVICE_CLASS(oc); 4173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4174 4175 dc->desc = "PowerPC 7400 (aka G4)"; 4176 pcc->init_proc = init_proc_7400; 4177 pcc->check_pow = check_pow_hid0; 4178 pcc->check_attn = check_attn_none; 4179 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4180 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4181 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4182 PPC_FLOAT_STFIWX | 4183 PPC_CACHE | PPC_CACHE_ICBI | 4184 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4185 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4186 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4187 PPC_MEM_TLBIA | 4188 PPC_SEGMENT | PPC_EXTERN | 4189 PPC_ALTIVEC; 4190 pcc->msr_mask = (1ull << MSR_VR) | 4191 (1ull << MSR_POW) | 4192 (1ull << MSR_ILE) | 4193 (1ull << MSR_EE) | 4194 (1ull << MSR_PR) | 4195 (1ull << MSR_FP) | 4196 (1ull << MSR_ME) | 4197 (1ull << MSR_FE0) | 4198 (1ull << MSR_SE) | 4199 (1ull << MSR_DE) | 4200 (1ull << MSR_FE1) | 4201 (1ull << MSR_EP) | 4202 (1ull << MSR_IR) | 4203 (1ull << MSR_DR) | 4204 (1ull << MSR_PMM) | 4205 (1ull << MSR_RI) | 4206 (1ull << MSR_LE); 4207 pcc->mmu_model = POWERPC_MMU_32B; 4208 pcc->excp_model = POWERPC_EXCP_74xx; 4209 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4210 pcc->bfd_mach = bfd_mach_ppc_7400; 4211 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4212 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4213 POWERPC_FLAG_BUS_CLK; 4214 } 4215 4216 static void init_proc_7410(CPUPPCState *env) 4217 { 4218 register_non_embedded_sprs(env); 4219 register_sdr1_sprs(env); 4220 register_74xx_sprs(env); 4221 vscr_init(env, 0x00010000); 4222 4223 spr_register(env, SPR_UBAMR, "UBAMR", 4224 &spr_read_ureg, SPR_NOACCESS, 4225 &spr_read_ureg, SPR_NOACCESS, 4226 0x00000000); 4227 /* Thermal management */ 4228 register_thrm_sprs(env); 4229 /* L2PMCR */ 4230 4231 spr_register(env, SPR_L2PMCR, "L2PMCR", 4232 SPR_NOACCESS, SPR_NOACCESS, 4233 &spr_read_generic, &spr_write_generic, 4234 0x00000000); 4235 /* LDSTDB */ 4236 4237 spr_register(env, SPR_LDSTDB, "LDSTDB", 4238 SPR_NOACCESS, SPR_NOACCESS, 4239 &spr_read_generic, &spr_write_generic, 4240 0x00000000); 4241 /* Memory management */ 4242 register_low_BATs(env); 4243 init_excp_7400(env); 4244 env->dcache_line_size = 32; 4245 env->icache_line_size = 32; 4246 /* Allocate hardware IRQ controller */ 4247 ppc6xx_irq_init(env_archcpu(env)); 4248 } 4249 4250 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4251 { 4252 DeviceClass *dc = DEVICE_CLASS(oc); 4253 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4254 4255 dc->desc = "PowerPC 7410 (aka G4)"; 4256 pcc->init_proc = init_proc_7410; 4257 pcc->check_pow = check_pow_hid0; 4258 pcc->check_attn = check_attn_none; 4259 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4260 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4261 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4262 PPC_FLOAT_STFIWX | 4263 PPC_CACHE | PPC_CACHE_ICBI | 4264 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4265 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4266 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4267 PPC_MEM_TLBIA | 4268 PPC_SEGMENT | PPC_EXTERN | 4269 PPC_ALTIVEC; 4270 pcc->msr_mask = (1ull << MSR_VR) | 4271 (1ull << MSR_POW) | 4272 (1ull << MSR_ILE) | 4273 (1ull << MSR_EE) | 4274 (1ull << MSR_PR) | 4275 (1ull << MSR_FP) | 4276 (1ull << MSR_ME) | 4277 (1ull << MSR_FE0) | 4278 (1ull << MSR_SE) | 4279 (1ull << MSR_DE) | 4280 (1ull << MSR_FE1) | 4281 (1ull << MSR_EP) | 4282 (1ull << MSR_IR) | 4283 (1ull << MSR_DR) | 4284 (1ull << MSR_PMM) | 4285 (1ull << MSR_RI) | 4286 (1ull << MSR_LE); 4287 pcc->mmu_model = POWERPC_MMU_32B; 4288 pcc->excp_model = POWERPC_EXCP_74xx; 4289 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4290 pcc->bfd_mach = bfd_mach_ppc_7400; 4291 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4292 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4293 POWERPC_FLAG_BUS_CLK; 4294 } 4295 4296 static void init_proc_7440(CPUPPCState *env) 4297 { 4298 register_non_embedded_sprs(env); 4299 register_sdr1_sprs(env); 4300 register_74xx_sprs(env); 4301 vscr_init(env, 0x00010000); 4302 4303 spr_register(env, SPR_UBAMR, "UBAMR", 4304 &spr_read_ureg, SPR_NOACCESS, 4305 &spr_read_ureg, SPR_NOACCESS, 4306 0x00000000); 4307 /* LDSTCR */ 4308 spr_register(env, SPR_LDSTCR, "LDSTCR", 4309 SPR_NOACCESS, SPR_NOACCESS, 4310 &spr_read_generic, &spr_write_generic, 4311 0x00000000); 4312 /* ICTRL */ 4313 spr_register(env, SPR_ICTRL, "ICTRL", 4314 SPR_NOACCESS, SPR_NOACCESS, 4315 &spr_read_generic, &spr_write_generic, 4316 0x00000000); 4317 /* MSSSR0 */ 4318 spr_register(env, SPR_MSSSR0, "MSSSR0", 4319 SPR_NOACCESS, SPR_NOACCESS, 4320 &spr_read_generic, &spr_write_generic, 4321 0x00000000); 4322 /* PMC */ 4323 spr_register(env, SPR_7XX_PMC5, "PMC5", 4324 SPR_NOACCESS, SPR_NOACCESS, 4325 &spr_read_generic, &spr_write_generic, 4326 0x00000000); 4327 4328 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4329 &spr_read_ureg, SPR_NOACCESS, 4330 &spr_read_ureg, SPR_NOACCESS, 4331 0x00000000); 4332 4333 spr_register(env, SPR_7XX_PMC6, "PMC6", 4334 SPR_NOACCESS, SPR_NOACCESS, 4335 &spr_read_generic, &spr_write_generic, 4336 0x00000000); 4337 4338 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4339 &spr_read_ureg, SPR_NOACCESS, 4340 &spr_read_ureg, SPR_NOACCESS, 4341 0x00000000); 4342 /* Memory management */ 4343 register_low_BATs(env); 4344 init_excp_7450(env); 4345 env->dcache_line_size = 32; 4346 env->icache_line_size = 32; 4347 /* Allocate hardware IRQ controller */ 4348 ppc6xx_irq_init(env_archcpu(env)); 4349 } 4350 4351 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4352 { 4353 DeviceClass *dc = DEVICE_CLASS(oc); 4354 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4355 4356 dc->desc = "PowerPC 7440 (aka G4)"; 4357 pcc->init_proc = init_proc_7440; 4358 pcc->check_pow = check_pow_hid0_74xx; 4359 pcc->check_attn = check_attn_none; 4360 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4361 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4362 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4363 PPC_FLOAT_STFIWX | 4364 PPC_CACHE | PPC_CACHE_ICBI | 4365 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4366 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4367 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4368 PPC_MEM_TLBIA | 4369 PPC_SEGMENT | PPC_EXTERN | 4370 PPC_ALTIVEC; 4371 pcc->msr_mask = (1ull << MSR_VR) | 4372 (1ull << MSR_POW) | 4373 (1ull << MSR_ILE) | 4374 (1ull << MSR_EE) | 4375 (1ull << MSR_PR) | 4376 (1ull << MSR_FP) | 4377 (1ull << MSR_ME) | 4378 (1ull << MSR_FE0) | 4379 (1ull << MSR_SE) | 4380 (1ull << MSR_DE) | 4381 (1ull << MSR_FE1) | 4382 (1ull << MSR_EP) | 4383 (1ull << MSR_IR) | 4384 (1ull << MSR_DR) | 4385 (1ull << MSR_PMM) | 4386 (1ull << MSR_RI) | 4387 (1ull << MSR_LE); 4388 pcc->mmu_model = POWERPC_MMU_32B; 4389 pcc->excp_model = POWERPC_EXCP_74xx; 4390 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4391 pcc->bfd_mach = bfd_mach_ppc_7400; 4392 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4393 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4394 POWERPC_FLAG_BUS_CLK; 4395 } 4396 4397 static void init_proc_7450(CPUPPCState *env) 4398 { 4399 register_non_embedded_sprs(env); 4400 register_sdr1_sprs(env); 4401 register_74xx_sprs(env); 4402 vscr_init(env, 0x00010000); 4403 /* Level 3 cache control */ 4404 register_l3_ctrl(env); 4405 /* L3ITCR1 */ 4406 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4407 SPR_NOACCESS, SPR_NOACCESS, 4408 &spr_read_generic, &spr_write_generic, 4409 0x00000000); 4410 /* L3ITCR2 */ 4411 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4412 SPR_NOACCESS, SPR_NOACCESS, 4413 &spr_read_generic, &spr_write_generic, 4414 0x00000000); 4415 /* L3ITCR3 */ 4416 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, &spr_write_generic, 4419 0x00000000); 4420 /* L3OHCR */ 4421 spr_register(env, SPR_L3OHCR, "L3OHCR", 4422 SPR_NOACCESS, SPR_NOACCESS, 4423 &spr_read_generic, &spr_write_generic, 4424 0x00000000); 4425 4426 spr_register(env, SPR_UBAMR, "UBAMR", 4427 &spr_read_ureg, SPR_NOACCESS, 4428 &spr_read_ureg, SPR_NOACCESS, 4429 0x00000000); 4430 /* LDSTCR */ 4431 spr_register(env, SPR_LDSTCR, "LDSTCR", 4432 SPR_NOACCESS, SPR_NOACCESS, 4433 &spr_read_generic, &spr_write_generic, 4434 0x00000000); 4435 /* ICTRL */ 4436 spr_register(env, SPR_ICTRL, "ICTRL", 4437 SPR_NOACCESS, SPR_NOACCESS, 4438 &spr_read_generic, &spr_write_generic, 4439 0x00000000); 4440 /* MSSSR0 */ 4441 spr_register(env, SPR_MSSSR0, "MSSSR0", 4442 SPR_NOACCESS, SPR_NOACCESS, 4443 &spr_read_generic, &spr_write_generic, 4444 0x00000000); 4445 /* PMC */ 4446 spr_register(env, SPR_7XX_PMC5, "PMC5", 4447 SPR_NOACCESS, SPR_NOACCESS, 4448 &spr_read_generic, &spr_write_generic, 4449 0x00000000); 4450 4451 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4452 &spr_read_ureg, SPR_NOACCESS, 4453 &spr_read_ureg, SPR_NOACCESS, 4454 0x00000000); 4455 4456 spr_register(env, SPR_7XX_PMC6, "PMC6", 4457 SPR_NOACCESS, SPR_NOACCESS, 4458 &spr_read_generic, &spr_write_generic, 4459 0x00000000); 4460 4461 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4462 &spr_read_ureg, SPR_NOACCESS, 4463 &spr_read_ureg, SPR_NOACCESS, 4464 0x00000000); 4465 /* Memory management */ 4466 register_low_BATs(env); 4467 init_excp_7450(env); 4468 env->dcache_line_size = 32; 4469 env->icache_line_size = 32; 4470 /* Allocate hardware IRQ controller */ 4471 ppc6xx_irq_init(env_archcpu(env)); 4472 } 4473 4474 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4475 { 4476 DeviceClass *dc = DEVICE_CLASS(oc); 4477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4478 4479 dc->desc = "PowerPC 7450 (aka G4)"; 4480 pcc->init_proc = init_proc_7450; 4481 pcc->check_pow = check_pow_hid0_74xx; 4482 pcc->check_attn = check_attn_none; 4483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4484 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4485 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4486 PPC_FLOAT_STFIWX | 4487 PPC_CACHE | PPC_CACHE_ICBI | 4488 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4489 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4490 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4491 PPC_MEM_TLBIA | 4492 PPC_SEGMENT | PPC_EXTERN | 4493 PPC_ALTIVEC; 4494 pcc->msr_mask = (1ull << MSR_VR) | 4495 (1ull << MSR_POW) | 4496 (1ull << MSR_ILE) | 4497 (1ull << MSR_EE) | 4498 (1ull << MSR_PR) | 4499 (1ull << MSR_FP) | 4500 (1ull << MSR_ME) | 4501 (1ull << MSR_FE0) | 4502 (1ull << MSR_SE) | 4503 (1ull << MSR_DE) | 4504 (1ull << MSR_FE1) | 4505 (1ull << MSR_EP) | 4506 (1ull << MSR_IR) | 4507 (1ull << MSR_DR) | 4508 (1ull << MSR_PMM) | 4509 (1ull << MSR_RI) | 4510 (1ull << MSR_LE); 4511 pcc->mmu_model = POWERPC_MMU_32B; 4512 pcc->excp_model = POWERPC_EXCP_74xx; 4513 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4514 pcc->bfd_mach = bfd_mach_ppc_7400; 4515 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4516 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4517 POWERPC_FLAG_BUS_CLK; 4518 } 4519 4520 static void init_proc_7445(CPUPPCState *env) 4521 { 4522 register_non_embedded_sprs(env); 4523 register_sdr1_sprs(env); 4524 register_74xx_sprs(env); 4525 vscr_init(env, 0x00010000); 4526 /* LDSTCR */ 4527 spr_register(env, SPR_LDSTCR, "LDSTCR", 4528 SPR_NOACCESS, SPR_NOACCESS, 4529 &spr_read_generic, &spr_write_generic, 4530 0x00000000); 4531 /* ICTRL */ 4532 spr_register(env, SPR_ICTRL, "ICTRL", 4533 SPR_NOACCESS, SPR_NOACCESS, 4534 &spr_read_generic, &spr_write_generic, 4535 0x00000000); 4536 /* MSSSR0 */ 4537 spr_register(env, SPR_MSSSR0, "MSSSR0", 4538 SPR_NOACCESS, SPR_NOACCESS, 4539 &spr_read_generic, &spr_write_generic, 4540 0x00000000); 4541 /* PMC */ 4542 spr_register(env, SPR_7XX_PMC5, "PMC5", 4543 SPR_NOACCESS, SPR_NOACCESS, 4544 &spr_read_generic, &spr_write_generic, 4545 0x00000000); 4546 4547 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4548 &spr_read_ureg, SPR_NOACCESS, 4549 &spr_read_ureg, SPR_NOACCESS, 4550 0x00000000); 4551 4552 spr_register(env, SPR_7XX_PMC6, "PMC6", 4553 SPR_NOACCESS, SPR_NOACCESS, 4554 &spr_read_generic, &spr_write_generic, 4555 0x00000000); 4556 4557 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4558 &spr_read_ureg, SPR_NOACCESS, 4559 &spr_read_ureg, SPR_NOACCESS, 4560 0x00000000); 4561 /* SPRGs */ 4562 spr_register(env, SPR_SPRG4, "SPRG4", 4563 SPR_NOACCESS, SPR_NOACCESS, 4564 &spr_read_generic, &spr_write_generic, 4565 0x00000000); 4566 spr_register(env, SPR_USPRG4, "USPRG4", 4567 &spr_read_ureg, SPR_NOACCESS, 4568 &spr_read_ureg, SPR_NOACCESS, 4569 0x00000000); 4570 spr_register(env, SPR_SPRG5, "SPRG5", 4571 SPR_NOACCESS, SPR_NOACCESS, 4572 &spr_read_generic, &spr_write_generic, 4573 0x00000000); 4574 spr_register(env, SPR_USPRG5, "USPRG5", 4575 &spr_read_ureg, SPR_NOACCESS, 4576 &spr_read_ureg, SPR_NOACCESS, 4577 0x00000000); 4578 spr_register(env, SPR_SPRG6, "SPRG6", 4579 SPR_NOACCESS, SPR_NOACCESS, 4580 &spr_read_generic, &spr_write_generic, 4581 0x00000000); 4582 spr_register(env, SPR_USPRG6, "USPRG6", 4583 &spr_read_ureg, SPR_NOACCESS, 4584 &spr_read_ureg, SPR_NOACCESS, 4585 0x00000000); 4586 spr_register(env, SPR_SPRG7, "SPRG7", 4587 SPR_NOACCESS, SPR_NOACCESS, 4588 &spr_read_generic, &spr_write_generic, 4589 0x00000000); 4590 spr_register(env, SPR_USPRG7, "USPRG7", 4591 &spr_read_ureg, SPR_NOACCESS, 4592 &spr_read_ureg, SPR_NOACCESS, 4593 0x00000000); 4594 /* Memory management */ 4595 register_low_BATs(env); 4596 register_high_BATs(env); 4597 init_excp_7450(env); 4598 env->dcache_line_size = 32; 4599 env->icache_line_size = 32; 4600 /* Allocate hardware IRQ controller */ 4601 ppc6xx_irq_init(env_archcpu(env)); 4602 } 4603 4604 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4605 { 4606 DeviceClass *dc = DEVICE_CLASS(oc); 4607 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4608 4609 dc->desc = "PowerPC 7445 (aka G4)"; 4610 pcc->init_proc = init_proc_7445; 4611 pcc->check_pow = check_pow_hid0_74xx; 4612 pcc->check_attn = check_attn_none; 4613 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4614 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4615 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4616 PPC_FLOAT_STFIWX | 4617 PPC_CACHE | PPC_CACHE_ICBI | 4618 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4619 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4620 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4621 PPC_MEM_TLBIA | 4622 PPC_SEGMENT | PPC_EXTERN | 4623 PPC_ALTIVEC; 4624 pcc->msr_mask = (1ull << MSR_VR) | 4625 (1ull << MSR_POW) | 4626 (1ull << MSR_ILE) | 4627 (1ull << MSR_EE) | 4628 (1ull << MSR_PR) | 4629 (1ull << MSR_FP) | 4630 (1ull << MSR_ME) | 4631 (1ull << MSR_FE0) | 4632 (1ull << MSR_SE) | 4633 (1ull << MSR_DE) | 4634 (1ull << MSR_FE1) | 4635 (1ull << MSR_EP) | 4636 (1ull << MSR_IR) | 4637 (1ull << MSR_DR) | 4638 (1ull << MSR_PMM) | 4639 (1ull << MSR_RI) | 4640 (1ull << MSR_LE); 4641 pcc->mmu_model = POWERPC_MMU_32B; 4642 pcc->excp_model = POWERPC_EXCP_74xx; 4643 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4644 pcc->bfd_mach = bfd_mach_ppc_7400; 4645 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4646 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4647 POWERPC_FLAG_BUS_CLK; 4648 } 4649 4650 static void init_proc_7455(CPUPPCState *env) 4651 { 4652 register_non_embedded_sprs(env); 4653 register_sdr1_sprs(env); 4654 register_74xx_sprs(env); 4655 vscr_init(env, 0x00010000); 4656 /* Level 3 cache control */ 4657 register_l3_ctrl(env); 4658 /* LDSTCR */ 4659 spr_register(env, SPR_LDSTCR, "LDSTCR", 4660 SPR_NOACCESS, SPR_NOACCESS, 4661 &spr_read_generic, &spr_write_generic, 4662 0x00000000); 4663 /* ICTRL */ 4664 spr_register(env, SPR_ICTRL, "ICTRL", 4665 SPR_NOACCESS, SPR_NOACCESS, 4666 &spr_read_generic, &spr_write_generic, 4667 0x00000000); 4668 /* MSSSR0 */ 4669 spr_register(env, SPR_MSSSR0, "MSSSR0", 4670 SPR_NOACCESS, SPR_NOACCESS, 4671 &spr_read_generic, &spr_write_generic, 4672 0x00000000); 4673 /* PMC */ 4674 spr_register(env, SPR_7XX_PMC5, "PMC5", 4675 SPR_NOACCESS, SPR_NOACCESS, 4676 &spr_read_generic, &spr_write_generic, 4677 0x00000000); 4678 4679 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4680 &spr_read_ureg, SPR_NOACCESS, 4681 &spr_read_ureg, SPR_NOACCESS, 4682 0x00000000); 4683 4684 spr_register(env, SPR_7XX_PMC6, "PMC6", 4685 SPR_NOACCESS, SPR_NOACCESS, 4686 &spr_read_generic, &spr_write_generic, 4687 0x00000000); 4688 4689 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4690 &spr_read_ureg, SPR_NOACCESS, 4691 &spr_read_ureg, SPR_NOACCESS, 4692 0x00000000); 4693 /* SPRGs */ 4694 spr_register(env, SPR_SPRG4, "SPRG4", 4695 SPR_NOACCESS, SPR_NOACCESS, 4696 &spr_read_generic, &spr_write_generic, 4697 0x00000000); 4698 spr_register(env, SPR_USPRG4, "USPRG4", 4699 &spr_read_ureg, SPR_NOACCESS, 4700 &spr_read_ureg, SPR_NOACCESS, 4701 0x00000000); 4702 spr_register(env, SPR_SPRG5, "SPRG5", 4703 SPR_NOACCESS, SPR_NOACCESS, 4704 &spr_read_generic, &spr_write_generic, 4705 0x00000000); 4706 spr_register(env, SPR_USPRG5, "USPRG5", 4707 &spr_read_ureg, SPR_NOACCESS, 4708 &spr_read_ureg, SPR_NOACCESS, 4709 0x00000000); 4710 spr_register(env, SPR_SPRG6, "SPRG6", 4711 SPR_NOACCESS, SPR_NOACCESS, 4712 &spr_read_generic, &spr_write_generic, 4713 0x00000000); 4714 spr_register(env, SPR_USPRG6, "USPRG6", 4715 &spr_read_ureg, SPR_NOACCESS, 4716 &spr_read_ureg, SPR_NOACCESS, 4717 0x00000000); 4718 spr_register(env, SPR_SPRG7, "SPRG7", 4719 SPR_NOACCESS, SPR_NOACCESS, 4720 &spr_read_generic, &spr_write_generic, 4721 0x00000000); 4722 spr_register(env, SPR_USPRG7, "USPRG7", 4723 &spr_read_ureg, SPR_NOACCESS, 4724 &spr_read_ureg, SPR_NOACCESS, 4725 0x00000000); 4726 /* Memory management */ 4727 register_low_BATs(env); 4728 register_high_BATs(env); 4729 init_excp_7450(env); 4730 env->dcache_line_size = 32; 4731 env->icache_line_size = 32; 4732 /* Allocate hardware IRQ controller */ 4733 ppc6xx_irq_init(env_archcpu(env)); 4734 } 4735 4736 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4737 { 4738 DeviceClass *dc = DEVICE_CLASS(oc); 4739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4740 4741 dc->desc = "PowerPC 7455 (aka G4)"; 4742 pcc->init_proc = init_proc_7455; 4743 pcc->check_pow = check_pow_hid0_74xx; 4744 pcc->check_attn = check_attn_none; 4745 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4746 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4747 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4748 PPC_FLOAT_STFIWX | 4749 PPC_CACHE | PPC_CACHE_ICBI | 4750 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4751 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4752 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4753 PPC_MEM_TLBIA | 4754 PPC_SEGMENT | PPC_EXTERN | 4755 PPC_ALTIVEC; 4756 pcc->msr_mask = (1ull << MSR_VR) | 4757 (1ull << MSR_POW) | 4758 (1ull << MSR_ILE) | 4759 (1ull << MSR_EE) | 4760 (1ull << MSR_PR) | 4761 (1ull << MSR_FP) | 4762 (1ull << MSR_ME) | 4763 (1ull << MSR_FE0) | 4764 (1ull << MSR_SE) | 4765 (1ull << MSR_DE) | 4766 (1ull << MSR_FE1) | 4767 (1ull << MSR_EP) | 4768 (1ull << MSR_IR) | 4769 (1ull << MSR_DR) | 4770 (1ull << MSR_PMM) | 4771 (1ull << MSR_RI) | 4772 (1ull << MSR_LE); 4773 pcc->mmu_model = POWERPC_MMU_32B; 4774 pcc->excp_model = POWERPC_EXCP_74xx; 4775 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4776 pcc->bfd_mach = bfd_mach_ppc_7400; 4777 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4778 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4779 POWERPC_FLAG_BUS_CLK; 4780 } 4781 4782 static void init_proc_7457(CPUPPCState *env) 4783 { 4784 register_non_embedded_sprs(env); 4785 register_sdr1_sprs(env); 4786 register_74xx_sprs(env); 4787 vscr_init(env, 0x00010000); 4788 /* Level 3 cache control */ 4789 register_l3_ctrl(env); 4790 /* L3ITCR1 */ 4791 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4792 SPR_NOACCESS, SPR_NOACCESS, 4793 &spr_read_generic, &spr_write_generic, 4794 0x00000000); 4795 /* L3ITCR2 */ 4796 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4797 SPR_NOACCESS, SPR_NOACCESS, 4798 &spr_read_generic, &spr_write_generic, 4799 0x00000000); 4800 /* L3ITCR3 */ 4801 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4802 SPR_NOACCESS, SPR_NOACCESS, 4803 &spr_read_generic, &spr_write_generic, 4804 0x00000000); 4805 /* L3OHCR */ 4806 spr_register(env, SPR_L3OHCR, "L3OHCR", 4807 SPR_NOACCESS, SPR_NOACCESS, 4808 &spr_read_generic, &spr_write_generic, 4809 0x00000000); 4810 /* LDSTCR */ 4811 spr_register(env, SPR_LDSTCR, "LDSTCR", 4812 SPR_NOACCESS, SPR_NOACCESS, 4813 &spr_read_generic, &spr_write_generic, 4814 0x00000000); 4815 /* ICTRL */ 4816 spr_register(env, SPR_ICTRL, "ICTRL", 4817 SPR_NOACCESS, SPR_NOACCESS, 4818 &spr_read_generic, &spr_write_generic, 4819 0x00000000); 4820 /* MSSSR0 */ 4821 spr_register(env, SPR_MSSSR0, "MSSSR0", 4822 SPR_NOACCESS, SPR_NOACCESS, 4823 &spr_read_generic, &spr_write_generic, 4824 0x00000000); 4825 /* PMC */ 4826 spr_register(env, SPR_7XX_PMC5, "PMC5", 4827 SPR_NOACCESS, SPR_NOACCESS, 4828 &spr_read_generic, &spr_write_generic, 4829 0x00000000); 4830 4831 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4832 &spr_read_ureg, SPR_NOACCESS, 4833 &spr_read_ureg, SPR_NOACCESS, 4834 0x00000000); 4835 4836 spr_register(env, SPR_7XX_PMC6, "PMC6", 4837 SPR_NOACCESS, SPR_NOACCESS, 4838 &spr_read_generic, &spr_write_generic, 4839 0x00000000); 4840 4841 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4842 &spr_read_ureg, SPR_NOACCESS, 4843 &spr_read_ureg, SPR_NOACCESS, 4844 0x00000000); 4845 /* SPRGs */ 4846 spr_register(env, SPR_SPRG4, "SPRG4", 4847 SPR_NOACCESS, SPR_NOACCESS, 4848 &spr_read_generic, &spr_write_generic, 4849 0x00000000); 4850 spr_register(env, SPR_USPRG4, "USPRG4", 4851 &spr_read_ureg, SPR_NOACCESS, 4852 &spr_read_ureg, SPR_NOACCESS, 4853 0x00000000); 4854 spr_register(env, SPR_SPRG5, "SPRG5", 4855 SPR_NOACCESS, SPR_NOACCESS, 4856 &spr_read_generic, &spr_write_generic, 4857 0x00000000); 4858 spr_register(env, SPR_USPRG5, "USPRG5", 4859 &spr_read_ureg, SPR_NOACCESS, 4860 &spr_read_ureg, SPR_NOACCESS, 4861 0x00000000); 4862 spr_register(env, SPR_SPRG6, "SPRG6", 4863 SPR_NOACCESS, SPR_NOACCESS, 4864 &spr_read_generic, &spr_write_generic, 4865 0x00000000); 4866 spr_register(env, SPR_USPRG6, "USPRG6", 4867 &spr_read_ureg, SPR_NOACCESS, 4868 &spr_read_ureg, SPR_NOACCESS, 4869 0x00000000); 4870 spr_register(env, SPR_SPRG7, "SPRG7", 4871 SPR_NOACCESS, SPR_NOACCESS, 4872 &spr_read_generic, &spr_write_generic, 4873 0x00000000); 4874 spr_register(env, SPR_USPRG7, "USPRG7", 4875 &spr_read_ureg, SPR_NOACCESS, 4876 &spr_read_ureg, SPR_NOACCESS, 4877 0x00000000); 4878 /* Memory management */ 4879 register_low_BATs(env); 4880 register_high_BATs(env); 4881 init_excp_7450(env); 4882 env->dcache_line_size = 32; 4883 env->icache_line_size = 32; 4884 /* Allocate hardware IRQ controller */ 4885 ppc6xx_irq_init(env_archcpu(env)); 4886 } 4887 4888 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4889 { 4890 DeviceClass *dc = DEVICE_CLASS(oc); 4891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4892 4893 dc->desc = "PowerPC 7457 (aka G4)"; 4894 pcc->init_proc = init_proc_7457; 4895 pcc->check_pow = check_pow_hid0_74xx; 4896 pcc->check_attn = check_attn_none; 4897 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4898 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4899 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4900 PPC_FLOAT_STFIWX | 4901 PPC_CACHE | PPC_CACHE_ICBI | 4902 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4903 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4904 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4905 PPC_MEM_TLBIA | 4906 PPC_SEGMENT | PPC_EXTERN | 4907 PPC_ALTIVEC; 4908 pcc->msr_mask = (1ull << MSR_VR) | 4909 (1ull << MSR_POW) | 4910 (1ull << MSR_ILE) | 4911 (1ull << MSR_EE) | 4912 (1ull << MSR_PR) | 4913 (1ull << MSR_FP) | 4914 (1ull << MSR_ME) | 4915 (1ull << MSR_FE0) | 4916 (1ull << MSR_SE) | 4917 (1ull << MSR_DE) | 4918 (1ull << MSR_FE1) | 4919 (1ull << MSR_EP) | 4920 (1ull << MSR_IR) | 4921 (1ull << MSR_DR) | 4922 (1ull << MSR_PMM) | 4923 (1ull << MSR_RI) | 4924 (1ull << MSR_LE); 4925 pcc->mmu_model = POWERPC_MMU_32B; 4926 pcc->excp_model = POWERPC_EXCP_74xx; 4927 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4928 pcc->bfd_mach = bfd_mach_ppc_7400; 4929 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4930 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4931 POWERPC_FLAG_BUS_CLK; 4932 } 4933 4934 static void init_proc_e600(CPUPPCState *env) 4935 { 4936 register_non_embedded_sprs(env); 4937 register_sdr1_sprs(env); 4938 register_74xx_sprs(env); 4939 vscr_init(env, 0x00010000); 4940 4941 spr_register(env, SPR_UBAMR, "UBAMR", 4942 &spr_read_ureg, SPR_NOACCESS, 4943 &spr_read_ureg, SPR_NOACCESS, 4944 0x00000000); 4945 4946 spr_register(env, SPR_LDSTCR, "LDSTCR", 4947 SPR_NOACCESS, SPR_NOACCESS, 4948 &spr_read_generic, &spr_write_generic, 4949 0x00000000); 4950 4951 spr_register(env, SPR_ICTRL, "ICTRL", 4952 SPR_NOACCESS, SPR_NOACCESS, 4953 &spr_read_generic, &spr_write_generic, 4954 0x00000000); 4955 4956 spr_register(env, SPR_MSSSR0, "MSSSR0", 4957 SPR_NOACCESS, SPR_NOACCESS, 4958 &spr_read_generic, &spr_write_generic, 4959 0x00000000); 4960 4961 spr_register(env, SPR_7XX_PMC5, "PMC5", 4962 SPR_NOACCESS, SPR_NOACCESS, 4963 &spr_read_generic, &spr_write_generic, 4964 0x00000000); 4965 4966 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4967 &spr_read_ureg, SPR_NOACCESS, 4968 &spr_read_ureg, SPR_NOACCESS, 4969 0x00000000); 4970 4971 spr_register(env, SPR_7XX_PMC6, "PMC6", 4972 SPR_NOACCESS, SPR_NOACCESS, 4973 &spr_read_generic, &spr_write_generic, 4974 0x00000000); 4975 4976 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4977 &spr_read_ureg, SPR_NOACCESS, 4978 &spr_read_ureg, SPR_NOACCESS, 4979 0x00000000); 4980 /* SPRGs */ 4981 spr_register(env, SPR_SPRG4, "SPRG4", 4982 SPR_NOACCESS, SPR_NOACCESS, 4983 &spr_read_generic, &spr_write_generic, 4984 0x00000000); 4985 spr_register(env, SPR_USPRG4, "USPRG4", 4986 &spr_read_ureg, SPR_NOACCESS, 4987 &spr_read_ureg, SPR_NOACCESS, 4988 0x00000000); 4989 spr_register(env, SPR_SPRG5, "SPRG5", 4990 SPR_NOACCESS, SPR_NOACCESS, 4991 &spr_read_generic, &spr_write_generic, 4992 0x00000000); 4993 spr_register(env, SPR_USPRG5, "USPRG5", 4994 &spr_read_ureg, SPR_NOACCESS, 4995 &spr_read_ureg, SPR_NOACCESS, 4996 0x00000000); 4997 spr_register(env, SPR_SPRG6, "SPRG6", 4998 SPR_NOACCESS, SPR_NOACCESS, 4999 &spr_read_generic, &spr_write_generic, 5000 0x00000000); 5001 spr_register(env, SPR_USPRG6, "USPRG6", 5002 &spr_read_ureg, SPR_NOACCESS, 5003 &spr_read_ureg, SPR_NOACCESS, 5004 0x00000000); 5005 spr_register(env, SPR_SPRG7, "SPRG7", 5006 SPR_NOACCESS, SPR_NOACCESS, 5007 &spr_read_generic, &spr_write_generic, 5008 0x00000000); 5009 spr_register(env, SPR_USPRG7, "USPRG7", 5010 &spr_read_ureg, SPR_NOACCESS, 5011 &spr_read_ureg, SPR_NOACCESS, 5012 0x00000000); 5013 /* Memory management */ 5014 register_low_BATs(env); 5015 register_high_BATs(env); 5016 init_excp_7450(env); 5017 env->dcache_line_size = 32; 5018 env->icache_line_size = 32; 5019 /* Allocate hardware IRQ controller */ 5020 ppc6xx_irq_init(env_archcpu(env)); 5021 } 5022 5023 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5024 { 5025 DeviceClass *dc = DEVICE_CLASS(oc); 5026 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5027 5028 dc->desc = "PowerPC e600"; 5029 pcc->init_proc = init_proc_e600; 5030 pcc->check_pow = check_pow_hid0_74xx; 5031 pcc->check_attn = check_attn_none; 5032 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5033 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5034 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5035 PPC_FLOAT_STFIWX | 5036 PPC_CACHE | PPC_CACHE_ICBI | 5037 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5038 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5039 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5040 PPC_MEM_TLBIA | 5041 PPC_SEGMENT | PPC_EXTERN | 5042 PPC_ALTIVEC; 5043 pcc->insns_flags2 = PPC_NONE; 5044 pcc->msr_mask = (1ull << MSR_VR) | 5045 (1ull << MSR_POW) | 5046 (1ull << MSR_ILE) | 5047 (1ull << MSR_EE) | 5048 (1ull << MSR_PR) | 5049 (1ull << MSR_FP) | 5050 (1ull << MSR_ME) | 5051 (1ull << MSR_FE0) | 5052 (1ull << MSR_SE) | 5053 (1ull << MSR_DE) | 5054 (1ull << MSR_FE1) | 5055 (1ull << MSR_EP) | 5056 (1ull << MSR_IR) | 5057 (1ull << MSR_DR) | 5058 (1ull << MSR_PMM) | 5059 (1ull << MSR_RI) | 5060 (1ull << MSR_LE); 5061 pcc->mmu_model = POWERPC_MMU_32B; 5062 pcc->excp_model = POWERPC_EXCP_74xx; 5063 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5064 pcc->bfd_mach = bfd_mach_ppc_7400; 5065 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5066 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5067 POWERPC_FLAG_BUS_CLK; 5068 } 5069 5070 #if defined(TARGET_PPC64) 5071 #if defined(CONFIG_USER_ONLY) 5072 #define POWERPC970_HID5_INIT 0x00000080 5073 #else 5074 #define POWERPC970_HID5_INIT 0x00000000 5075 #endif 5076 5077 static int check_pow_970(CPUPPCState *env) 5078 { 5079 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5080 return 1; 5081 } 5082 5083 return 0; 5084 } 5085 5086 static void register_970_hid_sprs(CPUPPCState *env) 5087 { 5088 /* Hardware implementation registers */ 5089 spr_register(env, SPR_HID0, "HID0", 5090 SPR_NOACCESS, SPR_NOACCESS, 5091 &spr_read_generic, &spr_write_clear, 5092 0x60000000); 5093 spr_register(env, SPR_HID1, "HID1", 5094 SPR_NOACCESS, SPR_NOACCESS, 5095 &spr_read_generic, &spr_write_generic, 5096 0x00000000); 5097 spr_register(env, SPR_970_HID5, "HID5", 5098 SPR_NOACCESS, SPR_NOACCESS, 5099 &spr_read_generic, &spr_write_generic, 5100 POWERPC970_HID5_INIT); 5101 } 5102 5103 static void register_970_hior_sprs(CPUPPCState *env) 5104 { 5105 spr_register(env, SPR_HIOR, "HIOR", 5106 SPR_NOACCESS, SPR_NOACCESS, 5107 &spr_read_hior, &spr_write_hior, 5108 0x00000000); 5109 } 5110 5111 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5112 { 5113 spr_register(env, SPR_CTRL, "CTRL", 5114 SPR_NOACCESS, SPR_NOACCESS, 5115 SPR_NOACCESS, &spr_write_CTRL, 5116 0x00000000); 5117 spr_register(env, SPR_UCTRL, "UCTRL", 5118 &spr_read_ureg, SPR_NOACCESS, 5119 &spr_read_ureg, SPR_NOACCESS, 5120 0x00000000); 5121 } 5122 5123 static void register_book3s_altivec_sprs(CPUPPCState *env) 5124 { 5125 if (!(env->insns_flags & PPC_ALTIVEC)) { 5126 return; 5127 } 5128 5129 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5130 &spr_read_generic, &spr_write_generic32, 5131 &spr_read_generic, &spr_write_generic32, 5132 KVM_REG_PPC_VRSAVE, 0x00000000); 5133 5134 } 5135 5136 static void register_book3s_dbg_sprs(CPUPPCState *env) 5137 { 5138 /* 5139 * TODO: different specs define different scopes for these, 5140 * will have to address this: 5141 * 970: super/write and super/read 5142 * powerisa 2.03..2.04: hypv/write and super/read. 5143 * powerisa 2.05 and newer: hypv/write and hypv/read. 5144 */ 5145 spr_register_kvm(env, SPR_DABR, "DABR", 5146 SPR_NOACCESS, SPR_NOACCESS, 5147 &spr_read_generic, &spr_write_generic, 5148 KVM_REG_PPC_DABR, 0x00000000); 5149 spr_register_kvm(env, SPR_DABRX, "DABRX", 5150 SPR_NOACCESS, SPR_NOACCESS, 5151 &spr_read_generic, &spr_write_generic, 5152 KVM_REG_PPC_DABRX, 0x00000000); 5153 } 5154 5155 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5156 { 5157 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5158 SPR_NOACCESS, SPR_NOACCESS, 5159 SPR_NOACCESS, SPR_NOACCESS, 5160 &spr_read_generic, &spr_write_dawr0, 5161 KVM_REG_PPC_DAWR, 0x00000000); 5162 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5163 SPR_NOACCESS, SPR_NOACCESS, 5164 SPR_NOACCESS, SPR_NOACCESS, 5165 &spr_read_generic, &spr_write_dawrx0, 5166 KVM_REG_PPC_DAWRX, 0x00000000); 5167 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_generic, &spr_write_ciabr, 5171 KVM_REG_PPC_CIABR, 0x00000000); 5172 } 5173 5174 static void register_970_dbg_sprs(CPUPPCState *env) 5175 { 5176 /* Breakpoints */ 5177 spr_register(env, SPR_IABR, "IABR", 5178 SPR_NOACCESS, SPR_NOACCESS, 5179 &spr_read_generic, &spr_write_generic, 5180 0x00000000); 5181 } 5182 5183 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5184 { 5185 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 &spr_read_generic, &spr_write_MMCR0, 5188 KVM_REG_PPC_MMCR0, 0x80000000); 5189 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5190 SPR_NOACCESS, SPR_NOACCESS, 5191 &spr_read_generic, &spr_write_MMCR1, 5192 KVM_REG_PPC_MMCR1, 0x00000000); 5193 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5194 SPR_NOACCESS, SPR_NOACCESS, 5195 &spr_read_generic, &spr_write_MMCRA, 5196 KVM_REG_PPC_MMCRA, 0x00000000); 5197 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5198 SPR_NOACCESS, SPR_NOACCESS, 5199 &spr_read_PMC, &spr_write_PMC, 5200 KVM_REG_PPC_PMC1, 0x00000000); 5201 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5202 SPR_NOACCESS, SPR_NOACCESS, 5203 &spr_read_PMC, &spr_write_PMC, 5204 KVM_REG_PPC_PMC2, 0x00000000); 5205 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5206 SPR_NOACCESS, SPR_NOACCESS, 5207 &spr_read_PMC, &spr_write_PMC, 5208 KVM_REG_PPC_PMC3, 0x00000000); 5209 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5210 SPR_NOACCESS, SPR_NOACCESS, 5211 &spr_read_PMC, &spr_write_PMC, 5212 KVM_REG_PPC_PMC4, 0x00000000); 5213 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5214 SPR_NOACCESS, SPR_NOACCESS, 5215 &spr_read_PMC, &spr_write_PMC, 5216 KVM_REG_PPC_PMC5, 0x00000000); 5217 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5218 SPR_NOACCESS, SPR_NOACCESS, 5219 &spr_read_PMC, &spr_write_PMC, 5220 KVM_REG_PPC_PMC6, 0x00000000); 5221 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5222 SPR_NOACCESS, SPR_NOACCESS, 5223 &spr_read_generic, &spr_write_generic, 5224 KVM_REG_PPC_SIAR, 0x00000000); 5225 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5226 SPR_NOACCESS, SPR_NOACCESS, 5227 &spr_read_generic, &spr_write_generic, 5228 KVM_REG_PPC_SDAR, 0x00000000); 5229 } 5230 5231 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5232 { 5233 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5234 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5235 &spr_read_ureg, &spr_write_ureg, 5236 0x80000000); 5237 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5238 &spr_read_ureg, SPR_NOACCESS, 5239 &spr_read_ureg, &spr_write_ureg, 5240 0x00000000); 5241 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5242 &spr_read_ureg, SPR_NOACCESS, 5243 &spr_read_ureg, &spr_write_ureg, 5244 0x00000000); 5245 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5246 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5247 &spr_read_ureg, &spr_write_ureg, 5248 0x00000000); 5249 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5250 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5251 &spr_read_ureg, &spr_write_ureg, 5252 0x00000000); 5253 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5254 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5255 &spr_read_ureg, &spr_write_ureg, 5256 0x00000000); 5257 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5258 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5259 &spr_read_ureg, &spr_write_ureg, 5260 0x00000000); 5261 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5262 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5263 &spr_read_ureg, &spr_write_ureg, 5264 0x00000000); 5265 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5266 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5267 &spr_read_ureg, &spr_write_ureg, 5268 0x00000000); 5269 spr_register(env, SPR_POWER_USIAR, "USIAR", 5270 &spr_read_ureg, SPR_NOACCESS, 5271 &spr_read_ureg, &spr_write_ureg, 5272 0x00000000); 5273 spr_register(env, SPR_POWER_USDAR, "USDAR", 5274 &spr_read_ureg, SPR_NOACCESS, 5275 &spr_read_ureg, &spr_write_ureg, 5276 0x00000000); 5277 } 5278 5279 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5280 { 5281 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5282 SPR_NOACCESS, SPR_NOACCESS, 5283 &spr_read_generic, &spr_write_generic, 5284 KVM_REG_PPC_PMC7, 0x00000000); 5285 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5286 SPR_NOACCESS, SPR_NOACCESS, 5287 &spr_read_generic, &spr_write_generic, 5288 KVM_REG_PPC_PMC8, 0x00000000); 5289 } 5290 5291 static void register_970_pmu_user_sprs(CPUPPCState *env) 5292 { 5293 spr_register(env, SPR_970_UPMC7, "UPMC7", 5294 &spr_read_ureg, SPR_NOACCESS, 5295 &spr_read_ureg, &spr_write_ureg, 5296 0x00000000); 5297 spr_register(env, SPR_970_UPMC8, "UPMC8", 5298 &spr_read_ureg, SPR_NOACCESS, 5299 &spr_read_ureg, &spr_write_ureg, 5300 0x00000000); 5301 } 5302 5303 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5304 { 5305 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5306 SPR_NOACCESS, SPR_NOACCESS, 5307 &spr_read_generic, &spr_write_generic, 5308 KVM_REG_PPC_MMCR2, 0x00000000); 5309 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5310 SPR_NOACCESS, SPR_NOACCESS, 5311 &spr_read_generic, &spr_write_generic, 5312 KVM_REG_PPC_MMCRS, 0x00000000); 5313 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5314 SPR_NOACCESS, SPR_NOACCESS, 5315 &spr_read_generic, &spr_write_generic, 5316 KVM_REG_PPC_SIER, 0x00000000); 5317 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5318 SPR_NOACCESS, SPR_NOACCESS, 5319 &spr_read_generic, &spr_write_generic, 5320 KVM_REG_PPC_SPMC1, 0x00000000); 5321 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5322 SPR_NOACCESS, SPR_NOACCESS, 5323 &spr_read_generic, &spr_write_generic, 5324 KVM_REG_PPC_SPMC2, 0x00000000); 5325 spr_register_kvm(env, SPR_TACR, "TACR", 5326 SPR_NOACCESS, SPR_NOACCESS, 5327 &spr_read_generic, &spr_write_generic, 5328 KVM_REG_PPC_TACR, 0x00000000); 5329 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5330 SPR_NOACCESS, SPR_NOACCESS, 5331 &spr_read_generic, &spr_write_generic, 5332 KVM_REG_PPC_TCSCR, 0x00000000); 5333 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5334 SPR_NOACCESS, SPR_NOACCESS, 5335 &spr_read_generic, &spr_write_generic, 5336 KVM_REG_PPC_CSIGR, 0x00000000); 5337 } 5338 5339 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5340 { 5341 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5342 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5343 &spr_read_ureg, &spr_write_ureg, 5344 0x00000000); 5345 spr_register(env, SPR_POWER_USIER, "USIER", 5346 &spr_read_generic, SPR_NOACCESS, 5347 &spr_read_generic, &spr_write_generic, 5348 0x00000000); 5349 } 5350 5351 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5352 { 5353 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5354 SPR_NOACCESS, SPR_NOACCESS, 5355 &spr_read_generic, &spr_write_generic, 5356 KVM_REG_PPC_MMCR3, 0x00000000); 5357 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5358 SPR_NOACCESS, SPR_NOACCESS, 5359 &spr_read_generic, &spr_write_generic, 5360 KVM_REG_PPC_SIER2, 0x00000000); 5361 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5362 SPR_NOACCESS, SPR_NOACCESS, 5363 &spr_read_generic, &spr_write_generic, 5364 KVM_REG_PPC_SIER3, 0x00000000); 5365 } 5366 5367 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5368 { 5369 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5370 &spr_read_generic, &spr_write_generic, 5371 &spr_read_generic, &spr_write_generic, 5372 0x00000000); 5373 spr_register(env, SPR_POWER_USIER2, "USIER2", 5374 &spr_read_generic, SPR_NOACCESS, 5375 &spr_read_generic, &spr_write_generic, 5376 0x00000000); 5377 spr_register(env, SPR_POWER_USIER3, "USIER3", 5378 &spr_read_generic, SPR_NOACCESS, 5379 &spr_read_generic, &spr_write_generic, 5380 0x00000000); 5381 } 5382 5383 static void register_power5p_ear_sprs(CPUPPCState *env) 5384 { 5385 /* External access control */ 5386 spr_register(env, SPR_EAR, "EAR", 5387 SPR_NOACCESS, SPR_NOACCESS, 5388 &spr_read_generic, &spr_write_generic, 5389 0x00000000); 5390 } 5391 5392 static void register_power5p_tb_sprs(CPUPPCState *env) 5393 { 5394 /* TBU40 (High 40 bits of the Timebase register */ 5395 spr_register_hv(env, SPR_TBU40, "TBU40", 5396 SPR_NOACCESS, SPR_NOACCESS, 5397 SPR_NOACCESS, SPR_NOACCESS, 5398 SPR_NOACCESS, &spr_write_tbu40, 5399 0x00000000); 5400 } 5401 5402 static void register_970_lpar_sprs(CPUPPCState *env) 5403 { 5404 #if !defined(CONFIG_USER_ONLY) 5405 /* 5406 * PPC970: HID4 covers things later controlled by the LPCR and 5407 * RMOR in later CPUs, but with a different encoding. We only 5408 * support the 970 in "Apple mode" which has all hypervisor 5409 * facilities disabled by strapping, so we can basically just 5410 * ignore it 5411 */ 5412 spr_register(env, SPR_970_HID4, "HID4", 5413 SPR_NOACCESS, SPR_NOACCESS, 5414 &spr_read_generic, &spr_write_generic, 5415 0x00000000); 5416 #endif 5417 } 5418 5419 static void register_power5p_lpar_sprs(CPUPPCState *env) 5420 { 5421 #if !defined(CONFIG_USER_ONLY) 5422 /* Logical partitioning */ 5423 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5424 SPR_NOACCESS, SPR_NOACCESS, 5425 SPR_NOACCESS, SPR_NOACCESS, 5426 &spr_read_generic, &spr_write_lpcr, 5427 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5428 spr_register_hv(env, SPR_HDEC, "HDEC", 5429 SPR_NOACCESS, SPR_NOACCESS, 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_hdecr, &spr_write_hdecr, 0); 5432 #endif 5433 } 5434 5435 static void register_book3s_ids_sprs(CPUPPCState *env) 5436 { 5437 /* FIXME: Will need to deal with thread vs core only SPRs */ 5438 5439 /* Processor identification */ 5440 spr_register_hv(env, SPR_PIR, "PIR", 5441 SPR_NOACCESS, SPR_NOACCESS, 5442 &spr_read_generic, SPR_NOACCESS, 5443 &spr_read_generic, NULL, 5444 0x00000000); 5445 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5446 SPR_NOACCESS, SPR_NOACCESS, 5447 SPR_NOACCESS, SPR_NOACCESS, 5448 &spr_read_generic, &spr_write_lpidr, 5449 0x00000000); 5450 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5451 SPR_NOACCESS, SPR_NOACCESS, 5452 SPR_NOACCESS, SPR_NOACCESS, 5453 &spr_read_generic, &spr_write_generic, 5454 0x00000000); 5455 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5456 SPR_NOACCESS, SPR_NOACCESS, 5457 SPR_NOACCESS, SPR_NOACCESS, 5458 &spr_read_generic, &spr_core_write_generic32, 5459 0x00000000); 5460 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 SPR_NOACCESS, SPR_NOACCESS, 5463 &spr_read_generic, &spr_write_generic, 5464 0x00000000); 5465 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5466 SPR_NOACCESS, SPR_NOACCESS, 5467 SPR_NOACCESS, SPR_NOACCESS, 5468 &spr_read_generic, &spr_write_generic, 5469 0x00000000); 5470 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 SPR_NOACCESS, SPR_NOACCESS, 5473 &spr_read_generic, &spr_write_generic, 5474 0x00000000); 5475 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 SPR_NOACCESS, SPR_NOACCESS, 5478 &spr_read_generic, &spr_write_generic, 5479 0x00000000); 5480 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 SPR_NOACCESS, SPR_NOACCESS, 5483 &spr_read_generic, &spr_write_generic, 5484 0x00000000); 5485 spr_register_hv(env, SPR_HDAR, "HDAR", 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 SPR_NOACCESS, SPR_NOACCESS, 5488 &spr_read_generic, &spr_write_generic, 5489 0x00000000); 5490 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 SPR_NOACCESS, SPR_NOACCESS, 5493 &spr_read_generic, &spr_write_generic32, 5494 0x00000000); 5495 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5496 SPR_NOACCESS, SPR_NOACCESS, 5497 SPR_NOACCESS, SPR_NOACCESS, 5498 &spr_read_generic, &spr_core_write_generic, 5499 0x00000000); 5500 } 5501 5502 static void register_rmor_sprs(CPUPPCState *env) 5503 { 5504 spr_register_hv(env, SPR_RMOR, "RMOR", 5505 SPR_NOACCESS, SPR_NOACCESS, 5506 SPR_NOACCESS, SPR_NOACCESS, 5507 &spr_read_generic, &spr_write_generic, 5508 0x00000000); 5509 } 5510 5511 static void register_power8_ids_sprs(CPUPPCState *env) 5512 { 5513 /* Thread identification */ 5514 spr_register(env, SPR_TIR, "TIR", 5515 SPR_NOACCESS, SPR_NOACCESS, 5516 &spr_read_generic, SPR_NOACCESS, 5517 0x00000000); 5518 } 5519 5520 static void register_book3s_purr_sprs(CPUPPCState *env) 5521 { 5522 #if !defined(CONFIG_USER_ONLY) 5523 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5524 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5525 &spr_read_purr, SPR_NOACCESS, 5526 &spr_read_purr, SPR_NOACCESS, 5527 &spr_read_purr, &spr_write_purr, 5528 KVM_REG_PPC_PURR, 0x00000000); 5529 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5530 &spr_read_purr, SPR_NOACCESS, 5531 &spr_read_purr, SPR_NOACCESS, 5532 &spr_read_purr, &spr_write_purr, 5533 KVM_REG_PPC_SPURR, 0x00000000); 5534 #endif 5535 } 5536 5537 static void register_power6_dbg_sprs(CPUPPCState *env) 5538 { 5539 #if !defined(CONFIG_USER_ONLY) 5540 spr_register(env, SPR_CFAR, "CFAR", 5541 SPR_NOACCESS, SPR_NOACCESS, 5542 &spr_read_cfar, &spr_write_cfar, 5543 0x00000000); 5544 #endif 5545 } 5546 5547 static void register_power5p_common_sprs(CPUPPCState *env) 5548 { 5549 spr_register_kvm(env, SPR_PPR, "PPR", 5550 &spr_read_generic, &spr_write_generic, 5551 &spr_read_generic, &spr_write_generic, 5552 KVM_REG_PPC_PPR, 0x00000000); 5553 } 5554 5555 static void register_power6_common_sprs(CPUPPCState *env) 5556 { 5557 #if !defined(CONFIG_USER_ONLY) 5558 spr_register_kvm(env, SPR_DSCR, "DSCR", 5559 SPR_NOACCESS, SPR_NOACCESS, 5560 &spr_read_generic, &spr_write_generic, 5561 KVM_REG_PPC_DSCR, 0x00000000); 5562 #endif 5563 /* 5564 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5565 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5566 */ 5567 spr_register_hv(env, SPR_PCR, "PCR", 5568 SPR_NOACCESS, SPR_NOACCESS, 5569 SPR_NOACCESS, SPR_NOACCESS, 5570 &spr_read_generic, &spr_write_pcr, 5571 0x00000000); 5572 } 5573 5574 static void register_HEIR32_spr(CPUPPCState *env) 5575 { 5576 spr_register_hv(env, SPR_HEIR, "HEIR", 5577 SPR_NOACCESS, SPR_NOACCESS, 5578 SPR_NOACCESS, SPR_NOACCESS, 5579 &spr_read_generic, &spr_write_generic32, 5580 0x00000000); 5581 } 5582 5583 static void register_HEIR64_spr(CPUPPCState *env) 5584 { 5585 spr_register_hv(env, SPR_HEIR, "HEIR", 5586 SPR_NOACCESS, SPR_NOACCESS, 5587 SPR_NOACCESS, SPR_NOACCESS, 5588 &spr_read_generic, &spr_write_generic, 5589 0x00000000); 5590 } 5591 5592 static void register_power7_common_sprs(CPUPPCState *env) 5593 { 5594 spr_register(env, SPR_PPR32, "PPR32", 5595 &spr_read_ppr32, &spr_write_ppr32, 5596 &spr_read_ppr32, &spr_write_ppr32, 5597 0x00000000); 5598 } 5599 5600 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5601 { 5602 spr_register_kvm(env, SPR_TAR, "TAR", 5603 &spr_read_tar, &spr_write_tar, 5604 &spr_read_generic, &spr_write_generic, 5605 KVM_REG_PPC_TAR, 0x00000000); 5606 } 5607 5608 static void register_power8_tm_sprs(CPUPPCState *env) 5609 { 5610 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5611 &spr_read_tm, &spr_write_tm, 5612 &spr_read_tm, &spr_write_tm, 5613 KVM_REG_PPC_TFHAR, 0x00000000); 5614 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5615 &spr_read_tm, &spr_write_tm, 5616 &spr_read_tm, &spr_write_tm, 5617 KVM_REG_PPC_TFIAR, 0x00000000); 5618 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5619 &spr_read_tm, &spr_write_tm, 5620 &spr_read_tm, &spr_write_tm, 5621 KVM_REG_PPC_TEXASR, 0x00000000); 5622 spr_register(env, SPR_TEXASRU, "TEXASRU", 5623 &spr_read_tm_upper32, &spr_write_tm_upper32, 5624 &spr_read_tm_upper32, &spr_write_tm_upper32, 5625 0x00000000); 5626 } 5627 5628 static void register_power8_ebb_sprs(CPUPPCState *env) 5629 { 5630 spr_register(env, SPR_BESCRS, "BESCRS", 5631 &spr_read_ebb, &spr_write_ebb, 5632 &spr_read_generic, &spr_write_generic, 5633 0x00000000); 5634 spr_register(env, SPR_BESCRSU, "BESCRSU", 5635 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5636 &spr_read_prev_upper32, &spr_write_prev_upper32, 5637 0x00000000); 5638 spr_register(env, SPR_BESCRR, "BESCRR", 5639 &spr_read_ebb, &spr_write_ebb, 5640 &spr_read_generic, &spr_write_generic, 5641 0x00000000); 5642 spr_register(env, SPR_BESCRRU, "BESCRRU", 5643 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5644 &spr_read_prev_upper32, &spr_write_prev_upper32, 5645 0x00000000); 5646 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5647 &spr_read_ebb, &spr_write_ebb, 5648 &spr_read_generic, &spr_write_generic, 5649 KVM_REG_PPC_EBBHR, 0x00000000); 5650 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5651 &spr_read_ebb, &spr_write_ebb, 5652 &spr_read_generic, &spr_write_generic, 5653 KVM_REG_PPC_EBBRR, 0x00000000); 5654 spr_register_kvm(env, SPR_BESCR, "BESCR", 5655 &spr_read_ebb, &spr_write_ebb, 5656 &spr_read_generic, &spr_write_generic, 5657 KVM_REG_PPC_BESCR, 0x00000000); 5658 } 5659 5660 /* Virtual Time Base */ 5661 static void register_vtb_sprs(CPUPPCState *env) 5662 { 5663 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5664 SPR_NOACCESS, SPR_NOACCESS, 5665 &spr_read_vtb, SPR_NOACCESS, 5666 &spr_read_vtb, &spr_write_vtb, 5667 KVM_REG_PPC_VTB, 0x00000000); 5668 } 5669 5670 static void register_power8_fscr_sprs(CPUPPCState *env) 5671 { 5672 #if defined(CONFIG_USER_ONLY) 5673 target_ulong initval = 1ULL << FSCR_TAR; 5674 #else 5675 target_ulong initval = 0; 5676 #endif 5677 spr_register_kvm(env, SPR_FSCR, "FSCR", 5678 SPR_NOACCESS, SPR_NOACCESS, 5679 &spr_read_generic, &spr_write_generic, 5680 KVM_REG_PPC_FSCR, initval); 5681 } 5682 5683 static void register_power8_pspb_sprs(CPUPPCState *env) 5684 { 5685 spr_register_kvm(env, SPR_PSPB, "PSPB", 5686 SPR_NOACCESS, SPR_NOACCESS, 5687 &spr_read_generic, &spr_write_generic32, 5688 KVM_REG_PPC_PSPB, 0); 5689 } 5690 5691 static void register_power8_dpdes_sprs(CPUPPCState *env) 5692 { 5693 #if !defined(CONFIG_USER_ONLY) 5694 /* Directed Privileged Door-bell Exception State, used for IPI */ 5695 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5696 SPR_NOACCESS, SPR_NOACCESS, 5697 &spr_read_dpdes, SPR_NOACCESS, 5698 &spr_read_dpdes, &spr_write_dpdes, 5699 KVM_REG_PPC_DPDES, 0x00000000); 5700 #endif 5701 } 5702 5703 static void register_power8_ic_sprs(CPUPPCState *env) 5704 { 5705 #if !defined(CONFIG_USER_ONLY) 5706 spr_register_hv(env, SPR_IC, "IC", 5707 SPR_NOACCESS, SPR_NOACCESS, 5708 &spr_read_generic, SPR_NOACCESS, 5709 &spr_read_generic, &spr_write_generic, 5710 0); 5711 #endif 5712 } 5713 5714 /* SPRs specific to IBM POWER CPUs */ 5715 static void register_power_common_book4_sprs(CPUPPCState *env) 5716 { 5717 #if !defined(CONFIG_USER_ONLY) 5718 spr_register_hv(env, SPR_HID0, "HID0", 5719 SPR_NOACCESS, SPR_NOACCESS, 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_generic, &spr_core_write_generic, 5722 0x00000000); 5723 spr_register_hv(env, SPR_TSCR, "TSCR", 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 SPR_NOACCESS, SPR_NOACCESS, 5726 &spr_read_generic, &spr_core_write_generic32, 5727 0x00000000); 5728 spr_register_hv(env, SPR_HMER, "HMER", 5729 SPR_NOACCESS, SPR_NOACCESS, 5730 SPR_NOACCESS, SPR_NOACCESS, 5731 &spr_read_generic, &spr_write_hmer, 5732 0x00000000); 5733 spr_register_hv(env, SPR_HMEER, "HMEER", 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 SPR_NOACCESS, SPR_NOACCESS, 5736 &spr_read_generic, &spr_core_write_generic, 5737 0x00000000); 5738 spr_register_hv(env, SPR_TFMR, "TFMR", 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 SPR_NOACCESS, SPR_NOACCESS, 5741 &spr_read_tfmr, &spr_write_tfmr, 5742 0x00000000); 5743 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_access_nop, &spr_write_generic, 5746 &spr_access_nop, &spr_write_generic, 5747 0x00000000); 5748 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_access_nop, &spr_write_generic, 5751 &spr_access_nop, &spr_write_generic, 5752 0x00000000); 5753 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 SPR_NOACCESS, SPR_NOACCESS, 5756 &spr_read_generic, &spr_core_lpar_write_generic, 5757 0x00000000); 5758 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 SPR_NOACCESS, SPR_NOACCESS, 5761 &spr_read_generic, &spr_core_write_generic, 5762 0x00000000); 5763 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5764 SPR_NOACCESS, SPR_NOACCESS, 5765 SPR_NOACCESS, SPR_NOACCESS, 5766 &spr_read_generic, &spr_write_sprc, 5767 0x00000000); 5768 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5769 SPR_NOACCESS, SPR_NOACCESS, 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_sprd, &spr_write_sprd, 5772 0x00000000); 5773 #endif 5774 } 5775 5776 static void register_power9_book4_sprs(CPUPPCState *env) 5777 { 5778 /* Add a number of P9 book4 registers */ 5779 register_power_common_book4_sprs(env); 5780 #if !defined(CONFIG_USER_ONLY) 5781 spr_register_kvm(env, SPR_WORT, "WORT", 5782 SPR_NOACCESS, SPR_NOACCESS, 5783 &spr_read_generic, &spr_write_generic, 5784 KVM_REG_PPC_WORT, 0); 5785 #endif 5786 } 5787 5788 static void register_power8_book4_sprs(CPUPPCState *env) 5789 { 5790 /* Add a number of P8 book4 registers */ 5791 register_power_common_book4_sprs(env); 5792 #if !defined(CONFIG_USER_ONLY) 5793 spr_register_kvm(env, SPR_ACOP, "ACOP", 5794 SPR_NOACCESS, SPR_NOACCESS, 5795 &spr_read_generic, &spr_write_generic, 5796 KVM_REG_PPC_ACOP, 0); 5797 /* PID is only in BookE in ISA v2.07 */ 5798 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5799 SPR_NOACCESS, SPR_NOACCESS, 5800 &spr_read_generic, &spr_write_pidr, 5801 KVM_REG_PPC_PID, 0); 5802 spr_register_kvm(env, SPR_WORT, "WORT", 5803 SPR_NOACCESS, SPR_NOACCESS, 5804 &spr_read_generic, &spr_write_generic, 5805 KVM_REG_PPC_WORT, 0); 5806 #endif 5807 } 5808 5809 static void register_power7_book4_sprs(CPUPPCState *env) 5810 { 5811 /* Add a number of P7 book4 registers */ 5812 #if !defined(CONFIG_USER_ONLY) 5813 register_power_common_book4_sprs(env); 5814 spr_register_kvm(env, SPR_ACOP, "ACOP", 5815 SPR_NOACCESS, SPR_NOACCESS, 5816 &spr_read_generic, &spr_write_generic, 5817 KVM_REG_PPC_ACOP, 0); 5818 /* PID is only in BookE in ISA v2.06 */ 5819 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5820 SPR_NOACCESS, SPR_NOACCESS, 5821 &spr_read_generic, &spr_write_generic32, 5822 KVM_REG_PPC_PID, 0); 5823 #endif 5824 } 5825 5826 static void register_power8_rpr_sprs(CPUPPCState *env) 5827 { 5828 #if !defined(CONFIG_USER_ONLY) 5829 spr_register_hv(env, SPR_RPR, "RPR", 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 SPR_NOACCESS, SPR_NOACCESS, 5832 &spr_read_generic, &spr_core_write_generic, 5833 0x00000103070F1F3F); 5834 #endif 5835 } 5836 5837 static void register_power9_mmu_sprs(CPUPPCState *env) 5838 { 5839 #if !defined(CONFIG_USER_ONLY) 5840 /* Partition Table Control */ 5841 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 SPR_NOACCESS, SPR_NOACCESS, 5844 &spr_read_generic, &spr_write_ptcr, 5845 KVM_REG_PPC_PTCR, 0x00000000); 5846 /* Address Segment Descriptor Register */ 5847 spr_register_hv(env, SPR_ASDR, "ASDR", 5848 SPR_NOACCESS, SPR_NOACCESS, 5849 SPR_NOACCESS, SPR_NOACCESS, 5850 &spr_read_generic, &spr_write_generic, 5851 0x0000000000000000); 5852 /* PID is part of the BookS ISA from v3.0 */ 5853 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5854 SPR_NOACCESS, SPR_NOACCESS, 5855 &spr_read_generic, &spr_write_pidr, 5856 KVM_REG_PPC_PID, 0); 5857 #endif 5858 } 5859 5860 static void register_power10_hash_sprs(CPUPPCState *env) 5861 { 5862 /* 5863 * it's the OS responsibility to generate a random value for the registers 5864 * in each process' context. So, initialize it with 0 here. 5865 */ 5866 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5867 #if defined(CONFIG_USER_ONLY) 5868 /* in linux-user, setup the hash register with a random value */ 5869 GRand *rand = g_rand_new(); 5870 hashkeyr_initial_value = 5871 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5872 hashpkeyr_initial_value = 5873 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5874 g_rand_free(rand); 5875 #endif 5876 spr_register(env, SPR_HASHKEYR, "HASHKEYR", 5877 SPR_NOACCESS, SPR_NOACCESS, 5878 &spr_read_generic, &spr_write_generic, 5879 hashkeyr_initial_value); 5880 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5881 SPR_NOACCESS, SPR_NOACCESS, 5882 SPR_NOACCESS, SPR_NOACCESS, 5883 &spr_read_generic, &spr_write_generic, 5884 hashpkeyr_initial_value); 5885 } 5886 5887 static void register_power10_dexcr_sprs(CPUPPCState *env) 5888 { 5889 spr_register(env, SPR_DEXCR, "DEXCR", 5890 SPR_NOACCESS, SPR_NOACCESS, 5891 &spr_read_generic, &spr_write_generic, 5892 0); 5893 5894 spr_register(env, SPR_UDEXCR, "UDEXCR", 5895 &spr_read_dexcr_ureg, SPR_NOACCESS, 5896 &spr_read_dexcr_ureg, SPR_NOACCESS, 5897 0); 5898 5899 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 SPR_NOACCESS, SPR_NOACCESS, 5902 &spr_read_generic, &spr_write_generic, 5903 0); 5904 5905 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5906 &spr_read_dexcr_ureg, SPR_NOACCESS, 5907 &spr_read_dexcr_ureg, SPR_NOACCESS, 5908 0); 5909 } 5910 5911 /* 5912 * Initialize PMU counter overflow timers for Power8 and 5913 * newer Power chips when using TCG. 5914 */ 5915 static void init_tcg_pmu_power8(CPUPPCState *env) 5916 { 5917 /* Init PMU overflow timers */ 5918 if (tcg_enabled()) { 5919 cpu_ppc_pmu_init(env); 5920 } 5921 } 5922 5923 static void init_proc_book3s_common(CPUPPCState *env) 5924 { 5925 register_non_embedded_sprs(env); 5926 register_book3s_altivec_sprs(env); 5927 register_book3s_pmu_sup_sprs(env); 5928 register_book3s_pmu_user_sprs(env); 5929 register_book3s_ctrl_sprs(env); 5930 /* 5931 * Can't find information on what this should be on reset. This 5932 * value is the one used by 74xx processors. 5933 */ 5934 vscr_init(env, 0x00010000); 5935 5936 spr_register(env, SPR_USPRG3, "USPRG3", 5937 &spr_read_ureg, SPR_NOACCESS, 5938 &spr_read_ureg, SPR_NOACCESS, 5939 0x00000000); 5940 } 5941 5942 static void init_proc_970(CPUPPCState *env) 5943 { 5944 /* Common Registers */ 5945 init_proc_book3s_common(env); 5946 register_sdr1_sprs(env); 5947 register_book3s_dbg_sprs(env); 5948 5949 /* 970 Specific Registers */ 5950 register_970_hid_sprs(env); 5951 register_970_hior_sprs(env); 5952 register_low_BATs(env); 5953 register_970_pmu_sup_sprs(env); 5954 register_970_pmu_user_sprs(env); 5955 register_970_lpar_sprs(env); 5956 register_970_dbg_sprs(env); 5957 5958 /* env variables */ 5959 env->dcache_line_size = 128; 5960 env->icache_line_size = 128; 5961 5962 /* Allocate hardware IRQ controller */ 5963 init_excp_970(env); 5964 ppc970_irq_init(env_archcpu(env)); 5965 } 5966 5967 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5968 { 5969 DeviceClass *dc = DEVICE_CLASS(oc); 5970 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5971 5972 dc->desc = "PowerPC 970"; 5973 pcc->init_proc = init_proc_970; 5974 pcc->check_pow = check_pow_970; 5975 pcc->check_attn = check_attn_hid0; 5976 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5977 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5978 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5979 PPC_FLOAT_STFIWX | 5980 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5981 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5982 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5983 PPC_64B | PPC_ALTIVEC | 5984 PPC_SEGMENT_64B | PPC_SLBI; 5985 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 5986 pcc->msr_mask = (1ull << MSR_SF) | 5987 (1ull << MSR_VR) | 5988 (1ull << MSR_POW) | 5989 (1ull << MSR_EE) | 5990 (1ull << MSR_PR) | 5991 (1ull << MSR_FP) | 5992 (1ull << MSR_ME) | 5993 (1ull << MSR_FE0) | 5994 (1ull << MSR_SE) | 5995 (1ull << MSR_DE) | 5996 (1ull << MSR_FE1) | 5997 (1ull << MSR_IR) | 5998 (1ull << MSR_DR) | 5999 (1ull << MSR_PMM) | 6000 (1ull << MSR_RI); 6001 pcc->mmu_model = POWERPC_MMU_64B; 6002 #if !defined(CONFIG_USER_ONLY) 6003 pcc->hash64_opts = &ppc_hash64_opts_basic; 6004 #endif 6005 pcc->excp_model = POWERPC_EXCP_970; 6006 pcc->bus_model = PPC_FLAGS_INPUT_970; 6007 pcc->bfd_mach = bfd_mach_ppc64; 6008 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6009 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6010 POWERPC_FLAG_BUS_CLK; 6011 pcc->l1_dcache_size = 0x8000; 6012 pcc->l1_icache_size = 0x10000; 6013 } 6014 6015 static void init_proc_power5plus(CPUPPCState *env) 6016 { 6017 /* Common Registers */ 6018 init_proc_book3s_common(env); 6019 register_sdr1_sprs(env); 6020 register_book3s_dbg_sprs(env); 6021 6022 /* POWER5+ Specific Registers */ 6023 register_970_hid_sprs(env); 6024 register_970_hior_sprs(env); 6025 register_low_BATs(env); 6026 register_970_pmu_sup_sprs(env); 6027 register_970_pmu_user_sprs(env); 6028 register_power5p_common_sprs(env); 6029 register_power5p_lpar_sprs(env); 6030 register_power5p_ear_sprs(env); 6031 register_power5p_tb_sprs(env); 6032 6033 /* env variables */ 6034 env->dcache_line_size = 128; 6035 env->icache_line_size = 128; 6036 6037 /* Allocate hardware IRQ controller */ 6038 init_excp_970(env); 6039 ppc970_irq_init(env_archcpu(env)); 6040 } 6041 6042 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6043 { 6044 DeviceClass *dc = DEVICE_CLASS(oc); 6045 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6046 6047 dc->fw_name = "PowerPC,POWER5"; 6048 dc->desc = "POWER5+"; 6049 pcc->init_proc = init_proc_power5plus; 6050 pcc->check_pow = check_pow_970; 6051 pcc->check_attn = check_attn_hid0; 6052 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6053 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6054 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6055 PPC_FLOAT_STFIWX | 6056 PPC_FLOAT_EXT | 6057 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6058 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6059 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6060 PPC_64B | 6061 PPC_POPCNTB | 6062 PPC_SEGMENT_64B | PPC_SLBI; 6063 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6064 pcc->msr_mask = (1ull << MSR_SF) | 6065 (1ull << MSR_VR) | 6066 (1ull << MSR_POW) | 6067 (1ull << MSR_EE) | 6068 (1ull << MSR_PR) | 6069 (1ull << MSR_FP) | 6070 (1ull << MSR_ME) | 6071 (1ull << MSR_FE0) | 6072 (1ull << MSR_SE) | 6073 (1ull << MSR_DE) | 6074 (1ull << MSR_FE1) | 6075 (1ull << MSR_IR) | 6076 (1ull << MSR_DR) | 6077 (1ull << MSR_PMM) | 6078 (1ull << MSR_RI); 6079 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6080 LPCR_RMI | LPCR_HDICE; 6081 pcc->mmu_model = POWERPC_MMU_2_03; 6082 #if !defined(CONFIG_USER_ONLY) 6083 pcc->hash64_opts = &ppc_hash64_opts_basic; 6084 pcc->lrg_decr_bits = 32; 6085 #endif 6086 pcc->excp_model = POWERPC_EXCP_970; 6087 pcc->bus_model = PPC_FLAGS_INPUT_970; 6088 pcc->bfd_mach = bfd_mach_ppc64; 6089 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6090 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6091 POWERPC_FLAG_BUS_CLK; 6092 pcc->l1_dcache_size = 0x8000; 6093 pcc->l1_icache_size = 0x10000; 6094 } 6095 6096 static void init_proc_POWER7(CPUPPCState *env) 6097 { 6098 /* Common Registers */ 6099 init_proc_book3s_common(env); 6100 register_sdr1_sprs(env); 6101 register_book3s_dbg_sprs(env); 6102 6103 /* POWER7 Specific Registers */ 6104 register_book3s_ids_sprs(env); 6105 register_rmor_sprs(env); 6106 register_amr_sprs(env); 6107 register_book3s_purr_sprs(env); 6108 register_power5p_common_sprs(env); 6109 register_power5p_lpar_sprs(env); 6110 register_power5p_ear_sprs(env); 6111 register_power5p_tb_sprs(env); 6112 register_power6_common_sprs(env); 6113 register_HEIR32_spr(env); 6114 register_power6_dbg_sprs(env); 6115 register_power7_common_sprs(env); 6116 register_power7_book4_sprs(env); 6117 6118 /* env variables */ 6119 env->dcache_line_size = 128; 6120 env->icache_line_size = 128; 6121 6122 /* Allocate hardware IRQ controller */ 6123 init_excp_POWER7(env); 6124 ppcPOWER7_irq_init(env_archcpu(env)); 6125 } 6126 6127 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6128 { 6129 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6130 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6131 6132 if (!best) { 6133 if (base == CPU_POWERPC_POWER7_BASE) { 6134 return true; 6135 } 6136 if (base == CPU_POWERPC_POWER7P_BASE) { 6137 return true; 6138 } 6139 } 6140 6141 if (base != pcc_base) { 6142 return false; 6143 } 6144 6145 return true; 6146 } 6147 6148 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6149 { 6150 DeviceClass *dc = DEVICE_CLASS(oc); 6151 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6152 6153 dc->fw_name = "PowerPC,POWER7"; 6154 dc->desc = "POWER7"; 6155 pcc->pvr_match = ppc_pvr_match_power7; 6156 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6157 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6158 pcc->init_proc = init_proc_POWER7; 6159 pcc->check_pow = check_pow_nocheck; 6160 pcc->check_attn = check_attn_hid0; 6161 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6162 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6163 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6164 PPC_FLOAT_FRSQRTES | 6165 PPC_FLOAT_STFIWX | 6166 PPC_FLOAT_EXT | 6167 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6168 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6169 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6170 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6171 PPC_SEGMENT_64B | PPC_SLBI | 6172 PPC_POPCNTB | PPC_POPCNTWD | 6173 PPC_CILDST; 6174 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6175 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6176 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6177 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6178 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6179 pcc->msr_mask = (1ull << MSR_SF) | 6180 (1ull << MSR_VR) | 6181 (1ull << MSR_VSX) | 6182 (1ull << MSR_EE) | 6183 (1ull << MSR_PR) | 6184 (1ull << MSR_FP) | 6185 (1ull << MSR_ME) | 6186 (1ull << MSR_FE0) | 6187 (1ull << MSR_SE) | 6188 (1ull << MSR_DE) | 6189 (1ull << MSR_FE1) | 6190 (1ull << MSR_IR) | 6191 (1ull << MSR_DR) | 6192 (1ull << MSR_PMM) | 6193 (1ull << MSR_RI) | 6194 (1ull << MSR_LE); 6195 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6196 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6197 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6198 LPCR_MER | LPCR_TC | 6199 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6200 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6201 pcc->mmu_model = POWERPC_MMU_2_06; 6202 #if !defined(CONFIG_USER_ONLY) 6203 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6204 pcc->lrg_decr_bits = 32; 6205 #endif 6206 pcc->excp_model = POWERPC_EXCP_POWER7; 6207 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6208 pcc->bfd_mach = bfd_mach_ppc64; 6209 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6210 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6211 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6212 POWERPC_FLAG_VSX; 6213 pcc->l1_dcache_size = 0x8000; 6214 pcc->l1_icache_size = 0x8000; 6215 } 6216 6217 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6218 { 6219 if (env->flags & POWERPC_FLAG_BHRB) { 6220 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6221 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6222 } 6223 env->bhrb_num_entries = 1 << num_entries_log2; 6224 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6225 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6226 } 6227 } 6228 6229 static void bhrb_reset_state(CPUPPCState *env) 6230 { 6231 if (env->flags & POWERPC_FLAG_BHRB) { 6232 env->bhrb_offset = 0; 6233 env->bhrb_filter = 0; 6234 memset(env->bhrb, 0, sizeof(env->bhrb)); 6235 } 6236 } 6237 6238 #define POWER8_BHRB_ENTRIES_LOG2 5 6239 static void init_proc_POWER8(CPUPPCState *env) 6240 { 6241 /* Common Registers */ 6242 init_proc_book3s_common(env); 6243 register_sdr1_sprs(env); 6244 register_book3s_207_dbg_sprs(env); 6245 6246 /* Common TCG PMU */ 6247 init_tcg_pmu_power8(env); 6248 6249 /* POWER8 Specific Registers */ 6250 register_book3s_ids_sprs(env); 6251 register_rmor_sprs(env); 6252 register_amr_sprs(env); 6253 register_iamr_sprs(env); 6254 register_book3s_purr_sprs(env); 6255 register_power5p_common_sprs(env); 6256 register_power5p_lpar_sprs(env); 6257 register_power5p_ear_sprs(env); 6258 register_power5p_tb_sprs(env); 6259 register_power6_common_sprs(env); 6260 register_HEIR32_spr(env); 6261 register_power6_dbg_sprs(env); 6262 register_power7_common_sprs(env); 6263 register_power8_tce_address_control_sprs(env); 6264 register_power8_ids_sprs(env); 6265 register_power8_ebb_sprs(env); 6266 register_power8_fscr_sprs(env); 6267 register_power8_pmu_sup_sprs(env); 6268 register_power8_pmu_user_sprs(env); 6269 register_power8_tm_sprs(env); 6270 register_power8_pspb_sprs(env); 6271 register_power8_dpdes_sprs(env); 6272 register_vtb_sprs(env); 6273 register_power8_ic_sprs(env); 6274 register_power8_book4_sprs(env); 6275 register_power8_rpr_sprs(env); 6276 6277 /* env variables */ 6278 env->dcache_line_size = 128; 6279 env->icache_line_size = 128; 6280 6281 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6282 6283 /* Allocate hardware IRQ controller */ 6284 init_excp_POWER8(env); 6285 ppcPOWER7_irq_init(env_archcpu(env)); 6286 } 6287 6288 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6289 { 6290 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6291 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6292 6293 if (!best) { 6294 if (base == CPU_POWERPC_POWER8_BASE) { 6295 return true; 6296 } 6297 if (base == CPU_POWERPC_POWER8E_BASE) { 6298 return true; 6299 } 6300 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6301 return true; 6302 } 6303 } 6304 if (base != pcc_base) { 6305 return false; 6306 } 6307 6308 return true; 6309 } 6310 6311 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6312 { 6313 DeviceClass *dc = DEVICE_CLASS(oc); 6314 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6315 6316 dc->fw_name = "PowerPC,POWER8"; 6317 dc->desc = "POWER8"; 6318 pcc->pvr_match = ppc_pvr_match_power8; 6319 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6320 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6321 pcc->init_proc = init_proc_POWER8; 6322 pcc->check_pow = check_pow_nocheck; 6323 pcc->check_attn = check_attn_hid0; 6324 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6326 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6327 PPC_FLOAT_FRSQRTES | 6328 PPC_FLOAT_STFIWX | 6329 PPC_FLOAT_EXT | 6330 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6331 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6333 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6334 PPC_SEGMENT_64B | PPC_SLBI | 6335 PPC_POPCNTB | PPC_POPCNTWD | 6336 PPC_CILDST; 6337 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6338 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6339 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6340 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6341 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6342 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6343 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6344 PPC2_BCDA_ISA206; 6345 pcc->msr_mask = (1ull << MSR_SF) | 6346 (1ull << MSR_HV) | 6347 (1ull << MSR_TM) | 6348 (1ull << MSR_VR) | 6349 (1ull << MSR_VSX) | 6350 (1ull << MSR_EE) | 6351 (1ull << MSR_PR) | 6352 (1ull << MSR_FP) | 6353 (1ull << MSR_ME) | 6354 (1ull << MSR_FE0) | 6355 (1ull << MSR_SE) | 6356 (1ull << MSR_DE) | 6357 (1ull << MSR_FE1) | 6358 (1ull << MSR_IR) | 6359 (1ull << MSR_DR) | 6360 (1ull << MSR_PMM) | 6361 (1ull << MSR_RI) | 6362 (1ull << MSR_TS0) | 6363 (1ull << MSR_TS1) | 6364 (1ull << MSR_LE); 6365 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6366 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6367 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6368 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6369 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6370 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6371 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6372 pcc->mmu_model = POWERPC_MMU_2_07; 6373 #if !defined(CONFIG_USER_ONLY) 6374 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6375 pcc->lrg_decr_bits = 32; 6376 pcc->n_host_threads = 8; 6377 #endif 6378 pcc->excp_model = POWERPC_EXCP_POWER8; 6379 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6380 pcc->bfd_mach = bfd_mach_ppc64; 6381 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6382 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6383 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6384 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6385 pcc->l1_dcache_size = 0x8000; 6386 pcc->l1_icache_size = 0x8000; 6387 } 6388 6389 #ifndef CONFIG_USER_ONLY 6390 /* 6391 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6392 * Encoded as array of int_32s in the form: 6393 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6394 * x -> AP encoding 6395 * y -> radix mode supported page size (encoded as a shift) 6396 */ 6397 static struct ppc_radix_page_info POWER9_radix_page_info = { 6398 .count = 4, 6399 .entries = { 6400 0x0000000c, /* 4K - enc: 0x0 */ 6401 0xa0000010, /* 64K - enc: 0x5 */ 6402 0x20000015, /* 2M - enc: 0x1 */ 6403 0x4000001e /* 1G - enc: 0x2 */ 6404 } 6405 }; 6406 #endif /* CONFIG_USER_ONLY */ 6407 6408 #define POWER9_BHRB_ENTRIES_LOG2 5 6409 static void init_proc_POWER9(CPUPPCState *env) 6410 { 6411 /* Common Registers */ 6412 init_proc_book3s_common(env); 6413 register_book3s_207_dbg_sprs(env); 6414 6415 /* Common TCG PMU */ 6416 init_tcg_pmu_power8(env); 6417 6418 /* POWER8 Specific Registers */ 6419 register_book3s_ids_sprs(env); 6420 register_amr_sprs(env); 6421 register_iamr_sprs(env); 6422 register_book3s_purr_sprs(env); 6423 register_power5p_common_sprs(env); 6424 register_power5p_lpar_sprs(env); 6425 register_power5p_ear_sprs(env); 6426 register_power5p_tb_sprs(env); 6427 register_power6_common_sprs(env); 6428 register_HEIR32_spr(env); 6429 register_power6_dbg_sprs(env); 6430 register_power7_common_sprs(env); 6431 register_power8_tce_address_control_sprs(env); 6432 register_power8_ids_sprs(env); 6433 register_power8_ebb_sprs(env); 6434 register_power8_fscr_sprs(env); 6435 register_power8_pmu_sup_sprs(env); 6436 register_power8_pmu_user_sprs(env); 6437 register_power8_tm_sprs(env); 6438 register_power8_pspb_sprs(env); 6439 register_power8_dpdes_sprs(env); 6440 register_vtb_sprs(env); 6441 register_power8_ic_sprs(env); 6442 register_power9_book4_sprs(env); 6443 register_power8_rpr_sprs(env); 6444 register_power9_mmu_sprs(env); 6445 6446 /* POWER9 Specific registers */ 6447 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6448 spr_read_generic, spr_write_generic, 6449 KVM_REG_PPC_TIDR, 0); 6450 6451 /* FIXME: Filter fields properly based on privilege level */ 6452 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6453 spr_read_generic, spr_write_generic, 6454 KVM_REG_PPC_PSSCR, 0); 6455 6456 /* env variables */ 6457 env->dcache_line_size = 128; 6458 env->icache_line_size = 128; 6459 6460 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6461 6462 /* Allocate hardware IRQ controller */ 6463 init_excp_POWER9(env); 6464 ppcPOWER9_irq_init(env_archcpu(env)); 6465 } 6466 6467 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6468 { 6469 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6470 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6471 6472 if (!best) { 6473 if (base == CPU_POWERPC_POWER9_BASE) { 6474 return true; 6475 } 6476 } 6477 6478 if (base != pcc_base) { 6479 return false; 6480 } 6481 6482 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6483 /* Major DD version does not match */ 6484 return false; 6485 } 6486 6487 if ((pvr & 0x0f00) == 0x200) { 6488 if ((pvr & 0xf) < 2) { 6489 /* DD2.0, DD2.1 match power9_v2.0 */ 6490 if ((pcc->pvr & 0xf) == 0) { 6491 return true; 6492 } 6493 } else { 6494 /* DD2.2, DD2.3 match power9_v2.2 */ 6495 if ((pcc->pvr & 0xf) == 2) { 6496 return true; 6497 } 6498 } 6499 } 6500 6501 return false; 6502 } 6503 6504 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6505 { 6506 DeviceClass *dc = DEVICE_CLASS(oc); 6507 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6508 6509 dc->fw_name = "PowerPC,POWER9"; 6510 dc->desc = "POWER9"; 6511 pcc->pvr_match = ppc_pvr_match_power9; 6512 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6513 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6514 PCR_COMPAT_2_05; 6515 pcc->init_proc = init_proc_POWER9; 6516 pcc->check_pow = check_pow_nocheck; 6517 pcc->check_attn = check_attn_hid0_power9; 6518 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6521 PPC_FLOAT_FRSQRTES | 6522 PPC_FLOAT_STFIWX | 6523 PPC_FLOAT_EXT | 6524 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6525 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6526 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6527 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6528 PPC_SEGMENT_64B | PPC_SLBI | 6529 PPC_POPCNTB | PPC_POPCNTWD | 6530 PPC_CILDST; 6531 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6532 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6533 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6534 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6535 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6536 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6537 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC | 6538 PPC2_BCDA_ISA206; 6539 pcc->msr_mask = (1ull << MSR_SF) | 6540 (1ull << MSR_HV) | 6541 (1ull << MSR_TM) | 6542 (1ull << MSR_VR) | 6543 (1ull << MSR_VSX) | 6544 (1ull << MSR_EE) | 6545 (1ull << MSR_PR) | 6546 (1ull << MSR_FP) | 6547 (1ull << MSR_ME) | 6548 (1ull << MSR_FE0) | 6549 (1ull << MSR_SE) | 6550 (1ull << MSR_DE) | 6551 (1ull << MSR_FE1) | 6552 (1ull << MSR_IR) | 6553 (1ull << MSR_DR) | 6554 (1ull << MSR_PMM) | 6555 (1ull << MSR_RI) | 6556 (1ull << MSR_LE); 6557 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6558 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6559 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6560 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6561 LPCR_DEE | LPCR_OEE)) 6562 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6563 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6564 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6565 pcc->mmu_model = POWERPC_MMU_3_00; 6566 #if !defined(CONFIG_USER_ONLY) 6567 /* segment page size remain the same */ 6568 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6569 pcc->radix_page_info = &POWER9_radix_page_info; 6570 pcc->lrg_decr_bits = 56; 6571 pcc->n_host_threads = 4; 6572 #endif 6573 pcc->excp_model = POWERPC_EXCP_POWER9; 6574 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6575 pcc->bfd_mach = bfd_mach_ppc64; 6576 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6577 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6578 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6579 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6580 pcc->l1_dcache_size = 0x8000; 6581 pcc->l1_icache_size = 0x8000; 6582 } 6583 6584 #ifndef CONFIG_USER_ONLY 6585 /* 6586 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6587 * Encoded as array of int_32s in the form: 6588 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6589 * x -> AP encoding 6590 * y -> radix mode supported page size (encoded as a shift) 6591 */ 6592 static struct ppc_radix_page_info POWER10_radix_page_info = { 6593 .count = 4, 6594 .entries = { 6595 0x0000000c, /* 4K - enc: 0x0 */ 6596 0xa0000010, /* 64K - enc: 0x5 */ 6597 0x20000015, /* 2M - enc: 0x1 */ 6598 0x4000001e /* 1G - enc: 0x2 */ 6599 } 6600 }; 6601 #endif /* !CONFIG_USER_ONLY */ 6602 6603 #define POWER10_BHRB_ENTRIES_LOG2 5 6604 static void init_proc_POWER10(CPUPPCState *env) 6605 { 6606 /* Common Registers */ 6607 init_proc_book3s_common(env); 6608 register_book3s_207_dbg_sprs(env); 6609 6610 /* Common TCG PMU */ 6611 init_tcg_pmu_power8(env); 6612 6613 /* POWER8 Specific Registers */ 6614 register_book3s_ids_sprs(env); 6615 register_amr_sprs(env); 6616 register_iamr_sprs(env); 6617 register_book3s_purr_sprs(env); 6618 register_power5p_common_sprs(env); 6619 register_power5p_lpar_sprs(env); 6620 register_power5p_ear_sprs(env); 6621 register_power5p_tb_sprs(env); 6622 register_power6_common_sprs(env); 6623 register_HEIR64_spr(env); 6624 register_power6_dbg_sprs(env); 6625 register_power7_common_sprs(env); 6626 register_power8_tce_address_control_sprs(env); 6627 register_power8_ids_sprs(env); 6628 register_power8_ebb_sprs(env); 6629 register_power8_fscr_sprs(env); 6630 register_power8_pmu_sup_sprs(env); 6631 register_power8_pmu_user_sprs(env); 6632 register_power8_tm_sprs(env); 6633 register_power8_pspb_sprs(env); 6634 register_power8_dpdes_sprs(env); 6635 register_vtb_sprs(env); 6636 register_power8_ic_sprs(env); 6637 register_power9_book4_sprs(env); 6638 register_power8_rpr_sprs(env); 6639 register_power9_mmu_sprs(env); 6640 register_power10_hash_sprs(env); 6641 register_power10_dexcr_sprs(env); 6642 register_power10_pmu_sup_sprs(env); 6643 register_power10_pmu_user_sprs(env); 6644 6645 /* FIXME: Filter fields properly based on privilege level */ 6646 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6647 spr_read_generic, spr_write_generic, 6648 KVM_REG_PPC_PSSCR, 0); 6649 6650 /* env variables */ 6651 env->dcache_line_size = 128; 6652 env->icache_line_size = 128; 6653 6654 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6655 6656 /* Allocate hardware IRQ controller */ 6657 init_excp_POWER10(env); 6658 ppcPOWER9_irq_init(env_archcpu(env)); 6659 } 6660 6661 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6662 { 6663 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6664 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6665 6666 if (!best) { 6667 if (base == CPU_POWERPC_POWER10_BASE) { 6668 return true; 6669 } 6670 } 6671 6672 if (base != pcc_base) { 6673 return false; 6674 } 6675 6676 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6677 /* Major DD version matches power10_v2.0 */ 6678 return true; 6679 } 6680 6681 return false; 6682 } 6683 6684 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6685 { 6686 DeviceClass *dc = DEVICE_CLASS(oc); 6687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6688 6689 dc->fw_name = "PowerPC,POWER10"; 6690 dc->desc = "POWER10"; 6691 pcc->pvr_match = ppc_pvr_match_power10; 6692 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 6693 PCR_COMPAT_3_00; 6694 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 6695 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6696 pcc->init_proc = init_proc_POWER10; 6697 pcc->check_pow = check_pow_nocheck; 6698 pcc->check_attn = check_attn_hid0_power9; 6699 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6700 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6701 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6702 PPC_FLOAT_FRSQRTES | 6703 PPC_FLOAT_STFIWX | 6704 PPC_FLOAT_EXT | 6705 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6706 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6707 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6708 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6709 PPC_SEGMENT_64B | PPC_SLBI | 6710 PPC_POPCNTB | PPC_POPCNTWD | 6711 PPC_CILDST; 6712 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6713 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6714 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6715 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6716 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6717 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6718 PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | 6719 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6720 pcc->msr_mask = (1ull << MSR_SF) | 6721 (1ull << MSR_HV) | 6722 (1ull << MSR_VR) | 6723 (1ull << MSR_VSX) | 6724 (1ull << MSR_EE) | 6725 (1ull << MSR_PR) | 6726 (1ull << MSR_FP) | 6727 (1ull << MSR_ME) | 6728 (1ull << MSR_FE0) | 6729 (1ull << MSR_SE) | 6730 (1ull << MSR_DE) | 6731 (1ull << MSR_FE1) | 6732 (1ull << MSR_IR) | 6733 (1ull << MSR_DR) | 6734 (1ull << MSR_PMM) | 6735 (1ull << MSR_RI) | 6736 (1ull << MSR_LE); 6737 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6738 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6739 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6740 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6741 LPCR_DEE | LPCR_OEE)) 6742 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6743 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6744 /* DD2 adds an extra HAIL bit */ 6745 pcc->lpcr_mask |= LPCR_HAIL; 6746 6747 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6748 pcc->mmu_model = POWERPC_MMU_3_00; 6749 #if !defined(CONFIG_USER_ONLY) 6750 /* segment page size remain the same */ 6751 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6752 pcc->radix_page_info = &POWER10_radix_page_info; 6753 pcc->lrg_decr_bits = 56; 6754 #endif 6755 pcc->excp_model = POWERPC_EXCP_POWER10; 6756 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6757 pcc->bfd_mach = bfd_mach_ppc64; 6758 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6759 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6760 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6761 POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | 6762 POWERPC_FLAG_BHRB; 6763 pcc->l1_dcache_size = 0x8000; 6764 pcc->l1_icache_size = 0x8000; 6765 } 6766 6767 #if !defined(CONFIG_USER_ONLY) 6768 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6769 { 6770 CPUPPCState *env = &cpu->env; 6771 6772 cpu->vhyp = vhyp; 6773 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6774 6775 /* 6776 * With a virtual hypervisor mode we never allow the CPU to go 6777 * hypervisor mode itself 6778 */ 6779 env->msr_mask &= ~MSR_HVB; 6780 } 6781 6782 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6783 { 6784 CPUPPCState *env = &cpu->env; 6785 6786 /* 6787 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6788 * between threads. 6789 */ 6790 if (env->flags & POWERPC_FLAG_SMT) { 6791 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6792 } 6793 } 6794 #endif /* !defined(CONFIG_USER_ONLY) */ 6795 6796 #endif /* defined(TARGET_PPC64) */ 6797 6798 /*****************************************************************************/ 6799 /* Generic CPU instantiation routine */ 6800 static void init_ppc_proc(PowerPCCPU *cpu) 6801 { 6802 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6803 CPUPPCState *env = &cpu->env; 6804 #if !defined(CONFIG_USER_ONLY) 6805 int i; 6806 6807 /* Set all exception vectors to an invalid address */ 6808 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6809 env->excp_vectors[i] = (target_ulong)(-1ULL); 6810 } 6811 env->ivor_mask = 0x00000000; 6812 env->ivpr_mask = 0x00000000; 6813 /* Default MMU definitions */ 6814 env->nb_BATs = 0; 6815 env->nb_tlb = 0; 6816 env->nb_ways = 0; 6817 env->tlb_type = TLB_NONE; 6818 #endif 6819 /* Register SPR common to all PowerPC implementations */ 6820 register_generic_sprs(cpu); 6821 6822 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6823 (*pcc->init_proc)(env); 6824 6825 /* MSR bits & flags consistency checks */ 6826 if (env->msr_mask & (1 << 25)) { 6827 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6828 case POWERPC_FLAG_SPE: 6829 case POWERPC_FLAG_VRE: 6830 break; 6831 default: 6832 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6833 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6834 exit(1); 6835 } 6836 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6837 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6838 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6839 exit(1); 6840 } 6841 if (env->msr_mask & (1 << 17)) { 6842 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6843 case POWERPC_FLAG_TGPR: 6844 case POWERPC_FLAG_CE: 6845 break; 6846 default: 6847 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6848 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6849 exit(1); 6850 } 6851 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6852 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6853 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6854 exit(1); 6855 } 6856 if (env->msr_mask & (1 << 10)) { 6857 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6858 POWERPC_FLAG_UBLE)) { 6859 case POWERPC_FLAG_SE: 6860 case POWERPC_FLAG_DWE: 6861 case POWERPC_FLAG_UBLE: 6862 break; 6863 default: 6864 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6865 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6866 "POWERPC_FLAG_UBLE\n"); 6867 exit(1); 6868 } 6869 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6870 POWERPC_FLAG_UBLE)) { 6871 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6872 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6873 "POWERPC_FLAG_UBLE\n"); 6874 exit(1); 6875 } 6876 if (env->msr_mask & (1 << 9)) { 6877 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6878 case POWERPC_FLAG_BE: 6879 case POWERPC_FLAG_DE: 6880 break; 6881 default: 6882 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6883 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6884 exit(1); 6885 } 6886 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6887 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6888 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6889 exit(1); 6890 } 6891 if (env->msr_mask & (1 << 2)) { 6892 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6893 case POWERPC_FLAG_PX: 6894 case POWERPC_FLAG_PMM: 6895 break; 6896 default: 6897 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6898 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6899 exit(1); 6900 } 6901 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6902 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6903 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6904 exit(1); 6905 } 6906 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6907 fprintf(stderr, "PowerPC flags inconsistency\n" 6908 "Should define the time-base and decrementer clock source\n"); 6909 exit(1); 6910 } 6911 /* Allocate TLBs buffer when needed */ 6912 #if !defined(CONFIG_USER_ONLY) 6913 if (env->nb_tlb) { 6914 switch (env->tlb_type) { 6915 case TLB_6XX: 6916 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6917 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6918 break; 6919 case TLB_EMB: 6920 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6921 break; 6922 case TLB_MAS: 6923 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6924 break; 6925 } 6926 /* Pre-compute some useful values */ 6927 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6928 } 6929 #endif 6930 if (env->check_pow == NULL) { 6931 warn_report("no power management check handler registered." 6932 " Attempt QEMU to crash very soon !"); 6933 } 6934 6935 if (env->check_attn == NULL) { 6936 warn_report("no attn check handler registered." 6937 " Attempt QEMU to crash very soon !"); 6938 } 6939 } 6940 6941 6942 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6943 { 6944 CPUState *cs = CPU(dev); 6945 PowerPCCPU *cpu = POWERPC_CPU(dev); 6946 CPUPPCState *env = &cpu->env; 6947 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6948 Error *local_err = NULL; 6949 6950 cpu_exec_realizefn(cs, &local_err); 6951 if (local_err != NULL) { 6952 error_propagate(errp, local_err); 6953 return; 6954 } 6955 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6956 cpu->vcpu_id = cs->cpu_index; 6957 } 6958 6959 if (tcg_enabled()) { 6960 if (ppc_fixup_cpu(cpu) != 0) { 6961 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6962 goto unrealize; 6963 } 6964 } 6965 6966 create_ppc_opcodes(cpu, &local_err); 6967 if (local_err != NULL) { 6968 error_propagate(errp, local_err); 6969 goto unrealize; 6970 } 6971 init_ppc_proc(cpu); 6972 6973 ppc_gdb_init(cs, pcc); 6974 qemu_init_vcpu(cs); 6975 6976 pcc->parent_realize(dev, errp); 6977 6978 if (env_cpu(env)->nr_threads > 1) { 6979 env->flags |= POWERPC_FLAG_SMT; 6980 } 6981 6982 return; 6983 6984 unrealize: 6985 cpu_exec_unrealizefn(cs); 6986 } 6987 6988 static void ppc_cpu_unrealize(DeviceState *dev) 6989 { 6990 PowerPCCPU *cpu = POWERPC_CPU(dev); 6991 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6992 6993 pcc->parent_unrealize(dev); 6994 6995 cpu_remove_sync(CPU(cpu)); 6996 6997 destroy_ppc_opcodes(cpu); 6998 } 6999 7000 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7001 { 7002 ObjectClass *oc = (ObjectClass *)a; 7003 uint32_t pvr = *(uint32_t *)b; 7004 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7005 7006 /* -cpu host does a PVR lookup during construction */ 7007 if (unlikely(strcmp(object_class_get_name(oc), 7008 TYPE_HOST_POWERPC_CPU) == 0)) { 7009 return -1; 7010 } 7011 7012 return pcc->pvr == pvr ? 0 : -1; 7013 } 7014 7015 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7016 { 7017 GSList *list, *item; 7018 PowerPCCPUClass *pcc = NULL; 7019 7020 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7021 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7022 if (item != NULL) { 7023 pcc = POWERPC_CPU_CLASS(item->data); 7024 } 7025 g_slist_free(list); 7026 7027 return pcc; 7028 } 7029 7030 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7031 { 7032 ObjectClass *oc = (ObjectClass *)a; 7033 uint32_t pvr = *(uint32_t *)b; 7034 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7035 7036 /* -cpu host does a PVR lookup during construction */ 7037 if (unlikely(strcmp(object_class_get_name(oc), 7038 TYPE_HOST_POWERPC_CPU) == 0)) { 7039 return -1; 7040 } 7041 7042 if (pcc->pvr_match(pcc, pvr, true)) { 7043 return 0; 7044 } 7045 7046 return -1; 7047 } 7048 7049 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7050 { 7051 GSList *list, *item; 7052 PowerPCCPUClass *pcc = NULL; 7053 7054 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7055 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7056 if (item != NULL) { 7057 pcc = POWERPC_CPU_CLASS(item->data); 7058 } 7059 g_slist_free(list); 7060 7061 return pcc; 7062 } 7063 7064 static const char *ppc_cpu_lookup_alias(const char *alias) 7065 { 7066 int ai; 7067 7068 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7069 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7070 return ppc_cpu_aliases[ai].model; 7071 } 7072 } 7073 7074 return NULL; 7075 } 7076 7077 ObjectClass *ppc_cpu_class_by_name(const char *name) 7078 { 7079 char *cpu_model, *typename; 7080 ObjectClass *oc; 7081 const char *p; 7082 unsigned long pvr; 7083 7084 /* 7085 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7086 * 0x prefix if present) 7087 */ 7088 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7089 int len = p - name; 7090 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7091 if ((len == 8) && (*p == '\0')) { 7092 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7093 } 7094 } 7095 7096 /* 7097 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7098 * do not have a "max" CPU with all possible emulated features enabled. 7099 * Return the default CPU type for the machine because that has greater 7100 * chance of being useful as the "max" CPU. 7101 */ 7102 #if !defined(CONFIG_USER_ONLY) 7103 if (strcmp(name, "max") == 0) { 7104 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7105 if (mc) { 7106 return object_class_by_name(mc->default_cpu_type); 7107 } 7108 } 7109 #endif 7110 7111 cpu_model = g_ascii_strdown(name, -1); 7112 p = ppc_cpu_lookup_alias(cpu_model); 7113 if (p) { 7114 g_free(cpu_model); 7115 cpu_model = g_strdup(p); 7116 } 7117 7118 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7119 oc = object_class_by_name(typename); 7120 g_free(typename); 7121 g_free(cpu_model); 7122 7123 return oc; 7124 } 7125 7126 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7127 { 7128 ObjectClass *oc = OBJECT_CLASS(pcc); 7129 7130 while (oc && !object_class_is_abstract(oc)) { 7131 oc = object_class_get_parent(oc); 7132 } 7133 assert(oc); 7134 7135 return POWERPC_CPU_CLASS(oc); 7136 } 7137 7138 /* Sort by PVR, ordering special case "host" last. */ 7139 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7140 { 7141 ObjectClass *oc_a = (ObjectClass *)a; 7142 ObjectClass *oc_b = (ObjectClass *)b; 7143 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7144 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7145 const char *name_a = object_class_get_name(oc_a); 7146 const char *name_b = object_class_get_name(oc_b); 7147 7148 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7149 return 1; 7150 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7151 return -1; 7152 } else { 7153 /* Avoid an integer overflow during subtraction */ 7154 if (pcc_a->pvr < pcc_b->pvr) { 7155 return -1; 7156 } else if (pcc_a->pvr > pcc_b->pvr) { 7157 return 1; 7158 } else { 7159 return 0; 7160 } 7161 } 7162 } 7163 7164 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7165 { 7166 ObjectClass *oc = data; 7167 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7168 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7169 const char *typename = object_class_get_name(oc); 7170 char *name; 7171 int i; 7172 7173 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7174 return; 7175 } 7176 7177 name = cpu_model_from_type(typename); 7178 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7179 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7180 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7181 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7182 7183 if (alias_oc != oc) { 7184 continue; 7185 } 7186 /* 7187 * If running with KVM, we might update the family alias later, so 7188 * avoid printing the wrong alias here and use "preferred" instead 7189 */ 7190 if (strcmp(alias->alias, family->desc) == 0) { 7191 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7192 alias->alias, family->desc); 7193 } else { 7194 qemu_printf(" %-16s (alias for %s)\n", 7195 alias->alias, name); 7196 } 7197 } 7198 g_free(name); 7199 } 7200 7201 void ppc_cpu_list(void) 7202 { 7203 GSList *list; 7204 7205 qemu_printf("Available CPUs:\n"); 7206 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7207 list = g_slist_sort(list, ppc_cpu_list_compare); 7208 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7209 g_slist_free(list); 7210 7211 #ifdef CONFIG_KVM 7212 qemu_printf("\n"); 7213 qemu_printf(" %s\n", "host"); 7214 #endif 7215 } 7216 7217 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7218 { 7219 PowerPCCPU *cpu = POWERPC_CPU(cs); 7220 7221 cpu->env.nip = value; 7222 } 7223 7224 static vaddr ppc_cpu_get_pc(CPUState *cs) 7225 { 7226 PowerPCCPU *cpu = POWERPC_CPU(cs); 7227 7228 return cpu->env.nip; 7229 } 7230 7231 #ifdef CONFIG_TCG 7232 static void ppc_restore_state_to_opc(CPUState *cs, 7233 const TranslationBlock *tb, 7234 const uint64_t *data) 7235 { 7236 PowerPCCPU *cpu = POWERPC_CPU(cs); 7237 7238 cpu->env.nip = data[0]; 7239 } 7240 #endif /* CONFIG_TCG */ 7241 7242 static bool ppc_cpu_has_work(CPUState *cs) 7243 { 7244 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7245 } 7246 7247 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7248 { 7249 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7250 } 7251 7252 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7253 { 7254 CPUState *cs = CPU(obj); 7255 PowerPCCPU *cpu = POWERPC_CPU(cs); 7256 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7257 CPUPPCState *env = &cpu->env; 7258 target_ulong msr; 7259 int i; 7260 7261 if (pcc->parent_phases.hold) { 7262 pcc->parent_phases.hold(obj, type); 7263 } 7264 7265 msr = (target_ulong)0; 7266 msr |= (target_ulong)MSR_HVB; 7267 msr |= (target_ulong)1 << MSR_EP; 7268 #if defined(DO_SINGLE_STEP) && 0 7269 /* Single step trace mode */ 7270 msr |= (target_ulong)1 << MSR_SE; 7271 msr |= (target_ulong)1 << MSR_BE; 7272 #endif 7273 #if defined(CONFIG_USER_ONLY) 7274 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7275 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7276 msr |= (target_ulong)1 << MSR_FE1; 7277 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7278 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7279 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7280 msr |= (target_ulong)1 << MSR_PR; 7281 #if defined(TARGET_PPC64) 7282 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7283 #endif 7284 #if !TARGET_BIG_ENDIAN 7285 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7286 if (!((env->msr_mask >> MSR_LE) & 1)) { 7287 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7288 exit(1); 7289 } 7290 #endif 7291 #endif 7292 7293 #if defined(TARGET_PPC64) 7294 if (mmu_is_64bit(env->mmu_model)) { 7295 msr |= (1ULL << MSR_SF); 7296 } 7297 #endif 7298 7299 hreg_store_msr(env, msr, 1); 7300 7301 #if !defined(CONFIG_USER_ONLY) 7302 env->nip = env->hreset_vector | env->excp_prefix; 7303 7304 if (tcg_enabled()) { 7305 cpu_breakpoint_remove_all(cs, BP_CPU); 7306 cpu_watchpoint_remove_all(cs, BP_CPU); 7307 if (env->mmu_model != POWERPC_MMU_REAL) { 7308 ppc_tlb_invalidate_all(env); 7309 } 7310 pmu_mmcr01a_updated(env); 7311 } 7312 7313 /* clean any pending stop state */ 7314 env->resume_as_sreset = 0; 7315 #endif 7316 hreg_compute_hflags(env); 7317 env->reserve_addr = (target_ulong)-1ULL; 7318 /* Be sure no exception or interrupt is pending */ 7319 env->pending_interrupts = 0; 7320 cs->exception_index = POWERPC_EXCP_NONE; 7321 env->error_code = 0; 7322 ppc_irq_reset(cpu); 7323 7324 /* tininess for underflow is detected before rounding */ 7325 set_float_detect_tininess(float_tininess_before_rounding, 7326 &env->fp_status); 7327 7328 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7329 ppc_spr_t *spr = &env->spr_cb[i]; 7330 7331 if (!spr->name) { 7332 continue; 7333 } 7334 env->spr[i] = spr->default_value; 7335 } 7336 7337 #if defined(TARGET_PPC64) 7338 bhrb_reset_state(env); 7339 #endif 7340 } 7341 7342 #ifndef CONFIG_USER_ONLY 7343 7344 static bool ppc_cpu_is_big_endian(CPUState *cs) 7345 { 7346 cpu_synchronize_state(cs); 7347 7348 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7349 } 7350 7351 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7352 uint64_t **irq_counts, unsigned int *nb_irqs) 7353 { 7354 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7355 7356 *irq_counts = env->excp_stats; 7357 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7358 return true; 7359 } 7360 7361 #ifdef CONFIG_TCG 7362 static void ppc_cpu_exec_enter(CPUState *cs) 7363 { 7364 PowerPCCPU *cpu = POWERPC_CPU(cs); 7365 7366 if (cpu->vhyp) { 7367 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7368 } 7369 } 7370 7371 static void ppc_cpu_exec_exit(CPUState *cs) 7372 { 7373 PowerPCCPU *cpu = POWERPC_CPU(cs); 7374 7375 if (cpu->vhyp) { 7376 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7377 } 7378 } 7379 #endif /* CONFIG_TCG */ 7380 7381 #endif /* !CONFIG_USER_ONLY */ 7382 7383 static void ppc_cpu_instance_init(Object *obj) 7384 { 7385 PowerPCCPU *cpu = POWERPC_CPU(obj); 7386 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7387 CPUPPCState *env = &cpu->env; 7388 7389 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7390 7391 env->msr_mask = pcc->msr_mask; 7392 env->mmu_model = pcc->mmu_model; 7393 env->excp_model = pcc->excp_model; 7394 env->bus_model = pcc->bus_model; 7395 env->insns_flags = pcc->insns_flags; 7396 env->insns_flags2 = pcc->insns_flags2; 7397 env->flags = pcc->flags; 7398 env->bfd_mach = pcc->bfd_mach; 7399 env->check_pow = pcc->check_pow; 7400 env->check_attn = pcc->check_attn; 7401 7402 /* 7403 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7404 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7405 * mode support will remain, thus enforcing that we cannot use 7406 * priv. instructions in guest in PAPR mode. For 970 we currently 7407 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7408 * 970. If we ever want to support 970 HV mode, we'll have to add 7409 * a processor attribute of some sort. 7410 */ 7411 #if !defined(CONFIG_USER_ONLY) 7412 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7413 #endif 7414 7415 ppc_hash64_init(cpu); 7416 } 7417 7418 static void ppc_cpu_instance_finalize(Object *obj) 7419 { 7420 PowerPCCPU *cpu = POWERPC_CPU(obj); 7421 7422 ppc_hash64_finalize(cpu); 7423 } 7424 7425 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7426 { 7427 return pcc->pvr == pvr; 7428 } 7429 7430 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7431 { 7432 CPUPPCState *env = cpu_env(cs); 7433 7434 if ((env->hflags >> MSR_LE) & 1) { 7435 info->endian = BFD_ENDIAN_LITTLE; 7436 } 7437 info->mach = env->bfd_mach; 7438 if (!env->bfd_mach) { 7439 #ifdef TARGET_PPC64 7440 info->mach = bfd_mach_ppc64; 7441 #else 7442 info->mach = bfd_mach_ppc; 7443 #endif 7444 } 7445 7446 info->cap_arch = CS_ARCH_PPC; 7447 #ifdef TARGET_PPC64 7448 info->cap_mode = CS_MODE_64; 7449 #endif 7450 } 7451 7452 static Property ppc_cpu_properties[] = { 7453 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7454 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7455 false), 7456 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7457 false), 7458 DEFINE_PROP_END_OF_LIST(), 7459 }; 7460 7461 #ifndef CONFIG_USER_ONLY 7462 #include "hw/core/sysemu-cpu-ops.h" 7463 7464 static const struct SysemuCPUOps ppc_sysemu_ops = { 7465 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7466 .write_elf32_note = ppc32_cpu_write_elf32_note, 7467 .write_elf64_note = ppc64_cpu_write_elf64_note, 7468 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7469 .legacy_vmsd = &vmstate_ppc_cpu, 7470 }; 7471 #endif 7472 7473 #ifdef CONFIG_TCG 7474 #include "hw/core/tcg-cpu-ops.h" 7475 7476 static const TCGCPUOps ppc_tcg_ops = { 7477 .initialize = ppc_translate_init, 7478 .restore_state_to_opc = ppc_restore_state_to_opc, 7479 7480 #ifdef CONFIG_USER_ONLY 7481 .record_sigsegv = ppc_cpu_record_sigsegv, 7482 #else 7483 .tlb_fill = ppc_cpu_tlb_fill, 7484 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7485 .cpu_exec_halt = ppc_cpu_has_work, 7486 .do_interrupt = ppc_cpu_do_interrupt, 7487 .cpu_exec_enter = ppc_cpu_exec_enter, 7488 .cpu_exec_exit = ppc_cpu_exec_exit, 7489 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7490 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7491 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7492 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7493 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7494 #endif /* !CONFIG_USER_ONLY */ 7495 }; 7496 #endif /* CONFIG_TCG */ 7497 7498 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7499 { 7500 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7501 CPUClass *cc = CPU_CLASS(oc); 7502 DeviceClass *dc = DEVICE_CLASS(oc); 7503 ResettableClass *rc = RESETTABLE_CLASS(oc); 7504 7505 device_class_set_parent_realize(dc, ppc_cpu_realize, 7506 &pcc->parent_realize); 7507 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7508 &pcc->parent_unrealize); 7509 pcc->pvr_match = ppc_pvr_match_default; 7510 device_class_set_props(dc, ppc_cpu_properties); 7511 7512 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7513 &pcc->parent_phases); 7514 7515 cc->class_by_name = ppc_cpu_class_by_name; 7516 cc->has_work = ppc_cpu_has_work; 7517 cc->mmu_index = ppc_cpu_mmu_index; 7518 cc->dump_state = ppc_cpu_dump_state; 7519 cc->set_pc = ppc_cpu_set_pc; 7520 cc->get_pc = ppc_cpu_get_pc; 7521 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7522 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7523 #ifndef CONFIG_USER_ONLY 7524 cc->sysemu_ops = &ppc_sysemu_ops; 7525 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7526 7527 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7528 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7529 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7530 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7531 #endif 7532 7533 cc->gdb_num_core_regs = 71; 7534 #ifdef USE_APPLE_GDB 7535 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7536 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7537 cc->gdb_num_core_regs = 71 + 32; 7538 #endif 7539 7540 cc->gdb_arch_name = ppc_gdb_arch_name; 7541 #if defined(TARGET_PPC64) 7542 cc->gdb_core_xml_file = "power64-core.xml"; 7543 #else 7544 cc->gdb_core_xml_file = "power-core.xml"; 7545 #endif 7546 cc->disas_set_info = ppc_disas_set_info; 7547 7548 dc->fw_name = "PowerPC,UNKNOWN"; 7549 7550 #ifdef CONFIG_TCG 7551 cc->tcg_ops = &ppc_tcg_ops; 7552 #endif /* CONFIG_TCG */ 7553 } 7554 7555 static const TypeInfo ppc_cpu_type_info = { 7556 .name = TYPE_POWERPC_CPU, 7557 .parent = TYPE_CPU, 7558 .instance_size = sizeof(PowerPCCPU), 7559 .instance_align = __alignof__(PowerPCCPU), 7560 .instance_init = ppc_cpu_instance_init, 7561 .instance_finalize = ppc_cpu_instance_finalize, 7562 .abstract = true, 7563 .class_size = sizeof(PowerPCCPUClass), 7564 .class_init = ppc_cpu_class_init, 7565 #ifndef CONFIG_USER_ONLY 7566 .interfaces = (InterfaceInfo[]) { 7567 { TYPE_INTERRUPT_STATS_PROVIDER }, 7568 { } 7569 }, 7570 #endif 7571 }; 7572 7573 #ifndef CONFIG_USER_ONLY 7574 static const TypeInfo ppc_vhyp_type_info = { 7575 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7576 .parent = TYPE_INTERFACE, 7577 .class_size = sizeof(PPCVirtualHypervisorClass), 7578 }; 7579 #endif 7580 7581 static void ppc_cpu_register_types(void) 7582 { 7583 type_register_static(&ppc_cpu_type_info); 7584 #ifndef CONFIG_USER_ONLY 7585 type_register_static(&ppc_vhyp_type_info); 7586 #endif 7587 } 7588 7589 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7590 { 7591 #define RGPL 4 7592 #define RFPL 4 7593 7594 CPUPPCState *env = cpu_env(cs); 7595 int i; 7596 7597 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7598 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7599 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7600 cs->cpu_index); 7601 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7602 "%08x iidx %d didx %d\n", 7603 env->msr, env->spr[SPR_HID0], env->hflags, 7604 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7605 #if !defined(CONFIG_USER_ONLY) 7606 if (env->tb_env) { 7607 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7608 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7609 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7610 } 7611 #else 7612 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7613 cpu_ppc_load_tbl(env)); 7614 #endif 7615 for (i = 0; i < 32; i++) { 7616 if ((i & (RGPL - 1)) == 0) { 7617 qemu_fprintf(f, "GPR%02d", i); 7618 } 7619 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7620 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7621 qemu_fprintf(f, "\n"); 7622 } 7623 } 7624 qemu_fprintf(f, "CR "); 7625 for (i = 0; i < 8; i++) 7626 qemu_fprintf(f, "%01x", env->crf[i]); 7627 qemu_fprintf(f, " ["); 7628 for (i = 0; i < 8; i++) { 7629 char a = '-'; 7630 if (env->crf[i] & 0x08) { 7631 a = 'L'; 7632 } else if (env->crf[i] & 0x04) { 7633 a = 'G'; 7634 } else if (env->crf[i] & 0x02) { 7635 a = 'E'; 7636 } 7637 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7638 } 7639 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7640 (int)env->reserve_length, env->reserve_addr); 7641 7642 if (flags & CPU_DUMP_FPU) { 7643 for (i = 0; i < 32; i++) { 7644 if ((i & (RFPL - 1)) == 0) { 7645 qemu_fprintf(f, "FPR%02d", i); 7646 } 7647 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7648 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7649 qemu_fprintf(f, "\n"); 7650 } 7651 } 7652 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7653 } 7654 7655 #if !defined(CONFIG_USER_ONLY) 7656 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7657 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7658 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7659 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7660 7661 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7662 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7663 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7664 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7665 7666 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7667 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7668 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7669 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7670 7671 switch (env->excp_model) { 7672 #if defined(TARGET_PPC64) 7673 case POWERPC_EXCP_POWER7: 7674 case POWERPC_EXCP_POWER8: 7675 case POWERPC_EXCP_POWER9: 7676 case POWERPC_EXCP_POWER10: 7677 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7678 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7679 break; 7680 #endif 7681 case POWERPC_EXCP_BOOKE: 7682 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7683 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7684 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7685 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7686 7687 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7688 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7689 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7690 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7691 7692 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7693 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7694 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7695 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7696 7697 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7698 " EPR " TARGET_FMT_lx "\n", 7699 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7700 env->spr[SPR_BOOKE_EPR]); 7701 7702 /* FSL-specific */ 7703 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7704 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7705 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7706 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7707 7708 /* 7709 * IVORs are left out as they are large and do not change often -- 7710 * they can be read with "p $ivor0", "p $ivor1", etc. 7711 */ 7712 break; 7713 case POWERPC_EXCP_40x: 7714 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7715 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7716 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7717 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7718 7719 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7720 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7721 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7722 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7723 break; 7724 default: 7725 break; 7726 } 7727 7728 #if defined(TARGET_PPC64) 7729 if (env->flags & POWERPC_FLAG_CFAR) { 7730 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7731 } 7732 #endif 7733 7734 if (env->spr_cb[SPR_LPCR].name) { 7735 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7736 } 7737 7738 switch (env->mmu_model) { 7739 case POWERPC_MMU_32B: 7740 case POWERPC_MMU_SOFT_6xx: 7741 #if defined(TARGET_PPC64) 7742 case POWERPC_MMU_64B: 7743 case POWERPC_MMU_2_03: 7744 case POWERPC_MMU_2_06: 7745 case POWERPC_MMU_2_07: 7746 case POWERPC_MMU_3_00: 7747 #endif 7748 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7749 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7750 } 7751 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7752 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7753 } 7754 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7755 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7756 break; 7757 case POWERPC_MMU_BOOKE206: 7758 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7759 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7760 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7761 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7762 7763 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7764 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7765 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7766 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7767 7768 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7769 " TLB1CFG " TARGET_FMT_lx "\n", 7770 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7771 env->spr[SPR_BOOKE_TLB1CFG]); 7772 break; 7773 default: 7774 break; 7775 } 7776 #endif 7777 7778 #undef RGPL 7779 #undef RFPL 7780 } 7781 type_init(ppc_cpu_register_types) 7782