1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/arch_init.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/hw_accel.h" 28 #include "sysemu/tcg.h" 29 #include "cpu-models.h" 30 #include "mmu-hash32.h" 31 #include "mmu-hash64.h" 32 #include "qemu/error-report.h" 33 #include "qemu/module.h" 34 #include "qemu/qemu-print.h" 35 #include "qapi/error.h" 36 #include "qapi/qmp/qnull.h" 37 #include "qapi/visitor.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/ppc/ppc.h" 40 #include "mmu-book3s-v3.h" 41 #include "qemu/cutils.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 #include "qapi/qapi-commands-machine-target.h" 45 46 #include "helper_regs.h" 47 #include "internal.h" 48 #include "spr_tcg.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 602 implementation */ 753 static void register_602_sprs(CPUPPCState *env) 754 { 755 /* ESA registers */ 756 /* XXX : not implemented */ 757 spr_register(env, SPR_SER, "SER", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* XXX : not implemented */ 762 spr_register(env, SPR_SEBR, "SEBR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* XXX : not implemented */ 767 spr_register(env, SPR_ESASRR, "ESASRR", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 /* Floating point status */ 772 /* XXX : not implemented */ 773 spr_register(env, SPR_SP, "SP", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* XXX : not implemented */ 778 spr_register(env, SPR_LT, "LT", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 /* Watchdog timer */ 783 /* XXX : not implemented */ 784 spr_register(env, SPR_TCR, "TCR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 /* Interrupt base */ 789 spr_register(env, SPR_IBR, "IBR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* XXX : not implemented */ 794 spr_register(env, SPR_IABR, "IABR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 } 799 800 /* SPR specific to PowerPC 601 implementation */ 801 static void register_601_sprs(CPUPPCState *env) 802 { 803 /* Multiplication/division register */ 804 /* MQ */ 805 spr_register(env, SPR_MQ, "MQ", 806 &spr_read_generic, &spr_write_generic, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 /* RTC registers */ 810 spr_register(env, SPR_601_RTCU, "RTCU", 811 SPR_NOACCESS, SPR_NOACCESS, 812 SPR_NOACCESS, &spr_write_601_rtcu, 813 0x00000000); 814 spr_register(env, SPR_601_VRTCU, "RTCU", 815 &spr_read_601_rtcu, SPR_NOACCESS, 816 &spr_read_601_rtcu, SPR_NOACCESS, 817 0x00000000); 818 spr_register(env, SPR_601_RTCL, "RTCL", 819 SPR_NOACCESS, SPR_NOACCESS, 820 SPR_NOACCESS, &spr_write_601_rtcl, 821 0x00000000); 822 spr_register(env, SPR_601_VRTCL, "RTCL", 823 &spr_read_601_rtcl, SPR_NOACCESS, 824 &spr_read_601_rtcl, SPR_NOACCESS, 825 0x00000000); 826 /* Timer */ 827 #if 0 /* ? */ 828 spr_register(env, SPR_601_UDECR, "UDECR", 829 &spr_read_decr, SPR_NOACCESS, 830 &spr_read_decr, SPR_NOACCESS, 831 0x00000000); 832 #endif 833 /* External access control */ 834 /* XXX : not implemented */ 835 spr_register(env, SPR_EAR, "EAR", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 /* Memory management */ 840 #if !defined(CONFIG_USER_ONLY) 841 spr_register(env, SPR_IBAT0U, "IBAT0U", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_601_ubat, &spr_write_601_ubatu, 844 0x00000000); 845 spr_register(env, SPR_IBAT0L, "IBAT0L", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_601_ubat, &spr_write_601_ubatl, 848 0x00000000); 849 spr_register(env, SPR_IBAT1U, "IBAT1U", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_601_ubat, &spr_write_601_ubatu, 852 0x00000000); 853 spr_register(env, SPR_IBAT1L, "IBAT1L", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_601_ubat, &spr_write_601_ubatl, 856 0x00000000); 857 spr_register(env, SPR_IBAT2U, "IBAT2U", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_601_ubat, &spr_write_601_ubatu, 860 0x00000000); 861 spr_register(env, SPR_IBAT2L, "IBAT2L", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_601_ubat, &spr_write_601_ubatl, 864 0x00000000); 865 spr_register(env, SPR_IBAT3U, "IBAT3U", 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_601_ubat, &spr_write_601_ubatu, 868 0x00000000); 869 spr_register(env, SPR_IBAT3L, "IBAT3L", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_601_ubat, &spr_write_601_ubatl, 872 0x00000000); 873 env->nb_BATs = 4; 874 #endif 875 } 876 877 static void register_74xx_sprs(CPUPPCState *env) 878 { 879 /* Processor identification */ 880 spr_register(env, SPR_PIR, "PIR", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_pir, 883 0x00000000); 884 /* XXX : not implemented */ 885 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 886 SPR_NOACCESS, SPR_NOACCESS, 887 &spr_read_generic, &spr_write_generic, 888 0x00000000); 889 /* XXX : not implemented */ 890 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 891 &spr_read_ureg, SPR_NOACCESS, 892 &spr_read_ureg, SPR_NOACCESS, 893 0x00000000); 894 /* XXX: not implemented */ 895 spr_register(env, SPR_BAMR, "BAMR", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 /* XXX : not implemented */ 900 spr_register(env, SPR_MSSCR0, "MSSCR0", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_generic, 903 0x00000000); 904 /* Hardware implementation registers */ 905 /* XXX : not implemented */ 906 spr_register(env, SPR_HID0, "HID0", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 /* XXX : not implemented */ 911 spr_register(env, SPR_HID1, "HID1", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 /* Altivec */ 916 spr_register(env, SPR_VRSAVE, "VRSAVE", 917 &spr_read_generic, &spr_write_generic, 918 &spr_read_generic, &spr_write_generic, 919 0x00000000); 920 /* XXX : not implemented */ 921 spr_register(env, SPR_L2CR, "L2CR", 922 SPR_NOACCESS, SPR_NOACCESS, 923 &spr_read_generic, spr_access_nop, 924 0x00000000); 925 } 926 927 static void register_l3_ctrl(CPUPPCState *env) 928 { 929 /* L3CR */ 930 /* XXX : not implemented */ 931 spr_register(env, SPR_L3CR, "L3CR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 /* L3ITCR0 */ 936 /* XXX : not implemented */ 937 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 /* L3PM */ 942 /* XXX : not implemented */ 943 spr_register(env, SPR_L3PM, "L3PM", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 } 948 949 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 950 { 951 #if !defined(CONFIG_USER_ONLY) 952 env->nb_tlb = nb_tlbs; 953 env->nb_ways = nb_ways; 954 env->id_tlbs = 1; 955 env->tlb_type = TLB_6XX; 956 /* XXX : not implemented */ 957 spr_register(env, SPR_PTEHI, "PTEHI", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 /* XXX : not implemented */ 962 spr_register(env, SPR_PTELO, "PTELO", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 /* XXX : not implemented */ 967 spr_register(env, SPR_TLBMISS, "TLBMISS", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 #endif 972 } 973 974 static void register_usprg3_sprs(CPUPPCState *env) 975 { 976 spr_register(env, SPR_USPRG3, "USPRG3", 977 &spr_read_ureg, SPR_NOACCESS, 978 &spr_read_ureg, SPR_NOACCESS, 979 0x00000000); 980 } 981 982 static void register_usprgh_sprs(CPUPPCState *env) 983 { 984 spr_register(env, SPR_USPRG4, "USPRG4", 985 &spr_read_ureg, SPR_NOACCESS, 986 &spr_read_ureg, SPR_NOACCESS, 987 0x00000000); 988 spr_register(env, SPR_USPRG5, "USPRG5", 989 &spr_read_ureg, SPR_NOACCESS, 990 &spr_read_ureg, SPR_NOACCESS, 991 0x00000000); 992 spr_register(env, SPR_USPRG6, "USPRG6", 993 &spr_read_ureg, SPR_NOACCESS, 994 &spr_read_ureg, SPR_NOACCESS, 995 0x00000000); 996 spr_register(env, SPR_USPRG7, "USPRG7", 997 &spr_read_ureg, SPR_NOACCESS, 998 &spr_read_ureg, SPR_NOACCESS, 999 0x00000000); 1000 } 1001 1002 /* PowerPC BookE SPR */ 1003 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1004 { 1005 const char *ivor_names[64] = { 1006 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1007 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1008 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1009 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1010 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1011 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1012 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1013 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1014 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1015 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1016 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1017 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1018 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1019 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1020 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1021 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1022 }; 1023 #define SPR_BOOKE_IVORxx (-1) 1024 int ivor_sprn[64] = { 1025 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1026 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1027 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1028 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1029 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1030 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1031 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1032 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1033 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1034 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1035 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1036 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1037 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1038 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1039 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1040 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1041 }; 1042 int i; 1043 1044 /* Interrupt processing */ 1045 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1046 SPR_NOACCESS, SPR_NOACCESS, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1050 SPR_NOACCESS, SPR_NOACCESS, 1051 &spr_read_generic, &spr_write_generic, 1052 0x00000000); 1053 /* Debug */ 1054 /* XXX : not implemented */ 1055 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 /* XXX : not implemented */ 1060 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 /* XXX : not implemented */ 1065 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, &spr_write_generic, 1068 0x00000000); 1069 /* XXX : not implemented */ 1070 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 /* XXX : not implemented */ 1075 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1076 SPR_NOACCESS, SPR_NOACCESS, 1077 &spr_read_generic, &spr_write_40x_dbcr0, 1078 0x00000000); 1079 /* XXX : not implemented */ 1080 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 /* XXX : not implemented */ 1085 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_generic, 1088 0x00000000); 1089 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, &spr_write_generic, 1092 0x00000000); 1093 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, &spr_write_generic, 1096 0x00000000); 1097 /* XXX : not implemented */ 1098 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1099 SPR_NOACCESS, SPR_NOACCESS, 1100 &spr_read_generic, &spr_write_clear, 1101 0x00000000); 1102 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, &spr_write_generic, 1105 0x00000000); 1106 spr_register(env, SPR_BOOKE_ESR, "ESR", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, &spr_write_generic, 1109 0x00000000); 1110 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_excp_prefix, 1113 0x00000000); 1114 /* Exception vectors */ 1115 for (i = 0; i < 64; i++) { 1116 if (ivor_mask & (1ULL << i)) { 1117 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1118 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1119 exit(1); 1120 } 1121 spr_register(env, ivor_sprn[i], ivor_names[i], 1122 SPR_NOACCESS, SPR_NOACCESS, 1123 &spr_read_generic, &spr_write_excp_vector, 1124 0x00000000); 1125 } 1126 } 1127 spr_register(env, SPR_BOOKE_PID, "PID", 1128 SPR_NOACCESS, SPR_NOACCESS, 1129 &spr_read_generic, &spr_write_booke_pid, 1130 0x00000000); 1131 spr_register(env, SPR_BOOKE_TCR, "TCR", 1132 SPR_NOACCESS, SPR_NOACCESS, 1133 &spr_read_generic, &spr_write_booke_tcr, 1134 0x00000000); 1135 spr_register(env, SPR_BOOKE_TSR, "TSR", 1136 SPR_NOACCESS, SPR_NOACCESS, 1137 &spr_read_generic, &spr_write_booke_tsr, 1138 0x00000000); 1139 /* Timer */ 1140 spr_register(env, SPR_DECR, "DECR", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_decr, &spr_write_decr, 1143 0x00000000); 1144 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 SPR_NOACCESS, &spr_write_generic, 1147 0x00000000); 1148 /* SPRGs */ 1149 spr_register(env, SPR_USPRG0, "USPRG0", 1150 &spr_read_generic, &spr_write_generic, 1151 &spr_read_generic, &spr_write_generic, 1152 0x00000000); 1153 spr_register(env, SPR_SPRG4, "SPRG4", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00000000); 1157 spr_register(env, SPR_SPRG5, "SPRG5", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 spr_register(env, SPR_SPRG6, "SPRG6", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 spr_register(env, SPR_SPRG7, "SPRG7", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_generic, 1168 0x00000000); 1169 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1170 SPR_NOACCESS, SPR_NOACCESS, 1171 &spr_read_generic, &spr_write_generic, 1172 0x00000000); 1173 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 } 1178 1179 #if !defined(CONFIG_USER_ONLY) 1180 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1181 uint32_t maxsize, uint32_t flags, 1182 uint32_t nentries) 1183 { 1184 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1185 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1186 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1187 flags | nentries; 1188 } 1189 #endif /* !CONFIG_USER_ONLY */ 1190 1191 /* BookE 2.06 storage control registers */ 1192 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1193 uint32_t *tlbncfg, uint32_t mmucfg) 1194 { 1195 #if !defined(CONFIG_USER_ONLY) 1196 const char *mas_names[8] = { 1197 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1198 }; 1199 int mas_sprn[8] = { 1200 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1201 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1202 }; 1203 int i; 1204 1205 /* TLB assist registers */ 1206 /* XXX : not implemented */ 1207 for (i = 0; i < 8; i++) { 1208 if (mas_mask & (1 << i)) { 1209 spr_register(env, mas_sprn[i], mas_names[i], 1210 SPR_NOACCESS, SPR_NOACCESS, 1211 &spr_read_generic, 1212 (i == 2 && (env->insns_flags & PPC_64B)) 1213 ? &spr_write_generic : &spr_write_generic32, 1214 0x00000000); 1215 } 1216 } 1217 if (env->nb_pids > 1) { 1218 /* XXX : not implemented */ 1219 spr_register(env, SPR_BOOKE_PID1, "PID1", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_booke_pid, 1222 0x00000000); 1223 } 1224 if (env->nb_pids > 2) { 1225 /* XXX : not implemented */ 1226 spr_register(env, SPR_BOOKE_PID2, "PID2", 1227 SPR_NOACCESS, SPR_NOACCESS, 1228 &spr_read_generic, &spr_write_booke_pid, 1229 0x00000000); 1230 } 1231 1232 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_eplc, 1235 0x00000000); 1236 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 &spr_read_generic, &spr_write_epsc, 1239 0x00000000); 1240 1241 /* XXX : not implemented */ 1242 spr_register(env, SPR_MMUCFG, "MMUCFG", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, SPR_NOACCESS, 1245 mmucfg); 1246 switch (env->nb_ways) { 1247 case 4: 1248 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1249 SPR_NOACCESS, SPR_NOACCESS, 1250 &spr_read_generic, SPR_NOACCESS, 1251 tlbncfg[3]); 1252 /* Fallthru */ 1253 case 3: 1254 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 &spr_read_generic, SPR_NOACCESS, 1257 tlbncfg[2]); 1258 /* Fallthru */ 1259 case 2: 1260 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1261 SPR_NOACCESS, SPR_NOACCESS, 1262 &spr_read_generic, SPR_NOACCESS, 1263 tlbncfg[1]); 1264 /* Fallthru */ 1265 case 1: 1266 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, SPR_NOACCESS, 1269 tlbncfg[0]); 1270 /* Fallthru */ 1271 case 0: 1272 default: 1273 break; 1274 } 1275 #endif 1276 1277 register_usprgh_sprs(env); 1278 } 1279 1280 /* SPR specific to PowerPC 440 implementation */ 1281 static void register_440_sprs(CPUPPCState *env) 1282 { 1283 /* Cache control */ 1284 /* XXX : not implemented */ 1285 spr_register(env, SPR_440_DNV0, "DNV0", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_generic, &spr_write_generic, 1288 0x00000000); 1289 /* XXX : not implemented */ 1290 spr_register(env, SPR_440_DNV1, "DNV1", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 /* XXX : not implemented */ 1295 spr_register(env, SPR_440_DNV2, "DNV2", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 /* XXX : not implemented */ 1300 spr_register(env, SPR_440_DNV3, "DNV3", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 /* XXX : not implemented */ 1305 spr_register(env, SPR_440_DTV0, "DTV0", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 /* XXX : not implemented */ 1310 spr_register(env, SPR_440_DTV1, "DTV1", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 /* XXX : not implemented */ 1315 spr_register(env, SPR_440_DTV2, "DTV2", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 /* XXX : not implemented */ 1320 spr_register(env, SPR_440_DTV3, "DTV3", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 /* XXX : not implemented */ 1325 spr_register(env, SPR_440_DVLIM, "DVLIM", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 /* XXX : not implemented */ 1330 spr_register(env, SPR_440_INV0, "INV0", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 /* XXX : not implemented */ 1335 spr_register(env, SPR_440_INV1, "INV1", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 /* XXX : not implemented */ 1340 spr_register(env, SPR_440_INV2, "INV2", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 /* XXX : not implemented */ 1345 spr_register(env, SPR_440_INV3, "INV3", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 /* XXX : not implemented */ 1350 spr_register(env, SPR_440_ITV0, "ITV0", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 /* XXX : not implemented */ 1355 spr_register(env, SPR_440_ITV1, "ITV1", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 /* XXX : not implemented */ 1360 spr_register(env, SPR_440_ITV2, "ITV2", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 /* XXX : not implemented */ 1365 spr_register(env, SPR_440_ITV3, "ITV3", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 /* XXX : not implemented */ 1370 spr_register(env, SPR_440_IVLIM, "IVLIM", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 /* Cache debug */ 1375 /* XXX : not implemented */ 1376 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, SPR_NOACCESS, 1379 0x00000000); 1380 /* XXX : not implemented */ 1381 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, SPR_NOACCESS, 1384 0x00000000); 1385 /* XXX : not implemented */ 1386 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1387 SPR_NOACCESS, SPR_NOACCESS, 1388 &spr_read_generic, SPR_NOACCESS, 1389 0x00000000); 1390 /* XXX : not implemented */ 1391 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1392 SPR_NOACCESS, SPR_NOACCESS, 1393 &spr_read_generic, SPR_NOACCESS, 1394 0x00000000); 1395 /* XXX : not implemented */ 1396 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 &spr_read_generic, SPR_NOACCESS, 1399 0x00000000); 1400 /* XXX : not implemented */ 1401 spr_register(env, SPR_440_DBDR, "DBDR", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 /* Processor control */ 1406 spr_register(env, SPR_4xx_CCR0, "CCR0", 1407 SPR_NOACCESS, SPR_NOACCESS, 1408 &spr_read_generic, &spr_write_generic, 1409 0x00000000); 1410 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, SPR_NOACCESS, 1413 0x00000000); 1414 /* Storage control */ 1415 spr_register(env, SPR_440_MMUCR, "MMUCR", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 0x00000000); 1419 } 1420 1421 /* SPR shared between PowerPC 40x implementations */ 1422 static void register_40x_sprs(CPUPPCState *env) 1423 { 1424 /* Cache */ 1425 /* not emulated, as QEMU do not emulate caches */ 1426 spr_register(env, SPR_40x_DCCR, "DCCR", 1427 SPR_NOACCESS, SPR_NOACCESS, 1428 &spr_read_generic, &spr_write_generic, 1429 0x00000000); 1430 /* not emulated, as QEMU do not emulate caches */ 1431 spr_register(env, SPR_40x_ICCR, "ICCR", 1432 SPR_NOACCESS, SPR_NOACCESS, 1433 &spr_read_generic, &spr_write_generic, 1434 0x00000000); 1435 /* not emulated, as QEMU do not emulate caches */ 1436 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1437 SPR_NOACCESS, SPR_NOACCESS, 1438 &spr_read_generic, SPR_NOACCESS, 1439 0x00000000); 1440 /* Exception */ 1441 spr_register(env, SPR_40x_DEAR, "DEAR", 1442 SPR_NOACCESS, SPR_NOACCESS, 1443 &spr_read_generic, &spr_write_generic, 1444 0x00000000); 1445 spr_register(env, SPR_40x_ESR, "ESR", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 spr_register(env, SPR_40x_EVPR, "EVPR", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, &spr_write_excp_prefix, 1452 0x00000000); 1453 spr_register(env, SPR_40x_SRR2, "SRR2", 1454 &spr_read_generic, &spr_write_generic, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 spr_register(env, SPR_40x_SRR3, "SRR3", 1458 &spr_read_generic, &spr_write_generic, 1459 &spr_read_generic, &spr_write_generic, 1460 0x00000000); 1461 /* Timers */ 1462 spr_register(env, SPR_40x_PIT, "PIT", 1463 SPR_NOACCESS, SPR_NOACCESS, 1464 &spr_read_40x_pit, &spr_write_40x_pit, 1465 0x00000000); 1466 spr_register(env, SPR_40x_TCR, "TCR", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_booke_tcr, 1469 0x00000000); 1470 spr_register(env, SPR_40x_TSR, "TSR", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_booke_tsr, 1473 0x00000000); 1474 } 1475 1476 /* SPR specific to PowerPC 405 implementation */ 1477 static void register_405_sprs(CPUPPCState *env) 1478 { 1479 /* MMU */ 1480 spr_register(env, SPR_40x_PID, "PID", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 spr_register(env, SPR_4xx_CCR0, "CCR0", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, &spr_write_generic, 1487 0x00700000); 1488 /* Debug interface */ 1489 /* XXX : not implemented */ 1490 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_40x_dbcr0, 1493 0x00000000); 1494 /* XXX : not implemented */ 1495 spr_register(env, SPR_405_DBCR1, "DBCR1", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 /* XXX : not implemented */ 1500 spr_register(env, SPR_40x_DBSR, "DBSR", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_clear, 1503 /* Last reset was system reset */ 1504 0x00000300); 1505 /* XXX : not implemented */ 1506 spr_register(env, SPR_40x_DAC1, "DAC1", 1507 SPR_NOACCESS, SPR_NOACCESS, 1508 &spr_read_generic, &spr_write_generic, 1509 0x00000000); 1510 spr_register(env, SPR_40x_DAC2, "DAC2", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 /* XXX : not implemented */ 1515 spr_register(env, SPR_405_DVC1, "DVC1", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 /* XXX : not implemented */ 1520 spr_register(env, SPR_405_DVC2, "DVC2", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 /* XXX : not implemented */ 1525 spr_register(env, SPR_40x_IAC1, "IAC1", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 spr_register(env, SPR_40x_IAC2, "IAC2", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 /* XXX : not implemented */ 1534 spr_register(env, SPR_405_IAC3, "IAC3", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 /* XXX : not implemented */ 1539 spr_register(env, SPR_405_IAC4, "IAC4", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 /* Storage control */ 1544 /* XXX: TODO: not implemented */ 1545 spr_register(env, SPR_405_SLER, "SLER", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_40x_sler, 1548 0x00000000); 1549 spr_register(env, SPR_40x_ZPR, "ZPR", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 /* XXX : not implemented */ 1554 spr_register(env, SPR_405_SU0R, "SU0R", 1555 SPR_NOACCESS, SPR_NOACCESS, 1556 &spr_read_generic, &spr_write_generic, 1557 0x00000000); 1558 /* SPRG */ 1559 spr_register(env, SPR_USPRG0, "USPRG0", 1560 &spr_read_ureg, SPR_NOACCESS, 1561 &spr_read_ureg, SPR_NOACCESS, 1562 0x00000000); 1563 spr_register(env, SPR_SPRG4, "SPRG4", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 spr_register(env, SPR_SPRG5, "SPRG5", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 spr_register(env, SPR_SPRG6, "SPRG6", 1572 SPR_NOACCESS, SPR_NOACCESS, 1573 spr_read_generic, &spr_write_generic, 1574 0x00000000); 1575 spr_register(env, SPR_SPRG7, "SPRG7", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 register_usprgh_sprs(env); 1580 } 1581 1582 /* SPR shared between PowerPC 401 & 403 implementations */ 1583 static void register_401_403_sprs(CPUPPCState *env) 1584 { 1585 /* Time base */ 1586 spr_register(env, SPR_403_VTBL, "TBL", 1587 &spr_read_tbl, SPR_NOACCESS, 1588 &spr_read_tbl, SPR_NOACCESS, 1589 0x00000000); 1590 spr_register(env, SPR_403_TBL, "TBL", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 SPR_NOACCESS, &spr_write_tbl, 1593 0x00000000); 1594 spr_register(env, SPR_403_VTBU, "TBU", 1595 &spr_read_tbu, SPR_NOACCESS, 1596 &spr_read_tbu, SPR_NOACCESS, 1597 0x00000000); 1598 spr_register(env, SPR_403_TBU, "TBU", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 SPR_NOACCESS, &spr_write_tbu, 1601 0x00000000); 1602 /* Debug */ 1603 /* not emulated, as QEMU do not emulate caches */ 1604 spr_register(env, SPR_403_CDBCR, "CDBCR", 1605 SPR_NOACCESS, SPR_NOACCESS, 1606 &spr_read_generic, &spr_write_generic, 1607 0x00000000); 1608 } 1609 1610 /* SPR specific to PowerPC 401 implementation */ 1611 static void register_401_sprs(CPUPPCState *env) 1612 { 1613 /* Debug interface */ 1614 /* XXX : not implemented */ 1615 spr_register(env, SPR_40x_DBCR0, "DBCR", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_40x_dbcr0, 1618 0x00000000); 1619 /* XXX : not implemented */ 1620 spr_register(env, SPR_40x_DBSR, "DBSR", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_generic, &spr_write_clear, 1623 /* Last reset was system reset */ 1624 0x00000300); 1625 /* XXX : not implemented */ 1626 spr_register(env, SPR_40x_DAC1, "DAC", 1627 SPR_NOACCESS, SPR_NOACCESS, 1628 &spr_read_generic, &spr_write_generic, 1629 0x00000000); 1630 /* XXX : not implemented */ 1631 spr_register(env, SPR_40x_IAC1, "IAC", 1632 SPR_NOACCESS, SPR_NOACCESS, 1633 &spr_read_generic, &spr_write_generic, 1634 0x00000000); 1635 /* Storage control */ 1636 /* XXX: TODO: not implemented */ 1637 spr_register(env, SPR_405_SLER, "SLER", 1638 SPR_NOACCESS, SPR_NOACCESS, 1639 &spr_read_generic, &spr_write_40x_sler, 1640 0x00000000); 1641 /* not emulated, as QEMU never does speculative access */ 1642 spr_register(env, SPR_40x_SGR, "SGR", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_generic, &spr_write_generic, 1645 0xFFFFFFFF); 1646 /* not emulated, as QEMU do not emulate caches */ 1647 spr_register(env, SPR_40x_DCWR, "DCWR", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 } 1652 1653 static void register_401x2_sprs(CPUPPCState *env) 1654 { 1655 register_401_sprs(env); 1656 spr_register(env, SPR_40x_PID, "PID", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_generic, 1659 0x00000000); 1660 spr_register(env, SPR_40x_ZPR, "ZPR", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_generic, 1663 0x00000000); 1664 } 1665 1666 /* SPR specific to PowerPC 403 implementation */ 1667 static void register_403_sprs(CPUPPCState *env) 1668 { 1669 /* Debug interface */ 1670 /* XXX : not implemented */ 1671 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_40x_dbcr0, 1674 0x00000000); 1675 /* XXX : not implemented */ 1676 spr_register(env, SPR_40x_DBSR, "DBSR", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_clear, 1679 /* Last reset was system reset */ 1680 0x00000300); 1681 /* XXX : not implemented */ 1682 spr_register(env, SPR_40x_DAC1, "DAC1", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 /* XXX : not implemented */ 1687 spr_register(env, SPR_40x_DAC2, "DAC2", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 /* XXX : not implemented */ 1692 spr_register(env, SPR_40x_IAC1, "IAC1", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 /* XXX : not implemented */ 1697 spr_register(env, SPR_40x_IAC2, "IAC2", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 } 1702 1703 static void register_403_real_sprs(CPUPPCState *env) 1704 { 1705 spr_register(env, SPR_403_PBL1, "PBL1", 1706 SPR_NOACCESS, SPR_NOACCESS, 1707 &spr_read_403_pbr, &spr_write_403_pbr, 1708 0x00000000); 1709 spr_register(env, SPR_403_PBU1, "PBU1", 1710 SPR_NOACCESS, SPR_NOACCESS, 1711 &spr_read_403_pbr, &spr_write_403_pbr, 1712 0x00000000); 1713 spr_register(env, SPR_403_PBL2, "PBL2", 1714 SPR_NOACCESS, SPR_NOACCESS, 1715 &spr_read_403_pbr, &spr_write_403_pbr, 1716 0x00000000); 1717 spr_register(env, SPR_403_PBU2, "PBU2", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_403_pbr, &spr_write_403_pbr, 1720 0x00000000); 1721 } 1722 1723 static void register_403_mmu_sprs(CPUPPCState *env) 1724 { 1725 /* MMU */ 1726 spr_register(env, SPR_40x_PID, "PID", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 spr_register(env, SPR_40x_ZPR, "ZPR", 1731 SPR_NOACCESS, SPR_NOACCESS, 1732 &spr_read_generic, &spr_write_generic, 1733 0x00000000); 1734 } 1735 1736 /* SPR specific to PowerPC compression coprocessor extension */ 1737 static void register_compress_sprs(CPUPPCState *env) 1738 { 1739 /* XXX : not implemented */ 1740 spr_register(env, SPR_401_SKR, "SKR", 1741 SPR_NOACCESS, SPR_NOACCESS, 1742 &spr_read_generic, &spr_write_generic, 1743 0x00000000); 1744 } 1745 1746 static void register_5xx_8xx_sprs(CPUPPCState *env) 1747 { 1748 /* Exception processing */ 1749 spr_register_kvm(env, SPR_DSISR, "DSISR", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 KVM_REG_PPC_DSISR, 0x00000000); 1753 spr_register_kvm(env, SPR_DAR, "DAR", 1754 SPR_NOACCESS, SPR_NOACCESS, 1755 &spr_read_generic, &spr_write_generic, 1756 KVM_REG_PPC_DAR, 0x00000000); 1757 /* Timer */ 1758 spr_register(env, SPR_DECR, "DECR", 1759 SPR_NOACCESS, SPR_NOACCESS, 1760 &spr_read_decr, &spr_write_decr, 1761 0x00000000); 1762 /* XXX : not implemented */ 1763 spr_register(env, SPR_MPC_EIE, "EIE", 1764 SPR_NOACCESS, SPR_NOACCESS, 1765 &spr_read_generic, &spr_write_generic, 1766 0x00000000); 1767 /* XXX : not implemented */ 1768 spr_register(env, SPR_MPC_EID, "EID", 1769 SPR_NOACCESS, SPR_NOACCESS, 1770 &spr_read_generic, &spr_write_generic, 1771 0x00000000); 1772 /* XXX : not implemented */ 1773 spr_register(env, SPR_MPC_NRI, "NRI", 1774 SPR_NOACCESS, SPR_NOACCESS, 1775 &spr_read_generic, &spr_write_generic, 1776 0x00000000); 1777 /* XXX : not implemented */ 1778 spr_register(env, SPR_MPC_CMPA, "CMPA", 1779 SPR_NOACCESS, SPR_NOACCESS, 1780 &spr_read_generic, &spr_write_generic, 1781 0x00000000); 1782 /* XXX : not implemented */ 1783 spr_register(env, SPR_MPC_CMPB, "CMPB", 1784 SPR_NOACCESS, SPR_NOACCESS, 1785 &spr_read_generic, &spr_write_generic, 1786 0x00000000); 1787 /* XXX : not implemented */ 1788 spr_register(env, SPR_MPC_CMPC, "CMPC", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 /* XXX : not implemented */ 1793 spr_register(env, SPR_MPC_CMPD, "CMPD", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 /* XXX : not implemented */ 1798 spr_register(env, SPR_MPC_ECR, "ECR", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 /* XXX : not implemented */ 1803 spr_register(env, SPR_MPC_DER, "DER", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 /* XXX : not implemented */ 1808 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 /* XXX : not implemented */ 1813 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 /* XXX : not implemented */ 1818 spr_register(env, SPR_MPC_CMPE, "CMPE", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 /* XXX : not implemented */ 1823 spr_register(env, SPR_MPC_CMPF, "CMPF", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 /* XXX : not implemented */ 1828 spr_register(env, SPR_MPC_CMPG, "CMPG", 1829 SPR_NOACCESS, SPR_NOACCESS, 1830 &spr_read_generic, &spr_write_generic, 1831 0x00000000); 1832 /* XXX : not implemented */ 1833 spr_register(env, SPR_MPC_CMPH, "CMPH", 1834 SPR_NOACCESS, SPR_NOACCESS, 1835 &spr_read_generic, &spr_write_generic, 1836 0x00000000); 1837 /* XXX : not implemented */ 1838 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1839 SPR_NOACCESS, SPR_NOACCESS, 1840 &spr_read_generic, &spr_write_generic, 1841 0x00000000); 1842 /* XXX : not implemented */ 1843 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1844 SPR_NOACCESS, SPR_NOACCESS, 1845 &spr_read_generic, &spr_write_generic, 1846 0x00000000); 1847 /* XXX : not implemented */ 1848 spr_register(env, SPR_MPC_BAR, "BAR", 1849 SPR_NOACCESS, SPR_NOACCESS, 1850 &spr_read_generic, &spr_write_generic, 1851 0x00000000); 1852 /* XXX : not implemented */ 1853 spr_register(env, SPR_MPC_DPDR, "DPDR", 1854 SPR_NOACCESS, SPR_NOACCESS, 1855 &spr_read_generic, &spr_write_generic, 1856 0x00000000); 1857 /* XXX : not implemented */ 1858 spr_register(env, SPR_MPC_IMMR, "IMMR", 1859 SPR_NOACCESS, SPR_NOACCESS, 1860 &spr_read_generic, &spr_write_generic, 1861 0x00000000); 1862 } 1863 1864 static void register_5xx_sprs(CPUPPCState *env) 1865 { 1866 /* XXX : not implemented */ 1867 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1868 SPR_NOACCESS, SPR_NOACCESS, 1869 &spr_read_generic, &spr_write_generic, 1870 0x00000000); 1871 /* XXX : not implemented */ 1872 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1873 SPR_NOACCESS, SPR_NOACCESS, 1874 &spr_read_generic, &spr_write_generic, 1875 0x00000000); 1876 /* XXX : not implemented */ 1877 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1878 SPR_NOACCESS, SPR_NOACCESS, 1879 &spr_read_generic, &spr_write_generic, 1880 0x00000000); 1881 /* XXX : not implemented */ 1882 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1883 SPR_NOACCESS, SPR_NOACCESS, 1884 &spr_read_generic, &spr_write_generic, 1885 0x00000000); 1886 /* XXX : not implemented */ 1887 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1888 SPR_NOACCESS, SPR_NOACCESS, 1889 &spr_read_generic, &spr_write_generic, 1890 0x00000000); 1891 /* XXX : not implemented */ 1892 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1893 SPR_NOACCESS, SPR_NOACCESS, 1894 &spr_read_generic, &spr_write_generic, 1895 0x00000000); 1896 /* XXX : not implemented */ 1897 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1898 SPR_NOACCESS, SPR_NOACCESS, 1899 &spr_read_generic, &spr_write_generic, 1900 0x00000000); 1901 /* XXX : not implemented */ 1902 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1903 SPR_NOACCESS, SPR_NOACCESS, 1904 &spr_read_generic, &spr_write_generic, 1905 0x00000000); 1906 /* XXX : not implemented */ 1907 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1908 SPR_NOACCESS, SPR_NOACCESS, 1909 &spr_read_generic, &spr_write_generic, 1910 0x00000000); 1911 /* XXX : not implemented */ 1912 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1913 SPR_NOACCESS, SPR_NOACCESS, 1914 &spr_read_generic, &spr_write_generic, 1915 0x00000000); 1916 /* XXX : not implemented */ 1917 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1918 SPR_NOACCESS, SPR_NOACCESS, 1919 &spr_read_generic, &spr_write_generic, 1920 0x00000000); 1921 /* XXX : not implemented */ 1922 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1923 SPR_NOACCESS, SPR_NOACCESS, 1924 &spr_read_generic, &spr_write_generic, 1925 0x00000000); 1926 /* XXX : not implemented */ 1927 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1928 SPR_NOACCESS, SPR_NOACCESS, 1929 &spr_read_generic, &spr_write_generic, 1930 0x00000000); 1931 /* XXX : not implemented */ 1932 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1933 SPR_NOACCESS, SPR_NOACCESS, 1934 &spr_read_generic, &spr_write_generic, 1935 0x00000000); 1936 /* XXX : not implemented */ 1937 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1938 SPR_NOACCESS, SPR_NOACCESS, 1939 &spr_read_generic, &spr_write_generic, 1940 0x00000000); 1941 /* XXX : not implemented */ 1942 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1943 SPR_NOACCESS, SPR_NOACCESS, 1944 &spr_read_generic, &spr_write_generic, 1945 0x00000000); 1946 /* XXX : not implemented */ 1947 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1948 SPR_NOACCESS, SPR_NOACCESS, 1949 &spr_read_generic, &spr_write_generic, 1950 0x00000000); 1951 /* XXX : not implemented */ 1952 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1953 SPR_NOACCESS, SPR_NOACCESS, 1954 &spr_read_generic, &spr_write_generic, 1955 0x00000000); 1956 /* XXX : not implemented */ 1957 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1958 SPR_NOACCESS, SPR_NOACCESS, 1959 &spr_read_generic, &spr_write_generic, 1960 0x00000000); 1961 /* XXX : not implemented */ 1962 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1963 SPR_NOACCESS, SPR_NOACCESS, 1964 &spr_read_generic, &spr_write_generic, 1965 0x00000000); 1966 /* XXX : not implemented */ 1967 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1968 SPR_NOACCESS, SPR_NOACCESS, 1969 &spr_read_generic, &spr_write_generic, 1970 0x00000000); 1971 } 1972 1973 static void register_8xx_sprs(CPUPPCState *env) 1974 { 1975 /* XXX : not implemented */ 1976 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1977 SPR_NOACCESS, SPR_NOACCESS, 1978 &spr_read_generic, &spr_write_generic, 1979 0x00000000); 1980 /* XXX : not implemented */ 1981 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1982 SPR_NOACCESS, SPR_NOACCESS, 1983 &spr_read_generic, &spr_write_generic, 1984 0x00000000); 1985 /* XXX : not implemented */ 1986 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1987 SPR_NOACCESS, SPR_NOACCESS, 1988 &spr_read_generic, &spr_write_generic, 1989 0x00000000); 1990 /* XXX : not implemented */ 1991 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1992 SPR_NOACCESS, SPR_NOACCESS, 1993 &spr_read_generic, &spr_write_generic, 1994 0x00000000); 1995 /* XXX : not implemented */ 1996 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1997 SPR_NOACCESS, SPR_NOACCESS, 1998 &spr_read_generic, &spr_write_generic, 1999 0x00000000); 2000 /* XXX : not implemented */ 2001 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 2002 SPR_NOACCESS, SPR_NOACCESS, 2003 &spr_read_generic, &spr_write_generic, 2004 0x00000000); 2005 /* XXX : not implemented */ 2006 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 2007 SPR_NOACCESS, SPR_NOACCESS, 2008 &spr_read_generic, &spr_write_generic, 2009 0x00000000); 2010 /* XXX : not implemented */ 2011 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 2012 SPR_NOACCESS, SPR_NOACCESS, 2013 &spr_read_generic, &spr_write_generic, 2014 0x00000000); 2015 /* XXX : not implemented */ 2016 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 2017 SPR_NOACCESS, SPR_NOACCESS, 2018 &spr_read_generic, &spr_write_generic, 2019 0x00000000); 2020 /* XXX : not implemented */ 2021 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 2022 SPR_NOACCESS, SPR_NOACCESS, 2023 &spr_read_generic, &spr_write_generic, 2024 0x00000000); 2025 /* XXX : not implemented */ 2026 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 2027 SPR_NOACCESS, SPR_NOACCESS, 2028 &spr_read_generic, &spr_write_generic, 2029 0x00000000); 2030 /* XXX : not implemented */ 2031 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 2032 SPR_NOACCESS, SPR_NOACCESS, 2033 &spr_read_generic, &spr_write_generic, 2034 0x00000000); 2035 /* XXX : not implemented */ 2036 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2037 SPR_NOACCESS, SPR_NOACCESS, 2038 &spr_read_generic, &spr_write_generic, 2039 0x00000000); 2040 /* XXX : not implemented */ 2041 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2042 SPR_NOACCESS, SPR_NOACCESS, 2043 &spr_read_generic, &spr_write_generic, 2044 0x00000000); 2045 /* XXX : not implemented */ 2046 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2047 SPR_NOACCESS, SPR_NOACCESS, 2048 &spr_read_generic, &spr_write_generic, 2049 0x00000000); 2050 /* XXX : not implemented */ 2051 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2052 SPR_NOACCESS, SPR_NOACCESS, 2053 &spr_read_generic, &spr_write_generic, 2054 0x00000000); 2055 /* XXX : not implemented */ 2056 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2057 SPR_NOACCESS, SPR_NOACCESS, 2058 &spr_read_generic, &spr_write_generic, 2059 0x00000000); 2060 /* XXX : not implemented */ 2061 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2062 SPR_NOACCESS, SPR_NOACCESS, 2063 &spr_read_generic, &spr_write_generic, 2064 0x00000000); 2065 /* XXX : not implemented */ 2066 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2067 SPR_NOACCESS, SPR_NOACCESS, 2068 &spr_read_generic, &spr_write_generic, 2069 0x00000000); 2070 /* XXX : not implemented */ 2071 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2072 SPR_NOACCESS, SPR_NOACCESS, 2073 &spr_read_generic, &spr_write_generic, 2074 0x00000000); 2075 /* XXX : not implemented */ 2076 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2077 SPR_NOACCESS, SPR_NOACCESS, 2078 &spr_read_generic, &spr_write_generic, 2079 0x00000000); 2080 /* XXX : not implemented */ 2081 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2082 SPR_NOACCESS, SPR_NOACCESS, 2083 &spr_read_generic, &spr_write_generic, 2084 0x00000000); 2085 /* XXX : not implemented */ 2086 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2087 SPR_NOACCESS, SPR_NOACCESS, 2088 &spr_read_generic, &spr_write_generic, 2089 0x00000000); 2090 /* XXX : not implemented */ 2091 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2092 SPR_NOACCESS, SPR_NOACCESS, 2093 &spr_read_generic, &spr_write_generic, 2094 0x00000000); 2095 /* XXX : not implemented */ 2096 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2097 SPR_NOACCESS, SPR_NOACCESS, 2098 &spr_read_generic, &spr_write_generic, 2099 0x00000000); 2100 } 2101 2102 /* 2103 * AMR => SPR 29 (Power 2.04) 2104 * CTRL => SPR 136 (Power 2.04) 2105 * CTRL => SPR 152 (Power 2.04) 2106 * SCOMC => SPR 276 (64 bits ?) 2107 * SCOMD => SPR 277 (64 bits ?) 2108 * TBU40 => SPR 286 (Power 2.04 hypv) 2109 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2110 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2111 * HDSISR => SPR 306 (Power 2.04 hypv) 2112 * HDAR => SPR 307 (Power 2.04 hypv) 2113 * PURR => SPR 309 (Power 2.04 hypv) 2114 * HDEC => SPR 310 (Power 2.04 hypv) 2115 * HIOR => SPR 311 (hypv) 2116 * RMOR => SPR 312 (970) 2117 * HRMOR => SPR 313 (Power 2.04 hypv) 2118 * HSRR0 => SPR 314 (Power 2.04 hypv) 2119 * HSRR1 => SPR 315 (Power 2.04 hypv) 2120 * LPIDR => SPR 317 (970) 2121 * EPR => SPR 702 (Power 2.04 emb) 2122 * perf => 768-783 (Power 2.04) 2123 * perf => 784-799 (Power 2.04) 2124 * PPR => SPR 896 (Power 2.04) 2125 * DABRX => 1015 (Power 2.04 hypv) 2126 * FPECR => SPR 1022 (?) 2127 * ... and more (thermal management, performance counters, ...) 2128 */ 2129 2130 /*****************************************************************************/ 2131 /* Exception vectors models */ 2132 static void init_excp_4xx_real(CPUPPCState *env) 2133 { 2134 #if !defined(CONFIG_USER_ONLY) 2135 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2136 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2137 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2138 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2139 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2140 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2141 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2142 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2143 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2144 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2145 env->ivor_mask = 0x0000FFF0UL; 2146 env->ivpr_mask = 0xFFFF0000UL; 2147 /* Hardware reset vector */ 2148 env->hreset_vector = 0xFFFFFFFCUL; 2149 #endif 2150 } 2151 2152 static void init_excp_4xx_softmmu(CPUPPCState *env) 2153 { 2154 #if !defined(CONFIG_USER_ONLY) 2155 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2158 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2163 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2164 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2165 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2166 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2167 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2168 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2169 env->ivor_mask = 0x0000FFF0UL; 2170 env->ivpr_mask = 0xFFFF0000UL; 2171 /* Hardware reset vector */ 2172 env->hreset_vector = 0xFFFFFFFCUL; 2173 #endif 2174 } 2175 2176 static void init_excp_MPC5xx(CPUPPCState *env) 2177 { 2178 #if !defined(CONFIG_USER_ONLY) 2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2181 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2182 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2183 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2184 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2185 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2186 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2187 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2188 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2189 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2190 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2191 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2192 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2193 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2194 env->ivor_mask = 0x0000FFF0UL; 2195 env->ivpr_mask = 0xFFFF0000UL; 2196 /* Hardware reset vector */ 2197 env->hreset_vector = 0x00000100UL; 2198 #endif 2199 } 2200 2201 static void init_excp_MPC8xx(CPUPPCState *env) 2202 { 2203 #if !defined(CONFIG_USER_ONLY) 2204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2205 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2206 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2207 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2208 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2209 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2210 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2211 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2212 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2213 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2214 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2215 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2216 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2217 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2218 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2219 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2220 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2221 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2222 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2223 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2224 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2225 env->ivor_mask = 0x0000FFF0UL; 2226 env->ivpr_mask = 0xFFFF0000UL; 2227 /* Hardware reset vector */ 2228 env->hreset_vector = 0x00000100UL; 2229 #endif 2230 } 2231 2232 static void init_excp_G2(CPUPPCState *env) 2233 { 2234 #if !defined(CONFIG_USER_ONLY) 2235 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2236 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2237 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2238 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2239 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2240 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2241 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2242 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2243 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2244 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2245 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2246 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2247 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2248 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2249 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2250 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2251 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2252 /* Hardware reset vector */ 2253 env->hreset_vector = 0x00000100UL; 2254 #endif 2255 } 2256 2257 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2258 { 2259 #if !defined(CONFIG_USER_ONLY) 2260 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2261 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2262 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2263 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2264 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2265 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2266 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2267 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2268 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2269 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2270 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2271 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2272 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2273 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2274 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2275 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2276 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2277 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2278 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2279 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2280 env->ivor_mask = 0x0000FFF7UL; 2281 env->ivpr_mask = ivpr_mask; 2282 /* Hardware reset vector */ 2283 env->hreset_vector = 0xFFFFFFFCUL; 2284 #endif 2285 } 2286 2287 static void init_excp_BookE(CPUPPCState *env) 2288 { 2289 #if !defined(CONFIG_USER_ONLY) 2290 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2291 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2292 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2293 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2294 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2295 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2296 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2297 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2298 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2299 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2300 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2301 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2302 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2303 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2304 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2305 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2306 env->ivor_mask = 0x0000FFF0UL; 2307 env->ivpr_mask = 0xFFFF0000UL; 2308 /* Hardware reset vector */ 2309 env->hreset_vector = 0xFFFFFFFCUL; 2310 #endif 2311 } 2312 2313 static void init_excp_601(CPUPPCState *env) 2314 { 2315 #if !defined(CONFIG_USER_ONLY) 2316 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2317 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2318 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2319 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2320 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2321 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2322 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2323 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2324 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2325 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2326 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2327 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2328 /* Hardware reset vector */ 2329 env->hreset_vector = 0x00000100UL; 2330 #endif 2331 } 2332 2333 static void init_excp_602(CPUPPCState *env) 2334 { 2335 #if !defined(CONFIG_USER_ONLY) 2336 /* XXX: exception prefix has a special behavior on 602 */ 2337 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2338 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2339 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2340 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2341 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2342 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2343 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2344 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2345 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2346 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2347 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2348 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2349 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2350 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2351 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2352 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2353 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 2354 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 2355 /* Hardware reset vector */ 2356 env->hreset_vector = 0x00000100UL; 2357 #endif 2358 } 2359 2360 static void init_excp_603(CPUPPCState *env) 2361 { 2362 #if !defined(CONFIG_USER_ONLY) 2363 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2364 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2365 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2366 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2367 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2368 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2369 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2370 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2371 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2372 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2373 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2374 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2375 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2376 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2377 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2378 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2379 /* Hardware reset vector */ 2380 env->hreset_vector = 0x00000100UL; 2381 #endif 2382 } 2383 2384 static void init_excp_604(CPUPPCState *env) 2385 { 2386 #if !defined(CONFIG_USER_ONLY) 2387 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2388 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2389 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2390 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2391 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2392 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2393 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2394 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2395 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2396 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2397 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2398 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2399 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2400 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2401 /* Hardware reset vector */ 2402 env->hreset_vector = 0x00000100UL; 2403 #endif 2404 } 2405 2406 static void init_excp_7x0(CPUPPCState *env) 2407 { 2408 #if !defined(CONFIG_USER_ONLY) 2409 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2410 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2411 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2412 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2413 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2414 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2415 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2416 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2417 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2418 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2419 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2423 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2424 /* Hardware reset vector */ 2425 env->hreset_vector = 0x00000100UL; 2426 #endif 2427 } 2428 2429 static void init_excp_750cl(CPUPPCState *env) 2430 { 2431 #if !defined(CONFIG_USER_ONLY) 2432 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2433 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2434 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2435 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2436 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2437 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2438 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2439 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2440 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2441 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2442 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2443 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2444 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2445 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2446 /* Hardware reset vector */ 2447 env->hreset_vector = 0x00000100UL; 2448 #endif 2449 } 2450 2451 static void init_excp_750cx(CPUPPCState *env) 2452 { 2453 #if !defined(CONFIG_USER_ONLY) 2454 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2455 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2456 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2457 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2458 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2459 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2460 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2461 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2462 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2463 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2464 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2465 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2466 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2467 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2468 /* Hardware reset vector */ 2469 env->hreset_vector = 0x00000100UL; 2470 #endif 2471 } 2472 2473 /* XXX: Check if this is correct */ 2474 static void init_excp_7x5(CPUPPCState *env) 2475 { 2476 #if !defined(CONFIG_USER_ONLY) 2477 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2478 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2479 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2480 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2481 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2482 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2483 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2484 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2485 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2486 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2487 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2488 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2489 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2490 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2491 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2492 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2493 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2494 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2495 /* Hardware reset vector */ 2496 env->hreset_vector = 0x00000100UL; 2497 #endif 2498 } 2499 2500 static void init_excp_7400(CPUPPCState *env) 2501 { 2502 #if !defined(CONFIG_USER_ONLY) 2503 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2504 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2505 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2506 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2507 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2508 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2509 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2510 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2511 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2512 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2513 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2514 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2515 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2516 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2517 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2518 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2519 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2520 /* Hardware reset vector */ 2521 env->hreset_vector = 0x00000100UL; 2522 #endif 2523 } 2524 2525 static void init_excp_7450(CPUPPCState *env) 2526 { 2527 #if !defined(CONFIG_USER_ONLY) 2528 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2529 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2530 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2531 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2532 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2533 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2534 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2535 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2536 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2537 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2538 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2539 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2540 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2541 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2542 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2543 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2544 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2545 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2546 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2547 /* Hardware reset vector */ 2548 env->hreset_vector = 0x00000100UL; 2549 #endif 2550 } 2551 2552 #if defined(TARGET_PPC64) 2553 static void init_excp_970(CPUPPCState *env) 2554 { 2555 #if !defined(CONFIG_USER_ONLY) 2556 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2557 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2558 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2559 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2560 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2561 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2562 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2563 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2564 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2565 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2566 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2567 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2568 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2569 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2570 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2571 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2572 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2573 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2574 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2575 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2576 /* Hardware reset vector */ 2577 env->hreset_vector = 0x0000000000000100ULL; 2578 #endif 2579 } 2580 2581 static void init_excp_POWER7(CPUPPCState *env) 2582 { 2583 #if !defined(CONFIG_USER_ONLY) 2584 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2585 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2586 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2587 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2588 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2589 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2590 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2591 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2592 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2593 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2594 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2595 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2596 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2597 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2598 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2599 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2600 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2601 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2602 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2603 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2604 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2605 /* Hardware reset vector */ 2606 env->hreset_vector = 0x0000000000000100ULL; 2607 #endif 2608 } 2609 2610 static void init_excp_POWER8(CPUPPCState *env) 2611 { 2612 init_excp_POWER7(env); 2613 2614 #if !defined(CONFIG_USER_ONLY) 2615 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2616 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2617 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2618 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2619 #endif 2620 } 2621 2622 static void init_excp_POWER9(CPUPPCState *env) 2623 { 2624 init_excp_POWER8(env); 2625 2626 #if !defined(CONFIG_USER_ONLY) 2627 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2628 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2629 #endif 2630 } 2631 2632 static void init_excp_POWER10(CPUPPCState *env) 2633 { 2634 init_excp_POWER9(env); 2635 } 2636 2637 #endif 2638 2639 /*****************************************************************************/ 2640 /* Power management enable checks */ 2641 static int check_pow_none(CPUPPCState *env) 2642 { 2643 return 0; 2644 } 2645 2646 static int check_pow_nocheck(CPUPPCState *env) 2647 { 2648 return 1; 2649 } 2650 2651 static int check_pow_hid0(CPUPPCState *env) 2652 { 2653 if (env->spr[SPR_HID0] & 0x00E00000) { 2654 return 1; 2655 } 2656 2657 return 0; 2658 } 2659 2660 static int check_pow_hid0_74xx(CPUPPCState *env) 2661 { 2662 if (env->spr[SPR_HID0] & 0x00600000) { 2663 return 1; 2664 } 2665 2666 return 0; 2667 } 2668 2669 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) 2670 { 2671 return true; 2672 } 2673 2674 #ifdef TARGET_PPC64 2675 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) 2676 { 2677 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); 2678 } 2679 #endif 2680 2681 /*****************************************************************************/ 2682 /* PowerPC implementations definitions */ 2683 2684 #define POWERPC_FAMILY(_name) \ 2685 static void \ 2686 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2687 \ 2688 static const TypeInfo \ 2689 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2690 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2691 .parent = TYPE_POWERPC_CPU, \ 2692 .abstract = true, \ 2693 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2694 }; \ 2695 \ 2696 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2697 { \ 2698 type_register_static( \ 2699 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2700 } \ 2701 \ 2702 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2703 \ 2704 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2705 2706 static void init_proc_401(CPUPPCState *env) 2707 { 2708 register_40x_sprs(env); 2709 register_401_403_sprs(env); 2710 register_401_sprs(env); 2711 init_excp_4xx_real(env); 2712 env->dcache_line_size = 32; 2713 env->icache_line_size = 32; 2714 /* Allocate hardware IRQ controller */ 2715 ppc40x_irq_init(env_archcpu(env)); 2716 2717 SET_FIT_PERIOD(12, 16, 20, 24); 2718 SET_WDT_PERIOD(16, 20, 24, 28); 2719 } 2720 2721 POWERPC_FAMILY(401)(ObjectClass *oc, void *data) 2722 { 2723 DeviceClass *dc = DEVICE_CLASS(oc); 2724 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2725 2726 dc->desc = "PowerPC 401"; 2727 pcc->init_proc = init_proc_401; 2728 pcc->check_pow = check_pow_nocheck; 2729 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2730 PPC_WRTEE | PPC_DCR | 2731 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2732 PPC_CACHE_DCBZ | 2733 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2734 PPC_4xx_COMMON | PPC_40x_EXCP; 2735 pcc->msr_mask = (1ull << MSR_KEY) | 2736 (1ull << MSR_POW) | 2737 (1ull << MSR_CE) | 2738 (1ull << MSR_ILE) | 2739 (1ull << MSR_EE) | 2740 (1ull << MSR_PR) | 2741 (1ull << MSR_ME) | 2742 (1ull << MSR_DE) | 2743 (1ull << MSR_LE); 2744 pcc->mmu_model = POWERPC_MMU_REAL; 2745 pcc->excp_model = POWERPC_EXCP_40x; 2746 pcc->bus_model = PPC_FLAGS_INPUT_401; 2747 pcc->bfd_mach = bfd_mach_ppc_403; 2748 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2749 POWERPC_FLAG_BUS_CLK; 2750 } 2751 2752 static void init_proc_401x2(CPUPPCState *env) 2753 { 2754 register_40x_sprs(env); 2755 register_401_403_sprs(env); 2756 register_401x2_sprs(env); 2757 register_compress_sprs(env); 2758 /* Memory management */ 2759 #if !defined(CONFIG_USER_ONLY) 2760 env->nb_tlb = 64; 2761 env->nb_ways = 1; 2762 env->id_tlbs = 0; 2763 env->tlb_type = TLB_EMB; 2764 #endif 2765 init_excp_4xx_softmmu(env); 2766 env->dcache_line_size = 32; 2767 env->icache_line_size = 32; 2768 /* Allocate hardware IRQ controller */ 2769 ppc40x_irq_init(env_archcpu(env)); 2770 2771 SET_FIT_PERIOD(12, 16, 20, 24); 2772 SET_WDT_PERIOD(16, 20, 24, 28); 2773 } 2774 2775 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) 2776 { 2777 DeviceClass *dc = DEVICE_CLASS(oc); 2778 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2779 2780 dc->desc = "PowerPC 401x2"; 2781 pcc->init_proc = init_proc_401x2; 2782 pcc->check_pow = check_pow_nocheck; 2783 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2784 PPC_DCR | PPC_WRTEE | 2785 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2786 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2787 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2788 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2789 PPC_4xx_COMMON | PPC_40x_EXCP; 2790 pcc->msr_mask = (1ull << 20) | 2791 (1ull << MSR_KEY) | 2792 (1ull << MSR_POW) | 2793 (1ull << MSR_CE) | 2794 (1ull << MSR_ILE) | 2795 (1ull << MSR_EE) | 2796 (1ull << MSR_PR) | 2797 (1ull << MSR_ME) | 2798 (1ull << MSR_DE) | 2799 (1ull << MSR_IR) | 2800 (1ull << MSR_DR) | 2801 (1ull << MSR_LE); 2802 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2803 pcc->excp_model = POWERPC_EXCP_40x; 2804 pcc->bus_model = PPC_FLAGS_INPUT_401; 2805 pcc->bfd_mach = bfd_mach_ppc_403; 2806 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2807 POWERPC_FLAG_BUS_CLK; 2808 } 2809 2810 static void init_proc_401x3(CPUPPCState *env) 2811 { 2812 register_40x_sprs(env); 2813 register_401_403_sprs(env); 2814 register_401_sprs(env); 2815 register_401x2_sprs(env); 2816 register_compress_sprs(env); 2817 init_excp_4xx_softmmu(env); 2818 env->dcache_line_size = 32; 2819 env->icache_line_size = 32; 2820 /* Allocate hardware IRQ controller */ 2821 ppc40x_irq_init(env_archcpu(env)); 2822 2823 SET_FIT_PERIOD(12, 16, 20, 24); 2824 SET_WDT_PERIOD(16, 20, 24, 28); 2825 } 2826 2827 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) 2828 { 2829 DeviceClass *dc = DEVICE_CLASS(oc); 2830 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2831 2832 dc->desc = "PowerPC 401x3"; 2833 pcc->init_proc = init_proc_401x3; 2834 pcc->check_pow = check_pow_nocheck; 2835 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2836 PPC_DCR | PPC_WRTEE | 2837 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2838 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2839 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2840 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2841 PPC_4xx_COMMON | PPC_40x_EXCP; 2842 pcc->msr_mask = (1ull << 20) | 2843 (1ull << MSR_KEY) | 2844 (1ull << MSR_POW) | 2845 (1ull << MSR_CE) | 2846 (1ull << MSR_ILE) | 2847 (1ull << MSR_EE) | 2848 (1ull << MSR_PR) | 2849 (1ull << MSR_ME) | 2850 (1ull << MSR_DWE) | 2851 (1ull << MSR_DE) | 2852 (1ull << MSR_IR) | 2853 (1ull << MSR_DR) | 2854 (1ull << MSR_LE); 2855 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2856 pcc->excp_model = POWERPC_EXCP_40x; 2857 pcc->bus_model = PPC_FLAGS_INPUT_401; 2858 pcc->bfd_mach = bfd_mach_ppc_403; 2859 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2860 POWERPC_FLAG_BUS_CLK; 2861 } 2862 2863 static void init_proc_IOP480(CPUPPCState *env) 2864 { 2865 register_40x_sprs(env); 2866 register_401_403_sprs(env); 2867 register_401x2_sprs(env); 2868 register_compress_sprs(env); 2869 /* Memory management */ 2870 #if !defined(CONFIG_USER_ONLY) 2871 env->nb_tlb = 64; 2872 env->nb_ways = 1; 2873 env->id_tlbs = 0; 2874 env->tlb_type = TLB_EMB; 2875 #endif 2876 init_excp_4xx_softmmu(env); 2877 env->dcache_line_size = 32; 2878 env->icache_line_size = 32; 2879 /* Allocate hardware IRQ controller */ 2880 ppc40x_irq_init(env_archcpu(env)); 2881 2882 SET_FIT_PERIOD(8, 12, 16, 20); 2883 SET_WDT_PERIOD(16, 20, 24, 28); 2884 } 2885 2886 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) 2887 { 2888 DeviceClass *dc = DEVICE_CLASS(oc); 2889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2890 2891 dc->desc = "IOP480"; 2892 pcc->init_proc = init_proc_IOP480; 2893 pcc->check_pow = check_pow_nocheck; 2894 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2895 PPC_DCR | PPC_WRTEE | 2896 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2897 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2898 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2899 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2900 PPC_4xx_COMMON | PPC_40x_EXCP; 2901 pcc->msr_mask = (1ull << 20) | 2902 (1ull << MSR_KEY) | 2903 (1ull << MSR_POW) | 2904 (1ull << MSR_CE) | 2905 (1ull << MSR_ILE) | 2906 (1ull << MSR_EE) | 2907 (1ull << MSR_PR) | 2908 (1ull << MSR_ME) | 2909 (1ull << MSR_DE) | 2910 (1ull << MSR_IR) | 2911 (1ull << MSR_DR) | 2912 (1ull << MSR_LE); 2913 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2914 pcc->excp_model = POWERPC_EXCP_40x; 2915 pcc->bus_model = PPC_FLAGS_INPUT_401; 2916 pcc->bfd_mach = bfd_mach_ppc_403; 2917 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2918 POWERPC_FLAG_BUS_CLK; 2919 } 2920 2921 static void init_proc_403(CPUPPCState *env) 2922 { 2923 register_40x_sprs(env); 2924 register_401_403_sprs(env); 2925 register_403_sprs(env); 2926 register_403_real_sprs(env); 2927 init_excp_4xx_real(env); 2928 env->dcache_line_size = 32; 2929 env->icache_line_size = 32; 2930 /* Allocate hardware IRQ controller */ 2931 ppc40x_irq_init(env_archcpu(env)); 2932 2933 SET_FIT_PERIOD(8, 12, 16, 20); 2934 SET_WDT_PERIOD(16, 20, 24, 28); 2935 } 2936 2937 POWERPC_FAMILY(403)(ObjectClass *oc, void *data) 2938 { 2939 DeviceClass *dc = DEVICE_CLASS(oc); 2940 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2941 2942 dc->desc = "PowerPC 403"; 2943 pcc->init_proc = init_proc_403; 2944 pcc->check_pow = check_pow_nocheck; 2945 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2946 PPC_DCR | PPC_WRTEE | 2947 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2948 PPC_CACHE_DCBZ | 2949 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2950 PPC_4xx_COMMON | PPC_40x_EXCP; 2951 pcc->msr_mask = (1ull << MSR_POW) | 2952 (1ull << MSR_CE) | 2953 (1ull << MSR_ILE) | 2954 (1ull << MSR_EE) | 2955 (1ull << MSR_PR) | 2956 (1ull << MSR_ME) | 2957 (1ull << MSR_PE) | 2958 (1ull << MSR_PX) | 2959 (1ull << MSR_LE); 2960 pcc->mmu_model = POWERPC_MMU_REAL; 2961 pcc->excp_model = POWERPC_EXCP_40x; 2962 pcc->bus_model = PPC_FLAGS_INPUT_401; 2963 pcc->bfd_mach = bfd_mach_ppc_403; 2964 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 2965 POWERPC_FLAG_BUS_CLK; 2966 } 2967 2968 static void init_proc_403GCX(CPUPPCState *env) 2969 { 2970 register_40x_sprs(env); 2971 register_401_403_sprs(env); 2972 register_403_sprs(env); 2973 register_403_real_sprs(env); 2974 register_403_mmu_sprs(env); 2975 /* Bus access control */ 2976 /* not emulated, as QEMU never does speculative access */ 2977 spr_register(env, SPR_40x_SGR, "SGR", 2978 SPR_NOACCESS, SPR_NOACCESS, 2979 &spr_read_generic, &spr_write_generic, 2980 0xFFFFFFFF); 2981 /* not emulated, as QEMU do not emulate caches */ 2982 spr_register(env, SPR_40x_DCWR, "DCWR", 2983 SPR_NOACCESS, SPR_NOACCESS, 2984 &spr_read_generic, &spr_write_generic, 2985 0x00000000); 2986 /* Memory management */ 2987 #if !defined(CONFIG_USER_ONLY) 2988 env->nb_tlb = 64; 2989 env->nb_ways = 1; 2990 env->id_tlbs = 0; 2991 env->tlb_type = TLB_EMB; 2992 #endif 2993 init_excp_4xx_softmmu(env); 2994 env->dcache_line_size = 32; 2995 env->icache_line_size = 32; 2996 /* Allocate hardware IRQ controller */ 2997 ppc40x_irq_init(env_archcpu(env)); 2998 2999 SET_FIT_PERIOD(8, 12, 16, 20); 3000 SET_WDT_PERIOD(16, 20, 24, 28); 3001 } 3002 3003 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) 3004 { 3005 DeviceClass *dc = DEVICE_CLASS(oc); 3006 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3007 3008 dc->desc = "PowerPC 403 GCX"; 3009 pcc->init_proc = init_proc_403GCX; 3010 pcc->check_pow = check_pow_nocheck; 3011 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3012 PPC_DCR | PPC_WRTEE | 3013 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3014 PPC_CACHE_DCBZ | 3015 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3016 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3017 PPC_4xx_COMMON | PPC_40x_EXCP; 3018 pcc->msr_mask = (1ull << MSR_POW) | 3019 (1ull << MSR_CE) | 3020 (1ull << MSR_ILE) | 3021 (1ull << MSR_EE) | 3022 (1ull << MSR_PR) | 3023 (1ull << MSR_ME) | 3024 (1ull << MSR_PE) | 3025 (1ull << MSR_PX) | 3026 (1ull << MSR_LE); 3027 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3028 pcc->excp_model = POWERPC_EXCP_40x; 3029 pcc->bus_model = PPC_FLAGS_INPUT_401; 3030 pcc->bfd_mach = bfd_mach_ppc_403; 3031 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3032 POWERPC_FLAG_BUS_CLK; 3033 } 3034 3035 static void init_proc_405(CPUPPCState *env) 3036 { 3037 /* Time base */ 3038 register_tbl(env); 3039 register_40x_sprs(env); 3040 register_405_sprs(env); 3041 /* Bus access control */ 3042 /* not emulated, as QEMU never does speculative access */ 3043 spr_register(env, SPR_40x_SGR, "SGR", 3044 SPR_NOACCESS, SPR_NOACCESS, 3045 &spr_read_generic, &spr_write_generic, 3046 0xFFFFFFFF); 3047 /* not emulated, as QEMU do not emulate caches */ 3048 spr_register(env, SPR_40x_DCWR, "DCWR", 3049 SPR_NOACCESS, SPR_NOACCESS, 3050 &spr_read_generic, &spr_write_generic, 3051 0x00000000); 3052 /* Memory management */ 3053 #if !defined(CONFIG_USER_ONLY) 3054 env->nb_tlb = 64; 3055 env->nb_ways = 1; 3056 env->id_tlbs = 0; 3057 env->tlb_type = TLB_EMB; 3058 #endif 3059 init_excp_4xx_softmmu(env); 3060 env->dcache_line_size = 32; 3061 env->icache_line_size = 32; 3062 /* Allocate hardware IRQ controller */ 3063 ppc40x_irq_init(env_archcpu(env)); 3064 3065 SET_FIT_PERIOD(8, 12, 16, 20); 3066 SET_WDT_PERIOD(16, 20, 24, 28); 3067 } 3068 3069 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 3070 { 3071 DeviceClass *dc = DEVICE_CLASS(oc); 3072 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3073 3074 dc->desc = "PowerPC 405"; 3075 pcc->init_proc = init_proc_405; 3076 pcc->check_pow = check_pow_nocheck; 3077 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3078 PPC_DCR | PPC_WRTEE | 3079 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3080 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3081 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3082 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3083 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 3084 pcc->msr_mask = (1ull << MSR_POW) | 3085 (1ull << MSR_CE) | 3086 (1ull << MSR_EE) | 3087 (1ull << MSR_PR) | 3088 (1ull << MSR_FP) | 3089 (1ull << MSR_DWE) | 3090 (1ull << MSR_DE) | 3091 (1ull << MSR_IR) | 3092 (1ull << MSR_DR); 3093 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 3094 pcc->excp_model = POWERPC_EXCP_40x; 3095 pcc->bus_model = PPC_FLAGS_INPUT_405; 3096 pcc->bfd_mach = bfd_mach_ppc_403; 3097 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3098 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3099 } 3100 3101 static void init_proc_440EP(CPUPPCState *env) 3102 { 3103 /* Time base */ 3104 register_tbl(env); 3105 register_BookE_sprs(env, 0x000000000000FFFFULL); 3106 register_440_sprs(env); 3107 register_usprgh_sprs(env); 3108 /* Processor identification */ 3109 spr_register(env, SPR_BOOKE_PIR, "PIR", 3110 SPR_NOACCESS, SPR_NOACCESS, 3111 &spr_read_generic, &spr_write_pir, 3112 0x00000000); 3113 /* XXX : not implemented */ 3114 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3115 SPR_NOACCESS, SPR_NOACCESS, 3116 &spr_read_generic, &spr_write_generic, 3117 0x00000000); 3118 /* XXX : not implemented */ 3119 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3120 SPR_NOACCESS, SPR_NOACCESS, 3121 &spr_read_generic, &spr_write_generic, 3122 0x00000000); 3123 /* XXX : not implemented */ 3124 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3125 SPR_NOACCESS, SPR_NOACCESS, 3126 &spr_read_generic, &spr_write_generic, 3127 0x00000000); 3128 /* XXX : not implemented */ 3129 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3130 SPR_NOACCESS, SPR_NOACCESS, 3131 &spr_read_generic, &spr_write_generic, 3132 0x00000000); 3133 /* XXX : not implemented */ 3134 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3135 SPR_NOACCESS, SPR_NOACCESS, 3136 &spr_read_generic, &spr_write_generic, 3137 0x00000000); 3138 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3139 SPR_NOACCESS, SPR_NOACCESS, 3140 &spr_read_generic, &spr_write_generic, 3141 0x00000000); 3142 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3143 SPR_NOACCESS, SPR_NOACCESS, 3144 &spr_read_generic, &spr_write_generic, 3145 0x00000000); 3146 /* XXX : not implemented */ 3147 spr_register(env, SPR_440_CCR1, "CCR1", 3148 SPR_NOACCESS, SPR_NOACCESS, 3149 &spr_read_generic, &spr_write_generic, 3150 0x00000000); 3151 /* Memory management */ 3152 #if !defined(CONFIG_USER_ONLY) 3153 env->nb_tlb = 64; 3154 env->nb_ways = 1; 3155 env->id_tlbs = 0; 3156 env->tlb_type = TLB_EMB; 3157 #endif 3158 init_excp_BookE(env); 3159 env->dcache_line_size = 32; 3160 env->icache_line_size = 32; 3161 ppc40x_irq_init(env_archcpu(env)); 3162 3163 SET_FIT_PERIOD(12, 16, 20, 24); 3164 SET_WDT_PERIOD(20, 24, 28, 32); 3165 } 3166 3167 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 3168 { 3169 DeviceClass *dc = DEVICE_CLASS(oc); 3170 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3171 3172 dc->desc = "PowerPC 440 EP"; 3173 pcc->init_proc = init_proc_440EP; 3174 pcc->check_pow = check_pow_nocheck; 3175 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3176 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3177 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3178 PPC_FLOAT_STFIWX | 3179 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3180 PPC_CACHE | PPC_CACHE_ICBI | 3181 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3182 PPC_MEM_TLBSYNC | PPC_MFTB | 3183 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3184 PPC_440_SPEC; 3185 pcc->msr_mask = (1ull << MSR_POW) | 3186 (1ull << MSR_CE) | 3187 (1ull << MSR_EE) | 3188 (1ull << MSR_PR) | 3189 (1ull << MSR_FP) | 3190 (1ull << MSR_ME) | 3191 (1ull << MSR_FE0) | 3192 (1ull << MSR_DWE) | 3193 (1ull << MSR_DE) | 3194 (1ull << MSR_FE1) | 3195 (1ull << MSR_IR) | 3196 (1ull << MSR_DR); 3197 pcc->mmu_model = POWERPC_MMU_BOOKE; 3198 pcc->excp_model = POWERPC_EXCP_BOOKE; 3199 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3200 pcc->bfd_mach = bfd_mach_ppc_403; 3201 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3202 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3203 } 3204 3205 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 3206 { 3207 DeviceClass *dc = DEVICE_CLASS(oc); 3208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3209 3210 dc->desc = "PowerPC 460 EX"; 3211 pcc->init_proc = init_proc_440EP; 3212 pcc->check_pow = check_pow_nocheck; 3213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3214 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3215 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3216 PPC_FLOAT_STFIWX | 3217 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 3218 PPC_CACHE | PPC_CACHE_ICBI | 3219 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3220 PPC_MEM_TLBSYNC | PPC_MFTB | 3221 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3222 PPC_440_SPEC; 3223 pcc->msr_mask = (1ull << MSR_POW) | 3224 (1ull << MSR_CE) | 3225 (1ull << MSR_EE) | 3226 (1ull << MSR_PR) | 3227 (1ull << MSR_FP) | 3228 (1ull << MSR_ME) | 3229 (1ull << MSR_FE0) | 3230 (1ull << MSR_DWE) | 3231 (1ull << MSR_DE) | 3232 (1ull << MSR_FE1) | 3233 (1ull << MSR_IR) | 3234 (1ull << MSR_DR); 3235 pcc->mmu_model = POWERPC_MMU_BOOKE; 3236 pcc->excp_model = POWERPC_EXCP_BOOKE; 3237 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3238 pcc->bfd_mach = bfd_mach_ppc_403; 3239 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3240 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3241 } 3242 3243 static void init_proc_440GP(CPUPPCState *env) 3244 { 3245 /* Time base */ 3246 register_tbl(env); 3247 register_BookE_sprs(env, 0x000000000000FFFFULL); 3248 register_440_sprs(env); 3249 register_usprgh_sprs(env); 3250 /* Processor identification */ 3251 spr_register(env, SPR_BOOKE_PIR, "PIR", 3252 SPR_NOACCESS, SPR_NOACCESS, 3253 &spr_read_generic, &spr_write_pir, 3254 0x00000000); 3255 /* XXX : not implemented */ 3256 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3257 SPR_NOACCESS, SPR_NOACCESS, 3258 &spr_read_generic, &spr_write_generic, 3259 0x00000000); 3260 /* XXX : not implemented */ 3261 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3262 SPR_NOACCESS, SPR_NOACCESS, 3263 &spr_read_generic, &spr_write_generic, 3264 0x00000000); 3265 /* XXX : not implemented */ 3266 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3267 SPR_NOACCESS, SPR_NOACCESS, 3268 &spr_read_generic, &spr_write_generic, 3269 0x00000000); 3270 /* XXX : not implemented */ 3271 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3272 SPR_NOACCESS, SPR_NOACCESS, 3273 &spr_read_generic, &spr_write_generic, 3274 0x00000000); 3275 /* Memory management */ 3276 #if !defined(CONFIG_USER_ONLY) 3277 env->nb_tlb = 64; 3278 env->nb_ways = 1; 3279 env->id_tlbs = 0; 3280 env->tlb_type = TLB_EMB; 3281 #endif 3282 init_excp_BookE(env); 3283 env->dcache_line_size = 32; 3284 env->icache_line_size = 32; 3285 /* XXX: TODO: allocate internal IRQ controller */ 3286 3287 SET_FIT_PERIOD(12, 16, 20, 24); 3288 SET_WDT_PERIOD(20, 24, 28, 32); 3289 } 3290 3291 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 3292 { 3293 DeviceClass *dc = DEVICE_CLASS(oc); 3294 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3295 3296 dc->desc = "PowerPC 440 GP"; 3297 pcc->init_proc = init_proc_440GP; 3298 pcc->check_pow = check_pow_nocheck; 3299 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3300 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 3301 PPC_CACHE | PPC_CACHE_ICBI | 3302 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3303 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 3304 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3305 PPC_440_SPEC; 3306 pcc->msr_mask = (1ull << MSR_POW) | 3307 (1ull << MSR_CE) | 3308 (1ull << MSR_EE) | 3309 (1ull << MSR_PR) | 3310 (1ull << MSR_FP) | 3311 (1ull << MSR_ME) | 3312 (1ull << MSR_FE0) | 3313 (1ull << MSR_DWE) | 3314 (1ull << MSR_DE) | 3315 (1ull << MSR_FE1) | 3316 (1ull << MSR_IR) | 3317 (1ull << MSR_DR); 3318 pcc->mmu_model = POWERPC_MMU_BOOKE; 3319 pcc->excp_model = POWERPC_EXCP_BOOKE; 3320 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3321 pcc->bfd_mach = bfd_mach_ppc_403; 3322 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3323 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3324 } 3325 3326 static void init_proc_440x4(CPUPPCState *env) 3327 { 3328 /* Time base */ 3329 register_tbl(env); 3330 register_BookE_sprs(env, 0x000000000000FFFFULL); 3331 register_440_sprs(env); 3332 register_usprgh_sprs(env); 3333 /* Processor identification */ 3334 spr_register(env, SPR_BOOKE_PIR, "PIR", 3335 SPR_NOACCESS, SPR_NOACCESS, 3336 &spr_read_generic, &spr_write_pir, 3337 0x00000000); 3338 /* XXX : not implemented */ 3339 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3340 SPR_NOACCESS, SPR_NOACCESS, 3341 &spr_read_generic, &spr_write_generic, 3342 0x00000000); 3343 /* XXX : not implemented */ 3344 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3345 SPR_NOACCESS, SPR_NOACCESS, 3346 &spr_read_generic, &spr_write_generic, 3347 0x00000000); 3348 /* XXX : not implemented */ 3349 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3350 SPR_NOACCESS, SPR_NOACCESS, 3351 &spr_read_generic, &spr_write_generic, 3352 0x00000000); 3353 /* XXX : not implemented */ 3354 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3355 SPR_NOACCESS, SPR_NOACCESS, 3356 &spr_read_generic, &spr_write_generic, 3357 0x00000000); 3358 /* Memory management */ 3359 #if !defined(CONFIG_USER_ONLY) 3360 env->nb_tlb = 64; 3361 env->nb_ways = 1; 3362 env->id_tlbs = 0; 3363 env->tlb_type = TLB_EMB; 3364 #endif 3365 init_excp_BookE(env); 3366 env->dcache_line_size = 32; 3367 env->icache_line_size = 32; 3368 /* XXX: TODO: allocate internal IRQ controller */ 3369 3370 SET_FIT_PERIOD(12, 16, 20, 24); 3371 SET_WDT_PERIOD(20, 24, 28, 32); 3372 } 3373 3374 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 3375 { 3376 DeviceClass *dc = DEVICE_CLASS(oc); 3377 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3378 3379 dc->desc = "PowerPC 440x4"; 3380 pcc->init_proc = init_proc_440x4; 3381 pcc->check_pow = check_pow_nocheck; 3382 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3383 PPC_DCR | PPC_WRTEE | 3384 PPC_CACHE | PPC_CACHE_ICBI | 3385 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3386 PPC_MEM_TLBSYNC | PPC_MFTB | 3387 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3388 PPC_440_SPEC; 3389 pcc->msr_mask = (1ull << MSR_POW) | 3390 (1ull << MSR_CE) | 3391 (1ull << MSR_EE) | 3392 (1ull << MSR_PR) | 3393 (1ull << MSR_FP) | 3394 (1ull << MSR_ME) | 3395 (1ull << MSR_FE0) | 3396 (1ull << MSR_DWE) | 3397 (1ull << MSR_DE) | 3398 (1ull << MSR_FE1) | 3399 (1ull << MSR_IR) | 3400 (1ull << MSR_DR); 3401 pcc->mmu_model = POWERPC_MMU_BOOKE; 3402 pcc->excp_model = POWERPC_EXCP_BOOKE; 3403 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3404 pcc->bfd_mach = bfd_mach_ppc_403; 3405 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3406 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3407 } 3408 3409 static void init_proc_440x5(CPUPPCState *env) 3410 { 3411 /* Time base */ 3412 register_tbl(env); 3413 register_BookE_sprs(env, 0x000000000000FFFFULL); 3414 register_440_sprs(env); 3415 register_usprgh_sprs(env); 3416 /* Processor identification */ 3417 spr_register(env, SPR_BOOKE_PIR, "PIR", 3418 SPR_NOACCESS, SPR_NOACCESS, 3419 &spr_read_generic, &spr_write_pir, 3420 0x00000000); 3421 /* XXX : not implemented */ 3422 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3423 SPR_NOACCESS, SPR_NOACCESS, 3424 &spr_read_generic, &spr_write_generic, 3425 0x00000000); 3426 /* XXX : not implemented */ 3427 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3428 SPR_NOACCESS, SPR_NOACCESS, 3429 &spr_read_generic, &spr_write_generic, 3430 0x00000000); 3431 /* XXX : not implemented */ 3432 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3433 SPR_NOACCESS, SPR_NOACCESS, 3434 &spr_read_generic, &spr_write_generic, 3435 0x00000000); 3436 /* XXX : not implemented */ 3437 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3438 SPR_NOACCESS, SPR_NOACCESS, 3439 &spr_read_generic, &spr_write_generic, 3440 0x00000000); 3441 /* XXX : not implemented */ 3442 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3443 SPR_NOACCESS, SPR_NOACCESS, 3444 &spr_read_generic, &spr_write_generic, 3445 0x00000000); 3446 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3447 SPR_NOACCESS, SPR_NOACCESS, 3448 &spr_read_generic, &spr_write_generic, 3449 0x00000000); 3450 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3451 SPR_NOACCESS, SPR_NOACCESS, 3452 &spr_read_generic, &spr_write_generic, 3453 0x00000000); 3454 /* XXX : not implemented */ 3455 spr_register(env, SPR_440_CCR1, "CCR1", 3456 SPR_NOACCESS, SPR_NOACCESS, 3457 &spr_read_generic, &spr_write_generic, 3458 0x00000000); 3459 /* Memory management */ 3460 #if !defined(CONFIG_USER_ONLY) 3461 env->nb_tlb = 64; 3462 env->nb_ways = 1; 3463 env->id_tlbs = 0; 3464 env->tlb_type = TLB_EMB; 3465 #endif 3466 init_excp_BookE(env); 3467 env->dcache_line_size = 32; 3468 env->icache_line_size = 32; 3469 ppc40x_irq_init(env_archcpu(env)); 3470 3471 SET_FIT_PERIOD(12, 16, 20, 24); 3472 SET_WDT_PERIOD(20, 24, 28, 32); 3473 } 3474 3475 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 3476 { 3477 DeviceClass *dc = DEVICE_CLASS(oc); 3478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3479 3480 dc->desc = "PowerPC 440x5"; 3481 pcc->init_proc = init_proc_440x5; 3482 pcc->check_pow = check_pow_nocheck; 3483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3484 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3485 PPC_CACHE | PPC_CACHE_ICBI | 3486 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3487 PPC_MEM_TLBSYNC | PPC_MFTB | 3488 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3489 PPC_440_SPEC; 3490 pcc->msr_mask = (1ull << MSR_POW) | 3491 (1ull << MSR_CE) | 3492 (1ull << MSR_EE) | 3493 (1ull << MSR_PR) | 3494 (1ull << MSR_FP) | 3495 (1ull << MSR_ME) | 3496 (1ull << MSR_FE0) | 3497 (1ull << MSR_DWE) | 3498 (1ull << MSR_DE) | 3499 (1ull << MSR_FE1) | 3500 (1ull << MSR_IR) | 3501 (1ull << MSR_DR); 3502 pcc->mmu_model = POWERPC_MMU_BOOKE; 3503 pcc->excp_model = POWERPC_EXCP_BOOKE; 3504 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3505 pcc->bfd_mach = bfd_mach_ppc_403; 3506 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3507 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3508 } 3509 3510 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 3511 { 3512 DeviceClass *dc = DEVICE_CLASS(oc); 3513 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3514 3515 dc->desc = "PowerPC 440x5 with double precision FPU"; 3516 pcc->init_proc = init_proc_440x5; 3517 pcc->check_pow = check_pow_nocheck; 3518 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3519 PPC_FLOAT | PPC_FLOAT_FSQRT | 3520 PPC_FLOAT_STFIWX | 3521 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3522 PPC_CACHE | PPC_CACHE_ICBI | 3523 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3524 PPC_MEM_TLBSYNC | PPC_MFTB | 3525 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3526 PPC_440_SPEC; 3527 pcc->insns_flags2 = PPC2_FP_CVT_S64; 3528 pcc->msr_mask = (1ull << MSR_POW) | 3529 (1ull << MSR_CE) | 3530 (1ull << MSR_EE) | 3531 (1ull << MSR_PR) | 3532 (1ull << MSR_FP) | 3533 (1ull << MSR_ME) | 3534 (1ull << MSR_FE0) | 3535 (1ull << MSR_DWE) | 3536 (1ull << MSR_DE) | 3537 (1ull << MSR_FE1) | 3538 (1ull << MSR_IR) | 3539 (1ull << MSR_DR); 3540 pcc->mmu_model = POWERPC_MMU_BOOKE; 3541 pcc->excp_model = POWERPC_EXCP_BOOKE; 3542 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3543 pcc->bfd_mach = bfd_mach_ppc_403; 3544 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3545 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3546 } 3547 3548 static void init_proc_MPC5xx(CPUPPCState *env) 3549 { 3550 /* Time base */ 3551 register_tbl(env); 3552 register_5xx_8xx_sprs(env); 3553 register_5xx_sprs(env); 3554 init_excp_MPC5xx(env); 3555 env->dcache_line_size = 32; 3556 env->icache_line_size = 32; 3557 /* XXX: TODO: allocate internal IRQ controller */ 3558 } 3559 3560 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 3561 { 3562 DeviceClass *dc = DEVICE_CLASS(oc); 3563 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3564 3565 dc->desc = "Freescale 5xx cores (aka RCPU)"; 3566 pcc->init_proc = init_proc_MPC5xx; 3567 pcc->check_pow = check_pow_none; 3568 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3569 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3570 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 3571 PPC_MFTB; 3572 pcc->msr_mask = (1ull << MSR_ILE) | 3573 (1ull << MSR_EE) | 3574 (1ull << MSR_PR) | 3575 (1ull << MSR_FP) | 3576 (1ull << MSR_ME) | 3577 (1ull << MSR_FE0) | 3578 (1ull << MSR_SE) | 3579 (1ull << MSR_DE) | 3580 (1ull << MSR_FE1) | 3581 (1ull << MSR_EP) | 3582 (1ull << MSR_RI) | 3583 (1ull << MSR_LE); 3584 pcc->mmu_model = POWERPC_MMU_REAL; 3585 pcc->excp_model = POWERPC_EXCP_603; 3586 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3587 pcc->bfd_mach = bfd_mach_ppc_505; 3588 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3589 POWERPC_FLAG_BUS_CLK; 3590 } 3591 3592 static void init_proc_MPC8xx(CPUPPCState *env) 3593 { 3594 /* Time base */ 3595 register_tbl(env); 3596 register_5xx_8xx_sprs(env); 3597 register_8xx_sprs(env); 3598 init_excp_MPC8xx(env); 3599 env->dcache_line_size = 32; 3600 env->icache_line_size = 32; 3601 /* XXX: TODO: allocate internal IRQ controller */ 3602 } 3603 3604 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 3605 { 3606 DeviceClass *dc = DEVICE_CLASS(oc); 3607 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3608 3609 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 3610 pcc->init_proc = init_proc_MPC8xx; 3611 pcc->check_pow = check_pow_none; 3612 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3613 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3614 PPC_CACHE_ICBI | PPC_MFTB; 3615 pcc->msr_mask = (1ull << MSR_ILE) | 3616 (1ull << MSR_EE) | 3617 (1ull << MSR_PR) | 3618 (1ull << MSR_FP) | 3619 (1ull << MSR_ME) | 3620 (1ull << MSR_SE) | 3621 (1ull << MSR_DE) | 3622 (1ull << MSR_EP) | 3623 (1ull << MSR_IR) | 3624 (1ull << MSR_DR) | 3625 (1ull << MSR_RI) | 3626 (1ull << MSR_LE); 3627 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3628 pcc->excp_model = POWERPC_EXCP_603; 3629 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3630 pcc->bfd_mach = bfd_mach_ppc_860; 3631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3632 POWERPC_FLAG_BUS_CLK; 3633 } 3634 3635 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3636 3637 static void init_proc_G2(CPUPPCState *env) 3638 { 3639 register_ne_601_sprs(env); 3640 register_sdr1_sprs(env); 3641 register_G2_755_sprs(env); 3642 register_G2_sprs(env); 3643 /* Time base */ 3644 register_tbl(env); 3645 /* External access control */ 3646 /* XXX : not implemented */ 3647 spr_register(env, SPR_EAR, "EAR", 3648 SPR_NOACCESS, SPR_NOACCESS, 3649 &spr_read_generic, &spr_write_generic, 3650 0x00000000); 3651 /* Hardware implementation register */ 3652 /* XXX : not implemented */ 3653 spr_register(env, SPR_HID0, "HID0", 3654 SPR_NOACCESS, SPR_NOACCESS, 3655 &spr_read_generic, &spr_write_generic, 3656 0x00000000); 3657 /* XXX : not implemented */ 3658 spr_register(env, SPR_HID1, "HID1", 3659 SPR_NOACCESS, SPR_NOACCESS, 3660 &spr_read_generic, &spr_write_generic, 3661 0x00000000); 3662 /* XXX : not implemented */ 3663 spr_register(env, SPR_HID2, "HID2", 3664 SPR_NOACCESS, SPR_NOACCESS, 3665 &spr_read_generic, &spr_write_generic, 3666 0x00000000); 3667 /* Memory management */ 3668 register_low_BATs(env); 3669 register_high_BATs(env); 3670 register_6xx_7xx_soft_tlb(env, 64, 2); 3671 init_excp_G2(env); 3672 env->dcache_line_size = 32; 3673 env->icache_line_size = 32; 3674 /* Allocate hardware IRQ controller */ 3675 ppc6xx_irq_init(env_archcpu(env)); 3676 } 3677 3678 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3679 { 3680 DeviceClass *dc = DEVICE_CLASS(oc); 3681 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3682 3683 dc->desc = "PowerPC G2"; 3684 pcc->init_proc = init_proc_G2; 3685 pcc->check_pow = check_pow_hid0; 3686 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3687 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3688 PPC_FLOAT_STFIWX | 3689 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3690 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3691 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3692 PPC_SEGMENT | PPC_EXTERN; 3693 pcc->msr_mask = (1ull << MSR_POW) | 3694 (1ull << MSR_TGPR) | 3695 (1ull << MSR_EE) | 3696 (1ull << MSR_PR) | 3697 (1ull << MSR_FP) | 3698 (1ull << MSR_ME) | 3699 (1ull << MSR_FE0) | 3700 (1ull << MSR_SE) | 3701 (1ull << MSR_DE) | 3702 (1ull << MSR_FE1) | 3703 (1ull << MSR_AL) | 3704 (1ull << MSR_EP) | 3705 (1ull << MSR_IR) | 3706 (1ull << MSR_DR) | 3707 (1ull << MSR_RI); 3708 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3709 pcc->excp_model = POWERPC_EXCP_G2; 3710 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3711 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3712 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3713 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3714 } 3715 3716 static void init_proc_G2LE(CPUPPCState *env) 3717 { 3718 register_ne_601_sprs(env); 3719 register_sdr1_sprs(env); 3720 register_G2_755_sprs(env); 3721 register_G2_sprs(env); 3722 /* Time base */ 3723 register_tbl(env); 3724 /* External access control */ 3725 /* XXX : not implemented */ 3726 spr_register(env, SPR_EAR, "EAR", 3727 SPR_NOACCESS, SPR_NOACCESS, 3728 &spr_read_generic, &spr_write_generic, 3729 0x00000000); 3730 /* Hardware implementation register */ 3731 /* XXX : not implemented */ 3732 spr_register(env, SPR_HID0, "HID0", 3733 SPR_NOACCESS, SPR_NOACCESS, 3734 &spr_read_generic, &spr_write_generic, 3735 0x00000000); 3736 /* XXX : not implemented */ 3737 spr_register(env, SPR_HID1, "HID1", 3738 SPR_NOACCESS, SPR_NOACCESS, 3739 &spr_read_generic, &spr_write_generic, 3740 0x00000000); 3741 /* XXX : not implemented */ 3742 spr_register(env, SPR_HID2, "HID2", 3743 SPR_NOACCESS, SPR_NOACCESS, 3744 &spr_read_generic, &spr_write_generic, 3745 0x00000000); 3746 3747 /* Memory management */ 3748 register_low_BATs(env); 3749 register_high_BATs(env); 3750 register_6xx_7xx_soft_tlb(env, 64, 2); 3751 init_excp_G2(env); 3752 env->dcache_line_size = 32; 3753 env->icache_line_size = 32; 3754 /* Allocate hardware IRQ controller */ 3755 ppc6xx_irq_init(env_archcpu(env)); 3756 } 3757 3758 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3759 { 3760 DeviceClass *dc = DEVICE_CLASS(oc); 3761 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3762 3763 dc->desc = "PowerPC G2LE"; 3764 pcc->init_proc = init_proc_G2LE; 3765 pcc->check_pow = check_pow_hid0; 3766 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3767 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3768 PPC_FLOAT_STFIWX | 3769 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3770 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3771 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3772 PPC_SEGMENT | PPC_EXTERN; 3773 pcc->msr_mask = (1ull << MSR_POW) | 3774 (1ull << MSR_TGPR) | 3775 (1ull << MSR_ILE) | 3776 (1ull << MSR_EE) | 3777 (1ull << MSR_PR) | 3778 (1ull << MSR_FP) | 3779 (1ull << MSR_ME) | 3780 (1ull << MSR_FE0) | 3781 (1ull << MSR_SE) | 3782 (1ull << MSR_DE) | 3783 (1ull << MSR_FE1) | 3784 (1ull << MSR_AL) | 3785 (1ull << MSR_EP) | 3786 (1ull << MSR_IR) | 3787 (1ull << MSR_DR) | 3788 (1ull << MSR_RI) | 3789 (1ull << MSR_LE); 3790 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3791 pcc->excp_model = POWERPC_EXCP_G2; 3792 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3793 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3794 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3795 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3796 } 3797 3798 static void init_proc_e200(CPUPPCState *env) 3799 { 3800 /* Time base */ 3801 register_tbl(env); 3802 register_BookE_sprs(env, 0x000000070000FFFFULL); 3803 /* XXX : not implemented */ 3804 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3805 &spr_read_spefscr, &spr_write_spefscr, 3806 &spr_read_spefscr, &spr_write_spefscr, 3807 0x00000000); 3808 /* Memory management */ 3809 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3810 /* XXX : not implemented */ 3811 spr_register(env, SPR_HID0, "HID0", 3812 SPR_NOACCESS, SPR_NOACCESS, 3813 &spr_read_generic, &spr_write_generic, 3814 0x00000000); 3815 /* XXX : not implemented */ 3816 spr_register(env, SPR_HID1, "HID1", 3817 SPR_NOACCESS, SPR_NOACCESS, 3818 &spr_read_generic, &spr_write_generic, 3819 0x00000000); 3820 /* XXX : not implemented */ 3821 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3822 SPR_NOACCESS, SPR_NOACCESS, 3823 &spr_read_generic, &spr_write_generic, 3824 0x00000000); 3825 /* XXX : not implemented */ 3826 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3827 SPR_NOACCESS, SPR_NOACCESS, 3828 &spr_read_generic, &spr_write_generic, 3829 0x00000000); 3830 /* XXX : not implemented */ 3831 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3832 SPR_NOACCESS, SPR_NOACCESS, 3833 &spr_read_generic, &spr_write_generic, 3834 0x00000000); 3835 /* XXX : not implemented */ 3836 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3837 SPR_NOACCESS, SPR_NOACCESS, 3838 &spr_read_generic, &spr_write_generic, 3839 0x00000000); 3840 /* XXX : not implemented */ 3841 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3842 SPR_NOACCESS, SPR_NOACCESS, 3843 &spr_read_generic, &spr_write_generic, 3844 0x00000000); 3845 /* XXX : not implemented */ 3846 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3847 &spr_read_generic, SPR_NOACCESS, 3848 &spr_read_generic, SPR_NOACCESS, 3849 0x00000000); 3850 /* XXX : not implemented */ 3851 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3852 SPR_NOACCESS, SPR_NOACCESS, 3853 &spr_read_generic, &spr_write_generic, 3854 0x00000000); 3855 /* XXX : not implemented */ 3856 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3857 SPR_NOACCESS, SPR_NOACCESS, 3858 &spr_read_generic, &spr_write_generic, 3859 0x00000000); 3860 /* XXX : not implemented */ 3861 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3862 SPR_NOACCESS, SPR_NOACCESS, 3863 &spr_read_generic, &spr_write_generic, 3864 0x00000000); 3865 /* XXX : not implemented */ 3866 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3867 SPR_NOACCESS, SPR_NOACCESS, 3868 &spr_read_generic, &spr_write_generic, 3869 0x00000000); 3870 /* XXX : not implemented */ 3871 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3872 SPR_NOACCESS, SPR_NOACCESS, 3873 &spr_read_generic, &spr_write_generic, 3874 0x00000000); 3875 /* XXX : not implemented */ 3876 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3877 SPR_NOACCESS, SPR_NOACCESS, 3878 &spr_read_generic, &spr_write_generic, 3879 0x00000000); 3880 /* XXX : not implemented */ 3881 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3882 SPR_NOACCESS, SPR_NOACCESS, 3883 &spr_read_generic, &spr_write_generic, 3884 0x00000000); /* TOFIX */ 3885 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3886 SPR_NOACCESS, SPR_NOACCESS, 3887 &spr_read_generic, &spr_write_generic, 3888 0x00000000); 3889 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3890 SPR_NOACCESS, SPR_NOACCESS, 3891 &spr_read_generic, &spr_write_generic, 3892 0x00000000); 3893 #if !defined(CONFIG_USER_ONLY) 3894 env->nb_tlb = 64; 3895 env->nb_ways = 1; 3896 env->id_tlbs = 0; 3897 env->tlb_type = TLB_EMB; 3898 #endif 3899 init_excp_e200(env, 0xFFFF0000UL); 3900 env->dcache_line_size = 32; 3901 env->icache_line_size = 32; 3902 /* XXX: TODO: allocate internal IRQ controller */ 3903 } 3904 3905 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3906 { 3907 DeviceClass *dc = DEVICE_CLASS(oc); 3908 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3909 3910 dc->desc = "e200 core"; 3911 pcc->init_proc = init_proc_e200; 3912 pcc->check_pow = check_pow_hid0; 3913 /* 3914 * XXX: unimplemented instructions: 3915 * dcblc 3916 * dcbtlst 3917 * dcbtstls 3918 * icblc 3919 * icbtls 3920 * tlbivax 3921 * all SPE multiply-accumulate instructions 3922 */ 3923 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3924 PPC_SPE | PPC_SPE_SINGLE | 3925 PPC_WRTEE | PPC_RFDI | 3926 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3927 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3928 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3929 PPC_BOOKE; 3930 pcc->msr_mask = (1ull << MSR_UCLE) | 3931 (1ull << MSR_SPE) | 3932 (1ull << MSR_POW) | 3933 (1ull << MSR_CE) | 3934 (1ull << MSR_EE) | 3935 (1ull << MSR_PR) | 3936 (1ull << MSR_FP) | 3937 (1ull << MSR_ME) | 3938 (1ull << MSR_FE0) | 3939 (1ull << MSR_DWE) | 3940 (1ull << MSR_DE) | 3941 (1ull << MSR_FE1) | 3942 (1ull << MSR_IR) | 3943 (1ull << MSR_DR); 3944 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3945 pcc->excp_model = POWERPC_EXCP_BOOKE; 3946 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3947 pcc->bfd_mach = bfd_mach_ppc_860; 3948 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3949 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3950 POWERPC_FLAG_BUS_CLK; 3951 } 3952 3953 static void init_proc_e300(CPUPPCState *env) 3954 { 3955 register_ne_601_sprs(env); 3956 register_sdr1_sprs(env); 3957 register_603_sprs(env); 3958 /* Time base */ 3959 register_tbl(env); 3960 /* hardware implementation registers */ 3961 /* XXX : not implemented */ 3962 spr_register(env, SPR_HID0, "HID0", 3963 SPR_NOACCESS, SPR_NOACCESS, 3964 &spr_read_generic, &spr_write_generic, 3965 0x00000000); 3966 /* XXX : not implemented */ 3967 spr_register(env, SPR_HID1, "HID1", 3968 SPR_NOACCESS, SPR_NOACCESS, 3969 &spr_read_generic, &spr_write_generic, 3970 0x00000000); 3971 /* XXX : not implemented */ 3972 spr_register(env, SPR_HID2, "HID2", 3973 SPR_NOACCESS, SPR_NOACCESS, 3974 &spr_read_generic, &spr_write_generic, 3975 0x00000000); 3976 /* Breakpoints */ 3977 /* XXX : not implemented */ 3978 spr_register(env, SPR_DABR, "DABR", 3979 SPR_NOACCESS, SPR_NOACCESS, 3980 &spr_read_generic, &spr_write_generic, 3981 0x00000000); 3982 /* XXX : not implemented */ 3983 spr_register(env, SPR_DABR2, "DABR2", 3984 SPR_NOACCESS, SPR_NOACCESS, 3985 &spr_read_generic, &spr_write_generic, 3986 0x00000000); 3987 /* XXX : not implemented */ 3988 spr_register(env, SPR_IABR2, "IABR2", 3989 SPR_NOACCESS, SPR_NOACCESS, 3990 &spr_read_generic, &spr_write_generic, 3991 0x00000000); 3992 /* XXX : not implemented */ 3993 spr_register(env, SPR_IBCR, "IBCR", 3994 SPR_NOACCESS, SPR_NOACCESS, 3995 &spr_read_generic, &spr_write_generic, 3996 0x00000000); 3997 /* XXX : not implemented */ 3998 spr_register(env, SPR_DBCR, "DBCR", 3999 SPR_NOACCESS, SPR_NOACCESS, 4000 &spr_read_generic, &spr_write_generic, 4001 0x00000000); 4002 /* Memory management */ 4003 register_low_BATs(env); 4004 register_high_BATs(env); 4005 register_6xx_7xx_soft_tlb(env, 64, 2); 4006 init_excp_603(env); 4007 env->dcache_line_size = 32; 4008 env->icache_line_size = 32; 4009 /* Allocate hardware IRQ controller */ 4010 ppc6xx_irq_init(env_archcpu(env)); 4011 } 4012 4013 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 4014 { 4015 DeviceClass *dc = DEVICE_CLASS(oc); 4016 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4017 4018 dc->desc = "e300 core"; 4019 pcc->init_proc = init_proc_e300; 4020 pcc->check_pow = check_pow_hid0; 4021 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4022 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4023 PPC_FLOAT_STFIWX | 4024 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4025 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4026 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4027 PPC_SEGMENT | PPC_EXTERN; 4028 pcc->msr_mask = (1ull << MSR_POW) | 4029 (1ull << MSR_TGPR) | 4030 (1ull << MSR_ILE) | 4031 (1ull << MSR_EE) | 4032 (1ull << MSR_PR) | 4033 (1ull << MSR_FP) | 4034 (1ull << MSR_ME) | 4035 (1ull << MSR_FE0) | 4036 (1ull << MSR_SE) | 4037 (1ull << MSR_DE) | 4038 (1ull << MSR_FE1) | 4039 (1ull << MSR_AL) | 4040 (1ull << MSR_EP) | 4041 (1ull << MSR_IR) | 4042 (1ull << MSR_DR) | 4043 (1ull << MSR_RI) | 4044 (1ull << MSR_LE); 4045 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4046 pcc->excp_model = POWERPC_EXCP_603; 4047 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4048 pcc->bfd_mach = bfd_mach_ppc_603; 4049 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4050 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4051 } 4052 4053 enum fsl_e500_version { 4054 fsl_e500v1, 4055 fsl_e500v2, 4056 fsl_e500mc, 4057 fsl_e5500, 4058 fsl_e6500, 4059 }; 4060 4061 static void init_proc_e500(CPUPPCState *env, int version) 4062 { 4063 uint32_t tlbncfg[2]; 4064 uint64_t ivor_mask; 4065 uint64_t ivpr_mask = 0xFFFF0000ULL; 4066 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 4067 | 0x0020; /* 32 kb */ 4068 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 4069 | 0x0020; /* 32 kb */ 4070 uint32_t mmucfg = 0; 4071 #if !defined(CONFIG_USER_ONLY) 4072 int i; 4073 #endif 4074 4075 /* Time base */ 4076 register_tbl(env); 4077 /* 4078 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 4079 * complain when accessing them. 4080 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 4081 */ 4082 switch (version) { 4083 case fsl_e500v1: 4084 case fsl_e500v2: 4085 default: 4086 ivor_mask = 0x0000000F0000FFFFULL; 4087 break; 4088 case fsl_e500mc: 4089 case fsl_e5500: 4090 ivor_mask = 0x000003FE0000FFFFULL; 4091 break; 4092 case fsl_e6500: 4093 ivor_mask = 0x000003FF0000FFFFULL; 4094 break; 4095 } 4096 register_BookE_sprs(env, ivor_mask); 4097 register_usprg3_sprs(env); 4098 /* Processor identification */ 4099 spr_register(env, SPR_BOOKE_PIR, "PIR", 4100 SPR_NOACCESS, SPR_NOACCESS, 4101 &spr_read_generic, &spr_write_pir, 4102 0x00000000); 4103 /* XXX : not implemented */ 4104 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4105 &spr_read_spefscr, &spr_write_spefscr, 4106 &spr_read_spefscr, &spr_write_spefscr, 4107 0x00000000); 4108 #if !defined(CONFIG_USER_ONLY) 4109 /* Memory management */ 4110 env->nb_pids = 3; 4111 env->nb_ways = 2; 4112 env->id_tlbs = 0; 4113 switch (version) { 4114 case fsl_e500v1: 4115 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 4116 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4117 break; 4118 case fsl_e500v2: 4119 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4120 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4121 break; 4122 case fsl_e500mc: 4123 case fsl_e5500: 4124 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4125 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 4126 break; 4127 case fsl_e6500: 4128 mmucfg = 0x6510B45; 4129 env->nb_pids = 1; 4130 tlbncfg[0] = 0x08052400; 4131 tlbncfg[1] = 0x40028040; 4132 break; 4133 default: 4134 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4135 env->spr[SPR_PVR]); 4136 } 4137 #endif 4138 /* Cache sizes */ 4139 switch (version) { 4140 case fsl_e500v1: 4141 case fsl_e500v2: 4142 env->dcache_line_size = 32; 4143 env->icache_line_size = 32; 4144 break; 4145 case fsl_e500mc: 4146 case fsl_e5500: 4147 env->dcache_line_size = 64; 4148 env->icache_line_size = 64; 4149 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 4150 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 4151 break; 4152 case fsl_e6500: 4153 env->dcache_line_size = 32; 4154 env->icache_line_size = 32; 4155 l1cfg0 |= 0x0F83820; 4156 l1cfg1 |= 0x0B83820; 4157 break; 4158 default: 4159 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4160 env->spr[SPR_PVR]); 4161 } 4162 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 4163 /* XXX : not implemented */ 4164 spr_register(env, SPR_HID0, "HID0", 4165 SPR_NOACCESS, SPR_NOACCESS, 4166 &spr_read_generic, &spr_write_generic, 4167 0x00000000); 4168 /* XXX : not implemented */ 4169 spr_register(env, SPR_HID1, "HID1", 4170 SPR_NOACCESS, SPR_NOACCESS, 4171 &spr_read_generic, &spr_write_generic, 4172 0x00000000); 4173 /* XXX : not implemented */ 4174 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 4175 SPR_NOACCESS, SPR_NOACCESS, 4176 &spr_read_generic, &spr_write_generic, 4177 0x00000000); 4178 /* XXX : not implemented */ 4179 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 4180 SPR_NOACCESS, SPR_NOACCESS, 4181 &spr_read_generic, &spr_write_generic, 4182 0x00000000); 4183 /* XXX : not implemented */ 4184 spr_register(env, SPR_Exxx_MCAR, "MCAR", 4185 SPR_NOACCESS, SPR_NOACCESS, 4186 &spr_read_generic, &spr_write_generic, 4187 0x00000000); 4188 /* XXX : not implemented */ 4189 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 4190 SPR_NOACCESS, SPR_NOACCESS, 4191 &spr_read_generic, &spr_write_generic, 4192 0x00000000); 4193 /* XXX : not implemented */ 4194 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 4195 SPR_NOACCESS, SPR_NOACCESS, 4196 &spr_read_generic, &spr_write_generic, 4197 0x00000000); 4198 /* XXX : not implemented */ 4199 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 4200 SPR_NOACCESS, SPR_NOACCESS, 4201 &spr_read_generic, &spr_write_generic, 4202 0x00000000); 4203 /* XXX : not implemented */ 4204 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 4205 &spr_read_generic, SPR_NOACCESS, 4206 &spr_read_generic, SPR_NOACCESS, 4207 l1cfg0); 4208 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 4209 &spr_read_generic, SPR_NOACCESS, 4210 &spr_read_generic, SPR_NOACCESS, 4211 l1cfg1); 4212 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 4213 SPR_NOACCESS, SPR_NOACCESS, 4214 &spr_read_generic, &spr_write_e500_l1csr0, 4215 0x00000000); 4216 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 4217 SPR_NOACCESS, SPR_NOACCESS, 4218 &spr_read_generic, &spr_write_e500_l1csr1, 4219 0x00000000); 4220 if (version != fsl_e500v1 && version != fsl_e500v2) { 4221 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 4222 SPR_NOACCESS, SPR_NOACCESS, 4223 &spr_read_generic, &spr_write_e500_l2csr0, 4224 0x00000000); 4225 } 4226 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 4227 SPR_NOACCESS, SPR_NOACCESS, 4228 &spr_read_generic, &spr_write_generic, 4229 0x00000000); 4230 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 4231 SPR_NOACCESS, SPR_NOACCESS, 4232 &spr_read_generic, &spr_write_generic, 4233 0x00000000); 4234 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 4235 SPR_NOACCESS, SPR_NOACCESS, 4236 &spr_read_generic, &spr_write_booke206_mmucsr0, 4237 0x00000000); 4238 spr_register(env, SPR_BOOKE_EPR, "EPR", 4239 SPR_NOACCESS, SPR_NOACCESS, 4240 &spr_read_generic, SPR_NOACCESS, 4241 0x00000000); 4242 /* XXX better abstract into Emb.xxx features */ 4243 if ((version == fsl_e5500) || (version == fsl_e6500)) { 4244 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 4245 SPR_NOACCESS, SPR_NOACCESS, 4246 &spr_read_generic, &spr_write_generic, 4247 0x00000000); 4248 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 4249 SPR_NOACCESS, SPR_NOACCESS, 4250 &spr_read_mas73, &spr_write_mas73, 4251 0x00000000); 4252 ivpr_mask = (target_ulong)~0xFFFFULL; 4253 } 4254 4255 if (version == fsl_e6500) { 4256 /* Thread identification */ 4257 spr_register(env, SPR_TIR, "TIR", 4258 SPR_NOACCESS, SPR_NOACCESS, 4259 &spr_read_generic, SPR_NOACCESS, 4260 0x00000000); 4261 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 4262 SPR_NOACCESS, SPR_NOACCESS, 4263 &spr_read_generic, SPR_NOACCESS, 4264 0x00000004); 4265 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 4266 SPR_NOACCESS, SPR_NOACCESS, 4267 &spr_read_generic, SPR_NOACCESS, 4268 0x7FFFFFFC); 4269 } 4270 4271 #if !defined(CONFIG_USER_ONLY) 4272 env->nb_tlb = 0; 4273 env->tlb_type = TLB_MAS; 4274 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 4275 env->nb_tlb += booke206_tlb_size(env, i); 4276 } 4277 #endif 4278 4279 init_excp_e200(env, ivpr_mask); 4280 /* Allocate hardware IRQ controller */ 4281 ppce500_irq_init(env_archcpu(env)); 4282 } 4283 4284 static void init_proc_e500v1(CPUPPCState *env) 4285 { 4286 init_proc_e500(env, fsl_e500v1); 4287 } 4288 4289 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 4290 { 4291 DeviceClass *dc = DEVICE_CLASS(oc); 4292 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4293 4294 dc->desc = "e500v1 core"; 4295 pcc->init_proc = init_proc_e500v1; 4296 pcc->check_pow = check_pow_hid0; 4297 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4298 PPC_SPE | PPC_SPE_SINGLE | 4299 PPC_WRTEE | PPC_RFDI | 4300 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4301 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4302 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4303 pcc->insns_flags2 = PPC2_BOOKE206; 4304 pcc->msr_mask = (1ull << MSR_UCLE) | 4305 (1ull << MSR_SPE) | 4306 (1ull << MSR_POW) | 4307 (1ull << MSR_CE) | 4308 (1ull << MSR_EE) | 4309 (1ull << MSR_PR) | 4310 (1ull << MSR_FP) | 4311 (1ull << MSR_ME) | 4312 (1ull << MSR_FE0) | 4313 (1ull << MSR_DWE) | 4314 (1ull << MSR_DE) | 4315 (1ull << MSR_FE1) | 4316 (1ull << MSR_IR) | 4317 (1ull << MSR_DR); 4318 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4319 pcc->excp_model = POWERPC_EXCP_BOOKE; 4320 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4321 pcc->bfd_mach = bfd_mach_ppc_860; 4322 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4323 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4324 POWERPC_FLAG_BUS_CLK; 4325 } 4326 4327 static void init_proc_e500v2(CPUPPCState *env) 4328 { 4329 init_proc_e500(env, fsl_e500v2); 4330 } 4331 4332 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 4333 { 4334 DeviceClass *dc = DEVICE_CLASS(oc); 4335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4336 4337 dc->desc = "e500v2 core"; 4338 pcc->init_proc = init_proc_e500v2; 4339 pcc->check_pow = check_pow_hid0; 4340 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4341 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 4342 PPC_WRTEE | PPC_RFDI | 4343 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4344 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4345 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4346 pcc->insns_flags2 = PPC2_BOOKE206; 4347 pcc->msr_mask = (1ull << MSR_UCLE) | 4348 (1ull << MSR_SPE) | 4349 (1ull << MSR_POW) | 4350 (1ull << MSR_CE) | 4351 (1ull << MSR_EE) | 4352 (1ull << MSR_PR) | 4353 (1ull << MSR_FP) | 4354 (1ull << MSR_ME) | 4355 (1ull << MSR_FE0) | 4356 (1ull << MSR_DWE) | 4357 (1ull << MSR_DE) | 4358 (1ull << MSR_FE1) | 4359 (1ull << MSR_IR) | 4360 (1ull << MSR_DR); 4361 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4362 pcc->excp_model = POWERPC_EXCP_BOOKE; 4363 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4364 pcc->bfd_mach = bfd_mach_ppc_860; 4365 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4366 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4367 POWERPC_FLAG_BUS_CLK; 4368 } 4369 4370 static void init_proc_e500mc(CPUPPCState *env) 4371 { 4372 init_proc_e500(env, fsl_e500mc); 4373 } 4374 4375 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 4376 { 4377 DeviceClass *dc = DEVICE_CLASS(oc); 4378 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4379 4380 dc->desc = "e500mc core"; 4381 pcc->init_proc = init_proc_e500mc; 4382 pcc->check_pow = check_pow_none; 4383 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4384 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4385 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4386 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4387 PPC_FLOAT | PPC_FLOAT_FRES | 4388 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4389 PPC_FLOAT_STFIWX | PPC_WAIT | 4390 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4391 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 4392 pcc->msr_mask = (1ull << MSR_GS) | 4393 (1ull << MSR_UCLE) | 4394 (1ull << MSR_CE) | 4395 (1ull << MSR_EE) | 4396 (1ull << MSR_PR) | 4397 (1ull << MSR_FP) | 4398 (1ull << MSR_ME) | 4399 (1ull << MSR_FE0) | 4400 (1ull << MSR_DE) | 4401 (1ull << MSR_FE1) | 4402 (1ull << MSR_IR) | 4403 (1ull << MSR_DR) | 4404 (1ull << MSR_PX) | 4405 (1ull << MSR_RI); 4406 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4407 pcc->excp_model = POWERPC_EXCP_BOOKE; 4408 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4409 /* FIXME: figure out the correct flag for e500mc */ 4410 pcc->bfd_mach = bfd_mach_ppc_e500; 4411 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4412 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4413 } 4414 4415 #ifdef TARGET_PPC64 4416 static void init_proc_e5500(CPUPPCState *env) 4417 { 4418 init_proc_e500(env, fsl_e5500); 4419 } 4420 4421 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 4422 { 4423 DeviceClass *dc = DEVICE_CLASS(oc); 4424 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4425 4426 dc->desc = "e5500 core"; 4427 pcc->init_proc = init_proc_e5500; 4428 pcc->check_pow = check_pow_none; 4429 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4430 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4431 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4432 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4433 PPC_FLOAT | PPC_FLOAT_FRES | 4434 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4435 PPC_FLOAT_STFIWX | PPC_WAIT | 4436 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4437 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 4438 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4439 PPC2_FP_CVT_S64; 4440 pcc->msr_mask = (1ull << MSR_CM) | 4441 (1ull << MSR_GS) | 4442 (1ull << MSR_UCLE) | 4443 (1ull << MSR_CE) | 4444 (1ull << MSR_EE) | 4445 (1ull << MSR_PR) | 4446 (1ull << MSR_FP) | 4447 (1ull << MSR_ME) | 4448 (1ull << MSR_FE0) | 4449 (1ull << MSR_DE) | 4450 (1ull << MSR_FE1) | 4451 (1ull << MSR_IR) | 4452 (1ull << MSR_DR) | 4453 (1ull << MSR_PX) | 4454 (1ull << MSR_RI); 4455 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4456 pcc->excp_model = POWERPC_EXCP_BOOKE; 4457 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4458 /* FIXME: figure out the correct flag for e5500 */ 4459 pcc->bfd_mach = bfd_mach_ppc_e500; 4460 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4461 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4462 } 4463 4464 static void init_proc_e6500(CPUPPCState *env) 4465 { 4466 init_proc_e500(env, fsl_e6500); 4467 } 4468 4469 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 4470 { 4471 DeviceClass *dc = DEVICE_CLASS(oc); 4472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4473 4474 dc->desc = "e6500 core"; 4475 pcc->init_proc = init_proc_e6500; 4476 pcc->check_pow = check_pow_none; 4477 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4478 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4479 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4480 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4481 PPC_FLOAT | PPC_FLOAT_FRES | 4482 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4483 PPC_FLOAT_STFIWX | PPC_WAIT | 4484 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4485 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 4486 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4487 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 4488 pcc->msr_mask = (1ull << MSR_CM) | 4489 (1ull << MSR_GS) | 4490 (1ull << MSR_UCLE) | 4491 (1ull << MSR_CE) | 4492 (1ull << MSR_EE) | 4493 (1ull << MSR_PR) | 4494 (1ull << MSR_FP) | 4495 (1ull << MSR_ME) | 4496 (1ull << MSR_FE0) | 4497 (1ull << MSR_DE) | 4498 (1ull << MSR_FE1) | 4499 (1ull << MSR_IS) | 4500 (1ull << MSR_DS) | 4501 (1ull << MSR_PX) | 4502 (1ull << MSR_RI) | 4503 (1ull << MSR_VR); 4504 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4505 pcc->excp_model = POWERPC_EXCP_BOOKE; 4506 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4507 pcc->bfd_mach = bfd_mach_ppc_e500; 4508 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4509 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 4510 } 4511 4512 #endif 4513 4514 /* Non-embedded PowerPC */ 4515 4516 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 4517 4518 static void init_proc_601(CPUPPCState *env) 4519 { 4520 register_ne_601_sprs(env); 4521 register_sdr1_sprs(env); 4522 register_601_sprs(env); 4523 /* Hardware implementation registers */ 4524 /* XXX : not implemented */ 4525 spr_register(env, SPR_HID0, "HID0", 4526 SPR_NOACCESS, SPR_NOACCESS, 4527 &spr_read_generic, &spr_write_hid0_601, 4528 0x80010080); 4529 /* XXX : not implemented */ 4530 spr_register(env, SPR_HID1, "HID1", 4531 SPR_NOACCESS, SPR_NOACCESS, 4532 &spr_read_generic, &spr_write_generic, 4533 0x00000000); 4534 /* XXX : not implemented */ 4535 spr_register(env, SPR_601_HID2, "HID2", 4536 SPR_NOACCESS, SPR_NOACCESS, 4537 &spr_read_generic, &spr_write_generic, 4538 0x00000000); 4539 /* XXX : not implemented */ 4540 spr_register(env, SPR_601_HID5, "HID5", 4541 SPR_NOACCESS, SPR_NOACCESS, 4542 &spr_read_generic, &spr_write_generic, 4543 0x00000000); 4544 /* Memory management */ 4545 init_excp_601(env); 4546 /* 4547 * XXX: beware that dcache line size is 64 4548 * but dcbz uses 32 bytes "sectors" 4549 * XXX: this breaks clcs instruction ! 4550 */ 4551 env->dcache_line_size = 32; 4552 env->icache_line_size = 64; 4553 /* Allocate hardware IRQ controller */ 4554 ppc6xx_irq_init(env_archcpu(env)); 4555 } 4556 4557 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 4558 { 4559 DeviceClass *dc = DEVICE_CLASS(oc); 4560 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4561 4562 dc->desc = "PowerPC 601"; 4563 pcc->init_proc = init_proc_601; 4564 pcc->check_pow = check_pow_none; 4565 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4566 PPC_FLOAT | 4567 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4568 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4569 PPC_SEGMENT | PPC_EXTERN; 4570 pcc->msr_mask = (1ull << MSR_EE) | 4571 (1ull << MSR_PR) | 4572 (1ull << MSR_FP) | 4573 (1ull << MSR_ME) | 4574 (1ull << MSR_FE0) | 4575 (1ull << MSR_SE) | 4576 (1ull << MSR_FE1) | 4577 (1ull << MSR_EP) | 4578 (1ull << MSR_IR) | 4579 (1ull << MSR_DR); 4580 pcc->mmu_model = POWERPC_MMU_601; 4581 #if defined(CONFIG_SOFTMMU) 4582 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4583 #endif 4584 pcc->excp_model = POWERPC_EXCP_601; 4585 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4586 pcc->bfd_mach = bfd_mach_ppc_601; 4587 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4588 } 4589 4590 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 4591 4592 static void init_proc_601v(CPUPPCState *env) 4593 { 4594 init_proc_601(env); 4595 /* XXX : not implemented */ 4596 spr_register(env, SPR_601_HID15, "HID15", 4597 SPR_NOACCESS, SPR_NOACCESS, 4598 &spr_read_generic, &spr_write_generic, 4599 0x00000000); 4600 } 4601 4602 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 4603 { 4604 DeviceClass *dc = DEVICE_CLASS(oc); 4605 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4606 4607 dc->desc = "PowerPC 601v"; 4608 pcc->init_proc = init_proc_601v; 4609 pcc->check_pow = check_pow_none; 4610 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4611 PPC_FLOAT | 4612 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4613 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4614 PPC_SEGMENT | PPC_EXTERN; 4615 pcc->msr_mask = (1ull << MSR_EE) | 4616 (1ull << MSR_PR) | 4617 (1ull << MSR_FP) | 4618 (1ull << MSR_ME) | 4619 (1ull << MSR_FE0) | 4620 (1ull << MSR_SE) | 4621 (1ull << MSR_FE1) | 4622 (1ull << MSR_EP) | 4623 (1ull << MSR_IR) | 4624 (1ull << MSR_DR); 4625 pcc->mmu_model = POWERPC_MMU_601; 4626 #if defined(CONFIG_SOFTMMU) 4627 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4628 #endif 4629 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4630 pcc->bfd_mach = bfd_mach_ppc_601; 4631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4632 } 4633 4634 static void init_proc_602(CPUPPCState *env) 4635 { 4636 register_ne_601_sprs(env); 4637 register_sdr1_sprs(env); 4638 register_602_sprs(env); 4639 /* Time base */ 4640 register_tbl(env); 4641 /* hardware implementation registers */ 4642 /* XXX : not implemented */ 4643 spr_register(env, SPR_HID0, "HID0", 4644 SPR_NOACCESS, SPR_NOACCESS, 4645 &spr_read_generic, &spr_write_generic, 4646 0x00000000); 4647 /* XXX : not implemented */ 4648 spr_register(env, SPR_HID1, "HID1", 4649 SPR_NOACCESS, SPR_NOACCESS, 4650 &spr_read_generic, &spr_write_generic, 4651 0x00000000); 4652 /* Memory management */ 4653 register_low_BATs(env); 4654 register_6xx_7xx_soft_tlb(env, 64, 2); 4655 init_excp_602(env); 4656 env->dcache_line_size = 32; 4657 env->icache_line_size = 32; 4658 /* Allocate hardware IRQ controller */ 4659 ppc6xx_irq_init(env_archcpu(env)); 4660 } 4661 4662 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 4663 { 4664 DeviceClass *dc = DEVICE_CLASS(oc); 4665 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4666 4667 dc->desc = "PowerPC 602"; 4668 pcc->init_proc = init_proc_602; 4669 pcc->check_pow = check_pow_hid0; 4670 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4671 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4672 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4673 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4674 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4675 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 4676 PPC_SEGMENT | PPC_602_SPEC; 4677 pcc->msr_mask = (1ull << MSR_VSX) | 4678 (1ull << MSR_SA) | 4679 (1ull << MSR_POW) | 4680 (1ull << MSR_TGPR) | 4681 (1ull << MSR_ILE) | 4682 (1ull << MSR_EE) | 4683 (1ull << MSR_PR) | 4684 (1ull << MSR_FP) | 4685 (1ull << MSR_ME) | 4686 (1ull << MSR_FE0) | 4687 (1ull << MSR_SE) | 4688 (1ull << MSR_DE) | 4689 (1ull << MSR_FE1) | 4690 (1ull << MSR_EP) | 4691 (1ull << MSR_IR) | 4692 (1ull << MSR_DR) | 4693 (1ull << MSR_RI) | 4694 (1ull << MSR_LE); 4695 /* XXX: 602 MMU is quite specific. Should add a special case */ 4696 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4697 pcc->excp_model = POWERPC_EXCP_602; 4698 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4699 pcc->bfd_mach = bfd_mach_ppc_602; 4700 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4701 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4702 } 4703 4704 static void init_proc_603(CPUPPCState *env) 4705 { 4706 register_ne_601_sprs(env); 4707 register_sdr1_sprs(env); 4708 register_603_sprs(env); 4709 /* Time base */ 4710 register_tbl(env); 4711 /* hardware implementation registers */ 4712 /* XXX : not implemented */ 4713 spr_register(env, SPR_HID0, "HID0", 4714 SPR_NOACCESS, SPR_NOACCESS, 4715 &spr_read_generic, &spr_write_generic, 4716 0x00000000); 4717 /* XXX : not implemented */ 4718 spr_register(env, SPR_HID1, "HID1", 4719 SPR_NOACCESS, SPR_NOACCESS, 4720 &spr_read_generic, &spr_write_generic, 4721 0x00000000); 4722 /* Memory management */ 4723 register_low_BATs(env); 4724 register_6xx_7xx_soft_tlb(env, 64, 2); 4725 init_excp_603(env); 4726 env->dcache_line_size = 32; 4727 env->icache_line_size = 32; 4728 /* Allocate hardware IRQ controller */ 4729 ppc6xx_irq_init(env_archcpu(env)); 4730 } 4731 4732 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4733 { 4734 DeviceClass *dc = DEVICE_CLASS(oc); 4735 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4736 4737 dc->desc = "PowerPC 603"; 4738 pcc->init_proc = init_proc_603; 4739 pcc->check_pow = check_pow_hid0; 4740 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4741 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4742 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4743 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4744 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4745 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4746 PPC_SEGMENT | PPC_EXTERN; 4747 pcc->msr_mask = (1ull << MSR_POW) | 4748 (1ull << MSR_TGPR) | 4749 (1ull << MSR_ILE) | 4750 (1ull << MSR_EE) | 4751 (1ull << MSR_PR) | 4752 (1ull << MSR_FP) | 4753 (1ull << MSR_ME) | 4754 (1ull << MSR_FE0) | 4755 (1ull << MSR_SE) | 4756 (1ull << MSR_DE) | 4757 (1ull << MSR_FE1) | 4758 (1ull << MSR_EP) | 4759 (1ull << MSR_IR) | 4760 (1ull << MSR_DR) | 4761 (1ull << MSR_RI) | 4762 (1ull << MSR_LE); 4763 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4764 pcc->excp_model = POWERPC_EXCP_603; 4765 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4766 pcc->bfd_mach = bfd_mach_ppc_603; 4767 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4768 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4769 } 4770 4771 static void init_proc_603E(CPUPPCState *env) 4772 { 4773 register_ne_601_sprs(env); 4774 register_sdr1_sprs(env); 4775 register_603_sprs(env); 4776 /* Time base */ 4777 register_tbl(env); 4778 /* hardware implementation registers */ 4779 /* XXX : not implemented */ 4780 spr_register(env, SPR_HID0, "HID0", 4781 SPR_NOACCESS, SPR_NOACCESS, 4782 &spr_read_generic, &spr_write_generic, 4783 0x00000000); 4784 /* XXX : not implemented */ 4785 spr_register(env, SPR_HID1, "HID1", 4786 SPR_NOACCESS, SPR_NOACCESS, 4787 &spr_read_generic, &spr_write_generic, 4788 0x00000000); 4789 /* Memory management */ 4790 register_low_BATs(env); 4791 register_6xx_7xx_soft_tlb(env, 64, 2); 4792 init_excp_603(env); 4793 env->dcache_line_size = 32; 4794 env->icache_line_size = 32; 4795 /* Allocate hardware IRQ controller */ 4796 ppc6xx_irq_init(env_archcpu(env)); 4797 } 4798 4799 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4800 { 4801 DeviceClass *dc = DEVICE_CLASS(oc); 4802 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4803 4804 dc->desc = "PowerPC 603e"; 4805 pcc->init_proc = init_proc_603E; 4806 pcc->check_pow = check_pow_hid0; 4807 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4808 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4809 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4810 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4811 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4812 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4813 PPC_SEGMENT | PPC_EXTERN; 4814 pcc->msr_mask = (1ull << MSR_POW) | 4815 (1ull << MSR_TGPR) | 4816 (1ull << MSR_ILE) | 4817 (1ull << MSR_EE) | 4818 (1ull << MSR_PR) | 4819 (1ull << MSR_FP) | 4820 (1ull << MSR_ME) | 4821 (1ull << MSR_FE0) | 4822 (1ull << MSR_SE) | 4823 (1ull << MSR_DE) | 4824 (1ull << MSR_FE1) | 4825 (1ull << MSR_EP) | 4826 (1ull << MSR_IR) | 4827 (1ull << MSR_DR) | 4828 (1ull << MSR_RI) | 4829 (1ull << MSR_LE); 4830 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4831 pcc->excp_model = POWERPC_EXCP_603E; 4832 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4833 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4834 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4835 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4836 } 4837 4838 static void init_proc_604(CPUPPCState *env) 4839 { 4840 register_ne_601_sprs(env); 4841 register_sdr1_sprs(env); 4842 register_604_sprs(env); 4843 /* Time base */ 4844 register_tbl(env); 4845 /* Hardware implementation registers */ 4846 /* XXX : not implemented */ 4847 spr_register(env, SPR_HID0, "HID0", 4848 SPR_NOACCESS, SPR_NOACCESS, 4849 &spr_read_generic, &spr_write_generic, 4850 0x00000000); 4851 /* Memory management */ 4852 register_low_BATs(env); 4853 init_excp_604(env); 4854 env->dcache_line_size = 32; 4855 env->icache_line_size = 32; 4856 /* Allocate hardware IRQ controller */ 4857 ppc6xx_irq_init(env_archcpu(env)); 4858 } 4859 4860 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4861 { 4862 DeviceClass *dc = DEVICE_CLASS(oc); 4863 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4864 4865 dc->desc = "PowerPC 604"; 4866 pcc->init_proc = init_proc_604; 4867 pcc->check_pow = check_pow_nocheck; 4868 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4869 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4870 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4871 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4872 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4873 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4874 PPC_SEGMENT | PPC_EXTERN; 4875 pcc->msr_mask = (1ull << MSR_POW) | 4876 (1ull << MSR_ILE) | 4877 (1ull << MSR_EE) | 4878 (1ull << MSR_PR) | 4879 (1ull << MSR_FP) | 4880 (1ull << MSR_ME) | 4881 (1ull << MSR_FE0) | 4882 (1ull << MSR_SE) | 4883 (1ull << MSR_DE) | 4884 (1ull << MSR_FE1) | 4885 (1ull << MSR_EP) | 4886 (1ull << MSR_IR) | 4887 (1ull << MSR_DR) | 4888 (1ull << MSR_PMM) | 4889 (1ull << MSR_RI) | 4890 (1ull << MSR_LE); 4891 pcc->mmu_model = POWERPC_MMU_32B; 4892 #if defined(CONFIG_SOFTMMU) 4893 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4894 #endif 4895 pcc->excp_model = POWERPC_EXCP_604; 4896 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4897 pcc->bfd_mach = bfd_mach_ppc_604; 4898 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4899 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4900 } 4901 4902 static void init_proc_604E(CPUPPCState *env) 4903 { 4904 register_ne_601_sprs(env); 4905 register_sdr1_sprs(env); 4906 register_604_sprs(env); 4907 /* XXX : not implemented */ 4908 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4909 SPR_NOACCESS, SPR_NOACCESS, 4910 &spr_read_generic, &spr_write_generic, 4911 0x00000000); 4912 /* XXX : not implemented */ 4913 spr_register(env, SPR_7XX_PMC3, "PMC3", 4914 SPR_NOACCESS, SPR_NOACCESS, 4915 &spr_read_generic, &spr_write_generic, 4916 0x00000000); 4917 /* XXX : not implemented */ 4918 spr_register(env, SPR_7XX_PMC4, "PMC4", 4919 SPR_NOACCESS, SPR_NOACCESS, 4920 &spr_read_generic, &spr_write_generic, 4921 0x00000000); 4922 /* Time base */ 4923 register_tbl(env); 4924 /* Hardware implementation registers */ 4925 /* XXX : not implemented */ 4926 spr_register(env, SPR_HID0, "HID0", 4927 SPR_NOACCESS, SPR_NOACCESS, 4928 &spr_read_generic, &spr_write_generic, 4929 0x00000000); 4930 /* XXX : not implemented */ 4931 spr_register(env, SPR_HID1, "HID1", 4932 SPR_NOACCESS, SPR_NOACCESS, 4933 &spr_read_generic, &spr_write_generic, 4934 0x00000000); 4935 /* Memory management */ 4936 register_low_BATs(env); 4937 init_excp_604(env); 4938 env->dcache_line_size = 32; 4939 env->icache_line_size = 32; 4940 /* Allocate hardware IRQ controller */ 4941 ppc6xx_irq_init(env_archcpu(env)); 4942 } 4943 4944 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4945 { 4946 DeviceClass *dc = DEVICE_CLASS(oc); 4947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4948 4949 dc->desc = "PowerPC 604E"; 4950 pcc->init_proc = init_proc_604E; 4951 pcc->check_pow = check_pow_nocheck; 4952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4954 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4955 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4956 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4957 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4958 PPC_SEGMENT | PPC_EXTERN; 4959 pcc->msr_mask = (1ull << MSR_POW) | 4960 (1ull << MSR_ILE) | 4961 (1ull << MSR_EE) | 4962 (1ull << MSR_PR) | 4963 (1ull << MSR_FP) | 4964 (1ull << MSR_ME) | 4965 (1ull << MSR_FE0) | 4966 (1ull << MSR_SE) | 4967 (1ull << MSR_DE) | 4968 (1ull << MSR_FE1) | 4969 (1ull << MSR_EP) | 4970 (1ull << MSR_IR) | 4971 (1ull << MSR_DR) | 4972 (1ull << MSR_PMM) | 4973 (1ull << MSR_RI) | 4974 (1ull << MSR_LE); 4975 pcc->mmu_model = POWERPC_MMU_32B; 4976 #if defined(CONFIG_SOFTMMU) 4977 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4978 #endif 4979 pcc->excp_model = POWERPC_EXCP_604; 4980 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4981 pcc->bfd_mach = bfd_mach_ppc_604; 4982 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4983 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4984 } 4985 4986 static void init_proc_740(CPUPPCState *env) 4987 { 4988 register_ne_601_sprs(env); 4989 register_sdr1_sprs(env); 4990 register_7xx_sprs(env); 4991 /* Time base */ 4992 register_tbl(env); 4993 /* Thermal management */ 4994 register_thrm_sprs(env); 4995 /* Hardware implementation registers */ 4996 /* XXX : not implemented */ 4997 spr_register(env, SPR_HID0, "HID0", 4998 SPR_NOACCESS, SPR_NOACCESS, 4999 &spr_read_generic, &spr_write_generic, 5000 0x00000000); 5001 /* XXX : not implemented */ 5002 spr_register(env, SPR_HID1, "HID1", 5003 SPR_NOACCESS, SPR_NOACCESS, 5004 &spr_read_generic, &spr_write_generic, 5005 0x00000000); 5006 /* Memory management */ 5007 register_low_BATs(env); 5008 init_excp_7x0(env); 5009 env->dcache_line_size = 32; 5010 env->icache_line_size = 32; 5011 /* Allocate hardware IRQ controller */ 5012 ppc6xx_irq_init(env_archcpu(env)); 5013 } 5014 5015 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 5016 { 5017 DeviceClass *dc = DEVICE_CLASS(oc); 5018 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5019 5020 dc->desc = "PowerPC 740"; 5021 pcc->init_proc = init_proc_740; 5022 pcc->check_pow = check_pow_hid0; 5023 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5025 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5027 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5029 PPC_SEGMENT | PPC_EXTERN; 5030 pcc->msr_mask = (1ull << MSR_POW) | 5031 (1ull << MSR_ILE) | 5032 (1ull << MSR_EE) | 5033 (1ull << MSR_PR) | 5034 (1ull << MSR_FP) | 5035 (1ull << MSR_ME) | 5036 (1ull << MSR_FE0) | 5037 (1ull << MSR_SE) | 5038 (1ull << MSR_DE) | 5039 (1ull << MSR_FE1) | 5040 (1ull << MSR_EP) | 5041 (1ull << MSR_IR) | 5042 (1ull << MSR_DR) | 5043 (1ull << MSR_PMM) | 5044 (1ull << MSR_RI) | 5045 (1ull << MSR_LE); 5046 pcc->mmu_model = POWERPC_MMU_32B; 5047 #if defined(CONFIG_SOFTMMU) 5048 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5049 #endif 5050 pcc->excp_model = POWERPC_EXCP_7x0; 5051 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5052 pcc->bfd_mach = bfd_mach_ppc_750; 5053 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5054 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5055 } 5056 5057 static void init_proc_750(CPUPPCState *env) 5058 { 5059 register_ne_601_sprs(env); 5060 register_sdr1_sprs(env); 5061 register_7xx_sprs(env); 5062 /* XXX : not implemented */ 5063 spr_register(env, SPR_L2CR, "L2CR", 5064 SPR_NOACCESS, SPR_NOACCESS, 5065 &spr_read_generic, spr_access_nop, 5066 0x00000000); 5067 /* Time base */ 5068 register_tbl(env); 5069 /* Thermal management */ 5070 register_thrm_sprs(env); 5071 /* Hardware implementation registers */ 5072 /* XXX : not implemented */ 5073 spr_register(env, SPR_HID0, "HID0", 5074 SPR_NOACCESS, SPR_NOACCESS, 5075 &spr_read_generic, &spr_write_generic, 5076 0x00000000); 5077 /* XXX : not implemented */ 5078 spr_register(env, SPR_HID1, "HID1", 5079 SPR_NOACCESS, SPR_NOACCESS, 5080 &spr_read_generic, &spr_write_generic, 5081 0x00000000); 5082 /* Memory management */ 5083 register_low_BATs(env); 5084 /* 5085 * XXX: high BATs are also present but are known to be bugged on 5086 * die version 1.x 5087 */ 5088 init_excp_7x0(env); 5089 env->dcache_line_size = 32; 5090 env->icache_line_size = 32; 5091 /* Allocate hardware IRQ controller */ 5092 ppc6xx_irq_init(env_archcpu(env)); 5093 } 5094 5095 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 5096 { 5097 DeviceClass *dc = DEVICE_CLASS(oc); 5098 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5099 5100 dc->desc = "PowerPC 750"; 5101 pcc->init_proc = init_proc_750; 5102 pcc->check_pow = check_pow_hid0; 5103 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5104 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5105 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5106 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5107 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5108 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5109 PPC_SEGMENT | PPC_EXTERN; 5110 pcc->msr_mask = (1ull << MSR_POW) | 5111 (1ull << MSR_ILE) | 5112 (1ull << MSR_EE) | 5113 (1ull << MSR_PR) | 5114 (1ull << MSR_FP) | 5115 (1ull << MSR_ME) | 5116 (1ull << MSR_FE0) | 5117 (1ull << MSR_SE) | 5118 (1ull << MSR_DE) | 5119 (1ull << MSR_FE1) | 5120 (1ull << MSR_EP) | 5121 (1ull << MSR_IR) | 5122 (1ull << MSR_DR) | 5123 (1ull << MSR_PMM) | 5124 (1ull << MSR_RI) | 5125 (1ull << MSR_LE); 5126 pcc->mmu_model = POWERPC_MMU_32B; 5127 #if defined(CONFIG_SOFTMMU) 5128 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5129 #endif 5130 pcc->excp_model = POWERPC_EXCP_7x0; 5131 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5132 pcc->bfd_mach = bfd_mach_ppc_750; 5133 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5134 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5135 } 5136 5137 static void init_proc_750cl(CPUPPCState *env) 5138 { 5139 register_ne_601_sprs(env); 5140 register_sdr1_sprs(env); 5141 register_7xx_sprs(env); 5142 /* XXX : not implemented */ 5143 spr_register(env, SPR_L2CR, "L2CR", 5144 SPR_NOACCESS, SPR_NOACCESS, 5145 &spr_read_generic, spr_access_nop, 5146 0x00000000); 5147 /* Time base */ 5148 register_tbl(env); 5149 /* Thermal management */ 5150 /* Those registers are fake on 750CL */ 5151 spr_register(env, SPR_THRM1, "THRM1", 5152 SPR_NOACCESS, SPR_NOACCESS, 5153 &spr_read_generic, &spr_write_generic, 5154 0x00000000); 5155 spr_register(env, SPR_THRM2, "THRM2", 5156 SPR_NOACCESS, SPR_NOACCESS, 5157 &spr_read_generic, &spr_write_generic, 5158 0x00000000); 5159 spr_register(env, SPR_THRM3, "THRM3", 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_generic, 5162 0x00000000); 5163 /* XXX: not implemented */ 5164 spr_register(env, SPR_750_TDCL, "TDCL", 5165 SPR_NOACCESS, SPR_NOACCESS, 5166 &spr_read_generic, &spr_write_generic, 5167 0x00000000); 5168 spr_register(env, SPR_750_TDCH, "TDCH", 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_generic, &spr_write_generic, 5171 0x00000000); 5172 /* DMA */ 5173 /* XXX : not implemented */ 5174 spr_register(env, SPR_750_WPAR, "WPAR", 5175 SPR_NOACCESS, SPR_NOACCESS, 5176 &spr_read_generic, &spr_write_generic, 5177 0x00000000); 5178 spr_register(env, SPR_750_DMAL, "DMAL", 5179 SPR_NOACCESS, SPR_NOACCESS, 5180 &spr_read_generic, &spr_write_generic, 5181 0x00000000); 5182 spr_register(env, SPR_750_DMAU, "DMAU", 5183 SPR_NOACCESS, SPR_NOACCESS, 5184 &spr_read_generic, &spr_write_generic, 5185 0x00000000); 5186 /* Hardware implementation registers */ 5187 /* XXX : not implemented */ 5188 spr_register(env, SPR_HID0, "HID0", 5189 SPR_NOACCESS, SPR_NOACCESS, 5190 &spr_read_generic, &spr_write_generic, 5191 0x00000000); 5192 /* XXX : not implemented */ 5193 spr_register(env, SPR_HID1, "HID1", 5194 SPR_NOACCESS, SPR_NOACCESS, 5195 &spr_read_generic, &spr_write_generic, 5196 0x00000000); 5197 /* XXX : not implemented */ 5198 spr_register(env, SPR_750CL_HID2, "HID2", 5199 SPR_NOACCESS, SPR_NOACCESS, 5200 &spr_read_generic, &spr_write_generic, 5201 0x00000000); 5202 /* XXX : not implemented */ 5203 spr_register(env, SPR_750CL_HID4, "HID4", 5204 SPR_NOACCESS, SPR_NOACCESS, 5205 &spr_read_generic, &spr_write_generic, 5206 0x00000000); 5207 /* Quantization registers */ 5208 /* XXX : not implemented */ 5209 spr_register(env, SPR_750_GQR0, "GQR0", 5210 SPR_NOACCESS, SPR_NOACCESS, 5211 &spr_read_generic, &spr_write_generic, 5212 0x00000000); 5213 /* XXX : not implemented */ 5214 spr_register(env, SPR_750_GQR1, "GQR1", 5215 SPR_NOACCESS, SPR_NOACCESS, 5216 &spr_read_generic, &spr_write_generic, 5217 0x00000000); 5218 /* XXX : not implemented */ 5219 spr_register(env, SPR_750_GQR2, "GQR2", 5220 SPR_NOACCESS, SPR_NOACCESS, 5221 &spr_read_generic, &spr_write_generic, 5222 0x00000000); 5223 /* XXX : not implemented */ 5224 spr_register(env, SPR_750_GQR3, "GQR3", 5225 SPR_NOACCESS, SPR_NOACCESS, 5226 &spr_read_generic, &spr_write_generic, 5227 0x00000000); 5228 /* XXX : not implemented */ 5229 spr_register(env, SPR_750_GQR4, "GQR4", 5230 SPR_NOACCESS, SPR_NOACCESS, 5231 &spr_read_generic, &spr_write_generic, 5232 0x00000000); 5233 /* XXX : not implemented */ 5234 spr_register(env, SPR_750_GQR5, "GQR5", 5235 SPR_NOACCESS, SPR_NOACCESS, 5236 &spr_read_generic, &spr_write_generic, 5237 0x00000000); 5238 /* XXX : not implemented */ 5239 spr_register(env, SPR_750_GQR6, "GQR6", 5240 SPR_NOACCESS, SPR_NOACCESS, 5241 &spr_read_generic, &spr_write_generic, 5242 0x00000000); 5243 /* XXX : not implemented */ 5244 spr_register(env, SPR_750_GQR7, "GQR7", 5245 SPR_NOACCESS, SPR_NOACCESS, 5246 &spr_read_generic, &spr_write_generic, 5247 0x00000000); 5248 /* Memory management */ 5249 register_low_BATs(env); 5250 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 5251 register_high_BATs(env); 5252 init_excp_750cl(env); 5253 env->dcache_line_size = 32; 5254 env->icache_line_size = 32; 5255 /* Allocate hardware IRQ controller */ 5256 ppc6xx_irq_init(env_archcpu(env)); 5257 } 5258 5259 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 5260 { 5261 DeviceClass *dc = DEVICE_CLASS(oc); 5262 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5263 5264 dc->desc = "PowerPC 750 CL"; 5265 pcc->init_proc = init_proc_750cl; 5266 pcc->check_pow = check_pow_hid0; 5267 /* 5268 * XXX: not implemented: 5269 * cache lock instructions: 5270 * dcbz_l 5271 * floating point paired instructions 5272 * psq_lux 5273 * psq_lx 5274 * psq_stux 5275 * psq_stx 5276 * ps_abs 5277 * ps_add 5278 * ps_cmpo0 5279 * ps_cmpo1 5280 * ps_cmpu0 5281 * ps_cmpu1 5282 * ps_div 5283 * ps_madd 5284 * ps_madds0 5285 * ps_madds1 5286 * ps_merge00 5287 * ps_merge01 5288 * ps_merge10 5289 * ps_merge11 5290 * ps_mr 5291 * ps_msub 5292 * ps_mul 5293 * ps_muls0 5294 * ps_muls1 5295 * ps_nabs 5296 * ps_neg 5297 * ps_nmadd 5298 * ps_nmsub 5299 * ps_res 5300 * ps_rsqrte 5301 * ps_sel 5302 * ps_sub 5303 * ps_sum0 5304 * ps_sum1 5305 */ 5306 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5307 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5308 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5309 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5310 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5311 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5312 PPC_SEGMENT | PPC_EXTERN; 5313 pcc->msr_mask = (1ull << MSR_POW) | 5314 (1ull << MSR_ILE) | 5315 (1ull << MSR_EE) | 5316 (1ull << MSR_PR) | 5317 (1ull << MSR_FP) | 5318 (1ull << MSR_ME) | 5319 (1ull << MSR_FE0) | 5320 (1ull << MSR_SE) | 5321 (1ull << MSR_DE) | 5322 (1ull << MSR_FE1) | 5323 (1ull << MSR_EP) | 5324 (1ull << MSR_IR) | 5325 (1ull << MSR_DR) | 5326 (1ull << MSR_PMM) | 5327 (1ull << MSR_RI) | 5328 (1ull << MSR_LE); 5329 pcc->mmu_model = POWERPC_MMU_32B; 5330 #if defined(CONFIG_SOFTMMU) 5331 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5332 #endif 5333 pcc->excp_model = POWERPC_EXCP_7x0; 5334 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5335 pcc->bfd_mach = bfd_mach_ppc_750; 5336 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5337 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5338 } 5339 5340 static void init_proc_750cx(CPUPPCState *env) 5341 { 5342 register_ne_601_sprs(env); 5343 register_sdr1_sprs(env); 5344 register_7xx_sprs(env); 5345 /* XXX : not implemented */ 5346 spr_register(env, SPR_L2CR, "L2CR", 5347 SPR_NOACCESS, SPR_NOACCESS, 5348 &spr_read_generic, spr_access_nop, 5349 0x00000000); 5350 /* Time base */ 5351 register_tbl(env); 5352 /* Thermal management */ 5353 register_thrm_sprs(env); 5354 /* This register is not implemented but is present for compatibility */ 5355 spr_register(env, SPR_SDA, "SDA", 5356 SPR_NOACCESS, SPR_NOACCESS, 5357 &spr_read_generic, &spr_write_generic, 5358 0x00000000); 5359 /* Hardware implementation registers */ 5360 /* XXX : not implemented */ 5361 spr_register(env, SPR_HID0, "HID0", 5362 SPR_NOACCESS, SPR_NOACCESS, 5363 &spr_read_generic, &spr_write_generic, 5364 0x00000000); 5365 /* XXX : not implemented */ 5366 spr_register(env, SPR_HID1, "HID1", 5367 SPR_NOACCESS, SPR_NOACCESS, 5368 &spr_read_generic, &spr_write_generic, 5369 0x00000000); 5370 /* Memory management */ 5371 register_low_BATs(env); 5372 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 5373 register_high_BATs(env); 5374 init_excp_750cx(env); 5375 env->dcache_line_size = 32; 5376 env->icache_line_size = 32; 5377 /* Allocate hardware IRQ controller */ 5378 ppc6xx_irq_init(env_archcpu(env)); 5379 } 5380 5381 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 5382 { 5383 DeviceClass *dc = DEVICE_CLASS(oc); 5384 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5385 5386 dc->desc = "PowerPC 750CX"; 5387 pcc->init_proc = init_proc_750cx; 5388 pcc->check_pow = check_pow_hid0; 5389 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5390 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5391 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5392 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5393 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5395 PPC_SEGMENT | PPC_EXTERN; 5396 pcc->msr_mask = (1ull << MSR_POW) | 5397 (1ull << MSR_ILE) | 5398 (1ull << MSR_EE) | 5399 (1ull << MSR_PR) | 5400 (1ull << MSR_FP) | 5401 (1ull << MSR_ME) | 5402 (1ull << MSR_FE0) | 5403 (1ull << MSR_SE) | 5404 (1ull << MSR_DE) | 5405 (1ull << MSR_FE1) | 5406 (1ull << MSR_EP) | 5407 (1ull << MSR_IR) | 5408 (1ull << MSR_DR) | 5409 (1ull << MSR_PMM) | 5410 (1ull << MSR_RI) | 5411 (1ull << MSR_LE); 5412 pcc->mmu_model = POWERPC_MMU_32B; 5413 #if defined(CONFIG_SOFTMMU) 5414 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5415 #endif 5416 pcc->excp_model = POWERPC_EXCP_7x0; 5417 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5418 pcc->bfd_mach = bfd_mach_ppc_750; 5419 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5420 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5421 } 5422 5423 static void init_proc_750fx(CPUPPCState *env) 5424 { 5425 register_ne_601_sprs(env); 5426 register_sdr1_sprs(env); 5427 register_7xx_sprs(env); 5428 /* XXX : not implemented */ 5429 spr_register(env, SPR_L2CR, "L2CR", 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_generic, spr_access_nop, 5432 0x00000000); 5433 /* Time base */ 5434 register_tbl(env); 5435 /* Thermal management */ 5436 register_thrm_sprs(env); 5437 /* XXX : not implemented */ 5438 spr_register(env, SPR_750_THRM4, "THRM4", 5439 SPR_NOACCESS, SPR_NOACCESS, 5440 &spr_read_generic, &spr_write_generic, 5441 0x00000000); 5442 /* Hardware implementation registers */ 5443 /* XXX : not implemented */ 5444 spr_register(env, SPR_HID0, "HID0", 5445 SPR_NOACCESS, SPR_NOACCESS, 5446 &spr_read_generic, &spr_write_generic, 5447 0x00000000); 5448 /* XXX : not implemented */ 5449 spr_register(env, SPR_HID1, "HID1", 5450 SPR_NOACCESS, SPR_NOACCESS, 5451 &spr_read_generic, &spr_write_generic, 5452 0x00000000); 5453 /* XXX : not implemented */ 5454 spr_register(env, SPR_750FX_HID2, "HID2", 5455 SPR_NOACCESS, SPR_NOACCESS, 5456 &spr_read_generic, &spr_write_generic, 5457 0x00000000); 5458 /* Memory management */ 5459 register_low_BATs(env); 5460 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5461 register_high_BATs(env); 5462 init_excp_7x0(env); 5463 env->dcache_line_size = 32; 5464 env->icache_line_size = 32; 5465 /* Allocate hardware IRQ controller */ 5466 ppc6xx_irq_init(env_archcpu(env)); 5467 } 5468 5469 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 5470 { 5471 DeviceClass *dc = DEVICE_CLASS(oc); 5472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5473 5474 dc->desc = "PowerPC 750FX"; 5475 pcc->init_proc = init_proc_750fx; 5476 pcc->check_pow = check_pow_hid0; 5477 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5478 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5479 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5480 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5481 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5482 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5483 PPC_SEGMENT | PPC_EXTERN; 5484 pcc->msr_mask = (1ull << MSR_POW) | 5485 (1ull << MSR_ILE) | 5486 (1ull << MSR_EE) | 5487 (1ull << MSR_PR) | 5488 (1ull << MSR_FP) | 5489 (1ull << MSR_ME) | 5490 (1ull << MSR_FE0) | 5491 (1ull << MSR_SE) | 5492 (1ull << MSR_DE) | 5493 (1ull << MSR_FE1) | 5494 (1ull << MSR_EP) | 5495 (1ull << MSR_IR) | 5496 (1ull << MSR_DR) | 5497 (1ull << MSR_PMM) | 5498 (1ull << MSR_RI) | 5499 (1ull << MSR_LE); 5500 pcc->mmu_model = POWERPC_MMU_32B; 5501 #if defined(CONFIG_SOFTMMU) 5502 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5503 #endif 5504 pcc->excp_model = POWERPC_EXCP_7x0; 5505 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5506 pcc->bfd_mach = bfd_mach_ppc_750; 5507 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5508 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5509 } 5510 5511 static void init_proc_750gx(CPUPPCState *env) 5512 { 5513 register_ne_601_sprs(env); 5514 register_sdr1_sprs(env); 5515 register_7xx_sprs(env); 5516 /* XXX : not implemented (XXX: different from 750fx) */ 5517 spr_register(env, SPR_L2CR, "L2CR", 5518 SPR_NOACCESS, SPR_NOACCESS, 5519 &spr_read_generic, spr_access_nop, 5520 0x00000000); 5521 /* Time base */ 5522 register_tbl(env); 5523 /* Thermal management */ 5524 register_thrm_sprs(env); 5525 /* XXX : not implemented */ 5526 spr_register(env, SPR_750_THRM4, "THRM4", 5527 SPR_NOACCESS, SPR_NOACCESS, 5528 &spr_read_generic, &spr_write_generic, 5529 0x00000000); 5530 /* Hardware implementation registers */ 5531 /* XXX : not implemented (XXX: different from 750fx) */ 5532 spr_register(env, SPR_HID0, "HID0", 5533 SPR_NOACCESS, SPR_NOACCESS, 5534 &spr_read_generic, &spr_write_generic, 5535 0x00000000); 5536 /* XXX : not implemented */ 5537 spr_register(env, SPR_HID1, "HID1", 5538 SPR_NOACCESS, SPR_NOACCESS, 5539 &spr_read_generic, &spr_write_generic, 5540 0x00000000); 5541 /* XXX : not implemented (XXX: different from 750fx) */ 5542 spr_register(env, SPR_750FX_HID2, "HID2", 5543 SPR_NOACCESS, SPR_NOACCESS, 5544 &spr_read_generic, &spr_write_generic, 5545 0x00000000); 5546 /* Memory management */ 5547 register_low_BATs(env); 5548 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5549 register_high_BATs(env); 5550 init_excp_7x0(env); 5551 env->dcache_line_size = 32; 5552 env->icache_line_size = 32; 5553 /* Allocate hardware IRQ controller */ 5554 ppc6xx_irq_init(env_archcpu(env)); 5555 } 5556 5557 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 5558 { 5559 DeviceClass *dc = DEVICE_CLASS(oc); 5560 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5561 5562 dc->desc = "PowerPC 750GX"; 5563 pcc->init_proc = init_proc_750gx; 5564 pcc->check_pow = check_pow_hid0; 5565 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5566 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5567 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5568 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5569 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5570 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5571 PPC_SEGMENT | PPC_EXTERN; 5572 pcc->msr_mask = (1ull << MSR_POW) | 5573 (1ull << MSR_ILE) | 5574 (1ull << MSR_EE) | 5575 (1ull << MSR_PR) | 5576 (1ull << MSR_FP) | 5577 (1ull << MSR_ME) | 5578 (1ull << MSR_FE0) | 5579 (1ull << MSR_SE) | 5580 (1ull << MSR_DE) | 5581 (1ull << MSR_FE1) | 5582 (1ull << MSR_EP) | 5583 (1ull << MSR_IR) | 5584 (1ull << MSR_DR) | 5585 (1ull << MSR_PMM) | 5586 (1ull << MSR_RI) | 5587 (1ull << MSR_LE); 5588 pcc->mmu_model = POWERPC_MMU_32B; 5589 #if defined(CONFIG_SOFTMMU) 5590 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5591 #endif 5592 pcc->excp_model = POWERPC_EXCP_7x0; 5593 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5594 pcc->bfd_mach = bfd_mach_ppc_750; 5595 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5596 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5597 } 5598 5599 static void init_proc_745(CPUPPCState *env) 5600 { 5601 register_ne_601_sprs(env); 5602 register_sdr1_sprs(env); 5603 register_7xx_sprs(env); 5604 register_G2_755_sprs(env); 5605 /* Time base */ 5606 register_tbl(env); 5607 /* Thermal management */ 5608 register_thrm_sprs(env); 5609 /* Hardware implementation registers */ 5610 /* XXX : not implemented */ 5611 spr_register(env, SPR_HID0, "HID0", 5612 SPR_NOACCESS, SPR_NOACCESS, 5613 &spr_read_generic, &spr_write_generic, 5614 0x00000000); 5615 /* XXX : not implemented */ 5616 spr_register(env, SPR_HID1, "HID1", 5617 SPR_NOACCESS, SPR_NOACCESS, 5618 &spr_read_generic, &spr_write_generic, 5619 0x00000000); 5620 /* XXX : not implemented */ 5621 spr_register(env, SPR_HID2, "HID2", 5622 SPR_NOACCESS, SPR_NOACCESS, 5623 &spr_read_generic, &spr_write_generic, 5624 0x00000000); 5625 /* Memory management */ 5626 register_low_BATs(env); 5627 register_high_BATs(env); 5628 register_6xx_7xx_soft_tlb(env, 64, 2); 5629 init_excp_7x5(env); 5630 env->dcache_line_size = 32; 5631 env->icache_line_size = 32; 5632 /* Allocate hardware IRQ controller */ 5633 ppc6xx_irq_init(env_archcpu(env)); 5634 } 5635 5636 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 5637 { 5638 DeviceClass *dc = DEVICE_CLASS(oc); 5639 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5640 5641 dc->desc = "PowerPC 745"; 5642 pcc->init_proc = init_proc_745; 5643 pcc->check_pow = check_pow_hid0; 5644 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5645 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5646 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5647 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5648 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5649 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5650 PPC_SEGMENT | PPC_EXTERN; 5651 pcc->msr_mask = (1ull << MSR_POW) | 5652 (1ull << MSR_ILE) | 5653 (1ull << MSR_EE) | 5654 (1ull << MSR_PR) | 5655 (1ull << MSR_FP) | 5656 (1ull << MSR_ME) | 5657 (1ull << MSR_FE0) | 5658 (1ull << MSR_SE) | 5659 (1ull << MSR_DE) | 5660 (1ull << MSR_FE1) | 5661 (1ull << MSR_EP) | 5662 (1ull << MSR_IR) | 5663 (1ull << MSR_DR) | 5664 (1ull << MSR_PMM) | 5665 (1ull << MSR_RI) | 5666 (1ull << MSR_LE); 5667 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5668 pcc->excp_model = POWERPC_EXCP_7x5; 5669 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5670 pcc->bfd_mach = bfd_mach_ppc_750; 5671 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5672 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5673 } 5674 5675 static void init_proc_755(CPUPPCState *env) 5676 { 5677 register_ne_601_sprs(env); 5678 register_sdr1_sprs(env); 5679 register_7xx_sprs(env); 5680 register_G2_755_sprs(env); 5681 /* Time base */ 5682 register_tbl(env); 5683 /* L2 cache control */ 5684 /* XXX : not implemented */ 5685 spr_register(env, SPR_L2CR, "L2CR", 5686 SPR_NOACCESS, SPR_NOACCESS, 5687 &spr_read_generic, spr_access_nop, 5688 0x00000000); 5689 /* XXX : not implemented */ 5690 spr_register(env, SPR_L2PMCR, "L2PMCR", 5691 SPR_NOACCESS, SPR_NOACCESS, 5692 &spr_read_generic, &spr_write_generic, 5693 0x00000000); 5694 /* Thermal management */ 5695 register_thrm_sprs(env); 5696 /* Hardware implementation registers */ 5697 /* XXX : not implemented */ 5698 spr_register(env, SPR_HID0, "HID0", 5699 SPR_NOACCESS, SPR_NOACCESS, 5700 &spr_read_generic, &spr_write_generic, 5701 0x00000000); 5702 /* XXX : not implemented */ 5703 spr_register(env, SPR_HID1, "HID1", 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_generic, &spr_write_generic, 5706 0x00000000); 5707 /* XXX : not implemented */ 5708 spr_register(env, SPR_HID2, "HID2", 5709 SPR_NOACCESS, SPR_NOACCESS, 5710 &spr_read_generic, &spr_write_generic, 5711 0x00000000); 5712 /* Memory management */ 5713 register_low_BATs(env); 5714 register_high_BATs(env); 5715 register_6xx_7xx_soft_tlb(env, 64, 2); 5716 init_excp_7x5(env); 5717 env->dcache_line_size = 32; 5718 env->icache_line_size = 32; 5719 /* Allocate hardware IRQ controller */ 5720 ppc6xx_irq_init(env_archcpu(env)); 5721 } 5722 5723 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 5724 { 5725 DeviceClass *dc = DEVICE_CLASS(oc); 5726 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5727 5728 dc->desc = "PowerPC 755"; 5729 pcc->init_proc = init_proc_755; 5730 pcc->check_pow = check_pow_hid0; 5731 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5732 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5733 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5734 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5735 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5736 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5737 PPC_SEGMENT | PPC_EXTERN; 5738 pcc->msr_mask = (1ull << MSR_POW) | 5739 (1ull << MSR_ILE) | 5740 (1ull << MSR_EE) | 5741 (1ull << MSR_PR) | 5742 (1ull << MSR_FP) | 5743 (1ull << MSR_ME) | 5744 (1ull << MSR_FE0) | 5745 (1ull << MSR_SE) | 5746 (1ull << MSR_DE) | 5747 (1ull << MSR_FE1) | 5748 (1ull << MSR_EP) | 5749 (1ull << MSR_IR) | 5750 (1ull << MSR_DR) | 5751 (1ull << MSR_PMM) | 5752 (1ull << MSR_RI) | 5753 (1ull << MSR_LE); 5754 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5755 pcc->excp_model = POWERPC_EXCP_7x5; 5756 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5757 pcc->bfd_mach = bfd_mach_ppc_750; 5758 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5759 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5760 } 5761 5762 static void init_proc_7400(CPUPPCState *env) 5763 { 5764 register_ne_601_sprs(env); 5765 register_sdr1_sprs(env); 5766 register_7xx_sprs(env); 5767 /* Time base */ 5768 register_tbl(env); 5769 /* 74xx specific SPR */ 5770 register_74xx_sprs(env); 5771 vscr_init(env, 0x00010000); 5772 /* XXX : not implemented */ 5773 spr_register(env, SPR_UBAMR, "UBAMR", 5774 &spr_read_ureg, SPR_NOACCESS, 5775 &spr_read_ureg, SPR_NOACCESS, 5776 0x00000000); 5777 /* XXX: this seems not implemented on all revisions. */ 5778 /* XXX : not implemented */ 5779 spr_register(env, SPR_MSSCR1, "MSSCR1", 5780 SPR_NOACCESS, SPR_NOACCESS, 5781 &spr_read_generic, &spr_write_generic, 5782 0x00000000); 5783 /* Thermal management */ 5784 register_thrm_sprs(env); 5785 /* Memory management */ 5786 register_low_BATs(env); 5787 init_excp_7400(env); 5788 env->dcache_line_size = 32; 5789 env->icache_line_size = 32; 5790 /* Allocate hardware IRQ controller */ 5791 ppc6xx_irq_init(env_archcpu(env)); 5792 } 5793 5794 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5795 { 5796 DeviceClass *dc = DEVICE_CLASS(oc); 5797 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5798 5799 dc->desc = "PowerPC 7400 (aka G4)"; 5800 pcc->init_proc = init_proc_7400; 5801 pcc->check_pow = check_pow_hid0; 5802 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5803 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5804 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5805 PPC_FLOAT_STFIWX | 5806 PPC_CACHE | PPC_CACHE_ICBI | 5807 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5808 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5809 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5810 PPC_MEM_TLBIA | 5811 PPC_SEGMENT | PPC_EXTERN | 5812 PPC_ALTIVEC; 5813 pcc->msr_mask = (1ull << MSR_VR) | 5814 (1ull << MSR_POW) | 5815 (1ull << MSR_ILE) | 5816 (1ull << MSR_EE) | 5817 (1ull << MSR_PR) | 5818 (1ull << MSR_FP) | 5819 (1ull << MSR_ME) | 5820 (1ull << MSR_FE0) | 5821 (1ull << MSR_SE) | 5822 (1ull << MSR_DE) | 5823 (1ull << MSR_FE1) | 5824 (1ull << MSR_EP) | 5825 (1ull << MSR_IR) | 5826 (1ull << MSR_DR) | 5827 (1ull << MSR_PMM) | 5828 (1ull << MSR_RI) | 5829 (1ull << MSR_LE); 5830 pcc->mmu_model = POWERPC_MMU_32B; 5831 #if defined(CONFIG_SOFTMMU) 5832 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5833 #endif 5834 pcc->excp_model = POWERPC_EXCP_74xx; 5835 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5836 pcc->bfd_mach = bfd_mach_ppc_7400; 5837 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5838 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5839 POWERPC_FLAG_BUS_CLK; 5840 } 5841 5842 static void init_proc_7410(CPUPPCState *env) 5843 { 5844 register_ne_601_sprs(env); 5845 register_sdr1_sprs(env); 5846 register_7xx_sprs(env); 5847 /* Time base */ 5848 register_tbl(env); 5849 /* 74xx specific SPR */ 5850 register_74xx_sprs(env); 5851 vscr_init(env, 0x00010000); 5852 /* XXX : not implemented */ 5853 spr_register(env, SPR_UBAMR, "UBAMR", 5854 &spr_read_ureg, SPR_NOACCESS, 5855 &spr_read_ureg, SPR_NOACCESS, 5856 0x00000000); 5857 /* Thermal management */ 5858 register_thrm_sprs(env); 5859 /* L2PMCR */ 5860 /* XXX : not implemented */ 5861 spr_register(env, SPR_L2PMCR, "L2PMCR", 5862 SPR_NOACCESS, SPR_NOACCESS, 5863 &spr_read_generic, &spr_write_generic, 5864 0x00000000); 5865 /* LDSTDB */ 5866 /* XXX : not implemented */ 5867 spr_register(env, SPR_LDSTDB, "LDSTDB", 5868 SPR_NOACCESS, SPR_NOACCESS, 5869 &spr_read_generic, &spr_write_generic, 5870 0x00000000); 5871 /* Memory management */ 5872 register_low_BATs(env); 5873 init_excp_7400(env); 5874 env->dcache_line_size = 32; 5875 env->icache_line_size = 32; 5876 /* Allocate hardware IRQ controller */ 5877 ppc6xx_irq_init(env_archcpu(env)); 5878 } 5879 5880 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5881 { 5882 DeviceClass *dc = DEVICE_CLASS(oc); 5883 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5884 5885 dc->desc = "PowerPC 7410 (aka G4)"; 5886 pcc->init_proc = init_proc_7410; 5887 pcc->check_pow = check_pow_hid0; 5888 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5890 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5891 PPC_FLOAT_STFIWX | 5892 PPC_CACHE | PPC_CACHE_ICBI | 5893 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5894 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5896 PPC_MEM_TLBIA | 5897 PPC_SEGMENT | PPC_EXTERN | 5898 PPC_ALTIVEC; 5899 pcc->msr_mask = (1ull << MSR_VR) | 5900 (1ull << MSR_POW) | 5901 (1ull << MSR_ILE) | 5902 (1ull << MSR_EE) | 5903 (1ull << MSR_PR) | 5904 (1ull << MSR_FP) | 5905 (1ull << MSR_ME) | 5906 (1ull << MSR_FE0) | 5907 (1ull << MSR_SE) | 5908 (1ull << MSR_DE) | 5909 (1ull << MSR_FE1) | 5910 (1ull << MSR_EP) | 5911 (1ull << MSR_IR) | 5912 (1ull << MSR_DR) | 5913 (1ull << MSR_PMM) | 5914 (1ull << MSR_RI) | 5915 (1ull << MSR_LE); 5916 pcc->mmu_model = POWERPC_MMU_32B; 5917 #if defined(CONFIG_SOFTMMU) 5918 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5919 #endif 5920 pcc->excp_model = POWERPC_EXCP_74xx; 5921 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5922 pcc->bfd_mach = bfd_mach_ppc_7400; 5923 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5924 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5925 POWERPC_FLAG_BUS_CLK; 5926 } 5927 5928 static void init_proc_7440(CPUPPCState *env) 5929 { 5930 register_ne_601_sprs(env); 5931 register_sdr1_sprs(env); 5932 register_7xx_sprs(env); 5933 /* Time base */ 5934 register_tbl(env); 5935 /* 74xx specific SPR */ 5936 register_74xx_sprs(env); 5937 vscr_init(env, 0x00010000); 5938 /* XXX : not implemented */ 5939 spr_register(env, SPR_UBAMR, "UBAMR", 5940 &spr_read_ureg, SPR_NOACCESS, 5941 &spr_read_ureg, SPR_NOACCESS, 5942 0x00000000); 5943 /* LDSTCR */ 5944 /* XXX : not implemented */ 5945 spr_register(env, SPR_LDSTCR, "LDSTCR", 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 &spr_read_generic, &spr_write_generic, 5948 0x00000000); 5949 /* ICTRL */ 5950 /* XXX : not implemented */ 5951 spr_register(env, SPR_ICTRL, "ICTRL", 5952 SPR_NOACCESS, SPR_NOACCESS, 5953 &spr_read_generic, &spr_write_generic, 5954 0x00000000); 5955 /* MSSSR0 */ 5956 /* XXX : not implemented */ 5957 spr_register(env, SPR_MSSSR0, "MSSSR0", 5958 SPR_NOACCESS, SPR_NOACCESS, 5959 &spr_read_generic, &spr_write_generic, 5960 0x00000000); 5961 /* PMC */ 5962 /* XXX : not implemented */ 5963 spr_register(env, SPR_7XX_PMC5, "PMC5", 5964 SPR_NOACCESS, SPR_NOACCESS, 5965 &spr_read_generic, &spr_write_generic, 5966 0x00000000); 5967 /* XXX : not implemented */ 5968 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5969 &spr_read_ureg, SPR_NOACCESS, 5970 &spr_read_ureg, SPR_NOACCESS, 5971 0x00000000); 5972 /* XXX : not implemented */ 5973 spr_register(env, SPR_7XX_PMC6, "PMC6", 5974 SPR_NOACCESS, SPR_NOACCESS, 5975 &spr_read_generic, &spr_write_generic, 5976 0x00000000); 5977 /* XXX : not implemented */ 5978 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5979 &spr_read_ureg, SPR_NOACCESS, 5980 &spr_read_ureg, SPR_NOACCESS, 5981 0x00000000); 5982 /* Memory management */ 5983 register_low_BATs(env); 5984 register_74xx_soft_tlb(env, 128, 2); 5985 init_excp_7450(env); 5986 env->dcache_line_size = 32; 5987 env->icache_line_size = 32; 5988 /* Allocate hardware IRQ controller */ 5989 ppc6xx_irq_init(env_archcpu(env)); 5990 } 5991 5992 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5993 { 5994 DeviceClass *dc = DEVICE_CLASS(oc); 5995 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5996 5997 dc->desc = "PowerPC 7440 (aka G4)"; 5998 pcc->init_proc = init_proc_7440; 5999 pcc->check_pow = check_pow_hid0_74xx; 6000 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6001 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6002 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6003 PPC_FLOAT_STFIWX | 6004 PPC_CACHE | PPC_CACHE_ICBI | 6005 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6006 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6007 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6008 PPC_MEM_TLBIA | PPC_74xx_TLB | 6009 PPC_SEGMENT | PPC_EXTERN | 6010 PPC_ALTIVEC; 6011 pcc->msr_mask = (1ull << MSR_VR) | 6012 (1ull << MSR_POW) | 6013 (1ull << MSR_ILE) | 6014 (1ull << MSR_EE) | 6015 (1ull << MSR_PR) | 6016 (1ull << MSR_FP) | 6017 (1ull << MSR_ME) | 6018 (1ull << MSR_FE0) | 6019 (1ull << MSR_SE) | 6020 (1ull << MSR_DE) | 6021 (1ull << MSR_FE1) | 6022 (1ull << MSR_EP) | 6023 (1ull << MSR_IR) | 6024 (1ull << MSR_DR) | 6025 (1ull << MSR_PMM) | 6026 (1ull << MSR_RI) | 6027 (1ull << MSR_LE); 6028 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6029 pcc->excp_model = POWERPC_EXCP_74xx; 6030 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6031 pcc->bfd_mach = bfd_mach_ppc_7400; 6032 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6033 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6034 POWERPC_FLAG_BUS_CLK; 6035 } 6036 6037 static void init_proc_7450(CPUPPCState *env) 6038 { 6039 register_ne_601_sprs(env); 6040 register_sdr1_sprs(env); 6041 register_7xx_sprs(env); 6042 /* Time base */ 6043 register_tbl(env); 6044 /* 74xx specific SPR */ 6045 register_74xx_sprs(env); 6046 vscr_init(env, 0x00010000); 6047 /* Level 3 cache control */ 6048 register_l3_ctrl(env); 6049 /* L3ITCR1 */ 6050 /* XXX : not implemented */ 6051 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6052 SPR_NOACCESS, SPR_NOACCESS, 6053 &spr_read_generic, &spr_write_generic, 6054 0x00000000); 6055 /* L3ITCR2 */ 6056 /* XXX : not implemented */ 6057 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6058 SPR_NOACCESS, SPR_NOACCESS, 6059 &spr_read_generic, &spr_write_generic, 6060 0x00000000); 6061 /* L3ITCR3 */ 6062 /* XXX : not implemented */ 6063 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6064 SPR_NOACCESS, SPR_NOACCESS, 6065 &spr_read_generic, &spr_write_generic, 6066 0x00000000); 6067 /* L3OHCR */ 6068 /* XXX : not implemented */ 6069 spr_register(env, SPR_L3OHCR, "L3OHCR", 6070 SPR_NOACCESS, SPR_NOACCESS, 6071 &spr_read_generic, &spr_write_generic, 6072 0x00000000); 6073 /* XXX : not implemented */ 6074 spr_register(env, SPR_UBAMR, "UBAMR", 6075 &spr_read_ureg, SPR_NOACCESS, 6076 &spr_read_ureg, SPR_NOACCESS, 6077 0x00000000); 6078 /* LDSTCR */ 6079 /* XXX : not implemented */ 6080 spr_register(env, SPR_LDSTCR, "LDSTCR", 6081 SPR_NOACCESS, SPR_NOACCESS, 6082 &spr_read_generic, &spr_write_generic, 6083 0x00000000); 6084 /* ICTRL */ 6085 /* XXX : not implemented */ 6086 spr_register(env, SPR_ICTRL, "ICTRL", 6087 SPR_NOACCESS, SPR_NOACCESS, 6088 &spr_read_generic, &spr_write_generic, 6089 0x00000000); 6090 /* MSSSR0 */ 6091 /* XXX : not implemented */ 6092 spr_register(env, SPR_MSSSR0, "MSSSR0", 6093 SPR_NOACCESS, SPR_NOACCESS, 6094 &spr_read_generic, &spr_write_generic, 6095 0x00000000); 6096 /* PMC */ 6097 /* XXX : not implemented */ 6098 spr_register(env, SPR_7XX_PMC5, "PMC5", 6099 SPR_NOACCESS, SPR_NOACCESS, 6100 &spr_read_generic, &spr_write_generic, 6101 0x00000000); 6102 /* XXX : not implemented */ 6103 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6104 &spr_read_ureg, SPR_NOACCESS, 6105 &spr_read_ureg, SPR_NOACCESS, 6106 0x00000000); 6107 /* XXX : not implemented */ 6108 spr_register(env, SPR_7XX_PMC6, "PMC6", 6109 SPR_NOACCESS, SPR_NOACCESS, 6110 &spr_read_generic, &spr_write_generic, 6111 0x00000000); 6112 /* XXX : not implemented */ 6113 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6114 &spr_read_ureg, SPR_NOACCESS, 6115 &spr_read_ureg, SPR_NOACCESS, 6116 0x00000000); 6117 /* Memory management */ 6118 register_low_BATs(env); 6119 register_74xx_soft_tlb(env, 128, 2); 6120 init_excp_7450(env); 6121 env->dcache_line_size = 32; 6122 env->icache_line_size = 32; 6123 /* Allocate hardware IRQ controller */ 6124 ppc6xx_irq_init(env_archcpu(env)); 6125 } 6126 6127 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 6128 { 6129 DeviceClass *dc = DEVICE_CLASS(oc); 6130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6131 6132 dc->desc = "PowerPC 7450 (aka G4)"; 6133 pcc->init_proc = init_proc_7450; 6134 pcc->check_pow = check_pow_hid0_74xx; 6135 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6137 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6138 PPC_FLOAT_STFIWX | 6139 PPC_CACHE | PPC_CACHE_ICBI | 6140 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6141 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6142 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6143 PPC_MEM_TLBIA | PPC_74xx_TLB | 6144 PPC_SEGMENT | PPC_EXTERN | 6145 PPC_ALTIVEC; 6146 pcc->msr_mask = (1ull << MSR_VR) | 6147 (1ull << MSR_POW) | 6148 (1ull << MSR_ILE) | 6149 (1ull << MSR_EE) | 6150 (1ull << MSR_PR) | 6151 (1ull << MSR_FP) | 6152 (1ull << MSR_ME) | 6153 (1ull << MSR_FE0) | 6154 (1ull << MSR_SE) | 6155 (1ull << MSR_DE) | 6156 (1ull << MSR_FE1) | 6157 (1ull << MSR_EP) | 6158 (1ull << MSR_IR) | 6159 (1ull << MSR_DR) | 6160 (1ull << MSR_PMM) | 6161 (1ull << MSR_RI) | 6162 (1ull << MSR_LE); 6163 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6164 pcc->excp_model = POWERPC_EXCP_74xx; 6165 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6166 pcc->bfd_mach = bfd_mach_ppc_7400; 6167 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6168 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6169 POWERPC_FLAG_BUS_CLK; 6170 } 6171 6172 static void init_proc_7445(CPUPPCState *env) 6173 { 6174 register_ne_601_sprs(env); 6175 register_sdr1_sprs(env); 6176 register_7xx_sprs(env); 6177 /* Time base */ 6178 register_tbl(env); 6179 /* 74xx specific SPR */ 6180 register_74xx_sprs(env); 6181 vscr_init(env, 0x00010000); 6182 /* LDSTCR */ 6183 /* XXX : not implemented */ 6184 spr_register(env, SPR_LDSTCR, "LDSTCR", 6185 SPR_NOACCESS, SPR_NOACCESS, 6186 &spr_read_generic, &spr_write_generic, 6187 0x00000000); 6188 /* ICTRL */ 6189 /* XXX : not implemented */ 6190 spr_register(env, SPR_ICTRL, "ICTRL", 6191 SPR_NOACCESS, SPR_NOACCESS, 6192 &spr_read_generic, &spr_write_generic, 6193 0x00000000); 6194 /* MSSSR0 */ 6195 /* XXX : not implemented */ 6196 spr_register(env, SPR_MSSSR0, "MSSSR0", 6197 SPR_NOACCESS, SPR_NOACCESS, 6198 &spr_read_generic, &spr_write_generic, 6199 0x00000000); 6200 /* PMC */ 6201 /* XXX : not implemented */ 6202 spr_register(env, SPR_7XX_PMC5, "PMC5", 6203 SPR_NOACCESS, SPR_NOACCESS, 6204 &spr_read_generic, &spr_write_generic, 6205 0x00000000); 6206 /* XXX : not implemented */ 6207 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6208 &spr_read_ureg, SPR_NOACCESS, 6209 &spr_read_ureg, SPR_NOACCESS, 6210 0x00000000); 6211 /* XXX : not implemented */ 6212 spr_register(env, SPR_7XX_PMC6, "PMC6", 6213 SPR_NOACCESS, SPR_NOACCESS, 6214 &spr_read_generic, &spr_write_generic, 6215 0x00000000); 6216 /* XXX : not implemented */ 6217 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6218 &spr_read_ureg, SPR_NOACCESS, 6219 &spr_read_ureg, SPR_NOACCESS, 6220 0x00000000); 6221 /* SPRGs */ 6222 spr_register(env, SPR_SPRG4, "SPRG4", 6223 SPR_NOACCESS, SPR_NOACCESS, 6224 &spr_read_generic, &spr_write_generic, 6225 0x00000000); 6226 spr_register(env, SPR_USPRG4, "USPRG4", 6227 &spr_read_ureg, SPR_NOACCESS, 6228 &spr_read_ureg, SPR_NOACCESS, 6229 0x00000000); 6230 spr_register(env, SPR_SPRG5, "SPRG5", 6231 SPR_NOACCESS, SPR_NOACCESS, 6232 &spr_read_generic, &spr_write_generic, 6233 0x00000000); 6234 spr_register(env, SPR_USPRG5, "USPRG5", 6235 &spr_read_ureg, SPR_NOACCESS, 6236 &spr_read_ureg, SPR_NOACCESS, 6237 0x00000000); 6238 spr_register(env, SPR_SPRG6, "SPRG6", 6239 SPR_NOACCESS, SPR_NOACCESS, 6240 &spr_read_generic, &spr_write_generic, 6241 0x00000000); 6242 spr_register(env, SPR_USPRG6, "USPRG6", 6243 &spr_read_ureg, SPR_NOACCESS, 6244 &spr_read_ureg, SPR_NOACCESS, 6245 0x00000000); 6246 spr_register(env, SPR_SPRG7, "SPRG7", 6247 SPR_NOACCESS, SPR_NOACCESS, 6248 &spr_read_generic, &spr_write_generic, 6249 0x00000000); 6250 spr_register(env, SPR_USPRG7, "USPRG7", 6251 &spr_read_ureg, SPR_NOACCESS, 6252 &spr_read_ureg, SPR_NOACCESS, 6253 0x00000000); 6254 /* Memory management */ 6255 register_low_BATs(env); 6256 register_high_BATs(env); 6257 register_74xx_soft_tlb(env, 128, 2); 6258 init_excp_7450(env); 6259 env->dcache_line_size = 32; 6260 env->icache_line_size = 32; 6261 /* Allocate hardware IRQ controller */ 6262 ppc6xx_irq_init(env_archcpu(env)); 6263 } 6264 6265 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 6266 { 6267 DeviceClass *dc = DEVICE_CLASS(oc); 6268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6269 6270 dc->desc = "PowerPC 7445 (aka G4)"; 6271 pcc->init_proc = init_proc_7445; 6272 pcc->check_pow = check_pow_hid0_74xx; 6273 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6274 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6275 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6276 PPC_FLOAT_STFIWX | 6277 PPC_CACHE | PPC_CACHE_ICBI | 6278 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6279 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6280 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6281 PPC_MEM_TLBIA | PPC_74xx_TLB | 6282 PPC_SEGMENT | PPC_EXTERN | 6283 PPC_ALTIVEC; 6284 pcc->msr_mask = (1ull << MSR_VR) | 6285 (1ull << MSR_POW) | 6286 (1ull << MSR_ILE) | 6287 (1ull << MSR_EE) | 6288 (1ull << MSR_PR) | 6289 (1ull << MSR_FP) | 6290 (1ull << MSR_ME) | 6291 (1ull << MSR_FE0) | 6292 (1ull << MSR_SE) | 6293 (1ull << MSR_DE) | 6294 (1ull << MSR_FE1) | 6295 (1ull << MSR_EP) | 6296 (1ull << MSR_IR) | 6297 (1ull << MSR_DR) | 6298 (1ull << MSR_PMM) | 6299 (1ull << MSR_RI) | 6300 (1ull << MSR_LE); 6301 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6302 pcc->excp_model = POWERPC_EXCP_74xx; 6303 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6304 pcc->bfd_mach = bfd_mach_ppc_7400; 6305 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6306 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6307 POWERPC_FLAG_BUS_CLK; 6308 } 6309 6310 static void init_proc_7455(CPUPPCState *env) 6311 { 6312 register_ne_601_sprs(env); 6313 register_sdr1_sprs(env); 6314 register_7xx_sprs(env); 6315 /* Time base */ 6316 register_tbl(env); 6317 /* 74xx specific SPR */ 6318 register_74xx_sprs(env); 6319 vscr_init(env, 0x00010000); 6320 /* Level 3 cache control */ 6321 register_l3_ctrl(env); 6322 /* LDSTCR */ 6323 /* XXX : not implemented */ 6324 spr_register(env, SPR_LDSTCR, "LDSTCR", 6325 SPR_NOACCESS, SPR_NOACCESS, 6326 &spr_read_generic, &spr_write_generic, 6327 0x00000000); 6328 /* ICTRL */ 6329 /* XXX : not implemented */ 6330 spr_register(env, SPR_ICTRL, "ICTRL", 6331 SPR_NOACCESS, SPR_NOACCESS, 6332 &spr_read_generic, &spr_write_generic, 6333 0x00000000); 6334 /* MSSSR0 */ 6335 /* XXX : not implemented */ 6336 spr_register(env, SPR_MSSSR0, "MSSSR0", 6337 SPR_NOACCESS, SPR_NOACCESS, 6338 &spr_read_generic, &spr_write_generic, 6339 0x00000000); 6340 /* PMC */ 6341 /* XXX : not implemented */ 6342 spr_register(env, SPR_7XX_PMC5, "PMC5", 6343 SPR_NOACCESS, SPR_NOACCESS, 6344 &spr_read_generic, &spr_write_generic, 6345 0x00000000); 6346 /* XXX : not implemented */ 6347 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6348 &spr_read_ureg, SPR_NOACCESS, 6349 &spr_read_ureg, SPR_NOACCESS, 6350 0x00000000); 6351 /* XXX : not implemented */ 6352 spr_register(env, SPR_7XX_PMC6, "PMC6", 6353 SPR_NOACCESS, SPR_NOACCESS, 6354 &spr_read_generic, &spr_write_generic, 6355 0x00000000); 6356 /* XXX : not implemented */ 6357 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6358 &spr_read_ureg, SPR_NOACCESS, 6359 &spr_read_ureg, SPR_NOACCESS, 6360 0x00000000); 6361 /* SPRGs */ 6362 spr_register(env, SPR_SPRG4, "SPRG4", 6363 SPR_NOACCESS, SPR_NOACCESS, 6364 &spr_read_generic, &spr_write_generic, 6365 0x00000000); 6366 spr_register(env, SPR_USPRG4, "USPRG4", 6367 &spr_read_ureg, SPR_NOACCESS, 6368 &spr_read_ureg, SPR_NOACCESS, 6369 0x00000000); 6370 spr_register(env, SPR_SPRG5, "SPRG5", 6371 SPR_NOACCESS, SPR_NOACCESS, 6372 &spr_read_generic, &spr_write_generic, 6373 0x00000000); 6374 spr_register(env, SPR_USPRG5, "USPRG5", 6375 &spr_read_ureg, SPR_NOACCESS, 6376 &spr_read_ureg, SPR_NOACCESS, 6377 0x00000000); 6378 spr_register(env, SPR_SPRG6, "SPRG6", 6379 SPR_NOACCESS, SPR_NOACCESS, 6380 &spr_read_generic, &spr_write_generic, 6381 0x00000000); 6382 spr_register(env, SPR_USPRG6, "USPRG6", 6383 &spr_read_ureg, SPR_NOACCESS, 6384 &spr_read_ureg, SPR_NOACCESS, 6385 0x00000000); 6386 spr_register(env, SPR_SPRG7, "SPRG7", 6387 SPR_NOACCESS, SPR_NOACCESS, 6388 &spr_read_generic, &spr_write_generic, 6389 0x00000000); 6390 spr_register(env, SPR_USPRG7, "USPRG7", 6391 &spr_read_ureg, SPR_NOACCESS, 6392 &spr_read_ureg, SPR_NOACCESS, 6393 0x00000000); 6394 /* Memory management */ 6395 register_low_BATs(env); 6396 register_high_BATs(env); 6397 register_74xx_soft_tlb(env, 128, 2); 6398 init_excp_7450(env); 6399 env->dcache_line_size = 32; 6400 env->icache_line_size = 32; 6401 /* Allocate hardware IRQ controller */ 6402 ppc6xx_irq_init(env_archcpu(env)); 6403 } 6404 6405 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 6406 { 6407 DeviceClass *dc = DEVICE_CLASS(oc); 6408 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6409 6410 dc->desc = "PowerPC 7455 (aka G4)"; 6411 pcc->init_proc = init_proc_7455; 6412 pcc->check_pow = check_pow_hid0_74xx; 6413 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6414 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6415 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6416 PPC_FLOAT_STFIWX | 6417 PPC_CACHE | PPC_CACHE_ICBI | 6418 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6419 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6420 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6421 PPC_MEM_TLBIA | PPC_74xx_TLB | 6422 PPC_SEGMENT | PPC_EXTERN | 6423 PPC_ALTIVEC; 6424 pcc->msr_mask = (1ull << MSR_VR) | 6425 (1ull << MSR_POW) | 6426 (1ull << MSR_ILE) | 6427 (1ull << MSR_EE) | 6428 (1ull << MSR_PR) | 6429 (1ull << MSR_FP) | 6430 (1ull << MSR_ME) | 6431 (1ull << MSR_FE0) | 6432 (1ull << MSR_SE) | 6433 (1ull << MSR_DE) | 6434 (1ull << MSR_FE1) | 6435 (1ull << MSR_EP) | 6436 (1ull << MSR_IR) | 6437 (1ull << MSR_DR) | 6438 (1ull << MSR_PMM) | 6439 (1ull << MSR_RI) | 6440 (1ull << MSR_LE); 6441 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6442 pcc->excp_model = POWERPC_EXCP_74xx; 6443 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6444 pcc->bfd_mach = bfd_mach_ppc_7400; 6445 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6446 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6447 POWERPC_FLAG_BUS_CLK; 6448 } 6449 6450 static void init_proc_7457(CPUPPCState *env) 6451 { 6452 register_ne_601_sprs(env); 6453 register_sdr1_sprs(env); 6454 register_7xx_sprs(env); 6455 /* Time base */ 6456 register_tbl(env); 6457 /* 74xx specific SPR */ 6458 register_74xx_sprs(env); 6459 vscr_init(env, 0x00010000); 6460 /* Level 3 cache control */ 6461 register_l3_ctrl(env); 6462 /* L3ITCR1 */ 6463 /* XXX : not implemented */ 6464 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6465 SPR_NOACCESS, SPR_NOACCESS, 6466 &spr_read_generic, &spr_write_generic, 6467 0x00000000); 6468 /* L3ITCR2 */ 6469 /* XXX : not implemented */ 6470 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6471 SPR_NOACCESS, SPR_NOACCESS, 6472 &spr_read_generic, &spr_write_generic, 6473 0x00000000); 6474 /* L3ITCR3 */ 6475 /* XXX : not implemented */ 6476 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6477 SPR_NOACCESS, SPR_NOACCESS, 6478 &spr_read_generic, &spr_write_generic, 6479 0x00000000); 6480 /* L3OHCR */ 6481 /* XXX : not implemented */ 6482 spr_register(env, SPR_L3OHCR, "L3OHCR", 6483 SPR_NOACCESS, SPR_NOACCESS, 6484 &spr_read_generic, &spr_write_generic, 6485 0x00000000); 6486 /* LDSTCR */ 6487 /* XXX : not implemented */ 6488 spr_register(env, SPR_LDSTCR, "LDSTCR", 6489 SPR_NOACCESS, SPR_NOACCESS, 6490 &spr_read_generic, &spr_write_generic, 6491 0x00000000); 6492 /* ICTRL */ 6493 /* XXX : not implemented */ 6494 spr_register(env, SPR_ICTRL, "ICTRL", 6495 SPR_NOACCESS, SPR_NOACCESS, 6496 &spr_read_generic, &spr_write_generic, 6497 0x00000000); 6498 /* MSSSR0 */ 6499 /* XXX : not implemented */ 6500 spr_register(env, SPR_MSSSR0, "MSSSR0", 6501 SPR_NOACCESS, SPR_NOACCESS, 6502 &spr_read_generic, &spr_write_generic, 6503 0x00000000); 6504 /* PMC */ 6505 /* XXX : not implemented */ 6506 spr_register(env, SPR_7XX_PMC5, "PMC5", 6507 SPR_NOACCESS, SPR_NOACCESS, 6508 &spr_read_generic, &spr_write_generic, 6509 0x00000000); 6510 /* XXX : not implemented */ 6511 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6512 &spr_read_ureg, SPR_NOACCESS, 6513 &spr_read_ureg, SPR_NOACCESS, 6514 0x00000000); 6515 /* XXX : not implemented */ 6516 spr_register(env, SPR_7XX_PMC6, "PMC6", 6517 SPR_NOACCESS, SPR_NOACCESS, 6518 &spr_read_generic, &spr_write_generic, 6519 0x00000000); 6520 /* XXX : not implemented */ 6521 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6522 &spr_read_ureg, SPR_NOACCESS, 6523 &spr_read_ureg, SPR_NOACCESS, 6524 0x00000000); 6525 /* SPRGs */ 6526 spr_register(env, SPR_SPRG4, "SPRG4", 6527 SPR_NOACCESS, SPR_NOACCESS, 6528 &spr_read_generic, &spr_write_generic, 6529 0x00000000); 6530 spr_register(env, SPR_USPRG4, "USPRG4", 6531 &spr_read_ureg, SPR_NOACCESS, 6532 &spr_read_ureg, SPR_NOACCESS, 6533 0x00000000); 6534 spr_register(env, SPR_SPRG5, "SPRG5", 6535 SPR_NOACCESS, SPR_NOACCESS, 6536 &spr_read_generic, &spr_write_generic, 6537 0x00000000); 6538 spr_register(env, SPR_USPRG5, "USPRG5", 6539 &spr_read_ureg, SPR_NOACCESS, 6540 &spr_read_ureg, SPR_NOACCESS, 6541 0x00000000); 6542 spr_register(env, SPR_SPRG6, "SPRG6", 6543 SPR_NOACCESS, SPR_NOACCESS, 6544 &spr_read_generic, &spr_write_generic, 6545 0x00000000); 6546 spr_register(env, SPR_USPRG6, "USPRG6", 6547 &spr_read_ureg, SPR_NOACCESS, 6548 &spr_read_ureg, SPR_NOACCESS, 6549 0x00000000); 6550 spr_register(env, SPR_SPRG7, "SPRG7", 6551 SPR_NOACCESS, SPR_NOACCESS, 6552 &spr_read_generic, &spr_write_generic, 6553 0x00000000); 6554 spr_register(env, SPR_USPRG7, "USPRG7", 6555 &spr_read_ureg, SPR_NOACCESS, 6556 &spr_read_ureg, SPR_NOACCESS, 6557 0x00000000); 6558 /* Memory management */ 6559 register_low_BATs(env); 6560 register_high_BATs(env); 6561 register_74xx_soft_tlb(env, 128, 2); 6562 init_excp_7450(env); 6563 env->dcache_line_size = 32; 6564 env->icache_line_size = 32; 6565 /* Allocate hardware IRQ controller */ 6566 ppc6xx_irq_init(env_archcpu(env)); 6567 } 6568 6569 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 6570 { 6571 DeviceClass *dc = DEVICE_CLASS(oc); 6572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6573 6574 dc->desc = "PowerPC 7457 (aka G4)"; 6575 pcc->init_proc = init_proc_7457; 6576 pcc->check_pow = check_pow_hid0_74xx; 6577 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6579 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6580 PPC_FLOAT_STFIWX | 6581 PPC_CACHE | PPC_CACHE_ICBI | 6582 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6583 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6585 PPC_MEM_TLBIA | PPC_74xx_TLB | 6586 PPC_SEGMENT | PPC_EXTERN | 6587 PPC_ALTIVEC; 6588 pcc->msr_mask = (1ull << MSR_VR) | 6589 (1ull << MSR_POW) | 6590 (1ull << MSR_ILE) | 6591 (1ull << MSR_EE) | 6592 (1ull << MSR_PR) | 6593 (1ull << MSR_FP) | 6594 (1ull << MSR_ME) | 6595 (1ull << MSR_FE0) | 6596 (1ull << MSR_SE) | 6597 (1ull << MSR_DE) | 6598 (1ull << MSR_FE1) | 6599 (1ull << MSR_EP) | 6600 (1ull << MSR_IR) | 6601 (1ull << MSR_DR) | 6602 (1ull << MSR_PMM) | 6603 (1ull << MSR_RI) | 6604 (1ull << MSR_LE); 6605 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6606 pcc->excp_model = POWERPC_EXCP_74xx; 6607 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6608 pcc->bfd_mach = bfd_mach_ppc_7400; 6609 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6610 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6611 POWERPC_FLAG_BUS_CLK; 6612 } 6613 6614 static void init_proc_e600(CPUPPCState *env) 6615 { 6616 register_ne_601_sprs(env); 6617 register_sdr1_sprs(env); 6618 register_7xx_sprs(env); 6619 /* Time base */ 6620 register_tbl(env); 6621 /* 74xx specific SPR */ 6622 register_74xx_sprs(env); 6623 vscr_init(env, 0x00010000); 6624 /* XXX : not implemented */ 6625 spr_register(env, SPR_UBAMR, "UBAMR", 6626 &spr_read_ureg, SPR_NOACCESS, 6627 &spr_read_ureg, SPR_NOACCESS, 6628 0x00000000); 6629 /* XXX : not implemented */ 6630 spr_register(env, SPR_LDSTCR, "LDSTCR", 6631 SPR_NOACCESS, SPR_NOACCESS, 6632 &spr_read_generic, &spr_write_generic, 6633 0x00000000); 6634 /* XXX : not implemented */ 6635 spr_register(env, SPR_ICTRL, "ICTRL", 6636 SPR_NOACCESS, SPR_NOACCESS, 6637 &spr_read_generic, &spr_write_generic, 6638 0x00000000); 6639 /* XXX : not implemented */ 6640 spr_register(env, SPR_MSSSR0, "MSSSR0", 6641 SPR_NOACCESS, SPR_NOACCESS, 6642 &spr_read_generic, &spr_write_generic, 6643 0x00000000); 6644 /* XXX : not implemented */ 6645 spr_register(env, SPR_7XX_PMC5, "PMC5", 6646 SPR_NOACCESS, SPR_NOACCESS, 6647 &spr_read_generic, &spr_write_generic, 6648 0x00000000); 6649 /* XXX : not implemented */ 6650 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6651 &spr_read_ureg, SPR_NOACCESS, 6652 &spr_read_ureg, SPR_NOACCESS, 6653 0x00000000); 6654 /* XXX : not implemented */ 6655 spr_register(env, SPR_7XX_PMC6, "PMC6", 6656 SPR_NOACCESS, SPR_NOACCESS, 6657 &spr_read_generic, &spr_write_generic, 6658 0x00000000); 6659 /* XXX : not implemented */ 6660 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6661 &spr_read_ureg, SPR_NOACCESS, 6662 &spr_read_ureg, SPR_NOACCESS, 6663 0x00000000); 6664 /* SPRGs */ 6665 spr_register(env, SPR_SPRG4, "SPRG4", 6666 SPR_NOACCESS, SPR_NOACCESS, 6667 &spr_read_generic, &spr_write_generic, 6668 0x00000000); 6669 spr_register(env, SPR_USPRG4, "USPRG4", 6670 &spr_read_ureg, SPR_NOACCESS, 6671 &spr_read_ureg, SPR_NOACCESS, 6672 0x00000000); 6673 spr_register(env, SPR_SPRG5, "SPRG5", 6674 SPR_NOACCESS, SPR_NOACCESS, 6675 &spr_read_generic, &spr_write_generic, 6676 0x00000000); 6677 spr_register(env, SPR_USPRG5, "USPRG5", 6678 &spr_read_ureg, SPR_NOACCESS, 6679 &spr_read_ureg, SPR_NOACCESS, 6680 0x00000000); 6681 spr_register(env, SPR_SPRG6, "SPRG6", 6682 SPR_NOACCESS, SPR_NOACCESS, 6683 &spr_read_generic, &spr_write_generic, 6684 0x00000000); 6685 spr_register(env, SPR_USPRG6, "USPRG6", 6686 &spr_read_ureg, SPR_NOACCESS, 6687 &spr_read_ureg, SPR_NOACCESS, 6688 0x00000000); 6689 spr_register(env, SPR_SPRG7, "SPRG7", 6690 SPR_NOACCESS, SPR_NOACCESS, 6691 &spr_read_generic, &spr_write_generic, 6692 0x00000000); 6693 spr_register(env, SPR_USPRG7, "USPRG7", 6694 &spr_read_ureg, SPR_NOACCESS, 6695 &spr_read_ureg, SPR_NOACCESS, 6696 0x00000000); 6697 /* Memory management */ 6698 register_low_BATs(env); 6699 register_high_BATs(env); 6700 register_74xx_soft_tlb(env, 128, 2); 6701 init_excp_7450(env); 6702 env->dcache_line_size = 32; 6703 env->icache_line_size = 32; 6704 /* Allocate hardware IRQ controller */ 6705 ppc6xx_irq_init(env_archcpu(env)); 6706 } 6707 6708 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 6709 { 6710 DeviceClass *dc = DEVICE_CLASS(oc); 6711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6712 6713 dc->desc = "PowerPC e600"; 6714 pcc->init_proc = init_proc_e600; 6715 pcc->check_pow = check_pow_hid0_74xx; 6716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6718 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6719 PPC_FLOAT_STFIWX | 6720 PPC_CACHE | PPC_CACHE_ICBI | 6721 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6722 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6723 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6724 PPC_MEM_TLBIA | PPC_74xx_TLB | 6725 PPC_SEGMENT | PPC_EXTERN | 6726 PPC_ALTIVEC; 6727 pcc->insns_flags2 = PPC_NONE; 6728 pcc->msr_mask = (1ull << MSR_VR) | 6729 (1ull << MSR_POW) | 6730 (1ull << MSR_ILE) | 6731 (1ull << MSR_EE) | 6732 (1ull << MSR_PR) | 6733 (1ull << MSR_FP) | 6734 (1ull << MSR_ME) | 6735 (1ull << MSR_FE0) | 6736 (1ull << MSR_SE) | 6737 (1ull << MSR_DE) | 6738 (1ull << MSR_FE1) | 6739 (1ull << MSR_EP) | 6740 (1ull << MSR_IR) | 6741 (1ull << MSR_DR) | 6742 (1ull << MSR_PMM) | 6743 (1ull << MSR_RI) | 6744 (1ull << MSR_LE); 6745 pcc->mmu_model = POWERPC_MMU_32B; 6746 #if defined(CONFIG_SOFTMMU) 6747 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6748 #endif 6749 pcc->excp_model = POWERPC_EXCP_74xx; 6750 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6751 pcc->bfd_mach = bfd_mach_ppc_7400; 6752 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6753 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6754 POWERPC_FLAG_BUS_CLK; 6755 } 6756 6757 #if defined(TARGET_PPC64) 6758 #if defined(CONFIG_USER_ONLY) 6759 #define POWERPC970_HID5_INIT 0x00000080 6760 #else 6761 #define POWERPC970_HID5_INIT 0x00000000 6762 #endif 6763 6764 static int check_pow_970(CPUPPCState *env) 6765 { 6766 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6767 return 1; 6768 } 6769 6770 return 0; 6771 } 6772 6773 static void register_970_hid_sprs(CPUPPCState *env) 6774 { 6775 /* Hardware implementation registers */ 6776 /* XXX : not implemented */ 6777 spr_register(env, SPR_HID0, "HID0", 6778 SPR_NOACCESS, SPR_NOACCESS, 6779 &spr_read_generic, &spr_write_clear, 6780 0x60000000); 6781 spr_register(env, SPR_HID1, "HID1", 6782 SPR_NOACCESS, SPR_NOACCESS, 6783 &spr_read_generic, &spr_write_generic, 6784 0x00000000); 6785 spr_register(env, SPR_970_HID5, "HID5", 6786 SPR_NOACCESS, SPR_NOACCESS, 6787 &spr_read_generic, &spr_write_generic, 6788 POWERPC970_HID5_INIT); 6789 } 6790 6791 static void register_970_hior_sprs(CPUPPCState *env) 6792 { 6793 spr_register(env, SPR_HIOR, "SPR_HIOR", 6794 SPR_NOACCESS, SPR_NOACCESS, 6795 &spr_read_hior, &spr_write_hior, 6796 0x00000000); 6797 } 6798 6799 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6800 { 6801 spr_register(env, SPR_CTRL, "SPR_CTRL", 6802 SPR_NOACCESS, SPR_NOACCESS, 6803 SPR_NOACCESS, &spr_write_generic, 6804 0x00000000); 6805 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6806 &spr_read_ureg, SPR_NOACCESS, 6807 &spr_read_ureg, SPR_NOACCESS, 6808 0x00000000); 6809 } 6810 6811 static void register_book3s_altivec_sprs(CPUPPCState *env) 6812 { 6813 if (!(env->insns_flags & PPC_ALTIVEC)) { 6814 return; 6815 } 6816 6817 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6818 &spr_read_generic, &spr_write_generic, 6819 &spr_read_generic, &spr_write_generic, 6820 KVM_REG_PPC_VRSAVE, 0x00000000); 6821 6822 } 6823 6824 static void register_book3s_dbg_sprs(CPUPPCState *env) 6825 { 6826 /* 6827 * TODO: different specs define different scopes for these, 6828 * will have to address this: 6829 * 970: super/write and super/read 6830 * powerisa 2.03..2.04: hypv/write and super/read. 6831 * powerisa 2.05 and newer: hypv/write and hypv/read. 6832 */ 6833 spr_register_kvm(env, SPR_DABR, "DABR", 6834 SPR_NOACCESS, SPR_NOACCESS, 6835 &spr_read_generic, &spr_write_generic, 6836 KVM_REG_PPC_DABR, 0x00000000); 6837 spr_register_kvm(env, SPR_DABRX, "DABRX", 6838 SPR_NOACCESS, SPR_NOACCESS, 6839 &spr_read_generic, &spr_write_generic, 6840 KVM_REG_PPC_DABRX, 0x00000000); 6841 } 6842 6843 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6844 { 6845 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6846 SPR_NOACCESS, SPR_NOACCESS, 6847 SPR_NOACCESS, SPR_NOACCESS, 6848 &spr_read_generic, &spr_write_generic, 6849 KVM_REG_PPC_DAWR, 0x00000000); 6850 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6851 SPR_NOACCESS, SPR_NOACCESS, 6852 SPR_NOACCESS, SPR_NOACCESS, 6853 &spr_read_generic, &spr_write_generic, 6854 KVM_REG_PPC_DAWRX, 0x00000000); 6855 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6856 SPR_NOACCESS, SPR_NOACCESS, 6857 SPR_NOACCESS, SPR_NOACCESS, 6858 &spr_read_generic, &spr_write_generic, 6859 KVM_REG_PPC_CIABR, 0x00000000); 6860 } 6861 6862 static void register_970_dbg_sprs(CPUPPCState *env) 6863 { 6864 /* Breakpoints */ 6865 spr_register(env, SPR_IABR, "IABR", 6866 SPR_NOACCESS, SPR_NOACCESS, 6867 &spr_read_generic, &spr_write_generic, 6868 0x00000000); 6869 } 6870 6871 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6872 { 6873 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6874 SPR_NOACCESS, SPR_NOACCESS, 6875 &spr_read_generic, &spr_write_generic, 6876 KVM_REG_PPC_MMCR0, 0x00000000); 6877 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6878 SPR_NOACCESS, SPR_NOACCESS, 6879 &spr_read_generic, &spr_write_generic, 6880 KVM_REG_PPC_MMCR1, 0x00000000); 6881 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6882 SPR_NOACCESS, SPR_NOACCESS, 6883 &spr_read_generic, &spr_write_generic, 6884 KVM_REG_PPC_MMCRA, 0x00000000); 6885 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6886 SPR_NOACCESS, SPR_NOACCESS, 6887 &spr_read_generic, &spr_write_generic, 6888 KVM_REG_PPC_PMC1, 0x00000000); 6889 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6890 SPR_NOACCESS, SPR_NOACCESS, 6891 &spr_read_generic, &spr_write_generic, 6892 KVM_REG_PPC_PMC2, 0x00000000); 6893 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6894 SPR_NOACCESS, SPR_NOACCESS, 6895 &spr_read_generic, &spr_write_generic, 6896 KVM_REG_PPC_PMC3, 0x00000000); 6897 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6898 SPR_NOACCESS, SPR_NOACCESS, 6899 &spr_read_generic, &spr_write_generic, 6900 KVM_REG_PPC_PMC4, 0x00000000); 6901 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6902 SPR_NOACCESS, SPR_NOACCESS, 6903 &spr_read_generic, &spr_write_generic, 6904 KVM_REG_PPC_PMC5, 0x00000000); 6905 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6906 SPR_NOACCESS, SPR_NOACCESS, 6907 &spr_read_generic, &spr_write_generic, 6908 KVM_REG_PPC_PMC6, 0x00000000); 6909 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6910 SPR_NOACCESS, SPR_NOACCESS, 6911 &spr_read_generic, &spr_write_generic, 6912 KVM_REG_PPC_SIAR, 0x00000000); 6913 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6914 SPR_NOACCESS, SPR_NOACCESS, 6915 &spr_read_generic, &spr_write_generic, 6916 KVM_REG_PPC_SDAR, 0x00000000); 6917 } 6918 6919 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6920 { 6921 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6922 &spr_read_ureg, SPR_NOACCESS, 6923 &spr_read_ureg, &spr_write_ureg, 6924 0x00000000); 6925 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6926 &spr_read_ureg, SPR_NOACCESS, 6927 &spr_read_ureg, &spr_write_ureg, 6928 0x00000000); 6929 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6930 &spr_read_ureg, SPR_NOACCESS, 6931 &spr_read_ureg, &spr_write_ureg, 6932 0x00000000); 6933 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6934 &spr_read_ureg, SPR_NOACCESS, 6935 &spr_read_ureg, &spr_write_ureg, 6936 0x00000000); 6937 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6938 &spr_read_ureg, SPR_NOACCESS, 6939 &spr_read_ureg, &spr_write_ureg, 6940 0x00000000); 6941 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6942 &spr_read_ureg, SPR_NOACCESS, 6943 &spr_read_ureg, &spr_write_ureg, 6944 0x00000000); 6945 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6946 &spr_read_ureg, SPR_NOACCESS, 6947 &spr_read_ureg, &spr_write_ureg, 6948 0x00000000); 6949 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6950 &spr_read_ureg, SPR_NOACCESS, 6951 &spr_read_ureg, &spr_write_ureg, 6952 0x00000000); 6953 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6954 &spr_read_ureg, SPR_NOACCESS, 6955 &spr_read_ureg, &spr_write_ureg, 6956 0x00000000); 6957 spr_register(env, SPR_POWER_USIAR, "USIAR", 6958 &spr_read_ureg, SPR_NOACCESS, 6959 &spr_read_ureg, &spr_write_ureg, 6960 0x00000000); 6961 spr_register(env, SPR_POWER_USDAR, "USDAR", 6962 &spr_read_ureg, SPR_NOACCESS, 6963 &spr_read_ureg, &spr_write_ureg, 6964 0x00000000); 6965 } 6966 6967 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6968 { 6969 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6970 SPR_NOACCESS, SPR_NOACCESS, 6971 &spr_read_generic, &spr_write_generic, 6972 KVM_REG_PPC_PMC7, 0x00000000); 6973 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6974 SPR_NOACCESS, SPR_NOACCESS, 6975 &spr_read_generic, &spr_write_generic, 6976 KVM_REG_PPC_PMC8, 0x00000000); 6977 } 6978 6979 static void register_970_pmu_user_sprs(CPUPPCState *env) 6980 { 6981 spr_register(env, SPR_970_UPMC7, "UPMC7", 6982 &spr_read_ureg, SPR_NOACCESS, 6983 &spr_read_ureg, &spr_write_ureg, 6984 0x00000000); 6985 spr_register(env, SPR_970_UPMC8, "UPMC8", 6986 &spr_read_ureg, SPR_NOACCESS, 6987 &spr_read_ureg, &spr_write_ureg, 6988 0x00000000); 6989 } 6990 6991 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6992 { 6993 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6994 SPR_NOACCESS, SPR_NOACCESS, 6995 &spr_read_generic, &spr_write_generic, 6996 KVM_REG_PPC_MMCR2, 0x00000000); 6997 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6998 SPR_NOACCESS, SPR_NOACCESS, 6999 &spr_read_generic, &spr_write_generic, 7000 KVM_REG_PPC_MMCRS, 0x00000000); 7001 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 7002 SPR_NOACCESS, SPR_NOACCESS, 7003 &spr_read_generic, &spr_write_generic, 7004 KVM_REG_PPC_SIER, 0x00000000); 7005 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 7006 SPR_NOACCESS, SPR_NOACCESS, 7007 &spr_read_generic, &spr_write_generic, 7008 KVM_REG_PPC_SPMC1, 0x00000000); 7009 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 7010 SPR_NOACCESS, SPR_NOACCESS, 7011 &spr_read_generic, &spr_write_generic, 7012 KVM_REG_PPC_SPMC2, 0x00000000); 7013 spr_register_kvm(env, SPR_TACR, "TACR", 7014 SPR_NOACCESS, SPR_NOACCESS, 7015 &spr_read_generic, &spr_write_generic, 7016 KVM_REG_PPC_TACR, 0x00000000); 7017 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 7018 SPR_NOACCESS, SPR_NOACCESS, 7019 &spr_read_generic, &spr_write_generic, 7020 KVM_REG_PPC_TCSCR, 0x00000000); 7021 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 7022 SPR_NOACCESS, SPR_NOACCESS, 7023 &spr_read_generic, &spr_write_generic, 7024 KVM_REG_PPC_CSIGR, 0x00000000); 7025 } 7026 7027 static void register_power8_pmu_user_sprs(CPUPPCState *env) 7028 { 7029 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 7030 &spr_read_ureg, SPR_NOACCESS, 7031 &spr_read_ureg, &spr_write_ureg, 7032 0x00000000); 7033 spr_register(env, SPR_POWER_USIER, "USIER", 7034 &spr_read_generic, SPR_NOACCESS, 7035 &spr_read_generic, &spr_write_generic, 7036 0x00000000); 7037 } 7038 7039 static void register_power5p_ear_sprs(CPUPPCState *env) 7040 { 7041 /* External access control */ 7042 spr_register(env, SPR_EAR, "EAR", 7043 SPR_NOACCESS, SPR_NOACCESS, 7044 &spr_read_generic, &spr_write_generic, 7045 0x00000000); 7046 } 7047 7048 static void register_power5p_tb_sprs(CPUPPCState *env) 7049 { 7050 /* TBU40 (High 40 bits of the Timebase register */ 7051 spr_register_hv(env, SPR_TBU40, "TBU40", 7052 SPR_NOACCESS, SPR_NOACCESS, 7053 SPR_NOACCESS, SPR_NOACCESS, 7054 SPR_NOACCESS, &spr_write_tbu40, 7055 0x00000000); 7056 } 7057 7058 static void register_970_lpar_sprs(CPUPPCState *env) 7059 { 7060 #if !defined(CONFIG_USER_ONLY) 7061 /* 7062 * PPC970: HID4 covers things later controlled by the LPCR and 7063 * RMOR in later CPUs, but with a different encoding. We only 7064 * support the 970 in "Apple mode" which has all hypervisor 7065 * facilities disabled by strapping, so we can basically just 7066 * ignore it 7067 */ 7068 spr_register(env, SPR_970_HID4, "HID4", 7069 SPR_NOACCESS, SPR_NOACCESS, 7070 &spr_read_generic, &spr_write_generic, 7071 0x00000000); 7072 #endif 7073 } 7074 7075 static void register_power5p_lpar_sprs(CPUPPCState *env) 7076 { 7077 #if !defined(CONFIG_USER_ONLY) 7078 /* Logical partitionning */ 7079 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 7080 SPR_NOACCESS, SPR_NOACCESS, 7081 SPR_NOACCESS, SPR_NOACCESS, 7082 &spr_read_generic, &spr_write_lpcr, 7083 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 7084 spr_register_hv(env, SPR_HDEC, "HDEC", 7085 SPR_NOACCESS, SPR_NOACCESS, 7086 SPR_NOACCESS, SPR_NOACCESS, 7087 &spr_read_hdecr, &spr_write_hdecr, 0); 7088 #endif 7089 } 7090 7091 static void register_book3s_ids_sprs(CPUPPCState *env) 7092 { 7093 /* FIXME: Will need to deal with thread vs core only SPRs */ 7094 7095 /* Processor identification */ 7096 spr_register_hv(env, SPR_PIR, "PIR", 7097 SPR_NOACCESS, SPR_NOACCESS, 7098 &spr_read_generic, SPR_NOACCESS, 7099 &spr_read_generic, NULL, 7100 0x00000000); 7101 spr_register_hv(env, SPR_HID0, "HID0", 7102 SPR_NOACCESS, SPR_NOACCESS, 7103 SPR_NOACCESS, SPR_NOACCESS, 7104 &spr_read_generic, &spr_write_generic, 7105 0x00000000); 7106 spr_register_hv(env, SPR_TSCR, "TSCR", 7107 SPR_NOACCESS, SPR_NOACCESS, 7108 SPR_NOACCESS, SPR_NOACCESS, 7109 &spr_read_generic, &spr_write_generic, 7110 0x00000000); 7111 spr_register_hv(env, SPR_HMER, "HMER", 7112 SPR_NOACCESS, SPR_NOACCESS, 7113 SPR_NOACCESS, SPR_NOACCESS, 7114 &spr_read_generic, &spr_write_hmer, 7115 0x00000000); 7116 spr_register_hv(env, SPR_HMEER, "HMEER", 7117 SPR_NOACCESS, SPR_NOACCESS, 7118 SPR_NOACCESS, SPR_NOACCESS, 7119 &spr_read_generic, &spr_write_generic, 7120 0x00000000); 7121 spr_register_hv(env, SPR_TFMR, "TFMR", 7122 SPR_NOACCESS, SPR_NOACCESS, 7123 SPR_NOACCESS, SPR_NOACCESS, 7124 &spr_read_generic, &spr_write_generic, 7125 0x00000000); 7126 spr_register_hv(env, SPR_LPIDR, "LPIDR", 7127 SPR_NOACCESS, SPR_NOACCESS, 7128 SPR_NOACCESS, SPR_NOACCESS, 7129 &spr_read_generic, &spr_write_lpidr, 7130 0x00000000); 7131 spr_register_hv(env, SPR_HFSCR, "HFSCR", 7132 SPR_NOACCESS, SPR_NOACCESS, 7133 SPR_NOACCESS, SPR_NOACCESS, 7134 &spr_read_generic, &spr_write_generic, 7135 0x00000000); 7136 spr_register_hv(env, SPR_MMCRC, "MMCRC", 7137 SPR_NOACCESS, SPR_NOACCESS, 7138 SPR_NOACCESS, SPR_NOACCESS, 7139 &spr_read_generic, &spr_write_generic, 7140 0x00000000); 7141 spr_register_hv(env, SPR_MMCRH, "MMCRH", 7142 SPR_NOACCESS, SPR_NOACCESS, 7143 SPR_NOACCESS, SPR_NOACCESS, 7144 &spr_read_generic, &spr_write_generic, 7145 0x00000000); 7146 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 7147 SPR_NOACCESS, SPR_NOACCESS, 7148 SPR_NOACCESS, SPR_NOACCESS, 7149 &spr_read_generic, &spr_write_generic, 7150 0x00000000); 7151 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 7152 SPR_NOACCESS, SPR_NOACCESS, 7153 SPR_NOACCESS, SPR_NOACCESS, 7154 &spr_read_generic, &spr_write_generic, 7155 0x00000000); 7156 spr_register_hv(env, SPR_HSRR0, "HSRR0", 7157 SPR_NOACCESS, SPR_NOACCESS, 7158 SPR_NOACCESS, SPR_NOACCESS, 7159 &spr_read_generic, &spr_write_generic, 7160 0x00000000); 7161 spr_register_hv(env, SPR_HSRR1, "HSRR1", 7162 SPR_NOACCESS, SPR_NOACCESS, 7163 SPR_NOACCESS, SPR_NOACCESS, 7164 &spr_read_generic, &spr_write_generic, 7165 0x00000000); 7166 spr_register_hv(env, SPR_HDAR, "HDAR", 7167 SPR_NOACCESS, SPR_NOACCESS, 7168 SPR_NOACCESS, SPR_NOACCESS, 7169 &spr_read_generic, &spr_write_generic, 7170 0x00000000); 7171 spr_register_hv(env, SPR_HDSISR, "HDSISR", 7172 SPR_NOACCESS, SPR_NOACCESS, 7173 SPR_NOACCESS, SPR_NOACCESS, 7174 &spr_read_generic, &spr_write_generic, 7175 0x00000000); 7176 spr_register_hv(env, SPR_HRMOR, "HRMOR", 7177 SPR_NOACCESS, SPR_NOACCESS, 7178 SPR_NOACCESS, SPR_NOACCESS, 7179 &spr_read_generic, &spr_write_generic, 7180 0x00000000); 7181 } 7182 7183 static void register_rmor_sprs(CPUPPCState *env) 7184 { 7185 spr_register_hv(env, SPR_RMOR, "RMOR", 7186 SPR_NOACCESS, SPR_NOACCESS, 7187 SPR_NOACCESS, SPR_NOACCESS, 7188 &spr_read_generic, &spr_write_generic, 7189 0x00000000); 7190 } 7191 7192 static void register_power8_ids_sprs(CPUPPCState *env) 7193 { 7194 /* Thread identification */ 7195 spr_register(env, SPR_TIR, "TIR", 7196 SPR_NOACCESS, SPR_NOACCESS, 7197 &spr_read_generic, SPR_NOACCESS, 7198 0x00000000); 7199 } 7200 7201 static void register_book3s_purr_sprs(CPUPPCState *env) 7202 { 7203 #if !defined(CONFIG_USER_ONLY) 7204 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 7205 spr_register_kvm_hv(env, SPR_PURR, "PURR", 7206 &spr_read_purr, SPR_NOACCESS, 7207 &spr_read_purr, SPR_NOACCESS, 7208 &spr_read_purr, &spr_write_purr, 7209 KVM_REG_PPC_PURR, 0x00000000); 7210 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 7211 &spr_read_purr, SPR_NOACCESS, 7212 &spr_read_purr, SPR_NOACCESS, 7213 &spr_read_purr, &spr_write_purr, 7214 KVM_REG_PPC_SPURR, 0x00000000); 7215 #endif 7216 } 7217 7218 static void register_power6_dbg_sprs(CPUPPCState *env) 7219 { 7220 #if !defined(CONFIG_USER_ONLY) 7221 spr_register(env, SPR_CFAR, "SPR_CFAR", 7222 SPR_NOACCESS, SPR_NOACCESS, 7223 &spr_read_cfar, &spr_write_cfar, 7224 0x00000000); 7225 #endif 7226 } 7227 7228 static void register_power5p_common_sprs(CPUPPCState *env) 7229 { 7230 spr_register_kvm(env, SPR_PPR, "PPR", 7231 &spr_read_generic, &spr_write_generic, 7232 &spr_read_generic, &spr_write_generic, 7233 KVM_REG_PPC_PPR, 0x00000000); 7234 } 7235 7236 static void register_power6_common_sprs(CPUPPCState *env) 7237 { 7238 #if !defined(CONFIG_USER_ONLY) 7239 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 7240 SPR_NOACCESS, SPR_NOACCESS, 7241 &spr_read_generic, &spr_write_generic, 7242 KVM_REG_PPC_DSCR, 0x00000000); 7243 #endif 7244 /* 7245 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 7246 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 7247 */ 7248 spr_register_hv(env, SPR_PCR, "PCR", 7249 SPR_NOACCESS, SPR_NOACCESS, 7250 SPR_NOACCESS, SPR_NOACCESS, 7251 &spr_read_generic, &spr_write_pcr, 7252 0x00000000); 7253 } 7254 7255 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 7256 { 7257 spr_register_kvm(env, SPR_TAR, "TAR", 7258 &spr_read_tar, &spr_write_tar, 7259 &spr_read_generic, &spr_write_generic, 7260 KVM_REG_PPC_TAR, 0x00000000); 7261 } 7262 7263 static void register_power8_tm_sprs(CPUPPCState *env) 7264 { 7265 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 7266 &spr_read_tm, &spr_write_tm, 7267 &spr_read_tm, &spr_write_tm, 7268 KVM_REG_PPC_TFHAR, 0x00000000); 7269 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 7270 &spr_read_tm, &spr_write_tm, 7271 &spr_read_tm, &spr_write_tm, 7272 KVM_REG_PPC_TFIAR, 0x00000000); 7273 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 7274 &spr_read_tm, &spr_write_tm, 7275 &spr_read_tm, &spr_write_tm, 7276 KVM_REG_PPC_TEXASR, 0x00000000); 7277 spr_register(env, SPR_TEXASRU, "TEXASRU", 7278 &spr_read_tm_upper32, &spr_write_tm_upper32, 7279 &spr_read_tm_upper32, &spr_write_tm_upper32, 7280 0x00000000); 7281 } 7282 7283 static void register_power8_ebb_sprs(CPUPPCState *env) 7284 { 7285 spr_register(env, SPR_BESCRS, "BESCRS", 7286 &spr_read_ebb, &spr_write_ebb, 7287 &spr_read_generic, &spr_write_generic, 7288 0x00000000); 7289 spr_register(env, SPR_BESCRSU, "BESCRSU", 7290 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7291 &spr_read_prev_upper32, &spr_write_prev_upper32, 7292 0x00000000); 7293 spr_register(env, SPR_BESCRR, "BESCRR", 7294 &spr_read_ebb, &spr_write_ebb, 7295 &spr_read_generic, &spr_write_generic, 7296 0x00000000); 7297 spr_register(env, SPR_BESCRRU, "BESCRRU", 7298 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7299 &spr_read_prev_upper32, &spr_write_prev_upper32, 7300 0x00000000); 7301 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 7302 &spr_read_ebb, &spr_write_ebb, 7303 &spr_read_generic, &spr_write_generic, 7304 KVM_REG_PPC_EBBHR, 0x00000000); 7305 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 7306 &spr_read_ebb, &spr_write_ebb, 7307 &spr_read_generic, &spr_write_generic, 7308 KVM_REG_PPC_EBBRR, 0x00000000); 7309 spr_register_kvm(env, SPR_BESCR, "BESCR", 7310 &spr_read_ebb, &spr_write_ebb, 7311 &spr_read_generic, &spr_write_generic, 7312 KVM_REG_PPC_BESCR, 0x00000000); 7313 } 7314 7315 /* Virtual Time Base */ 7316 static void register_vtb_sprs(CPUPPCState *env) 7317 { 7318 spr_register_kvm_hv(env, SPR_VTB, "VTB", 7319 SPR_NOACCESS, SPR_NOACCESS, 7320 &spr_read_vtb, SPR_NOACCESS, 7321 &spr_read_vtb, &spr_write_vtb, 7322 KVM_REG_PPC_VTB, 0x00000000); 7323 } 7324 7325 static void register_power8_fscr_sprs(CPUPPCState *env) 7326 { 7327 #if defined(CONFIG_USER_ONLY) 7328 target_ulong initval = 1ULL << FSCR_TAR; 7329 #else 7330 target_ulong initval = 0; 7331 #endif 7332 spr_register_kvm(env, SPR_FSCR, "FSCR", 7333 SPR_NOACCESS, SPR_NOACCESS, 7334 &spr_read_generic, &spr_write_generic, 7335 KVM_REG_PPC_FSCR, initval); 7336 } 7337 7338 static void register_power8_pspb_sprs(CPUPPCState *env) 7339 { 7340 spr_register_kvm(env, SPR_PSPB, "PSPB", 7341 SPR_NOACCESS, SPR_NOACCESS, 7342 &spr_read_generic, &spr_write_generic32, 7343 KVM_REG_PPC_PSPB, 0); 7344 } 7345 7346 static void register_power8_dpdes_sprs(CPUPPCState *env) 7347 { 7348 #if !defined(CONFIG_USER_ONLY) 7349 /* Directed Privileged Door-bell Exception State, used for IPI */ 7350 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 7351 SPR_NOACCESS, SPR_NOACCESS, 7352 &spr_read_dpdes, SPR_NOACCESS, 7353 &spr_read_dpdes, &spr_write_dpdes, 7354 KVM_REG_PPC_DPDES, 0x00000000); 7355 #endif 7356 } 7357 7358 static void register_power8_ic_sprs(CPUPPCState *env) 7359 { 7360 #if !defined(CONFIG_USER_ONLY) 7361 spr_register_hv(env, SPR_IC, "IC", 7362 SPR_NOACCESS, SPR_NOACCESS, 7363 &spr_read_generic, SPR_NOACCESS, 7364 &spr_read_generic, &spr_write_generic, 7365 0); 7366 #endif 7367 } 7368 7369 static void register_power8_book4_sprs(CPUPPCState *env) 7370 { 7371 /* Add a number of P8 book4 registers */ 7372 #if !defined(CONFIG_USER_ONLY) 7373 spr_register_kvm(env, SPR_ACOP, "ACOP", 7374 SPR_NOACCESS, SPR_NOACCESS, 7375 &spr_read_generic, &spr_write_generic, 7376 KVM_REG_PPC_ACOP, 0); 7377 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7378 SPR_NOACCESS, SPR_NOACCESS, 7379 &spr_read_generic, &spr_write_pidr, 7380 KVM_REG_PPC_PID, 0); 7381 spr_register_kvm(env, SPR_WORT, "WORT", 7382 SPR_NOACCESS, SPR_NOACCESS, 7383 &spr_read_generic, &spr_write_generic, 7384 KVM_REG_PPC_WORT, 0); 7385 #endif 7386 } 7387 7388 static void register_power7_book4_sprs(CPUPPCState *env) 7389 { 7390 /* Add a number of P7 book4 registers */ 7391 #if !defined(CONFIG_USER_ONLY) 7392 spr_register_kvm(env, SPR_ACOP, "ACOP", 7393 SPR_NOACCESS, SPR_NOACCESS, 7394 &spr_read_generic, &spr_write_generic, 7395 KVM_REG_PPC_ACOP, 0); 7396 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7397 SPR_NOACCESS, SPR_NOACCESS, 7398 &spr_read_generic, &spr_write_generic, 7399 KVM_REG_PPC_PID, 0); 7400 #endif 7401 } 7402 7403 static void register_power8_rpr_sprs(CPUPPCState *env) 7404 { 7405 #if !defined(CONFIG_USER_ONLY) 7406 spr_register_hv(env, SPR_RPR, "RPR", 7407 SPR_NOACCESS, SPR_NOACCESS, 7408 SPR_NOACCESS, SPR_NOACCESS, 7409 &spr_read_generic, &spr_write_generic, 7410 0x00000103070F1F3F); 7411 #endif 7412 } 7413 7414 static void register_power9_mmu_sprs(CPUPPCState *env) 7415 { 7416 #if !defined(CONFIG_USER_ONLY) 7417 /* Partition Table Control */ 7418 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 7419 SPR_NOACCESS, SPR_NOACCESS, 7420 SPR_NOACCESS, SPR_NOACCESS, 7421 &spr_read_generic, &spr_write_ptcr, 7422 KVM_REG_PPC_PTCR, 0x00000000); 7423 /* Address Segment Descriptor Register */ 7424 spr_register_hv(env, SPR_ASDR, "ASDR", 7425 SPR_NOACCESS, SPR_NOACCESS, 7426 SPR_NOACCESS, SPR_NOACCESS, 7427 &spr_read_generic, &spr_write_generic, 7428 0x0000000000000000); 7429 #endif 7430 } 7431 7432 static void init_proc_book3s_common(CPUPPCState *env) 7433 { 7434 register_ne_601_sprs(env); 7435 register_tbl(env); 7436 register_usprg3_sprs(env); 7437 register_book3s_altivec_sprs(env); 7438 register_book3s_pmu_sup_sprs(env); 7439 register_book3s_pmu_user_sprs(env); 7440 register_book3s_ctrl_sprs(env); 7441 /* 7442 * Can't find information on what this should be on reset. This 7443 * value is the one used by 74xx processors. 7444 */ 7445 vscr_init(env, 0x00010000); 7446 } 7447 7448 static void init_proc_970(CPUPPCState *env) 7449 { 7450 /* Common Registers */ 7451 init_proc_book3s_common(env); 7452 register_sdr1_sprs(env); 7453 register_book3s_dbg_sprs(env); 7454 7455 /* 970 Specific Registers */ 7456 register_970_hid_sprs(env); 7457 register_970_hior_sprs(env); 7458 register_low_BATs(env); 7459 register_970_pmu_sup_sprs(env); 7460 register_970_pmu_user_sprs(env); 7461 register_970_lpar_sprs(env); 7462 register_970_dbg_sprs(env); 7463 7464 /* env variables */ 7465 env->dcache_line_size = 128; 7466 env->icache_line_size = 128; 7467 7468 /* Allocate hardware IRQ controller */ 7469 init_excp_970(env); 7470 ppc970_irq_init(env_archcpu(env)); 7471 } 7472 7473 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 7474 { 7475 DeviceClass *dc = DEVICE_CLASS(oc); 7476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7477 7478 dc->desc = "PowerPC 970"; 7479 pcc->init_proc = init_proc_970; 7480 pcc->check_pow = check_pow_970; 7481 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7483 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7484 PPC_FLOAT_STFIWX | 7485 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7486 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7487 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7488 PPC_64B | PPC_ALTIVEC | 7489 PPC_SEGMENT_64B | PPC_SLBI; 7490 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7491 pcc->msr_mask = (1ull << MSR_SF) | 7492 (1ull << MSR_VR) | 7493 (1ull << MSR_POW) | 7494 (1ull << MSR_EE) | 7495 (1ull << MSR_PR) | 7496 (1ull << MSR_FP) | 7497 (1ull << MSR_ME) | 7498 (1ull << MSR_FE0) | 7499 (1ull << MSR_SE) | 7500 (1ull << MSR_DE) | 7501 (1ull << MSR_FE1) | 7502 (1ull << MSR_IR) | 7503 (1ull << MSR_DR) | 7504 (1ull << MSR_PMM) | 7505 (1ull << MSR_RI); 7506 pcc->mmu_model = POWERPC_MMU_64B; 7507 #if defined(CONFIG_SOFTMMU) 7508 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7509 pcc->hash64_opts = &ppc_hash64_opts_basic; 7510 #endif 7511 pcc->excp_model = POWERPC_EXCP_970; 7512 pcc->bus_model = PPC_FLAGS_INPUT_970; 7513 pcc->bfd_mach = bfd_mach_ppc64; 7514 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7515 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7516 POWERPC_FLAG_BUS_CLK; 7517 pcc->l1_dcache_size = 0x8000; 7518 pcc->l1_icache_size = 0x10000; 7519 } 7520 7521 static void init_proc_power5plus(CPUPPCState *env) 7522 { 7523 /* Common Registers */ 7524 init_proc_book3s_common(env); 7525 register_sdr1_sprs(env); 7526 register_book3s_dbg_sprs(env); 7527 7528 /* POWER5+ Specific Registers */ 7529 register_970_hid_sprs(env); 7530 register_970_hior_sprs(env); 7531 register_low_BATs(env); 7532 register_970_pmu_sup_sprs(env); 7533 register_970_pmu_user_sprs(env); 7534 register_power5p_common_sprs(env); 7535 register_power5p_lpar_sprs(env); 7536 register_power5p_ear_sprs(env); 7537 register_power5p_tb_sprs(env); 7538 7539 /* env variables */ 7540 env->dcache_line_size = 128; 7541 env->icache_line_size = 128; 7542 7543 /* Allocate hardware IRQ controller */ 7544 init_excp_970(env); 7545 ppc970_irq_init(env_archcpu(env)); 7546 } 7547 7548 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 7549 { 7550 DeviceClass *dc = DEVICE_CLASS(oc); 7551 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7552 7553 dc->fw_name = "PowerPC,POWER5"; 7554 dc->desc = "POWER5+"; 7555 pcc->init_proc = init_proc_power5plus; 7556 pcc->check_pow = check_pow_970; 7557 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7558 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7559 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7560 PPC_FLOAT_STFIWX | 7561 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7562 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7563 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7564 PPC_64B | 7565 PPC_SEGMENT_64B | PPC_SLBI; 7566 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7567 pcc->msr_mask = (1ull << MSR_SF) | 7568 (1ull << MSR_VR) | 7569 (1ull << MSR_POW) | 7570 (1ull << MSR_EE) | 7571 (1ull << MSR_PR) | 7572 (1ull << MSR_FP) | 7573 (1ull << MSR_ME) | 7574 (1ull << MSR_FE0) | 7575 (1ull << MSR_SE) | 7576 (1ull << MSR_DE) | 7577 (1ull << MSR_FE1) | 7578 (1ull << MSR_IR) | 7579 (1ull << MSR_DR) | 7580 (1ull << MSR_PMM) | 7581 (1ull << MSR_RI); 7582 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 7583 LPCR_RMI | LPCR_HDICE; 7584 pcc->mmu_model = POWERPC_MMU_2_03; 7585 #if defined(CONFIG_SOFTMMU) 7586 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7587 pcc->hash64_opts = &ppc_hash64_opts_basic; 7588 pcc->lrg_decr_bits = 32; 7589 #endif 7590 pcc->excp_model = POWERPC_EXCP_970; 7591 pcc->bus_model = PPC_FLAGS_INPUT_970; 7592 pcc->bfd_mach = bfd_mach_ppc64; 7593 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7594 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7595 POWERPC_FLAG_BUS_CLK; 7596 pcc->l1_dcache_size = 0x8000; 7597 pcc->l1_icache_size = 0x10000; 7598 } 7599 7600 static void init_proc_POWER7(CPUPPCState *env) 7601 { 7602 /* Common Registers */ 7603 init_proc_book3s_common(env); 7604 register_sdr1_sprs(env); 7605 register_book3s_dbg_sprs(env); 7606 7607 /* POWER7 Specific Registers */ 7608 register_book3s_ids_sprs(env); 7609 register_rmor_sprs(env); 7610 register_amr_sprs(env); 7611 register_book3s_purr_sprs(env); 7612 register_power5p_common_sprs(env); 7613 register_power5p_lpar_sprs(env); 7614 register_power5p_ear_sprs(env); 7615 register_power5p_tb_sprs(env); 7616 register_power6_common_sprs(env); 7617 register_power6_dbg_sprs(env); 7618 register_power7_book4_sprs(env); 7619 7620 /* env variables */ 7621 env->dcache_line_size = 128; 7622 env->icache_line_size = 128; 7623 7624 /* Allocate hardware IRQ controller */ 7625 init_excp_POWER7(env); 7626 ppcPOWER7_irq_init(env_archcpu(env)); 7627 } 7628 7629 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 7630 { 7631 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 7632 return true; 7633 } 7634 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 7635 return true; 7636 } 7637 return false; 7638 } 7639 7640 static bool cpu_has_work_POWER7(CPUState *cs) 7641 { 7642 PowerPCCPU *cpu = POWERPC_CPU(cs); 7643 CPUPPCState *env = &cpu->env; 7644 7645 if (cs->halted) { 7646 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7647 return false; 7648 } 7649 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7650 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 7651 return true; 7652 } 7653 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7654 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 7655 return true; 7656 } 7657 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7658 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7659 return true; 7660 } 7661 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7662 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7663 return true; 7664 } 7665 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7666 return true; 7667 } 7668 return false; 7669 } else { 7670 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7671 } 7672 } 7673 7674 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 7675 { 7676 DeviceClass *dc = DEVICE_CLASS(oc); 7677 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7678 CPUClass *cc = CPU_CLASS(oc); 7679 7680 dc->fw_name = "PowerPC,POWER7"; 7681 dc->desc = "POWER7"; 7682 pcc->pvr_match = ppc_pvr_match_power7; 7683 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 7684 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7685 pcc->init_proc = init_proc_POWER7; 7686 pcc->check_pow = check_pow_nocheck; 7687 cc->has_work = cpu_has_work_POWER7; 7688 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7689 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7690 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7691 PPC_FLOAT_FRSQRTES | 7692 PPC_FLOAT_STFIWX | 7693 PPC_FLOAT_EXT | 7694 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7695 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7696 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7697 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7698 PPC_SEGMENT_64B | PPC_SLBI | 7699 PPC_POPCNTB | PPC_POPCNTWD | 7700 PPC_CILDST; 7701 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 7702 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7703 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7704 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 7705 PPC2_PM_ISA206; 7706 pcc->msr_mask = (1ull << MSR_SF) | 7707 (1ull << MSR_VR) | 7708 (1ull << MSR_VSX) | 7709 (1ull << MSR_EE) | 7710 (1ull << MSR_PR) | 7711 (1ull << MSR_FP) | 7712 (1ull << MSR_ME) | 7713 (1ull << MSR_FE0) | 7714 (1ull << MSR_SE) | 7715 (1ull << MSR_DE) | 7716 (1ull << MSR_FE1) | 7717 (1ull << MSR_IR) | 7718 (1ull << MSR_DR) | 7719 (1ull << MSR_PMM) | 7720 (1ull << MSR_RI) | 7721 (1ull << MSR_LE); 7722 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 7723 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7724 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 7725 LPCR_MER | LPCR_TC | 7726 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 7727 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 7728 pcc->mmu_model = POWERPC_MMU_2_06; 7729 #if defined(CONFIG_SOFTMMU) 7730 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7731 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7732 pcc->lrg_decr_bits = 32; 7733 #endif 7734 pcc->excp_model = POWERPC_EXCP_POWER7; 7735 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7736 pcc->bfd_mach = bfd_mach_ppc64; 7737 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7738 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7739 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7740 POWERPC_FLAG_VSX; 7741 pcc->l1_dcache_size = 0x8000; 7742 pcc->l1_icache_size = 0x8000; 7743 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 7744 } 7745 7746 static void init_proc_POWER8(CPUPPCState *env) 7747 { 7748 /* Common Registers */ 7749 init_proc_book3s_common(env); 7750 register_sdr1_sprs(env); 7751 register_book3s_207_dbg_sprs(env); 7752 7753 /* POWER8 Specific Registers */ 7754 register_book3s_ids_sprs(env); 7755 register_rmor_sprs(env); 7756 register_amr_sprs(env); 7757 register_iamr_sprs(env); 7758 register_book3s_purr_sprs(env); 7759 register_power5p_common_sprs(env); 7760 register_power5p_lpar_sprs(env); 7761 register_power5p_ear_sprs(env); 7762 register_power5p_tb_sprs(env); 7763 register_power6_common_sprs(env); 7764 register_power6_dbg_sprs(env); 7765 register_power8_tce_address_control_sprs(env); 7766 register_power8_ids_sprs(env); 7767 register_power8_ebb_sprs(env); 7768 register_power8_fscr_sprs(env); 7769 register_power8_pmu_sup_sprs(env); 7770 register_power8_pmu_user_sprs(env); 7771 register_power8_tm_sprs(env); 7772 register_power8_pspb_sprs(env); 7773 register_power8_dpdes_sprs(env); 7774 register_vtb_sprs(env); 7775 register_power8_ic_sprs(env); 7776 register_power8_book4_sprs(env); 7777 register_power8_rpr_sprs(env); 7778 7779 /* env variables */ 7780 env->dcache_line_size = 128; 7781 env->icache_line_size = 128; 7782 7783 /* Allocate hardware IRQ controller */ 7784 init_excp_POWER8(env); 7785 ppcPOWER7_irq_init(env_archcpu(env)); 7786 } 7787 7788 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7789 { 7790 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7791 return true; 7792 } 7793 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7794 return true; 7795 } 7796 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7797 return true; 7798 } 7799 return false; 7800 } 7801 7802 static bool cpu_has_work_POWER8(CPUState *cs) 7803 { 7804 PowerPCCPU *cpu = POWERPC_CPU(cs); 7805 CPUPPCState *env = &cpu->env; 7806 7807 if (cs->halted) { 7808 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7809 return false; 7810 } 7811 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7812 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7813 return true; 7814 } 7815 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7816 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7817 return true; 7818 } 7819 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7820 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7821 return true; 7822 } 7823 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7824 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7825 return true; 7826 } 7827 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7828 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7829 return true; 7830 } 7831 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7832 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7833 return true; 7834 } 7835 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7836 return true; 7837 } 7838 return false; 7839 } else { 7840 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7841 } 7842 } 7843 7844 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7845 { 7846 DeviceClass *dc = DEVICE_CLASS(oc); 7847 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7848 CPUClass *cc = CPU_CLASS(oc); 7849 7850 dc->fw_name = "PowerPC,POWER8"; 7851 dc->desc = "POWER8"; 7852 pcc->pvr_match = ppc_pvr_match_power8; 7853 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7854 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7855 pcc->init_proc = init_proc_POWER8; 7856 pcc->check_pow = check_pow_nocheck; 7857 cc->has_work = cpu_has_work_POWER8; 7858 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7859 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7860 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7861 PPC_FLOAT_FRSQRTES | 7862 PPC_FLOAT_STFIWX | 7863 PPC_FLOAT_EXT | 7864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7865 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7867 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7868 PPC_SEGMENT_64B | PPC_SLBI | 7869 PPC_POPCNTB | PPC_POPCNTWD | 7870 PPC_CILDST; 7871 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7872 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7873 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7874 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7875 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7876 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7877 PPC2_TM | PPC2_PM_ISA206; 7878 pcc->msr_mask = (1ull << MSR_SF) | 7879 (1ull << MSR_HV) | 7880 (1ull << MSR_TM) | 7881 (1ull << MSR_VR) | 7882 (1ull << MSR_VSX) | 7883 (1ull << MSR_EE) | 7884 (1ull << MSR_PR) | 7885 (1ull << MSR_FP) | 7886 (1ull << MSR_ME) | 7887 (1ull << MSR_FE0) | 7888 (1ull << MSR_SE) | 7889 (1ull << MSR_DE) | 7890 (1ull << MSR_FE1) | 7891 (1ull << MSR_IR) | 7892 (1ull << MSR_DR) | 7893 (1ull << MSR_PMM) | 7894 (1ull << MSR_RI) | 7895 (1ull << MSR_TS0) | 7896 (1ull << MSR_TS1) | 7897 (1ull << MSR_LE); 7898 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7899 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7900 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7901 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7902 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7903 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7904 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7905 pcc->mmu_model = POWERPC_MMU_2_07; 7906 #if defined(CONFIG_SOFTMMU) 7907 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7908 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7909 pcc->lrg_decr_bits = 32; 7910 pcc->n_host_threads = 8; 7911 #endif 7912 pcc->excp_model = POWERPC_EXCP_POWER8; 7913 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7914 pcc->bfd_mach = bfd_mach_ppc64; 7915 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7916 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7917 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7918 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7919 pcc->l1_dcache_size = 0x8000; 7920 pcc->l1_icache_size = 0x8000; 7921 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 7922 } 7923 7924 #ifdef CONFIG_SOFTMMU 7925 /* 7926 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7927 * Encoded as array of int_32s in the form: 7928 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7929 * x -> AP encoding 7930 * y -> radix mode supported page size (encoded as a shift) 7931 */ 7932 static struct ppc_radix_page_info POWER9_radix_page_info = { 7933 .count = 4, 7934 .entries = { 7935 0x0000000c, /* 4K - enc: 0x0 */ 7936 0xa0000010, /* 64K - enc: 0x5 */ 7937 0x20000015, /* 2M - enc: 0x1 */ 7938 0x4000001e /* 1G - enc: 0x2 */ 7939 } 7940 }; 7941 #endif /* CONFIG_SOFTMMU */ 7942 7943 static void init_proc_POWER9(CPUPPCState *env) 7944 { 7945 /* Common Registers */ 7946 init_proc_book3s_common(env); 7947 register_book3s_207_dbg_sprs(env); 7948 7949 /* POWER8 Specific Registers */ 7950 register_book3s_ids_sprs(env); 7951 register_amr_sprs(env); 7952 register_iamr_sprs(env); 7953 register_book3s_purr_sprs(env); 7954 register_power5p_common_sprs(env); 7955 register_power5p_lpar_sprs(env); 7956 register_power5p_ear_sprs(env); 7957 register_power5p_tb_sprs(env); 7958 register_power6_common_sprs(env); 7959 register_power6_dbg_sprs(env); 7960 register_power8_tce_address_control_sprs(env); 7961 register_power8_ids_sprs(env); 7962 register_power8_ebb_sprs(env); 7963 register_power8_fscr_sprs(env); 7964 register_power8_pmu_sup_sprs(env); 7965 register_power8_pmu_user_sprs(env); 7966 register_power8_tm_sprs(env); 7967 register_power8_pspb_sprs(env); 7968 register_power8_dpdes_sprs(env); 7969 register_vtb_sprs(env); 7970 register_power8_ic_sprs(env); 7971 register_power8_book4_sprs(env); 7972 register_power8_rpr_sprs(env); 7973 register_power9_mmu_sprs(env); 7974 7975 /* POWER9 Specific registers */ 7976 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7977 spr_read_generic, spr_write_generic, 7978 KVM_REG_PPC_TIDR, 0); 7979 7980 /* FIXME: Filter fields properly based on privilege level */ 7981 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7982 spr_read_generic, spr_write_generic, 7983 KVM_REG_PPC_PSSCR, 0); 7984 7985 /* env variables */ 7986 env->dcache_line_size = 128; 7987 env->icache_line_size = 128; 7988 7989 /* Allocate hardware IRQ controller */ 7990 init_excp_POWER9(env); 7991 ppcPOWER9_irq_init(env_archcpu(env)); 7992 } 7993 7994 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7995 { 7996 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7997 return true; 7998 } 7999 return false; 8000 } 8001 8002 static bool cpu_has_work_POWER9(CPUState *cs) 8003 { 8004 PowerPCCPU *cpu = POWERPC_CPU(cs); 8005 CPUPPCState *env = &cpu->env; 8006 8007 if (cs->halted) { 8008 uint64_t psscr = env->spr[SPR_PSSCR]; 8009 8010 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8011 return false; 8012 } 8013 8014 /* If EC is clear, just return true on any pending interrupt */ 8015 if (!(psscr & PSSCR_EC)) { 8016 return true; 8017 } 8018 /* External Exception */ 8019 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8020 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8021 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8022 if (heic == 0 || !msr_hv || msr_pr) { 8023 return true; 8024 } 8025 } 8026 /* Decrementer Exception */ 8027 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8028 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8029 return true; 8030 } 8031 /* Machine Check or Hypervisor Maintenance Exception */ 8032 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8033 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8034 return true; 8035 } 8036 /* Privileged Doorbell Exception */ 8037 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8038 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8039 return true; 8040 } 8041 /* Hypervisor Doorbell Exception */ 8042 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8043 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8044 return true; 8045 } 8046 /* Hypervisor virtualization exception */ 8047 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8048 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8049 return true; 8050 } 8051 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8052 return true; 8053 } 8054 return false; 8055 } else { 8056 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8057 } 8058 } 8059 8060 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 8061 { 8062 DeviceClass *dc = DEVICE_CLASS(oc); 8063 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8064 CPUClass *cc = CPU_CLASS(oc); 8065 8066 dc->fw_name = "PowerPC,POWER9"; 8067 dc->desc = "POWER9"; 8068 pcc->pvr_match = ppc_pvr_match_power9; 8069 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 8070 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 8071 PCR_COMPAT_2_05; 8072 pcc->init_proc = init_proc_POWER9; 8073 pcc->check_pow = check_pow_nocheck; 8074 cc->has_work = cpu_has_work_POWER9; 8075 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8077 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8078 PPC_FLOAT_FRSQRTES | 8079 PPC_FLOAT_STFIWX | 8080 PPC_FLOAT_EXT | 8081 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8082 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8083 PPC_MEM_TLBSYNC | 8084 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8085 PPC_SEGMENT_64B | PPC_SLBI | 8086 PPC_POPCNTB | PPC_POPCNTWD | 8087 PPC_CILDST; 8088 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8089 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8090 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8091 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8092 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8093 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8094 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 8095 pcc->msr_mask = (1ull << MSR_SF) | 8096 (1ull << MSR_HV) | 8097 (1ull << MSR_TM) | 8098 (1ull << MSR_VR) | 8099 (1ull << MSR_VSX) | 8100 (1ull << MSR_EE) | 8101 (1ull << MSR_PR) | 8102 (1ull << MSR_FP) | 8103 (1ull << MSR_ME) | 8104 (1ull << MSR_FE0) | 8105 (1ull << MSR_SE) | 8106 (1ull << MSR_DE) | 8107 (1ull << MSR_FE1) | 8108 (1ull << MSR_IR) | 8109 (1ull << MSR_DR) | 8110 (1ull << MSR_PMM) | 8111 (1ull << MSR_RI) | 8112 (1ull << MSR_LE); 8113 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8114 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8115 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8116 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8117 LPCR_DEE | LPCR_OEE)) 8118 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8119 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8120 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8121 pcc->mmu_model = POWERPC_MMU_3_00; 8122 #if defined(CONFIG_SOFTMMU) 8123 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8124 /* segment page size remain the same */ 8125 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8126 pcc->radix_page_info = &POWER9_radix_page_info; 8127 pcc->lrg_decr_bits = 56; 8128 pcc->n_host_threads = 4; 8129 #endif 8130 pcc->excp_model = POWERPC_EXCP_POWER9; 8131 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8132 pcc->bfd_mach = bfd_mach_ppc64; 8133 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8134 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8135 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8136 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8137 pcc->l1_dcache_size = 0x8000; 8138 pcc->l1_icache_size = 0x8000; 8139 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8140 } 8141 8142 #ifdef CONFIG_SOFTMMU 8143 /* 8144 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 8145 * Encoded as array of int_32s in the form: 8146 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 8147 * x -> AP encoding 8148 * y -> radix mode supported page size (encoded as a shift) 8149 */ 8150 static struct ppc_radix_page_info POWER10_radix_page_info = { 8151 .count = 4, 8152 .entries = { 8153 0x0000000c, /* 4K - enc: 0x0 */ 8154 0xa0000010, /* 64K - enc: 0x5 */ 8155 0x20000015, /* 2M - enc: 0x1 */ 8156 0x4000001e /* 1G - enc: 0x2 */ 8157 } 8158 }; 8159 #endif /* CONFIG_SOFTMMU */ 8160 8161 static void init_proc_POWER10(CPUPPCState *env) 8162 { 8163 /* Common Registers */ 8164 init_proc_book3s_common(env); 8165 register_book3s_207_dbg_sprs(env); 8166 8167 /* POWER8 Specific Registers */ 8168 register_book3s_ids_sprs(env); 8169 register_amr_sprs(env); 8170 register_iamr_sprs(env); 8171 register_book3s_purr_sprs(env); 8172 register_power5p_common_sprs(env); 8173 register_power5p_lpar_sprs(env); 8174 register_power5p_ear_sprs(env); 8175 register_power6_common_sprs(env); 8176 register_power6_dbg_sprs(env); 8177 register_power8_tce_address_control_sprs(env); 8178 register_power8_ids_sprs(env); 8179 register_power8_ebb_sprs(env); 8180 register_power8_fscr_sprs(env); 8181 register_power8_pmu_sup_sprs(env); 8182 register_power8_pmu_user_sprs(env); 8183 register_power8_tm_sprs(env); 8184 register_power8_pspb_sprs(env); 8185 register_vtb_sprs(env); 8186 register_power8_ic_sprs(env); 8187 register_power8_book4_sprs(env); 8188 register_power8_rpr_sprs(env); 8189 register_power9_mmu_sprs(env); 8190 8191 /* FIXME: Filter fields properly based on privilege level */ 8192 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 8193 spr_read_generic, spr_write_generic, 8194 KVM_REG_PPC_PSSCR, 0); 8195 8196 /* env variables */ 8197 env->dcache_line_size = 128; 8198 env->icache_line_size = 128; 8199 8200 /* Allocate hardware IRQ controller */ 8201 init_excp_POWER10(env); 8202 ppcPOWER9_irq_init(env_archcpu(env)); 8203 } 8204 8205 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 8206 { 8207 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 8208 return true; 8209 } 8210 return false; 8211 } 8212 8213 static bool cpu_has_work_POWER10(CPUState *cs) 8214 { 8215 PowerPCCPU *cpu = POWERPC_CPU(cs); 8216 CPUPPCState *env = &cpu->env; 8217 8218 if (cs->halted) { 8219 uint64_t psscr = env->spr[SPR_PSSCR]; 8220 8221 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8222 return false; 8223 } 8224 8225 /* If EC is clear, just return true on any pending interrupt */ 8226 if (!(psscr & PSSCR_EC)) { 8227 return true; 8228 } 8229 /* External Exception */ 8230 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8231 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8232 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8233 if (heic == 0 || !msr_hv || msr_pr) { 8234 return true; 8235 } 8236 } 8237 /* Decrementer Exception */ 8238 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8239 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8240 return true; 8241 } 8242 /* Machine Check or Hypervisor Maintenance Exception */ 8243 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8244 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8245 return true; 8246 } 8247 /* Privileged Doorbell Exception */ 8248 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8249 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8250 return true; 8251 } 8252 /* Hypervisor Doorbell Exception */ 8253 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8254 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8255 return true; 8256 } 8257 /* Hypervisor virtualization exception */ 8258 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8259 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8260 return true; 8261 } 8262 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8263 return true; 8264 } 8265 return false; 8266 } else { 8267 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8268 } 8269 } 8270 8271 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 8272 { 8273 DeviceClass *dc = DEVICE_CLASS(oc); 8274 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8275 CPUClass *cc = CPU_CLASS(oc); 8276 8277 dc->fw_name = "PowerPC,POWER10"; 8278 dc->desc = "POWER10"; 8279 pcc->pvr_match = ppc_pvr_match_power10; 8280 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 8281 PCR_COMPAT_3_00; 8282 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 8283 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8284 pcc->init_proc = init_proc_POWER10; 8285 pcc->check_pow = check_pow_nocheck; 8286 cc->has_work = cpu_has_work_POWER10; 8287 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8288 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8289 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8290 PPC_FLOAT_FRSQRTES | 8291 PPC_FLOAT_STFIWX | 8292 PPC_FLOAT_EXT | 8293 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8294 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8295 PPC_MEM_TLBSYNC | 8296 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8297 PPC_SEGMENT_64B | PPC_SLBI | 8298 PPC_POPCNTB | PPC_POPCNTWD | 8299 PPC_CILDST; 8300 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8301 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8302 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8303 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8304 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8305 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8306 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 8307 pcc->msr_mask = (1ull << MSR_SF) | 8308 (1ull << MSR_HV) | 8309 (1ull << MSR_TM) | 8310 (1ull << MSR_VR) | 8311 (1ull << MSR_VSX) | 8312 (1ull << MSR_EE) | 8313 (1ull << MSR_PR) | 8314 (1ull << MSR_FP) | 8315 (1ull << MSR_ME) | 8316 (1ull << MSR_FE0) | 8317 (1ull << MSR_SE) | 8318 (1ull << MSR_DE) | 8319 (1ull << MSR_FE1) | 8320 (1ull << MSR_IR) | 8321 (1ull << MSR_DR) | 8322 (1ull << MSR_PMM) | 8323 (1ull << MSR_RI) | 8324 (1ull << MSR_LE); 8325 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8326 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8327 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8328 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8329 LPCR_DEE | LPCR_OEE)) 8330 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8331 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8332 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8333 pcc->mmu_model = POWERPC_MMU_3_00; 8334 #if defined(CONFIG_SOFTMMU) 8335 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8336 /* segment page size remain the same */ 8337 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8338 pcc->radix_page_info = &POWER10_radix_page_info; 8339 pcc->lrg_decr_bits = 56; 8340 #endif 8341 pcc->excp_model = POWERPC_EXCP_POWER10; 8342 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8343 pcc->bfd_mach = bfd_mach_ppc64; 8344 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8345 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8346 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8347 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8348 pcc->l1_dcache_size = 0x8000; 8349 pcc->l1_icache_size = 0x8000; 8350 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8351 } 8352 8353 #if !defined(CONFIG_USER_ONLY) 8354 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 8355 { 8356 CPUPPCState *env = &cpu->env; 8357 8358 cpu->vhyp = vhyp; 8359 8360 /* 8361 * With a virtual hypervisor mode we never allow the CPU to go 8362 * hypervisor mode itself 8363 */ 8364 env->msr_mask &= ~MSR_HVB; 8365 } 8366 8367 #endif /* !defined(CONFIG_USER_ONLY) */ 8368 8369 #endif /* defined(TARGET_PPC64) */ 8370 8371 /*****************************************************************************/ 8372 /* Generic CPU instantiation routine */ 8373 static void init_ppc_proc(PowerPCCPU *cpu) 8374 { 8375 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8376 CPUPPCState *env = &cpu->env; 8377 #if !defined(CONFIG_USER_ONLY) 8378 int i; 8379 8380 env->irq_inputs = NULL; 8381 /* Set all exception vectors to an invalid address */ 8382 for (i = 0; i < POWERPC_EXCP_NB; i++) { 8383 env->excp_vectors[i] = (target_ulong)(-1ULL); 8384 } 8385 env->ivor_mask = 0x00000000; 8386 env->ivpr_mask = 0x00000000; 8387 /* Default MMU definitions */ 8388 env->nb_BATs = 0; 8389 env->nb_tlb = 0; 8390 env->nb_ways = 0; 8391 env->tlb_type = TLB_NONE; 8392 #endif 8393 /* Register SPR common to all PowerPC implementations */ 8394 register_generic_sprs(env); 8395 spr_register(env, SPR_PVR, "PVR", 8396 /* Linux permits userspace to read PVR */ 8397 #if defined(CONFIG_LINUX_USER) 8398 &spr_read_generic, 8399 #else 8400 SPR_NOACCESS, 8401 #endif 8402 SPR_NOACCESS, 8403 &spr_read_generic, SPR_NOACCESS, 8404 pcc->pvr); 8405 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 8406 if (pcc->svr != POWERPC_SVR_NONE) { 8407 if (pcc->svr & POWERPC_SVR_E500) { 8408 spr_register(env, SPR_E500_SVR, "SVR", 8409 SPR_NOACCESS, SPR_NOACCESS, 8410 &spr_read_generic, SPR_NOACCESS, 8411 pcc->svr & ~POWERPC_SVR_E500); 8412 } else { 8413 spr_register(env, SPR_SVR, "SVR", 8414 SPR_NOACCESS, SPR_NOACCESS, 8415 &spr_read_generic, SPR_NOACCESS, 8416 pcc->svr); 8417 } 8418 } 8419 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 8420 (*pcc->init_proc)(env); 8421 8422 #if !defined(CONFIG_USER_ONLY) 8423 ppc_gdb_gen_spr_xml(cpu); 8424 #endif 8425 8426 /* MSR bits & flags consistency checks */ 8427 if (env->msr_mask & (1 << 25)) { 8428 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8429 case POWERPC_FLAG_SPE: 8430 case POWERPC_FLAG_VRE: 8431 break; 8432 default: 8433 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8434 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 8435 exit(1); 8436 } 8437 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8438 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8439 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 8440 exit(1); 8441 } 8442 if (env->msr_mask & (1 << 17)) { 8443 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8444 case POWERPC_FLAG_TGPR: 8445 case POWERPC_FLAG_CE: 8446 break; 8447 default: 8448 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8449 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 8450 exit(1); 8451 } 8452 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8453 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8454 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 8455 exit(1); 8456 } 8457 if (env->msr_mask & (1 << 10)) { 8458 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8459 POWERPC_FLAG_UBLE)) { 8460 case POWERPC_FLAG_SE: 8461 case POWERPC_FLAG_DWE: 8462 case POWERPC_FLAG_UBLE: 8463 break; 8464 default: 8465 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8466 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 8467 "POWERPC_FLAG_UBLE\n"); 8468 exit(1); 8469 } 8470 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8471 POWERPC_FLAG_UBLE)) { 8472 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8473 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 8474 "POWERPC_FLAG_UBLE\n"); 8475 exit(1); 8476 } 8477 if (env->msr_mask & (1 << 9)) { 8478 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8479 case POWERPC_FLAG_BE: 8480 case POWERPC_FLAG_DE: 8481 break; 8482 default: 8483 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8484 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 8485 exit(1); 8486 } 8487 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8488 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8489 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 8490 exit(1); 8491 } 8492 if (env->msr_mask & (1 << 2)) { 8493 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8494 case POWERPC_FLAG_PX: 8495 case POWERPC_FLAG_PMM: 8496 break; 8497 default: 8498 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8499 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 8500 exit(1); 8501 } 8502 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8503 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8504 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 8505 exit(1); 8506 } 8507 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 8508 fprintf(stderr, "PowerPC flags inconsistency\n" 8509 "Should define the time-base and decrementer clock source\n"); 8510 exit(1); 8511 } 8512 /* Allocate TLBs buffer when needed */ 8513 #if !defined(CONFIG_USER_ONLY) 8514 if (env->nb_tlb != 0) { 8515 int nb_tlb = env->nb_tlb; 8516 if (env->id_tlbs != 0) { 8517 nb_tlb *= 2; 8518 } 8519 switch (env->tlb_type) { 8520 case TLB_6XX: 8521 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 8522 break; 8523 case TLB_EMB: 8524 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 8525 break; 8526 case TLB_MAS: 8527 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 8528 break; 8529 } 8530 /* Pre-compute some useful values */ 8531 env->tlb_per_way = env->nb_tlb / env->nb_ways; 8532 } 8533 if (env->irq_inputs == NULL) { 8534 warn_report("no internal IRQ controller registered." 8535 " Attempt QEMU to crash very soon !"); 8536 } 8537 #endif 8538 if (env->check_pow == NULL) { 8539 warn_report("no power management check handler registered." 8540 " Attempt QEMU to crash very soon !"); 8541 } 8542 } 8543 8544 8545 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 8546 { 8547 CPUState *cs = CPU(dev); 8548 PowerPCCPU *cpu = POWERPC_CPU(dev); 8549 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8550 Error *local_err = NULL; 8551 8552 cpu_exec_realizefn(cs, &local_err); 8553 if (local_err != NULL) { 8554 error_propagate(errp, local_err); 8555 return; 8556 } 8557 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 8558 cpu->vcpu_id = cs->cpu_index; 8559 } 8560 8561 if (tcg_enabled()) { 8562 if (ppc_fixup_cpu(cpu) != 0) { 8563 error_setg(errp, "Unable to emulate selected CPU with TCG"); 8564 goto unrealize; 8565 } 8566 } 8567 8568 create_ppc_opcodes(cpu, &local_err); 8569 if (local_err != NULL) { 8570 error_propagate(errp, local_err); 8571 goto unrealize; 8572 } 8573 init_ppc_proc(cpu); 8574 8575 ppc_gdb_init(cs, pcc); 8576 qemu_init_vcpu(cs); 8577 8578 pcc->parent_realize(dev, errp); 8579 8580 return; 8581 8582 unrealize: 8583 cpu_exec_unrealizefn(cs); 8584 } 8585 8586 static void ppc_cpu_unrealize(DeviceState *dev) 8587 { 8588 PowerPCCPU *cpu = POWERPC_CPU(dev); 8589 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8590 8591 pcc->parent_unrealize(dev); 8592 8593 cpu_remove_sync(CPU(cpu)); 8594 8595 destroy_ppc_opcodes(cpu); 8596 } 8597 8598 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 8599 { 8600 ObjectClass *oc = (ObjectClass *)a; 8601 uint32_t pvr = *(uint32_t *)b; 8602 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8603 8604 /* -cpu host does a PVR lookup during construction */ 8605 if (unlikely(strcmp(object_class_get_name(oc), 8606 TYPE_HOST_POWERPC_CPU) == 0)) { 8607 return -1; 8608 } 8609 8610 return pcc->pvr == pvr ? 0 : -1; 8611 } 8612 8613 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 8614 { 8615 GSList *list, *item; 8616 PowerPCCPUClass *pcc = NULL; 8617 8618 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8619 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 8620 if (item != NULL) { 8621 pcc = POWERPC_CPU_CLASS(item->data); 8622 } 8623 g_slist_free(list); 8624 8625 return pcc; 8626 } 8627 8628 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 8629 { 8630 ObjectClass *oc = (ObjectClass *)a; 8631 uint32_t pvr = *(uint32_t *)b; 8632 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8633 8634 /* -cpu host does a PVR lookup during construction */ 8635 if (unlikely(strcmp(object_class_get_name(oc), 8636 TYPE_HOST_POWERPC_CPU) == 0)) { 8637 return -1; 8638 } 8639 8640 if (pcc->pvr_match(pcc, pvr)) { 8641 return 0; 8642 } 8643 8644 return -1; 8645 } 8646 8647 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 8648 { 8649 GSList *list, *item; 8650 PowerPCCPUClass *pcc = NULL; 8651 8652 list = object_class_get_list(TYPE_POWERPC_CPU, true); 8653 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 8654 if (item != NULL) { 8655 pcc = POWERPC_CPU_CLASS(item->data); 8656 } 8657 g_slist_free(list); 8658 8659 return pcc; 8660 } 8661 8662 static const char *ppc_cpu_lookup_alias(const char *alias) 8663 { 8664 int ai; 8665 8666 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 8667 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 8668 return ppc_cpu_aliases[ai].model; 8669 } 8670 } 8671 8672 return NULL; 8673 } 8674 8675 static ObjectClass *ppc_cpu_class_by_name(const char *name) 8676 { 8677 char *cpu_model, *typename; 8678 ObjectClass *oc; 8679 const char *p; 8680 unsigned long pvr; 8681 8682 /* 8683 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 8684 * 0x prefix if present) 8685 */ 8686 if (!qemu_strtoul(name, &p, 16, &pvr)) { 8687 int len = p - name; 8688 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 8689 if ((len == 8) && (*p == '\0')) { 8690 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 8691 } 8692 } 8693 8694 cpu_model = g_ascii_strdown(name, -1); 8695 p = ppc_cpu_lookup_alias(cpu_model); 8696 if (p) { 8697 g_free(cpu_model); 8698 cpu_model = g_strdup(p); 8699 } 8700 8701 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 8702 oc = object_class_by_name(typename); 8703 g_free(typename); 8704 g_free(cpu_model); 8705 8706 return oc; 8707 } 8708 8709 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 8710 { 8711 ObjectClass *oc = OBJECT_CLASS(pcc); 8712 8713 while (oc && !object_class_is_abstract(oc)) { 8714 oc = object_class_get_parent(oc); 8715 } 8716 assert(oc); 8717 8718 return POWERPC_CPU_CLASS(oc); 8719 } 8720 8721 /* Sort by PVR, ordering special case "host" last. */ 8722 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 8723 { 8724 ObjectClass *oc_a = (ObjectClass *)a; 8725 ObjectClass *oc_b = (ObjectClass *)b; 8726 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 8727 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 8728 const char *name_a = object_class_get_name(oc_a); 8729 const char *name_b = object_class_get_name(oc_b); 8730 8731 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 8732 return 1; 8733 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 8734 return -1; 8735 } else { 8736 /* Avoid an integer overflow during subtraction */ 8737 if (pcc_a->pvr < pcc_b->pvr) { 8738 return -1; 8739 } else if (pcc_a->pvr > pcc_b->pvr) { 8740 return 1; 8741 } else { 8742 return 0; 8743 } 8744 } 8745 } 8746 8747 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8748 { 8749 ObjectClass *oc = data; 8750 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8751 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8752 const char *typename = object_class_get_name(oc); 8753 char *name; 8754 int i; 8755 8756 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8757 return; 8758 } 8759 8760 name = g_strndup(typename, 8761 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8762 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8763 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8764 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8765 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8766 8767 if (alias_oc != oc) { 8768 continue; 8769 } 8770 /* 8771 * If running with KVM, we might update the family alias later, so 8772 * avoid printing the wrong alias here and use "preferred" instead 8773 */ 8774 if (strcmp(alias->alias, family->desc) == 0) { 8775 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8776 alias->alias, family->desc); 8777 } else { 8778 qemu_printf("PowerPC %-16s (alias for %s)\n", 8779 alias->alias, name); 8780 } 8781 } 8782 g_free(name); 8783 } 8784 8785 void ppc_cpu_list(void) 8786 { 8787 GSList *list; 8788 8789 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8790 list = g_slist_sort(list, ppc_cpu_list_compare); 8791 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 8792 g_slist_free(list); 8793 8794 #ifdef CONFIG_KVM 8795 qemu_printf("\n"); 8796 qemu_printf("PowerPC %-16s\n", "host"); 8797 #endif 8798 } 8799 8800 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 8801 { 8802 ObjectClass *oc = data; 8803 CpuDefinitionInfoList **first = user_data; 8804 const char *typename; 8805 CpuDefinitionInfo *info; 8806 8807 typename = object_class_get_name(oc); 8808 info = g_malloc0(sizeof(*info)); 8809 info->name = g_strndup(typename, 8810 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8811 8812 QAPI_LIST_PREPEND(*first, info); 8813 } 8814 8815 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8816 { 8817 CpuDefinitionInfoList *cpu_list = NULL; 8818 GSList *list; 8819 int i; 8820 8821 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8822 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 8823 g_slist_free(list); 8824 8825 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8826 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8827 ObjectClass *oc; 8828 CpuDefinitionInfo *info; 8829 8830 oc = ppc_cpu_class_by_name(alias->model); 8831 if (oc == NULL) { 8832 continue; 8833 } 8834 8835 info = g_malloc0(sizeof(*info)); 8836 info->name = g_strdup(alias->alias); 8837 info->q_typename = g_strdup(object_class_get_name(oc)); 8838 8839 QAPI_LIST_PREPEND(cpu_list, info); 8840 } 8841 8842 return cpu_list; 8843 } 8844 8845 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8846 { 8847 PowerPCCPU *cpu = POWERPC_CPU(cs); 8848 8849 cpu->env.nip = value; 8850 } 8851 8852 static bool ppc_cpu_has_work(CPUState *cs) 8853 { 8854 PowerPCCPU *cpu = POWERPC_CPU(cs); 8855 CPUPPCState *env = &cpu->env; 8856 8857 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8858 } 8859 8860 static void ppc_cpu_reset(DeviceState *dev) 8861 { 8862 CPUState *s = CPU(dev); 8863 PowerPCCPU *cpu = POWERPC_CPU(s); 8864 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8865 CPUPPCState *env = &cpu->env; 8866 target_ulong msr; 8867 int i; 8868 8869 pcc->parent_reset(dev); 8870 8871 msr = (target_ulong)0; 8872 msr |= (target_ulong)MSR_HVB; 8873 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 8874 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 8875 msr |= (target_ulong)1 << MSR_EP; 8876 #if defined(DO_SINGLE_STEP) && 0 8877 /* Single step trace mode */ 8878 msr |= (target_ulong)1 << MSR_SE; 8879 msr |= (target_ulong)1 << MSR_BE; 8880 #endif 8881 #if defined(CONFIG_USER_ONLY) 8882 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8883 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8884 msr |= (target_ulong)1 << MSR_FE1; 8885 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8886 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8887 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8888 msr |= (target_ulong)1 << MSR_PR; 8889 #if defined(TARGET_PPC64) 8890 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8891 #endif 8892 #if !defined(TARGET_WORDS_BIGENDIAN) 8893 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8894 if (!((env->msr_mask >> MSR_LE) & 1)) { 8895 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8896 exit(1); 8897 } 8898 #endif 8899 #endif 8900 8901 #if defined(TARGET_PPC64) 8902 if (mmu_is_64bit(env->mmu_model)) { 8903 msr |= (1ULL << MSR_SF); 8904 } 8905 #endif 8906 8907 hreg_store_msr(env, msr, 1); 8908 8909 #if !defined(CONFIG_USER_ONLY) 8910 env->nip = env->hreset_vector | env->excp_prefix; 8911 if (env->mmu_model != POWERPC_MMU_REAL) { 8912 ppc_tlb_invalidate_all(env); 8913 } 8914 #endif 8915 8916 hreg_compute_hflags(env); 8917 env->reserve_addr = (target_ulong)-1ULL; 8918 /* Be sure no exception or interrupt is pending */ 8919 env->pending_interrupts = 0; 8920 s->exception_index = POWERPC_EXCP_NONE; 8921 env->error_code = 0; 8922 ppc_irq_reset(cpu); 8923 8924 /* tininess for underflow is detected before rounding */ 8925 set_float_detect_tininess(float_tininess_before_rounding, 8926 &env->fp_status); 8927 8928 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8929 ppc_spr_t *spr = &env->spr_cb[i]; 8930 8931 if (!spr->name) { 8932 continue; 8933 } 8934 env->spr[i] = spr->default_value; 8935 } 8936 } 8937 8938 #ifndef CONFIG_USER_ONLY 8939 8940 static bool ppc_cpu_is_big_endian(CPUState *cs) 8941 { 8942 PowerPCCPU *cpu = POWERPC_CPU(cs); 8943 CPUPPCState *env = &cpu->env; 8944 8945 cpu_synchronize_state(cs); 8946 8947 return !msr_le; 8948 } 8949 8950 #ifdef CONFIG_TCG 8951 static void ppc_cpu_exec_enter(CPUState *cs) 8952 { 8953 PowerPCCPU *cpu = POWERPC_CPU(cs); 8954 8955 if (cpu->vhyp) { 8956 PPCVirtualHypervisorClass *vhc = 8957 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8958 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8959 } 8960 } 8961 8962 static void ppc_cpu_exec_exit(CPUState *cs) 8963 { 8964 PowerPCCPU *cpu = POWERPC_CPU(cs); 8965 8966 if (cpu->vhyp) { 8967 PPCVirtualHypervisorClass *vhc = 8968 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8969 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8970 } 8971 } 8972 #endif /* CONFIG_TCG */ 8973 8974 #endif /* !CONFIG_USER_ONLY */ 8975 8976 static void ppc_cpu_instance_init(Object *obj) 8977 { 8978 PowerPCCPU *cpu = POWERPC_CPU(obj); 8979 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8980 CPUPPCState *env = &cpu->env; 8981 8982 cpu_set_cpustate_pointers(cpu); 8983 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8984 8985 env->msr_mask = pcc->msr_mask; 8986 env->mmu_model = pcc->mmu_model; 8987 env->excp_model = pcc->excp_model; 8988 env->bus_model = pcc->bus_model; 8989 env->insns_flags = pcc->insns_flags; 8990 env->insns_flags2 = pcc->insns_flags2; 8991 env->flags = pcc->flags; 8992 env->bfd_mach = pcc->bfd_mach; 8993 env->check_pow = pcc->check_pow; 8994 8995 /* 8996 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8997 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8998 * mode support will remain, thus enforcing that we cannot use 8999 * priv. instructions in guest in PAPR mode. For 970 we currently 9000 * simply don't set HV in msr_mask thus simulating an "Apple mode" 9001 * 970. If we ever want to support 970 HV mode, we'll have to add 9002 * a processor attribute of some sort. 9003 */ 9004 #if !defined(CONFIG_USER_ONLY) 9005 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 9006 #endif 9007 9008 ppc_hash64_init(cpu); 9009 } 9010 9011 static void ppc_cpu_instance_finalize(Object *obj) 9012 { 9013 PowerPCCPU *cpu = POWERPC_CPU(obj); 9014 9015 ppc_hash64_finalize(cpu); 9016 } 9017 9018 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 9019 { 9020 return pcc->pvr == pvr; 9021 } 9022 9023 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 9024 { 9025 PowerPCCPU *cpu = POWERPC_CPU(cs); 9026 CPUPPCState *env = &cpu->env; 9027 9028 if ((env->hflags >> MSR_LE) & 1) { 9029 info->endian = BFD_ENDIAN_LITTLE; 9030 } 9031 info->mach = env->bfd_mach; 9032 if (!env->bfd_mach) { 9033 #ifdef TARGET_PPC64 9034 info->mach = bfd_mach_ppc64; 9035 #else 9036 info->mach = bfd_mach_ppc; 9037 #endif 9038 } 9039 info->disassembler_options = (char *)"any"; 9040 info->print_insn = print_insn_ppc; 9041 9042 info->cap_arch = CS_ARCH_PPC; 9043 #ifdef TARGET_PPC64 9044 info->cap_mode = CS_MODE_64; 9045 #endif 9046 } 9047 9048 static Property ppc_cpu_properties[] = { 9049 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 9050 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 9051 false), 9052 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 9053 false), 9054 DEFINE_PROP_END_OF_LIST(), 9055 }; 9056 9057 #ifndef CONFIG_USER_ONLY 9058 #include "hw/core/sysemu-cpu-ops.h" 9059 9060 static const struct SysemuCPUOps ppc_sysemu_ops = { 9061 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 9062 .write_elf32_note = ppc32_cpu_write_elf32_note, 9063 .write_elf64_note = ppc64_cpu_write_elf64_note, 9064 .virtio_is_big_endian = ppc_cpu_is_big_endian, 9065 .legacy_vmsd = &vmstate_ppc_cpu, 9066 }; 9067 #endif 9068 9069 #ifdef CONFIG_TCG 9070 #include "hw/core/tcg-cpu-ops.h" 9071 9072 static const struct TCGCPUOps ppc_tcg_ops = { 9073 .initialize = ppc_translate_init, 9074 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 9075 .tlb_fill = ppc_cpu_tlb_fill, 9076 9077 #ifndef CONFIG_USER_ONLY 9078 .do_interrupt = ppc_cpu_do_interrupt, 9079 .cpu_exec_enter = ppc_cpu_exec_enter, 9080 .cpu_exec_exit = ppc_cpu_exec_exit, 9081 .do_unaligned_access = ppc_cpu_do_unaligned_access, 9082 #endif /* !CONFIG_USER_ONLY */ 9083 }; 9084 #endif /* CONFIG_TCG */ 9085 9086 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 9087 { 9088 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9089 CPUClass *cc = CPU_CLASS(oc); 9090 DeviceClass *dc = DEVICE_CLASS(oc); 9091 9092 device_class_set_parent_realize(dc, ppc_cpu_realize, 9093 &pcc->parent_realize); 9094 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 9095 &pcc->parent_unrealize); 9096 pcc->pvr_match = ppc_pvr_match_default; 9097 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; 9098 device_class_set_props(dc, ppc_cpu_properties); 9099 9100 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 9101 9102 cc->class_by_name = ppc_cpu_class_by_name; 9103 cc->has_work = ppc_cpu_has_work; 9104 cc->dump_state = ppc_cpu_dump_state; 9105 cc->set_pc = ppc_cpu_set_pc; 9106 cc->gdb_read_register = ppc_cpu_gdb_read_register; 9107 cc->gdb_write_register = ppc_cpu_gdb_write_register; 9108 #ifndef CONFIG_USER_ONLY 9109 cc->sysemu_ops = &ppc_sysemu_ops; 9110 #endif 9111 9112 cc->gdb_num_core_regs = 71; 9113 #ifndef CONFIG_USER_ONLY 9114 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 9115 #endif 9116 #ifdef USE_APPLE_GDB 9117 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 9118 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 9119 cc->gdb_num_core_regs = 71 + 32; 9120 #endif 9121 9122 cc->gdb_arch_name = ppc_gdb_arch_name; 9123 #if defined(TARGET_PPC64) 9124 cc->gdb_core_xml_file = "power64-core.xml"; 9125 #else 9126 cc->gdb_core_xml_file = "power-core.xml"; 9127 #endif 9128 cc->disas_set_info = ppc_disas_set_info; 9129 9130 dc->fw_name = "PowerPC,UNKNOWN"; 9131 9132 #ifdef CONFIG_TCG 9133 cc->tcg_ops = &ppc_tcg_ops; 9134 #endif /* CONFIG_TCG */ 9135 } 9136 9137 static const TypeInfo ppc_cpu_type_info = { 9138 .name = TYPE_POWERPC_CPU, 9139 .parent = TYPE_CPU, 9140 .instance_size = sizeof(PowerPCCPU), 9141 .instance_align = __alignof__(PowerPCCPU), 9142 .instance_init = ppc_cpu_instance_init, 9143 .instance_finalize = ppc_cpu_instance_finalize, 9144 .abstract = true, 9145 .class_size = sizeof(PowerPCCPUClass), 9146 .class_init = ppc_cpu_class_init, 9147 }; 9148 9149 #ifndef CONFIG_USER_ONLY 9150 static const TypeInfo ppc_vhyp_type_info = { 9151 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 9152 .parent = TYPE_INTERFACE, 9153 .class_size = sizeof(PPCVirtualHypervisorClass), 9154 }; 9155 #endif 9156 9157 static void ppc_cpu_register_types(void) 9158 { 9159 type_register_static(&ppc_cpu_type_info); 9160 #ifndef CONFIG_USER_ONLY 9161 type_register_static(&ppc_vhyp_type_info); 9162 #endif 9163 } 9164 9165 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 9166 { 9167 #define RGPL 4 9168 #define RFPL 4 9169 9170 PowerPCCPU *cpu = POWERPC_CPU(cs); 9171 CPUPPCState *env = &cpu->env; 9172 int i; 9173 9174 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 9175 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 9176 env->nip, env->lr, env->ctr, cpu_read_xer(env), 9177 cs->cpu_index); 9178 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 9179 "%08x iidx %d didx %d\n", 9180 env->msr, env->spr[SPR_HID0], env->hflags, 9181 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 9182 #if !defined(NO_TIMER_DUMP) 9183 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 9184 #if !defined(CONFIG_USER_ONLY) 9185 " DECR " TARGET_FMT_lu 9186 #endif 9187 "\n", 9188 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 9189 #if !defined(CONFIG_USER_ONLY) 9190 , cpu_ppc_load_decr(env) 9191 #endif 9192 ); 9193 #endif 9194 for (i = 0; i < 32; i++) { 9195 if ((i & (RGPL - 1)) == 0) { 9196 qemu_fprintf(f, "GPR%02d", i); 9197 } 9198 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 9199 if ((i & (RGPL - 1)) == (RGPL - 1)) { 9200 qemu_fprintf(f, "\n"); 9201 } 9202 } 9203 qemu_fprintf(f, "CR "); 9204 for (i = 0; i < 8; i++) 9205 qemu_fprintf(f, "%01x", env->crf[i]); 9206 qemu_fprintf(f, " ["); 9207 for (i = 0; i < 8; i++) { 9208 char a = '-'; 9209 if (env->crf[i] & 0x08) { 9210 a = 'L'; 9211 } else if (env->crf[i] & 0x04) { 9212 a = 'G'; 9213 } else if (env->crf[i] & 0x02) { 9214 a = 'E'; 9215 } 9216 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 9217 } 9218 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 9219 env->reserve_addr); 9220 9221 if (flags & CPU_DUMP_FPU) { 9222 for (i = 0; i < 32; i++) { 9223 if ((i & (RFPL - 1)) == 0) { 9224 qemu_fprintf(f, "FPR%02d", i); 9225 } 9226 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 9227 if ((i & (RFPL - 1)) == (RFPL - 1)) { 9228 qemu_fprintf(f, "\n"); 9229 } 9230 } 9231 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 9232 } 9233 9234 #if !defined(CONFIG_USER_ONLY) 9235 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 9236 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 9237 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 9238 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 9239 9240 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 9241 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 9242 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 9243 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 9244 9245 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 9246 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 9247 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 9248 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 9249 9250 #if defined(TARGET_PPC64) 9251 if (env->excp_model == POWERPC_EXCP_POWER7 || 9252 env->excp_model == POWERPC_EXCP_POWER8 || 9253 env->excp_model == POWERPC_EXCP_POWER9 || 9254 env->excp_model == POWERPC_EXCP_POWER10) { 9255 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 9256 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 9257 } 9258 #endif 9259 if (env->excp_model == POWERPC_EXCP_BOOKE) { 9260 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 9261 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 9262 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 9263 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 9264 9265 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 9266 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 9267 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 9268 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 9269 9270 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 9271 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 9272 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 9273 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 9274 9275 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 9276 " EPR " TARGET_FMT_lx "\n", 9277 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 9278 env->spr[SPR_BOOKE_EPR]); 9279 9280 /* FSL-specific */ 9281 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 9282 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 9283 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 9284 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 9285 9286 /* 9287 * IVORs are left out as they are large and do not change often -- 9288 * they can be read with "p $ivor0", "p $ivor1", etc. 9289 */ 9290 } 9291 9292 #if defined(TARGET_PPC64) 9293 if (env->flags & POWERPC_FLAG_CFAR) { 9294 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 9295 } 9296 #endif 9297 9298 if (env->spr_cb[SPR_LPCR].name) { 9299 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 9300 } 9301 9302 switch (env->mmu_model) { 9303 case POWERPC_MMU_32B: 9304 case POWERPC_MMU_601: 9305 case POWERPC_MMU_SOFT_6xx: 9306 case POWERPC_MMU_SOFT_74xx: 9307 #if defined(TARGET_PPC64) 9308 case POWERPC_MMU_64B: 9309 case POWERPC_MMU_2_03: 9310 case POWERPC_MMU_2_06: 9311 case POWERPC_MMU_2_07: 9312 case POWERPC_MMU_3_00: 9313 #endif 9314 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 9315 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 9316 } 9317 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 9318 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 9319 } 9320 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 9321 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 9322 break; 9323 case POWERPC_MMU_BOOKE206: 9324 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 9325 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 9326 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 9327 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 9328 9329 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 9330 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 9331 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 9332 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 9333 9334 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 9335 " TLB1CFG " TARGET_FMT_lx "\n", 9336 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 9337 env->spr[SPR_BOOKE_TLB1CFG]); 9338 break; 9339 default: 9340 break; 9341 } 9342 #endif 9343 9344 #undef RGPL 9345 #undef RFPL 9346 } 9347 type_init(ppc_cpu_register_types) 9348