1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/arch_init.h" 26 #include "sysemu/cpus.h" 27 #include "sysemu/hw_accel.h" 28 #include "sysemu/tcg.h" 29 #include "cpu-models.h" 30 #include "mmu-hash32.h" 31 #include "mmu-hash64.h" 32 #include "qemu/error-report.h" 33 #include "qemu/module.h" 34 #include "qemu/qemu-print.h" 35 #include "qapi/error.h" 36 #include "qapi/qmp/qnull.h" 37 #include "qapi/visitor.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/ppc/ppc.h" 40 #include "mmu-book3s-v3.h" 41 #include "qemu/cutils.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 #include "qapi/qapi-commands-machine-target.h" 45 46 #include "helper_regs.h" 47 #include "internal.h" 48 #include "spr_tcg.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 602 implementation */ 753 static void register_602_sprs(CPUPPCState *env) 754 { 755 /* ESA registers */ 756 /* XXX : not implemented */ 757 spr_register(env, SPR_SER, "SER", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* XXX : not implemented */ 762 spr_register(env, SPR_SEBR, "SEBR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* XXX : not implemented */ 767 spr_register(env, SPR_ESASRR, "ESASRR", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 /* Floating point status */ 772 /* XXX : not implemented */ 773 spr_register(env, SPR_SP, "SP", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* XXX : not implemented */ 778 spr_register(env, SPR_LT, "LT", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 /* Watchdog timer */ 783 /* XXX : not implemented */ 784 spr_register(env, SPR_TCR, "TCR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 /* Interrupt base */ 789 spr_register(env, SPR_IBR, "IBR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* XXX : not implemented */ 794 spr_register(env, SPR_IABR, "IABR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 } 799 800 /* SPR specific to PowerPC 601 implementation */ 801 static void register_601_sprs(CPUPPCState *env) 802 { 803 /* Multiplication/division register */ 804 /* MQ */ 805 spr_register(env, SPR_MQ, "MQ", 806 &spr_read_generic, &spr_write_generic, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 /* RTC registers */ 810 spr_register(env, SPR_601_RTCU, "RTCU", 811 SPR_NOACCESS, SPR_NOACCESS, 812 SPR_NOACCESS, &spr_write_601_rtcu, 813 0x00000000); 814 spr_register(env, SPR_601_VRTCU, "RTCU", 815 &spr_read_601_rtcu, SPR_NOACCESS, 816 &spr_read_601_rtcu, SPR_NOACCESS, 817 0x00000000); 818 spr_register(env, SPR_601_RTCL, "RTCL", 819 SPR_NOACCESS, SPR_NOACCESS, 820 SPR_NOACCESS, &spr_write_601_rtcl, 821 0x00000000); 822 spr_register(env, SPR_601_VRTCL, "RTCL", 823 &spr_read_601_rtcl, SPR_NOACCESS, 824 &spr_read_601_rtcl, SPR_NOACCESS, 825 0x00000000); 826 /* Timer */ 827 #if 0 /* ? */ 828 spr_register(env, SPR_601_UDECR, "UDECR", 829 &spr_read_decr, SPR_NOACCESS, 830 &spr_read_decr, SPR_NOACCESS, 831 0x00000000); 832 #endif 833 /* External access control */ 834 /* XXX : not implemented */ 835 spr_register(env, SPR_EAR, "EAR", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 /* Memory management */ 840 #if !defined(CONFIG_USER_ONLY) 841 spr_register(env, SPR_IBAT0U, "IBAT0U", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_601_ubat, &spr_write_601_ubatu, 844 0x00000000); 845 spr_register(env, SPR_IBAT0L, "IBAT0L", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_601_ubat, &spr_write_601_ubatl, 848 0x00000000); 849 spr_register(env, SPR_IBAT1U, "IBAT1U", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_601_ubat, &spr_write_601_ubatu, 852 0x00000000); 853 spr_register(env, SPR_IBAT1L, "IBAT1L", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_601_ubat, &spr_write_601_ubatl, 856 0x00000000); 857 spr_register(env, SPR_IBAT2U, "IBAT2U", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_601_ubat, &spr_write_601_ubatu, 860 0x00000000); 861 spr_register(env, SPR_IBAT2L, "IBAT2L", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_601_ubat, &spr_write_601_ubatl, 864 0x00000000); 865 spr_register(env, SPR_IBAT3U, "IBAT3U", 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_601_ubat, &spr_write_601_ubatu, 868 0x00000000); 869 spr_register(env, SPR_IBAT3L, "IBAT3L", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_601_ubat, &spr_write_601_ubatl, 872 0x00000000); 873 env->nb_BATs = 4; 874 #endif 875 } 876 877 static void register_74xx_sprs(CPUPPCState *env) 878 { 879 /* Processor identification */ 880 spr_register(env, SPR_PIR, "PIR", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_pir, 883 0x00000000); 884 /* XXX : not implemented */ 885 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 886 SPR_NOACCESS, SPR_NOACCESS, 887 &spr_read_generic, &spr_write_generic, 888 0x00000000); 889 /* XXX : not implemented */ 890 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 891 &spr_read_ureg, SPR_NOACCESS, 892 &spr_read_ureg, SPR_NOACCESS, 893 0x00000000); 894 /* XXX: not implemented */ 895 spr_register(env, SPR_BAMR, "BAMR", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 /* XXX : not implemented */ 900 spr_register(env, SPR_MSSCR0, "MSSCR0", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_generic, 903 0x00000000); 904 /* Hardware implementation registers */ 905 /* XXX : not implemented */ 906 spr_register(env, SPR_HID0, "HID0", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 /* XXX : not implemented */ 911 spr_register(env, SPR_HID1, "HID1", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 /* Altivec */ 916 spr_register(env, SPR_VRSAVE, "VRSAVE", 917 &spr_read_generic, &spr_write_generic, 918 &spr_read_generic, &spr_write_generic, 919 0x00000000); 920 /* XXX : not implemented */ 921 spr_register(env, SPR_L2CR, "L2CR", 922 SPR_NOACCESS, SPR_NOACCESS, 923 &spr_read_generic, spr_access_nop, 924 0x00000000); 925 } 926 927 static void register_l3_ctrl(CPUPPCState *env) 928 { 929 /* L3CR */ 930 /* XXX : not implemented */ 931 spr_register(env, SPR_L3CR, "L3CR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 /* L3ITCR0 */ 936 /* XXX : not implemented */ 937 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 /* L3PM */ 942 /* XXX : not implemented */ 943 spr_register(env, SPR_L3PM, "L3PM", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 } 948 949 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 950 { 951 #if !defined(CONFIG_USER_ONLY) 952 env->nb_tlb = nb_tlbs; 953 env->nb_ways = nb_ways; 954 env->id_tlbs = 1; 955 env->tlb_type = TLB_6XX; 956 /* XXX : not implemented */ 957 spr_register(env, SPR_PTEHI, "PTEHI", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 /* XXX : not implemented */ 962 spr_register(env, SPR_PTELO, "PTELO", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 /* XXX : not implemented */ 967 spr_register(env, SPR_TLBMISS, "TLBMISS", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 #endif 972 } 973 974 static void register_usprg3_sprs(CPUPPCState *env) 975 { 976 spr_register(env, SPR_USPRG3, "USPRG3", 977 &spr_read_ureg, SPR_NOACCESS, 978 &spr_read_ureg, SPR_NOACCESS, 979 0x00000000); 980 } 981 982 static void register_usprgh_sprs(CPUPPCState *env) 983 { 984 spr_register(env, SPR_USPRG4, "USPRG4", 985 &spr_read_ureg, SPR_NOACCESS, 986 &spr_read_ureg, SPR_NOACCESS, 987 0x00000000); 988 spr_register(env, SPR_USPRG5, "USPRG5", 989 &spr_read_ureg, SPR_NOACCESS, 990 &spr_read_ureg, SPR_NOACCESS, 991 0x00000000); 992 spr_register(env, SPR_USPRG6, "USPRG6", 993 &spr_read_ureg, SPR_NOACCESS, 994 &spr_read_ureg, SPR_NOACCESS, 995 0x00000000); 996 spr_register(env, SPR_USPRG7, "USPRG7", 997 &spr_read_ureg, SPR_NOACCESS, 998 &spr_read_ureg, SPR_NOACCESS, 999 0x00000000); 1000 } 1001 1002 /* PowerPC BookE SPR */ 1003 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1004 { 1005 const char *ivor_names[64] = { 1006 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1007 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1008 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1009 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1010 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1011 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1012 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1013 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1014 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1015 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1016 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1017 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1018 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1019 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1020 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1021 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1022 }; 1023 #define SPR_BOOKE_IVORxx (-1) 1024 int ivor_sprn[64] = { 1025 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1026 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1027 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1028 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1029 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1030 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1031 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1032 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1033 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1034 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1035 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1036 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1037 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1038 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1039 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1040 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1041 }; 1042 int i; 1043 1044 /* Interrupt processing */ 1045 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1046 SPR_NOACCESS, SPR_NOACCESS, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1050 SPR_NOACCESS, SPR_NOACCESS, 1051 &spr_read_generic, &spr_write_generic, 1052 0x00000000); 1053 /* Debug */ 1054 /* XXX : not implemented */ 1055 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 /* XXX : not implemented */ 1060 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 /* XXX : not implemented */ 1065 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, &spr_write_generic, 1068 0x00000000); 1069 /* XXX : not implemented */ 1070 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 /* XXX : not implemented */ 1075 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1076 SPR_NOACCESS, SPR_NOACCESS, 1077 &spr_read_generic, &spr_write_40x_dbcr0, 1078 0x00000000); 1079 /* XXX : not implemented */ 1080 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 /* XXX : not implemented */ 1085 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_generic, 1088 0x00000000); 1089 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, &spr_write_generic, 1092 0x00000000); 1093 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, &spr_write_generic, 1096 0x00000000); 1097 /* XXX : not implemented */ 1098 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1099 SPR_NOACCESS, SPR_NOACCESS, 1100 &spr_read_generic, &spr_write_clear, 1101 0x00000000); 1102 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, &spr_write_generic, 1105 0x00000000); 1106 spr_register(env, SPR_BOOKE_ESR, "ESR", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, &spr_write_generic, 1109 0x00000000); 1110 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_excp_prefix, 1113 0x00000000); 1114 /* Exception vectors */ 1115 for (i = 0; i < 64; i++) { 1116 if (ivor_mask & (1ULL << i)) { 1117 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1118 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1119 exit(1); 1120 } 1121 spr_register(env, ivor_sprn[i], ivor_names[i], 1122 SPR_NOACCESS, SPR_NOACCESS, 1123 &spr_read_generic, &spr_write_excp_vector, 1124 0x00000000); 1125 } 1126 } 1127 spr_register(env, SPR_BOOKE_PID, "PID", 1128 SPR_NOACCESS, SPR_NOACCESS, 1129 &spr_read_generic, &spr_write_booke_pid, 1130 0x00000000); 1131 spr_register(env, SPR_BOOKE_TCR, "TCR", 1132 SPR_NOACCESS, SPR_NOACCESS, 1133 &spr_read_generic, &spr_write_booke_tcr, 1134 0x00000000); 1135 spr_register(env, SPR_BOOKE_TSR, "TSR", 1136 SPR_NOACCESS, SPR_NOACCESS, 1137 &spr_read_generic, &spr_write_booke_tsr, 1138 0x00000000); 1139 /* Timer */ 1140 spr_register(env, SPR_DECR, "DECR", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_decr, &spr_write_decr, 1143 0x00000000); 1144 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 SPR_NOACCESS, &spr_write_generic, 1147 0x00000000); 1148 /* SPRGs */ 1149 spr_register(env, SPR_USPRG0, "USPRG0", 1150 &spr_read_generic, &spr_write_generic, 1151 &spr_read_generic, &spr_write_generic, 1152 0x00000000); 1153 spr_register(env, SPR_SPRG4, "SPRG4", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00000000); 1157 spr_register(env, SPR_SPRG5, "SPRG5", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 spr_register(env, SPR_SPRG6, "SPRG6", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 spr_register(env, SPR_SPRG7, "SPRG7", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_generic, 1168 0x00000000); 1169 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1170 SPR_NOACCESS, SPR_NOACCESS, 1171 &spr_read_generic, &spr_write_generic, 1172 0x00000000); 1173 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 } 1178 1179 #if !defined(CONFIG_USER_ONLY) 1180 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1181 uint32_t maxsize, uint32_t flags, 1182 uint32_t nentries) 1183 { 1184 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1185 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1186 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1187 flags | nentries; 1188 } 1189 #endif /* !CONFIG_USER_ONLY */ 1190 1191 /* BookE 2.06 storage control registers */ 1192 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1193 uint32_t *tlbncfg, uint32_t mmucfg) 1194 { 1195 #if !defined(CONFIG_USER_ONLY) 1196 const char *mas_names[8] = { 1197 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1198 }; 1199 int mas_sprn[8] = { 1200 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1201 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1202 }; 1203 int i; 1204 1205 /* TLB assist registers */ 1206 /* XXX : not implemented */ 1207 for (i = 0; i < 8; i++) { 1208 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = 1209 &spr_write_generic32; 1210 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { 1211 uea_write = &spr_write_generic; 1212 } 1213 if (mas_mask & (1 << i)) { 1214 spr_register(env, mas_sprn[i], mas_names[i], 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, uea_write, 1217 0x00000000); 1218 } 1219 } 1220 if (env->nb_pids > 1) { 1221 /* XXX : not implemented */ 1222 spr_register(env, SPR_BOOKE_PID1, "PID1", 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_booke_pid, 1225 0x00000000); 1226 } 1227 if (env->nb_pids > 2) { 1228 /* XXX : not implemented */ 1229 spr_register(env, SPR_BOOKE_PID2, "PID2", 1230 SPR_NOACCESS, SPR_NOACCESS, 1231 &spr_read_generic, &spr_write_booke_pid, 1232 0x00000000); 1233 } 1234 1235 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1236 SPR_NOACCESS, SPR_NOACCESS, 1237 &spr_read_generic, &spr_write_eplc, 1238 0x00000000); 1239 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1240 SPR_NOACCESS, SPR_NOACCESS, 1241 &spr_read_generic, &spr_write_epsc, 1242 0x00000000); 1243 1244 /* XXX : not implemented */ 1245 spr_register(env, SPR_MMUCFG, "MMUCFG", 1246 SPR_NOACCESS, SPR_NOACCESS, 1247 &spr_read_generic, SPR_NOACCESS, 1248 mmucfg); 1249 switch (env->nb_ways) { 1250 case 4: 1251 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1252 SPR_NOACCESS, SPR_NOACCESS, 1253 &spr_read_generic, SPR_NOACCESS, 1254 tlbncfg[3]); 1255 /* Fallthru */ 1256 case 3: 1257 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, SPR_NOACCESS, 1260 tlbncfg[2]); 1261 /* Fallthru */ 1262 case 2: 1263 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, SPR_NOACCESS, 1266 tlbncfg[1]); 1267 /* Fallthru */ 1268 case 1: 1269 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1270 SPR_NOACCESS, SPR_NOACCESS, 1271 &spr_read_generic, SPR_NOACCESS, 1272 tlbncfg[0]); 1273 /* Fallthru */ 1274 case 0: 1275 default: 1276 break; 1277 } 1278 #endif 1279 1280 register_usprgh_sprs(env); 1281 } 1282 1283 /* SPR specific to PowerPC 440 implementation */ 1284 static void register_440_sprs(CPUPPCState *env) 1285 { 1286 /* Cache control */ 1287 /* XXX : not implemented */ 1288 spr_register(env, SPR_440_DNV0, "DNV0", 1289 SPR_NOACCESS, SPR_NOACCESS, 1290 &spr_read_generic, &spr_write_generic, 1291 0x00000000); 1292 /* XXX : not implemented */ 1293 spr_register(env, SPR_440_DNV1, "DNV1", 1294 SPR_NOACCESS, SPR_NOACCESS, 1295 &spr_read_generic, &spr_write_generic, 1296 0x00000000); 1297 /* XXX : not implemented */ 1298 spr_register(env, SPR_440_DNV2, "DNV2", 1299 SPR_NOACCESS, SPR_NOACCESS, 1300 &spr_read_generic, &spr_write_generic, 1301 0x00000000); 1302 /* XXX : not implemented */ 1303 spr_register(env, SPR_440_DNV3, "DNV3", 1304 SPR_NOACCESS, SPR_NOACCESS, 1305 &spr_read_generic, &spr_write_generic, 1306 0x00000000); 1307 /* XXX : not implemented */ 1308 spr_register(env, SPR_440_DTV0, "DTV0", 1309 SPR_NOACCESS, SPR_NOACCESS, 1310 &spr_read_generic, &spr_write_generic, 1311 0x00000000); 1312 /* XXX : not implemented */ 1313 spr_register(env, SPR_440_DTV1, "DTV1", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_generic, &spr_write_generic, 1316 0x00000000); 1317 /* XXX : not implemented */ 1318 spr_register(env, SPR_440_DTV2, "DTV2", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, &spr_write_generic, 1321 0x00000000); 1322 /* XXX : not implemented */ 1323 spr_register(env, SPR_440_DTV3, "DTV3", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, &spr_write_generic, 1326 0x00000000); 1327 /* XXX : not implemented */ 1328 spr_register(env, SPR_440_DVLIM, "DVLIM", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 /* XXX : not implemented */ 1333 spr_register(env, SPR_440_INV0, "INV0", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 /* XXX : not implemented */ 1338 spr_register(env, SPR_440_INV1, "INV1", 1339 SPR_NOACCESS, SPR_NOACCESS, 1340 &spr_read_generic, &spr_write_generic, 1341 0x00000000); 1342 /* XXX : not implemented */ 1343 spr_register(env, SPR_440_INV2, "INV2", 1344 SPR_NOACCESS, SPR_NOACCESS, 1345 &spr_read_generic, &spr_write_generic, 1346 0x00000000); 1347 /* XXX : not implemented */ 1348 spr_register(env, SPR_440_INV3, "INV3", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, &spr_write_generic, 1351 0x00000000); 1352 /* XXX : not implemented */ 1353 spr_register(env, SPR_440_ITV0, "ITV0", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 /* XXX : not implemented */ 1358 spr_register(env, SPR_440_ITV1, "ITV1", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 /* XXX : not implemented */ 1363 spr_register(env, SPR_440_ITV2, "ITV2", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, &spr_write_generic, 1366 0x00000000); 1367 /* XXX : not implemented */ 1368 spr_register(env, SPR_440_ITV3, "ITV3", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 /* XXX : not implemented */ 1373 spr_register(env, SPR_440_IVLIM, "IVLIM", 1374 SPR_NOACCESS, SPR_NOACCESS, 1375 &spr_read_generic, &spr_write_generic, 1376 0x00000000); 1377 /* Cache debug */ 1378 /* XXX : not implemented */ 1379 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, SPR_NOACCESS, 1382 0x00000000); 1383 /* XXX : not implemented */ 1384 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, SPR_NOACCESS, 1387 0x00000000); 1388 /* XXX : not implemented */ 1389 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, SPR_NOACCESS, 1392 0x00000000); 1393 /* XXX : not implemented */ 1394 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, SPR_NOACCESS, 1397 0x00000000); 1398 /* XXX : not implemented */ 1399 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1400 SPR_NOACCESS, SPR_NOACCESS, 1401 &spr_read_generic, SPR_NOACCESS, 1402 0x00000000); 1403 /* XXX : not implemented */ 1404 spr_register(env, SPR_440_DBDR, "DBDR", 1405 SPR_NOACCESS, SPR_NOACCESS, 1406 &spr_read_generic, &spr_write_generic, 1407 0x00000000); 1408 /* Processor control */ 1409 spr_register(env, SPR_4xx_CCR0, "CCR0", 1410 SPR_NOACCESS, SPR_NOACCESS, 1411 &spr_read_generic, &spr_write_generic, 1412 0x00000000); 1413 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, SPR_NOACCESS, 1416 0x00000000); 1417 /* Storage control */ 1418 spr_register(env, SPR_440_MMUCR, "MMUCR", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, &spr_write_generic, 1421 0x00000000); 1422 } 1423 1424 /* SPR shared between PowerPC 40x implementations */ 1425 static void register_40x_sprs(CPUPPCState *env) 1426 { 1427 /* Cache */ 1428 /* not emulated, as QEMU do not emulate caches */ 1429 spr_register(env, SPR_40x_DCCR, "DCCR", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 &spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 /* not emulated, as QEMU do not emulate caches */ 1434 spr_register(env, SPR_40x_ICCR, "ICCR", 1435 SPR_NOACCESS, SPR_NOACCESS, 1436 &spr_read_generic, &spr_write_generic, 1437 0x00000000); 1438 /* not emulated, as QEMU do not emulate caches */ 1439 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1440 SPR_NOACCESS, SPR_NOACCESS, 1441 &spr_read_generic, SPR_NOACCESS, 1442 0x00000000); 1443 /* Exception */ 1444 spr_register(env, SPR_40x_DEAR, "DEAR", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, &spr_write_generic, 1447 0x00000000); 1448 spr_register(env, SPR_40x_ESR, "ESR", 1449 SPR_NOACCESS, SPR_NOACCESS, 1450 &spr_read_generic, &spr_write_generic, 1451 0x00000000); 1452 spr_register(env, SPR_40x_EVPR, "EVPR", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_excp_prefix, 1455 0x00000000); 1456 spr_register(env, SPR_40x_SRR2, "SRR2", 1457 &spr_read_generic, &spr_write_generic, 1458 &spr_read_generic, &spr_write_generic, 1459 0x00000000); 1460 spr_register(env, SPR_40x_SRR3, "SRR3", 1461 &spr_read_generic, &spr_write_generic, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 /* Timers */ 1465 spr_register(env, SPR_40x_PIT, "PIT", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_40x_pit, &spr_write_40x_pit, 1468 0x00000000); 1469 spr_register(env, SPR_40x_TCR, "TCR", 1470 SPR_NOACCESS, SPR_NOACCESS, 1471 &spr_read_generic, &spr_write_booke_tcr, 1472 0x00000000); 1473 spr_register(env, SPR_40x_TSR, "TSR", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_booke_tsr, 1476 0x00000000); 1477 } 1478 1479 /* SPR specific to PowerPC 405 implementation */ 1480 static void register_405_sprs(CPUPPCState *env) 1481 { 1482 /* MMU */ 1483 spr_register(env, SPR_40x_PID, "PID", 1484 SPR_NOACCESS, SPR_NOACCESS, 1485 &spr_read_generic, &spr_write_generic, 1486 0x00000000); 1487 spr_register(env, SPR_4xx_CCR0, "CCR0", 1488 SPR_NOACCESS, SPR_NOACCESS, 1489 &spr_read_generic, &spr_write_generic, 1490 0x00700000); 1491 /* Debug interface */ 1492 /* XXX : not implemented */ 1493 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_40x_dbcr0, 1496 0x00000000); 1497 /* XXX : not implemented */ 1498 spr_register(env, SPR_405_DBCR1, "DBCR1", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 &spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 /* XXX : not implemented */ 1503 spr_register(env, SPR_40x_DBSR, "DBSR", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, &spr_write_clear, 1506 /* Last reset was system reset */ 1507 0x00000300); 1508 /* XXX : not implemented */ 1509 spr_register(env, SPR_40x_DAC1, "DAC1", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 spr_register(env, SPR_40x_DAC2, "DAC2", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 0x00000000); 1517 /* XXX : not implemented */ 1518 spr_register(env, SPR_405_DVC1, "DVC1", 1519 SPR_NOACCESS, SPR_NOACCESS, 1520 &spr_read_generic, &spr_write_generic, 1521 0x00000000); 1522 /* XXX : not implemented */ 1523 spr_register(env, SPR_405_DVC2, "DVC2", 1524 SPR_NOACCESS, SPR_NOACCESS, 1525 &spr_read_generic, &spr_write_generic, 1526 0x00000000); 1527 /* XXX : not implemented */ 1528 spr_register(env, SPR_40x_IAC1, "IAC1", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_generic, 1531 0x00000000); 1532 spr_register(env, SPR_40x_IAC2, "IAC2", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 /* XXX : not implemented */ 1537 spr_register(env, SPR_405_IAC3, "IAC3", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 /* XXX : not implemented */ 1542 spr_register(env, SPR_405_IAC4, "IAC4", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 /* Storage control */ 1547 /* XXX: TODO: not implemented */ 1548 spr_register(env, SPR_405_SLER, "SLER", 1549 SPR_NOACCESS, SPR_NOACCESS, 1550 &spr_read_generic, &spr_write_40x_sler, 1551 0x00000000); 1552 spr_register(env, SPR_40x_ZPR, "ZPR", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 /* XXX : not implemented */ 1557 spr_register(env, SPR_405_SU0R, "SU0R", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 /* SPRG */ 1562 spr_register(env, SPR_USPRG0, "USPRG0", 1563 &spr_read_ureg, SPR_NOACCESS, 1564 &spr_read_ureg, SPR_NOACCESS, 1565 0x00000000); 1566 spr_register(env, SPR_SPRG4, "SPRG4", 1567 SPR_NOACCESS, SPR_NOACCESS, 1568 &spr_read_generic, &spr_write_generic, 1569 0x00000000); 1570 spr_register(env, SPR_SPRG5, "SPRG5", 1571 SPR_NOACCESS, SPR_NOACCESS, 1572 spr_read_generic, &spr_write_generic, 1573 0x00000000); 1574 spr_register(env, SPR_SPRG6, "SPRG6", 1575 SPR_NOACCESS, SPR_NOACCESS, 1576 spr_read_generic, &spr_write_generic, 1577 0x00000000); 1578 spr_register(env, SPR_SPRG7, "SPRG7", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 register_usprgh_sprs(env); 1583 } 1584 1585 /* SPR shared between PowerPC 401 & 403 implementations */ 1586 static void register_401_403_sprs(CPUPPCState *env) 1587 { 1588 /* Time base */ 1589 spr_register(env, SPR_403_VTBL, "TBL", 1590 &spr_read_tbl, SPR_NOACCESS, 1591 &spr_read_tbl, SPR_NOACCESS, 1592 0x00000000); 1593 spr_register(env, SPR_403_TBL, "TBL", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 SPR_NOACCESS, &spr_write_tbl, 1596 0x00000000); 1597 spr_register(env, SPR_403_VTBU, "TBU", 1598 &spr_read_tbu, SPR_NOACCESS, 1599 &spr_read_tbu, SPR_NOACCESS, 1600 0x00000000); 1601 spr_register(env, SPR_403_TBU, "TBU", 1602 SPR_NOACCESS, SPR_NOACCESS, 1603 SPR_NOACCESS, &spr_write_tbu, 1604 0x00000000); 1605 /* Debug */ 1606 /* not emulated, as QEMU do not emulate caches */ 1607 spr_register(env, SPR_403_CDBCR, "CDBCR", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 } 1612 1613 /* SPR specific to PowerPC 401 implementation */ 1614 static void register_401_sprs(CPUPPCState *env) 1615 { 1616 /* Debug interface */ 1617 /* XXX : not implemented */ 1618 spr_register(env, SPR_40x_DBCR0, "DBCR", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_generic, &spr_write_40x_dbcr0, 1621 0x00000000); 1622 /* XXX : not implemented */ 1623 spr_register(env, SPR_40x_DBSR, "DBSR", 1624 SPR_NOACCESS, SPR_NOACCESS, 1625 &spr_read_generic, &spr_write_clear, 1626 /* Last reset was system reset */ 1627 0x00000300); 1628 /* XXX : not implemented */ 1629 spr_register(env, SPR_40x_DAC1, "DAC", 1630 SPR_NOACCESS, SPR_NOACCESS, 1631 &spr_read_generic, &spr_write_generic, 1632 0x00000000); 1633 /* XXX : not implemented */ 1634 spr_register(env, SPR_40x_IAC1, "IAC", 1635 SPR_NOACCESS, SPR_NOACCESS, 1636 &spr_read_generic, &spr_write_generic, 1637 0x00000000); 1638 /* Storage control */ 1639 /* XXX: TODO: not implemented */ 1640 spr_register(env, SPR_405_SLER, "SLER", 1641 SPR_NOACCESS, SPR_NOACCESS, 1642 &spr_read_generic, &spr_write_40x_sler, 1643 0x00000000); 1644 /* not emulated, as QEMU never does speculative access */ 1645 spr_register(env, SPR_40x_SGR, "SGR", 1646 SPR_NOACCESS, SPR_NOACCESS, 1647 &spr_read_generic, &spr_write_generic, 1648 0xFFFFFFFF); 1649 /* not emulated, as QEMU do not emulate caches */ 1650 spr_register(env, SPR_40x_DCWR, "DCWR", 1651 SPR_NOACCESS, SPR_NOACCESS, 1652 &spr_read_generic, &spr_write_generic, 1653 0x00000000); 1654 } 1655 1656 static void register_401x2_sprs(CPUPPCState *env) 1657 { 1658 register_401_sprs(env); 1659 spr_register(env, SPR_40x_PID, "PID", 1660 SPR_NOACCESS, SPR_NOACCESS, 1661 &spr_read_generic, &spr_write_generic, 1662 0x00000000); 1663 spr_register(env, SPR_40x_ZPR, "ZPR", 1664 SPR_NOACCESS, SPR_NOACCESS, 1665 &spr_read_generic, &spr_write_generic, 1666 0x00000000); 1667 } 1668 1669 /* SPR specific to PowerPC 403 implementation */ 1670 static void register_403_sprs(CPUPPCState *env) 1671 { 1672 /* Debug interface */ 1673 /* XXX : not implemented */ 1674 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1675 SPR_NOACCESS, SPR_NOACCESS, 1676 &spr_read_generic, &spr_write_40x_dbcr0, 1677 0x00000000); 1678 /* XXX : not implemented */ 1679 spr_register(env, SPR_40x_DBSR, "DBSR", 1680 SPR_NOACCESS, SPR_NOACCESS, 1681 &spr_read_generic, &spr_write_clear, 1682 /* Last reset was system reset */ 1683 0x00000300); 1684 /* XXX : not implemented */ 1685 spr_register(env, SPR_40x_DAC1, "DAC1", 1686 SPR_NOACCESS, SPR_NOACCESS, 1687 &spr_read_generic, &spr_write_generic, 1688 0x00000000); 1689 /* XXX : not implemented */ 1690 spr_register(env, SPR_40x_DAC2, "DAC2", 1691 SPR_NOACCESS, SPR_NOACCESS, 1692 &spr_read_generic, &spr_write_generic, 1693 0x00000000); 1694 /* XXX : not implemented */ 1695 spr_register(env, SPR_40x_IAC1, "IAC1", 1696 SPR_NOACCESS, SPR_NOACCESS, 1697 &spr_read_generic, &spr_write_generic, 1698 0x00000000); 1699 /* XXX : not implemented */ 1700 spr_register(env, SPR_40x_IAC2, "IAC2", 1701 SPR_NOACCESS, SPR_NOACCESS, 1702 &spr_read_generic, &spr_write_generic, 1703 0x00000000); 1704 } 1705 1706 static void register_403_real_sprs(CPUPPCState *env) 1707 { 1708 spr_register(env, SPR_403_PBL1, "PBL1", 1709 SPR_NOACCESS, SPR_NOACCESS, 1710 &spr_read_403_pbr, &spr_write_403_pbr, 1711 0x00000000); 1712 spr_register(env, SPR_403_PBU1, "PBU1", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_403_pbr, &spr_write_403_pbr, 1715 0x00000000); 1716 spr_register(env, SPR_403_PBL2, "PBL2", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_403_pbr, &spr_write_403_pbr, 1719 0x00000000); 1720 spr_register(env, SPR_403_PBU2, "PBU2", 1721 SPR_NOACCESS, SPR_NOACCESS, 1722 &spr_read_403_pbr, &spr_write_403_pbr, 1723 0x00000000); 1724 } 1725 1726 static void register_403_mmu_sprs(CPUPPCState *env) 1727 { 1728 /* MMU */ 1729 spr_register(env, SPR_40x_PID, "PID", 1730 SPR_NOACCESS, SPR_NOACCESS, 1731 &spr_read_generic, &spr_write_generic, 1732 0x00000000); 1733 spr_register(env, SPR_40x_ZPR, "ZPR", 1734 SPR_NOACCESS, SPR_NOACCESS, 1735 &spr_read_generic, &spr_write_generic, 1736 0x00000000); 1737 } 1738 1739 /* SPR specific to PowerPC compression coprocessor extension */ 1740 static void register_compress_sprs(CPUPPCState *env) 1741 { 1742 /* XXX : not implemented */ 1743 spr_register(env, SPR_401_SKR, "SKR", 1744 SPR_NOACCESS, SPR_NOACCESS, 1745 &spr_read_generic, &spr_write_generic, 1746 0x00000000); 1747 } 1748 1749 static void register_5xx_8xx_sprs(CPUPPCState *env) 1750 { 1751 /* Exception processing */ 1752 spr_register_kvm(env, SPR_DSISR, "DSISR", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 KVM_REG_PPC_DSISR, 0x00000000); 1756 spr_register_kvm(env, SPR_DAR, "DAR", 1757 SPR_NOACCESS, SPR_NOACCESS, 1758 &spr_read_generic, &spr_write_generic, 1759 KVM_REG_PPC_DAR, 0x00000000); 1760 /* Timer */ 1761 spr_register(env, SPR_DECR, "DECR", 1762 SPR_NOACCESS, SPR_NOACCESS, 1763 &spr_read_decr, &spr_write_decr, 1764 0x00000000); 1765 /* XXX : not implemented */ 1766 spr_register(env, SPR_MPC_EIE, "EIE", 1767 SPR_NOACCESS, SPR_NOACCESS, 1768 &spr_read_generic, &spr_write_generic, 1769 0x00000000); 1770 /* XXX : not implemented */ 1771 spr_register(env, SPR_MPC_EID, "EID", 1772 SPR_NOACCESS, SPR_NOACCESS, 1773 &spr_read_generic, &spr_write_generic, 1774 0x00000000); 1775 /* XXX : not implemented */ 1776 spr_register(env, SPR_MPC_NRI, "NRI", 1777 SPR_NOACCESS, SPR_NOACCESS, 1778 &spr_read_generic, &spr_write_generic, 1779 0x00000000); 1780 /* XXX : not implemented */ 1781 spr_register(env, SPR_MPC_CMPA, "CMPA", 1782 SPR_NOACCESS, SPR_NOACCESS, 1783 &spr_read_generic, &spr_write_generic, 1784 0x00000000); 1785 /* XXX : not implemented */ 1786 spr_register(env, SPR_MPC_CMPB, "CMPB", 1787 SPR_NOACCESS, SPR_NOACCESS, 1788 &spr_read_generic, &spr_write_generic, 1789 0x00000000); 1790 /* XXX : not implemented */ 1791 spr_register(env, SPR_MPC_CMPC, "CMPC", 1792 SPR_NOACCESS, SPR_NOACCESS, 1793 &spr_read_generic, &spr_write_generic, 1794 0x00000000); 1795 /* XXX : not implemented */ 1796 spr_register(env, SPR_MPC_CMPD, "CMPD", 1797 SPR_NOACCESS, SPR_NOACCESS, 1798 &spr_read_generic, &spr_write_generic, 1799 0x00000000); 1800 /* XXX : not implemented */ 1801 spr_register(env, SPR_MPC_ECR, "ECR", 1802 SPR_NOACCESS, SPR_NOACCESS, 1803 &spr_read_generic, &spr_write_generic, 1804 0x00000000); 1805 /* XXX : not implemented */ 1806 spr_register(env, SPR_MPC_DER, "DER", 1807 SPR_NOACCESS, SPR_NOACCESS, 1808 &spr_read_generic, &spr_write_generic, 1809 0x00000000); 1810 /* XXX : not implemented */ 1811 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1812 SPR_NOACCESS, SPR_NOACCESS, 1813 &spr_read_generic, &spr_write_generic, 1814 0x00000000); 1815 /* XXX : not implemented */ 1816 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1817 SPR_NOACCESS, SPR_NOACCESS, 1818 &spr_read_generic, &spr_write_generic, 1819 0x00000000); 1820 /* XXX : not implemented */ 1821 spr_register(env, SPR_MPC_CMPE, "CMPE", 1822 SPR_NOACCESS, SPR_NOACCESS, 1823 &spr_read_generic, &spr_write_generic, 1824 0x00000000); 1825 /* XXX : not implemented */ 1826 spr_register(env, SPR_MPC_CMPF, "CMPF", 1827 SPR_NOACCESS, SPR_NOACCESS, 1828 &spr_read_generic, &spr_write_generic, 1829 0x00000000); 1830 /* XXX : not implemented */ 1831 spr_register(env, SPR_MPC_CMPG, "CMPG", 1832 SPR_NOACCESS, SPR_NOACCESS, 1833 &spr_read_generic, &spr_write_generic, 1834 0x00000000); 1835 /* XXX : not implemented */ 1836 spr_register(env, SPR_MPC_CMPH, "CMPH", 1837 SPR_NOACCESS, SPR_NOACCESS, 1838 &spr_read_generic, &spr_write_generic, 1839 0x00000000); 1840 /* XXX : not implemented */ 1841 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1842 SPR_NOACCESS, SPR_NOACCESS, 1843 &spr_read_generic, &spr_write_generic, 1844 0x00000000); 1845 /* XXX : not implemented */ 1846 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1847 SPR_NOACCESS, SPR_NOACCESS, 1848 &spr_read_generic, &spr_write_generic, 1849 0x00000000); 1850 /* XXX : not implemented */ 1851 spr_register(env, SPR_MPC_BAR, "BAR", 1852 SPR_NOACCESS, SPR_NOACCESS, 1853 &spr_read_generic, &spr_write_generic, 1854 0x00000000); 1855 /* XXX : not implemented */ 1856 spr_register(env, SPR_MPC_DPDR, "DPDR", 1857 SPR_NOACCESS, SPR_NOACCESS, 1858 &spr_read_generic, &spr_write_generic, 1859 0x00000000); 1860 /* XXX : not implemented */ 1861 spr_register(env, SPR_MPC_IMMR, "IMMR", 1862 SPR_NOACCESS, SPR_NOACCESS, 1863 &spr_read_generic, &spr_write_generic, 1864 0x00000000); 1865 } 1866 1867 static void register_5xx_sprs(CPUPPCState *env) 1868 { 1869 /* XXX : not implemented */ 1870 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1871 SPR_NOACCESS, SPR_NOACCESS, 1872 &spr_read_generic, &spr_write_generic, 1873 0x00000000); 1874 /* XXX : not implemented */ 1875 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1876 SPR_NOACCESS, SPR_NOACCESS, 1877 &spr_read_generic, &spr_write_generic, 1878 0x00000000); 1879 /* XXX : not implemented */ 1880 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1881 SPR_NOACCESS, SPR_NOACCESS, 1882 &spr_read_generic, &spr_write_generic, 1883 0x00000000); 1884 /* XXX : not implemented */ 1885 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1886 SPR_NOACCESS, SPR_NOACCESS, 1887 &spr_read_generic, &spr_write_generic, 1888 0x00000000); 1889 /* XXX : not implemented */ 1890 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1891 SPR_NOACCESS, SPR_NOACCESS, 1892 &spr_read_generic, &spr_write_generic, 1893 0x00000000); 1894 /* XXX : not implemented */ 1895 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1896 SPR_NOACCESS, SPR_NOACCESS, 1897 &spr_read_generic, &spr_write_generic, 1898 0x00000000); 1899 /* XXX : not implemented */ 1900 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1901 SPR_NOACCESS, SPR_NOACCESS, 1902 &spr_read_generic, &spr_write_generic, 1903 0x00000000); 1904 /* XXX : not implemented */ 1905 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1906 SPR_NOACCESS, SPR_NOACCESS, 1907 &spr_read_generic, &spr_write_generic, 1908 0x00000000); 1909 /* XXX : not implemented */ 1910 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1911 SPR_NOACCESS, SPR_NOACCESS, 1912 &spr_read_generic, &spr_write_generic, 1913 0x00000000); 1914 /* XXX : not implemented */ 1915 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1916 SPR_NOACCESS, SPR_NOACCESS, 1917 &spr_read_generic, &spr_write_generic, 1918 0x00000000); 1919 /* XXX : not implemented */ 1920 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1921 SPR_NOACCESS, SPR_NOACCESS, 1922 &spr_read_generic, &spr_write_generic, 1923 0x00000000); 1924 /* XXX : not implemented */ 1925 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1926 SPR_NOACCESS, SPR_NOACCESS, 1927 &spr_read_generic, &spr_write_generic, 1928 0x00000000); 1929 /* XXX : not implemented */ 1930 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1931 SPR_NOACCESS, SPR_NOACCESS, 1932 &spr_read_generic, &spr_write_generic, 1933 0x00000000); 1934 /* XXX : not implemented */ 1935 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1936 SPR_NOACCESS, SPR_NOACCESS, 1937 &spr_read_generic, &spr_write_generic, 1938 0x00000000); 1939 /* XXX : not implemented */ 1940 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1941 SPR_NOACCESS, SPR_NOACCESS, 1942 &spr_read_generic, &spr_write_generic, 1943 0x00000000); 1944 /* XXX : not implemented */ 1945 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1946 SPR_NOACCESS, SPR_NOACCESS, 1947 &spr_read_generic, &spr_write_generic, 1948 0x00000000); 1949 /* XXX : not implemented */ 1950 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1951 SPR_NOACCESS, SPR_NOACCESS, 1952 &spr_read_generic, &spr_write_generic, 1953 0x00000000); 1954 /* XXX : not implemented */ 1955 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1956 SPR_NOACCESS, SPR_NOACCESS, 1957 &spr_read_generic, &spr_write_generic, 1958 0x00000000); 1959 /* XXX : not implemented */ 1960 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1961 SPR_NOACCESS, SPR_NOACCESS, 1962 &spr_read_generic, &spr_write_generic, 1963 0x00000000); 1964 /* XXX : not implemented */ 1965 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1966 SPR_NOACCESS, SPR_NOACCESS, 1967 &spr_read_generic, &spr_write_generic, 1968 0x00000000); 1969 /* XXX : not implemented */ 1970 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1971 SPR_NOACCESS, SPR_NOACCESS, 1972 &spr_read_generic, &spr_write_generic, 1973 0x00000000); 1974 } 1975 1976 static void register_8xx_sprs(CPUPPCState *env) 1977 { 1978 /* XXX : not implemented */ 1979 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1980 SPR_NOACCESS, SPR_NOACCESS, 1981 &spr_read_generic, &spr_write_generic, 1982 0x00000000); 1983 /* XXX : not implemented */ 1984 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1985 SPR_NOACCESS, SPR_NOACCESS, 1986 &spr_read_generic, &spr_write_generic, 1987 0x00000000); 1988 /* XXX : not implemented */ 1989 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1990 SPR_NOACCESS, SPR_NOACCESS, 1991 &spr_read_generic, &spr_write_generic, 1992 0x00000000); 1993 /* XXX : not implemented */ 1994 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1995 SPR_NOACCESS, SPR_NOACCESS, 1996 &spr_read_generic, &spr_write_generic, 1997 0x00000000); 1998 /* XXX : not implemented */ 1999 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 2000 SPR_NOACCESS, SPR_NOACCESS, 2001 &spr_read_generic, &spr_write_generic, 2002 0x00000000); 2003 /* XXX : not implemented */ 2004 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 2005 SPR_NOACCESS, SPR_NOACCESS, 2006 &spr_read_generic, &spr_write_generic, 2007 0x00000000); 2008 /* XXX : not implemented */ 2009 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 2010 SPR_NOACCESS, SPR_NOACCESS, 2011 &spr_read_generic, &spr_write_generic, 2012 0x00000000); 2013 /* XXX : not implemented */ 2014 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 2015 SPR_NOACCESS, SPR_NOACCESS, 2016 &spr_read_generic, &spr_write_generic, 2017 0x00000000); 2018 /* XXX : not implemented */ 2019 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 2020 SPR_NOACCESS, SPR_NOACCESS, 2021 &spr_read_generic, &spr_write_generic, 2022 0x00000000); 2023 /* XXX : not implemented */ 2024 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 2025 SPR_NOACCESS, SPR_NOACCESS, 2026 &spr_read_generic, &spr_write_generic, 2027 0x00000000); 2028 /* XXX : not implemented */ 2029 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 2030 SPR_NOACCESS, SPR_NOACCESS, 2031 &spr_read_generic, &spr_write_generic, 2032 0x00000000); 2033 /* XXX : not implemented */ 2034 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 2035 SPR_NOACCESS, SPR_NOACCESS, 2036 &spr_read_generic, &spr_write_generic, 2037 0x00000000); 2038 /* XXX : not implemented */ 2039 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2040 SPR_NOACCESS, SPR_NOACCESS, 2041 &spr_read_generic, &spr_write_generic, 2042 0x00000000); 2043 /* XXX : not implemented */ 2044 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2045 SPR_NOACCESS, SPR_NOACCESS, 2046 &spr_read_generic, &spr_write_generic, 2047 0x00000000); 2048 /* XXX : not implemented */ 2049 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2050 SPR_NOACCESS, SPR_NOACCESS, 2051 &spr_read_generic, &spr_write_generic, 2052 0x00000000); 2053 /* XXX : not implemented */ 2054 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2055 SPR_NOACCESS, SPR_NOACCESS, 2056 &spr_read_generic, &spr_write_generic, 2057 0x00000000); 2058 /* XXX : not implemented */ 2059 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2060 SPR_NOACCESS, SPR_NOACCESS, 2061 &spr_read_generic, &spr_write_generic, 2062 0x00000000); 2063 /* XXX : not implemented */ 2064 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2065 SPR_NOACCESS, SPR_NOACCESS, 2066 &spr_read_generic, &spr_write_generic, 2067 0x00000000); 2068 /* XXX : not implemented */ 2069 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2070 SPR_NOACCESS, SPR_NOACCESS, 2071 &spr_read_generic, &spr_write_generic, 2072 0x00000000); 2073 /* XXX : not implemented */ 2074 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2075 SPR_NOACCESS, SPR_NOACCESS, 2076 &spr_read_generic, &spr_write_generic, 2077 0x00000000); 2078 /* XXX : not implemented */ 2079 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2080 SPR_NOACCESS, SPR_NOACCESS, 2081 &spr_read_generic, &spr_write_generic, 2082 0x00000000); 2083 /* XXX : not implemented */ 2084 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2085 SPR_NOACCESS, SPR_NOACCESS, 2086 &spr_read_generic, &spr_write_generic, 2087 0x00000000); 2088 /* XXX : not implemented */ 2089 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2090 SPR_NOACCESS, SPR_NOACCESS, 2091 &spr_read_generic, &spr_write_generic, 2092 0x00000000); 2093 /* XXX : not implemented */ 2094 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2095 SPR_NOACCESS, SPR_NOACCESS, 2096 &spr_read_generic, &spr_write_generic, 2097 0x00000000); 2098 /* XXX : not implemented */ 2099 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2100 SPR_NOACCESS, SPR_NOACCESS, 2101 &spr_read_generic, &spr_write_generic, 2102 0x00000000); 2103 } 2104 2105 /* 2106 * AMR => SPR 29 (Power 2.04) 2107 * CTRL => SPR 136 (Power 2.04) 2108 * CTRL => SPR 152 (Power 2.04) 2109 * SCOMC => SPR 276 (64 bits ?) 2110 * SCOMD => SPR 277 (64 bits ?) 2111 * TBU40 => SPR 286 (Power 2.04 hypv) 2112 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2113 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2114 * HDSISR => SPR 306 (Power 2.04 hypv) 2115 * HDAR => SPR 307 (Power 2.04 hypv) 2116 * PURR => SPR 309 (Power 2.04 hypv) 2117 * HDEC => SPR 310 (Power 2.04 hypv) 2118 * HIOR => SPR 311 (hypv) 2119 * RMOR => SPR 312 (970) 2120 * HRMOR => SPR 313 (Power 2.04 hypv) 2121 * HSRR0 => SPR 314 (Power 2.04 hypv) 2122 * HSRR1 => SPR 315 (Power 2.04 hypv) 2123 * LPIDR => SPR 317 (970) 2124 * EPR => SPR 702 (Power 2.04 emb) 2125 * perf => 768-783 (Power 2.04) 2126 * perf => 784-799 (Power 2.04) 2127 * PPR => SPR 896 (Power 2.04) 2128 * DABRX => 1015 (Power 2.04 hypv) 2129 * FPECR => SPR 1022 (?) 2130 * ... and more (thermal management, performance counters, ...) 2131 */ 2132 2133 /*****************************************************************************/ 2134 /* Exception vectors models */ 2135 static void init_excp_4xx_real(CPUPPCState *env) 2136 { 2137 #if !defined(CONFIG_USER_ONLY) 2138 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2139 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2140 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2141 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2142 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2143 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2144 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2145 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2146 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2147 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2148 env->ivor_mask = 0x0000FFF0UL; 2149 env->ivpr_mask = 0xFFFF0000UL; 2150 /* Hardware reset vector */ 2151 env->hreset_vector = 0xFFFFFFFCUL; 2152 #endif 2153 } 2154 2155 static void init_excp_4xx_softmmu(CPUPPCState *env) 2156 { 2157 #if !defined(CONFIG_USER_ONLY) 2158 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2159 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2160 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2161 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2162 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2163 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2164 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2165 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2166 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2167 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2168 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2169 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2170 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2171 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2172 env->ivor_mask = 0x0000FFF0UL; 2173 env->ivpr_mask = 0xFFFF0000UL; 2174 /* Hardware reset vector */ 2175 env->hreset_vector = 0xFFFFFFFCUL; 2176 #endif 2177 } 2178 2179 static void init_excp_MPC5xx(CPUPPCState *env) 2180 { 2181 #if !defined(CONFIG_USER_ONLY) 2182 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2183 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2184 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2185 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2186 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2187 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2188 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2191 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2192 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2193 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2195 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2196 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2197 env->ivor_mask = 0x0000FFF0UL; 2198 env->ivpr_mask = 0xFFFF0000UL; 2199 /* Hardware reset vector */ 2200 env->hreset_vector = 0x00000100UL; 2201 #endif 2202 } 2203 2204 static void init_excp_MPC8xx(CPUPPCState *env) 2205 { 2206 #if !defined(CONFIG_USER_ONLY) 2207 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2208 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2209 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2210 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2211 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2212 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2213 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2214 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2216 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2217 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2218 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2219 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2220 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2221 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2222 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2223 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2224 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2225 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2226 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2227 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2228 env->ivor_mask = 0x0000FFF0UL; 2229 env->ivpr_mask = 0xFFFF0000UL; 2230 /* Hardware reset vector */ 2231 env->hreset_vector = 0x00000100UL; 2232 #endif 2233 } 2234 2235 static void init_excp_G2(CPUPPCState *env) 2236 { 2237 #if !defined(CONFIG_USER_ONLY) 2238 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2239 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2240 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2241 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2242 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2243 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2244 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2245 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2246 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2247 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2248 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2249 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2250 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2251 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2252 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2253 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2254 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2255 /* Hardware reset vector */ 2256 env->hreset_vector = 0x00000100UL; 2257 #endif 2258 } 2259 2260 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2261 { 2262 #if !defined(CONFIG_USER_ONLY) 2263 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2264 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2265 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2266 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2267 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2268 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2269 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2270 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2271 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2272 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2273 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2274 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2275 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2276 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2277 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2278 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2279 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2280 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2281 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2282 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2283 env->ivor_mask = 0x0000FFF7UL; 2284 env->ivpr_mask = ivpr_mask; 2285 /* Hardware reset vector */ 2286 env->hreset_vector = 0xFFFFFFFCUL; 2287 #endif 2288 } 2289 2290 static void init_excp_BookE(CPUPPCState *env) 2291 { 2292 #if !defined(CONFIG_USER_ONLY) 2293 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2294 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2295 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2296 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2297 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2298 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2299 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2300 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2301 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2302 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2303 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2304 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2305 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2306 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2307 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2308 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2309 env->ivor_mask = 0x0000FFF0UL; 2310 env->ivpr_mask = 0xFFFF0000UL; 2311 /* Hardware reset vector */ 2312 env->hreset_vector = 0xFFFFFFFCUL; 2313 #endif 2314 } 2315 2316 static void init_excp_601(CPUPPCState *env) 2317 { 2318 #if !defined(CONFIG_USER_ONLY) 2319 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2320 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2321 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2322 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2323 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2324 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2325 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2326 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2327 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2328 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2329 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2330 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2331 /* Hardware reset vector */ 2332 env->hreset_vector = 0x00000100UL; 2333 #endif 2334 } 2335 2336 static void init_excp_602(CPUPPCState *env) 2337 { 2338 #if !defined(CONFIG_USER_ONLY) 2339 /* XXX: exception prefix has a special behavior on 602 */ 2340 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2341 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2342 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2343 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2344 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2345 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2346 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2347 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2348 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2349 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2350 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2351 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2352 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2353 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2354 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2355 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2356 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 2357 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 2358 /* Hardware reset vector */ 2359 env->hreset_vector = 0x00000100UL; 2360 #endif 2361 } 2362 2363 static void init_excp_603(CPUPPCState *env) 2364 { 2365 #if !defined(CONFIG_USER_ONLY) 2366 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2367 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2368 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2369 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2370 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2371 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2372 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2373 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2374 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2375 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2376 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2377 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2378 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2379 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2380 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2381 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2382 /* Hardware reset vector */ 2383 env->hreset_vector = 0x00000100UL; 2384 #endif 2385 } 2386 2387 static void init_excp_604(CPUPPCState *env) 2388 { 2389 #if !defined(CONFIG_USER_ONLY) 2390 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2391 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2392 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2393 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2394 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2395 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2396 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2397 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2398 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2399 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2400 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2401 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2402 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2403 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2404 /* Hardware reset vector */ 2405 env->hreset_vector = 0x00000100UL; 2406 #endif 2407 } 2408 2409 static void init_excp_7x0(CPUPPCState *env) 2410 { 2411 #if !defined(CONFIG_USER_ONLY) 2412 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2413 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2414 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2415 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2416 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2417 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2418 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2419 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2420 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2421 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2422 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2423 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2424 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2425 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2426 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2427 /* Hardware reset vector */ 2428 env->hreset_vector = 0x00000100UL; 2429 #endif 2430 } 2431 2432 static void init_excp_750cl(CPUPPCState *env) 2433 { 2434 #if !defined(CONFIG_USER_ONLY) 2435 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2436 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2437 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2438 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2439 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2440 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2441 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2442 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2443 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2444 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2445 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2446 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2447 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2448 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2449 /* Hardware reset vector */ 2450 env->hreset_vector = 0x00000100UL; 2451 #endif 2452 } 2453 2454 static void init_excp_750cx(CPUPPCState *env) 2455 { 2456 #if !defined(CONFIG_USER_ONLY) 2457 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2458 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2459 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2460 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2461 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2462 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2463 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2464 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2465 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2466 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2467 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2468 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2469 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2470 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2471 /* Hardware reset vector */ 2472 env->hreset_vector = 0x00000100UL; 2473 #endif 2474 } 2475 2476 /* XXX: Check if this is correct */ 2477 static void init_excp_7x5(CPUPPCState *env) 2478 { 2479 #if !defined(CONFIG_USER_ONLY) 2480 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2481 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2482 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2483 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2484 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2485 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2486 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2487 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2488 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2489 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2490 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2491 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2492 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2493 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2494 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2495 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2496 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2497 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2498 /* Hardware reset vector */ 2499 env->hreset_vector = 0x00000100UL; 2500 #endif 2501 } 2502 2503 static void init_excp_7400(CPUPPCState *env) 2504 { 2505 #if !defined(CONFIG_USER_ONLY) 2506 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2507 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2508 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2509 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2510 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2511 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2512 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2513 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2514 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2515 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2516 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2517 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2518 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2519 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2520 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2521 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2522 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2523 /* Hardware reset vector */ 2524 env->hreset_vector = 0x00000100UL; 2525 #endif 2526 } 2527 2528 static void init_excp_7450(CPUPPCState *env) 2529 { 2530 #if !defined(CONFIG_USER_ONLY) 2531 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2532 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2533 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2534 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2535 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2536 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2537 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2538 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2539 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2540 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2541 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2542 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2543 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2544 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2545 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2546 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2547 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2548 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2549 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2550 /* Hardware reset vector */ 2551 env->hreset_vector = 0x00000100UL; 2552 #endif 2553 } 2554 2555 #if defined(TARGET_PPC64) 2556 static void init_excp_970(CPUPPCState *env) 2557 { 2558 #if !defined(CONFIG_USER_ONLY) 2559 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2560 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2561 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2562 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2563 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2564 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2565 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2566 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2567 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2568 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2569 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2570 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2571 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2572 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2573 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2574 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2575 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2576 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2577 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2578 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2579 /* Hardware reset vector */ 2580 env->hreset_vector = 0x0000000000000100ULL; 2581 #endif 2582 } 2583 2584 static void init_excp_POWER7(CPUPPCState *env) 2585 { 2586 #if !defined(CONFIG_USER_ONLY) 2587 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2588 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2589 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2590 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2591 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2592 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2593 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2594 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2595 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2596 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2597 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2598 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2599 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2600 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2601 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2602 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2603 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2604 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2605 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2606 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2607 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2608 /* Hardware reset vector */ 2609 env->hreset_vector = 0x0000000000000100ULL; 2610 #endif 2611 } 2612 2613 static void init_excp_POWER8(CPUPPCState *env) 2614 { 2615 init_excp_POWER7(env); 2616 2617 #if !defined(CONFIG_USER_ONLY) 2618 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2619 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2620 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2621 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2622 #endif 2623 } 2624 2625 static void init_excp_POWER9(CPUPPCState *env) 2626 { 2627 init_excp_POWER8(env); 2628 2629 #if !defined(CONFIG_USER_ONLY) 2630 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2631 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2632 #endif 2633 } 2634 2635 static void init_excp_POWER10(CPUPPCState *env) 2636 { 2637 init_excp_POWER9(env); 2638 } 2639 2640 #endif 2641 2642 /*****************************************************************************/ 2643 /* Power management enable checks */ 2644 static int check_pow_none(CPUPPCState *env) 2645 { 2646 return 0; 2647 } 2648 2649 static int check_pow_nocheck(CPUPPCState *env) 2650 { 2651 return 1; 2652 } 2653 2654 static int check_pow_hid0(CPUPPCState *env) 2655 { 2656 if (env->spr[SPR_HID0] & 0x00E00000) { 2657 return 1; 2658 } 2659 2660 return 0; 2661 } 2662 2663 static int check_pow_hid0_74xx(CPUPPCState *env) 2664 { 2665 if (env->spr[SPR_HID0] & 0x00600000) { 2666 return 1; 2667 } 2668 2669 return 0; 2670 } 2671 2672 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) 2673 { 2674 return true; 2675 } 2676 2677 #ifdef TARGET_PPC64 2678 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) 2679 { 2680 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); 2681 } 2682 #endif 2683 2684 /*****************************************************************************/ 2685 /* PowerPC implementations definitions */ 2686 2687 #define POWERPC_FAMILY(_name) \ 2688 static void \ 2689 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2690 \ 2691 static const TypeInfo \ 2692 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2693 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2694 .parent = TYPE_POWERPC_CPU, \ 2695 .abstract = true, \ 2696 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2697 }; \ 2698 \ 2699 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2700 { \ 2701 type_register_static( \ 2702 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2703 } \ 2704 \ 2705 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2706 \ 2707 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2708 2709 static void init_proc_401(CPUPPCState *env) 2710 { 2711 register_40x_sprs(env); 2712 register_401_403_sprs(env); 2713 register_401_sprs(env); 2714 init_excp_4xx_real(env); 2715 env->dcache_line_size = 32; 2716 env->icache_line_size = 32; 2717 /* Allocate hardware IRQ controller */ 2718 ppc40x_irq_init(env_archcpu(env)); 2719 2720 SET_FIT_PERIOD(12, 16, 20, 24); 2721 SET_WDT_PERIOD(16, 20, 24, 28); 2722 } 2723 2724 POWERPC_FAMILY(401)(ObjectClass *oc, void *data) 2725 { 2726 DeviceClass *dc = DEVICE_CLASS(oc); 2727 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2728 2729 dc->desc = "PowerPC 401"; 2730 pcc->init_proc = init_proc_401; 2731 pcc->check_pow = check_pow_nocheck; 2732 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2733 PPC_WRTEE | PPC_DCR | 2734 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2735 PPC_CACHE_DCBZ | 2736 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2737 PPC_4xx_COMMON | PPC_40x_EXCP; 2738 pcc->msr_mask = (1ull << MSR_KEY) | 2739 (1ull << MSR_POW) | 2740 (1ull << MSR_CE) | 2741 (1ull << MSR_ILE) | 2742 (1ull << MSR_EE) | 2743 (1ull << MSR_PR) | 2744 (1ull << MSR_ME) | 2745 (1ull << MSR_DE) | 2746 (1ull << MSR_LE); 2747 pcc->mmu_model = POWERPC_MMU_REAL; 2748 pcc->excp_model = POWERPC_EXCP_40x; 2749 pcc->bus_model = PPC_FLAGS_INPUT_401; 2750 pcc->bfd_mach = bfd_mach_ppc_403; 2751 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2752 POWERPC_FLAG_BUS_CLK; 2753 } 2754 2755 static void init_proc_401x2(CPUPPCState *env) 2756 { 2757 register_40x_sprs(env); 2758 register_401_403_sprs(env); 2759 register_401x2_sprs(env); 2760 register_compress_sprs(env); 2761 /* Memory management */ 2762 #if !defined(CONFIG_USER_ONLY) 2763 env->nb_tlb = 64; 2764 env->nb_ways = 1; 2765 env->id_tlbs = 0; 2766 env->tlb_type = TLB_EMB; 2767 #endif 2768 init_excp_4xx_softmmu(env); 2769 env->dcache_line_size = 32; 2770 env->icache_line_size = 32; 2771 /* Allocate hardware IRQ controller */ 2772 ppc40x_irq_init(env_archcpu(env)); 2773 2774 SET_FIT_PERIOD(12, 16, 20, 24); 2775 SET_WDT_PERIOD(16, 20, 24, 28); 2776 } 2777 2778 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) 2779 { 2780 DeviceClass *dc = DEVICE_CLASS(oc); 2781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2782 2783 dc->desc = "PowerPC 401x2"; 2784 pcc->init_proc = init_proc_401x2; 2785 pcc->check_pow = check_pow_nocheck; 2786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2787 PPC_DCR | PPC_WRTEE | 2788 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2789 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2790 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2791 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2792 PPC_4xx_COMMON | PPC_40x_EXCP; 2793 pcc->msr_mask = (1ull << 20) | 2794 (1ull << MSR_KEY) | 2795 (1ull << MSR_POW) | 2796 (1ull << MSR_CE) | 2797 (1ull << MSR_ILE) | 2798 (1ull << MSR_EE) | 2799 (1ull << MSR_PR) | 2800 (1ull << MSR_ME) | 2801 (1ull << MSR_DE) | 2802 (1ull << MSR_IR) | 2803 (1ull << MSR_DR) | 2804 (1ull << MSR_LE); 2805 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2806 pcc->excp_model = POWERPC_EXCP_40x; 2807 pcc->bus_model = PPC_FLAGS_INPUT_401; 2808 pcc->bfd_mach = bfd_mach_ppc_403; 2809 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2810 POWERPC_FLAG_BUS_CLK; 2811 } 2812 2813 static void init_proc_401x3(CPUPPCState *env) 2814 { 2815 register_40x_sprs(env); 2816 register_401_403_sprs(env); 2817 register_401_sprs(env); 2818 register_401x2_sprs(env); 2819 register_compress_sprs(env); 2820 init_excp_4xx_softmmu(env); 2821 env->dcache_line_size = 32; 2822 env->icache_line_size = 32; 2823 /* Allocate hardware IRQ controller */ 2824 ppc40x_irq_init(env_archcpu(env)); 2825 2826 SET_FIT_PERIOD(12, 16, 20, 24); 2827 SET_WDT_PERIOD(16, 20, 24, 28); 2828 } 2829 2830 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) 2831 { 2832 DeviceClass *dc = DEVICE_CLASS(oc); 2833 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2834 2835 dc->desc = "PowerPC 401x3"; 2836 pcc->init_proc = init_proc_401x3; 2837 pcc->check_pow = check_pow_nocheck; 2838 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2839 PPC_DCR | PPC_WRTEE | 2840 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2841 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2842 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2843 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2844 PPC_4xx_COMMON | PPC_40x_EXCP; 2845 pcc->msr_mask = (1ull << 20) | 2846 (1ull << MSR_KEY) | 2847 (1ull << MSR_POW) | 2848 (1ull << MSR_CE) | 2849 (1ull << MSR_ILE) | 2850 (1ull << MSR_EE) | 2851 (1ull << MSR_PR) | 2852 (1ull << MSR_ME) | 2853 (1ull << MSR_DWE) | 2854 (1ull << MSR_DE) | 2855 (1ull << MSR_IR) | 2856 (1ull << MSR_DR) | 2857 (1ull << MSR_LE); 2858 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2859 pcc->excp_model = POWERPC_EXCP_40x; 2860 pcc->bus_model = PPC_FLAGS_INPUT_401; 2861 pcc->bfd_mach = bfd_mach_ppc_403; 2862 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2863 POWERPC_FLAG_BUS_CLK; 2864 } 2865 2866 static void init_proc_IOP480(CPUPPCState *env) 2867 { 2868 register_40x_sprs(env); 2869 register_401_403_sprs(env); 2870 register_401x2_sprs(env); 2871 register_compress_sprs(env); 2872 /* Memory management */ 2873 #if !defined(CONFIG_USER_ONLY) 2874 env->nb_tlb = 64; 2875 env->nb_ways = 1; 2876 env->id_tlbs = 0; 2877 env->tlb_type = TLB_EMB; 2878 #endif 2879 init_excp_4xx_softmmu(env); 2880 env->dcache_line_size = 32; 2881 env->icache_line_size = 32; 2882 /* Allocate hardware IRQ controller */ 2883 ppc40x_irq_init(env_archcpu(env)); 2884 2885 SET_FIT_PERIOD(8, 12, 16, 20); 2886 SET_WDT_PERIOD(16, 20, 24, 28); 2887 } 2888 2889 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) 2890 { 2891 DeviceClass *dc = DEVICE_CLASS(oc); 2892 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2893 2894 dc->desc = "IOP480"; 2895 pcc->init_proc = init_proc_IOP480; 2896 pcc->check_pow = check_pow_nocheck; 2897 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2898 PPC_DCR | PPC_WRTEE | 2899 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2900 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2901 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2902 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2903 PPC_4xx_COMMON | PPC_40x_EXCP; 2904 pcc->msr_mask = (1ull << 20) | 2905 (1ull << MSR_KEY) | 2906 (1ull << MSR_POW) | 2907 (1ull << MSR_CE) | 2908 (1ull << MSR_ILE) | 2909 (1ull << MSR_EE) | 2910 (1ull << MSR_PR) | 2911 (1ull << MSR_ME) | 2912 (1ull << MSR_DE) | 2913 (1ull << MSR_IR) | 2914 (1ull << MSR_DR) | 2915 (1ull << MSR_LE); 2916 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 2917 pcc->excp_model = POWERPC_EXCP_40x; 2918 pcc->bus_model = PPC_FLAGS_INPUT_401; 2919 pcc->bfd_mach = bfd_mach_ppc_403; 2920 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 2921 POWERPC_FLAG_BUS_CLK; 2922 } 2923 2924 static void init_proc_403(CPUPPCState *env) 2925 { 2926 register_40x_sprs(env); 2927 register_401_403_sprs(env); 2928 register_403_sprs(env); 2929 register_403_real_sprs(env); 2930 init_excp_4xx_real(env); 2931 env->dcache_line_size = 32; 2932 env->icache_line_size = 32; 2933 /* Allocate hardware IRQ controller */ 2934 ppc40x_irq_init(env_archcpu(env)); 2935 2936 SET_FIT_PERIOD(8, 12, 16, 20); 2937 SET_WDT_PERIOD(16, 20, 24, 28); 2938 } 2939 2940 POWERPC_FAMILY(403)(ObjectClass *oc, void *data) 2941 { 2942 DeviceClass *dc = DEVICE_CLASS(oc); 2943 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2944 2945 dc->desc = "PowerPC 403"; 2946 pcc->init_proc = init_proc_403; 2947 pcc->check_pow = check_pow_nocheck; 2948 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2949 PPC_DCR | PPC_WRTEE | 2950 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2951 PPC_CACHE_DCBZ | 2952 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2953 PPC_4xx_COMMON | PPC_40x_EXCP; 2954 pcc->msr_mask = (1ull << MSR_POW) | 2955 (1ull << MSR_CE) | 2956 (1ull << MSR_ILE) | 2957 (1ull << MSR_EE) | 2958 (1ull << MSR_PR) | 2959 (1ull << MSR_ME) | 2960 (1ull << MSR_PE) | 2961 (1ull << MSR_PX) | 2962 (1ull << MSR_LE); 2963 pcc->mmu_model = POWERPC_MMU_REAL; 2964 pcc->excp_model = POWERPC_EXCP_40x; 2965 pcc->bus_model = PPC_FLAGS_INPUT_401; 2966 pcc->bfd_mach = bfd_mach_ppc_403; 2967 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 2968 POWERPC_FLAG_BUS_CLK; 2969 } 2970 2971 static void init_proc_403GCX(CPUPPCState *env) 2972 { 2973 register_40x_sprs(env); 2974 register_401_403_sprs(env); 2975 register_403_sprs(env); 2976 register_403_real_sprs(env); 2977 register_403_mmu_sprs(env); 2978 /* Bus access control */ 2979 /* not emulated, as QEMU never does speculative access */ 2980 spr_register(env, SPR_40x_SGR, "SGR", 2981 SPR_NOACCESS, SPR_NOACCESS, 2982 &spr_read_generic, &spr_write_generic, 2983 0xFFFFFFFF); 2984 /* not emulated, as QEMU do not emulate caches */ 2985 spr_register(env, SPR_40x_DCWR, "DCWR", 2986 SPR_NOACCESS, SPR_NOACCESS, 2987 &spr_read_generic, &spr_write_generic, 2988 0x00000000); 2989 /* Memory management */ 2990 #if !defined(CONFIG_USER_ONLY) 2991 env->nb_tlb = 64; 2992 env->nb_ways = 1; 2993 env->id_tlbs = 0; 2994 env->tlb_type = TLB_EMB; 2995 #endif 2996 init_excp_4xx_softmmu(env); 2997 env->dcache_line_size = 32; 2998 env->icache_line_size = 32; 2999 /* Allocate hardware IRQ controller */ 3000 ppc40x_irq_init(env_archcpu(env)); 3001 3002 SET_FIT_PERIOD(8, 12, 16, 20); 3003 SET_WDT_PERIOD(16, 20, 24, 28); 3004 } 3005 3006 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) 3007 { 3008 DeviceClass *dc = DEVICE_CLASS(oc); 3009 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3010 3011 dc->desc = "PowerPC 403 GCX"; 3012 pcc->init_proc = init_proc_403GCX; 3013 pcc->check_pow = check_pow_nocheck; 3014 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3015 PPC_DCR | PPC_WRTEE | 3016 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3017 PPC_CACHE_DCBZ | 3018 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3019 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3020 PPC_4xx_COMMON | PPC_40x_EXCP; 3021 pcc->msr_mask = (1ull << MSR_POW) | 3022 (1ull << MSR_CE) | 3023 (1ull << MSR_ILE) | 3024 (1ull << MSR_EE) | 3025 (1ull << MSR_PR) | 3026 (1ull << MSR_ME) | 3027 (1ull << MSR_PE) | 3028 (1ull << MSR_PX) | 3029 (1ull << MSR_LE); 3030 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3031 pcc->excp_model = POWERPC_EXCP_40x; 3032 pcc->bus_model = PPC_FLAGS_INPUT_401; 3033 pcc->bfd_mach = bfd_mach_ppc_403; 3034 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3035 POWERPC_FLAG_BUS_CLK; 3036 } 3037 3038 static void init_proc_405(CPUPPCState *env) 3039 { 3040 /* Time base */ 3041 register_tbl(env); 3042 register_40x_sprs(env); 3043 register_405_sprs(env); 3044 /* Bus access control */ 3045 /* not emulated, as QEMU never does speculative access */ 3046 spr_register(env, SPR_40x_SGR, "SGR", 3047 SPR_NOACCESS, SPR_NOACCESS, 3048 &spr_read_generic, &spr_write_generic, 3049 0xFFFFFFFF); 3050 /* not emulated, as QEMU do not emulate caches */ 3051 spr_register(env, SPR_40x_DCWR, "DCWR", 3052 SPR_NOACCESS, SPR_NOACCESS, 3053 &spr_read_generic, &spr_write_generic, 3054 0x00000000); 3055 /* Memory management */ 3056 #if !defined(CONFIG_USER_ONLY) 3057 env->nb_tlb = 64; 3058 env->nb_ways = 1; 3059 env->id_tlbs = 0; 3060 env->tlb_type = TLB_EMB; 3061 #endif 3062 init_excp_4xx_softmmu(env); 3063 env->dcache_line_size = 32; 3064 env->icache_line_size = 32; 3065 /* Allocate hardware IRQ controller */ 3066 ppc40x_irq_init(env_archcpu(env)); 3067 3068 SET_FIT_PERIOD(8, 12, 16, 20); 3069 SET_WDT_PERIOD(16, 20, 24, 28); 3070 } 3071 3072 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 3073 { 3074 DeviceClass *dc = DEVICE_CLASS(oc); 3075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3076 3077 dc->desc = "PowerPC 405"; 3078 pcc->init_proc = init_proc_405; 3079 pcc->check_pow = check_pow_nocheck; 3080 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3081 PPC_DCR | PPC_WRTEE | 3082 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3083 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3084 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3085 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3086 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 3087 pcc->msr_mask = (1ull << MSR_POW) | 3088 (1ull << MSR_CE) | 3089 (1ull << MSR_EE) | 3090 (1ull << MSR_PR) | 3091 (1ull << MSR_FP) | 3092 (1ull << MSR_DWE) | 3093 (1ull << MSR_DE) | 3094 (1ull << MSR_IR) | 3095 (1ull << MSR_DR); 3096 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 3097 pcc->excp_model = POWERPC_EXCP_40x; 3098 pcc->bus_model = PPC_FLAGS_INPUT_405; 3099 pcc->bfd_mach = bfd_mach_ppc_403; 3100 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3101 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3102 } 3103 3104 static void init_proc_440EP(CPUPPCState *env) 3105 { 3106 /* Time base */ 3107 register_tbl(env); 3108 register_BookE_sprs(env, 0x000000000000FFFFULL); 3109 register_440_sprs(env); 3110 register_usprgh_sprs(env); 3111 /* Processor identification */ 3112 spr_register(env, SPR_BOOKE_PIR, "PIR", 3113 SPR_NOACCESS, SPR_NOACCESS, 3114 &spr_read_generic, &spr_write_pir, 3115 0x00000000); 3116 /* XXX : not implemented */ 3117 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3118 SPR_NOACCESS, SPR_NOACCESS, 3119 &spr_read_generic, &spr_write_generic, 3120 0x00000000); 3121 /* XXX : not implemented */ 3122 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3123 SPR_NOACCESS, SPR_NOACCESS, 3124 &spr_read_generic, &spr_write_generic, 3125 0x00000000); 3126 /* XXX : not implemented */ 3127 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3128 SPR_NOACCESS, SPR_NOACCESS, 3129 &spr_read_generic, &spr_write_generic, 3130 0x00000000); 3131 /* XXX : not implemented */ 3132 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3133 SPR_NOACCESS, SPR_NOACCESS, 3134 &spr_read_generic, &spr_write_generic, 3135 0x00000000); 3136 /* XXX : not implemented */ 3137 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3138 SPR_NOACCESS, SPR_NOACCESS, 3139 &spr_read_generic, &spr_write_generic, 3140 0x00000000); 3141 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3142 SPR_NOACCESS, SPR_NOACCESS, 3143 &spr_read_generic, &spr_write_generic, 3144 0x00000000); 3145 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3146 SPR_NOACCESS, SPR_NOACCESS, 3147 &spr_read_generic, &spr_write_generic, 3148 0x00000000); 3149 /* XXX : not implemented */ 3150 spr_register(env, SPR_440_CCR1, "CCR1", 3151 SPR_NOACCESS, SPR_NOACCESS, 3152 &spr_read_generic, &spr_write_generic, 3153 0x00000000); 3154 /* Memory management */ 3155 #if !defined(CONFIG_USER_ONLY) 3156 env->nb_tlb = 64; 3157 env->nb_ways = 1; 3158 env->id_tlbs = 0; 3159 env->tlb_type = TLB_EMB; 3160 #endif 3161 init_excp_BookE(env); 3162 env->dcache_line_size = 32; 3163 env->icache_line_size = 32; 3164 ppc40x_irq_init(env_archcpu(env)); 3165 3166 SET_FIT_PERIOD(12, 16, 20, 24); 3167 SET_WDT_PERIOD(20, 24, 28, 32); 3168 } 3169 3170 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 3171 { 3172 DeviceClass *dc = DEVICE_CLASS(oc); 3173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3174 3175 dc->desc = "PowerPC 440 EP"; 3176 pcc->init_proc = init_proc_440EP; 3177 pcc->check_pow = check_pow_nocheck; 3178 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3179 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3180 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3181 PPC_FLOAT_STFIWX | 3182 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3183 PPC_CACHE | PPC_CACHE_ICBI | 3184 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3185 PPC_MEM_TLBSYNC | PPC_MFTB | 3186 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3187 PPC_440_SPEC; 3188 pcc->msr_mask = (1ull << MSR_POW) | 3189 (1ull << MSR_CE) | 3190 (1ull << MSR_EE) | 3191 (1ull << MSR_PR) | 3192 (1ull << MSR_FP) | 3193 (1ull << MSR_ME) | 3194 (1ull << MSR_FE0) | 3195 (1ull << MSR_DWE) | 3196 (1ull << MSR_DE) | 3197 (1ull << MSR_FE1) | 3198 (1ull << MSR_IR) | 3199 (1ull << MSR_DR); 3200 pcc->mmu_model = POWERPC_MMU_BOOKE; 3201 pcc->excp_model = POWERPC_EXCP_BOOKE; 3202 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3203 pcc->bfd_mach = bfd_mach_ppc_403; 3204 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3205 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3206 } 3207 3208 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 3209 { 3210 DeviceClass *dc = DEVICE_CLASS(oc); 3211 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3212 3213 dc->desc = "PowerPC 460 EX"; 3214 pcc->init_proc = init_proc_440EP; 3215 pcc->check_pow = check_pow_nocheck; 3216 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3217 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 3218 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 3219 PPC_FLOAT_STFIWX | 3220 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 3221 PPC_CACHE | PPC_CACHE_ICBI | 3222 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3223 PPC_MEM_TLBSYNC | PPC_MFTB | 3224 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3225 PPC_440_SPEC; 3226 pcc->msr_mask = (1ull << MSR_POW) | 3227 (1ull << MSR_CE) | 3228 (1ull << MSR_EE) | 3229 (1ull << MSR_PR) | 3230 (1ull << MSR_FP) | 3231 (1ull << MSR_ME) | 3232 (1ull << MSR_FE0) | 3233 (1ull << MSR_DWE) | 3234 (1ull << MSR_DE) | 3235 (1ull << MSR_FE1) | 3236 (1ull << MSR_IR) | 3237 (1ull << MSR_DR); 3238 pcc->mmu_model = POWERPC_MMU_BOOKE; 3239 pcc->excp_model = POWERPC_EXCP_BOOKE; 3240 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3241 pcc->bfd_mach = bfd_mach_ppc_403; 3242 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3243 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3244 } 3245 3246 static void init_proc_440GP(CPUPPCState *env) 3247 { 3248 /* Time base */ 3249 register_tbl(env); 3250 register_BookE_sprs(env, 0x000000000000FFFFULL); 3251 register_440_sprs(env); 3252 register_usprgh_sprs(env); 3253 /* Processor identification */ 3254 spr_register(env, SPR_BOOKE_PIR, "PIR", 3255 SPR_NOACCESS, SPR_NOACCESS, 3256 &spr_read_generic, &spr_write_pir, 3257 0x00000000); 3258 /* XXX : not implemented */ 3259 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3260 SPR_NOACCESS, SPR_NOACCESS, 3261 &spr_read_generic, &spr_write_generic, 3262 0x00000000); 3263 /* XXX : not implemented */ 3264 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3265 SPR_NOACCESS, SPR_NOACCESS, 3266 &spr_read_generic, &spr_write_generic, 3267 0x00000000); 3268 /* XXX : not implemented */ 3269 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3270 SPR_NOACCESS, SPR_NOACCESS, 3271 &spr_read_generic, &spr_write_generic, 3272 0x00000000); 3273 /* XXX : not implemented */ 3274 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3275 SPR_NOACCESS, SPR_NOACCESS, 3276 &spr_read_generic, &spr_write_generic, 3277 0x00000000); 3278 /* Memory management */ 3279 #if !defined(CONFIG_USER_ONLY) 3280 env->nb_tlb = 64; 3281 env->nb_ways = 1; 3282 env->id_tlbs = 0; 3283 env->tlb_type = TLB_EMB; 3284 #endif 3285 init_excp_BookE(env); 3286 env->dcache_line_size = 32; 3287 env->icache_line_size = 32; 3288 /* XXX: TODO: allocate internal IRQ controller */ 3289 3290 SET_FIT_PERIOD(12, 16, 20, 24); 3291 SET_WDT_PERIOD(20, 24, 28, 32); 3292 } 3293 3294 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 3295 { 3296 DeviceClass *dc = DEVICE_CLASS(oc); 3297 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3298 3299 dc->desc = "PowerPC 440 GP"; 3300 pcc->init_proc = init_proc_440GP; 3301 pcc->check_pow = check_pow_nocheck; 3302 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3303 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 3304 PPC_CACHE | PPC_CACHE_ICBI | 3305 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3306 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 3307 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3308 PPC_440_SPEC; 3309 pcc->msr_mask = (1ull << MSR_POW) | 3310 (1ull << MSR_CE) | 3311 (1ull << MSR_EE) | 3312 (1ull << MSR_PR) | 3313 (1ull << MSR_FP) | 3314 (1ull << MSR_ME) | 3315 (1ull << MSR_FE0) | 3316 (1ull << MSR_DWE) | 3317 (1ull << MSR_DE) | 3318 (1ull << MSR_FE1) | 3319 (1ull << MSR_IR) | 3320 (1ull << MSR_DR); 3321 pcc->mmu_model = POWERPC_MMU_BOOKE; 3322 pcc->excp_model = POWERPC_EXCP_BOOKE; 3323 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3324 pcc->bfd_mach = bfd_mach_ppc_403; 3325 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3326 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3327 } 3328 3329 static void init_proc_440x4(CPUPPCState *env) 3330 { 3331 /* Time base */ 3332 register_tbl(env); 3333 register_BookE_sprs(env, 0x000000000000FFFFULL); 3334 register_440_sprs(env); 3335 register_usprgh_sprs(env); 3336 /* Processor identification */ 3337 spr_register(env, SPR_BOOKE_PIR, "PIR", 3338 SPR_NOACCESS, SPR_NOACCESS, 3339 &spr_read_generic, &spr_write_pir, 3340 0x00000000); 3341 /* XXX : not implemented */ 3342 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_generic, 3345 0x00000000); 3346 /* XXX : not implemented */ 3347 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3348 SPR_NOACCESS, SPR_NOACCESS, 3349 &spr_read_generic, &spr_write_generic, 3350 0x00000000); 3351 /* XXX : not implemented */ 3352 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_generic, 3355 0x00000000); 3356 /* XXX : not implemented */ 3357 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3358 SPR_NOACCESS, SPR_NOACCESS, 3359 &spr_read_generic, &spr_write_generic, 3360 0x00000000); 3361 /* Memory management */ 3362 #if !defined(CONFIG_USER_ONLY) 3363 env->nb_tlb = 64; 3364 env->nb_ways = 1; 3365 env->id_tlbs = 0; 3366 env->tlb_type = TLB_EMB; 3367 #endif 3368 init_excp_BookE(env); 3369 env->dcache_line_size = 32; 3370 env->icache_line_size = 32; 3371 /* XXX: TODO: allocate internal IRQ controller */ 3372 3373 SET_FIT_PERIOD(12, 16, 20, 24); 3374 SET_WDT_PERIOD(20, 24, 28, 32); 3375 } 3376 3377 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 3378 { 3379 DeviceClass *dc = DEVICE_CLASS(oc); 3380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3381 3382 dc->desc = "PowerPC 440x4"; 3383 pcc->init_proc = init_proc_440x4; 3384 pcc->check_pow = check_pow_nocheck; 3385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3386 PPC_DCR | PPC_WRTEE | 3387 PPC_CACHE | PPC_CACHE_ICBI | 3388 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3389 PPC_MEM_TLBSYNC | PPC_MFTB | 3390 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3391 PPC_440_SPEC; 3392 pcc->msr_mask = (1ull << MSR_POW) | 3393 (1ull << MSR_CE) | 3394 (1ull << MSR_EE) | 3395 (1ull << MSR_PR) | 3396 (1ull << MSR_FP) | 3397 (1ull << MSR_ME) | 3398 (1ull << MSR_FE0) | 3399 (1ull << MSR_DWE) | 3400 (1ull << MSR_DE) | 3401 (1ull << MSR_FE1) | 3402 (1ull << MSR_IR) | 3403 (1ull << MSR_DR); 3404 pcc->mmu_model = POWERPC_MMU_BOOKE; 3405 pcc->excp_model = POWERPC_EXCP_BOOKE; 3406 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3407 pcc->bfd_mach = bfd_mach_ppc_403; 3408 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3409 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3410 } 3411 3412 static void init_proc_440x5(CPUPPCState *env) 3413 { 3414 /* Time base */ 3415 register_tbl(env); 3416 register_BookE_sprs(env, 0x000000000000FFFFULL); 3417 register_440_sprs(env); 3418 register_usprgh_sprs(env); 3419 /* Processor identification */ 3420 spr_register(env, SPR_BOOKE_PIR, "PIR", 3421 SPR_NOACCESS, SPR_NOACCESS, 3422 &spr_read_generic, &spr_write_pir, 3423 0x00000000); 3424 /* XXX : not implemented */ 3425 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3426 SPR_NOACCESS, SPR_NOACCESS, 3427 &spr_read_generic, &spr_write_generic, 3428 0x00000000); 3429 /* XXX : not implemented */ 3430 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3431 SPR_NOACCESS, SPR_NOACCESS, 3432 &spr_read_generic, &spr_write_generic, 3433 0x00000000); 3434 /* XXX : not implemented */ 3435 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3436 SPR_NOACCESS, SPR_NOACCESS, 3437 &spr_read_generic, &spr_write_generic, 3438 0x00000000); 3439 /* XXX : not implemented */ 3440 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3441 SPR_NOACCESS, SPR_NOACCESS, 3442 &spr_read_generic, &spr_write_generic, 3443 0x00000000); 3444 /* XXX : not implemented */ 3445 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3446 SPR_NOACCESS, SPR_NOACCESS, 3447 &spr_read_generic, &spr_write_generic, 3448 0x00000000); 3449 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3450 SPR_NOACCESS, SPR_NOACCESS, 3451 &spr_read_generic, &spr_write_generic, 3452 0x00000000); 3453 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3454 SPR_NOACCESS, SPR_NOACCESS, 3455 &spr_read_generic, &spr_write_generic, 3456 0x00000000); 3457 /* XXX : not implemented */ 3458 spr_register(env, SPR_440_CCR1, "CCR1", 3459 SPR_NOACCESS, SPR_NOACCESS, 3460 &spr_read_generic, &spr_write_generic, 3461 0x00000000); 3462 /* Memory management */ 3463 #if !defined(CONFIG_USER_ONLY) 3464 env->nb_tlb = 64; 3465 env->nb_ways = 1; 3466 env->id_tlbs = 0; 3467 env->tlb_type = TLB_EMB; 3468 #endif 3469 init_excp_BookE(env); 3470 env->dcache_line_size = 32; 3471 env->icache_line_size = 32; 3472 ppc40x_irq_init(env_archcpu(env)); 3473 3474 SET_FIT_PERIOD(12, 16, 20, 24); 3475 SET_WDT_PERIOD(20, 24, 28, 32); 3476 } 3477 3478 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 3479 { 3480 DeviceClass *dc = DEVICE_CLASS(oc); 3481 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3482 3483 dc->desc = "PowerPC 440x5"; 3484 pcc->init_proc = init_proc_440x5; 3485 pcc->check_pow = check_pow_nocheck; 3486 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3487 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3488 PPC_CACHE | PPC_CACHE_ICBI | 3489 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3490 PPC_MEM_TLBSYNC | PPC_MFTB | 3491 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3492 PPC_440_SPEC; 3493 pcc->msr_mask = (1ull << MSR_POW) | 3494 (1ull << MSR_CE) | 3495 (1ull << MSR_EE) | 3496 (1ull << MSR_PR) | 3497 (1ull << MSR_FP) | 3498 (1ull << MSR_ME) | 3499 (1ull << MSR_FE0) | 3500 (1ull << MSR_DWE) | 3501 (1ull << MSR_DE) | 3502 (1ull << MSR_FE1) | 3503 (1ull << MSR_IR) | 3504 (1ull << MSR_DR); 3505 pcc->mmu_model = POWERPC_MMU_BOOKE; 3506 pcc->excp_model = POWERPC_EXCP_BOOKE; 3507 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3508 pcc->bfd_mach = bfd_mach_ppc_403; 3509 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3510 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3511 } 3512 3513 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 3514 { 3515 DeviceClass *dc = DEVICE_CLASS(oc); 3516 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3517 3518 dc->desc = "PowerPC 440x5 with double precision FPU"; 3519 pcc->init_proc = init_proc_440x5; 3520 pcc->check_pow = check_pow_nocheck; 3521 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3522 PPC_FLOAT | PPC_FLOAT_FSQRT | 3523 PPC_FLOAT_STFIWX | 3524 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 3525 PPC_CACHE | PPC_CACHE_ICBI | 3526 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3527 PPC_MEM_TLBSYNC | PPC_MFTB | 3528 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 3529 PPC_440_SPEC; 3530 pcc->insns_flags2 = PPC2_FP_CVT_S64; 3531 pcc->msr_mask = (1ull << MSR_POW) | 3532 (1ull << MSR_CE) | 3533 (1ull << MSR_EE) | 3534 (1ull << MSR_PR) | 3535 (1ull << MSR_FP) | 3536 (1ull << MSR_ME) | 3537 (1ull << MSR_FE0) | 3538 (1ull << MSR_DWE) | 3539 (1ull << MSR_DE) | 3540 (1ull << MSR_FE1) | 3541 (1ull << MSR_IR) | 3542 (1ull << MSR_DR); 3543 pcc->mmu_model = POWERPC_MMU_BOOKE; 3544 pcc->excp_model = POWERPC_EXCP_BOOKE; 3545 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3546 pcc->bfd_mach = bfd_mach_ppc_403; 3547 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3548 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3549 } 3550 3551 static void init_proc_MPC5xx(CPUPPCState *env) 3552 { 3553 /* Time base */ 3554 register_tbl(env); 3555 register_5xx_8xx_sprs(env); 3556 register_5xx_sprs(env); 3557 init_excp_MPC5xx(env); 3558 env->dcache_line_size = 32; 3559 env->icache_line_size = 32; 3560 /* XXX: TODO: allocate internal IRQ controller */ 3561 } 3562 3563 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 3564 { 3565 DeviceClass *dc = DEVICE_CLASS(oc); 3566 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3567 3568 dc->desc = "Freescale 5xx cores (aka RCPU)"; 3569 pcc->init_proc = init_proc_MPC5xx; 3570 pcc->check_pow = check_pow_none; 3571 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3572 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3573 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 3574 PPC_MFTB; 3575 pcc->msr_mask = (1ull << MSR_ILE) | 3576 (1ull << MSR_EE) | 3577 (1ull << MSR_PR) | 3578 (1ull << MSR_FP) | 3579 (1ull << MSR_ME) | 3580 (1ull << MSR_FE0) | 3581 (1ull << MSR_SE) | 3582 (1ull << MSR_DE) | 3583 (1ull << MSR_FE1) | 3584 (1ull << MSR_EP) | 3585 (1ull << MSR_RI) | 3586 (1ull << MSR_LE); 3587 pcc->mmu_model = POWERPC_MMU_REAL; 3588 pcc->excp_model = POWERPC_EXCP_603; 3589 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3590 pcc->bfd_mach = bfd_mach_ppc_505; 3591 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3592 POWERPC_FLAG_BUS_CLK; 3593 } 3594 3595 static void init_proc_MPC8xx(CPUPPCState *env) 3596 { 3597 /* Time base */ 3598 register_tbl(env); 3599 register_5xx_8xx_sprs(env); 3600 register_8xx_sprs(env); 3601 init_excp_MPC8xx(env); 3602 env->dcache_line_size = 32; 3603 env->icache_line_size = 32; 3604 /* XXX: TODO: allocate internal IRQ controller */ 3605 } 3606 3607 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 3608 { 3609 DeviceClass *dc = DEVICE_CLASS(oc); 3610 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3611 3612 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 3613 pcc->init_proc = init_proc_MPC8xx; 3614 pcc->check_pow = check_pow_none; 3615 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3616 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3617 PPC_CACHE_ICBI | PPC_MFTB; 3618 pcc->msr_mask = (1ull << MSR_ILE) | 3619 (1ull << MSR_EE) | 3620 (1ull << MSR_PR) | 3621 (1ull << MSR_FP) | 3622 (1ull << MSR_ME) | 3623 (1ull << MSR_SE) | 3624 (1ull << MSR_DE) | 3625 (1ull << MSR_EP) | 3626 (1ull << MSR_IR) | 3627 (1ull << MSR_DR) | 3628 (1ull << MSR_RI) | 3629 (1ull << MSR_LE); 3630 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3631 pcc->excp_model = POWERPC_EXCP_603; 3632 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3633 pcc->bfd_mach = bfd_mach_ppc_860; 3634 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3635 POWERPC_FLAG_BUS_CLK; 3636 } 3637 3638 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3639 3640 static void init_proc_G2(CPUPPCState *env) 3641 { 3642 register_ne_601_sprs(env); 3643 register_sdr1_sprs(env); 3644 register_G2_755_sprs(env); 3645 register_G2_sprs(env); 3646 /* Time base */ 3647 register_tbl(env); 3648 /* External access control */ 3649 /* XXX : not implemented */ 3650 spr_register(env, SPR_EAR, "EAR", 3651 SPR_NOACCESS, SPR_NOACCESS, 3652 &spr_read_generic, &spr_write_generic, 3653 0x00000000); 3654 /* Hardware implementation register */ 3655 /* XXX : not implemented */ 3656 spr_register(env, SPR_HID0, "HID0", 3657 SPR_NOACCESS, SPR_NOACCESS, 3658 &spr_read_generic, &spr_write_generic, 3659 0x00000000); 3660 /* XXX : not implemented */ 3661 spr_register(env, SPR_HID1, "HID1", 3662 SPR_NOACCESS, SPR_NOACCESS, 3663 &spr_read_generic, &spr_write_generic, 3664 0x00000000); 3665 /* XXX : not implemented */ 3666 spr_register(env, SPR_HID2, "HID2", 3667 SPR_NOACCESS, SPR_NOACCESS, 3668 &spr_read_generic, &spr_write_generic, 3669 0x00000000); 3670 /* Memory management */ 3671 register_low_BATs(env); 3672 register_high_BATs(env); 3673 register_6xx_7xx_soft_tlb(env, 64, 2); 3674 init_excp_G2(env); 3675 env->dcache_line_size = 32; 3676 env->icache_line_size = 32; 3677 /* Allocate hardware IRQ controller */ 3678 ppc6xx_irq_init(env_archcpu(env)); 3679 } 3680 3681 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3682 { 3683 DeviceClass *dc = DEVICE_CLASS(oc); 3684 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3685 3686 dc->desc = "PowerPC G2"; 3687 pcc->init_proc = init_proc_G2; 3688 pcc->check_pow = check_pow_hid0; 3689 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3690 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3691 PPC_FLOAT_STFIWX | 3692 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3693 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3694 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3695 PPC_SEGMENT | PPC_EXTERN; 3696 pcc->msr_mask = (1ull << MSR_POW) | 3697 (1ull << MSR_TGPR) | 3698 (1ull << MSR_EE) | 3699 (1ull << MSR_PR) | 3700 (1ull << MSR_FP) | 3701 (1ull << MSR_ME) | 3702 (1ull << MSR_FE0) | 3703 (1ull << MSR_SE) | 3704 (1ull << MSR_DE) | 3705 (1ull << MSR_FE1) | 3706 (1ull << MSR_AL) | 3707 (1ull << MSR_EP) | 3708 (1ull << MSR_IR) | 3709 (1ull << MSR_DR) | 3710 (1ull << MSR_RI); 3711 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3712 pcc->excp_model = POWERPC_EXCP_G2; 3713 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3714 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3715 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3716 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3717 } 3718 3719 static void init_proc_G2LE(CPUPPCState *env) 3720 { 3721 register_ne_601_sprs(env); 3722 register_sdr1_sprs(env); 3723 register_G2_755_sprs(env); 3724 register_G2_sprs(env); 3725 /* Time base */ 3726 register_tbl(env); 3727 /* External access control */ 3728 /* XXX : not implemented */ 3729 spr_register(env, SPR_EAR, "EAR", 3730 SPR_NOACCESS, SPR_NOACCESS, 3731 &spr_read_generic, &spr_write_generic, 3732 0x00000000); 3733 /* Hardware implementation register */ 3734 /* XXX : not implemented */ 3735 spr_register(env, SPR_HID0, "HID0", 3736 SPR_NOACCESS, SPR_NOACCESS, 3737 &spr_read_generic, &spr_write_generic, 3738 0x00000000); 3739 /* XXX : not implemented */ 3740 spr_register(env, SPR_HID1, "HID1", 3741 SPR_NOACCESS, SPR_NOACCESS, 3742 &spr_read_generic, &spr_write_generic, 3743 0x00000000); 3744 /* XXX : not implemented */ 3745 spr_register(env, SPR_HID2, "HID2", 3746 SPR_NOACCESS, SPR_NOACCESS, 3747 &spr_read_generic, &spr_write_generic, 3748 0x00000000); 3749 3750 /* Memory management */ 3751 register_low_BATs(env); 3752 register_high_BATs(env); 3753 register_6xx_7xx_soft_tlb(env, 64, 2); 3754 init_excp_G2(env); 3755 env->dcache_line_size = 32; 3756 env->icache_line_size = 32; 3757 /* Allocate hardware IRQ controller */ 3758 ppc6xx_irq_init(env_archcpu(env)); 3759 } 3760 3761 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3762 { 3763 DeviceClass *dc = DEVICE_CLASS(oc); 3764 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3765 3766 dc->desc = "PowerPC G2LE"; 3767 pcc->init_proc = init_proc_G2LE; 3768 pcc->check_pow = check_pow_hid0; 3769 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3770 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3771 PPC_FLOAT_STFIWX | 3772 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3773 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3774 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3775 PPC_SEGMENT | PPC_EXTERN; 3776 pcc->msr_mask = (1ull << MSR_POW) | 3777 (1ull << MSR_TGPR) | 3778 (1ull << MSR_ILE) | 3779 (1ull << MSR_EE) | 3780 (1ull << MSR_PR) | 3781 (1ull << MSR_FP) | 3782 (1ull << MSR_ME) | 3783 (1ull << MSR_FE0) | 3784 (1ull << MSR_SE) | 3785 (1ull << MSR_DE) | 3786 (1ull << MSR_FE1) | 3787 (1ull << MSR_AL) | 3788 (1ull << MSR_EP) | 3789 (1ull << MSR_IR) | 3790 (1ull << MSR_DR) | 3791 (1ull << MSR_RI) | 3792 (1ull << MSR_LE); 3793 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3794 pcc->excp_model = POWERPC_EXCP_G2; 3795 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3796 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3797 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3798 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3799 } 3800 3801 static void init_proc_e200(CPUPPCState *env) 3802 { 3803 /* Time base */ 3804 register_tbl(env); 3805 register_BookE_sprs(env, 0x000000070000FFFFULL); 3806 /* XXX : not implemented */ 3807 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3808 &spr_read_spefscr, &spr_write_spefscr, 3809 &spr_read_spefscr, &spr_write_spefscr, 3810 0x00000000); 3811 /* Memory management */ 3812 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3813 /* XXX : not implemented */ 3814 spr_register(env, SPR_HID0, "HID0", 3815 SPR_NOACCESS, SPR_NOACCESS, 3816 &spr_read_generic, &spr_write_generic, 3817 0x00000000); 3818 /* XXX : not implemented */ 3819 spr_register(env, SPR_HID1, "HID1", 3820 SPR_NOACCESS, SPR_NOACCESS, 3821 &spr_read_generic, &spr_write_generic, 3822 0x00000000); 3823 /* XXX : not implemented */ 3824 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3825 SPR_NOACCESS, SPR_NOACCESS, 3826 &spr_read_generic, &spr_write_generic, 3827 0x00000000); 3828 /* XXX : not implemented */ 3829 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3830 SPR_NOACCESS, SPR_NOACCESS, 3831 &spr_read_generic, &spr_write_generic, 3832 0x00000000); 3833 /* XXX : not implemented */ 3834 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3835 SPR_NOACCESS, SPR_NOACCESS, 3836 &spr_read_generic, &spr_write_generic, 3837 0x00000000); 3838 /* XXX : not implemented */ 3839 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3840 SPR_NOACCESS, SPR_NOACCESS, 3841 &spr_read_generic, &spr_write_generic, 3842 0x00000000); 3843 /* XXX : not implemented */ 3844 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3845 SPR_NOACCESS, SPR_NOACCESS, 3846 &spr_read_generic, &spr_write_generic, 3847 0x00000000); 3848 /* XXX : not implemented */ 3849 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3850 &spr_read_generic, SPR_NOACCESS, 3851 &spr_read_generic, SPR_NOACCESS, 3852 0x00000000); 3853 /* XXX : not implemented */ 3854 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3855 SPR_NOACCESS, SPR_NOACCESS, 3856 &spr_read_generic, &spr_write_generic, 3857 0x00000000); 3858 /* XXX : not implemented */ 3859 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3860 SPR_NOACCESS, SPR_NOACCESS, 3861 &spr_read_generic, &spr_write_generic, 3862 0x00000000); 3863 /* XXX : not implemented */ 3864 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3865 SPR_NOACCESS, SPR_NOACCESS, 3866 &spr_read_generic, &spr_write_generic, 3867 0x00000000); 3868 /* XXX : not implemented */ 3869 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3870 SPR_NOACCESS, SPR_NOACCESS, 3871 &spr_read_generic, &spr_write_generic, 3872 0x00000000); 3873 /* XXX : not implemented */ 3874 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3875 SPR_NOACCESS, SPR_NOACCESS, 3876 &spr_read_generic, &spr_write_generic, 3877 0x00000000); 3878 /* XXX : not implemented */ 3879 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3880 SPR_NOACCESS, SPR_NOACCESS, 3881 &spr_read_generic, &spr_write_generic, 3882 0x00000000); 3883 /* XXX : not implemented */ 3884 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3885 SPR_NOACCESS, SPR_NOACCESS, 3886 &spr_read_generic, &spr_write_generic, 3887 0x00000000); /* TOFIX */ 3888 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3889 SPR_NOACCESS, SPR_NOACCESS, 3890 &spr_read_generic, &spr_write_generic, 3891 0x00000000); 3892 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3893 SPR_NOACCESS, SPR_NOACCESS, 3894 &spr_read_generic, &spr_write_generic, 3895 0x00000000); 3896 #if !defined(CONFIG_USER_ONLY) 3897 env->nb_tlb = 64; 3898 env->nb_ways = 1; 3899 env->id_tlbs = 0; 3900 env->tlb_type = TLB_EMB; 3901 #endif 3902 init_excp_e200(env, 0xFFFF0000UL); 3903 env->dcache_line_size = 32; 3904 env->icache_line_size = 32; 3905 /* XXX: TODO: allocate internal IRQ controller */ 3906 } 3907 3908 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3909 { 3910 DeviceClass *dc = DEVICE_CLASS(oc); 3911 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3912 3913 dc->desc = "e200 core"; 3914 pcc->init_proc = init_proc_e200; 3915 pcc->check_pow = check_pow_hid0; 3916 /* 3917 * XXX: unimplemented instructions: 3918 * dcblc 3919 * dcbtlst 3920 * dcbtstls 3921 * icblc 3922 * icbtls 3923 * tlbivax 3924 * all SPE multiply-accumulate instructions 3925 */ 3926 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3927 PPC_SPE | PPC_SPE_SINGLE | 3928 PPC_WRTEE | PPC_RFDI | 3929 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3930 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3931 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3932 PPC_BOOKE; 3933 pcc->msr_mask = (1ull << MSR_UCLE) | 3934 (1ull << MSR_SPE) | 3935 (1ull << MSR_POW) | 3936 (1ull << MSR_CE) | 3937 (1ull << MSR_EE) | 3938 (1ull << MSR_PR) | 3939 (1ull << MSR_FP) | 3940 (1ull << MSR_ME) | 3941 (1ull << MSR_FE0) | 3942 (1ull << MSR_DWE) | 3943 (1ull << MSR_DE) | 3944 (1ull << MSR_FE1) | 3945 (1ull << MSR_IR) | 3946 (1ull << MSR_DR); 3947 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3948 pcc->excp_model = POWERPC_EXCP_BOOKE; 3949 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3950 pcc->bfd_mach = bfd_mach_ppc_860; 3951 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3952 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3953 POWERPC_FLAG_BUS_CLK; 3954 } 3955 3956 static void init_proc_e300(CPUPPCState *env) 3957 { 3958 register_ne_601_sprs(env); 3959 register_sdr1_sprs(env); 3960 register_603_sprs(env); 3961 /* Time base */ 3962 register_tbl(env); 3963 /* hardware implementation registers */ 3964 /* XXX : not implemented */ 3965 spr_register(env, SPR_HID0, "HID0", 3966 SPR_NOACCESS, SPR_NOACCESS, 3967 &spr_read_generic, &spr_write_generic, 3968 0x00000000); 3969 /* XXX : not implemented */ 3970 spr_register(env, SPR_HID1, "HID1", 3971 SPR_NOACCESS, SPR_NOACCESS, 3972 &spr_read_generic, &spr_write_generic, 3973 0x00000000); 3974 /* XXX : not implemented */ 3975 spr_register(env, SPR_HID2, "HID2", 3976 SPR_NOACCESS, SPR_NOACCESS, 3977 &spr_read_generic, &spr_write_generic, 3978 0x00000000); 3979 /* Breakpoints */ 3980 /* XXX : not implemented */ 3981 spr_register(env, SPR_DABR, "DABR", 3982 SPR_NOACCESS, SPR_NOACCESS, 3983 &spr_read_generic, &spr_write_generic, 3984 0x00000000); 3985 /* XXX : not implemented */ 3986 spr_register(env, SPR_DABR2, "DABR2", 3987 SPR_NOACCESS, SPR_NOACCESS, 3988 &spr_read_generic, &spr_write_generic, 3989 0x00000000); 3990 /* XXX : not implemented */ 3991 spr_register(env, SPR_IABR2, "IABR2", 3992 SPR_NOACCESS, SPR_NOACCESS, 3993 &spr_read_generic, &spr_write_generic, 3994 0x00000000); 3995 /* XXX : not implemented */ 3996 spr_register(env, SPR_IBCR, "IBCR", 3997 SPR_NOACCESS, SPR_NOACCESS, 3998 &spr_read_generic, &spr_write_generic, 3999 0x00000000); 4000 /* XXX : not implemented */ 4001 spr_register(env, SPR_DBCR, "DBCR", 4002 SPR_NOACCESS, SPR_NOACCESS, 4003 &spr_read_generic, &spr_write_generic, 4004 0x00000000); 4005 /* Memory management */ 4006 register_low_BATs(env); 4007 register_high_BATs(env); 4008 register_6xx_7xx_soft_tlb(env, 64, 2); 4009 init_excp_603(env); 4010 env->dcache_line_size = 32; 4011 env->icache_line_size = 32; 4012 /* Allocate hardware IRQ controller */ 4013 ppc6xx_irq_init(env_archcpu(env)); 4014 } 4015 4016 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 4017 { 4018 DeviceClass *dc = DEVICE_CLASS(oc); 4019 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4020 4021 dc->desc = "e300 core"; 4022 pcc->init_proc = init_proc_e300; 4023 pcc->check_pow = check_pow_hid0; 4024 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4025 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4026 PPC_FLOAT_STFIWX | 4027 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4028 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4029 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4030 PPC_SEGMENT | PPC_EXTERN; 4031 pcc->msr_mask = (1ull << MSR_POW) | 4032 (1ull << MSR_TGPR) | 4033 (1ull << MSR_ILE) | 4034 (1ull << MSR_EE) | 4035 (1ull << MSR_PR) | 4036 (1ull << MSR_FP) | 4037 (1ull << MSR_ME) | 4038 (1ull << MSR_FE0) | 4039 (1ull << MSR_SE) | 4040 (1ull << MSR_DE) | 4041 (1ull << MSR_FE1) | 4042 (1ull << MSR_AL) | 4043 (1ull << MSR_EP) | 4044 (1ull << MSR_IR) | 4045 (1ull << MSR_DR) | 4046 (1ull << MSR_RI) | 4047 (1ull << MSR_LE); 4048 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4049 pcc->excp_model = POWERPC_EXCP_603; 4050 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4051 pcc->bfd_mach = bfd_mach_ppc_603; 4052 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4053 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4054 } 4055 4056 enum fsl_e500_version { 4057 fsl_e500v1, 4058 fsl_e500v2, 4059 fsl_e500mc, 4060 fsl_e5500, 4061 fsl_e6500, 4062 }; 4063 4064 static void init_proc_e500(CPUPPCState *env, int version) 4065 { 4066 uint32_t tlbncfg[2]; 4067 uint64_t ivor_mask; 4068 uint64_t ivpr_mask = 0xFFFF0000ULL; 4069 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 4070 | 0x0020; /* 32 kb */ 4071 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 4072 | 0x0020; /* 32 kb */ 4073 uint32_t mmucfg = 0; 4074 #if !defined(CONFIG_USER_ONLY) 4075 int i; 4076 #endif 4077 4078 /* Time base */ 4079 register_tbl(env); 4080 /* 4081 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 4082 * complain when accessing them. 4083 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 4084 */ 4085 switch (version) { 4086 case fsl_e500v1: 4087 case fsl_e500v2: 4088 default: 4089 ivor_mask = 0x0000000F0000FFFFULL; 4090 break; 4091 case fsl_e500mc: 4092 case fsl_e5500: 4093 ivor_mask = 0x000003FE0000FFFFULL; 4094 break; 4095 case fsl_e6500: 4096 ivor_mask = 0x000003FF0000FFFFULL; 4097 break; 4098 } 4099 register_BookE_sprs(env, ivor_mask); 4100 register_usprg3_sprs(env); 4101 /* Processor identification */ 4102 spr_register(env, SPR_BOOKE_PIR, "PIR", 4103 SPR_NOACCESS, SPR_NOACCESS, 4104 &spr_read_generic, &spr_write_pir, 4105 0x00000000); 4106 /* XXX : not implemented */ 4107 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4108 &spr_read_spefscr, &spr_write_spefscr, 4109 &spr_read_spefscr, &spr_write_spefscr, 4110 0x00000000); 4111 #if !defined(CONFIG_USER_ONLY) 4112 /* Memory management */ 4113 env->nb_pids = 3; 4114 env->nb_ways = 2; 4115 env->id_tlbs = 0; 4116 switch (version) { 4117 case fsl_e500v1: 4118 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 4119 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4120 break; 4121 case fsl_e500v2: 4122 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4123 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4124 break; 4125 case fsl_e500mc: 4126 case fsl_e5500: 4127 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 4128 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 4129 break; 4130 case fsl_e6500: 4131 mmucfg = 0x6510B45; 4132 env->nb_pids = 1; 4133 tlbncfg[0] = 0x08052400; 4134 tlbncfg[1] = 0x40028040; 4135 break; 4136 default: 4137 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4138 env->spr[SPR_PVR]); 4139 } 4140 #endif 4141 /* Cache sizes */ 4142 switch (version) { 4143 case fsl_e500v1: 4144 case fsl_e500v2: 4145 env->dcache_line_size = 32; 4146 env->icache_line_size = 32; 4147 break; 4148 case fsl_e500mc: 4149 case fsl_e5500: 4150 env->dcache_line_size = 64; 4151 env->icache_line_size = 64; 4152 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 4153 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 4154 break; 4155 case fsl_e6500: 4156 env->dcache_line_size = 32; 4157 env->icache_line_size = 32; 4158 l1cfg0 |= 0x0F83820; 4159 l1cfg1 |= 0x0B83820; 4160 break; 4161 default: 4162 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4163 env->spr[SPR_PVR]); 4164 } 4165 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 4166 /* XXX : not implemented */ 4167 spr_register(env, SPR_HID0, "HID0", 4168 SPR_NOACCESS, SPR_NOACCESS, 4169 &spr_read_generic, &spr_write_generic, 4170 0x00000000); 4171 /* XXX : not implemented */ 4172 spr_register(env, SPR_HID1, "HID1", 4173 SPR_NOACCESS, SPR_NOACCESS, 4174 &spr_read_generic, &spr_write_generic, 4175 0x00000000); 4176 /* XXX : not implemented */ 4177 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 4178 SPR_NOACCESS, SPR_NOACCESS, 4179 &spr_read_generic, &spr_write_generic, 4180 0x00000000); 4181 /* XXX : not implemented */ 4182 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 4183 SPR_NOACCESS, SPR_NOACCESS, 4184 &spr_read_generic, &spr_write_generic, 4185 0x00000000); 4186 /* XXX : not implemented */ 4187 spr_register(env, SPR_Exxx_MCAR, "MCAR", 4188 SPR_NOACCESS, SPR_NOACCESS, 4189 &spr_read_generic, &spr_write_generic, 4190 0x00000000); 4191 /* XXX : not implemented */ 4192 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 4193 SPR_NOACCESS, SPR_NOACCESS, 4194 &spr_read_generic, &spr_write_generic, 4195 0x00000000); 4196 /* XXX : not implemented */ 4197 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 4198 SPR_NOACCESS, SPR_NOACCESS, 4199 &spr_read_generic, &spr_write_generic, 4200 0x00000000); 4201 /* XXX : not implemented */ 4202 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 4203 SPR_NOACCESS, SPR_NOACCESS, 4204 &spr_read_generic, &spr_write_generic, 4205 0x00000000); 4206 /* XXX : not implemented */ 4207 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 4208 &spr_read_generic, SPR_NOACCESS, 4209 &spr_read_generic, SPR_NOACCESS, 4210 l1cfg0); 4211 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 4212 &spr_read_generic, SPR_NOACCESS, 4213 &spr_read_generic, SPR_NOACCESS, 4214 l1cfg1); 4215 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 4216 SPR_NOACCESS, SPR_NOACCESS, 4217 &spr_read_generic, &spr_write_e500_l1csr0, 4218 0x00000000); 4219 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 4220 SPR_NOACCESS, SPR_NOACCESS, 4221 &spr_read_generic, &spr_write_e500_l1csr1, 4222 0x00000000); 4223 if (version != fsl_e500v1 && version != fsl_e500v2) { 4224 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 4225 SPR_NOACCESS, SPR_NOACCESS, 4226 &spr_read_generic, &spr_write_e500_l2csr0, 4227 0x00000000); 4228 } 4229 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 4230 SPR_NOACCESS, SPR_NOACCESS, 4231 &spr_read_generic, &spr_write_generic, 4232 0x00000000); 4233 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 4234 SPR_NOACCESS, SPR_NOACCESS, 4235 &spr_read_generic, &spr_write_generic, 4236 0x00000000); 4237 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 4238 SPR_NOACCESS, SPR_NOACCESS, 4239 &spr_read_generic, &spr_write_booke206_mmucsr0, 4240 0x00000000); 4241 spr_register(env, SPR_BOOKE_EPR, "EPR", 4242 SPR_NOACCESS, SPR_NOACCESS, 4243 &spr_read_generic, SPR_NOACCESS, 4244 0x00000000); 4245 /* XXX better abstract into Emb.xxx features */ 4246 if ((version == fsl_e5500) || (version == fsl_e6500)) { 4247 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 4248 SPR_NOACCESS, SPR_NOACCESS, 4249 &spr_read_generic, &spr_write_generic, 4250 0x00000000); 4251 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 4252 SPR_NOACCESS, SPR_NOACCESS, 4253 &spr_read_mas73, &spr_write_mas73, 4254 0x00000000); 4255 ivpr_mask = (target_ulong)~0xFFFFULL; 4256 } 4257 4258 if (version == fsl_e6500) { 4259 /* Thread identification */ 4260 spr_register(env, SPR_TIR, "TIR", 4261 SPR_NOACCESS, SPR_NOACCESS, 4262 &spr_read_generic, SPR_NOACCESS, 4263 0x00000000); 4264 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 4265 SPR_NOACCESS, SPR_NOACCESS, 4266 &spr_read_generic, SPR_NOACCESS, 4267 0x00000004); 4268 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 4269 SPR_NOACCESS, SPR_NOACCESS, 4270 &spr_read_generic, SPR_NOACCESS, 4271 0x7FFFFFFC); 4272 } 4273 4274 #if !defined(CONFIG_USER_ONLY) 4275 env->nb_tlb = 0; 4276 env->tlb_type = TLB_MAS; 4277 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 4278 env->nb_tlb += booke206_tlb_size(env, i); 4279 } 4280 #endif 4281 4282 init_excp_e200(env, ivpr_mask); 4283 /* Allocate hardware IRQ controller */ 4284 ppce500_irq_init(env_archcpu(env)); 4285 } 4286 4287 static void init_proc_e500v1(CPUPPCState *env) 4288 { 4289 init_proc_e500(env, fsl_e500v1); 4290 } 4291 4292 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 4293 { 4294 DeviceClass *dc = DEVICE_CLASS(oc); 4295 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4296 4297 dc->desc = "e500v1 core"; 4298 pcc->init_proc = init_proc_e500v1; 4299 pcc->check_pow = check_pow_hid0; 4300 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4301 PPC_SPE | PPC_SPE_SINGLE | 4302 PPC_WRTEE | PPC_RFDI | 4303 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4304 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4305 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4306 pcc->insns_flags2 = PPC2_BOOKE206; 4307 pcc->msr_mask = (1ull << MSR_UCLE) | 4308 (1ull << MSR_SPE) | 4309 (1ull << MSR_POW) | 4310 (1ull << MSR_CE) | 4311 (1ull << MSR_EE) | 4312 (1ull << MSR_PR) | 4313 (1ull << MSR_FP) | 4314 (1ull << MSR_ME) | 4315 (1ull << MSR_FE0) | 4316 (1ull << MSR_DWE) | 4317 (1ull << MSR_DE) | 4318 (1ull << MSR_FE1) | 4319 (1ull << MSR_IR) | 4320 (1ull << MSR_DR); 4321 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4322 pcc->excp_model = POWERPC_EXCP_BOOKE; 4323 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4324 pcc->bfd_mach = bfd_mach_ppc_860; 4325 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4326 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4327 POWERPC_FLAG_BUS_CLK; 4328 } 4329 4330 static void init_proc_e500v2(CPUPPCState *env) 4331 { 4332 init_proc_e500(env, fsl_e500v2); 4333 } 4334 4335 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 4336 { 4337 DeviceClass *dc = DEVICE_CLASS(oc); 4338 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4339 4340 dc->desc = "e500v2 core"; 4341 pcc->init_proc = init_proc_e500v2; 4342 pcc->check_pow = check_pow_hid0; 4343 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4344 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 4345 PPC_WRTEE | PPC_RFDI | 4346 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4347 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4348 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4349 pcc->insns_flags2 = PPC2_BOOKE206; 4350 pcc->msr_mask = (1ull << MSR_UCLE) | 4351 (1ull << MSR_SPE) | 4352 (1ull << MSR_POW) | 4353 (1ull << MSR_CE) | 4354 (1ull << MSR_EE) | 4355 (1ull << MSR_PR) | 4356 (1ull << MSR_FP) | 4357 (1ull << MSR_ME) | 4358 (1ull << MSR_FE0) | 4359 (1ull << MSR_DWE) | 4360 (1ull << MSR_DE) | 4361 (1ull << MSR_FE1) | 4362 (1ull << MSR_IR) | 4363 (1ull << MSR_DR); 4364 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4365 pcc->excp_model = POWERPC_EXCP_BOOKE; 4366 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4367 pcc->bfd_mach = bfd_mach_ppc_860; 4368 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4369 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4370 POWERPC_FLAG_BUS_CLK; 4371 } 4372 4373 static void init_proc_e500mc(CPUPPCState *env) 4374 { 4375 init_proc_e500(env, fsl_e500mc); 4376 } 4377 4378 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 4379 { 4380 DeviceClass *dc = DEVICE_CLASS(oc); 4381 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4382 4383 dc->desc = "e500mc core"; 4384 pcc->init_proc = init_proc_e500mc; 4385 pcc->check_pow = check_pow_none; 4386 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4387 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4388 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4389 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4390 PPC_FLOAT | PPC_FLOAT_FRES | 4391 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4392 PPC_FLOAT_STFIWX | PPC_WAIT | 4393 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 4394 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 4395 pcc->msr_mask = (1ull << MSR_GS) | 4396 (1ull << MSR_UCLE) | 4397 (1ull << MSR_CE) | 4398 (1ull << MSR_EE) | 4399 (1ull << MSR_PR) | 4400 (1ull << MSR_FP) | 4401 (1ull << MSR_ME) | 4402 (1ull << MSR_FE0) | 4403 (1ull << MSR_DE) | 4404 (1ull << MSR_FE1) | 4405 (1ull << MSR_IR) | 4406 (1ull << MSR_DR) | 4407 (1ull << MSR_PX) | 4408 (1ull << MSR_RI); 4409 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4410 pcc->excp_model = POWERPC_EXCP_BOOKE; 4411 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4412 /* FIXME: figure out the correct flag for e500mc */ 4413 pcc->bfd_mach = bfd_mach_ppc_e500; 4414 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4415 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4416 } 4417 4418 #ifdef TARGET_PPC64 4419 static void init_proc_e5500(CPUPPCState *env) 4420 { 4421 init_proc_e500(env, fsl_e5500); 4422 } 4423 4424 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 4425 { 4426 DeviceClass *dc = DEVICE_CLASS(oc); 4427 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4428 4429 dc->desc = "e5500 core"; 4430 pcc->init_proc = init_proc_e5500; 4431 pcc->check_pow = check_pow_none; 4432 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4433 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4434 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4435 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4436 PPC_FLOAT | PPC_FLOAT_FRES | 4437 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4438 PPC_FLOAT_STFIWX | PPC_WAIT | 4439 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4440 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 4441 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4442 PPC2_FP_CVT_S64; 4443 pcc->msr_mask = (1ull << MSR_CM) | 4444 (1ull << MSR_GS) | 4445 (1ull << MSR_UCLE) | 4446 (1ull << MSR_CE) | 4447 (1ull << MSR_EE) | 4448 (1ull << MSR_PR) | 4449 (1ull << MSR_FP) | 4450 (1ull << MSR_ME) | 4451 (1ull << MSR_FE0) | 4452 (1ull << MSR_DE) | 4453 (1ull << MSR_FE1) | 4454 (1ull << MSR_IR) | 4455 (1ull << MSR_DR) | 4456 (1ull << MSR_PX) | 4457 (1ull << MSR_RI); 4458 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4459 pcc->excp_model = POWERPC_EXCP_BOOKE; 4460 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4461 /* FIXME: figure out the correct flag for e5500 */ 4462 pcc->bfd_mach = bfd_mach_ppc_e500; 4463 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4464 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4465 } 4466 4467 static void init_proc_e6500(CPUPPCState *env) 4468 { 4469 init_proc_e500(env, fsl_e6500); 4470 } 4471 4472 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 4473 { 4474 DeviceClass *dc = DEVICE_CLASS(oc); 4475 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4476 4477 dc->desc = "e6500 core"; 4478 pcc->init_proc = init_proc_e6500; 4479 pcc->check_pow = check_pow_none; 4480 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 4481 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 4482 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4483 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4484 PPC_FLOAT | PPC_FLOAT_FRES | 4485 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 4486 PPC_FLOAT_STFIWX | PPC_WAIT | 4487 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 4488 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 4489 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 4490 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 4491 pcc->msr_mask = (1ull << MSR_CM) | 4492 (1ull << MSR_GS) | 4493 (1ull << MSR_UCLE) | 4494 (1ull << MSR_CE) | 4495 (1ull << MSR_EE) | 4496 (1ull << MSR_PR) | 4497 (1ull << MSR_FP) | 4498 (1ull << MSR_ME) | 4499 (1ull << MSR_FE0) | 4500 (1ull << MSR_DE) | 4501 (1ull << MSR_FE1) | 4502 (1ull << MSR_IS) | 4503 (1ull << MSR_DS) | 4504 (1ull << MSR_PX) | 4505 (1ull << MSR_RI) | 4506 (1ull << MSR_VR); 4507 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4508 pcc->excp_model = POWERPC_EXCP_BOOKE; 4509 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4510 pcc->bfd_mach = bfd_mach_ppc_e500; 4511 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 4512 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 4513 } 4514 4515 #endif 4516 4517 /* Non-embedded PowerPC */ 4518 4519 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 4520 4521 static void init_proc_601(CPUPPCState *env) 4522 { 4523 register_ne_601_sprs(env); 4524 register_sdr1_sprs(env); 4525 register_601_sprs(env); 4526 /* Hardware implementation registers */ 4527 /* XXX : not implemented */ 4528 spr_register(env, SPR_HID0, "HID0", 4529 SPR_NOACCESS, SPR_NOACCESS, 4530 &spr_read_generic, &spr_write_hid0_601, 4531 0x80010080); 4532 /* XXX : not implemented */ 4533 spr_register(env, SPR_HID1, "HID1", 4534 SPR_NOACCESS, SPR_NOACCESS, 4535 &spr_read_generic, &spr_write_generic, 4536 0x00000000); 4537 /* XXX : not implemented */ 4538 spr_register(env, SPR_601_HID2, "HID2", 4539 SPR_NOACCESS, SPR_NOACCESS, 4540 &spr_read_generic, &spr_write_generic, 4541 0x00000000); 4542 /* XXX : not implemented */ 4543 spr_register(env, SPR_601_HID5, "HID5", 4544 SPR_NOACCESS, SPR_NOACCESS, 4545 &spr_read_generic, &spr_write_generic, 4546 0x00000000); 4547 /* Memory management */ 4548 init_excp_601(env); 4549 /* 4550 * XXX: beware that dcache line size is 64 4551 * but dcbz uses 32 bytes "sectors" 4552 * XXX: this breaks clcs instruction ! 4553 */ 4554 env->dcache_line_size = 32; 4555 env->icache_line_size = 64; 4556 /* Allocate hardware IRQ controller */ 4557 ppc6xx_irq_init(env_archcpu(env)); 4558 } 4559 4560 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 4561 { 4562 DeviceClass *dc = DEVICE_CLASS(oc); 4563 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4564 4565 dc->desc = "PowerPC 601"; 4566 pcc->init_proc = init_proc_601; 4567 pcc->check_pow = check_pow_none; 4568 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4569 PPC_FLOAT | 4570 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4571 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4572 PPC_SEGMENT | PPC_EXTERN; 4573 pcc->msr_mask = (1ull << MSR_EE) | 4574 (1ull << MSR_PR) | 4575 (1ull << MSR_FP) | 4576 (1ull << MSR_ME) | 4577 (1ull << MSR_FE0) | 4578 (1ull << MSR_SE) | 4579 (1ull << MSR_FE1) | 4580 (1ull << MSR_EP) | 4581 (1ull << MSR_IR) | 4582 (1ull << MSR_DR); 4583 pcc->mmu_model = POWERPC_MMU_601; 4584 #if defined(CONFIG_SOFTMMU) 4585 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4586 #endif 4587 pcc->excp_model = POWERPC_EXCP_601; 4588 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4589 pcc->bfd_mach = bfd_mach_ppc_601; 4590 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4591 } 4592 4593 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 4594 4595 static void init_proc_601v(CPUPPCState *env) 4596 { 4597 init_proc_601(env); 4598 /* XXX : not implemented */ 4599 spr_register(env, SPR_601_HID15, "HID15", 4600 SPR_NOACCESS, SPR_NOACCESS, 4601 &spr_read_generic, &spr_write_generic, 4602 0x00000000); 4603 } 4604 4605 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 4606 { 4607 DeviceClass *dc = DEVICE_CLASS(oc); 4608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4609 4610 dc->desc = "PowerPC 601v"; 4611 pcc->init_proc = init_proc_601v; 4612 pcc->check_pow = check_pow_none; 4613 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4614 PPC_FLOAT | 4615 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4616 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4617 PPC_SEGMENT | PPC_EXTERN; 4618 pcc->msr_mask = (1ull << MSR_EE) | 4619 (1ull << MSR_PR) | 4620 (1ull << MSR_FP) | 4621 (1ull << MSR_ME) | 4622 (1ull << MSR_FE0) | 4623 (1ull << MSR_SE) | 4624 (1ull << MSR_FE1) | 4625 (1ull << MSR_EP) | 4626 (1ull << MSR_IR) | 4627 (1ull << MSR_DR); 4628 pcc->mmu_model = POWERPC_MMU_601; 4629 #if defined(CONFIG_SOFTMMU) 4630 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4631 #endif 4632 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4633 pcc->bfd_mach = bfd_mach_ppc_601; 4634 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4635 } 4636 4637 static void init_proc_602(CPUPPCState *env) 4638 { 4639 register_ne_601_sprs(env); 4640 register_sdr1_sprs(env); 4641 register_602_sprs(env); 4642 /* Time base */ 4643 register_tbl(env); 4644 /* hardware implementation registers */ 4645 /* XXX : not implemented */ 4646 spr_register(env, SPR_HID0, "HID0", 4647 SPR_NOACCESS, SPR_NOACCESS, 4648 &spr_read_generic, &spr_write_generic, 4649 0x00000000); 4650 /* XXX : not implemented */ 4651 spr_register(env, SPR_HID1, "HID1", 4652 SPR_NOACCESS, SPR_NOACCESS, 4653 &spr_read_generic, &spr_write_generic, 4654 0x00000000); 4655 /* Memory management */ 4656 register_low_BATs(env); 4657 register_6xx_7xx_soft_tlb(env, 64, 2); 4658 init_excp_602(env); 4659 env->dcache_line_size = 32; 4660 env->icache_line_size = 32; 4661 /* Allocate hardware IRQ controller */ 4662 ppc6xx_irq_init(env_archcpu(env)); 4663 } 4664 4665 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 4666 { 4667 DeviceClass *dc = DEVICE_CLASS(oc); 4668 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4669 4670 dc->desc = "PowerPC 602"; 4671 pcc->init_proc = init_proc_602; 4672 pcc->check_pow = check_pow_hid0; 4673 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4674 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4675 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4676 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4677 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4678 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 4679 PPC_SEGMENT | PPC_602_SPEC; 4680 pcc->msr_mask = (1ull << MSR_VSX) | 4681 (1ull << MSR_SA) | 4682 (1ull << MSR_POW) | 4683 (1ull << MSR_TGPR) | 4684 (1ull << MSR_ILE) | 4685 (1ull << MSR_EE) | 4686 (1ull << MSR_PR) | 4687 (1ull << MSR_FP) | 4688 (1ull << MSR_ME) | 4689 (1ull << MSR_FE0) | 4690 (1ull << MSR_SE) | 4691 (1ull << MSR_DE) | 4692 (1ull << MSR_FE1) | 4693 (1ull << MSR_EP) | 4694 (1ull << MSR_IR) | 4695 (1ull << MSR_DR) | 4696 (1ull << MSR_RI) | 4697 (1ull << MSR_LE); 4698 /* XXX: 602 MMU is quite specific. Should add a special case */ 4699 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4700 pcc->excp_model = POWERPC_EXCP_602; 4701 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4702 pcc->bfd_mach = bfd_mach_ppc_602; 4703 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4704 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4705 } 4706 4707 static void init_proc_603(CPUPPCState *env) 4708 { 4709 register_ne_601_sprs(env); 4710 register_sdr1_sprs(env); 4711 register_603_sprs(env); 4712 /* Time base */ 4713 register_tbl(env); 4714 /* hardware implementation registers */ 4715 /* XXX : not implemented */ 4716 spr_register(env, SPR_HID0, "HID0", 4717 SPR_NOACCESS, SPR_NOACCESS, 4718 &spr_read_generic, &spr_write_generic, 4719 0x00000000); 4720 /* XXX : not implemented */ 4721 spr_register(env, SPR_HID1, "HID1", 4722 SPR_NOACCESS, SPR_NOACCESS, 4723 &spr_read_generic, &spr_write_generic, 4724 0x00000000); 4725 /* Memory management */ 4726 register_low_BATs(env); 4727 register_6xx_7xx_soft_tlb(env, 64, 2); 4728 init_excp_603(env); 4729 env->dcache_line_size = 32; 4730 env->icache_line_size = 32; 4731 /* Allocate hardware IRQ controller */ 4732 ppc6xx_irq_init(env_archcpu(env)); 4733 } 4734 4735 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4736 { 4737 DeviceClass *dc = DEVICE_CLASS(oc); 4738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4739 4740 dc->desc = "PowerPC 603"; 4741 pcc->init_proc = init_proc_603; 4742 pcc->check_pow = check_pow_hid0; 4743 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4744 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4745 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4746 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4747 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4748 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4749 PPC_SEGMENT | PPC_EXTERN; 4750 pcc->msr_mask = (1ull << MSR_POW) | 4751 (1ull << MSR_TGPR) | 4752 (1ull << MSR_ILE) | 4753 (1ull << MSR_EE) | 4754 (1ull << MSR_PR) | 4755 (1ull << MSR_FP) | 4756 (1ull << MSR_ME) | 4757 (1ull << MSR_FE0) | 4758 (1ull << MSR_SE) | 4759 (1ull << MSR_DE) | 4760 (1ull << MSR_FE1) | 4761 (1ull << MSR_EP) | 4762 (1ull << MSR_IR) | 4763 (1ull << MSR_DR) | 4764 (1ull << MSR_RI) | 4765 (1ull << MSR_LE); 4766 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4767 pcc->excp_model = POWERPC_EXCP_603; 4768 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4769 pcc->bfd_mach = bfd_mach_ppc_603; 4770 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4771 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4772 } 4773 4774 static void init_proc_603E(CPUPPCState *env) 4775 { 4776 register_ne_601_sprs(env); 4777 register_sdr1_sprs(env); 4778 register_603_sprs(env); 4779 /* Time base */ 4780 register_tbl(env); 4781 /* hardware implementation registers */ 4782 /* XXX : not implemented */ 4783 spr_register(env, SPR_HID0, "HID0", 4784 SPR_NOACCESS, SPR_NOACCESS, 4785 &spr_read_generic, &spr_write_generic, 4786 0x00000000); 4787 /* XXX : not implemented */ 4788 spr_register(env, SPR_HID1, "HID1", 4789 SPR_NOACCESS, SPR_NOACCESS, 4790 &spr_read_generic, &spr_write_generic, 4791 0x00000000); 4792 /* Memory management */ 4793 register_low_BATs(env); 4794 register_6xx_7xx_soft_tlb(env, 64, 2); 4795 init_excp_603(env); 4796 env->dcache_line_size = 32; 4797 env->icache_line_size = 32; 4798 /* Allocate hardware IRQ controller */ 4799 ppc6xx_irq_init(env_archcpu(env)); 4800 } 4801 4802 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4803 { 4804 DeviceClass *dc = DEVICE_CLASS(oc); 4805 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4806 4807 dc->desc = "PowerPC 603e"; 4808 pcc->init_proc = init_proc_603E; 4809 pcc->check_pow = check_pow_hid0; 4810 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4811 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4812 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4813 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4814 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4815 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4816 PPC_SEGMENT | PPC_EXTERN; 4817 pcc->msr_mask = (1ull << MSR_POW) | 4818 (1ull << MSR_TGPR) | 4819 (1ull << MSR_ILE) | 4820 (1ull << MSR_EE) | 4821 (1ull << MSR_PR) | 4822 (1ull << MSR_FP) | 4823 (1ull << MSR_ME) | 4824 (1ull << MSR_FE0) | 4825 (1ull << MSR_SE) | 4826 (1ull << MSR_DE) | 4827 (1ull << MSR_FE1) | 4828 (1ull << MSR_EP) | 4829 (1ull << MSR_IR) | 4830 (1ull << MSR_DR) | 4831 (1ull << MSR_RI) | 4832 (1ull << MSR_LE); 4833 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4834 pcc->excp_model = POWERPC_EXCP_603E; 4835 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4836 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4837 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4838 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4839 } 4840 4841 static void init_proc_604(CPUPPCState *env) 4842 { 4843 register_ne_601_sprs(env); 4844 register_sdr1_sprs(env); 4845 register_604_sprs(env); 4846 /* Time base */ 4847 register_tbl(env); 4848 /* Hardware implementation registers */ 4849 /* XXX : not implemented */ 4850 spr_register(env, SPR_HID0, "HID0", 4851 SPR_NOACCESS, SPR_NOACCESS, 4852 &spr_read_generic, &spr_write_generic, 4853 0x00000000); 4854 /* Memory management */ 4855 register_low_BATs(env); 4856 init_excp_604(env); 4857 env->dcache_line_size = 32; 4858 env->icache_line_size = 32; 4859 /* Allocate hardware IRQ controller */ 4860 ppc6xx_irq_init(env_archcpu(env)); 4861 } 4862 4863 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4864 { 4865 DeviceClass *dc = DEVICE_CLASS(oc); 4866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4867 4868 dc->desc = "PowerPC 604"; 4869 pcc->init_proc = init_proc_604; 4870 pcc->check_pow = check_pow_nocheck; 4871 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4873 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4874 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4875 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4876 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4877 PPC_SEGMENT | PPC_EXTERN; 4878 pcc->msr_mask = (1ull << MSR_POW) | 4879 (1ull << MSR_ILE) | 4880 (1ull << MSR_EE) | 4881 (1ull << MSR_PR) | 4882 (1ull << MSR_FP) | 4883 (1ull << MSR_ME) | 4884 (1ull << MSR_FE0) | 4885 (1ull << MSR_SE) | 4886 (1ull << MSR_DE) | 4887 (1ull << MSR_FE1) | 4888 (1ull << MSR_EP) | 4889 (1ull << MSR_IR) | 4890 (1ull << MSR_DR) | 4891 (1ull << MSR_PMM) | 4892 (1ull << MSR_RI) | 4893 (1ull << MSR_LE); 4894 pcc->mmu_model = POWERPC_MMU_32B; 4895 #if defined(CONFIG_SOFTMMU) 4896 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4897 #endif 4898 pcc->excp_model = POWERPC_EXCP_604; 4899 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4900 pcc->bfd_mach = bfd_mach_ppc_604; 4901 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4902 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4903 } 4904 4905 static void init_proc_604E(CPUPPCState *env) 4906 { 4907 register_ne_601_sprs(env); 4908 register_sdr1_sprs(env); 4909 register_604_sprs(env); 4910 /* XXX : not implemented */ 4911 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4912 SPR_NOACCESS, SPR_NOACCESS, 4913 &spr_read_generic, &spr_write_generic, 4914 0x00000000); 4915 /* XXX : not implemented */ 4916 spr_register(env, SPR_7XX_PMC3, "PMC3", 4917 SPR_NOACCESS, SPR_NOACCESS, 4918 &spr_read_generic, &spr_write_generic, 4919 0x00000000); 4920 /* XXX : not implemented */ 4921 spr_register(env, SPR_7XX_PMC4, "PMC4", 4922 SPR_NOACCESS, SPR_NOACCESS, 4923 &spr_read_generic, &spr_write_generic, 4924 0x00000000); 4925 /* Time base */ 4926 register_tbl(env); 4927 /* Hardware implementation registers */ 4928 /* XXX : not implemented */ 4929 spr_register(env, SPR_HID0, "HID0", 4930 SPR_NOACCESS, SPR_NOACCESS, 4931 &spr_read_generic, &spr_write_generic, 4932 0x00000000); 4933 /* XXX : not implemented */ 4934 spr_register(env, SPR_HID1, "HID1", 4935 SPR_NOACCESS, SPR_NOACCESS, 4936 &spr_read_generic, &spr_write_generic, 4937 0x00000000); 4938 /* Memory management */ 4939 register_low_BATs(env); 4940 init_excp_604(env); 4941 env->dcache_line_size = 32; 4942 env->icache_line_size = 32; 4943 /* Allocate hardware IRQ controller */ 4944 ppc6xx_irq_init(env_archcpu(env)); 4945 } 4946 4947 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4948 { 4949 DeviceClass *dc = DEVICE_CLASS(oc); 4950 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4951 4952 dc->desc = "PowerPC 604E"; 4953 pcc->init_proc = init_proc_604E; 4954 pcc->check_pow = check_pow_nocheck; 4955 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4956 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4957 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4958 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4959 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4960 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4961 PPC_SEGMENT | PPC_EXTERN; 4962 pcc->msr_mask = (1ull << MSR_POW) | 4963 (1ull << MSR_ILE) | 4964 (1ull << MSR_EE) | 4965 (1ull << MSR_PR) | 4966 (1ull << MSR_FP) | 4967 (1ull << MSR_ME) | 4968 (1ull << MSR_FE0) | 4969 (1ull << MSR_SE) | 4970 (1ull << MSR_DE) | 4971 (1ull << MSR_FE1) | 4972 (1ull << MSR_EP) | 4973 (1ull << MSR_IR) | 4974 (1ull << MSR_DR) | 4975 (1ull << MSR_PMM) | 4976 (1ull << MSR_RI) | 4977 (1ull << MSR_LE); 4978 pcc->mmu_model = POWERPC_MMU_32B; 4979 #if defined(CONFIG_SOFTMMU) 4980 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 4981 #endif 4982 pcc->excp_model = POWERPC_EXCP_604; 4983 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4984 pcc->bfd_mach = bfd_mach_ppc_604; 4985 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4986 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4987 } 4988 4989 static void init_proc_740(CPUPPCState *env) 4990 { 4991 register_ne_601_sprs(env); 4992 register_sdr1_sprs(env); 4993 register_7xx_sprs(env); 4994 /* Time base */ 4995 register_tbl(env); 4996 /* Thermal management */ 4997 register_thrm_sprs(env); 4998 /* Hardware implementation registers */ 4999 /* XXX : not implemented */ 5000 spr_register(env, SPR_HID0, "HID0", 5001 SPR_NOACCESS, SPR_NOACCESS, 5002 &spr_read_generic, &spr_write_generic, 5003 0x00000000); 5004 /* XXX : not implemented */ 5005 spr_register(env, SPR_HID1, "HID1", 5006 SPR_NOACCESS, SPR_NOACCESS, 5007 &spr_read_generic, &spr_write_generic, 5008 0x00000000); 5009 /* Memory management */ 5010 register_low_BATs(env); 5011 init_excp_7x0(env); 5012 env->dcache_line_size = 32; 5013 env->icache_line_size = 32; 5014 /* Allocate hardware IRQ controller */ 5015 ppc6xx_irq_init(env_archcpu(env)); 5016 } 5017 5018 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 5019 { 5020 DeviceClass *dc = DEVICE_CLASS(oc); 5021 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5022 5023 dc->desc = "PowerPC 740"; 5024 pcc->init_proc = init_proc_740; 5025 pcc->check_pow = check_pow_hid0; 5026 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5027 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5028 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5029 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5030 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5031 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5032 PPC_SEGMENT | PPC_EXTERN; 5033 pcc->msr_mask = (1ull << MSR_POW) | 5034 (1ull << MSR_ILE) | 5035 (1ull << MSR_EE) | 5036 (1ull << MSR_PR) | 5037 (1ull << MSR_FP) | 5038 (1ull << MSR_ME) | 5039 (1ull << MSR_FE0) | 5040 (1ull << MSR_SE) | 5041 (1ull << MSR_DE) | 5042 (1ull << MSR_FE1) | 5043 (1ull << MSR_EP) | 5044 (1ull << MSR_IR) | 5045 (1ull << MSR_DR) | 5046 (1ull << MSR_PMM) | 5047 (1ull << MSR_RI) | 5048 (1ull << MSR_LE); 5049 pcc->mmu_model = POWERPC_MMU_32B; 5050 #if defined(CONFIG_SOFTMMU) 5051 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5052 #endif 5053 pcc->excp_model = POWERPC_EXCP_7x0; 5054 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5055 pcc->bfd_mach = bfd_mach_ppc_750; 5056 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5057 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5058 } 5059 5060 static void init_proc_750(CPUPPCState *env) 5061 { 5062 register_ne_601_sprs(env); 5063 register_sdr1_sprs(env); 5064 register_7xx_sprs(env); 5065 /* XXX : not implemented */ 5066 spr_register(env, SPR_L2CR, "L2CR", 5067 SPR_NOACCESS, SPR_NOACCESS, 5068 &spr_read_generic, spr_access_nop, 5069 0x00000000); 5070 /* Time base */ 5071 register_tbl(env); 5072 /* Thermal management */ 5073 register_thrm_sprs(env); 5074 /* Hardware implementation registers */ 5075 /* XXX : not implemented */ 5076 spr_register(env, SPR_HID0, "HID0", 5077 SPR_NOACCESS, SPR_NOACCESS, 5078 &spr_read_generic, &spr_write_generic, 5079 0x00000000); 5080 /* XXX : not implemented */ 5081 spr_register(env, SPR_HID1, "HID1", 5082 SPR_NOACCESS, SPR_NOACCESS, 5083 &spr_read_generic, &spr_write_generic, 5084 0x00000000); 5085 /* Memory management */ 5086 register_low_BATs(env); 5087 /* 5088 * XXX: high BATs are also present but are known to be bugged on 5089 * die version 1.x 5090 */ 5091 init_excp_7x0(env); 5092 env->dcache_line_size = 32; 5093 env->icache_line_size = 32; 5094 /* Allocate hardware IRQ controller */ 5095 ppc6xx_irq_init(env_archcpu(env)); 5096 } 5097 5098 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 5099 { 5100 DeviceClass *dc = DEVICE_CLASS(oc); 5101 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5102 5103 dc->desc = "PowerPC 750"; 5104 pcc->init_proc = init_proc_750; 5105 pcc->check_pow = check_pow_hid0; 5106 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5107 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5108 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5109 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5110 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5111 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5112 PPC_SEGMENT | PPC_EXTERN; 5113 pcc->msr_mask = (1ull << MSR_POW) | 5114 (1ull << MSR_ILE) | 5115 (1ull << MSR_EE) | 5116 (1ull << MSR_PR) | 5117 (1ull << MSR_FP) | 5118 (1ull << MSR_ME) | 5119 (1ull << MSR_FE0) | 5120 (1ull << MSR_SE) | 5121 (1ull << MSR_DE) | 5122 (1ull << MSR_FE1) | 5123 (1ull << MSR_EP) | 5124 (1ull << MSR_IR) | 5125 (1ull << MSR_DR) | 5126 (1ull << MSR_PMM) | 5127 (1ull << MSR_RI) | 5128 (1ull << MSR_LE); 5129 pcc->mmu_model = POWERPC_MMU_32B; 5130 #if defined(CONFIG_SOFTMMU) 5131 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5132 #endif 5133 pcc->excp_model = POWERPC_EXCP_7x0; 5134 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5135 pcc->bfd_mach = bfd_mach_ppc_750; 5136 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5137 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5138 } 5139 5140 static void init_proc_750cl(CPUPPCState *env) 5141 { 5142 register_ne_601_sprs(env); 5143 register_sdr1_sprs(env); 5144 register_7xx_sprs(env); 5145 /* XXX : not implemented */ 5146 spr_register(env, SPR_L2CR, "L2CR", 5147 SPR_NOACCESS, SPR_NOACCESS, 5148 &spr_read_generic, spr_access_nop, 5149 0x00000000); 5150 /* Time base */ 5151 register_tbl(env); 5152 /* Thermal management */ 5153 /* Those registers are fake on 750CL */ 5154 spr_register(env, SPR_THRM1, "THRM1", 5155 SPR_NOACCESS, SPR_NOACCESS, 5156 &spr_read_generic, &spr_write_generic, 5157 0x00000000); 5158 spr_register(env, SPR_THRM2, "THRM2", 5159 SPR_NOACCESS, SPR_NOACCESS, 5160 &spr_read_generic, &spr_write_generic, 5161 0x00000000); 5162 spr_register(env, SPR_THRM3, "THRM3", 5163 SPR_NOACCESS, SPR_NOACCESS, 5164 &spr_read_generic, &spr_write_generic, 5165 0x00000000); 5166 /* XXX: not implemented */ 5167 spr_register(env, SPR_750_TDCL, "TDCL", 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 &spr_read_generic, &spr_write_generic, 5170 0x00000000); 5171 spr_register(env, SPR_750_TDCH, "TDCH", 5172 SPR_NOACCESS, SPR_NOACCESS, 5173 &spr_read_generic, &spr_write_generic, 5174 0x00000000); 5175 /* DMA */ 5176 /* XXX : not implemented */ 5177 spr_register(env, SPR_750_WPAR, "WPAR", 5178 SPR_NOACCESS, SPR_NOACCESS, 5179 &spr_read_generic, &spr_write_generic, 5180 0x00000000); 5181 spr_register(env, SPR_750_DMAL, "DMAL", 5182 SPR_NOACCESS, SPR_NOACCESS, 5183 &spr_read_generic, &spr_write_generic, 5184 0x00000000); 5185 spr_register(env, SPR_750_DMAU, "DMAU", 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 &spr_read_generic, &spr_write_generic, 5188 0x00000000); 5189 /* Hardware implementation registers */ 5190 /* XXX : not implemented */ 5191 spr_register(env, SPR_HID0, "HID0", 5192 SPR_NOACCESS, SPR_NOACCESS, 5193 &spr_read_generic, &spr_write_generic, 5194 0x00000000); 5195 /* XXX : not implemented */ 5196 spr_register(env, SPR_HID1, "HID1", 5197 SPR_NOACCESS, SPR_NOACCESS, 5198 &spr_read_generic, &spr_write_generic, 5199 0x00000000); 5200 /* XXX : not implemented */ 5201 spr_register(env, SPR_750CL_HID2, "HID2", 5202 SPR_NOACCESS, SPR_NOACCESS, 5203 &spr_read_generic, &spr_write_generic, 5204 0x00000000); 5205 /* XXX : not implemented */ 5206 spr_register(env, SPR_750CL_HID4, "HID4", 5207 SPR_NOACCESS, SPR_NOACCESS, 5208 &spr_read_generic, &spr_write_generic, 5209 0x00000000); 5210 /* Quantization registers */ 5211 /* XXX : not implemented */ 5212 spr_register(env, SPR_750_GQR0, "GQR0", 5213 SPR_NOACCESS, SPR_NOACCESS, 5214 &spr_read_generic, &spr_write_generic, 5215 0x00000000); 5216 /* XXX : not implemented */ 5217 spr_register(env, SPR_750_GQR1, "GQR1", 5218 SPR_NOACCESS, SPR_NOACCESS, 5219 &spr_read_generic, &spr_write_generic, 5220 0x00000000); 5221 /* XXX : not implemented */ 5222 spr_register(env, SPR_750_GQR2, "GQR2", 5223 SPR_NOACCESS, SPR_NOACCESS, 5224 &spr_read_generic, &spr_write_generic, 5225 0x00000000); 5226 /* XXX : not implemented */ 5227 spr_register(env, SPR_750_GQR3, "GQR3", 5228 SPR_NOACCESS, SPR_NOACCESS, 5229 &spr_read_generic, &spr_write_generic, 5230 0x00000000); 5231 /* XXX : not implemented */ 5232 spr_register(env, SPR_750_GQR4, "GQR4", 5233 SPR_NOACCESS, SPR_NOACCESS, 5234 &spr_read_generic, &spr_write_generic, 5235 0x00000000); 5236 /* XXX : not implemented */ 5237 spr_register(env, SPR_750_GQR5, "GQR5", 5238 SPR_NOACCESS, SPR_NOACCESS, 5239 &spr_read_generic, &spr_write_generic, 5240 0x00000000); 5241 /* XXX : not implemented */ 5242 spr_register(env, SPR_750_GQR6, "GQR6", 5243 SPR_NOACCESS, SPR_NOACCESS, 5244 &spr_read_generic, &spr_write_generic, 5245 0x00000000); 5246 /* XXX : not implemented */ 5247 spr_register(env, SPR_750_GQR7, "GQR7", 5248 SPR_NOACCESS, SPR_NOACCESS, 5249 &spr_read_generic, &spr_write_generic, 5250 0x00000000); 5251 /* Memory management */ 5252 register_low_BATs(env); 5253 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 5254 register_high_BATs(env); 5255 init_excp_750cl(env); 5256 env->dcache_line_size = 32; 5257 env->icache_line_size = 32; 5258 /* Allocate hardware IRQ controller */ 5259 ppc6xx_irq_init(env_archcpu(env)); 5260 } 5261 5262 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 5263 { 5264 DeviceClass *dc = DEVICE_CLASS(oc); 5265 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5266 5267 dc->desc = "PowerPC 750 CL"; 5268 pcc->init_proc = init_proc_750cl; 5269 pcc->check_pow = check_pow_hid0; 5270 /* 5271 * XXX: not implemented: 5272 * cache lock instructions: 5273 * dcbz_l 5274 * floating point paired instructions 5275 * psq_lux 5276 * psq_lx 5277 * psq_stux 5278 * psq_stx 5279 * ps_abs 5280 * ps_add 5281 * ps_cmpo0 5282 * ps_cmpo1 5283 * ps_cmpu0 5284 * ps_cmpu1 5285 * ps_div 5286 * ps_madd 5287 * ps_madds0 5288 * ps_madds1 5289 * ps_merge00 5290 * ps_merge01 5291 * ps_merge10 5292 * ps_merge11 5293 * ps_mr 5294 * ps_msub 5295 * ps_mul 5296 * ps_muls0 5297 * ps_muls1 5298 * ps_nabs 5299 * ps_neg 5300 * ps_nmadd 5301 * ps_nmsub 5302 * ps_res 5303 * ps_rsqrte 5304 * ps_sel 5305 * ps_sub 5306 * ps_sum0 5307 * ps_sum1 5308 */ 5309 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5310 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5311 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5312 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5313 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5314 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5315 PPC_SEGMENT | PPC_EXTERN; 5316 pcc->msr_mask = (1ull << MSR_POW) | 5317 (1ull << MSR_ILE) | 5318 (1ull << MSR_EE) | 5319 (1ull << MSR_PR) | 5320 (1ull << MSR_FP) | 5321 (1ull << MSR_ME) | 5322 (1ull << MSR_FE0) | 5323 (1ull << MSR_SE) | 5324 (1ull << MSR_DE) | 5325 (1ull << MSR_FE1) | 5326 (1ull << MSR_EP) | 5327 (1ull << MSR_IR) | 5328 (1ull << MSR_DR) | 5329 (1ull << MSR_PMM) | 5330 (1ull << MSR_RI) | 5331 (1ull << MSR_LE); 5332 pcc->mmu_model = POWERPC_MMU_32B; 5333 #if defined(CONFIG_SOFTMMU) 5334 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5335 #endif 5336 pcc->excp_model = POWERPC_EXCP_7x0; 5337 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5338 pcc->bfd_mach = bfd_mach_ppc_750; 5339 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5340 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5341 } 5342 5343 static void init_proc_750cx(CPUPPCState *env) 5344 { 5345 register_ne_601_sprs(env); 5346 register_sdr1_sprs(env); 5347 register_7xx_sprs(env); 5348 /* XXX : not implemented */ 5349 spr_register(env, SPR_L2CR, "L2CR", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, spr_access_nop, 5352 0x00000000); 5353 /* Time base */ 5354 register_tbl(env); 5355 /* Thermal management */ 5356 register_thrm_sprs(env); 5357 /* This register is not implemented but is present for compatibility */ 5358 spr_register(env, SPR_SDA, "SDA", 5359 SPR_NOACCESS, SPR_NOACCESS, 5360 &spr_read_generic, &spr_write_generic, 5361 0x00000000); 5362 /* Hardware implementation registers */ 5363 /* XXX : not implemented */ 5364 spr_register(env, SPR_HID0, "HID0", 5365 SPR_NOACCESS, SPR_NOACCESS, 5366 &spr_read_generic, &spr_write_generic, 5367 0x00000000); 5368 /* XXX : not implemented */ 5369 spr_register(env, SPR_HID1, "HID1", 5370 SPR_NOACCESS, SPR_NOACCESS, 5371 &spr_read_generic, &spr_write_generic, 5372 0x00000000); 5373 /* Memory management */ 5374 register_low_BATs(env); 5375 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 5376 register_high_BATs(env); 5377 init_excp_750cx(env); 5378 env->dcache_line_size = 32; 5379 env->icache_line_size = 32; 5380 /* Allocate hardware IRQ controller */ 5381 ppc6xx_irq_init(env_archcpu(env)); 5382 } 5383 5384 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 5385 { 5386 DeviceClass *dc = DEVICE_CLASS(oc); 5387 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5388 5389 dc->desc = "PowerPC 750CX"; 5390 pcc->init_proc = init_proc_750cx; 5391 pcc->check_pow = check_pow_hid0; 5392 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5393 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5394 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5395 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5396 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5397 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5398 PPC_SEGMENT | PPC_EXTERN; 5399 pcc->msr_mask = (1ull << MSR_POW) | 5400 (1ull << MSR_ILE) | 5401 (1ull << MSR_EE) | 5402 (1ull << MSR_PR) | 5403 (1ull << MSR_FP) | 5404 (1ull << MSR_ME) | 5405 (1ull << MSR_FE0) | 5406 (1ull << MSR_SE) | 5407 (1ull << MSR_DE) | 5408 (1ull << MSR_FE1) | 5409 (1ull << MSR_EP) | 5410 (1ull << MSR_IR) | 5411 (1ull << MSR_DR) | 5412 (1ull << MSR_PMM) | 5413 (1ull << MSR_RI) | 5414 (1ull << MSR_LE); 5415 pcc->mmu_model = POWERPC_MMU_32B; 5416 #if defined(CONFIG_SOFTMMU) 5417 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5418 #endif 5419 pcc->excp_model = POWERPC_EXCP_7x0; 5420 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5421 pcc->bfd_mach = bfd_mach_ppc_750; 5422 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5423 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5424 } 5425 5426 static void init_proc_750fx(CPUPPCState *env) 5427 { 5428 register_ne_601_sprs(env); 5429 register_sdr1_sprs(env); 5430 register_7xx_sprs(env); 5431 /* XXX : not implemented */ 5432 spr_register(env, SPR_L2CR, "L2CR", 5433 SPR_NOACCESS, SPR_NOACCESS, 5434 &spr_read_generic, spr_access_nop, 5435 0x00000000); 5436 /* Time base */ 5437 register_tbl(env); 5438 /* Thermal management */ 5439 register_thrm_sprs(env); 5440 /* XXX : not implemented */ 5441 spr_register(env, SPR_750_THRM4, "THRM4", 5442 SPR_NOACCESS, SPR_NOACCESS, 5443 &spr_read_generic, &spr_write_generic, 5444 0x00000000); 5445 /* Hardware implementation registers */ 5446 /* XXX : not implemented */ 5447 spr_register(env, SPR_HID0, "HID0", 5448 SPR_NOACCESS, SPR_NOACCESS, 5449 &spr_read_generic, &spr_write_generic, 5450 0x00000000); 5451 /* XXX : not implemented */ 5452 spr_register(env, SPR_HID1, "HID1", 5453 SPR_NOACCESS, SPR_NOACCESS, 5454 &spr_read_generic, &spr_write_generic, 5455 0x00000000); 5456 /* XXX : not implemented */ 5457 spr_register(env, SPR_750FX_HID2, "HID2", 5458 SPR_NOACCESS, SPR_NOACCESS, 5459 &spr_read_generic, &spr_write_generic, 5460 0x00000000); 5461 /* Memory management */ 5462 register_low_BATs(env); 5463 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5464 register_high_BATs(env); 5465 init_excp_7x0(env); 5466 env->dcache_line_size = 32; 5467 env->icache_line_size = 32; 5468 /* Allocate hardware IRQ controller */ 5469 ppc6xx_irq_init(env_archcpu(env)); 5470 } 5471 5472 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 5473 { 5474 DeviceClass *dc = DEVICE_CLASS(oc); 5475 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5476 5477 dc->desc = "PowerPC 750FX"; 5478 pcc->init_proc = init_proc_750fx; 5479 pcc->check_pow = check_pow_hid0; 5480 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5481 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5482 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5483 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5484 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5486 PPC_SEGMENT | PPC_EXTERN; 5487 pcc->msr_mask = (1ull << MSR_POW) | 5488 (1ull << MSR_ILE) | 5489 (1ull << MSR_EE) | 5490 (1ull << MSR_PR) | 5491 (1ull << MSR_FP) | 5492 (1ull << MSR_ME) | 5493 (1ull << MSR_FE0) | 5494 (1ull << MSR_SE) | 5495 (1ull << MSR_DE) | 5496 (1ull << MSR_FE1) | 5497 (1ull << MSR_EP) | 5498 (1ull << MSR_IR) | 5499 (1ull << MSR_DR) | 5500 (1ull << MSR_PMM) | 5501 (1ull << MSR_RI) | 5502 (1ull << MSR_LE); 5503 pcc->mmu_model = POWERPC_MMU_32B; 5504 #if defined(CONFIG_SOFTMMU) 5505 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5506 #endif 5507 pcc->excp_model = POWERPC_EXCP_7x0; 5508 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5509 pcc->bfd_mach = bfd_mach_ppc_750; 5510 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5511 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5512 } 5513 5514 static void init_proc_750gx(CPUPPCState *env) 5515 { 5516 register_ne_601_sprs(env); 5517 register_sdr1_sprs(env); 5518 register_7xx_sprs(env); 5519 /* XXX : not implemented (XXX: different from 750fx) */ 5520 spr_register(env, SPR_L2CR, "L2CR", 5521 SPR_NOACCESS, SPR_NOACCESS, 5522 &spr_read_generic, spr_access_nop, 5523 0x00000000); 5524 /* Time base */ 5525 register_tbl(env); 5526 /* Thermal management */ 5527 register_thrm_sprs(env); 5528 /* XXX : not implemented */ 5529 spr_register(env, SPR_750_THRM4, "THRM4", 5530 SPR_NOACCESS, SPR_NOACCESS, 5531 &spr_read_generic, &spr_write_generic, 5532 0x00000000); 5533 /* Hardware implementation registers */ 5534 /* XXX : not implemented (XXX: different from 750fx) */ 5535 spr_register(env, SPR_HID0, "HID0", 5536 SPR_NOACCESS, SPR_NOACCESS, 5537 &spr_read_generic, &spr_write_generic, 5538 0x00000000); 5539 /* XXX : not implemented */ 5540 spr_register(env, SPR_HID1, "HID1", 5541 SPR_NOACCESS, SPR_NOACCESS, 5542 &spr_read_generic, &spr_write_generic, 5543 0x00000000); 5544 /* XXX : not implemented (XXX: different from 750fx) */ 5545 spr_register(env, SPR_750FX_HID2, "HID2", 5546 SPR_NOACCESS, SPR_NOACCESS, 5547 &spr_read_generic, &spr_write_generic, 5548 0x00000000); 5549 /* Memory management */ 5550 register_low_BATs(env); 5551 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 5552 register_high_BATs(env); 5553 init_excp_7x0(env); 5554 env->dcache_line_size = 32; 5555 env->icache_line_size = 32; 5556 /* Allocate hardware IRQ controller */ 5557 ppc6xx_irq_init(env_archcpu(env)); 5558 } 5559 5560 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 5561 { 5562 DeviceClass *dc = DEVICE_CLASS(oc); 5563 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5564 5565 dc->desc = "PowerPC 750GX"; 5566 pcc->init_proc = init_proc_750gx; 5567 pcc->check_pow = check_pow_hid0; 5568 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5569 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5570 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5571 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5572 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5573 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5574 PPC_SEGMENT | PPC_EXTERN; 5575 pcc->msr_mask = (1ull << MSR_POW) | 5576 (1ull << MSR_ILE) | 5577 (1ull << MSR_EE) | 5578 (1ull << MSR_PR) | 5579 (1ull << MSR_FP) | 5580 (1ull << MSR_ME) | 5581 (1ull << MSR_FE0) | 5582 (1ull << MSR_SE) | 5583 (1ull << MSR_DE) | 5584 (1ull << MSR_FE1) | 5585 (1ull << MSR_EP) | 5586 (1ull << MSR_IR) | 5587 (1ull << MSR_DR) | 5588 (1ull << MSR_PMM) | 5589 (1ull << MSR_RI) | 5590 (1ull << MSR_LE); 5591 pcc->mmu_model = POWERPC_MMU_32B; 5592 #if defined(CONFIG_SOFTMMU) 5593 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5594 #endif 5595 pcc->excp_model = POWERPC_EXCP_7x0; 5596 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5597 pcc->bfd_mach = bfd_mach_ppc_750; 5598 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5599 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5600 } 5601 5602 static void init_proc_745(CPUPPCState *env) 5603 { 5604 register_ne_601_sprs(env); 5605 register_sdr1_sprs(env); 5606 register_7xx_sprs(env); 5607 register_G2_755_sprs(env); 5608 /* Time base */ 5609 register_tbl(env); 5610 /* Thermal management */ 5611 register_thrm_sprs(env); 5612 /* Hardware implementation registers */ 5613 /* XXX : not implemented */ 5614 spr_register(env, SPR_HID0, "HID0", 5615 SPR_NOACCESS, SPR_NOACCESS, 5616 &spr_read_generic, &spr_write_generic, 5617 0x00000000); 5618 /* XXX : not implemented */ 5619 spr_register(env, SPR_HID1, "HID1", 5620 SPR_NOACCESS, SPR_NOACCESS, 5621 &spr_read_generic, &spr_write_generic, 5622 0x00000000); 5623 /* XXX : not implemented */ 5624 spr_register(env, SPR_HID2, "HID2", 5625 SPR_NOACCESS, SPR_NOACCESS, 5626 &spr_read_generic, &spr_write_generic, 5627 0x00000000); 5628 /* Memory management */ 5629 register_low_BATs(env); 5630 register_high_BATs(env); 5631 register_6xx_7xx_soft_tlb(env, 64, 2); 5632 init_excp_7x5(env); 5633 env->dcache_line_size = 32; 5634 env->icache_line_size = 32; 5635 /* Allocate hardware IRQ controller */ 5636 ppc6xx_irq_init(env_archcpu(env)); 5637 } 5638 5639 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 5640 { 5641 DeviceClass *dc = DEVICE_CLASS(oc); 5642 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5643 5644 dc->desc = "PowerPC 745"; 5645 pcc->init_proc = init_proc_745; 5646 pcc->check_pow = check_pow_hid0; 5647 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5648 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5649 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5650 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5651 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5652 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5653 PPC_SEGMENT | PPC_EXTERN; 5654 pcc->msr_mask = (1ull << MSR_POW) | 5655 (1ull << MSR_ILE) | 5656 (1ull << MSR_EE) | 5657 (1ull << MSR_PR) | 5658 (1ull << MSR_FP) | 5659 (1ull << MSR_ME) | 5660 (1ull << MSR_FE0) | 5661 (1ull << MSR_SE) | 5662 (1ull << MSR_DE) | 5663 (1ull << MSR_FE1) | 5664 (1ull << MSR_EP) | 5665 (1ull << MSR_IR) | 5666 (1ull << MSR_DR) | 5667 (1ull << MSR_PMM) | 5668 (1ull << MSR_RI) | 5669 (1ull << MSR_LE); 5670 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5671 pcc->excp_model = POWERPC_EXCP_7x5; 5672 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5673 pcc->bfd_mach = bfd_mach_ppc_750; 5674 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5675 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5676 } 5677 5678 static void init_proc_755(CPUPPCState *env) 5679 { 5680 register_ne_601_sprs(env); 5681 register_sdr1_sprs(env); 5682 register_7xx_sprs(env); 5683 register_G2_755_sprs(env); 5684 /* Time base */ 5685 register_tbl(env); 5686 /* L2 cache control */ 5687 /* XXX : not implemented */ 5688 spr_register(env, SPR_L2CR, "L2CR", 5689 SPR_NOACCESS, SPR_NOACCESS, 5690 &spr_read_generic, spr_access_nop, 5691 0x00000000); 5692 /* XXX : not implemented */ 5693 spr_register(env, SPR_L2PMCR, "L2PMCR", 5694 SPR_NOACCESS, SPR_NOACCESS, 5695 &spr_read_generic, &spr_write_generic, 5696 0x00000000); 5697 /* Thermal management */ 5698 register_thrm_sprs(env); 5699 /* Hardware implementation registers */ 5700 /* XXX : not implemented */ 5701 spr_register(env, SPR_HID0, "HID0", 5702 SPR_NOACCESS, SPR_NOACCESS, 5703 &spr_read_generic, &spr_write_generic, 5704 0x00000000); 5705 /* XXX : not implemented */ 5706 spr_register(env, SPR_HID1, "HID1", 5707 SPR_NOACCESS, SPR_NOACCESS, 5708 &spr_read_generic, &spr_write_generic, 5709 0x00000000); 5710 /* XXX : not implemented */ 5711 spr_register(env, SPR_HID2, "HID2", 5712 SPR_NOACCESS, SPR_NOACCESS, 5713 &spr_read_generic, &spr_write_generic, 5714 0x00000000); 5715 /* Memory management */ 5716 register_low_BATs(env); 5717 register_high_BATs(env); 5718 register_6xx_7xx_soft_tlb(env, 64, 2); 5719 init_excp_7x5(env); 5720 env->dcache_line_size = 32; 5721 env->icache_line_size = 32; 5722 /* Allocate hardware IRQ controller */ 5723 ppc6xx_irq_init(env_archcpu(env)); 5724 } 5725 5726 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 5727 { 5728 DeviceClass *dc = DEVICE_CLASS(oc); 5729 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5730 5731 dc->desc = "PowerPC 755"; 5732 pcc->init_proc = init_proc_755; 5733 pcc->check_pow = check_pow_hid0; 5734 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5735 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5736 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5737 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5738 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5739 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5740 PPC_SEGMENT | PPC_EXTERN; 5741 pcc->msr_mask = (1ull << MSR_POW) | 5742 (1ull << MSR_ILE) | 5743 (1ull << MSR_EE) | 5744 (1ull << MSR_PR) | 5745 (1ull << MSR_FP) | 5746 (1ull << MSR_ME) | 5747 (1ull << MSR_FE0) | 5748 (1ull << MSR_SE) | 5749 (1ull << MSR_DE) | 5750 (1ull << MSR_FE1) | 5751 (1ull << MSR_EP) | 5752 (1ull << MSR_IR) | 5753 (1ull << MSR_DR) | 5754 (1ull << MSR_PMM) | 5755 (1ull << MSR_RI) | 5756 (1ull << MSR_LE); 5757 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5758 pcc->excp_model = POWERPC_EXCP_7x5; 5759 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5760 pcc->bfd_mach = bfd_mach_ppc_750; 5761 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5762 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5763 } 5764 5765 static void init_proc_7400(CPUPPCState *env) 5766 { 5767 register_ne_601_sprs(env); 5768 register_sdr1_sprs(env); 5769 register_7xx_sprs(env); 5770 /* Time base */ 5771 register_tbl(env); 5772 /* 74xx specific SPR */ 5773 register_74xx_sprs(env); 5774 vscr_init(env, 0x00010000); 5775 /* XXX : not implemented */ 5776 spr_register(env, SPR_UBAMR, "UBAMR", 5777 &spr_read_ureg, SPR_NOACCESS, 5778 &spr_read_ureg, SPR_NOACCESS, 5779 0x00000000); 5780 /* XXX: this seems not implemented on all revisions. */ 5781 /* XXX : not implemented */ 5782 spr_register(env, SPR_MSSCR1, "MSSCR1", 5783 SPR_NOACCESS, SPR_NOACCESS, 5784 &spr_read_generic, &spr_write_generic, 5785 0x00000000); 5786 /* Thermal management */ 5787 register_thrm_sprs(env); 5788 /* Memory management */ 5789 register_low_BATs(env); 5790 init_excp_7400(env); 5791 env->dcache_line_size = 32; 5792 env->icache_line_size = 32; 5793 /* Allocate hardware IRQ controller */ 5794 ppc6xx_irq_init(env_archcpu(env)); 5795 } 5796 5797 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5798 { 5799 DeviceClass *dc = DEVICE_CLASS(oc); 5800 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5801 5802 dc->desc = "PowerPC 7400 (aka G4)"; 5803 pcc->init_proc = init_proc_7400; 5804 pcc->check_pow = check_pow_hid0; 5805 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5806 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5807 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5808 PPC_FLOAT_STFIWX | 5809 PPC_CACHE | PPC_CACHE_ICBI | 5810 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5811 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5812 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5813 PPC_MEM_TLBIA | 5814 PPC_SEGMENT | PPC_EXTERN | 5815 PPC_ALTIVEC; 5816 pcc->msr_mask = (1ull << MSR_VR) | 5817 (1ull << MSR_POW) | 5818 (1ull << MSR_ILE) | 5819 (1ull << MSR_EE) | 5820 (1ull << MSR_PR) | 5821 (1ull << MSR_FP) | 5822 (1ull << MSR_ME) | 5823 (1ull << MSR_FE0) | 5824 (1ull << MSR_SE) | 5825 (1ull << MSR_DE) | 5826 (1ull << MSR_FE1) | 5827 (1ull << MSR_EP) | 5828 (1ull << MSR_IR) | 5829 (1ull << MSR_DR) | 5830 (1ull << MSR_PMM) | 5831 (1ull << MSR_RI) | 5832 (1ull << MSR_LE); 5833 pcc->mmu_model = POWERPC_MMU_32B; 5834 #if defined(CONFIG_SOFTMMU) 5835 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5836 #endif 5837 pcc->excp_model = POWERPC_EXCP_74xx; 5838 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5839 pcc->bfd_mach = bfd_mach_ppc_7400; 5840 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5841 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5842 POWERPC_FLAG_BUS_CLK; 5843 } 5844 5845 static void init_proc_7410(CPUPPCState *env) 5846 { 5847 register_ne_601_sprs(env); 5848 register_sdr1_sprs(env); 5849 register_7xx_sprs(env); 5850 /* Time base */ 5851 register_tbl(env); 5852 /* 74xx specific SPR */ 5853 register_74xx_sprs(env); 5854 vscr_init(env, 0x00010000); 5855 /* XXX : not implemented */ 5856 spr_register(env, SPR_UBAMR, "UBAMR", 5857 &spr_read_ureg, SPR_NOACCESS, 5858 &spr_read_ureg, SPR_NOACCESS, 5859 0x00000000); 5860 /* Thermal management */ 5861 register_thrm_sprs(env); 5862 /* L2PMCR */ 5863 /* XXX : not implemented */ 5864 spr_register(env, SPR_L2PMCR, "L2PMCR", 5865 SPR_NOACCESS, SPR_NOACCESS, 5866 &spr_read_generic, &spr_write_generic, 5867 0x00000000); 5868 /* LDSTDB */ 5869 /* XXX : not implemented */ 5870 spr_register(env, SPR_LDSTDB, "LDSTDB", 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 &spr_read_generic, &spr_write_generic, 5873 0x00000000); 5874 /* Memory management */ 5875 register_low_BATs(env); 5876 init_excp_7400(env); 5877 env->dcache_line_size = 32; 5878 env->icache_line_size = 32; 5879 /* Allocate hardware IRQ controller */ 5880 ppc6xx_irq_init(env_archcpu(env)); 5881 } 5882 5883 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5884 { 5885 DeviceClass *dc = DEVICE_CLASS(oc); 5886 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5887 5888 dc->desc = "PowerPC 7410 (aka G4)"; 5889 pcc->init_proc = init_proc_7410; 5890 pcc->check_pow = check_pow_hid0; 5891 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5892 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5893 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5894 PPC_FLOAT_STFIWX | 5895 PPC_CACHE | PPC_CACHE_ICBI | 5896 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5897 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5898 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5899 PPC_MEM_TLBIA | 5900 PPC_SEGMENT | PPC_EXTERN | 5901 PPC_ALTIVEC; 5902 pcc->msr_mask = (1ull << MSR_VR) | 5903 (1ull << MSR_POW) | 5904 (1ull << MSR_ILE) | 5905 (1ull << MSR_EE) | 5906 (1ull << MSR_PR) | 5907 (1ull << MSR_FP) | 5908 (1ull << MSR_ME) | 5909 (1ull << MSR_FE0) | 5910 (1ull << MSR_SE) | 5911 (1ull << MSR_DE) | 5912 (1ull << MSR_FE1) | 5913 (1ull << MSR_EP) | 5914 (1ull << MSR_IR) | 5915 (1ull << MSR_DR) | 5916 (1ull << MSR_PMM) | 5917 (1ull << MSR_RI) | 5918 (1ull << MSR_LE); 5919 pcc->mmu_model = POWERPC_MMU_32B; 5920 #if defined(CONFIG_SOFTMMU) 5921 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5922 #endif 5923 pcc->excp_model = POWERPC_EXCP_74xx; 5924 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5925 pcc->bfd_mach = bfd_mach_ppc_7400; 5926 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5927 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5928 POWERPC_FLAG_BUS_CLK; 5929 } 5930 5931 static void init_proc_7440(CPUPPCState *env) 5932 { 5933 register_ne_601_sprs(env); 5934 register_sdr1_sprs(env); 5935 register_7xx_sprs(env); 5936 /* Time base */ 5937 register_tbl(env); 5938 /* 74xx specific SPR */ 5939 register_74xx_sprs(env); 5940 vscr_init(env, 0x00010000); 5941 /* XXX : not implemented */ 5942 spr_register(env, SPR_UBAMR, "UBAMR", 5943 &spr_read_ureg, SPR_NOACCESS, 5944 &spr_read_ureg, SPR_NOACCESS, 5945 0x00000000); 5946 /* LDSTCR */ 5947 /* XXX : not implemented */ 5948 spr_register(env, SPR_LDSTCR, "LDSTCR", 5949 SPR_NOACCESS, SPR_NOACCESS, 5950 &spr_read_generic, &spr_write_generic, 5951 0x00000000); 5952 /* ICTRL */ 5953 /* XXX : not implemented */ 5954 spr_register(env, SPR_ICTRL, "ICTRL", 5955 SPR_NOACCESS, SPR_NOACCESS, 5956 &spr_read_generic, &spr_write_generic, 5957 0x00000000); 5958 /* MSSSR0 */ 5959 /* XXX : not implemented */ 5960 spr_register(env, SPR_MSSSR0, "MSSSR0", 5961 SPR_NOACCESS, SPR_NOACCESS, 5962 &spr_read_generic, &spr_write_generic, 5963 0x00000000); 5964 /* PMC */ 5965 /* XXX : not implemented */ 5966 spr_register(env, SPR_7XX_PMC5, "PMC5", 5967 SPR_NOACCESS, SPR_NOACCESS, 5968 &spr_read_generic, &spr_write_generic, 5969 0x00000000); 5970 /* XXX : not implemented */ 5971 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5972 &spr_read_ureg, SPR_NOACCESS, 5973 &spr_read_ureg, SPR_NOACCESS, 5974 0x00000000); 5975 /* XXX : not implemented */ 5976 spr_register(env, SPR_7XX_PMC6, "PMC6", 5977 SPR_NOACCESS, SPR_NOACCESS, 5978 &spr_read_generic, &spr_write_generic, 5979 0x00000000); 5980 /* XXX : not implemented */ 5981 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5982 &spr_read_ureg, SPR_NOACCESS, 5983 &spr_read_ureg, SPR_NOACCESS, 5984 0x00000000); 5985 /* Memory management */ 5986 register_low_BATs(env); 5987 register_74xx_soft_tlb(env, 128, 2); 5988 init_excp_7450(env); 5989 env->dcache_line_size = 32; 5990 env->icache_line_size = 32; 5991 /* Allocate hardware IRQ controller */ 5992 ppc6xx_irq_init(env_archcpu(env)); 5993 } 5994 5995 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5996 { 5997 DeviceClass *dc = DEVICE_CLASS(oc); 5998 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5999 6000 dc->desc = "PowerPC 7440 (aka G4)"; 6001 pcc->init_proc = init_proc_7440; 6002 pcc->check_pow = check_pow_hid0_74xx; 6003 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6004 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6005 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6006 PPC_FLOAT_STFIWX | 6007 PPC_CACHE | PPC_CACHE_ICBI | 6008 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6009 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6010 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6011 PPC_MEM_TLBIA | PPC_74xx_TLB | 6012 PPC_SEGMENT | PPC_EXTERN | 6013 PPC_ALTIVEC; 6014 pcc->msr_mask = (1ull << MSR_VR) | 6015 (1ull << MSR_POW) | 6016 (1ull << MSR_ILE) | 6017 (1ull << MSR_EE) | 6018 (1ull << MSR_PR) | 6019 (1ull << MSR_FP) | 6020 (1ull << MSR_ME) | 6021 (1ull << MSR_FE0) | 6022 (1ull << MSR_SE) | 6023 (1ull << MSR_DE) | 6024 (1ull << MSR_FE1) | 6025 (1ull << MSR_EP) | 6026 (1ull << MSR_IR) | 6027 (1ull << MSR_DR) | 6028 (1ull << MSR_PMM) | 6029 (1ull << MSR_RI) | 6030 (1ull << MSR_LE); 6031 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6032 pcc->excp_model = POWERPC_EXCP_74xx; 6033 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6034 pcc->bfd_mach = bfd_mach_ppc_7400; 6035 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6036 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6037 POWERPC_FLAG_BUS_CLK; 6038 } 6039 6040 static void init_proc_7450(CPUPPCState *env) 6041 { 6042 register_ne_601_sprs(env); 6043 register_sdr1_sprs(env); 6044 register_7xx_sprs(env); 6045 /* Time base */ 6046 register_tbl(env); 6047 /* 74xx specific SPR */ 6048 register_74xx_sprs(env); 6049 vscr_init(env, 0x00010000); 6050 /* Level 3 cache control */ 6051 register_l3_ctrl(env); 6052 /* L3ITCR1 */ 6053 /* XXX : not implemented */ 6054 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6055 SPR_NOACCESS, SPR_NOACCESS, 6056 &spr_read_generic, &spr_write_generic, 6057 0x00000000); 6058 /* L3ITCR2 */ 6059 /* XXX : not implemented */ 6060 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6061 SPR_NOACCESS, SPR_NOACCESS, 6062 &spr_read_generic, &spr_write_generic, 6063 0x00000000); 6064 /* L3ITCR3 */ 6065 /* XXX : not implemented */ 6066 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6067 SPR_NOACCESS, SPR_NOACCESS, 6068 &spr_read_generic, &spr_write_generic, 6069 0x00000000); 6070 /* L3OHCR */ 6071 /* XXX : not implemented */ 6072 spr_register(env, SPR_L3OHCR, "L3OHCR", 6073 SPR_NOACCESS, SPR_NOACCESS, 6074 &spr_read_generic, &spr_write_generic, 6075 0x00000000); 6076 /* XXX : not implemented */ 6077 spr_register(env, SPR_UBAMR, "UBAMR", 6078 &spr_read_ureg, SPR_NOACCESS, 6079 &spr_read_ureg, SPR_NOACCESS, 6080 0x00000000); 6081 /* LDSTCR */ 6082 /* XXX : not implemented */ 6083 spr_register(env, SPR_LDSTCR, "LDSTCR", 6084 SPR_NOACCESS, SPR_NOACCESS, 6085 &spr_read_generic, &spr_write_generic, 6086 0x00000000); 6087 /* ICTRL */ 6088 /* XXX : not implemented */ 6089 spr_register(env, SPR_ICTRL, "ICTRL", 6090 SPR_NOACCESS, SPR_NOACCESS, 6091 &spr_read_generic, &spr_write_generic, 6092 0x00000000); 6093 /* MSSSR0 */ 6094 /* XXX : not implemented */ 6095 spr_register(env, SPR_MSSSR0, "MSSSR0", 6096 SPR_NOACCESS, SPR_NOACCESS, 6097 &spr_read_generic, &spr_write_generic, 6098 0x00000000); 6099 /* PMC */ 6100 /* XXX : not implemented */ 6101 spr_register(env, SPR_7XX_PMC5, "PMC5", 6102 SPR_NOACCESS, SPR_NOACCESS, 6103 &spr_read_generic, &spr_write_generic, 6104 0x00000000); 6105 /* XXX : not implemented */ 6106 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6107 &spr_read_ureg, SPR_NOACCESS, 6108 &spr_read_ureg, SPR_NOACCESS, 6109 0x00000000); 6110 /* XXX : not implemented */ 6111 spr_register(env, SPR_7XX_PMC6, "PMC6", 6112 SPR_NOACCESS, SPR_NOACCESS, 6113 &spr_read_generic, &spr_write_generic, 6114 0x00000000); 6115 /* XXX : not implemented */ 6116 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6117 &spr_read_ureg, SPR_NOACCESS, 6118 &spr_read_ureg, SPR_NOACCESS, 6119 0x00000000); 6120 /* Memory management */ 6121 register_low_BATs(env); 6122 register_74xx_soft_tlb(env, 128, 2); 6123 init_excp_7450(env); 6124 env->dcache_line_size = 32; 6125 env->icache_line_size = 32; 6126 /* Allocate hardware IRQ controller */ 6127 ppc6xx_irq_init(env_archcpu(env)); 6128 } 6129 6130 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 6131 { 6132 DeviceClass *dc = DEVICE_CLASS(oc); 6133 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6134 6135 dc->desc = "PowerPC 7450 (aka G4)"; 6136 pcc->init_proc = init_proc_7450; 6137 pcc->check_pow = check_pow_hid0_74xx; 6138 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6139 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6140 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6141 PPC_FLOAT_STFIWX | 6142 PPC_CACHE | PPC_CACHE_ICBI | 6143 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6144 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6145 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6146 PPC_MEM_TLBIA | PPC_74xx_TLB | 6147 PPC_SEGMENT | PPC_EXTERN | 6148 PPC_ALTIVEC; 6149 pcc->msr_mask = (1ull << MSR_VR) | 6150 (1ull << MSR_POW) | 6151 (1ull << MSR_ILE) | 6152 (1ull << MSR_EE) | 6153 (1ull << MSR_PR) | 6154 (1ull << MSR_FP) | 6155 (1ull << MSR_ME) | 6156 (1ull << MSR_FE0) | 6157 (1ull << MSR_SE) | 6158 (1ull << MSR_DE) | 6159 (1ull << MSR_FE1) | 6160 (1ull << MSR_EP) | 6161 (1ull << MSR_IR) | 6162 (1ull << MSR_DR) | 6163 (1ull << MSR_PMM) | 6164 (1ull << MSR_RI) | 6165 (1ull << MSR_LE); 6166 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6167 pcc->excp_model = POWERPC_EXCP_74xx; 6168 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6169 pcc->bfd_mach = bfd_mach_ppc_7400; 6170 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6171 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6172 POWERPC_FLAG_BUS_CLK; 6173 } 6174 6175 static void init_proc_7445(CPUPPCState *env) 6176 { 6177 register_ne_601_sprs(env); 6178 register_sdr1_sprs(env); 6179 register_7xx_sprs(env); 6180 /* Time base */ 6181 register_tbl(env); 6182 /* 74xx specific SPR */ 6183 register_74xx_sprs(env); 6184 vscr_init(env, 0x00010000); 6185 /* LDSTCR */ 6186 /* XXX : not implemented */ 6187 spr_register(env, SPR_LDSTCR, "LDSTCR", 6188 SPR_NOACCESS, SPR_NOACCESS, 6189 &spr_read_generic, &spr_write_generic, 6190 0x00000000); 6191 /* ICTRL */ 6192 /* XXX : not implemented */ 6193 spr_register(env, SPR_ICTRL, "ICTRL", 6194 SPR_NOACCESS, SPR_NOACCESS, 6195 &spr_read_generic, &spr_write_generic, 6196 0x00000000); 6197 /* MSSSR0 */ 6198 /* XXX : not implemented */ 6199 spr_register(env, SPR_MSSSR0, "MSSSR0", 6200 SPR_NOACCESS, SPR_NOACCESS, 6201 &spr_read_generic, &spr_write_generic, 6202 0x00000000); 6203 /* PMC */ 6204 /* XXX : not implemented */ 6205 spr_register(env, SPR_7XX_PMC5, "PMC5", 6206 SPR_NOACCESS, SPR_NOACCESS, 6207 &spr_read_generic, &spr_write_generic, 6208 0x00000000); 6209 /* XXX : not implemented */ 6210 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6211 &spr_read_ureg, SPR_NOACCESS, 6212 &spr_read_ureg, SPR_NOACCESS, 6213 0x00000000); 6214 /* XXX : not implemented */ 6215 spr_register(env, SPR_7XX_PMC6, "PMC6", 6216 SPR_NOACCESS, SPR_NOACCESS, 6217 &spr_read_generic, &spr_write_generic, 6218 0x00000000); 6219 /* XXX : not implemented */ 6220 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6221 &spr_read_ureg, SPR_NOACCESS, 6222 &spr_read_ureg, SPR_NOACCESS, 6223 0x00000000); 6224 /* SPRGs */ 6225 spr_register(env, SPR_SPRG4, "SPRG4", 6226 SPR_NOACCESS, SPR_NOACCESS, 6227 &spr_read_generic, &spr_write_generic, 6228 0x00000000); 6229 spr_register(env, SPR_USPRG4, "USPRG4", 6230 &spr_read_ureg, SPR_NOACCESS, 6231 &spr_read_ureg, SPR_NOACCESS, 6232 0x00000000); 6233 spr_register(env, SPR_SPRG5, "SPRG5", 6234 SPR_NOACCESS, SPR_NOACCESS, 6235 &spr_read_generic, &spr_write_generic, 6236 0x00000000); 6237 spr_register(env, SPR_USPRG5, "USPRG5", 6238 &spr_read_ureg, SPR_NOACCESS, 6239 &spr_read_ureg, SPR_NOACCESS, 6240 0x00000000); 6241 spr_register(env, SPR_SPRG6, "SPRG6", 6242 SPR_NOACCESS, SPR_NOACCESS, 6243 &spr_read_generic, &spr_write_generic, 6244 0x00000000); 6245 spr_register(env, SPR_USPRG6, "USPRG6", 6246 &spr_read_ureg, SPR_NOACCESS, 6247 &spr_read_ureg, SPR_NOACCESS, 6248 0x00000000); 6249 spr_register(env, SPR_SPRG7, "SPRG7", 6250 SPR_NOACCESS, SPR_NOACCESS, 6251 &spr_read_generic, &spr_write_generic, 6252 0x00000000); 6253 spr_register(env, SPR_USPRG7, "USPRG7", 6254 &spr_read_ureg, SPR_NOACCESS, 6255 &spr_read_ureg, SPR_NOACCESS, 6256 0x00000000); 6257 /* Memory management */ 6258 register_low_BATs(env); 6259 register_high_BATs(env); 6260 register_74xx_soft_tlb(env, 128, 2); 6261 init_excp_7450(env); 6262 env->dcache_line_size = 32; 6263 env->icache_line_size = 32; 6264 /* Allocate hardware IRQ controller */ 6265 ppc6xx_irq_init(env_archcpu(env)); 6266 } 6267 6268 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 6269 { 6270 DeviceClass *dc = DEVICE_CLASS(oc); 6271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6272 6273 dc->desc = "PowerPC 7445 (aka G4)"; 6274 pcc->init_proc = init_proc_7445; 6275 pcc->check_pow = check_pow_hid0_74xx; 6276 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6277 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6278 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6279 PPC_FLOAT_STFIWX | 6280 PPC_CACHE | PPC_CACHE_ICBI | 6281 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6282 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6283 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6284 PPC_MEM_TLBIA | PPC_74xx_TLB | 6285 PPC_SEGMENT | PPC_EXTERN | 6286 PPC_ALTIVEC; 6287 pcc->msr_mask = (1ull << MSR_VR) | 6288 (1ull << MSR_POW) | 6289 (1ull << MSR_ILE) | 6290 (1ull << MSR_EE) | 6291 (1ull << MSR_PR) | 6292 (1ull << MSR_FP) | 6293 (1ull << MSR_ME) | 6294 (1ull << MSR_FE0) | 6295 (1ull << MSR_SE) | 6296 (1ull << MSR_DE) | 6297 (1ull << MSR_FE1) | 6298 (1ull << MSR_EP) | 6299 (1ull << MSR_IR) | 6300 (1ull << MSR_DR) | 6301 (1ull << MSR_PMM) | 6302 (1ull << MSR_RI) | 6303 (1ull << MSR_LE); 6304 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6305 pcc->excp_model = POWERPC_EXCP_74xx; 6306 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6307 pcc->bfd_mach = bfd_mach_ppc_7400; 6308 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6309 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6310 POWERPC_FLAG_BUS_CLK; 6311 } 6312 6313 static void init_proc_7455(CPUPPCState *env) 6314 { 6315 register_ne_601_sprs(env); 6316 register_sdr1_sprs(env); 6317 register_7xx_sprs(env); 6318 /* Time base */ 6319 register_tbl(env); 6320 /* 74xx specific SPR */ 6321 register_74xx_sprs(env); 6322 vscr_init(env, 0x00010000); 6323 /* Level 3 cache control */ 6324 register_l3_ctrl(env); 6325 /* LDSTCR */ 6326 /* XXX : not implemented */ 6327 spr_register(env, SPR_LDSTCR, "LDSTCR", 6328 SPR_NOACCESS, SPR_NOACCESS, 6329 &spr_read_generic, &spr_write_generic, 6330 0x00000000); 6331 /* ICTRL */ 6332 /* XXX : not implemented */ 6333 spr_register(env, SPR_ICTRL, "ICTRL", 6334 SPR_NOACCESS, SPR_NOACCESS, 6335 &spr_read_generic, &spr_write_generic, 6336 0x00000000); 6337 /* MSSSR0 */ 6338 /* XXX : not implemented */ 6339 spr_register(env, SPR_MSSSR0, "MSSSR0", 6340 SPR_NOACCESS, SPR_NOACCESS, 6341 &spr_read_generic, &spr_write_generic, 6342 0x00000000); 6343 /* PMC */ 6344 /* XXX : not implemented */ 6345 spr_register(env, SPR_7XX_PMC5, "PMC5", 6346 SPR_NOACCESS, SPR_NOACCESS, 6347 &spr_read_generic, &spr_write_generic, 6348 0x00000000); 6349 /* XXX : not implemented */ 6350 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6351 &spr_read_ureg, SPR_NOACCESS, 6352 &spr_read_ureg, SPR_NOACCESS, 6353 0x00000000); 6354 /* XXX : not implemented */ 6355 spr_register(env, SPR_7XX_PMC6, "PMC6", 6356 SPR_NOACCESS, SPR_NOACCESS, 6357 &spr_read_generic, &spr_write_generic, 6358 0x00000000); 6359 /* XXX : not implemented */ 6360 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6361 &spr_read_ureg, SPR_NOACCESS, 6362 &spr_read_ureg, SPR_NOACCESS, 6363 0x00000000); 6364 /* SPRGs */ 6365 spr_register(env, SPR_SPRG4, "SPRG4", 6366 SPR_NOACCESS, SPR_NOACCESS, 6367 &spr_read_generic, &spr_write_generic, 6368 0x00000000); 6369 spr_register(env, SPR_USPRG4, "USPRG4", 6370 &spr_read_ureg, SPR_NOACCESS, 6371 &spr_read_ureg, SPR_NOACCESS, 6372 0x00000000); 6373 spr_register(env, SPR_SPRG5, "SPRG5", 6374 SPR_NOACCESS, SPR_NOACCESS, 6375 &spr_read_generic, &spr_write_generic, 6376 0x00000000); 6377 spr_register(env, SPR_USPRG5, "USPRG5", 6378 &spr_read_ureg, SPR_NOACCESS, 6379 &spr_read_ureg, SPR_NOACCESS, 6380 0x00000000); 6381 spr_register(env, SPR_SPRG6, "SPRG6", 6382 SPR_NOACCESS, SPR_NOACCESS, 6383 &spr_read_generic, &spr_write_generic, 6384 0x00000000); 6385 spr_register(env, SPR_USPRG6, "USPRG6", 6386 &spr_read_ureg, SPR_NOACCESS, 6387 &spr_read_ureg, SPR_NOACCESS, 6388 0x00000000); 6389 spr_register(env, SPR_SPRG7, "SPRG7", 6390 SPR_NOACCESS, SPR_NOACCESS, 6391 &spr_read_generic, &spr_write_generic, 6392 0x00000000); 6393 spr_register(env, SPR_USPRG7, "USPRG7", 6394 &spr_read_ureg, SPR_NOACCESS, 6395 &spr_read_ureg, SPR_NOACCESS, 6396 0x00000000); 6397 /* Memory management */ 6398 register_low_BATs(env); 6399 register_high_BATs(env); 6400 register_74xx_soft_tlb(env, 128, 2); 6401 init_excp_7450(env); 6402 env->dcache_line_size = 32; 6403 env->icache_line_size = 32; 6404 /* Allocate hardware IRQ controller */ 6405 ppc6xx_irq_init(env_archcpu(env)); 6406 } 6407 6408 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 6409 { 6410 DeviceClass *dc = DEVICE_CLASS(oc); 6411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6412 6413 dc->desc = "PowerPC 7455 (aka G4)"; 6414 pcc->init_proc = init_proc_7455; 6415 pcc->check_pow = check_pow_hid0_74xx; 6416 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6417 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6418 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6419 PPC_FLOAT_STFIWX | 6420 PPC_CACHE | PPC_CACHE_ICBI | 6421 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6422 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6423 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6424 PPC_MEM_TLBIA | PPC_74xx_TLB | 6425 PPC_SEGMENT | PPC_EXTERN | 6426 PPC_ALTIVEC; 6427 pcc->msr_mask = (1ull << MSR_VR) | 6428 (1ull << MSR_POW) | 6429 (1ull << MSR_ILE) | 6430 (1ull << MSR_EE) | 6431 (1ull << MSR_PR) | 6432 (1ull << MSR_FP) | 6433 (1ull << MSR_ME) | 6434 (1ull << MSR_FE0) | 6435 (1ull << MSR_SE) | 6436 (1ull << MSR_DE) | 6437 (1ull << MSR_FE1) | 6438 (1ull << MSR_EP) | 6439 (1ull << MSR_IR) | 6440 (1ull << MSR_DR) | 6441 (1ull << MSR_PMM) | 6442 (1ull << MSR_RI) | 6443 (1ull << MSR_LE); 6444 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6445 pcc->excp_model = POWERPC_EXCP_74xx; 6446 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6447 pcc->bfd_mach = bfd_mach_ppc_7400; 6448 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6449 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6450 POWERPC_FLAG_BUS_CLK; 6451 } 6452 6453 static void init_proc_7457(CPUPPCState *env) 6454 { 6455 register_ne_601_sprs(env); 6456 register_sdr1_sprs(env); 6457 register_7xx_sprs(env); 6458 /* Time base */ 6459 register_tbl(env); 6460 /* 74xx specific SPR */ 6461 register_74xx_sprs(env); 6462 vscr_init(env, 0x00010000); 6463 /* Level 3 cache control */ 6464 register_l3_ctrl(env); 6465 /* L3ITCR1 */ 6466 /* XXX : not implemented */ 6467 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6468 SPR_NOACCESS, SPR_NOACCESS, 6469 &spr_read_generic, &spr_write_generic, 6470 0x00000000); 6471 /* L3ITCR2 */ 6472 /* XXX : not implemented */ 6473 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6474 SPR_NOACCESS, SPR_NOACCESS, 6475 &spr_read_generic, &spr_write_generic, 6476 0x00000000); 6477 /* L3ITCR3 */ 6478 /* XXX : not implemented */ 6479 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6480 SPR_NOACCESS, SPR_NOACCESS, 6481 &spr_read_generic, &spr_write_generic, 6482 0x00000000); 6483 /* L3OHCR */ 6484 /* XXX : not implemented */ 6485 spr_register(env, SPR_L3OHCR, "L3OHCR", 6486 SPR_NOACCESS, SPR_NOACCESS, 6487 &spr_read_generic, &spr_write_generic, 6488 0x00000000); 6489 /* LDSTCR */ 6490 /* XXX : not implemented */ 6491 spr_register(env, SPR_LDSTCR, "LDSTCR", 6492 SPR_NOACCESS, SPR_NOACCESS, 6493 &spr_read_generic, &spr_write_generic, 6494 0x00000000); 6495 /* ICTRL */ 6496 /* XXX : not implemented */ 6497 spr_register(env, SPR_ICTRL, "ICTRL", 6498 SPR_NOACCESS, SPR_NOACCESS, 6499 &spr_read_generic, &spr_write_generic, 6500 0x00000000); 6501 /* MSSSR0 */ 6502 /* XXX : not implemented */ 6503 spr_register(env, SPR_MSSSR0, "MSSSR0", 6504 SPR_NOACCESS, SPR_NOACCESS, 6505 &spr_read_generic, &spr_write_generic, 6506 0x00000000); 6507 /* PMC */ 6508 /* XXX : not implemented */ 6509 spr_register(env, SPR_7XX_PMC5, "PMC5", 6510 SPR_NOACCESS, SPR_NOACCESS, 6511 &spr_read_generic, &spr_write_generic, 6512 0x00000000); 6513 /* XXX : not implemented */ 6514 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6515 &spr_read_ureg, SPR_NOACCESS, 6516 &spr_read_ureg, SPR_NOACCESS, 6517 0x00000000); 6518 /* XXX : not implemented */ 6519 spr_register(env, SPR_7XX_PMC6, "PMC6", 6520 SPR_NOACCESS, SPR_NOACCESS, 6521 &spr_read_generic, &spr_write_generic, 6522 0x00000000); 6523 /* XXX : not implemented */ 6524 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6525 &spr_read_ureg, SPR_NOACCESS, 6526 &spr_read_ureg, SPR_NOACCESS, 6527 0x00000000); 6528 /* SPRGs */ 6529 spr_register(env, SPR_SPRG4, "SPRG4", 6530 SPR_NOACCESS, SPR_NOACCESS, 6531 &spr_read_generic, &spr_write_generic, 6532 0x00000000); 6533 spr_register(env, SPR_USPRG4, "USPRG4", 6534 &spr_read_ureg, SPR_NOACCESS, 6535 &spr_read_ureg, SPR_NOACCESS, 6536 0x00000000); 6537 spr_register(env, SPR_SPRG5, "SPRG5", 6538 SPR_NOACCESS, SPR_NOACCESS, 6539 &spr_read_generic, &spr_write_generic, 6540 0x00000000); 6541 spr_register(env, SPR_USPRG5, "USPRG5", 6542 &spr_read_ureg, SPR_NOACCESS, 6543 &spr_read_ureg, SPR_NOACCESS, 6544 0x00000000); 6545 spr_register(env, SPR_SPRG6, "SPRG6", 6546 SPR_NOACCESS, SPR_NOACCESS, 6547 &spr_read_generic, &spr_write_generic, 6548 0x00000000); 6549 spr_register(env, SPR_USPRG6, "USPRG6", 6550 &spr_read_ureg, SPR_NOACCESS, 6551 &spr_read_ureg, SPR_NOACCESS, 6552 0x00000000); 6553 spr_register(env, SPR_SPRG7, "SPRG7", 6554 SPR_NOACCESS, SPR_NOACCESS, 6555 &spr_read_generic, &spr_write_generic, 6556 0x00000000); 6557 spr_register(env, SPR_USPRG7, "USPRG7", 6558 &spr_read_ureg, SPR_NOACCESS, 6559 &spr_read_ureg, SPR_NOACCESS, 6560 0x00000000); 6561 /* Memory management */ 6562 register_low_BATs(env); 6563 register_high_BATs(env); 6564 register_74xx_soft_tlb(env, 128, 2); 6565 init_excp_7450(env); 6566 env->dcache_line_size = 32; 6567 env->icache_line_size = 32; 6568 /* Allocate hardware IRQ controller */ 6569 ppc6xx_irq_init(env_archcpu(env)); 6570 } 6571 6572 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 6573 { 6574 DeviceClass *dc = DEVICE_CLASS(oc); 6575 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6576 6577 dc->desc = "PowerPC 7457 (aka G4)"; 6578 pcc->init_proc = init_proc_7457; 6579 pcc->check_pow = check_pow_hid0_74xx; 6580 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6581 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6582 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6583 PPC_FLOAT_STFIWX | 6584 PPC_CACHE | PPC_CACHE_ICBI | 6585 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6586 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6587 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6588 PPC_MEM_TLBIA | PPC_74xx_TLB | 6589 PPC_SEGMENT | PPC_EXTERN | 6590 PPC_ALTIVEC; 6591 pcc->msr_mask = (1ull << MSR_VR) | 6592 (1ull << MSR_POW) | 6593 (1ull << MSR_ILE) | 6594 (1ull << MSR_EE) | 6595 (1ull << MSR_PR) | 6596 (1ull << MSR_FP) | 6597 (1ull << MSR_ME) | 6598 (1ull << MSR_FE0) | 6599 (1ull << MSR_SE) | 6600 (1ull << MSR_DE) | 6601 (1ull << MSR_FE1) | 6602 (1ull << MSR_EP) | 6603 (1ull << MSR_IR) | 6604 (1ull << MSR_DR) | 6605 (1ull << MSR_PMM) | 6606 (1ull << MSR_RI) | 6607 (1ull << MSR_LE); 6608 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6609 pcc->excp_model = POWERPC_EXCP_74xx; 6610 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6611 pcc->bfd_mach = bfd_mach_ppc_7400; 6612 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6613 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6614 POWERPC_FLAG_BUS_CLK; 6615 } 6616 6617 static void init_proc_e600(CPUPPCState *env) 6618 { 6619 register_ne_601_sprs(env); 6620 register_sdr1_sprs(env); 6621 register_7xx_sprs(env); 6622 /* Time base */ 6623 register_tbl(env); 6624 /* 74xx specific SPR */ 6625 register_74xx_sprs(env); 6626 vscr_init(env, 0x00010000); 6627 /* XXX : not implemented */ 6628 spr_register(env, SPR_UBAMR, "UBAMR", 6629 &spr_read_ureg, SPR_NOACCESS, 6630 &spr_read_ureg, SPR_NOACCESS, 6631 0x00000000); 6632 /* XXX : not implemented */ 6633 spr_register(env, SPR_LDSTCR, "LDSTCR", 6634 SPR_NOACCESS, SPR_NOACCESS, 6635 &spr_read_generic, &spr_write_generic, 6636 0x00000000); 6637 /* XXX : not implemented */ 6638 spr_register(env, SPR_ICTRL, "ICTRL", 6639 SPR_NOACCESS, SPR_NOACCESS, 6640 &spr_read_generic, &spr_write_generic, 6641 0x00000000); 6642 /* XXX : not implemented */ 6643 spr_register(env, SPR_MSSSR0, "MSSSR0", 6644 SPR_NOACCESS, SPR_NOACCESS, 6645 &spr_read_generic, &spr_write_generic, 6646 0x00000000); 6647 /* XXX : not implemented */ 6648 spr_register(env, SPR_7XX_PMC5, "PMC5", 6649 SPR_NOACCESS, SPR_NOACCESS, 6650 &spr_read_generic, &spr_write_generic, 6651 0x00000000); 6652 /* XXX : not implemented */ 6653 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6654 &spr_read_ureg, SPR_NOACCESS, 6655 &spr_read_ureg, SPR_NOACCESS, 6656 0x00000000); 6657 /* XXX : not implemented */ 6658 spr_register(env, SPR_7XX_PMC6, "PMC6", 6659 SPR_NOACCESS, SPR_NOACCESS, 6660 &spr_read_generic, &spr_write_generic, 6661 0x00000000); 6662 /* XXX : not implemented */ 6663 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6664 &spr_read_ureg, SPR_NOACCESS, 6665 &spr_read_ureg, SPR_NOACCESS, 6666 0x00000000); 6667 /* SPRGs */ 6668 spr_register(env, SPR_SPRG4, "SPRG4", 6669 SPR_NOACCESS, SPR_NOACCESS, 6670 &spr_read_generic, &spr_write_generic, 6671 0x00000000); 6672 spr_register(env, SPR_USPRG4, "USPRG4", 6673 &spr_read_ureg, SPR_NOACCESS, 6674 &spr_read_ureg, SPR_NOACCESS, 6675 0x00000000); 6676 spr_register(env, SPR_SPRG5, "SPRG5", 6677 SPR_NOACCESS, SPR_NOACCESS, 6678 &spr_read_generic, &spr_write_generic, 6679 0x00000000); 6680 spr_register(env, SPR_USPRG5, "USPRG5", 6681 &spr_read_ureg, SPR_NOACCESS, 6682 &spr_read_ureg, SPR_NOACCESS, 6683 0x00000000); 6684 spr_register(env, SPR_SPRG6, "SPRG6", 6685 SPR_NOACCESS, SPR_NOACCESS, 6686 &spr_read_generic, &spr_write_generic, 6687 0x00000000); 6688 spr_register(env, SPR_USPRG6, "USPRG6", 6689 &spr_read_ureg, SPR_NOACCESS, 6690 &spr_read_ureg, SPR_NOACCESS, 6691 0x00000000); 6692 spr_register(env, SPR_SPRG7, "SPRG7", 6693 SPR_NOACCESS, SPR_NOACCESS, 6694 &spr_read_generic, &spr_write_generic, 6695 0x00000000); 6696 spr_register(env, SPR_USPRG7, "USPRG7", 6697 &spr_read_ureg, SPR_NOACCESS, 6698 &spr_read_ureg, SPR_NOACCESS, 6699 0x00000000); 6700 /* Memory management */ 6701 register_low_BATs(env); 6702 register_high_BATs(env); 6703 register_74xx_soft_tlb(env, 128, 2); 6704 init_excp_7450(env); 6705 env->dcache_line_size = 32; 6706 env->icache_line_size = 32; 6707 /* Allocate hardware IRQ controller */ 6708 ppc6xx_irq_init(env_archcpu(env)); 6709 } 6710 6711 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 6712 { 6713 DeviceClass *dc = DEVICE_CLASS(oc); 6714 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6715 6716 dc->desc = "PowerPC e600"; 6717 pcc->init_proc = init_proc_e600; 6718 pcc->check_pow = check_pow_hid0_74xx; 6719 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6720 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6721 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6722 PPC_FLOAT_STFIWX | 6723 PPC_CACHE | PPC_CACHE_ICBI | 6724 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6725 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6726 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6727 PPC_MEM_TLBIA | PPC_74xx_TLB | 6728 PPC_SEGMENT | PPC_EXTERN | 6729 PPC_ALTIVEC; 6730 pcc->insns_flags2 = PPC_NONE; 6731 pcc->msr_mask = (1ull << MSR_VR) | 6732 (1ull << MSR_POW) | 6733 (1ull << MSR_ILE) | 6734 (1ull << MSR_EE) | 6735 (1ull << MSR_PR) | 6736 (1ull << MSR_FP) | 6737 (1ull << MSR_ME) | 6738 (1ull << MSR_FE0) | 6739 (1ull << MSR_SE) | 6740 (1ull << MSR_DE) | 6741 (1ull << MSR_FE1) | 6742 (1ull << MSR_EP) | 6743 (1ull << MSR_IR) | 6744 (1ull << MSR_DR) | 6745 (1ull << MSR_PMM) | 6746 (1ull << MSR_RI) | 6747 (1ull << MSR_LE); 6748 pcc->mmu_model = POWERPC_MMU_32B; 6749 #if defined(CONFIG_SOFTMMU) 6750 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6751 #endif 6752 pcc->excp_model = POWERPC_EXCP_74xx; 6753 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6754 pcc->bfd_mach = bfd_mach_ppc_7400; 6755 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6756 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6757 POWERPC_FLAG_BUS_CLK; 6758 } 6759 6760 #if defined(TARGET_PPC64) 6761 #if defined(CONFIG_USER_ONLY) 6762 #define POWERPC970_HID5_INIT 0x00000080 6763 #else 6764 #define POWERPC970_HID5_INIT 0x00000000 6765 #endif 6766 6767 static int check_pow_970(CPUPPCState *env) 6768 { 6769 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6770 return 1; 6771 } 6772 6773 return 0; 6774 } 6775 6776 static void register_970_hid_sprs(CPUPPCState *env) 6777 { 6778 /* Hardware implementation registers */ 6779 /* XXX : not implemented */ 6780 spr_register(env, SPR_HID0, "HID0", 6781 SPR_NOACCESS, SPR_NOACCESS, 6782 &spr_read_generic, &spr_write_clear, 6783 0x60000000); 6784 spr_register(env, SPR_HID1, "HID1", 6785 SPR_NOACCESS, SPR_NOACCESS, 6786 &spr_read_generic, &spr_write_generic, 6787 0x00000000); 6788 spr_register(env, SPR_970_HID5, "HID5", 6789 SPR_NOACCESS, SPR_NOACCESS, 6790 &spr_read_generic, &spr_write_generic, 6791 POWERPC970_HID5_INIT); 6792 } 6793 6794 static void register_970_hior_sprs(CPUPPCState *env) 6795 { 6796 spr_register(env, SPR_HIOR, "SPR_HIOR", 6797 SPR_NOACCESS, SPR_NOACCESS, 6798 &spr_read_hior, &spr_write_hior, 6799 0x00000000); 6800 } 6801 6802 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6803 { 6804 spr_register(env, SPR_CTRL, "SPR_CTRL", 6805 SPR_NOACCESS, SPR_NOACCESS, 6806 SPR_NOACCESS, &spr_write_generic, 6807 0x00000000); 6808 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6809 &spr_read_ureg, SPR_NOACCESS, 6810 &spr_read_ureg, SPR_NOACCESS, 6811 0x00000000); 6812 } 6813 6814 static void register_book3s_altivec_sprs(CPUPPCState *env) 6815 { 6816 if (!(env->insns_flags & PPC_ALTIVEC)) { 6817 return; 6818 } 6819 6820 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6821 &spr_read_generic, &spr_write_generic, 6822 &spr_read_generic, &spr_write_generic, 6823 KVM_REG_PPC_VRSAVE, 0x00000000); 6824 6825 } 6826 6827 static void register_book3s_dbg_sprs(CPUPPCState *env) 6828 { 6829 /* 6830 * TODO: different specs define different scopes for these, 6831 * will have to address this: 6832 * 970: super/write and super/read 6833 * powerisa 2.03..2.04: hypv/write and super/read. 6834 * powerisa 2.05 and newer: hypv/write and hypv/read. 6835 */ 6836 spr_register_kvm(env, SPR_DABR, "DABR", 6837 SPR_NOACCESS, SPR_NOACCESS, 6838 &spr_read_generic, &spr_write_generic, 6839 KVM_REG_PPC_DABR, 0x00000000); 6840 spr_register_kvm(env, SPR_DABRX, "DABRX", 6841 SPR_NOACCESS, SPR_NOACCESS, 6842 &spr_read_generic, &spr_write_generic, 6843 KVM_REG_PPC_DABRX, 0x00000000); 6844 } 6845 6846 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6847 { 6848 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6849 SPR_NOACCESS, SPR_NOACCESS, 6850 SPR_NOACCESS, SPR_NOACCESS, 6851 &spr_read_generic, &spr_write_generic, 6852 KVM_REG_PPC_DAWR, 0x00000000); 6853 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6854 SPR_NOACCESS, SPR_NOACCESS, 6855 SPR_NOACCESS, SPR_NOACCESS, 6856 &spr_read_generic, &spr_write_generic, 6857 KVM_REG_PPC_DAWRX, 0x00000000); 6858 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6859 SPR_NOACCESS, SPR_NOACCESS, 6860 SPR_NOACCESS, SPR_NOACCESS, 6861 &spr_read_generic, &spr_write_generic, 6862 KVM_REG_PPC_CIABR, 0x00000000); 6863 } 6864 6865 static void register_970_dbg_sprs(CPUPPCState *env) 6866 { 6867 /* Breakpoints */ 6868 spr_register(env, SPR_IABR, "IABR", 6869 SPR_NOACCESS, SPR_NOACCESS, 6870 &spr_read_generic, &spr_write_generic, 6871 0x00000000); 6872 } 6873 6874 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6875 { 6876 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6877 SPR_NOACCESS, SPR_NOACCESS, 6878 &spr_read_generic, &spr_write_generic, 6879 KVM_REG_PPC_MMCR0, 0x00000000); 6880 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6881 SPR_NOACCESS, SPR_NOACCESS, 6882 &spr_read_generic, &spr_write_generic, 6883 KVM_REG_PPC_MMCR1, 0x00000000); 6884 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6885 SPR_NOACCESS, SPR_NOACCESS, 6886 &spr_read_generic, &spr_write_generic, 6887 KVM_REG_PPC_MMCRA, 0x00000000); 6888 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6889 SPR_NOACCESS, SPR_NOACCESS, 6890 &spr_read_generic, &spr_write_generic, 6891 KVM_REG_PPC_PMC1, 0x00000000); 6892 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6893 SPR_NOACCESS, SPR_NOACCESS, 6894 &spr_read_generic, &spr_write_generic, 6895 KVM_REG_PPC_PMC2, 0x00000000); 6896 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6897 SPR_NOACCESS, SPR_NOACCESS, 6898 &spr_read_generic, &spr_write_generic, 6899 KVM_REG_PPC_PMC3, 0x00000000); 6900 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6901 SPR_NOACCESS, SPR_NOACCESS, 6902 &spr_read_generic, &spr_write_generic, 6903 KVM_REG_PPC_PMC4, 0x00000000); 6904 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6905 SPR_NOACCESS, SPR_NOACCESS, 6906 &spr_read_generic, &spr_write_generic, 6907 KVM_REG_PPC_PMC5, 0x00000000); 6908 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6909 SPR_NOACCESS, SPR_NOACCESS, 6910 &spr_read_generic, &spr_write_generic, 6911 KVM_REG_PPC_PMC6, 0x00000000); 6912 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6913 SPR_NOACCESS, SPR_NOACCESS, 6914 &spr_read_generic, &spr_write_generic, 6915 KVM_REG_PPC_SIAR, 0x00000000); 6916 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6917 SPR_NOACCESS, SPR_NOACCESS, 6918 &spr_read_generic, &spr_write_generic, 6919 KVM_REG_PPC_SDAR, 0x00000000); 6920 } 6921 6922 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6923 { 6924 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6925 &spr_read_ureg, SPR_NOACCESS, 6926 &spr_read_ureg, &spr_write_ureg, 6927 0x00000000); 6928 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6929 &spr_read_ureg, SPR_NOACCESS, 6930 &spr_read_ureg, &spr_write_ureg, 6931 0x00000000); 6932 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6933 &spr_read_ureg, SPR_NOACCESS, 6934 &spr_read_ureg, &spr_write_ureg, 6935 0x00000000); 6936 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6937 &spr_read_ureg, SPR_NOACCESS, 6938 &spr_read_ureg, &spr_write_ureg, 6939 0x00000000); 6940 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6941 &spr_read_ureg, SPR_NOACCESS, 6942 &spr_read_ureg, &spr_write_ureg, 6943 0x00000000); 6944 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6945 &spr_read_ureg, SPR_NOACCESS, 6946 &spr_read_ureg, &spr_write_ureg, 6947 0x00000000); 6948 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6949 &spr_read_ureg, SPR_NOACCESS, 6950 &spr_read_ureg, &spr_write_ureg, 6951 0x00000000); 6952 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6953 &spr_read_ureg, SPR_NOACCESS, 6954 &spr_read_ureg, &spr_write_ureg, 6955 0x00000000); 6956 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6957 &spr_read_ureg, SPR_NOACCESS, 6958 &spr_read_ureg, &spr_write_ureg, 6959 0x00000000); 6960 spr_register(env, SPR_POWER_USIAR, "USIAR", 6961 &spr_read_ureg, SPR_NOACCESS, 6962 &spr_read_ureg, &spr_write_ureg, 6963 0x00000000); 6964 spr_register(env, SPR_POWER_USDAR, "USDAR", 6965 &spr_read_ureg, SPR_NOACCESS, 6966 &spr_read_ureg, &spr_write_ureg, 6967 0x00000000); 6968 } 6969 6970 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6971 { 6972 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6973 SPR_NOACCESS, SPR_NOACCESS, 6974 &spr_read_generic, &spr_write_generic, 6975 KVM_REG_PPC_PMC7, 0x00000000); 6976 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6977 SPR_NOACCESS, SPR_NOACCESS, 6978 &spr_read_generic, &spr_write_generic, 6979 KVM_REG_PPC_PMC8, 0x00000000); 6980 } 6981 6982 static void register_970_pmu_user_sprs(CPUPPCState *env) 6983 { 6984 spr_register(env, SPR_970_UPMC7, "UPMC7", 6985 &spr_read_ureg, SPR_NOACCESS, 6986 &spr_read_ureg, &spr_write_ureg, 6987 0x00000000); 6988 spr_register(env, SPR_970_UPMC8, "UPMC8", 6989 &spr_read_ureg, SPR_NOACCESS, 6990 &spr_read_ureg, &spr_write_ureg, 6991 0x00000000); 6992 } 6993 6994 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6995 { 6996 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6997 SPR_NOACCESS, SPR_NOACCESS, 6998 &spr_read_generic, &spr_write_generic, 6999 KVM_REG_PPC_MMCR2, 0x00000000); 7000 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 7001 SPR_NOACCESS, SPR_NOACCESS, 7002 &spr_read_generic, &spr_write_generic, 7003 KVM_REG_PPC_MMCRS, 0x00000000); 7004 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 7005 SPR_NOACCESS, SPR_NOACCESS, 7006 &spr_read_generic, &spr_write_generic, 7007 KVM_REG_PPC_SIER, 0x00000000); 7008 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 7009 SPR_NOACCESS, SPR_NOACCESS, 7010 &spr_read_generic, &spr_write_generic, 7011 KVM_REG_PPC_SPMC1, 0x00000000); 7012 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 7013 SPR_NOACCESS, SPR_NOACCESS, 7014 &spr_read_generic, &spr_write_generic, 7015 KVM_REG_PPC_SPMC2, 0x00000000); 7016 spr_register_kvm(env, SPR_TACR, "TACR", 7017 SPR_NOACCESS, SPR_NOACCESS, 7018 &spr_read_generic, &spr_write_generic, 7019 KVM_REG_PPC_TACR, 0x00000000); 7020 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 7021 SPR_NOACCESS, SPR_NOACCESS, 7022 &spr_read_generic, &spr_write_generic, 7023 KVM_REG_PPC_TCSCR, 0x00000000); 7024 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 7025 SPR_NOACCESS, SPR_NOACCESS, 7026 &spr_read_generic, &spr_write_generic, 7027 KVM_REG_PPC_CSIGR, 0x00000000); 7028 } 7029 7030 static void register_power8_pmu_user_sprs(CPUPPCState *env) 7031 { 7032 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 7033 &spr_read_ureg, SPR_NOACCESS, 7034 &spr_read_ureg, &spr_write_ureg, 7035 0x00000000); 7036 spr_register(env, SPR_POWER_USIER, "USIER", 7037 &spr_read_generic, SPR_NOACCESS, 7038 &spr_read_generic, &spr_write_generic, 7039 0x00000000); 7040 } 7041 7042 static void register_power5p_ear_sprs(CPUPPCState *env) 7043 { 7044 /* External access control */ 7045 spr_register(env, SPR_EAR, "EAR", 7046 SPR_NOACCESS, SPR_NOACCESS, 7047 &spr_read_generic, &spr_write_generic, 7048 0x00000000); 7049 } 7050 7051 static void register_power5p_tb_sprs(CPUPPCState *env) 7052 { 7053 /* TBU40 (High 40 bits of the Timebase register */ 7054 spr_register_hv(env, SPR_TBU40, "TBU40", 7055 SPR_NOACCESS, SPR_NOACCESS, 7056 SPR_NOACCESS, SPR_NOACCESS, 7057 SPR_NOACCESS, &spr_write_tbu40, 7058 0x00000000); 7059 } 7060 7061 static void register_970_lpar_sprs(CPUPPCState *env) 7062 { 7063 #if !defined(CONFIG_USER_ONLY) 7064 /* 7065 * PPC970: HID4 covers things later controlled by the LPCR and 7066 * RMOR in later CPUs, but with a different encoding. We only 7067 * support the 970 in "Apple mode" which has all hypervisor 7068 * facilities disabled by strapping, so we can basically just 7069 * ignore it 7070 */ 7071 spr_register(env, SPR_970_HID4, "HID4", 7072 SPR_NOACCESS, SPR_NOACCESS, 7073 &spr_read_generic, &spr_write_generic, 7074 0x00000000); 7075 #endif 7076 } 7077 7078 static void register_power5p_lpar_sprs(CPUPPCState *env) 7079 { 7080 #if !defined(CONFIG_USER_ONLY) 7081 /* Logical partitionning */ 7082 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 7083 SPR_NOACCESS, SPR_NOACCESS, 7084 SPR_NOACCESS, SPR_NOACCESS, 7085 &spr_read_generic, &spr_write_lpcr, 7086 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 7087 spr_register_hv(env, SPR_HDEC, "HDEC", 7088 SPR_NOACCESS, SPR_NOACCESS, 7089 SPR_NOACCESS, SPR_NOACCESS, 7090 &spr_read_hdecr, &spr_write_hdecr, 0); 7091 #endif 7092 } 7093 7094 static void register_book3s_ids_sprs(CPUPPCState *env) 7095 { 7096 /* FIXME: Will need to deal with thread vs core only SPRs */ 7097 7098 /* Processor identification */ 7099 spr_register_hv(env, SPR_PIR, "PIR", 7100 SPR_NOACCESS, SPR_NOACCESS, 7101 &spr_read_generic, SPR_NOACCESS, 7102 &spr_read_generic, NULL, 7103 0x00000000); 7104 spr_register_hv(env, SPR_HID0, "HID0", 7105 SPR_NOACCESS, SPR_NOACCESS, 7106 SPR_NOACCESS, SPR_NOACCESS, 7107 &spr_read_generic, &spr_write_generic, 7108 0x00000000); 7109 spr_register_hv(env, SPR_TSCR, "TSCR", 7110 SPR_NOACCESS, SPR_NOACCESS, 7111 SPR_NOACCESS, SPR_NOACCESS, 7112 &spr_read_generic, &spr_write_generic, 7113 0x00000000); 7114 spr_register_hv(env, SPR_HMER, "HMER", 7115 SPR_NOACCESS, SPR_NOACCESS, 7116 SPR_NOACCESS, SPR_NOACCESS, 7117 &spr_read_generic, &spr_write_hmer, 7118 0x00000000); 7119 spr_register_hv(env, SPR_HMEER, "HMEER", 7120 SPR_NOACCESS, SPR_NOACCESS, 7121 SPR_NOACCESS, SPR_NOACCESS, 7122 &spr_read_generic, &spr_write_generic, 7123 0x00000000); 7124 spr_register_hv(env, SPR_TFMR, "TFMR", 7125 SPR_NOACCESS, SPR_NOACCESS, 7126 SPR_NOACCESS, SPR_NOACCESS, 7127 &spr_read_generic, &spr_write_generic, 7128 0x00000000); 7129 spr_register_hv(env, SPR_LPIDR, "LPIDR", 7130 SPR_NOACCESS, SPR_NOACCESS, 7131 SPR_NOACCESS, SPR_NOACCESS, 7132 &spr_read_generic, &spr_write_lpidr, 7133 0x00000000); 7134 spr_register_hv(env, SPR_HFSCR, "HFSCR", 7135 SPR_NOACCESS, SPR_NOACCESS, 7136 SPR_NOACCESS, SPR_NOACCESS, 7137 &spr_read_generic, &spr_write_generic, 7138 0x00000000); 7139 spr_register_hv(env, SPR_MMCRC, "MMCRC", 7140 SPR_NOACCESS, SPR_NOACCESS, 7141 SPR_NOACCESS, SPR_NOACCESS, 7142 &spr_read_generic, &spr_write_generic, 7143 0x00000000); 7144 spr_register_hv(env, SPR_MMCRH, "MMCRH", 7145 SPR_NOACCESS, SPR_NOACCESS, 7146 SPR_NOACCESS, SPR_NOACCESS, 7147 &spr_read_generic, &spr_write_generic, 7148 0x00000000); 7149 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 7150 SPR_NOACCESS, SPR_NOACCESS, 7151 SPR_NOACCESS, SPR_NOACCESS, 7152 &spr_read_generic, &spr_write_generic, 7153 0x00000000); 7154 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 7155 SPR_NOACCESS, SPR_NOACCESS, 7156 SPR_NOACCESS, SPR_NOACCESS, 7157 &spr_read_generic, &spr_write_generic, 7158 0x00000000); 7159 spr_register_hv(env, SPR_HSRR0, "HSRR0", 7160 SPR_NOACCESS, SPR_NOACCESS, 7161 SPR_NOACCESS, SPR_NOACCESS, 7162 &spr_read_generic, &spr_write_generic, 7163 0x00000000); 7164 spr_register_hv(env, SPR_HSRR1, "HSRR1", 7165 SPR_NOACCESS, SPR_NOACCESS, 7166 SPR_NOACCESS, SPR_NOACCESS, 7167 &spr_read_generic, &spr_write_generic, 7168 0x00000000); 7169 spr_register_hv(env, SPR_HDAR, "HDAR", 7170 SPR_NOACCESS, SPR_NOACCESS, 7171 SPR_NOACCESS, SPR_NOACCESS, 7172 &spr_read_generic, &spr_write_generic, 7173 0x00000000); 7174 spr_register_hv(env, SPR_HDSISR, "HDSISR", 7175 SPR_NOACCESS, SPR_NOACCESS, 7176 SPR_NOACCESS, SPR_NOACCESS, 7177 &spr_read_generic, &spr_write_generic, 7178 0x00000000); 7179 spr_register_hv(env, SPR_HRMOR, "HRMOR", 7180 SPR_NOACCESS, SPR_NOACCESS, 7181 SPR_NOACCESS, SPR_NOACCESS, 7182 &spr_read_generic, &spr_write_generic, 7183 0x00000000); 7184 } 7185 7186 static void register_rmor_sprs(CPUPPCState *env) 7187 { 7188 spr_register_hv(env, SPR_RMOR, "RMOR", 7189 SPR_NOACCESS, SPR_NOACCESS, 7190 SPR_NOACCESS, SPR_NOACCESS, 7191 &spr_read_generic, &spr_write_generic, 7192 0x00000000); 7193 } 7194 7195 static void register_power8_ids_sprs(CPUPPCState *env) 7196 { 7197 /* Thread identification */ 7198 spr_register(env, SPR_TIR, "TIR", 7199 SPR_NOACCESS, SPR_NOACCESS, 7200 &spr_read_generic, SPR_NOACCESS, 7201 0x00000000); 7202 } 7203 7204 static void register_book3s_purr_sprs(CPUPPCState *env) 7205 { 7206 #if !defined(CONFIG_USER_ONLY) 7207 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 7208 spr_register_kvm_hv(env, SPR_PURR, "PURR", 7209 &spr_read_purr, SPR_NOACCESS, 7210 &spr_read_purr, SPR_NOACCESS, 7211 &spr_read_purr, &spr_write_purr, 7212 KVM_REG_PPC_PURR, 0x00000000); 7213 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 7214 &spr_read_purr, SPR_NOACCESS, 7215 &spr_read_purr, SPR_NOACCESS, 7216 &spr_read_purr, &spr_write_purr, 7217 KVM_REG_PPC_SPURR, 0x00000000); 7218 #endif 7219 } 7220 7221 static void register_power6_dbg_sprs(CPUPPCState *env) 7222 { 7223 #if !defined(CONFIG_USER_ONLY) 7224 spr_register(env, SPR_CFAR, "SPR_CFAR", 7225 SPR_NOACCESS, SPR_NOACCESS, 7226 &spr_read_cfar, &spr_write_cfar, 7227 0x00000000); 7228 #endif 7229 } 7230 7231 static void register_power5p_common_sprs(CPUPPCState *env) 7232 { 7233 spr_register_kvm(env, SPR_PPR, "PPR", 7234 &spr_read_generic, &spr_write_generic, 7235 &spr_read_generic, &spr_write_generic, 7236 KVM_REG_PPC_PPR, 0x00000000); 7237 } 7238 7239 static void register_power6_common_sprs(CPUPPCState *env) 7240 { 7241 #if !defined(CONFIG_USER_ONLY) 7242 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 7243 SPR_NOACCESS, SPR_NOACCESS, 7244 &spr_read_generic, &spr_write_generic, 7245 KVM_REG_PPC_DSCR, 0x00000000); 7246 #endif 7247 /* 7248 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 7249 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 7250 */ 7251 spr_register_hv(env, SPR_PCR, "PCR", 7252 SPR_NOACCESS, SPR_NOACCESS, 7253 SPR_NOACCESS, SPR_NOACCESS, 7254 &spr_read_generic, &spr_write_pcr, 7255 0x00000000); 7256 } 7257 7258 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 7259 { 7260 spr_register_kvm(env, SPR_TAR, "TAR", 7261 &spr_read_tar, &spr_write_tar, 7262 &spr_read_generic, &spr_write_generic, 7263 KVM_REG_PPC_TAR, 0x00000000); 7264 } 7265 7266 static void register_power8_tm_sprs(CPUPPCState *env) 7267 { 7268 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 7269 &spr_read_tm, &spr_write_tm, 7270 &spr_read_tm, &spr_write_tm, 7271 KVM_REG_PPC_TFHAR, 0x00000000); 7272 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 7273 &spr_read_tm, &spr_write_tm, 7274 &spr_read_tm, &spr_write_tm, 7275 KVM_REG_PPC_TFIAR, 0x00000000); 7276 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 7277 &spr_read_tm, &spr_write_tm, 7278 &spr_read_tm, &spr_write_tm, 7279 KVM_REG_PPC_TEXASR, 0x00000000); 7280 spr_register(env, SPR_TEXASRU, "TEXASRU", 7281 &spr_read_tm_upper32, &spr_write_tm_upper32, 7282 &spr_read_tm_upper32, &spr_write_tm_upper32, 7283 0x00000000); 7284 } 7285 7286 static void register_power8_ebb_sprs(CPUPPCState *env) 7287 { 7288 spr_register(env, SPR_BESCRS, "BESCRS", 7289 &spr_read_ebb, &spr_write_ebb, 7290 &spr_read_generic, &spr_write_generic, 7291 0x00000000); 7292 spr_register(env, SPR_BESCRSU, "BESCRSU", 7293 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7294 &spr_read_prev_upper32, &spr_write_prev_upper32, 7295 0x00000000); 7296 spr_register(env, SPR_BESCRR, "BESCRR", 7297 &spr_read_ebb, &spr_write_ebb, 7298 &spr_read_generic, &spr_write_generic, 7299 0x00000000); 7300 spr_register(env, SPR_BESCRRU, "BESCRRU", 7301 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 7302 &spr_read_prev_upper32, &spr_write_prev_upper32, 7303 0x00000000); 7304 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 7305 &spr_read_ebb, &spr_write_ebb, 7306 &spr_read_generic, &spr_write_generic, 7307 KVM_REG_PPC_EBBHR, 0x00000000); 7308 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 7309 &spr_read_ebb, &spr_write_ebb, 7310 &spr_read_generic, &spr_write_generic, 7311 KVM_REG_PPC_EBBRR, 0x00000000); 7312 spr_register_kvm(env, SPR_BESCR, "BESCR", 7313 &spr_read_ebb, &spr_write_ebb, 7314 &spr_read_generic, &spr_write_generic, 7315 KVM_REG_PPC_BESCR, 0x00000000); 7316 } 7317 7318 /* Virtual Time Base */ 7319 static void register_vtb_sprs(CPUPPCState *env) 7320 { 7321 spr_register_kvm_hv(env, SPR_VTB, "VTB", 7322 SPR_NOACCESS, SPR_NOACCESS, 7323 &spr_read_vtb, SPR_NOACCESS, 7324 &spr_read_vtb, &spr_write_vtb, 7325 KVM_REG_PPC_VTB, 0x00000000); 7326 } 7327 7328 static void register_power8_fscr_sprs(CPUPPCState *env) 7329 { 7330 #if defined(CONFIG_USER_ONLY) 7331 target_ulong initval = 1ULL << FSCR_TAR; 7332 #else 7333 target_ulong initval = 0; 7334 #endif 7335 spr_register_kvm(env, SPR_FSCR, "FSCR", 7336 SPR_NOACCESS, SPR_NOACCESS, 7337 &spr_read_generic, &spr_write_generic, 7338 KVM_REG_PPC_FSCR, initval); 7339 } 7340 7341 static void register_power8_pspb_sprs(CPUPPCState *env) 7342 { 7343 spr_register_kvm(env, SPR_PSPB, "PSPB", 7344 SPR_NOACCESS, SPR_NOACCESS, 7345 &spr_read_generic, &spr_write_generic32, 7346 KVM_REG_PPC_PSPB, 0); 7347 } 7348 7349 static void register_power8_dpdes_sprs(CPUPPCState *env) 7350 { 7351 #if !defined(CONFIG_USER_ONLY) 7352 /* Directed Privileged Door-bell Exception State, used for IPI */ 7353 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 7354 SPR_NOACCESS, SPR_NOACCESS, 7355 &spr_read_dpdes, SPR_NOACCESS, 7356 &spr_read_dpdes, &spr_write_dpdes, 7357 KVM_REG_PPC_DPDES, 0x00000000); 7358 #endif 7359 } 7360 7361 static void register_power8_ic_sprs(CPUPPCState *env) 7362 { 7363 #if !defined(CONFIG_USER_ONLY) 7364 spr_register_hv(env, SPR_IC, "IC", 7365 SPR_NOACCESS, SPR_NOACCESS, 7366 &spr_read_generic, SPR_NOACCESS, 7367 &spr_read_generic, &spr_write_generic, 7368 0); 7369 #endif 7370 } 7371 7372 static void register_power8_book4_sprs(CPUPPCState *env) 7373 { 7374 /* Add a number of P8 book4 registers */ 7375 #if !defined(CONFIG_USER_ONLY) 7376 spr_register_kvm(env, SPR_ACOP, "ACOP", 7377 SPR_NOACCESS, SPR_NOACCESS, 7378 &spr_read_generic, &spr_write_generic, 7379 KVM_REG_PPC_ACOP, 0); 7380 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7381 SPR_NOACCESS, SPR_NOACCESS, 7382 &spr_read_generic, &spr_write_pidr, 7383 KVM_REG_PPC_PID, 0); 7384 spr_register_kvm(env, SPR_WORT, "WORT", 7385 SPR_NOACCESS, SPR_NOACCESS, 7386 &spr_read_generic, &spr_write_generic, 7387 KVM_REG_PPC_WORT, 0); 7388 #endif 7389 } 7390 7391 static void register_power7_book4_sprs(CPUPPCState *env) 7392 { 7393 /* Add a number of P7 book4 registers */ 7394 #if !defined(CONFIG_USER_ONLY) 7395 spr_register_kvm(env, SPR_ACOP, "ACOP", 7396 SPR_NOACCESS, SPR_NOACCESS, 7397 &spr_read_generic, &spr_write_generic, 7398 KVM_REG_PPC_ACOP, 0); 7399 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 7400 SPR_NOACCESS, SPR_NOACCESS, 7401 &spr_read_generic, &spr_write_generic, 7402 KVM_REG_PPC_PID, 0); 7403 #endif 7404 } 7405 7406 static void register_power8_rpr_sprs(CPUPPCState *env) 7407 { 7408 #if !defined(CONFIG_USER_ONLY) 7409 spr_register_hv(env, SPR_RPR, "RPR", 7410 SPR_NOACCESS, SPR_NOACCESS, 7411 SPR_NOACCESS, SPR_NOACCESS, 7412 &spr_read_generic, &spr_write_generic, 7413 0x00000103070F1F3F); 7414 #endif 7415 } 7416 7417 static void register_power9_mmu_sprs(CPUPPCState *env) 7418 { 7419 #if !defined(CONFIG_USER_ONLY) 7420 /* Partition Table Control */ 7421 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 7422 SPR_NOACCESS, SPR_NOACCESS, 7423 SPR_NOACCESS, SPR_NOACCESS, 7424 &spr_read_generic, &spr_write_ptcr, 7425 KVM_REG_PPC_PTCR, 0x00000000); 7426 /* Address Segment Descriptor Register */ 7427 spr_register_hv(env, SPR_ASDR, "ASDR", 7428 SPR_NOACCESS, SPR_NOACCESS, 7429 SPR_NOACCESS, SPR_NOACCESS, 7430 &spr_read_generic, &spr_write_generic, 7431 0x0000000000000000); 7432 #endif 7433 } 7434 7435 static void init_proc_book3s_common(CPUPPCState *env) 7436 { 7437 register_ne_601_sprs(env); 7438 register_tbl(env); 7439 register_usprg3_sprs(env); 7440 register_book3s_altivec_sprs(env); 7441 register_book3s_pmu_sup_sprs(env); 7442 register_book3s_pmu_user_sprs(env); 7443 register_book3s_ctrl_sprs(env); 7444 /* 7445 * Can't find information on what this should be on reset. This 7446 * value is the one used by 74xx processors. 7447 */ 7448 vscr_init(env, 0x00010000); 7449 } 7450 7451 static void init_proc_970(CPUPPCState *env) 7452 { 7453 /* Common Registers */ 7454 init_proc_book3s_common(env); 7455 register_sdr1_sprs(env); 7456 register_book3s_dbg_sprs(env); 7457 7458 /* 970 Specific Registers */ 7459 register_970_hid_sprs(env); 7460 register_970_hior_sprs(env); 7461 register_low_BATs(env); 7462 register_970_pmu_sup_sprs(env); 7463 register_970_pmu_user_sprs(env); 7464 register_970_lpar_sprs(env); 7465 register_970_dbg_sprs(env); 7466 7467 /* env variables */ 7468 env->dcache_line_size = 128; 7469 env->icache_line_size = 128; 7470 7471 /* Allocate hardware IRQ controller */ 7472 init_excp_970(env); 7473 ppc970_irq_init(env_archcpu(env)); 7474 } 7475 7476 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 7477 { 7478 DeviceClass *dc = DEVICE_CLASS(oc); 7479 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7480 7481 dc->desc = "PowerPC 970"; 7482 pcc->init_proc = init_proc_970; 7483 pcc->check_pow = check_pow_970; 7484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7485 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7486 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7487 PPC_FLOAT_STFIWX | 7488 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7489 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7490 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7491 PPC_64B | PPC_ALTIVEC | 7492 PPC_SEGMENT_64B | PPC_SLBI; 7493 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7494 pcc->msr_mask = (1ull << MSR_SF) | 7495 (1ull << MSR_VR) | 7496 (1ull << MSR_POW) | 7497 (1ull << MSR_EE) | 7498 (1ull << MSR_PR) | 7499 (1ull << MSR_FP) | 7500 (1ull << MSR_ME) | 7501 (1ull << MSR_FE0) | 7502 (1ull << MSR_SE) | 7503 (1ull << MSR_DE) | 7504 (1ull << MSR_FE1) | 7505 (1ull << MSR_IR) | 7506 (1ull << MSR_DR) | 7507 (1ull << MSR_PMM) | 7508 (1ull << MSR_RI); 7509 pcc->mmu_model = POWERPC_MMU_64B; 7510 #if defined(CONFIG_SOFTMMU) 7511 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7512 pcc->hash64_opts = &ppc_hash64_opts_basic; 7513 #endif 7514 pcc->excp_model = POWERPC_EXCP_970; 7515 pcc->bus_model = PPC_FLAGS_INPUT_970; 7516 pcc->bfd_mach = bfd_mach_ppc64; 7517 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7518 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7519 POWERPC_FLAG_BUS_CLK; 7520 pcc->l1_dcache_size = 0x8000; 7521 pcc->l1_icache_size = 0x10000; 7522 } 7523 7524 static void init_proc_power5plus(CPUPPCState *env) 7525 { 7526 /* Common Registers */ 7527 init_proc_book3s_common(env); 7528 register_sdr1_sprs(env); 7529 register_book3s_dbg_sprs(env); 7530 7531 /* POWER5+ Specific Registers */ 7532 register_970_hid_sprs(env); 7533 register_970_hior_sprs(env); 7534 register_low_BATs(env); 7535 register_970_pmu_sup_sprs(env); 7536 register_970_pmu_user_sprs(env); 7537 register_power5p_common_sprs(env); 7538 register_power5p_lpar_sprs(env); 7539 register_power5p_ear_sprs(env); 7540 register_power5p_tb_sprs(env); 7541 7542 /* env variables */ 7543 env->dcache_line_size = 128; 7544 env->icache_line_size = 128; 7545 7546 /* Allocate hardware IRQ controller */ 7547 init_excp_970(env); 7548 ppc970_irq_init(env_archcpu(env)); 7549 } 7550 7551 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 7552 { 7553 DeviceClass *dc = DEVICE_CLASS(oc); 7554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7555 7556 dc->fw_name = "PowerPC,POWER5"; 7557 dc->desc = "POWER5+"; 7558 pcc->init_proc = init_proc_power5plus; 7559 pcc->check_pow = check_pow_970; 7560 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7561 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7562 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7563 PPC_FLOAT_STFIWX | 7564 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7565 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7567 PPC_64B | 7568 PPC_SEGMENT_64B | PPC_SLBI; 7569 pcc->insns_flags2 = PPC2_FP_CVT_S64; 7570 pcc->msr_mask = (1ull << MSR_SF) | 7571 (1ull << MSR_VR) | 7572 (1ull << MSR_POW) | 7573 (1ull << MSR_EE) | 7574 (1ull << MSR_PR) | 7575 (1ull << MSR_FP) | 7576 (1ull << MSR_ME) | 7577 (1ull << MSR_FE0) | 7578 (1ull << MSR_SE) | 7579 (1ull << MSR_DE) | 7580 (1ull << MSR_FE1) | 7581 (1ull << MSR_IR) | 7582 (1ull << MSR_DR) | 7583 (1ull << MSR_PMM) | 7584 (1ull << MSR_RI); 7585 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 7586 LPCR_RMI | LPCR_HDICE; 7587 pcc->mmu_model = POWERPC_MMU_2_03; 7588 #if defined(CONFIG_SOFTMMU) 7589 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7590 pcc->hash64_opts = &ppc_hash64_opts_basic; 7591 pcc->lrg_decr_bits = 32; 7592 #endif 7593 pcc->excp_model = POWERPC_EXCP_970; 7594 pcc->bus_model = PPC_FLAGS_INPUT_970; 7595 pcc->bfd_mach = bfd_mach_ppc64; 7596 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7597 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7598 POWERPC_FLAG_BUS_CLK; 7599 pcc->l1_dcache_size = 0x8000; 7600 pcc->l1_icache_size = 0x10000; 7601 } 7602 7603 static void init_proc_POWER7(CPUPPCState *env) 7604 { 7605 /* Common Registers */ 7606 init_proc_book3s_common(env); 7607 register_sdr1_sprs(env); 7608 register_book3s_dbg_sprs(env); 7609 7610 /* POWER7 Specific Registers */ 7611 register_book3s_ids_sprs(env); 7612 register_rmor_sprs(env); 7613 register_amr_sprs(env); 7614 register_book3s_purr_sprs(env); 7615 register_power5p_common_sprs(env); 7616 register_power5p_lpar_sprs(env); 7617 register_power5p_ear_sprs(env); 7618 register_power5p_tb_sprs(env); 7619 register_power6_common_sprs(env); 7620 register_power6_dbg_sprs(env); 7621 register_power7_book4_sprs(env); 7622 7623 /* env variables */ 7624 env->dcache_line_size = 128; 7625 env->icache_line_size = 128; 7626 7627 /* Allocate hardware IRQ controller */ 7628 init_excp_POWER7(env); 7629 ppcPOWER7_irq_init(env_archcpu(env)); 7630 } 7631 7632 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 7633 { 7634 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 7635 return true; 7636 } 7637 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 7638 return true; 7639 } 7640 return false; 7641 } 7642 7643 static bool cpu_has_work_POWER7(CPUState *cs) 7644 { 7645 PowerPCCPU *cpu = POWERPC_CPU(cs); 7646 CPUPPCState *env = &cpu->env; 7647 7648 if (cs->halted) { 7649 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7650 return false; 7651 } 7652 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7653 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 7654 return true; 7655 } 7656 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7657 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 7658 return true; 7659 } 7660 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7661 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7662 return true; 7663 } 7664 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7665 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7666 return true; 7667 } 7668 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7669 return true; 7670 } 7671 return false; 7672 } else { 7673 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7674 } 7675 } 7676 7677 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 7678 { 7679 DeviceClass *dc = DEVICE_CLASS(oc); 7680 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7681 CPUClass *cc = CPU_CLASS(oc); 7682 7683 dc->fw_name = "PowerPC,POWER7"; 7684 dc->desc = "POWER7"; 7685 pcc->pvr_match = ppc_pvr_match_power7; 7686 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 7687 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7688 pcc->init_proc = init_proc_POWER7; 7689 pcc->check_pow = check_pow_nocheck; 7690 cc->has_work = cpu_has_work_POWER7; 7691 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7692 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7693 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7694 PPC_FLOAT_FRSQRTES | 7695 PPC_FLOAT_STFIWX | 7696 PPC_FLOAT_EXT | 7697 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7698 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7699 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7700 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7701 PPC_SEGMENT_64B | PPC_SLBI | 7702 PPC_POPCNTB | PPC_POPCNTWD | 7703 PPC_CILDST; 7704 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 7705 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7706 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7707 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 7708 PPC2_PM_ISA206; 7709 pcc->msr_mask = (1ull << MSR_SF) | 7710 (1ull << MSR_VR) | 7711 (1ull << MSR_VSX) | 7712 (1ull << MSR_EE) | 7713 (1ull << MSR_PR) | 7714 (1ull << MSR_FP) | 7715 (1ull << MSR_ME) | 7716 (1ull << MSR_FE0) | 7717 (1ull << MSR_SE) | 7718 (1ull << MSR_DE) | 7719 (1ull << MSR_FE1) | 7720 (1ull << MSR_IR) | 7721 (1ull << MSR_DR) | 7722 (1ull << MSR_PMM) | 7723 (1ull << MSR_RI) | 7724 (1ull << MSR_LE); 7725 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 7726 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7727 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 7728 LPCR_MER | LPCR_TC | 7729 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 7730 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 7731 pcc->mmu_model = POWERPC_MMU_2_06; 7732 #if defined(CONFIG_SOFTMMU) 7733 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7734 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7735 pcc->lrg_decr_bits = 32; 7736 #endif 7737 pcc->excp_model = POWERPC_EXCP_POWER7; 7738 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7739 pcc->bfd_mach = bfd_mach_ppc64; 7740 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7741 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7742 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7743 POWERPC_FLAG_VSX; 7744 pcc->l1_dcache_size = 0x8000; 7745 pcc->l1_icache_size = 0x8000; 7746 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 7747 } 7748 7749 static void init_proc_POWER8(CPUPPCState *env) 7750 { 7751 /* Common Registers */ 7752 init_proc_book3s_common(env); 7753 register_sdr1_sprs(env); 7754 register_book3s_207_dbg_sprs(env); 7755 7756 /* POWER8 Specific Registers */ 7757 register_book3s_ids_sprs(env); 7758 register_rmor_sprs(env); 7759 register_amr_sprs(env); 7760 register_iamr_sprs(env); 7761 register_book3s_purr_sprs(env); 7762 register_power5p_common_sprs(env); 7763 register_power5p_lpar_sprs(env); 7764 register_power5p_ear_sprs(env); 7765 register_power5p_tb_sprs(env); 7766 register_power6_common_sprs(env); 7767 register_power6_dbg_sprs(env); 7768 register_power8_tce_address_control_sprs(env); 7769 register_power8_ids_sprs(env); 7770 register_power8_ebb_sprs(env); 7771 register_power8_fscr_sprs(env); 7772 register_power8_pmu_sup_sprs(env); 7773 register_power8_pmu_user_sprs(env); 7774 register_power8_tm_sprs(env); 7775 register_power8_pspb_sprs(env); 7776 register_power8_dpdes_sprs(env); 7777 register_vtb_sprs(env); 7778 register_power8_ic_sprs(env); 7779 register_power8_book4_sprs(env); 7780 register_power8_rpr_sprs(env); 7781 7782 /* env variables */ 7783 env->dcache_line_size = 128; 7784 env->icache_line_size = 128; 7785 7786 /* Allocate hardware IRQ controller */ 7787 init_excp_POWER8(env); 7788 ppcPOWER7_irq_init(env_archcpu(env)); 7789 } 7790 7791 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7792 { 7793 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7794 return true; 7795 } 7796 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7797 return true; 7798 } 7799 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7800 return true; 7801 } 7802 return false; 7803 } 7804 7805 static bool cpu_has_work_POWER8(CPUState *cs) 7806 { 7807 PowerPCCPU *cpu = POWERPC_CPU(cs); 7808 CPUPPCState *env = &cpu->env; 7809 7810 if (cs->halted) { 7811 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7812 return false; 7813 } 7814 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7815 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7816 return true; 7817 } 7818 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7819 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7820 return true; 7821 } 7822 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7823 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7824 return true; 7825 } 7826 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7827 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7828 return true; 7829 } 7830 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7831 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7832 return true; 7833 } 7834 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7835 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7836 return true; 7837 } 7838 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7839 return true; 7840 } 7841 return false; 7842 } else { 7843 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7844 } 7845 } 7846 7847 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7848 { 7849 DeviceClass *dc = DEVICE_CLASS(oc); 7850 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7851 CPUClass *cc = CPU_CLASS(oc); 7852 7853 dc->fw_name = "PowerPC,POWER8"; 7854 dc->desc = "POWER8"; 7855 pcc->pvr_match = ppc_pvr_match_power8; 7856 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7857 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7858 pcc->init_proc = init_proc_POWER8; 7859 pcc->check_pow = check_pow_nocheck; 7860 cc->has_work = cpu_has_work_POWER8; 7861 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7862 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7863 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7864 PPC_FLOAT_FRSQRTES | 7865 PPC_FLOAT_STFIWX | 7866 PPC_FLOAT_EXT | 7867 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7868 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7869 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7870 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7871 PPC_SEGMENT_64B | PPC_SLBI | 7872 PPC_POPCNTB | PPC_POPCNTWD | 7873 PPC_CILDST; 7874 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7875 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7876 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7877 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7878 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7879 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7880 PPC2_TM | PPC2_PM_ISA206; 7881 pcc->msr_mask = (1ull << MSR_SF) | 7882 (1ull << MSR_HV) | 7883 (1ull << MSR_TM) | 7884 (1ull << MSR_VR) | 7885 (1ull << MSR_VSX) | 7886 (1ull << MSR_EE) | 7887 (1ull << MSR_PR) | 7888 (1ull << MSR_FP) | 7889 (1ull << MSR_ME) | 7890 (1ull << MSR_FE0) | 7891 (1ull << MSR_SE) | 7892 (1ull << MSR_DE) | 7893 (1ull << MSR_FE1) | 7894 (1ull << MSR_IR) | 7895 (1ull << MSR_DR) | 7896 (1ull << MSR_PMM) | 7897 (1ull << MSR_RI) | 7898 (1ull << MSR_TS0) | 7899 (1ull << MSR_TS1) | 7900 (1ull << MSR_LE); 7901 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7902 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7903 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7904 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7905 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7906 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7907 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7908 pcc->mmu_model = POWERPC_MMU_2_07; 7909 #if defined(CONFIG_SOFTMMU) 7910 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 7911 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7912 pcc->lrg_decr_bits = 32; 7913 pcc->n_host_threads = 8; 7914 #endif 7915 pcc->excp_model = POWERPC_EXCP_POWER8; 7916 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7917 pcc->bfd_mach = bfd_mach_ppc64; 7918 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7919 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7920 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7921 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7922 pcc->l1_dcache_size = 0x8000; 7923 pcc->l1_icache_size = 0x8000; 7924 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 7925 } 7926 7927 #ifdef CONFIG_SOFTMMU 7928 /* 7929 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7930 * Encoded as array of int_32s in the form: 7931 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7932 * x -> AP encoding 7933 * y -> radix mode supported page size (encoded as a shift) 7934 */ 7935 static struct ppc_radix_page_info POWER9_radix_page_info = { 7936 .count = 4, 7937 .entries = { 7938 0x0000000c, /* 4K - enc: 0x0 */ 7939 0xa0000010, /* 64K - enc: 0x5 */ 7940 0x20000015, /* 2M - enc: 0x1 */ 7941 0x4000001e /* 1G - enc: 0x2 */ 7942 } 7943 }; 7944 #endif /* CONFIG_SOFTMMU */ 7945 7946 static void init_proc_POWER9(CPUPPCState *env) 7947 { 7948 /* Common Registers */ 7949 init_proc_book3s_common(env); 7950 register_book3s_207_dbg_sprs(env); 7951 7952 /* POWER8 Specific Registers */ 7953 register_book3s_ids_sprs(env); 7954 register_amr_sprs(env); 7955 register_iamr_sprs(env); 7956 register_book3s_purr_sprs(env); 7957 register_power5p_common_sprs(env); 7958 register_power5p_lpar_sprs(env); 7959 register_power5p_ear_sprs(env); 7960 register_power5p_tb_sprs(env); 7961 register_power6_common_sprs(env); 7962 register_power6_dbg_sprs(env); 7963 register_power8_tce_address_control_sprs(env); 7964 register_power8_ids_sprs(env); 7965 register_power8_ebb_sprs(env); 7966 register_power8_fscr_sprs(env); 7967 register_power8_pmu_sup_sprs(env); 7968 register_power8_pmu_user_sprs(env); 7969 register_power8_tm_sprs(env); 7970 register_power8_pspb_sprs(env); 7971 register_power8_dpdes_sprs(env); 7972 register_vtb_sprs(env); 7973 register_power8_ic_sprs(env); 7974 register_power8_book4_sprs(env); 7975 register_power8_rpr_sprs(env); 7976 register_power9_mmu_sprs(env); 7977 7978 /* POWER9 Specific registers */ 7979 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7980 spr_read_generic, spr_write_generic, 7981 KVM_REG_PPC_TIDR, 0); 7982 7983 /* FIXME: Filter fields properly based on privilege level */ 7984 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7985 spr_read_generic, spr_write_generic, 7986 KVM_REG_PPC_PSSCR, 0); 7987 7988 /* env variables */ 7989 env->dcache_line_size = 128; 7990 env->icache_line_size = 128; 7991 7992 /* Allocate hardware IRQ controller */ 7993 init_excp_POWER9(env); 7994 ppcPOWER9_irq_init(env_archcpu(env)); 7995 } 7996 7997 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7998 { 7999 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 8000 return true; 8001 } 8002 return false; 8003 } 8004 8005 static bool cpu_has_work_POWER9(CPUState *cs) 8006 { 8007 PowerPCCPU *cpu = POWERPC_CPU(cs); 8008 CPUPPCState *env = &cpu->env; 8009 8010 if (cs->halted) { 8011 uint64_t psscr = env->spr[SPR_PSSCR]; 8012 8013 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8014 return false; 8015 } 8016 8017 /* If EC is clear, just return true on any pending interrupt */ 8018 if (!(psscr & PSSCR_EC)) { 8019 return true; 8020 } 8021 /* External Exception */ 8022 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8023 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8024 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8025 if (heic == 0 || !msr_hv || msr_pr) { 8026 return true; 8027 } 8028 } 8029 /* Decrementer Exception */ 8030 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8031 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8032 return true; 8033 } 8034 /* Machine Check or Hypervisor Maintenance Exception */ 8035 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8036 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8037 return true; 8038 } 8039 /* Privileged Doorbell Exception */ 8040 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8041 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8042 return true; 8043 } 8044 /* Hypervisor Doorbell Exception */ 8045 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8046 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8047 return true; 8048 } 8049 /* Hypervisor virtualization exception */ 8050 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8051 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8052 return true; 8053 } 8054 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8055 return true; 8056 } 8057 return false; 8058 } else { 8059 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8060 } 8061 } 8062 8063 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 8064 { 8065 DeviceClass *dc = DEVICE_CLASS(oc); 8066 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8067 CPUClass *cc = CPU_CLASS(oc); 8068 8069 dc->fw_name = "PowerPC,POWER9"; 8070 dc->desc = "POWER9"; 8071 pcc->pvr_match = ppc_pvr_match_power9; 8072 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 8073 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 8074 PCR_COMPAT_2_05; 8075 pcc->init_proc = init_proc_POWER9; 8076 pcc->check_pow = check_pow_nocheck; 8077 cc->has_work = cpu_has_work_POWER9; 8078 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8079 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8080 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8081 PPC_FLOAT_FRSQRTES | 8082 PPC_FLOAT_STFIWX | 8083 PPC_FLOAT_EXT | 8084 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8085 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8086 PPC_MEM_TLBSYNC | 8087 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8088 PPC_SEGMENT_64B | PPC_SLBI | 8089 PPC_POPCNTB | PPC_POPCNTWD | 8090 PPC_CILDST; 8091 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8092 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8093 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8094 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8095 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8096 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8097 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 8098 pcc->msr_mask = (1ull << MSR_SF) | 8099 (1ull << MSR_HV) | 8100 (1ull << MSR_TM) | 8101 (1ull << MSR_VR) | 8102 (1ull << MSR_VSX) | 8103 (1ull << MSR_EE) | 8104 (1ull << MSR_PR) | 8105 (1ull << MSR_FP) | 8106 (1ull << MSR_ME) | 8107 (1ull << MSR_FE0) | 8108 (1ull << MSR_SE) | 8109 (1ull << MSR_DE) | 8110 (1ull << MSR_FE1) | 8111 (1ull << MSR_IR) | 8112 (1ull << MSR_DR) | 8113 (1ull << MSR_PMM) | 8114 (1ull << MSR_RI) | 8115 (1ull << MSR_LE); 8116 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8117 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8118 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8119 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8120 LPCR_DEE | LPCR_OEE)) 8121 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8122 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8123 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8124 pcc->mmu_model = POWERPC_MMU_3_00; 8125 #if defined(CONFIG_SOFTMMU) 8126 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8127 /* segment page size remain the same */ 8128 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8129 pcc->radix_page_info = &POWER9_radix_page_info; 8130 pcc->lrg_decr_bits = 56; 8131 pcc->n_host_threads = 4; 8132 #endif 8133 pcc->excp_model = POWERPC_EXCP_POWER9; 8134 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8135 pcc->bfd_mach = bfd_mach_ppc64; 8136 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8137 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8138 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8139 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8140 pcc->l1_dcache_size = 0x8000; 8141 pcc->l1_icache_size = 0x8000; 8142 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8143 } 8144 8145 #ifdef CONFIG_SOFTMMU 8146 /* 8147 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 8148 * Encoded as array of int_32s in the form: 8149 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 8150 * x -> AP encoding 8151 * y -> radix mode supported page size (encoded as a shift) 8152 */ 8153 static struct ppc_radix_page_info POWER10_radix_page_info = { 8154 .count = 4, 8155 .entries = { 8156 0x0000000c, /* 4K - enc: 0x0 */ 8157 0xa0000010, /* 64K - enc: 0x5 */ 8158 0x20000015, /* 2M - enc: 0x1 */ 8159 0x4000001e /* 1G - enc: 0x2 */ 8160 } 8161 }; 8162 #endif /* CONFIG_SOFTMMU */ 8163 8164 static void init_proc_POWER10(CPUPPCState *env) 8165 { 8166 /* Common Registers */ 8167 init_proc_book3s_common(env); 8168 register_book3s_207_dbg_sprs(env); 8169 8170 /* POWER8 Specific Registers */ 8171 register_book3s_ids_sprs(env); 8172 register_amr_sprs(env); 8173 register_iamr_sprs(env); 8174 register_book3s_purr_sprs(env); 8175 register_power5p_common_sprs(env); 8176 register_power5p_lpar_sprs(env); 8177 register_power5p_ear_sprs(env); 8178 register_power6_common_sprs(env); 8179 register_power6_dbg_sprs(env); 8180 register_power8_tce_address_control_sprs(env); 8181 register_power8_ids_sprs(env); 8182 register_power8_ebb_sprs(env); 8183 register_power8_fscr_sprs(env); 8184 register_power8_pmu_sup_sprs(env); 8185 register_power8_pmu_user_sprs(env); 8186 register_power8_tm_sprs(env); 8187 register_power8_pspb_sprs(env); 8188 register_vtb_sprs(env); 8189 register_power8_ic_sprs(env); 8190 register_power8_book4_sprs(env); 8191 register_power8_rpr_sprs(env); 8192 register_power9_mmu_sprs(env); 8193 8194 /* FIXME: Filter fields properly based on privilege level */ 8195 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 8196 spr_read_generic, spr_write_generic, 8197 KVM_REG_PPC_PSSCR, 0); 8198 8199 /* env variables */ 8200 env->dcache_line_size = 128; 8201 env->icache_line_size = 128; 8202 8203 /* Allocate hardware IRQ controller */ 8204 init_excp_POWER10(env); 8205 ppcPOWER9_irq_init(env_archcpu(env)); 8206 } 8207 8208 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 8209 { 8210 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 8211 return true; 8212 } 8213 return false; 8214 } 8215 8216 static bool cpu_has_work_POWER10(CPUState *cs) 8217 { 8218 PowerPCCPU *cpu = POWERPC_CPU(cs); 8219 CPUPPCState *env = &cpu->env; 8220 8221 if (cs->halted) { 8222 uint64_t psscr = env->spr[SPR_PSSCR]; 8223 8224 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8225 return false; 8226 } 8227 8228 /* If EC is clear, just return true on any pending interrupt */ 8229 if (!(psscr & PSSCR_EC)) { 8230 return true; 8231 } 8232 /* External Exception */ 8233 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8234 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8235 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 8236 if (heic == 0 || !msr_hv || msr_pr) { 8237 return true; 8238 } 8239 } 8240 /* Decrementer Exception */ 8241 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8242 (env->spr[SPR_LPCR] & LPCR_DEE)) { 8243 return true; 8244 } 8245 /* Machine Check or Hypervisor Maintenance Exception */ 8246 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 8247 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 8248 return true; 8249 } 8250 /* Privileged Doorbell Exception */ 8251 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8252 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 8253 return true; 8254 } 8255 /* Hypervisor Doorbell Exception */ 8256 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8257 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 8258 return true; 8259 } 8260 /* Hypervisor virtualization exception */ 8261 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 8262 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 8263 return true; 8264 } 8265 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8266 return true; 8267 } 8268 return false; 8269 } else { 8270 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8271 } 8272 } 8273 8274 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 8275 { 8276 DeviceClass *dc = DEVICE_CLASS(oc); 8277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8278 CPUClass *cc = CPU_CLASS(oc); 8279 8280 dc->fw_name = "PowerPC,POWER10"; 8281 dc->desc = "POWER10"; 8282 pcc->pvr_match = ppc_pvr_match_power10; 8283 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 8284 PCR_COMPAT_3_00; 8285 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 8286 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8287 pcc->init_proc = init_proc_POWER10; 8288 pcc->check_pow = check_pow_nocheck; 8289 cc->has_work = cpu_has_work_POWER10; 8290 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8291 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8292 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8293 PPC_FLOAT_FRSQRTES | 8294 PPC_FLOAT_STFIWX | 8295 PPC_FLOAT_EXT | 8296 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8297 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8298 PPC_MEM_TLBSYNC | 8299 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8300 PPC_SEGMENT_64B | PPC_SLBI | 8301 PPC_POPCNTB | PPC_POPCNTWD | 8302 PPC_CILDST; 8303 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8304 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8305 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8306 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8307 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8308 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8309 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 8310 pcc->msr_mask = (1ull << MSR_SF) | 8311 (1ull << MSR_HV) | 8312 (1ull << MSR_TM) | 8313 (1ull << MSR_VR) | 8314 (1ull << MSR_VSX) | 8315 (1ull << MSR_EE) | 8316 (1ull << MSR_PR) | 8317 (1ull << MSR_FP) | 8318 (1ull << MSR_ME) | 8319 (1ull << MSR_FE0) | 8320 (1ull << MSR_SE) | 8321 (1ull << MSR_DE) | 8322 (1ull << MSR_FE1) | 8323 (1ull << MSR_IR) | 8324 (1ull << MSR_DR) | 8325 (1ull << MSR_PMM) | 8326 (1ull << MSR_RI) | 8327 (1ull << MSR_LE); 8328 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 8329 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 8330 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 8331 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 8332 LPCR_DEE | LPCR_OEE)) 8333 | LPCR_MER | LPCR_GTSE | LPCR_TC | 8334 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 8335 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 8336 pcc->mmu_model = POWERPC_MMU_3_00; 8337 #if defined(CONFIG_SOFTMMU) 8338 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 8339 /* segment page size remain the same */ 8340 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8341 pcc->radix_page_info = &POWER10_radix_page_info; 8342 pcc->lrg_decr_bits = 56; 8343 #endif 8344 pcc->excp_model = POWERPC_EXCP_POWER10; 8345 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 8346 pcc->bfd_mach = bfd_mach_ppc64; 8347 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8348 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8349 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8350 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 8351 pcc->l1_dcache_size = 0x8000; 8352 pcc->l1_icache_size = 0x8000; 8353 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8354 } 8355 8356 #if !defined(CONFIG_USER_ONLY) 8357 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 8358 { 8359 CPUPPCState *env = &cpu->env; 8360 8361 cpu->vhyp = vhyp; 8362 8363 /* 8364 * With a virtual hypervisor mode we never allow the CPU to go 8365 * hypervisor mode itself 8366 */ 8367 env->msr_mask &= ~MSR_HVB; 8368 } 8369 8370 #endif /* !defined(CONFIG_USER_ONLY) */ 8371 8372 #endif /* defined(TARGET_PPC64) */ 8373 8374 /*****************************************************************************/ 8375 /* Generic CPU instantiation routine */ 8376 static void init_ppc_proc(PowerPCCPU *cpu) 8377 { 8378 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8379 CPUPPCState *env = &cpu->env; 8380 #if !defined(CONFIG_USER_ONLY) 8381 int i; 8382 8383 env->irq_inputs = NULL; 8384 /* Set all exception vectors to an invalid address */ 8385 for (i = 0; i < POWERPC_EXCP_NB; i++) { 8386 env->excp_vectors[i] = (target_ulong)(-1ULL); 8387 } 8388 env->ivor_mask = 0x00000000; 8389 env->ivpr_mask = 0x00000000; 8390 /* Default MMU definitions */ 8391 env->nb_BATs = 0; 8392 env->nb_tlb = 0; 8393 env->nb_ways = 0; 8394 env->tlb_type = TLB_NONE; 8395 #endif 8396 /* Register SPR common to all PowerPC implementations */ 8397 register_generic_sprs(env); 8398 spr_register(env, SPR_PVR, "PVR", 8399 /* Linux permits userspace to read PVR */ 8400 #if defined(CONFIG_LINUX_USER) 8401 &spr_read_generic, 8402 #else 8403 SPR_NOACCESS, 8404 #endif 8405 SPR_NOACCESS, 8406 &spr_read_generic, SPR_NOACCESS, 8407 pcc->pvr); 8408 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 8409 if (pcc->svr != POWERPC_SVR_NONE) { 8410 if (pcc->svr & POWERPC_SVR_E500) { 8411 spr_register(env, SPR_E500_SVR, "SVR", 8412 SPR_NOACCESS, SPR_NOACCESS, 8413 &spr_read_generic, SPR_NOACCESS, 8414 pcc->svr & ~POWERPC_SVR_E500); 8415 } else { 8416 spr_register(env, SPR_SVR, "SVR", 8417 SPR_NOACCESS, SPR_NOACCESS, 8418 &spr_read_generic, SPR_NOACCESS, 8419 pcc->svr); 8420 } 8421 } 8422 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 8423 (*pcc->init_proc)(env); 8424 8425 #if !defined(CONFIG_USER_ONLY) 8426 ppc_gdb_gen_spr_xml(cpu); 8427 #endif 8428 8429 /* MSR bits & flags consistency checks */ 8430 if (env->msr_mask & (1 << 25)) { 8431 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8432 case POWERPC_FLAG_SPE: 8433 case POWERPC_FLAG_VRE: 8434 break; 8435 default: 8436 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8437 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 8438 exit(1); 8439 } 8440 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 8441 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8442 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 8443 exit(1); 8444 } 8445 if (env->msr_mask & (1 << 17)) { 8446 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8447 case POWERPC_FLAG_TGPR: 8448 case POWERPC_FLAG_CE: 8449 break; 8450 default: 8451 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8452 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 8453 exit(1); 8454 } 8455 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 8456 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8457 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 8458 exit(1); 8459 } 8460 if (env->msr_mask & (1 << 10)) { 8461 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8462 POWERPC_FLAG_UBLE)) { 8463 case POWERPC_FLAG_SE: 8464 case POWERPC_FLAG_DWE: 8465 case POWERPC_FLAG_UBLE: 8466 break; 8467 default: 8468 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8469 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 8470 "POWERPC_FLAG_UBLE\n"); 8471 exit(1); 8472 } 8473 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 8474 POWERPC_FLAG_UBLE)) { 8475 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8476 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 8477 "POWERPC_FLAG_UBLE\n"); 8478 exit(1); 8479 } 8480 if (env->msr_mask & (1 << 9)) { 8481 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8482 case POWERPC_FLAG_BE: 8483 case POWERPC_FLAG_DE: 8484 break; 8485 default: 8486 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8487 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 8488 exit(1); 8489 } 8490 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 8491 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8492 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 8493 exit(1); 8494 } 8495 if (env->msr_mask & (1 << 2)) { 8496 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8497 case POWERPC_FLAG_PX: 8498 case POWERPC_FLAG_PMM: 8499 break; 8500 default: 8501 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8502 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 8503 exit(1); 8504 } 8505 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 8506 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 8507 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 8508 exit(1); 8509 } 8510 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 8511 fprintf(stderr, "PowerPC flags inconsistency\n" 8512 "Should define the time-base and decrementer clock source\n"); 8513 exit(1); 8514 } 8515 /* Allocate TLBs buffer when needed */ 8516 #if !defined(CONFIG_USER_ONLY) 8517 if (env->nb_tlb != 0) { 8518 int nb_tlb = env->nb_tlb; 8519 if (env->id_tlbs != 0) { 8520 nb_tlb *= 2; 8521 } 8522 switch (env->tlb_type) { 8523 case TLB_6XX: 8524 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 8525 break; 8526 case TLB_EMB: 8527 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 8528 break; 8529 case TLB_MAS: 8530 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 8531 break; 8532 } 8533 /* Pre-compute some useful values */ 8534 env->tlb_per_way = env->nb_tlb / env->nb_ways; 8535 } 8536 if (env->irq_inputs == NULL) { 8537 warn_report("no internal IRQ controller registered." 8538 " Attempt QEMU to crash very soon !"); 8539 } 8540 #endif 8541 if (env->check_pow == NULL) { 8542 warn_report("no power management check handler registered." 8543 " Attempt QEMU to crash very soon !"); 8544 } 8545 } 8546 8547 #if defined(PPC_DUMP_CPU) 8548 static void dump_ppc_sprs(CPUPPCState *env) 8549 { 8550 ppc_spr_t *spr; 8551 #if !defined(CONFIG_USER_ONLY) 8552 uint32_t sr, sw; 8553 #endif 8554 uint32_t ur, uw; 8555 int i, j, n; 8556 8557 printf("Special purpose registers:\n"); 8558 for (i = 0; i < 32; i++) { 8559 for (j = 0; j < 32; j++) { 8560 n = (i << 5) | j; 8561 spr = &env->spr_cb[n]; 8562 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; 8563 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; 8564 #if !defined(CONFIG_USER_ONLY) 8565 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; 8566 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; 8567 if (sw || sr || uw || ur) { 8568 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", 8569 (i << 5) | j, (i << 5) | j, spr->name, 8570 sw ? 'w' : '-', sr ? 'r' : '-', 8571 uw ? 'w' : '-', ur ? 'r' : '-'); 8572 } 8573 #else 8574 if (uw || ur) { 8575 printf("SPR: %4d (%03x) %-8s u%c%c\n", 8576 (i << 5) | j, (i << 5) | j, spr->name, 8577 uw ? 'w' : '-', ur ? 'r' : '-'); 8578 } 8579 #endif 8580 } 8581 } 8582 fflush(stdout); 8583 fflush(stderr); 8584 } 8585 #endif 8586 8587 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 8588 { 8589 CPUState *cs = CPU(dev); 8590 PowerPCCPU *cpu = POWERPC_CPU(dev); 8591 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8592 Error *local_err = NULL; 8593 8594 cpu_exec_realizefn(cs, &local_err); 8595 if (local_err != NULL) { 8596 error_propagate(errp, local_err); 8597 return; 8598 } 8599 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 8600 cpu->vcpu_id = cs->cpu_index; 8601 } 8602 8603 if (tcg_enabled()) { 8604 if (ppc_fixup_cpu(cpu) != 0) { 8605 error_setg(errp, "Unable to emulate selected CPU with TCG"); 8606 goto unrealize; 8607 } 8608 } 8609 8610 create_ppc_opcodes(cpu, &local_err); 8611 if (local_err != NULL) { 8612 error_propagate(errp, local_err); 8613 goto unrealize; 8614 } 8615 init_ppc_proc(cpu); 8616 8617 ppc_gdb_init(cs, pcc); 8618 qemu_init_vcpu(cs); 8619 8620 pcc->parent_realize(dev, errp); 8621 8622 #if defined(PPC_DUMP_CPU) 8623 { 8624 CPUPPCState *env = &cpu->env; 8625 const char *mmu_model, *excp_model, *bus_model; 8626 switch (env->mmu_model) { 8627 case POWERPC_MMU_32B: 8628 mmu_model = "PowerPC 32"; 8629 break; 8630 case POWERPC_MMU_SOFT_6xx: 8631 mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; 8632 break; 8633 case POWERPC_MMU_SOFT_74xx: 8634 mmu_model = "PowerPC 74xx with software driven TLBs"; 8635 break; 8636 case POWERPC_MMU_SOFT_4xx: 8637 mmu_model = "PowerPC 4xx with software driven TLBs"; 8638 break; 8639 case POWERPC_MMU_SOFT_4xx_Z: 8640 mmu_model = "PowerPC 4xx with software driven TLBs " 8641 "and zones protections"; 8642 break; 8643 case POWERPC_MMU_REAL: 8644 mmu_model = "PowerPC real mode only"; 8645 break; 8646 case POWERPC_MMU_MPC8xx: 8647 mmu_model = "PowerPC MPC8xx"; 8648 break; 8649 case POWERPC_MMU_BOOKE: 8650 mmu_model = "PowerPC BookE"; 8651 break; 8652 case POWERPC_MMU_BOOKE206: 8653 mmu_model = "PowerPC BookE 2.06"; 8654 break; 8655 case POWERPC_MMU_601: 8656 mmu_model = "PowerPC 601"; 8657 break; 8658 #if defined(TARGET_PPC64) 8659 case POWERPC_MMU_64B: 8660 mmu_model = "PowerPC 64"; 8661 break; 8662 #endif 8663 default: 8664 mmu_model = "Unknown or invalid"; 8665 break; 8666 } 8667 switch (env->excp_model) { 8668 case POWERPC_EXCP_STD: 8669 excp_model = "PowerPC"; 8670 break; 8671 case POWERPC_EXCP_40x: 8672 excp_model = "PowerPC 40x"; 8673 break; 8674 case POWERPC_EXCP_601: 8675 excp_model = "PowerPC 601"; 8676 break; 8677 case POWERPC_EXCP_602: 8678 excp_model = "PowerPC 602"; 8679 break; 8680 case POWERPC_EXCP_603: 8681 excp_model = "PowerPC 603"; 8682 break; 8683 case POWERPC_EXCP_603E: 8684 excp_model = "PowerPC 603e"; 8685 break; 8686 case POWERPC_EXCP_604: 8687 excp_model = "PowerPC 604"; 8688 break; 8689 case POWERPC_EXCP_7x0: 8690 excp_model = "PowerPC 740/750"; 8691 break; 8692 case POWERPC_EXCP_7x5: 8693 excp_model = "PowerPC 745/755"; 8694 break; 8695 case POWERPC_EXCP_74xx: 8696 excp_model = "PowerPC 74xx"; 8697 break; 8698 case POWERPC_EXCP_BOOKE: 8699 excp_model = "PowerPC BookE"; 8700 break; 8701 #if defined(TARGET_PPC64) 8702 case POWERPC_EXCP_970: 8703 excp_model = "PowerPC 970"; 8704 break; 8705 #endif 8706 default: 8707 excp_model = "Unknown or invalid"; 8708 break; 8709 } 8710 switch (env->bus_model) { 8711 case PPC_FLAGS_INPUT_6xx: 8712 bus_model = "PowerPC 6xx"; 8713 break; 8714 case PPC_FLAGS_INPUT_BookE: 8715 bus_model = "PowerPC BookE"; 8716 break; 8717 case PPC_FLAGS_INPUT_405: 8718 bus_model = "PowerPC 405"; 8719 break; 8720 case PPC_FLAGS_INPUT_401: 8721 bus_model = "PowerPC 401/403"; 8722 break; 8723 case PPC_FLAGS_INPUT_RCPU: 8724 bus_model = "RCPU / MPC8xx"; 8725 break; 8726 #if defined(TARGET_PPC64) 8727 case PPC_FLAGS_INPUT_970: 8728 bus_model = "PowerPC 970"; 8729 break; 8730 #endif 8731 default: 8732 bus_model = "Unknown or invalid"; 8733 break; 8734 } 8735 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" 8736 " MMU model : %s\n", 8737 object_class_get_name(OBJECT_CLASS(pcc)), 8738 pcc->pvr, pcc->msr_mask, mmu_model); 8739 #if !defined(CONFIG_USER_ONLY) 8740 if (env->tlb.tlb6) { 8741 printf(" %d %s TLB in %d ways\n", 8742 env->nb_tlb, env->id_tlbs ? "splitted" : "merged", 8743 env->nb_ways); 8744 } 8745 #endif 8746 printf(" Exceptions model : %s\n" 8747 " Bus model : %s\n", 8748 excp_model, bus_model); 8749 printf(" MSR features :\n"); 8750 if (env->flags & POWERPC_FLAG_SPE) { 8751 printf(" signal processing engine enable" 8752 "\n"); 8753 } else if (env->flags & POWERPC_FLAG_VRE) { 8754 printf(" vector processor enable\n"); 8755 } 8756 if (env->flags & POWERPC_FLAG_TGPR) { 8757 printf(" temporary GPRs\n"); 8758 } else if (env->flags & POWERPC_FLAG_CE) { 8759 printf(" critical input enable\n"); 8760 } 8761 if (env->flags & POWERPC_FLAG_SE) { 8762 printf(" single-step trace mode\n"); 8763 } else if (env->flags & POWERPC_FLAG_DWE) { 8764 printf(" debug wait enable\n"); 8765 } else if (env->flags & POWERPC_FLAG_UBLE) { 8766 printf(" user BTB lock enable\n"); 8767 } 8768 if (env->flags & POWERPC_FLAG_BE) { 8769 printf(" branch-step trace mode\n"); 8770 } else if (env->flags & POWERPC_FLAG_DE) { 8771 printf(" debug interrupt enable\n"); 8772 } 8773 if (env->flags & POWERPC_FLAG_PX) { 8774 printf(" inclusive protection\n"); 8775 } else if (env->flags & POWERPC_FLAG_PMM) { 8776 printf(" performance monitor mark\n"); 8777 } 8778 if (env->flags == POWERPC_FLAG_NONE) { 8779 printf(" none\n"); 8780 } 8781 printf(" Time-base/decrementer clock source: %s\n", 8782 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); 8783 dump_ppc_insns(env); 8784 dump_ppc_sprs(env); 8785 fflush(stdout); 8786 } 8787 #endif 8788 return; 8789 8790 unrealize: 8791 cpu_exec_unrealizefn(cs); 8792 } 8793 8794 static void ppc_cpu_unrealize(DeviceState *dev) 8795 { 8796 PowerPCCPU *cpu = POWERPC_CPU(dev); 8797 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8798 8799 pcc->parent_unrealize(dev); 8800 8801 cpu_remove_sync(CPU(cpu)); 8802 8803 destroy_ppc_opcodes(cpu); 8804 } 8805 8806 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 8807 { 8808 ObjectClass *oc = (ObjectClass *)a; 8809 uint32_t pvr = *(uint32_t *)b; 8810 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8811 8812 /* -cpu host does a PVR lookup during construction */ 8813 if (unlikely(strcmp(object_class_get_name(oc), 8814 TYPE_HOST_POWERPC_CPU) == 0)) { 8815 return -1; 8816 } 8817 8818 return pcc->pvr == pvr ? 0 : -1; 8819 } 8820 8821 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 8822 { 8823 GSList *list, *item; 8824 PowerPCCPUClass *pcc = NULL; 8825 8826 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8827 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 8828 if (item != NULL) { 8829 pcc = POWERPC_CPU_CLASS(item->data); 8830 } 8831 g_slist_free(list); 8832 8833 return pcc; 8834 } 8835 8836 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 8837 { 8838 ObjectClass *oc = (ObjectClass *)a; 8839 uint32_t pvr = *(uint32_t *)b; 8840 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8841 8842 /* -cpu host does a PVR lookup during construction */ 8843 if (unlikely(strcmp(object_class_get_name(oc), 8844 TYPE_HOST_POWERPC_CPU) == 0)) { 8845 return -1; 8846 } 8847 8848 if (pcc->pvr_match(pcc, pvr)) { 8849 return 0; 8850 } 8851 8852 return -1; 8853 } 8854 8855 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 8856 { 8857 GSList *list, *item; 8858 PowerPCCPUClass *pcc = NULL; 8859 8860 list = object_class_get_list(TYPE_POWERPC_CPU, true); 8861 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 8862 if (item != NULL) { 8863 pcc = POWERPC_CPU_CLASS(item->data); 8864 } 8865 g_slist_free(list); 8866 8867 return pcc; 8868 } 8869 8870 static const char *ppc_cpu_lookup_alias(const char *alias) 8871 { 8872 int ai; 8873 8874 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 8875 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 8876 return ppc_cpu_aliases[ai].model; 8877 } 8878 } 8879 8880 return NULL; 8881 } 8882 8883 static ObjectClass *ppc_cpu_class_by_name(const char *name) 8884 { 8885 char *cpu_model, *typename; 8886 ObjectClass *oc; 8887 const char *p; 8888 unsigned long pvr; 8889 8890 /* 8891 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 8892 * 0x prefix if present) 8893 */ 8894 if (!qemu_strtoul(name, &p, 16, &pvr)) { 8895 int len = p - name; 8896 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 8897 if ((len == 8) && (*p == '\0')) { 8898 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 8899 } 8900 } 8901 8902 cpu_model = g_ascii_strdown(name, -1); 8903 p = ppc_cpu_lookup_alias(cpu_model); 8904 if (p) { 8905 g_free(cpu_model); 8906 cpu_model = g_strdup(p); 8907 } 8908 8909 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 8910 oc = object_class_by_name(typename); 8911 g_free(typename); 8912 g_free(cpu_model); 8913 8914 return oc; 8915 } 8916 8917 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 8918 { 8919 ObjectClass *oc = OBJECT_CLASS(pcc); 8920 8921 while (oc && !object_class_is_abstract(oc)) { 8922 oc = object_class_get_parent(oc); 8923 } 8924 assert(oc); 8925 8926 return POWERPC_CPU_CLASS(oc); 8927 } 8928 8929 /* Sort by PVR, ordering special case "host" last. */ 8930 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 8931 { 8932 ObjectClass *oc_a = (ObjectClass *)a; 8933 ObjectClass *oc_b = (ObjectClass *)b; 8934 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 8935 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 8936 const char *name_a = object_class_get_name(oc_a); 8937 const char *name_b = object_class_get_name(oc_b); 8938 8939 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 8940 return 1; 8941 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 8942 return -1; 8943 } else { 8944 /* Avoid an integer overflow during subtraction */ 8945 if (pcc_a->pvr < pcc_b->pvr) { 8946 return -1; 8947 } else if (pcc_a->pvr > pcc_b->pvr) { 8948 return 1; 8949 } else { 8950 return 0; 8951 } 8952 } 8953 } 8954 8955 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8956 { 8957 ObjectClass *oc = data; 8958 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8959 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8960 const char *typename = object_class_get_name(oc); 8961 char *name; 8962 int i; 8963 8964 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8965 return; 8966 } 8967 8968 name = g_strndup(typename, 8969 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8970 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8971 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8972 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8973 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8974 8975 if (alias_oc != oc) { 8976 continue; 8977 } 8978 /* 8979 * If running with KVM, we might update the family alias later, so 8980 * avoid printing the wrong alias here and use "preferred" instead 8981 */ 8982 if (strcmp(alias->alias, family->desc) == 0) { 8983 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8984 alias->alias, family->desc); 8985 } else { 8986 qemu_printf("PowerPC %-16s (alias for %s)\n", 8987 alias->alias, name); 8988 } 8989 } 8990 g_free(name); 8991 } 8992 8993 void ppc_cpu_list(void) 8994 { 8995 GSList *list; 8996 8997 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8998 list = g_slist_sort(list, ppc_cpu_list_compare); 8999 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 9000 g_slist_free(list); 9001 9002 #ifdef CONFIG_KVM 9003 qemu_printf("\n"); 9004 qemu_printf("PowerPC %-16s\n", "host"); 9005 #endif 9006 } 9007 9008 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 9009 { 9010 ObjectClass *oc = data; 9011 CpuDefinitionInfoList **first = user_data; 9012 const char *typename; 9013 CpuDefinitionInfo *info; 9014 9015 typename = object_class_get_name(oc); 9016 info = g_malloc0(sizeof(*info)); 9017 info->name = g_strndup(typename, 9018 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 9019 9020 QAPI_LIST_PREPEND(*first, info); 9021 } 9022 9023 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 9024 { 9025 CpuDefinitionInfoList *cpu_list = NULL; 9026 GSList *list; 9027 int i; 9028 9029 list = object_class_get_list(TYPE_POWERPC_CPU, false); 9030 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 9031 g_slist_free(list); 9032 9033 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 9034 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 9035 ObjectClass *oc; 9036 CpuDefinitionInfo *info; 9037 9038 oc = ppc_cpu_class_by_name(alias->model); 9039 if (oc == NULL) { 9040 continue; 9041 } 9042 9043 info = g_malloc0(sizeof(*info)); 9044 info->name = g_strdup(alias->alias); 9045 info->q_typename = g_strdup(object_class_get_name(oc)); 9046 9047 QAPI_LIST_PREPEND(cpu_list, info); 9048 } 9049 9050 return cpu_list; 9051 } 9052 9053 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 9054 { 9055 PowerPCCPU *cpu = POWERPC_CPU(cs); 9056 9057 cpu->env.nip = value; 9058 } 9059 9060 static bool ppc_cpu_has_work(CPUState *cs) 9061 { 9062 PowerPCCPU *cpu = POWERPC_CPU(cs); 9063 CPUPPCState *env = &cpu->env; 9064 9065 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 9066 } 9067 9068 static void ppc_cpu_reset(DeviceState *dev) 9069 { 9070 CPUState *s = CPU(dev); 9071 PowerPCCPU *cpu = POWERPC_CPU(s); 9072 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9073 CPUPPCState *env = &cpu->env; 9074 target_ulong msr; 9075 int i; 9076 9077 pcc->parent_reset(dev); 9078 9079 msr = (target_ulong)0; 9080 msr |= (target_ulong)MSR_HVB; 9081 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 9082 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 9083 msr |= (target_ulong)1 << MSR_EP; 9084 #if defined(DO_SINGLE_STEP) && 0 9085 /* Single step trace mode */ 9086 msr |= (target_ulong)1 << MSR_SE; 9087 msr |= (target_ulong)1 << MSR_BE; 9088 #endif 9089 #if defined(CONFIG_USER_ONLY) 9090 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 9091 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 9092 msr |= (target_ulong)1 << MSR_FE1; 9093 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 9094 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 9095 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 9096 msr |= (target_ulong)1 << MSR_PR; 9097 #if defined(TARGET_PPC64) 9098 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 9099 #endif 9100 #if !defined(TARGET_WORDS_BIGENDIAN) 9101 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 9102 if (!((env->msr_mask >> MSR_LE) & 1)) { 9103 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 9104 exit(1); 9105 } 9106 #endif 9107 #endif 9108 9109 #if defined(TARGET_PPC64) 9110 if (mmu_is_64bit(env->mmu_model)) { 9111 msr |= (1ULL << MSR_SF); 9112 } 9113 #endif 9114 9115 hreg_store_msr(env, msr, 1); 9116 9117 #if !defined(CONFIG_USER_ONLY) 9118 env->nip = env->hreset_vector | env->excp_prefix; 9119 if (env->mmu_model != POWERPC_MMU_REAL) { 9120 ppc_tlb_invalidate_all(env); 9121 } 9122 #endif 9123 9124 hreg_compute_hflags(env); 9125 env->reserve_addr = (target_ulong)-1ULL; 9126 /* Be sure no exception or interrupt is pending */ 9127 env->pending_interrupts = 0; 9128 s->exception_index = POWERPC_EXCP_NONE; 9129 env->error_code = 0; 9130 ppc_irq_reset(cpu); 9131 9132 /* tininess for underflow is detected before rounding */ 9133 set_float_detect_tininess(float_tininess_before_rounding, 9134 &env->fp_status); 9135 9136 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 9137 ppc_spr_t *spr = &env->spr_cb[i]; 9138 9139 if (!spr->name) { 9140 continue; 9141 } 9142 env->spr[i] = spr->default_value; 9143 } 9144 } 9145 9146 #ifndef CONFIG_USER_ONLY 9147 9148 static bool ppc_cpu_is_big_endian(CPUState *cs) 9149 { 9150 PowerPCCPU *cpu = POWERPC_CPU(cs); 9151 CPUPPCState *env = &cpu->env; 9152 9153 cpu_synchronize_state(cs); 9154 9155 return !msr_le; 9156 } 9157 9158 #ifdef CONFIG_TCG 9159 static void ppc_cpu_exec_enter(CPUState *cs) 9160 { 9161 PowerPCCPU *cpu = POWERPC_CPU(cs); 9162 9163 if (cpu->vhyp) { 9164 PPCVirtualHypervisorClass *vhc = 9165 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 9166 vhc->cpu_exec_enter(cpu->vhyp, cpu); 9167 } 9168 } 9169 9170 static void ppc_cpu_exec_exit(CPUState *cs) 9171 { 9172 PowerPCCPU *cpu = POWERPC_CPU(cs); 9173 9174 if (cpu->vhyp) { 9175 PPCVirtualHypervisorClass *vhc = 9176 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 9177 vhc->cpu_exec_exit(cpu->vhyp, cpu); 9178 } 9179 } 9180 #endif /* CONFIG_TCG */ 9181 9182 #endif /* !CONFIG_USER_ONLY */ 9183 9184 static void ppc_cpu_instance_init(Object *obj) 9185 { 9186 PowerPCCPU *cpu = POWERPC_CPU(obj); 9187 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9188 CPUPPCState *env = &cpu->env; 9189 9190 cpu_set_cpustate_pointers(cpu); 9191 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 9192 9193 env->msr_mask = pcc->msr_mask; 9194 env->mmu_model = pcc->mmu_model; 9195 env->excp_model = pcc->excp_model; 9196 env->bus_model = pcc->bus_model; 9197 env->insns_flags = pcc->insns_flags; 9198 env->insns_flags2 = pcc->insns_flags2; 9199 env->flags = pcc->flags; 9200 env->bfd_mach = pcc->bfd_mach; 9201 env->check_pow = pcc->check_pow; 9202 9203 /* 9204 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 9205 * msr_mask. The mask can later be cleared by PAPR mode but the hv 9206 * mode support will remain, thus enforcing that we cannot use 9207 * priv. instructions in guest in PAPR mode. For 970 we currently 9208 * simply don't set HV in msr_mask thus simulating an "Apple mode" 9209 * 970. If we ever want to support 970 HV mode, we'll have to add 9210 * a processor attribute of some sort. 9211 */ 9212 #if !defined(CONFIG_USER_ONLY) 9213 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 9214 #endif 9215 9216 ppc_hash64_init(cpu); 9217 } 9218 9219 static void ppc_cpu_instance_finalize(Object *obj) 9220 { 9221 PowerPCCPU *cpu = POWERPC_CPU(obj); 9222 9223 ppc_hash64_finalize(cpu); 9224 } 9225 9226 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 9227 { 9228 return pcc->pvr == pvr; 9229 } 9230 9231 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 9232 { 9233 PowerPCCPU *cpu = POWERPC_CPU(cs); 9234 CPUPPCState *env = &cpu->env; 9235 9236 if ((env->hflags >> MSR_LE) & 1) { 9237 info->endian = BFD_ENDIAN_LITTLE; 9238 } 9239 info->mach = env->bfd_mach; 9240 if (!env->bfd_mach) { 9241 #ifdef TARGET_PPC64 9242 info->mach = bfd_mach_ppc64; 9243 #else 9244 info->mach = bfd_mach_ppc; 9245 #endif 9246 } 9247 info->disassembler_options = (char *)"any"; 9248 info->print_insn = print_insn_ppc; 9249 9250 info->cap_arch = CS_ARCH_PPC; 9251 #ifdef TARGET_PPC64 9252 info->cap_mode = CS_MODE_64; 9253 #endif 9254 } 9255 9256 static Property ppc_cpu_properties[] = { 9257 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 9258 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 9259 false), 9260 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 9261 false), 9262 DEFINE_PROP_END_OF_LIST(), 9263 }; 9264 9265 #ifndef CONFIG_USER_ONLY 9266 #include "hw/core/sysemu-cpu-ops.h" 9267 9268 static const struct SysemuCPUOps ppc_sysemu_ops = { 9269 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 9270 .write_elf32_note = ppc32_cpu_write_elf32_note, 9271 .write_elf64_note = ppc64_cpu_write_elf64_note, 9272 .virtio_is_big_endian = ppc_cpu_is_big_endian, 9273 .legacy_vmsd = &vmstate_ppc_cpu, 9274 }; 9275 #endif 9276 9277 #ifdef CONFIG_TCG 9278 #include "hw/core/tcg-cpu-ops.h" 9279 9280 static const struct TCGCPUOps ppc_tcg_ops = { 9281 .initialize = ppc_translate_init, 9282 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 9283 .tlb_fill = ppc_cpu_tlb_fill, 9284 9285 #ifndef CONFIG_USER_ONLY 9286 .do_interrupt = ppc_cpu_do_interrupt, 9287 .cpu_exec_enter = ppc_cpu_exec_enter, 9288 .cpu_exec_exit = ppc_cpu_exec_exit, 9289 .do_unaligned_access = ppc_cpu_do_unaligned_access, 9290 #endif /* !CONFIG_USER_ONLY */ 9291 }; 9292 #endif /* CONFIG_TCG */ 9293 9294 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 9295 { 9296 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9297 CPUClass *cc = CPU_CLASS(oc); 9298 DeviceClass *dc = DEVICE_CLASS(oc); 9299 9300 device_class_set_parent_realize(dc, ppc_cpu_realize, 9301 &pcc->parent_realize); 9302 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 9303 &pcc->parent_unrealize); 9304 pcc->pvr_match = ppc_pvr_match_default; 9305 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; 9306 device_class_set_props(dc, ppc_cpu_properties); 9307 9308 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 9309 9310 cc->class_by_name = ppc_cpu_class_by_name; 9311 cc->has_work = ppc_cpu_has_work; 9312 cc->dump_state = ppc_cpu_dump_state; 9313 cc->dump_statistics = ppc_cpu_dump_statistics; 9314 cc->set_pc = ppc_cpu_set_pc; 9315 cc->gdb_read_register = ppc_cpu_gdb_read_register; 9316 cc->gdb_write_register = ppc_cpu_gdb_write_register; 9317 #ifndef CONFIG_USER_ONLY 9318 cc->sysemu_ops = &ppc_sysemu_ops; 9319 #endif 9320 9321 cc->gdb_num_core_regs = 71; 9322 #ifndef CONFIG_USER_ONLY 9323 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 9324 #endif 9325 #ifdef USE_APPLE_GDB 9326 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 9327 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 9328 cc->gdb_num_core_regs = 71 + 32; 9329 #endif 9330 9331 cc->gdb_arch_name = ppc_gdb_arch_name; 9332 #if defined(TARGET_PPC64) 9333 cc->gdb_core_xml_file = "power64-core.xml"; 9334 #else 9335 cc->gdb_core_xml_file = "power-core.xml"; 9336 #endif 9337 cc->disas_set_info = ppc_disas_set_info; 9338 9339 dc->fw_name = "PowerPC,UNKNOWN"; 9340 9341 #ifdef CONFIG_TCG 9342 cc->tcg_ops = &ppc_tcg_ops; 9343 #endif /* CONFIG_TCG */ 9344 } 9345 9346 static const TypeInfo ppc_cpu_type_info = { 9347 .name = TYPE_POWERPC_CPU, 9348 .parent = TYPE_CPU, 9349 .instance_size = sizeof(PowerPCCPU), 9350 .instance_align = __alignof__(PowerPCCPU), 9351 .instance_init = ppc_cpu_instance_init, 9352 .instance_finalize = ppc_cpu_instance_finalize, 9353 .abstract = true, 9354 .class_size = sizeof(PowerPCCPUClass), 9355 .class_init = ppc_cpu_class_init, 9356 }; 9357 9358 #ifndef CONFIG_USER_ONLY 9359 static const TypeInfo ppc_vhyp_type_info = { 9360 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 9361 .parent = TYPE_INTERFACE, 9362 .class_size = sizeof(PPCVirtualHypervisorClass), 9363 }; 9364 #endif 9365 9366 static void ppc_cpu_register_types(void) 9367 { 9368 type_register_static(&ppc_cpu_type_info); 9369 #ifndef CONFIG_USER_ONLY 9370 type_register_static(&ppc_vhyp_type_info); 9371 #endif 9372 } 9373 9374 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 9375 { 9376 #define RGPL 4 9377 #define RFPL 4 9378 9379 PowerPCCPU *cpu = POWERPC_CPU(cs); 9380 CPUPPCState *env = &cpu->env; 9381 int i; 9382 9383 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 9384 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 9385 env->nip, env->lr, env->ctr, cpu_read_xer(env), 9386 cs->cpu_index); 9387 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 9388 "%08x iidx %d didx %d\n", 9389 env->msr, env->spr[SPR_HID0], env->hflags, 9390 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 9391 #if !defined(NO_TIMER_DUMP) 9392 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 9393 #if !defined(CONFIG_USER_ONLY) 9394 " DECR " TARGET_FMT_lu 9395 #endif 9396 "\n", 9397 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 9398 #if !defined(CONFIG_USER_ONLY) 9399 , cpu_ppc_load_decr(env) 9400 #endif 9401 ); 9402 #endif 9403 for (i = 0; i < 32; i++) { 9404 if ((i & (RGPL - 1)) == 0) { 9405 qemu_fprintf(f, "GPR%02d", i); 9406 } 9407 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 9408 if ((i & (RGPL - 1)) == (RGPL - 1)) { 9409 qemu_fprintf(f, "\n"); 9410 } 9411 } 9412 qemu_fprintf(f, "CR "); 9413 for (i = 0; i < 8; i++) 9414 qemu_fprintf(f, "%01x", env->crf[i]); 9415 qemu_fprintf(f, " ["); 9416 for (i = 0; i < 8; i++) { 9417 char a = '-'; 9418 if (env->crf[i] & 0x08) { 9419 a = 'L'; 9420 } else if (env->crf[i] & 0x04) { 9421 a = 'G'; 9422 } else if (env->crf[i] & 0x02) { 9423 a = 'E'; 9424 } 9425 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 9426 } 9427 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 9428 env->reserve_addr); 9429 9430 if (flags & CPU_DUMP_FPU) { 9431 for (i = 0; i < 32; i++) { 9432 if ((i & (RFPL - 1)) == 0) { 9433 qemu_fprintf(f, "FPR%02d", i); 9434 } 9435 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 9436 if ((i & (RFPL - 1)) == (RFPL - 1)) { 9437 qemu_fprintf(f, "\n"); 9438 } 9439 } 9440 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 9441 } 9442 9443 #if !defined(CONFIG_USER_ONLY) 9444 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 9445 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 9446 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 9447 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 9448 9449 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 9450 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 9451 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 9452 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 9453 9454 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 9455 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 9456 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 9457 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 9458 9459 #if defined(TARGET_PPC64) 9460 if (env->excp_model == POWERPC_EXCP_POWER7 || 9461 env->excp_model == POWERPC_EXCP_POWER8 || 9462 env->excp_model == POWERPC_EXCP_POWER9 || 9463 env->excp_model == POWERPC_EXCP_POWER10) { 9464 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 9465 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 9466 } 9467 #endif 9468 if (env->excp_model == POWERPC_EXCP_BOOKE) { 9469 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 9470 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 9471 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 9472 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 9473 9474 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 9475 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 9476 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 9477 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 9478 9479 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 9480 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 9481 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 9482 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 9483 9484 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 9485 " EPR " TARGET_FMT_lx "\n", 9486 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 9487 env->spr[SPR_BOOKE_EPR]); 9488 9489 /* FSL-specific */ 9490 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 9491 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 9492 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 9493 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 9494 9495 /* 9496 * IVORs are left out as they are large and do not change often -- 9497 * they can be read with "p $ivor0", "p $ivor1", etc. 9498 */ 9499 } 9500 9501 #if defined(TARGET_PPC64) 9502 if (env->flags & POWERPC_FLAG_CFAR) { 9503 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 9504 } 9505 #endif 9506 9507 if (env->spr_cb[SPR_LPCR].name) { 9508 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 9509 } 9510 9511 switch (env->mmu_model) { 9512 case POWERPC_MMU_32B: 9513 case POWERPC_MMU_601: 9514 case POWERPC_MMU_SOFT_6xx: 9515 case POWERPC_MMU_SOFT_74xx: 9516 #if defined(TARGET_PPC64) 9517 case POWERPC_MMU_64B: 9518 case POWERPC_MMU_2_03: 9519 case POWERPC_MMU_2_06: 9520 case POWERPC_MMU_2_07: 9521 case POWERPC_MMU_3_00: 9522 #endif 9523 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 9524 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 9525 } 9526 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 9527 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 9528 } 9529 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 9530 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 9531 break; 9532 case POWERPC_MMU_BOOKE206: 9533 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 9534 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 9535 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 9536 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 9537 9538 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 9539 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 9540 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 9541 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 9542 9543 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 9544 " TLB1CFG " TARGET_FMT_lx "\n", 9545 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 9546 env->spr[SPR_BOOKE_TLB1CFG]); 9547 break; 9548 default: 9549 break; 9550 } 9551 #endif 9552 9553 #undef RGPL 9554 #undef RFPL 9555 } 9556 type_init(ppc_cpu_register_types) 9557