1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "gdbstub/helpers.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/hw_accel.h" 26 #include "sysemu/tcg.h" 27 #include "cpu-models.h" 28 #include "mmu-hash32.h" 29 #include "mmu-hash64.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 #include "qemu/qemu-print.h" 33 #include "qapi/error.h" 34 #include "qapi/qmp/qnull.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/ppc/ppc.h" 38 #include "mmu-book3s-v3.h" 39 #include "qemu/cutils.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 #include "helper_regs.h" 44 #include "internal.h" 45 #include "spr_common.h" 46 #include "power8-pmu.h" 47 48 #ifndef CONFIG_USER_ONLY 49 #include "hw/boards.h" 50 #include "hw/intc/intc.h" 51 #include "kvm_ppc.h" 52 #endif 53 54 /* #define PPC_DEBUG_SPR */ 55 /* #define USE_APPLE_GDB */ 56 57 static inline void vscr_init(CPUPPCState *env, uint32_t val) 58 { 59 /* Altivec always uses round-to-nearest */ 60 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 61 ppc_store_vscr(env, val); 62 } 63 64 static void register_745_sprs(CPUPPCState *env) 65 { 66 /* SGPRs */ 67 spr_register(env, SPR_SPRG4, "SPRG4", 68 SPR_NOACCESS, SPR_NOACCESS, 69 &spr_read_generic, &spr_write_generic, 70 0x00000000); 71 spr_register(env, SPR_SPRG5, "SPRG5", 72 SPR_NOACCESS, SPR_NOACCESS, 73 &spr_read_generic, &spr_write_generic, 74 0x00000000); 75 spr_register(env, SPR_SPRG6, "SPRG6", 76 SPR_NOACCESS, SPR_NOACCESS, 77 &spr_read_generic, &spr_write_generic, 78 0x00000000); 79 spr_register(env, SPR_SPRG7, "SPRG7", 80 SPR_NOACCESS, SPR_NOACCESS, 81 &spr_read_generic, &spr_write_generic, 82 0x00000000); 83 84 /* Hardware implementation registers */ 85 spr_register(env, SPR_HID0, "HID0", 86 SPR_NOACCESS, SPR_NOACCESS, 87 &spr_read_generic, &spr_write_generic, 88 0x00000000); 89 90 spr_register(env, SPR_HID1, "HID1", 91 SPR_NOACCESS, SPR_NOACCESS, 92 &spr_read_generic, &spr_write_generic, 93 0x00000000); 94 95 spr_register(env, SPR_HID2, "HID2", 96 SPR_NOACCESS, SPR_NOACCESS, 97 &spr_read_generic, &spr_write_generic, 98 0x00000000); 99 } 100 101 static void register_755_sprs(CPUPPCState *env) 102 { 103 /* L2 cache control */ 104 spr_register(env, SPR_L2CR, "L2CR", 105 SPR_NOACCESS, SPR_NOACCESS, 106 &spr_read_generic, spr_access_nop, 107 0x00000000); 108 109 spr_register(env, SPR_L2PMCR, "L2PMCR", 110 SPR_NOACCESS, SPR_NOACCESS, 111 &spr_read_generic, &spr_write_generic, 112 0x00000000); 113 } 114 115 /* SPR common to all 7xx PowerPC implementations */ 116 static void register_7xx_sprs(CPUPPCState *env) 117 { 118 /* Breakpoints */ 119 spr_register_kvm(env, SPR_DABR, "DABR", 120 SPR_NOACCESS, SPR_NOACCESS, 121 &spr_read_generic, &spr_write_generic, 122 KVM_REG_PPC_DABR, 0x00000000); 123 124 spr_register(env, SPR_IABR, "IABR", 125 SPR_NOACCESS, SPR_NOACCESS, 126 &spr_read_generic, &spr_write_generic, 127 0x00000000); 128 /* Cache management */ 129 spr_register(env, SPR_ICTC, "ICTC", 130 SPR_NOACCESS, SPR_NOACCESS, 131 &spr_read_generic, &spr_write_generic, 132 0x00000000); 133 /* Performance monitors */ 134 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 135 SPR_NOACCESS, SPR_NOACCESS, 136 &spr_read_generic, &spr_write_generic, 137 0x00000000); 138 139 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 140 SPR_NOACCESS, SPR_NOACCESS, 141 &spr_read_generic, &spr_write_generic, 142 0x00000000); 143 144 spr_register(env, SPR_7XX_PMC1, "PMC1", 145 SPR_NOACCESS, SPR_NOACCESS, 146 &spr_read_generic, &spr_write_generic, 147 0x00000000); 148 149 spr_register(env, SPR_7XX_PMC2, "PMC2", 150 SPR_NOACCESS, SPR_NOACCESS, 151 &spr_read_generic, &spr_write_generic, 152 0x00000000); 153 154 spr_register(env, SPR_7XX_PMC3, "PMC3", 155 SPR_NOACCESS, SPR_NOACCESS, 156 &spr_read_generic, &spr_write_generic, 157 0x00000000); 158 159 spr_register(env, SPR_7XX_PMC4, "PMC4", 160 SPR_NOACCESS, SPR_NOACCESS, 161 &spr_read_generic, &spr_write_generic, 162 0x00000000); 163 164 spr_register(env, SPR_7XX_SIAR, "SIAR", 165 SPR_NOACCESS, SPR_NOACCESS, 166 &spr_read_generic, SPR_NOACCESS, 167 0x00000000); 168 169 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 170 &spr_read_ureg, SPR_NOACCESS, 171 &spr_read_ureg, SPR_NOACCESS, 172 0x00000000); 173 174 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 175 &spr_read_ureg, SPR_NOACCESS, 176 &spr_read_ureg, SPR_NOACCESS, 177 0x00000000); 178 179 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 180 &spr_read_ureg, SPR_NOACCESS, 181 &spr_read_ureg, SPR_NOACCESS, 182 0x00000000); 183 184 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 185 &spr_read_ureg, SPR_NOACCESS, 186 &spr_read_ureg, SPR_NOACCESS, 187 0x00000000); 188 189 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 190 &spr_read_ureg, SPR_NOACCESS, 191 &spr_read_ureg, SPR_NOACCESS, 192 0x00000000); 193 194 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 195 &spr_read_ureg, SPR_NOACCESS, 196 &spr_read_ureg, SPR_NOACCESS, 197 0x00000000); 198 199 spr_register(env, SPR_7XX_USIAR, "USIAR", 200 &spr_read_ureg, SPR_NOACCESS, 201 &spr_read_ureg, SPR_NOACCESS, 202 0x00000000); 203 /* External access control */ 204 spr_register(env, SPR_EAR, "EAR", 205 SPR_NOACCESS, SPR_NOACCESS, 206 &spr_read_generic, &spr_write_generic, 207 0x00000000); 208 209 /* Hardware implementation registers */ 210 spr_register(env, SPR_HID0, "HID0", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_generic, &spr_write_generic, 213 0x00000000); 214 215 spr_register(env, SPR_HID1, "HID1", 216 SPR_NOACCESS, SPR_NOACCESS, 217 &spr_read_generic, &spr_write_generic, 218 0x00000000); 219 } 220 221 #ifdef TARGET_PPC64 222 static void register_amr_sprs(CPUPPCState *env) 223 { 224 #ifndef CONFIG_USER_ONLY 225 /* 226 * Virtual Page Class Key protection 227 * 228 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 229 * userspace accessible, 29 is privileged. So we only need to set 230 * the kvm ONE_REG id on one of them, we use 29 231 */ 232 spr_register(env, SPR_UAMR, "UAMR", 233 &spr_read_generic, &spr_write_amr, 234 &spr_read_generic, &spr_write_amr, 235 0); 236 spr_register_kvm_hv(env, SPR_AMR, "AMR", 237 SPR_NOACCESS, SPR_NOACCESS, 238 &spr_read_generic, &spr_write_amr, 239 &spr_read_generic, &spr_write_generic, 240 KVM_REG_PPC_AMR, 0); 241 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 242 SPR_NOACCESS, SPR_NOACCESS, 243 &spr_read_generic, &spr_write_uamor, 244 &spr_read_generic, &spr_write_generic, 245 KVM_REG_PPC_UAMOR, 0); 246 spr_register_hv(env, SPR_AMOR, "AMOR", 247 SPR_NOACCESS, SPR_NOACCESS, 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_generic, &spr_core_lpar_write_generic, 250 0); 251 #endif /* !CONFIG_USER_ONLY */ 252 } 253 254 static void register_iamr_sprs(CPUPPCState *env) 255 { 256 #ifndef CONFIG_USER_ONLY 257 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_generic, &spr_write_iamr, 260 &spr_read_generic, &spr_write_generic, 261 KVM_REG_PPC_IAMR, 0); 262 #endif /* !CONFIG_USER_ONLY */ 263 } 264 #endif /* TARGET_PPC64 */ 265 266 /* SPR specific to PowerPC 604 implementation */ 267 static void register_604_sprs(CPUPPCState *env) 268 { 269 /* Processor identification */ 270 spr_register(env, SPR_PIR, "PIR", 271 SPR_NOACCESS, SPR_NOACCESS, 272 &spr_read_generic, &spr_write_pir, 273 0x00000000); 274 /* Breakpoints */ 275 spr_register(env, SPR_IABR, "IABR", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_generic, &spr_write_generic, 278 0x00000000); 279 280 spr_register_kvm(env, SPR_DABR, "DABR", 281 SPR_NOACCESS, SPR_NOACCESS, 282 &spr_read_generic, &spr_write_generic, 283 KVM_REG_PPC_DABR, 0x00000000); 284 /* Performance counters */ 285 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 286 SPR_NOACCESS, SPR_NOACCESS, 287 &spr_read_generic, &spr_write_generic, 288 0x00000000); 289 290 spr_register(env, SPR_7XX_PMC1, "PMC1", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_generic, &spr_write_generic, 293 0x00000000); 294 295 spr_register(env, SPR_7XX_PMC2, "PMC2", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_generic, &spr_write_generic, 298 0x00000000); 299 300 spr_register(env, SPR_7XX_SIAR, "SIAR", 301 SPR_NOACCESS, SPR_NOACCESS, 302 &spr_read_generic, SPR_NOACCESS, 303 0x00000000); 304 305 spr_register(env, SPR_SDA, "SDA", 306 SPR_NOACCESS, SPR_NOACCESS, 307 &spr_read_generic, SPR_NOACCESS, 308 0x00000000); 309 /* External access control */ 310 spr_register(env, SPR_EAR, "EAR", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_generic, &spr_write_generic, 313 0x00000000); 314 315 /* Hardware implementation registers */ 316 spr_register(env, SPR_HID0, "HID0", 317 SPR_NOACCESS, SPR_NOACCESS, 318 &spr_read_generic, &spr_write_generic, 319 0x00000000); 320 } 321 322 static void register_604e_sprs(CPUPPCState *env) 323 { 324 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 325 SPR_NOACCESS, SPR_NOACCESS, 326 &spr_read_generic, &spr_write_generic, 327 0x00000000); 328 329 spr_register(env, SPR_7XX_PMC3, "PMC3", 330 SPR_NOACCESS, SPR_NOACCESS, 331 &spr_read_generic, &spr_write_generic, 332 0x00000000); 333 334 spr_register(env, SPR_7XX_PMC4, "PMC4", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_generic, &spr_write_generic, 337 0x00000000); 338 /* Hardware implementation registers */ 339 spr_register(env, SPR_HID1, "HID1", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_generic, &spr_write_generic, 342 0x00000000); 343 } 344 345 /* SPR specific to PowerPC 603 implementation */ 346 static void register_603_sprs(CPUPPCState *env) 347 { 348 /* External access control */ 349 spr_register(env, SPR_EAR, "EAR", 350 SPR_NOACCESS, SPR_NOACCESS, 351 &spr_read_generic, &spr_write_generic, 352 0x00000000); 353 /* Breakpoints */ 354 spr_register(env, SPR_IABR, "IABR", 355 SPR_NOACCESS, SPR_NOACCESS, 356 &spr_read_generic, &spr_write_generic, 357 0x00000000); 358 359 spr_register(env, SPR_HID0, "HID0", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_generic, &spr_write_generic, 362 0x00000000); 363 364 spr_register(env, SPR_HID1, "HID1", 365 SPR_NOACCESS, SPR_NOACCESS, 366 &spr_read_generic, &spr_write_generic, 367 0x00000000); 368 } 369 370 static void register_e300_sprs(CPUPPCState *env) 371 { 372 /* hardware implementation registers */ 373 spr_register(env, SPR_HID2, "HID2", 374 SPR_NOACCESS, SPR_NOACCESS, 375 &spr_read_generic, &spr_write_generic, 376 0x00000000); 377 /* Breakpoints */ 378 spr_register(env, SPR_DABR, "DABR", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_generic, &spr_write_generic, 381 0x00000000); 382 383 spr_register(env, SPR_DABR2, "DABR2", 384 SPR_NOACCESS, SPR_NOACCESS, 385 &spr_read_generic, &spr_write_generic, 386 0x00000000); 387 388 spr_register(env, SPR_IABR2, "IABR2", 389 SPR_NOACCESS, SPR_NOACCESS, 390 &spr_read_generic, &spr_write_generic, 391 0x00000000); 392 393 spr_register(env, SPR_IBCR, "IBCR", 394 SPR_NOACCESS, SPR_NOACCESS, 395 &spr_read_generic, &spr_write_generic, 396 0x00000000); 397 398 spr_register(env, SPR_DBCR, "DBCR", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_generic, &spr_write_generic, 401 0x00000000); 402 } 403 404 /* SPR specific to PowerPC G2 implementation */ 405 static void register_G2_sprs(CPUPPCState *env) 406 { 407 /* Memory base address */ 408 /* MBAR */ 409 spr_register(env, SPR_MBAR, "MBAR", 410 SPR_NOACCESS, SPR_NOACCESS, 411 &spr_read_generic, &spr_write_generic, 412 0x00000000); 413 /* Exception processing */ 414 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_generic, &spr_write_generic, 417 0x00000000); 418 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_generic, &spr_write_generic, 421 0x00000000); 422 /* Breakpoints */ 423 spr_register(env, SPR_DABR, "DABR", 424 SPR_NOACCESS, SPR_NOACCESS, 425 &spr_read_generic, &spr_write_generic, 426 0x00000000); 427 428 spr_register(env, SPR_DABR2, "DABR2", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, &spr_write_generic, 431 0x00000000); 432 433 spr_register(env, SPR_IABR, "IABR", 434 SPR_NOACCESS, SPR_NOACCESS, 435 &spr_read_generic, &spr_write_generic, 436 0x00000000); 437 438 spr_register(env, SPR_IABR2, "IABR2", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, &spr_write_generic, 441 0x00000000); 442 443 spr_register(env, SPR_IBCR, "IBCR", 444 SPR_NOACCESS, SPR_NOACCESS, 445 &spr_read_generic, &spr_write_generic, 446 0x00000000); 447 448 spr_register(env, SPR_DBCR, "DBCR", 449 SPR_NOACCESS, SPR_NOACCESS, 450 &spr_read_generic, &spr_write_generic, 451 0x00000000); 452 453 /* External access control */ 454 spr_register(env, SPR_EAR, "EAR", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, &spr_write_generic, 457 0x00000000); 458 /* Hardware implementation register */ 459 spr_register(env, SPR_HID0, "HID0", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 464 spr_register(env, SPR_HID1, "HID1", 465 SPR_NOACCESS, SPR_NOACCESS, 466 &spr_read_generic, &spr_write_generic, 467 0x00000000); 468 469 spr_register(env, SPR_HID2, "HID2", 470 SPR_NOACCESS, SPR_NOACCESS, 471 &spr_read_generic, &spr_write_generic, 472 0x00000000); 473 474 /* SGPRs */ 475 spr_register(env, SPR_SPRG4, "SPRG4", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 spr_register(env, SPR_SPRG5, "SPRG5", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 spr_register(env, SPR_SPRG6, "SPRG6", 484 SPR_NOACCESS, SPR_NOACCESS, 485 &spr_read_generic, &spr_write_generic, 486 0x00000000); 487 spr_register(env, SPR_SPRG7, "SPRG7", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 } 492 493 static void register_74xx_sprs(CPUPPCState *env) 494 { 495 /* Breakpoints */ 496 spr_register_kvm(env, SPR_DABR, "DABR", 497 SPR_NOACCESS, SPR_NOACCESS, 498 &spr_read_generic, &spr_write_generic, 499 KVM_REG_PPC_DABR, 0x00000000); 500 501 spr_register(env, SPR_IABR, "IABR", 502 SPR_NOACCESS, SPR_NOACCESS, 503 &spr_read_generic, &spr_write_generic, 504 0x00000000); 505 /* Cache management */ 506 spr_register(env, SPR_ICTC, "ICTC", 507 SPR_NOACCESS, SPR_NOACCESS, 508 &spr_read_generic, &spr_write_generic, 509 0x00000000); 510 /* Performance monitors */ 511 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 512 SPR_NOACCESS, SPR_NOACCESS, 513 &spr_read_generic, &spr_write_generic, 514 0x00000000); 515 516 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 517 SPR_NOACCESS, SPR_NOACCESS, 518 &spr_read_generic, &spr_write_generic, 519 0x00000000); 520 521 spr_register(env, SPR_7XX_PMC1, "PMC1", 522 SPR_NOACCESS, SPR_NOACCESS, 523 &spr_read_generic, &spr_write_generic, 524 0x00000000); 525 526 spr_register(env, SPR_7XX_PMC2, "PMC2", 527 SPR_NOACCESS, SPR_NOACCESS, 528 &spr_read_generic, &spr_write_generic, 529 0x00000000); 530 531 spr_register(env, SPR_7XX_PMC3, "PMC3", 532 SPR_NOACCESS, SPR_NOACCESS, 533 &spr_read_generic, &spr_write_generic, 534 0x00000000); 535 536 spr_register(env, SPR_7XX_PMC4, "PMC4", 537 SPR_NOACCESS, SPR_NOACCESS, 538 &spr_read_generic, &spr_write_generic, 539 0x00000000); 540 541 spr_register(env, SPR_7XX_SIAR, "SIAR", 542 SPR_NOACCESS, SPR_NOACCESS, 543 &spr_read_generic, SPR_NOACCESS, 544 0x00000000); 545 546 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 547 &spr_read_ureg, SPR_NOACCESS, 548 &spr_read_ureg, SPR_NOACCESS, 549 0x00000000); 550 551 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 552 &spr_read_ureg, SPR_NOACCESS, 553 &spr_read_ureg, SPR_NOACCESS, 554 0x00000000); 555 556 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 557 &spr_read_ureg, SPR_NOACCESS, 558 &spr_read_ureg, SPR_NOACCESS, 559 0x00000000); 560 561 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 562 &spr_read_ureg, SPR_NOACCESS, 563 &spr_read_ureg, SPR_NOACCESS, 564 0x00000000); 565 566 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 567 &spr_read_ureg, SPR_NOACCESS, 568 &spr_read_ureg, SPR_NOACCESS, 569 0x00000000); 570 571 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 572 &spr_read_ureg, SPR_NOACCESS, 573 &spr_read_ureg, SPR_NOACCESS, 574 0x00000000); 575 576 spr_register(env, SPR_7XX_USIAR, "USIAR", 577 &spr_read_ureg, SPR_NOACCESS, 578 &spr_read_ureg, SPR_NOACCESS, 579 0x00000000); 580 /* External access control */ 581 spr_register(env, SPR_EAR, "EAR", 582 SPR_NOACCESS, SPR_NOACCESS, 583 &spr_read_generic, &spr_write_generic, 584 0x00000000); 585 586 /* Processor identification */ 587 spr_register(env, SPR_PIR, "PIR", 588 SPR_NOACCESS, SPR_NOACCESS, 589 &spr_read_generic, &spr_write_pir, 590 0x00000000); 591 592 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 593 SPR_NOACCESS, SPR_NOACCESS, 594 &spr_read_generic, &spr_write_generic, 595 0x00000000); 596 597 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 598 &spr_read_ureg, SPR_NOACCESS, 599 &spr_read_ureg, SPR_NOACCESS, 600 0x00000000); 601 602 spr_register(env, SPR_BAMR, "BAMR", 603 SPR_NOACCESS, SPR_NOACCESS, 604 &spr_read_generic, &spr_write_generic, 605 0x00000000); 606 607 spr_register(env, SPR_MSSCR0, "MSSCR0", 608 SPR_NOACCESS, SPR_NOACCESS, 609 &spr_read_generic, &spr_write_generic, 610 0x00000000); 611 /* Hardware implementation registers */ 612 spr_register(env, SPR_HID0, "HID0", 613 SPR_NOACCESS, SPR_NOACCESS, 614 &spr_read_generic, &spr_write_generic, 615 0x00000000); 616 617 spr_register(env, SPR_HID1, "HID1", 618 SPR_NOACCESS, SPR_NOACCESS, 619 &spr_read_generic, &spr_write_generic, 620 0x00000000); 621 /* Altivec */ 622 spr_register(env, SPR_VRSAVE, "VRSAVE", 623 &spr_read_generic, &spr_write_generic, 624 &spr_read_generic, &spr_write_generic, 625 0x00000000); 626 627 spr_register(env, SPR_L2CR, "L2CR", 628 SPR_NOACCESS, SPR_NOACCESS, 629 &spr_read_generic, spr_access_nop, 630 0x00000000); 631 } 632 633 static void register_l3_ctrl(CPUPPCState *env) 634 { 635 /* L3CR */ 636 spr_register(env, SPR_L3CR, "L3CR", 637 SPR_NOACCESS, SPR_NOACCESS, 638 &spr_read_generic, &spr_write_generic, 639 0x00000000); 640 /* L3ITCR0 */ 641 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 642 SPR_NOACCESS, SPR_NOACCESS, 643 &spr_read_generic, &spr_write_generic, 644 0x00000000); 645 /* L3PM */ 646 spr_register(env, SPR_L3PM, "L3PM", 647 SPR_NOACCESS, SPR_NOACCESS, 648 &spr_read_generic, &spr_write_generic, 649 0x00000000); 650 } 651 652 /* PowerPC BookE SPR */ 653 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 654 { 655 const char *ivor_names[64] = { 656 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 657 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 658 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 659 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 660 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 661 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 662 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 663 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 664 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 665 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 666 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 667 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 668 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 669 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 670 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 671 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 672 }; 673 #define SPR_BOOKE_IVORxx (-1) 674 int ivor_sprn[64] = { 675 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 676 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 677 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 678 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 684 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 685 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 }; 692 int i; 693 694 /* Interrupt processing */ 695 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 700 SPR_NOACCESS, SPR_NOACCESS, 701 &spr_read_generic, &spr_write_generic, 702 0x00000000); 703 /* Debug */ 704 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 0x00000000); 708 709 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_40x_dbcr0, 727 0x00000000); 728 729 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, &spr_write_generic, 732 0x00000000); 733 734 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 739 SPR_NOACCESS, SPR_NOACCESS, 740 &spr_read_generic, &spr_write_generic, 741 0x00000000); 742 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 743 SPR_NOACCESS, SPR_NOACCESS, 744 &spr_read_generic, &spr_write_generic, 745 0x00000000); 746 747 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 748 SPR_NOACCESS, SPR_NOACCESS, 749 &spr_read_generic, &spr_write_clear, 750 0x00000000); 751 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 752 SPR_NOACCESS, SPR_NOACCESS, 753 &spr_read_generic, &spr_write_generic, 754 0x00000000); 755 spr_register(env, SPR_BOOKE_ESR, "ESR", 756 SPR_NOACCESS, SPR_NOACCESS, 757 &spr_read_generic, &spr_write_generic, 758 0x00000000); 759 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 760 SPR_NOACCESS, SPR_NOACCESS, 761 &spr_read_generic, &spr_write_excp_prefix, 762 0x00000000); 763 /* Exception vectors */ 764 for (i = 0; i < 64; i++) { 765 if (ivor_mask & (1ULL << i)) { 766 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 767 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 768 exit(1); 769 } 770 spr_register(env, ivor_sprn[i], ivor_names[i], 771 SPR_NOACCESS, SPR_NOACCESS, 772 &spr_read_generic, &spr_write_excp_vector, 773 0x00000000); 774 } 775 } 776 spr_register(env, SPR_BOOKE_PID, "PID", 777 SPR_NOACCESS, SPR_NOACCESS, 778 &spr_read_generic, &spr_write_booke_pid, 779 0x00000000); 780 spr_register(env, SPR_BOOKE_TCR, "TCR", 781 SPR_NOACCESS, SPR_NOACCESS, 782 &spr_read_generic, &spr_write_booke_tcr, 783 0x00000000); 784 spr_register(env, SPR_BOOKE_TSR, "TSR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_booke_tsr, 787 0x00000000); 788 /* Timer */ 789 spr_register(env, SPR_DECR, "DECR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_decr, &spr_write_decr, 792 0x00000000); 793 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 794 SPR_NOACCESS, SPR_NOACCESS, 795 SPR_NOACCESS, &spr_write_generic32, 796 0x00000000); 797 /* SPRGs */ 798 spr_register(env, SPR_USPRG0, "USPRG0", 799 &spr_read_generic, &spr_write_generic, 800 &spr_read_generic, &spr_write_generic, 801 0x00000000); 802 spr_register(env, SPR_SPRG4, "SPRG4", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 spr_register(env, SPR_SPRG5, "SPRG5", 807 SPR_NOACCESS, SPR_NOACCESS, 808 &spr_read_generic, &spr_write_generic, 809 0x00000000); 810 spr_register(env, SPR_SPRG6, "SPRG6", 811 SPR_NOACCESS, SPR_NOACCESS, 812 &spr_read_generic, &spr_write_generic, 813 0x00000000); 814 spr_register(env, SPR_SPRG7, "SPRG7", 815 SPR_NOACCESS, SPR_NOACCESS, 816 &spr_read_generic, &spr_write_generic, 817 0x00000000); 818 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 819 SPR_NOACCESS, SPR_NOACCESS, 820 &spr_read_generic, &spr_write_generic, 821 0x00000000); 822 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 823 SPR_NOACCESS, SPR_NOACCESS, 824 &spr_read_generic, &spr_write_generic, 825 0x00000000); 826 } 827 828 #if !defined(CONFIG_USER_ONLY) 829 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 830 uint32_t maxsize, uint32_t flags, 831 uint32_t nentries) 832 { 833 return (assoc << TLBnCFG_ASSOC_SHIFT) | 834 (minsize << TLBnCFG_MINSIZE_SHIFT) | 835 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 836 flags | nentries; 837 } 838 #endif /* !CONFIG_USER_ONLY */ 839 840 /* BookE 2.06 storage control registers */ 841 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 842 uint32_t *tlbncfg, uint32_t mmucfg) 843 { 844 #if !defined(CONFIG_USER_ONLY) 845 const char *mas_names[8] = { 846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 847 }; 848 int mas_sprn[8] = { 849 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 850 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 851 }; 852 int i; 853 854 /* TLB assist registers */ 855 for (i = 0; i < 8; i++) { 856 if (mas_mask & (1 << i)) { 857 spr_register(env, mas_sprn[i], mas_names[i], 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_generic, 860 (i == 2 && (env->insns_flags & PPC_64B)) 861 ? &spr_write_generic : &spr_write_generic32, 862 0x00000000); 863 } 864 } 865 if (env->nb_pids > 1) { 866 spr_register(env, SPR_BOOKE_PID1, "PID1", 867 SPR_NOACCESS, SPR_NOACCESS, 868 &spr_read_generic, &spr_write_booke_pid, 869 0x00000000); 870 } 871 if (env->nb_pids > 2) { 872 spr_register(env, SPR_BOOKE_PID2, "PID2", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_booke_pid, 875 0x00000000); 876 } 877 878 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 879 SPR_NOACCESS, SPR_NOACCESS, 880 &spr_read_generic, &spr_write_eplc, 881 0x00000000); 882 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 883 SPR_NOACCESS, SPR_NOACCESS, 884 &spr_read_generic, &spr_write_epsc, 885 0x00000000); 886 887 spr_register(env, SPR_MMUCFG, "MMUCFG", 888 SPR_NOACCESS, SPR_NOACCESS, 889 &spr_read_generic, SPR_NOACCESS, 890 mmucfg); 891 switch (env->nb_ways) { 892 case 4: 893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 894 SPR_NOACCESS, SPR_NOACCESS, 895 &spr_read_generic, SPR_NOACCESS, 896 tlbncfg[3]); 897 /* Fallthru */ 898 case 3: 899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 900 SPR_NOACCESS, SPR_NOACCESS, 901 &spr_read_generic, SPR_NOACCESS, 902 tlbncfg[2]); 903 /* Fallthru */ 904 case 2: 905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 906 SPR_NOACCESS, SPR_NOACCESS, 907 &spr_read_generic, SPR_NOACCESS, 908 tlbncfg[1]); 909 /* Fallthru */ 910 case 1: 911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, SPR_NOACCESS, 914 tlbncfg[0]); 915 /* Fallthru */ 916 case 0: 917 default: 918 break; 919 } 920 #endif 921 } 922 923 /* SPR specific to PowerPC 440 implementation */ 924 static void register_440_sprs(CPUPPCState *env) 925 { 926 /* Cache control */ 927 spr_register(env, SPR_440_DNV0, "DNV0", 928 SPR_NOACCESS, SPR_NOACCESS, 929 &spr_read_generic, &spr_write_generic, 930 0x00000000); 931 932 spr_register(env, SPR_440_DNV1, "DNV1", 933 SPR_NOACCESS, SPR_NOACCESS, 934 &spr_read_generic, &spr_write_generic, 935 0x00000000); 936 937 spr_register(env, SPR_440_DNV2, "DNV2", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 942 spr_register(env, SPR_440_DNV3, "DNV3", 943 SPR_NOACCESS, SPR_NOACCESS, 944 &spr_read_generic, &spr_write_generic, 945 0x00000000); 946 947 spr_register(env, SPR_440_DTV0, "DTV0", 948 SPR_NOACCESS, SPR_NOACCESS, 949 &spr_read_generic, &spr_write_generic, 950 0x00000000); 951 952 spr_register(env, SPR_440_DTV1, "DTV1", 953 SPR_NOACCESS, SPR_NOACCESS, 954 &spr_read_generic, &spr_write_generic, 955 0x00000000); 956 957 spr_register(env, SPR_440_DTV2, "DTV2", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 962 spr_register(env, SPR_440_DTV3, "DTV3", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 967 spr_register(env, SPR_440_DVLIM, "DVLIM", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 972 spr_register(env, SPR_440_INV0, "INV0", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_generic, 975 0x00000000); 976 977 spr_register(env, SPR_440_INV1, "INV1", 978 SPR_NOACCESS, SPR_NOACCESS, 979 &spr_read_generic, &spr_write_generic, 980 0x00000000); 981 982 spr_register(env, SPR_440_INV2, "INV2", 983 SPR_NOACCESS, SPR_NOACCESS, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 987 spr_register(env, SPR_440_INV3, "INV3", 988 SPR_NOACCESS, SPR_NOACCESS, 989 &spr_read_generic, &spr_write_generic, 990 0x00000000); 991 992 spr_register(env, SPR_440_ITV0, "ITV0", 993 SPR_NOACCESS, SPR_NOACCESS, 994 &spr_read_generic, &spr_write_generic, 995 0x00000000); 996 997 spr_register(env, SPR_440_ITV1, "ITV1", 998 SPR_NOACCESS, SPR_NOACCESS, 999 &spr_read_generic, &spr_write_generic, 1000 0x00000000); 1001 1002 spr_register(env, SPR_440_ITV2, "ITV2", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_generic, 1005 0x00000000); 1006 1007 spr_register(env, SPR_440_ITV3, "ITV3", 1008 SPR_NOACCESS, SPR_NOACCESS, 1009 &spr_read_generic, &spr_write_generic, 1010 0x00000000); 1011 1012 spr_register(env, SPR_440_IVLIM, "IVLIM", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 /* Cache debug */ 1017 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1018 SPR_NOACCESS, SPR_NOACCESS, 1019 &spr_read_generic, SPR_NOACCESS, 1020 0x00000000); 1021 1022 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1023 SPR_NOACCESS, SPR_NOACCESS, 1024 &spr_read_generic, SPR_NOACCESS, 1025 0x00000000); 1026 1027 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1028 SPR_NOACCESS, SPR_NOACCESS, 1029 &spr_read_generic, SPR_NOACCESS, 1030 0x00000000); 1031 1032 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1033 SPR_NOACCESS, SPR_NOACCESS, 1034 &spr_read_generic, SPR_NOACCESS, 1035 0x00000000); 1036 1037 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1038 SPR_NOACCESS, SPR_NOACCESS, 1039 &spr_read_generic, SPR_NOACCESS, 1040 0x00000000); 1041 1042 spr_register(env, SPR_440_DBDR, "DBDR", 1043 SPR_NOACCESS, SPR_NOACCESS, 1044 &spr_read_generic, &spr_write_generic, 1045 0x00000000); 1046 /* Processor control */ 1047 spr_register(env, SPR_4xx_CCR0, "CCR0", 1048 SPR_NOACCESS, SPR_NOACCESS, 1049 &spr_read_generic, &spr_write_generic, 1050 0x00000000); 1051 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1052 SPR_NOACCESS, SPR_NOACCESS, 1053 &spr_read_generic, SPR_NOACCESS, 1054 0x00000000); 1055 /* Storage control */ 1056 spr_register(env, SPR_440_MMUCR, "MMUCR", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_generic, 1059 0x00000000); 1060 1061 /* Processor identification */ 1062 spr_register(env, SPR_BOOKE_PIR, "PIR", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_pir, 1065 0x00000000); 1066 1067 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1068 SPR_NOACCESS, SPR_NOACCESS, 1069 &spr_read_generic, &spr_write_generic, 1070 0x00000000); 1071 1072 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1073 SPR_NOACCESS, SPR_NOACCESS, 1074 &spr_read_generic, &spr_write_generic, 1075 0x00000000); 1076 1077 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, &spr_write_generic, 1080 0x00000000); 1081 1082 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1083 SPR_NOACCESS, SPR_NOACCESS, 1084 &spr_read_generic, &spr_write_generic, 1085 0x00000000); 1086 } 1087 1088 /* SPR shared between PowerPC 40x implementations */ 1089 static void register_40x_sprs(CPUPPCState *env) 1090 { 1091 /* Cache */ 1092 /* not emulated, as QEMU do not emulate caches */ 1093 spr_register(env, SPR_40x_DCCR, "DCCR", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, &spr_write_generic, 1096 0x00000000); 1097 /* not emulated, as QEMU do not emulate caches */ 1098 spr_register(env, SPR_40x_ICCR, "ICCR", 1099 SPR_NOACCESS, SPR_NOACCESS, 1100 &spr_read_generic, &spr_write_generic, 1101 0x00000000); 1102 /* not emulated, as QEMU do not emulate caches */ 1103 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1104 SPR_NOACCESS, SPR_NOACCESS, 1105 &spr_read_generic, SPR_NOACCESS, 1106 0x00000000); 1107 /* Exception */ 1108 spr_register(env, SPR_40x_DEAR, "DEAR", 1109 SPR_NOACCESS, SPR_NOACCESS, 1110 &spr_read_generic, &spr_write_generic, 1111 0x00000000); 1112 spr_register(env, SPR_40x_ESR, "ESR", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_generic, 1115 0x00000000); 1116 spr_register(env, SPR_40x_EVPR, "EVPR", 1117 SPR_NOACCESS, SPR_NOACCESS, 1118 &spr_read_generic, &spr_write_excp_prefix, 1119 0x00000000); 1120 spr_register(env, SPR_40x_SRR2, "SRR2", 1121 &spr_read_generic, &spr_write_generic, 1122 &spr_read_generic, &spr_write_generic, 1123 0x00000000); 1124 spr_register(env, SPR_40x_SRR3, "SRR3", 1125 &spr_read_generic, &spr_write_generic, 1126 &spr_read_generic, &spr_write_generic, 1127 0x00000000); 1128 /* Timers */ 1129 spr_register(env, SPR_40x_PIT, "PIT", 1130 SPR_NOACCESS, SPR_NOACCESS, 1131 &spr_read_40x_pit, &spr_write_40x_pit, 1132 0x00000000); 1133 spr_register(env, SPR_40x_TCR, "TCR", 1134 SPR_NOACCESS, SPR_NOACCESS, 1135 &spr_read_generic, &spr_write_40x_tcr, 1136 0x00000000); 1137 spr_register(env, SPR_40x_TSR, "TSR", 1138 SPR_NOACCESS, SPR_NOACCESS, 1139 &spr_read_generic, &spr_write_40x_tsr, 1140 0x00000000); 1141 } 1142 1143 /* SPR specific to PowerPC 405 implementation */ 1144 static void register_405_sprs(CPUPPCState *env) 1145 { 1146 /* MMU */ 1147 spr_register(env, SPR_40x_PID, "PID", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_40x_pid, 1150 0x00000000); 1151 spr_register(env, SPR_4xx_CCR0, "CCR0", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_generic, 1154 0x00700000); 1155 /* Debug interface */ 1156 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1157 SPR_NOACCESS, SPR_NOACCESS, 1158 &spr_read_generic, &spr_write_40x_dbcr0, 1159 0x00000000); 1160 1161 spr_register(env, SPR_405_DBCR1, "DBCR1", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 1166 spr_register(env, SPR_40x_DBSR, "DBSR", 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_clear, 1169 /* Last reset was system reset */ 1170 0x00000300); 1171 1172 spr_register(env, SPR_40x_DAC1, "DAC1", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 spr_register(env, SPR_40x_DAC2, "DAC2", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_generic, 1179 0x00000000); 1180 1181 spr_register(env, SPR_405_DVC1, "DVC1", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, &spr_write_generic, 1184 0x00000000); 1185 1186 spr_register(env, SPR_405_DVC2, "DVC2", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, &spr_write_generic, 1189 0x00000000); 1190 1191 spr_register(env, SPR_40x_IAC1, "IAC1", 1192 SPR_NOACCESS, SPR_NOACCESS, 1193 &spr_read_generic, &spr_write_generic, 1194 0x00000000); 1195 spr_register(env, SPR_40x_IAC2, "IAC2", 1196 SPR_NOACCESS, SPR_NOACCESS, 1197 &spr_read_generic, &spr_write_generic, 1198 0x00000000); 1199 1200 spr_register(env, SPR_405_IAC3, "IAC3", 1201 SPR_NOACCESS, SPR_NOACCESS, 1202 &spr_read_generic, &spr_write_generic, 1203 0x00000000); 1204 1205 spr_register(env, SPR_405_IAC4, "IAC4", 1206 SPR_NOACCESS, SPR_NOACCESS, 1207 &spr_read_generic, &spr_write_generic, 1208 0x00000000); 1209 /* Storage control */ 1210 spr_register(env, SPR_405_SLER, "SLER", 1211 SPR_NOACCESS, SPR_NOACCESS, 1212 &spr_read_generic, &spr_write_40x_sler, 1213 0x00000000); 1214 spr_register(env, SPR_40x_ZPR, "ZPR", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 1219 spr_register(env, SPR_405_SU0R, "SU0R", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_generic, 1222 0x00000000); 1223 /* SPRG */ 1224 spr_register(env, SPR_USPRG0, "USPRG0", 1225 &spr_read_ureg, SPR_NOACCESS, 1226 &spr_read_ureg, SPR_NOACCESS, 1227 0x00000000); 1228 spr_register(env, SPR_SPRG4, "SPRG4", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 spr_register(env, SPR_SPRG5, "SPRG5", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 spr_read_generic, &spr_write_generic, 1235 0x00000000); 1236 spr_register(env, SPR_SPRG6, "SPRG6", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 spr_read_generic, &spr_write_generic, 1239 0x00000000); 1240 spr_register(env, SPR_SPRG7, "SPRG7", 1241 SPR_NOACCESS, SPR_NOACCESS, 1242 spr_read_generic, &spr_write_generic, 1243 0x00000000); 1244 1245 /* Bus access control */ 1246 /* not emulated, as QEMU never does speculative access */ 1247 spr_register(env, SPR_40x_SGR, "SGR", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, &spr_write_generic, 1250 0xFFFFFFFF); 1251 /* not emulated, as QEMU do not emulate caches */ 1252 spr_register(env, SPR_40x_DCWR, "DCWR", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_generic, 1255 0x00000000); 1256 } 1257 1258 1259 static void register_5xx_8xx_sprs(CPUPPCState *env) 1260 { 1261 /* Exception processing */ 1262 spr_register_kvm(env, SPR_DSISR, "DSISR", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 KVM_REG_PPC_DSISR, 0x00000000); 1266 spr_register_kvm(env, SPR_DAR, "DAR", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 KVM_REG_PPC_DAR, 0x00000000); 1270 /* Timer */ 1271 spr_register(env, SPR_DECR, "DECR", 1272 SPR_NOACCESS, SPR_NOACCESS, 1273 &spr_read_decr, &spr_write_decr, 1274 0x00000000); 1275 1276 spr_register(env, SPR_MPC_EIE, "EIE", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_generic, 1279 0x00000000); 1280 1281 spr_register(env, SPR_MPC_EID, "EID", 1282 SPR_NOACCESS, SPR_NOACCESS, 1283 &spr_read_generic, &spr_write_generic, 1284 0x00000000); 1285 1286 spr_register(env, SPR_MPC_NRI, "NRI", 1287 SPR_NOACCESS, SPR_NOACCESS, 1288 &spr_read_generic, &spr_write_generic, 1289 0x00000000); 1290 1291 spr_register(env, SPR_MPC_CMPA, "CMPA", 1292 SPR_NOACCESS, SPR_NOACCESS, 1293 &spr_read_generic, &spr_write_generic, 1294 0x00000000); 1295 1296 spr_register(env, SPR_MPC_CMPB, "CMPB", 1297 SPR_NOACCESS, SPR_NOACCESS, 1298 &spr_read_generic, &spr_write_generic, 1299 0x00000000); 1300 1301 spr_register(env, SPR_MPC_CMPC, "CMPC", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, &spr_write_generic, 1304 0x00000000); 1305 1306 spr_register(env, SPR_MPC_CMPD, "CMPD", 1307 SPR_NOACCESS, SPR_NOACCESS, 1308 &spr_read_generic, &spr_write_generic, 1309 0x00000000); 1310 1311 spr_register(env, SPR_MPC_ECR, "ECR", 1312 SPR_NOACCESS, SPR_NOACCESS, 1313 &spr_read_generic, &spr_write_generic, 1314 0x00000000); 1315 1316 spr_register(env, SPR_MPC_DER, "DER", 1317 SPR_NOACCESS, SPR_NOACCESS, 1318 &spr_read_generic, &spr_write_generic, 1319 0x00000000); 1320 1321 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_generic, 1324 0x00000000); 1325 1326 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_generic, 1329 0x00000000); 1330 1331 spr_register(env, SPR_MPC_CMPE, "CMPE", 1332 SPR_NOACCESS, SPR_NOACCESS, 1333 &spr_read_generic, &spr_write_generic, 1334 0x00000000); 1335 1336 spr_register(env, SPR_MPC_CMPF, "CMPF", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_generic, 1339 0x00000000); 1340 1341 spr_register(env, SPR_MPC_CMPG, "CMPG", 1342 SPR_NOACCESS, SPR_NOACCESS, 1343 &spr_read_generic, &spr_write_generic, 1344 0x00000000); 1345 1346 spr_register(env, SPR_MPC_CMPH, "CMPH", 1347 SPR_NOACCESS, SPR_NOACCESS, 1348 &spr_read_generic, &spr_write_generic, 1349 0x00000000); 1350 1351 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, &spr_write_generic, 1354 0x00000000); 1355 1356 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, &spr_write_generic, 1359 0x00000000); 1360 1361 spr_register(env, SPR_MPC_BAR, "BAR", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, &spr_write_generic, 1364 0x00000000); 1365 1366 spr_register(env, SPR_MPC_DPDR, "DPDR", 1367 SPR_NOACCESS, SPR_NOACCESS, 1368 &spr_read_generic, &spr_write_generic, 1369 0x00000000); 1370 1371 spr_register(env, SPR_MPC_IMMR, "IMMR", 1372 SPR_NOACCESS, SPR_NOACCESS, 1373 &spr_read_generic, &spr_write_generic, 1374 0x00000000); 1375 } 1376 1377 static void register_5xx_sprs(CPUPPCState *env) 1378 { 1379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 1384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 1389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, &spr_write_generic, 1392 0x00000000); 1393 1394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, &spr_write_generic, 1397 0x00000000); 1398 1399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1400 SPR_NOACCESS, SPR_NOACCESS, 1401 &spr_read_generic, &spr_write_generic, 1402 0x00000000); 1403 1404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1405 SPR_NOACCESS, SPR_NOACCESS, 1406 &spr_read_generic, &spr_write_generic, 1407 0x00000000); 1408 1409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1410 SPR_NOACCESS, SPR_NOACCESS, 1411 &spr_read_generic, &spr_write_generic, 1412 0x00000000); 1413 1414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1415 SPR_NOACCESS, SPR_NOACCESS, 1416 &spr_read_generic, &spr_write_generic, 1417 0x00000000); 1418 1419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1420 SPR_NOACCESS, SPR_NOACCESS, 1421 &spr_read_generic, &spr_write_generic, 1422 0x00000000); 1423 1424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 &spr_read_generic, &spr_write_generic, 1427 0x00000000); 1428 1429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 &spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 1434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1435 SPR_NOACCESS, SPR_NOACCESS, 1436 &spr_read_generic, &spr_write_generic, 1437 0x00000000); 1438 1439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1440 SPR_NOACCESS, SPR_NOACCESS, 1441 &spr_read_generic, &spr_write_generic, 1442 0x00000000); 1443 1444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, &spr_write_generic, 1447 0x00000000); 1448 1449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, &spr_write_generic, 1452 0x00000000); 1453 1454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1455 SPR_NOACCESS, SPR_NOACCESS, 1456 &spr_read_generic, &spr_write_generic, 1457 0x00000000); 1458 1459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00000000); 1463 1464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1465 SPR_NOACCESS, SPR_NOACCESS, 1466 &spr_read_generic, &spr_write_generic, 1467 0x00000000); 1468 1469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1470 SPR_NOACCESS, SPR_NOACCESS, 1471 &spr_read_generic, &spr_write_generic, 1472 0x00000000); 1473 1474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1475 SPR_NOACCESS, SPR_NOACCESS, 1476 &spr_read_generic, &spr_write_generic, 1477 0x00000000); 1478 1479 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1480 SPR_NOACCESS, SPR_NOACCESS, 1481 &spr_read_generic, &spr_write_generic, 1482 0x00000000); 1483 } 1484 1485 static void register_8xx_sprs(CPUPPCState *env) 1486 { 1487 1488 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1489 SPR_NOACCESS, SPR_NOACCESS, 1490 &spr_read_generic, &spr_write_generic, 1491 0x00000000); 1492 1493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_generic, 1496 0x00000000); 1497 1498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 &spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 1503 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, &spr_write_generic, 1506 0x00000000); 1507 1508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 1513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 0x00000000); 1517 1518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1519 SPR_NOACCESS, SPR_NOACCESS, 1520 &spr_read_generic, &spr_write_generic, 1521 0x00000000); 1522 1523 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1524 SPR_NOACCESS, SPR_NOACCESS, 1525 &spr_read_generic, &spr_write_generic, 1526 0x00000000); 1527 1528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_generic, 1531 0x00000000); 1532 1533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_generic, 1536 0x00000000); 1537 1538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 1543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_generic, 1546 0x00000000); 1547 1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1549 SPR_NOACCESS, SPR_NOACCESS, 1550 &spr_read_generic, &spr_write_generic, 1551 0x00000000); 1552 1553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1554 SPR_NOACCESS, SPR_NOACCESS, 1555 &spr_read_generic, &spr_write_generic, 1556 0x00000000); 1557 1558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1559 SPR_NOACCESS, SPR_NOACCESS, 1560 &spr_read_generic, &spr_write_generic, 1561 0x00000000); 1562 1563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 1568 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 1578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 &spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 1583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1584 SPR_NOACCESS, SPR_NOACCESS, 1585 &spr_read_generic, &spr_write_generic, 1586 0x00000000); 1587 1588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1589 SPR_NOACCESS, SPR_NOACCESS, 1590 &spr_read_generic, &spr_write_generic, 1591 0x00000000); 1592 1593 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 &spr_read_generic, &spr_write_generic, 1596 0x00000000); 1597 1598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 1603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00000000); 1607 1608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_generic, 1611 0x00000000); 1612 } 1613 1614 /* 1615 * AMR => SPR 29 (Power 2.04) 1616 * CTRL => SPR 136 (Power 2.04) 1617 * CTRL => SPR 152 (Power 2.04) 1618 * SCOMC => SPR 276 (64 bits ?) 1619 * SCOMD => SPR 277 (64 bits ?) 1620 * TBU40 => SPR 286 (Power 2.04 hypv) 1621 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1622 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1623 * HDSISR => SPR 306 (Power 2.04 hypv) 1624 * HDAR => SPR 307 (Power 2.04 hypv) 1625 * PURR => SPR 309 (Power 2.04 hypv) 1626 * HDEC => SPR 310 (Power 2.04 hypv) 1627 * HIOR => SPR 311 (hypv) 1628 * RMOR => SPR 312 (970) 1629 * HRMOR => SPR 313 (Power 2.04 hypv) 1630 * HSRR0 => SPR 314 (Power 2.04 hypv) 1631 * HSRR1 => SPR 315 (Power 2.04 hypv) 1632 * LPIDR => SPR 317 (970) 1633 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1634 * EPR => SPR 702 (Power 2.04 emb) 1635 * perf => 768-783 (Power 2.04) 1636 * perf => 784-799 (Power 2.04) 1637 * PPR => SPR 896 (Power 2.04) 1638 * DABRX => 1015 (Power 2.04 hypv) 1639 * FPECR => SPR 1022 (?) 1640 * ... and more (thermal management, performance counters, ...) 1641 */ 1642 1643 /*****************************************************************************/ 1644 /* Exception vectors models */ 1645 static void init_excp_4xx(CPUPPCState *env) 1646 { 1647 #if !defined(CONFIG_USER_ONLY) 1648 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1649 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1650 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1651 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1652 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1653 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1654 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1655 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1656 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1657 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1658 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1659 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1660 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1661 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1662 env->ivor_mask = 0x0000FFF0UL; 1663 env->ivpr_mask = 0xFFFF0000UL; 1664 /* Hardware reset vector */ 1665 env->hreset_vector = 0xFFFFFFFCUL; 1666 #endif 1667 } 1668 1669 static void init_excp_MPC5xx(CPUPPCState *env) 1670 { 1671 #if !defined(CONFIG_USER_ONLY) 1672 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1673 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1683 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1684 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1685 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1686 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1687 env->ivor_mask = 0x0000FFF0UL; 1688 env->ivpr_mask = 0xFFFF0000UL; 1689 /* Hardware reset vector */ 1690 env->hreset_vector = 0x00000100UL; 1691 #endif 1692 } 1693 1694 static void init_excp_MPC8xx(CPUPPCState *env) 1695 { 1696 #if !defined(CONFIG_USER_ONLY) 1697 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1698 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1699 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1700 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1701 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1702 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1703 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1704 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1705 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1706 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1707 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1708 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1709 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1710 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1712 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1713 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1714 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1715 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1716 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1717 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1718 env->ivor_mask = 0x0000FFF0UL; 1719 env->ivpr_mask = 0xFFFF0000UL; 1720 /* Hardware reset vector */ 1721 env->hreset_vector = 0x00000100UL; 1722 #endif 1723 } 1724 1725 static void init_excp_G2(CPUPPCState *env) 1726 { 1727 #if !defined(CONFIG_USER_ONLY) 1728 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1729 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1730 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1731 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1732 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1733 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1734 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1735 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1736 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1737 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1738 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1739 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1740 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1741 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1742 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1743 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1744 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1745 /* Hardware reset vector */ 1746 env->hreset_vector = 0x00000100UL; 1747 #endif 1748 } 1749 1750 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1751 { 1752 #if !defined(CONFIG_USER_ONLY) 1753 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1754 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1755 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1756 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1757 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1758 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1759 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1760 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1761 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1763 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1764 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1765 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1766 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1767 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1768 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1770 /* 1771 * These two are the same IVOR as POWERPC_EXCP_VPU and 1772 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1773 * powerpc_excp(). 1774 */ 1775 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1776 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1777 1778 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1779 env->ivor_mask = 0x0000FFF7UL; 1780 env->ivpr_mask = ivpr_mask; 1781 /* Hardware reset vector */ 1782 env->hreset_vector = 0xFFFFFFFCUL; 1783 #endif 1784 } 1785 1786 static void init_excp_BookE(CPUPPCState *env) 1787 { 1788 #if !defined(CONFIG_USER_ONLY) 1789 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1790 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1791 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1792 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1793 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1794 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1795 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1796 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1798 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1799 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1800 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1801 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1802 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1803 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1805 env->ivor_mask = 0x0000FFF0UL; 1806 env->ivpr_mask = 0xFFFF0000UL; 1807 /* Hardware reset vector */ 1808 env->hreset_vector = 0xFFFFFFFCUL; 1809 #endif 1810 } 1811 1812 static void init_excp_603(CPUPPCState *env) 1813 { 1814 #if !defined(CONFIG_USER_ONLY) 1815 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1816 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1817 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1818 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1822 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1823 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1824 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1825 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1826 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1827 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1828 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1829 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1830 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1831 /* Hardware reset vector */ 1832 env->hreset_vector = 0x00000100UL; 1833 #endif 1834 } 1835 1836 static void init_excp_604(CPUPPCState *env) 1837 { 1838 #if !defined(CONFIG_USER_ONLY) 1839 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1840 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1841 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1842 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1843 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1844 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1845 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1846 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1849 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1850 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1851 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1852 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1853 /* Hardware reset vector */ 1854 env->hreset_vector = 0x00000100UL; 1855 #endif 1856 } 1857 1858 static void init_excp_7x0(CPUPPCState *env) 1859 { 1860 #if !defined(CONFIG_USER_ONLY) 1861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1872 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1873 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1874 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1875 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1876 /* Hardware reset vector */ 1877 env->hreset_vector = 0x00000100UL; 1878 #endif 1879 } 1880 1881 static void init_excp_750cl(CPUPPCState *env) 1882 { 1883 #if !defined(CONFIG_USER_ONLY) 1884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1898 /* Hardware reset vector */ 1899 env->hreset_vector = 0x00000100UL; 1900 #endif 1901 } 1902 1903 static void init_excp_750cx(CPUPPCState *env) 1904 { 1905 #if !defined(CONFIG_USER_ONLY) 1906 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1907 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1908 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1909 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1910 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1911 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1912 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1913 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1914 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1916 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1917 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1918 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1919 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1920 /* Hardware reset vector */ 1921 env->hreset_vector = 0x00000100UL; 1922 #endif 1923 } 1924 1925 /* XXX: Check if this is correct */ 1926 static void init_excp_7x5(CPUPPCState *env) 1927 { 1928 #if !defined(CONFIG_USER_ONLY) 1929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1941 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1942 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1943 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1944 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1945 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1946 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1947 /* Hardware reset vector */ 1948 env->hreset_vector = 0x00000100UL; 1949 #endif 1950 } 1951 1952 static void init_excp_7400(CPUPPCState *env) 1953 { 1954 #if !defined(CONFIG_USER_ONLY) 1955 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1956 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1957 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1958 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1959 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1960 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1961 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1962 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1963 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1964 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1965 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1966 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1967 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1968 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1969 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1970 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1971 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1972 /* Hardware reset vector */ 1973 env->hreset_vector = 0x00000100UL; 1974 #endif 1975 } 1976 1977 static void init_excp_7450(CPUPPCState *env) 1978 { 1979 #if !defined(CONFIG_USER_ONLY) 1980 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1981 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1982 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1983 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1984 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1985 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1986 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1987 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1988 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1991 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1992 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1993 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1994 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1995 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1996 /* Hardware reset vector */ 1997 env->hreset_vector = 0x00000100UL; 1998 #endif 1999 } 2000 2001 #if defined(TARGET_PPC64) 2002 static void init_excp_970(CPUPPCState *env) 2003 { 2004 #if !defined(CONFIG_USER_ONLY) 2005 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2008 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2009 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2010 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2011 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2012 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2013 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2014 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2016 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2020 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2021 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2022 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2023 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2024 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2025 /* Hardware reset vector */ 2026 env->hreset_vector = 0x0000000000000100ULL; 2027 #endif 2028 } 2029 2030 static void init_excp_POWER7(CPUPPCState *env) 2031 { 2032 #if !defined(CONFIG_USER_ONLY) 2033 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2034 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2035 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2036 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2037 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2038 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2044 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2047 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2048 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2049 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2050 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2051 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2052 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2053 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2054 /* Hardware reset vector */ 2055 env->hreset_vector = 0x0000000000000100ULL; 2056 #endif 2057 } 2058 2059 static void init_excp_POWER8(CPUPPCState *env) 2060 { 2061 init_excp_POWER7(env); 2062 2063 #if !defined(CONFIG_USER_ONLY) 2064 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2065 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2066 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2067 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2068 2069 /* Userland exceptions without vector value in PowerISA v3.1 */ 2070 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2071 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2072 #endif 2073 } 2074 2075 static void init_excp_POWER9(CPUPPCState *env) 2076 { 2077 init_excp_POWER8(env); 2078 2079 #if !defined(CONFIG_USER_ONLY) 2080 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2081 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2082 #endif 2083 } 2084 2085 static void init_excp_POWER10(CPUPPCState *env) 2086 { 2087 init_excp_POWER9(env); 2088 } 2089 2090 #endif 2091 2092 static int check_pow_hid0(CPUPPCState *env) 2093 { 2094 if (env->spr[SPR_HID0] & 0x00E00000) { 2095 return 1; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int check_pow_hid0_74xx(CPUPPCState *env) 2102 { 2103 if (env->spr[SPR_HID0] & 0x00600000) { 2104 return 1; 2105 } 2106 2107 return 0; 2108 } 2109 2110 #if defined(TARGET_PPC64) 2111 static int check_attn_hid0(CPUPPCState *env) 2112 { 2113 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2114 return 1; 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int check_attn_hid0_power9(CPUPPCState *env) 2121 { 2122 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2123 return 1; 2124 } 2125 2126 return 0; 2127 } 2128 #endif 2129 2130 static void init_tlbs_emb(CPUPPCState *env) 2131 { 2132 #ifndef CONFIG_USER_ONLY 2133 env->nb_tlb = 64; 2134 env->nb_ways = 1; 2135 env->tlb_type = TLB_EMB; 2136 #endif 2137 } 2138 2139 static void init_proc_405(CPUPPCState *env) 2140 { 2141 register_40x_sprs(env); 2142 register_405_sprs(env); 2143 register_usprgh_sprs(env); 2144 2145 init_tlbs_emb(env); 2146 init_excp_4xx(env); 2147 env->dcache_line_size = 32; 2148 env->icache_line_size = 32; 2149 /* Allocate hardware IRQ controller */ 2150 ppc40x_irq_init(env_archcpu(env)); 2151 2152 SET_FIT_PERIOD(8, 12, 16, 20); 2153 SET_WDT_PERIOD(16, 20, 24, 28); 2154 } 2155 2156 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2157 { 2158 DeviceClass *dc = DEVICE_CLASS(oc); 2159 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2160 2161 dc->desc = "PowerPC 405"; 2162 pcc->init_proc = init_proc_405; 2163 pcc->check_pow = check_pow_nocheck; 2164 pcc->check_attn = check_attn_none; 2165 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2166 PPC_DCR | PPC_WRTEE | 2167 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2168 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2169 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2170 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2171 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2172 pcc->msr_mask = (1ull << MSR_WE) | 2173 (1ull << MSR_CE) | 2174 (1ull << MSR_EE) | 2175 (1ull << MSR_PR) | 2176 (1ull << MSR_FP) | 2177 (1ull << MSR_ME) | 2178 (1ull << MSR_DWE) | 2179 (1ull << MSR_DE) | 2180 (1ull << MSR_IR) | 2181 (1ull << MSR_DR); 2182 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2183 pcc->excp_model = POWERPC_EXCP_40x; 2184 pcc->bus_model = PPC_FLAGS_INPUT_405; 2185 pcc->bfd_mach = bfd_mach_ppc_403; 2186 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2187 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2188 } 2189 2190 static void init_proc_440EP(CPUPPCState *env) 2191 { 2192 register_BookE_sprs(env, 0x000000000000FFFFULL); 2193 register_440_sprs(env); 2194 register_usprgh_sprs(env); 2195 2196 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2197 SPR_NOACCESS, SPR_NOACCESS, 2198 &spr_read_generic, &spr_write_generic, 2199 0x00000000); 2200 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2201 SPR_NOACCESS, SPR_NOACCESS, 2202 &spr_read_generic, &spr_write_generic, 2203 0x00000000); 2204 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2205 SPR_NOACCESS, SPR_NOACCESS, 2206 &spr_read_generic, &spr_write_generic, 2207 0x00000000); 2208 2209 spr_register(env, SPR_440_CCR1, "CCR1", 2210 SPR_NOACCESS, SPR_NOACCESS, 2211 &spr_read_generic, &spr_write_generic, 2212 0x00000000); 2213 2214 init_tlbs_emb(env); 2215 init_excp_BookE(env); 2216 env->dcache_line_size = 32; 2217 env->icache_line_size = 32; 2218 ppc40x_irq_init(env_archcpu(env)); 2219 2220 SET_FIT_PERIOD(12, 16, 20, 24); 2221 SET_WDT_PERIOD(20, 24, 28, 32); 2222 } 2223 2224 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2225 { 2226 DeviceClass *dc = DEVICE_CLASS(oc); 2227 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2228 2229 dc->desc = "PowerPC 440 EP"; 2230 pcc->init_proc = init_proc_440EP; 2231 pcc->check_pow = check_pow_nocheck; 2232 pcc->check_attn = check_attn_none; 2233 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2234 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2235 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2236 PPC_FLOAT_STFIWX | 2237 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2238 PPC_CACHE | PPC_CACHE_ICBI | 2239 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2240 PPC_MEM_TLBSYNC | PPC_MFTB | 2241 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2242 PPC_440_SPEC; 2243 pcc->msr_mask = (1ull << MSR_POW) | 2244 (1ull << MSR_CE) | 2245 (1ull << MSR_EE) | 2246 (1ull << MSR_PR) | 2247 (1ull << MSR_FP) | 2248 (1ull << MSR_ME) | 2249 (1ull << MSR_FE0) | 2250 (1ull << MSR_DWE) | 2251 (1ull << MSR_DE) | 2252 (1ull << MSR_FE1) | 2253 (1ull << MSR_IR) | 2254 (1ull << MSR_DR); 2255 pcc->mmu_model = POWERPC_MMU_BOOKE; 2256 pcc->excp_model = POWERPC_EXCP_BOOKE; 2257 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2258 pcc->bfd_mach = bfd_mach_ppc_403; 2259 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2260 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2261 } 2262 2263 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2264 { 2265 DeviceClass *dc = DEVICE_CLASS(oc); 2266 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2267 2268 dc->desc = "PowerPC 460 EX"; 2269 pcc->init_proc = init_proc_440EP; 2270 pcc->check_pow = check_pow_nocheck; 2271 pcc->check_attn = check_attn_none; 2272 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2273 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2274 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2275 PPC_FLOAT_STFIWX | 2276 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2277 PPC_CACHE | PPC_CACHE_ICBI | 2278 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2279 PPC_MEM_TLBSYNC | PPC_MFTB | 2280 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2281 PPC_440_SPEC; 2282 pcc->msr_mask = (1ull << MSR_POW) | 2283 (1ull << MSR_CE) | 2284 (1ull << MSR_EE) | 2285 (1ull << MSR_PR) | 2286 (1ull << MSR_FP) | 2287 (1ull << MSR_ME) | 2288 (1ull << MSR_FE0) | 2289 (1ull << MSR_DWE) | 2290 (1ull << MSR_DE) | 2291 (1ull << MSR_FE1) | 2292 (1ull << MSR_IR) | 2293 (1ull << MSR_DR); 2294 pcc->mmu_model = POWERPC_MMU_BOOKE; 2295 pcc->excp_model = POWERPC_EXCP_BOOKE; 2296 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2297 pcc->bfd_mach = bfd_mach_ppc_403; 2298 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2299 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2300 } 2301 2302 static void init_proc_440GP(CPUPPCState *env) 2303 { 2304 register_BookE_sprs(env, 0x000000000000FFFFULL); 2305 register_440_sprs(env); 2306 register_usprgh_sprs(env); 2307 2308 init_tlbs_emb(env); 2309 init_excp_BookE(env); 2310 env->dcache_line_size = 32; 2311 env->icache_line_size = 32; 2312 /* XXX: TODO: allocate internal IRQ controller */ 2313 2314 SET_FIT_PERIOD(12, 16, 20, 24); 2315 SET_WDT_PERIOD(20, 24, 28, 32); 2316 } 2317 2318 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2319 { 2320 DeviceClass *dc = DEVICE_CLASS(oc); 2321 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2322 2323 dc->desc = "PowerPC 440 GP"; 2324 pcc->init_proc = init_proc_440GP; 2325 pcc->check_pow = check_pow_nocheck; 2326 pcc->check_attn = check_attn_none; 2327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2328 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2329 PPC_CACHE | PPC_CACHE_ICBI | 2330 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2331 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2332 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2333 PPC_440_SPEC; 2334 pcc->msr_mask = (1ull << MSR_POW) | 2335 (1ull << MSR_CE) | 2336 (1ull << MSR_EE) | 2337 (1ull << MSR_PR) | 2338 (1ull << MSR_FP) | 2339 (1ull << MSR_ME) | 2340 (1ull << MSR_FE0) | 2341 (1ull << MSR_DWE) | 2342 (1ull << MSR_DE) | 2343 (1ull << MSR_FE1) | 2344 (1ull << MSR_IR) | 2345 (1ull << MSR_DR); 2346 pcc->mmu_model = POWERPC_MMU_BOOKE; 2347 pcc->excp_model = POWERPC_EXCP_BOOKE; 2348 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2349 pcc->bfd_mach = bfd_mach_ppc_403; 2350 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2351 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2352 } 2353 2354 static void init_proc_440x5(CPUPPCState *env) 2355 { 2356 register_BookE_sprs(env, 0x000000000000FFFFULL); 2357 register_440_sprs(env); 2358 register_usprgh_sprs(env); 2359 2360 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2361 SPR_NOACCESS, SPR_NOACCESS, 2362 &spr_read_generic, &spr_write_generic, 2363 0x00000000); 2364 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2365 SPR_NOACCESS, SPR_NOACCESS, 2366 &spr_read_generic, &spr_write_generic, 2367 0x00000000); 2368 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2369 SPR_NOACCESS, SPR_NOACCESS, 2370 &spr_read_generic, &spr_write_generic, 2371 0x00000000); 2372 2373 spr_register(env, SPR_440_CCR1, "CCR1", 2374 SPR_NOACCESS, SPR_NOACCESS, 2375 &spr_read_generic, &spr_write_generic, 2376 0x00000000); 2377 2378 init_tlbs_emb(env); 2379 init_excp_BookE(env); 2380 env->dcache_line_size = 32; 2381 env->icache_line_size = 32; 2382 ppc40x_irq_init(env_archcpu(env)); 2383 2384 SET_FIT_PERIOD(12, 16, 20, 24); 2385 SET_WDT_PERIOD(20, 24, 28, 32); 2386 } 2387 2388 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2389 { 2390 DeviceClass *dc = DEVICE_CLASS(oc); 2391 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2392 2393 dc->desc = "PowerPC 440x5"; 2394 pcc->init_proc = init_proc_440x5; 2395 pcc->check_pow = check_pow_nocheck; 2396 pcc->check_attn = check_attn_none; 2397 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2398 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2399 PPC_CACHE | PPC_CACHE_ICBI | 2400 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2401 PPC_MEM_TLBSYNC | PPC_MFTB | 2402 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2403 PPC_440_SPEC; 2404 pcc->msr_mask = (1ull << MSR_POW) | 2405 (1ull << MSR_CE) | 2406 (1ull << MSR_EE) | 2407 (1ull << MSR_PR) | 2408 (1ull << MSR_FP) | 2409 (1ull << MSR_ME) | 2410 (1ull << MSR_FE0) | 2411 (1ull << MSR_DWE) | 2412 (1ull << MSR_DE) | 2413 (1ull << MSR_FE1) | 2414 (1ull << MSR_IR) | 2415 (1ull << MSR_DR); 2416 pcc->mmu_model = POWERPC_MMU_BOOKE; 2417 pcc->excp_model = POWERPC_EXCP_BOOKE; 2418 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2419 pcc->bfd_mach = bfd_mach_ppc_403; 2420 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2421 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2422 } 2423 2424 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2425 { 2426 DeviceClass *dc = DEVICE_CLASS(oc); 2427 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2428 2429 dc->desc = "PowerPC 440x5 with double precision FPU"; 2430 pcc->init_proc = init_proc_440x5; 2431 pcc->check_pow = check_pow_nocheck; 2432 pcc->check_attn = check_attn_none; 2433 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2434 PPC_FLOAT | PPC_FLOAT_FSQRT | 2435 PPC_FLOAT_STFIWX | 2436 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2437 PPC_CACHE | PPC_CACHE_ICBI | 2438 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2439 PPC_MEM_TLBSYNC | PPC_MFTB | 2440 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2441 PPC_440_SPEC; 2442 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2443 pcc->msr_mask = (1ull << MSR_POW) | 2444 (1ull << MSR_CE) | 2445 (1ull << MSR_EE) | 2446 (1ull << MSR_PR) | 2447 (1ull << MSR_FP) | 2448 (1ull << MSR_ME) | 2449 (1ull << MSR_FE0) | 2450 (1ull << MSR_DWE) | 2451 (1ull << MSR_DE) | 2452 (1ull << MSR_FE1) | 2453 (1ull << MSR_IR) | 2454 (1ull << MSR_DR); 2455 pcc->mmu_model = POWERPC_MMU_BOOKE; 2456 pcc->excp_model = POWERPC_EXCP_BOOKE; 2457 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2458 pcc->bfd_mach = bfd_mach_ppc_403; 2459 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2460 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2461 } 2462 2463 static void init_proc_MPC5xx(CPUPPCState *env) 2464 { 2465 register_5xx_8xx_sprs(env); 2466 register_5xx_sprs(env); 2467 init_excp_MPC5xx(env); 2468 env->dcache_line_size = 32; 2469 env->icache_line_size = 32; 2470 /* XXX: TODO: allocate internal IRQ controller */ 2471 } 2472 2473 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2474 { 2475 DeviceClass *dc = DEVICE_CLASS(oc); 2476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2477 2478 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2479 pcc->init_proc = init_proc_MPC5xx; 2480 pcc->check_pow = check_pow_none; 2481 pcc->check_attn = check_attn_none; 2482 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2483 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2484 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2485 PPC_MFTB; 2486 pcc->msr_mask = (1ull << MSR_ILE) | 2487 (1ull << MSR_EE) | 2488 (1ull << MSR_PR) | 2489 (1ull << MSR_FP) | 2490 (1ull << MSR_ME) | 2491 (1ull << MSR_FE0) | 2492 (1ull << MSR_SE) | 2493 (1ull << MSR_DE) | 2494 (1ull << MSR_FE1) | 2495 (1ull << MSR_EP) | 2496 (1ull << MSR_RI) | 2497 (1ull << MSR_LE); 2498 pcc->mmu_model = POWERPC_MMU_REAL; 2499 pcc->excp_model = POWERPC_EXCP_6xx; 2500 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2501 pcc->bfd_mach = bfd_mach_ppc_505; 2502 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2503 POWERPC_FLAG_BUS_CLK; 2504 } 2505 2506 static void init_proc_MPC8xx(CPUPPCState *env) 2507 { 2508 register_5xx_8xx_sprs(env); 2509 register_8xx_sprs(env); 2510 init_excp_MPC8xx(env); 2511 env->dcache_line_size = 32; 2512 env->icache_line_size = 32; 2513 /* XXX: TODO: allocate internal IRQ controller */ 2514 } 2515 2516 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2517 { 2518 DeviceClass *dc = DEVICE_CLASS(oc); 2519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2520 2521 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2522 pcc->init_proc = init_proc_MPC8xx; 2523 pcc->check_pow = check_pow_none; 2524 pcc->check_attn = check_attn_none; 2525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2526 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2527 PPC_CACHE_ICBI | PPC_MFTB; 2528 pcc->msr_mask = (1ull << MSR_ILE) | 2529 (1ull << MSR_EE) | 2530 (1ull << MSR_PR) | 2531 (1ull << MSR_FP) | 2532 (1ull << MSR_ME) | 2533 (1ull << MSR_SE) | 2534 (1ull << MSR_DE) | 2535 (1ull << MSR_EP) | 2536 (1ull << MSR_IR) | 2537 (1ull << MSR_DR) | 2538 (1ull << MSR_RI) | 2539 (1ull << MSR_LE); 2540 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2541 pcc->excp_model = POWERPC_EXCP_6xx; 2542 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2543 pcc->bfd_mach = bfd_mach_ppc_860; 2544 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2545 POWERPC_FLAG_BUS_CLK; 2546 } 2547 2548 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2549 2550 static void init_proc_G2(CPUPPCState *env) 2551 { 2552 register_non_embedded_sprs(env); 2553 register_sdr1_sprs(env); 2554 register_G2_sprs(env); 2555 2556 /* Memory management */ 2557 register_low_BATs(env); 2558 register_high_BATs(env); 2559 register_6xx_7xx_soft_tlb(env, 64, 2); 2560 init_excp_G2(env); 2561 env->dcache_line_size = 32; 2562 env->icache_line_size = 32; 2563 /* Allocate hardware IRQ controller */ 2564 ppc6xx_irq_init(env_archcpu(env)); 2565 } 2566 2567 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2568 { 2569 DeviceClass *dc = DEVICE_CLASS(oc); 2570 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2571 2572 dc->desc = "PowerPC G2"; 2573 pcc->init_proc = init_proc_G2; 2574 pcc->check_pow = check_pow_hid0; 2575 pcc->check_attn = check_attn_none; 2576 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2577 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2578 PPC_FLOAT_STFIWX | 2579 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2580 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2581 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2582 PPC_SEGMENT | PPC_EXTERN; 2583 pcc->msr_mask = (1ull << MSR_POW) | 2584 (1ull << MSR_TGPR) | 2585 (1ull << MSR_EE) | 2586 (1ull << MSR_PR) | 2587 (1ull << MSR_FP) | 2588 (1ull << MSR_ME) | 2589 (1ull << MSR_FE0) | 2590 (1ull << MSR_SE) | 2591 (1ull << MSR_DE) | 2592 (1ull << MSR_FE1) | 2593 (1ull << MSR_AL) | 2594 (1ull << MSR_EP) | 2595 (1ull << MSR_IR) | 2596 (1ull << MSR_DR) | 2597 (1ull << MSR_RI); 2598 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2599 pcc->excp_model = POWERPC_EXCP_6xx; 2600 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2601 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2602 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2603 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2604 } 2605 2606 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2607 { 2608 DeviceClass *dc = DEVICE_CLASS(oc); 2609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2610 2611 dc->desc = "PowerPC G2LE"; 2612 pcc->init_proc = init_proc_G2; 2613 pcc->check_pow = check_pow_hid0; 2614 pcc->check_attn = check_attn_none; 2615 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2616 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2617 PPC_FLOAT_STFIWX | 2618 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2619 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2620 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2621 PPC_SEGMENT | PPC_EXTERN; 2622 pcc->msr_mask = (1ull << MSR_POW) | 2623 (1ull << MSR_TGPR) | 2624 (1ull << MSR_ILE) | 2625 (1ull << MSR_EE) | 2626 (1ull << MSR_PR) | 2627 (1ull << MSR_FP) | 2628 (1ull << MSR_ME) | 2629 (1ull << MSR_FE0) | 2630 (1ull << MSR_SE) | 2631 (1ull << MSR_DE) | 2632 (1ull << MSR_FE1) | 2633 (1ull << MSR_AL) | 2634 (1ull << MSR_EP) | 2635 (1ull << MSR_IR) | 2636 (1ull << MSR_DR) | 2637 (1ull << MSR_RI) | 2638 (1ull << MSR_LE); 2639 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2640 pcc->excp_model = POWERPC_EXCP_6xx; 2641 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2642 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2643 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2644 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2645 } 2646 2647 static void init_proc_e200(CPUPPCState *env) 2648 { 2649 register_BookE_sprs(env, 0x000000070000FFFFULL); 2650 2651 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2652 &spr_read_spefscr, &spr_write_spefscr, 2653 &spr_read_spefscr, &spr_write_spefscr, 2654 0x00000000); 2655 /* Memory management */ 2656 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2657 register_usprgh_sprs(env); 2658 2659 spr_register(env, SPR_HID0, "HID0", 2660 SPR_NOACCESS, SPR_NOACCESS, 2661 &spr_read_generic, &spr_write_generic, 2662 0x00000000); 2663 2664 spr_register(env, SPR_HID1, "HID1", 2665 SPR_NOACCESS, SPR_NOACCESS, 2666 &spr_read_generic, &spr_write_generic, 2667 0x00000000); 2668 2669 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2670 SPR_NOACCESS, SPR_NOACCESS, 2671 &spr_read_generic, &spr_write_generic, 2672 0x00000000); 2673 2674 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2675 SPR_NOACCESS, SPR_NOACCESS, 2676 &spr_read_generic, &spr_write_generic, 2677 0x00000000); 2678 2679 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2680 SPR_NOACCESS, SPR_NOACCESS, 2681 &spr_read_generic, &spr_write_generic, 2682 0x00000000); 2683 2684 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2685 SPR_NOACCESS, SPR_NOACCESS, 2686 &spr_read_generic, &spr_write_generic, 2687 0x00000000); 2688 2689 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2690 SPR_NOACCESS, SPR_NOACCESS, 2691 &spr_read_generic, &spr_write_generic, 2692 0x00000000); 2693 2694 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2695 &spr_read_generic, SPR_NOACCESS, 2696 &spr_read_generic, SPR_NOACCESS, 2697 0x00000000); 2698 2699 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2700 SPR_NOACCESS, SPR_NOACCESS, 2701 &spr_read_generic, &spr_write_generic, 2702 0x00000000); 2703 2704 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2705 SPR_NOACCESS, SPR_NOACCESS, 2706 &spr_read_generic, &spr_write_generic, 2707 0x00000000); 2708 2709 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2710 SPR_NOACCESS, SPR_NOACCESS, 2711 &spr_read_generic, &spr_write_generic, 2712 0x00000000); 2713 2714 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2715 SPR_NOACCESS, SPR_NOACCESS, 2716 &spr_read_generic, &spr_write_generic, 2717 0x00000000); 2718 2719 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2720 SPR_NOACCESS, SPR_NOACCESS, 2721 &spr_read_generic, &spr_write_generic, 2722 0x00000000); 2723 2724 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2725 SPR_NOACCESS, SPR_NOACCESS, 2726 &spr_read_generic, &spr_write_generic, 2727 0x00000000); 2728 2729 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2730 SPR_NOACCESS, SPR_NOACCESS, 2731 &spr_read_generic, &spr_write_generic, 2732 0x00000000); /* TOFIX */ 2733 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2734 SPR_NOACCESS, SPR_NOACCESS, 2735 &spr_read_generic, &spr_write_generic, 2736 0x00000000); 2737 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2738 SPR_NOACCESS, SPR_NOACCESS, 2739 &spr_read_generic, &spr_write_generic, 2740 0x00000000); 2741 2742 init_tlbs_emb(env); 2743 init_excp_e200(env, 0xFFFF0000UL); 2744 env->dcache_line_size = 32; 2745 env->icache_line_size = 32; 2746 /* XXX: TODO: allocate internal IRQ controller */ 2747 } 2748 2749 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2750 { 2751 DeviceClass *dc = DEVICE_CLASS(oc); 2752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2753 2754 dc->desc = "e200 core"; 2755 pcc->init_proc = init_proc_e200; 2756 pcc->check_pow = check_pow_hid0; 2757 pcc->check_attn = check_attn_none; 2758 /* 2759 * XXX: unimplemented instructions: 2760 * dcblc 2761 * dcbtlst 2762 * dcbtstls 2763 * icblc 2764 * icbtls 2765 * tlbivax 2766 * all SPE multiply-accumulate instructions 2767 */ 2768 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2769 PPC_SPE | PPC_SPE_SINGLE | 2770 PPC_WRTEE | PPC_RFDI | 2771 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2772 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2773 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2774 PPC_BOOKE; 2775 pcc->msr_mask = (1ull << MSR_UCLE) | 2776 (1ull << MSR_SPE) | 2777 (1ull << MSR_POW) | 2778 (1ull << MSR_CE) | 2779 (1ull << MSR_EE) | 2780 (1ull << MSR_PR) | 2781 (1ull << MSR_FP) | 2782 (1ull << MSR_ME) | 2783 (1ull << MSR_FE0) | 2784 (1ull << MSR_DWE) | 2785 (1ull << MSR_DE) | 2786 (1ull << MSR_FE1) | 2787 (1ull << MSR_IR) | 2788 (1ull << MSR_DR); 2789 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2790 pcc->excp_model = POWERPC_EXCP_BOOKE; 2791 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2792 pcc->bfd_mach = bfd_mach_ppc_860; 2793 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2794 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2795 POWERPC_FLAG_BUS_CLK; 2796 } 2797 2798 enum fsl_e500_version { 2799 fsl_e500v1, 2800 fsl_e500v2, 2801 fsl_e500mc, 2802 fsl_e5500, 2803 fsl_e6500, 2804 }; 2805 2806 static void init_proc_e500(CPUPPCState *env, int version) 2807 { 2808 uint32_t tlbncfg[2]; 2809 uint64_t ivor_mask; 2810 uint64_t ivpr_mask = 0xFFFF0000ULL; 2811 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2812 | 0x0020; /* 32 kb */ 2813 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2814 | 0x0020; /* 32 kb */ 2815 uint32_t mmucfg = 0; 2816 #if !defined(CONFIG_USER_ONLY) 2817 int i; 2818 #endif 2819 2820 /* 2821 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2822 * complain when accessing them. 2823 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2824 */ 2825 switch (version) { 2826 case fsl_e500v1: 2827 case fsl_e500v2: 2828 default: 2829 ivor_mask = 0x0000000F0000FFFFULL; 2830 break; 2831 case fsl_e500mc: 2832 case fsl_e5500: 2833 ivor_mask = 0x000003FE0000FFFFULL; 2834 break; 2835 case fsl_e6500: 2836 ivor_mask = 0x000003FF0000FFFFULL; 2837 break; 2838 } 2839 register_BookE_sprs(env, ivor_mask); 2840 2841 spr_register(env, SPR_USPRG3, "USPRG3", 2842 &spr_read_ureg, SPR_NOACCESS, 2843 &spr_read_ureg, SPR_NOACCESS, 2844 0x00000000); 2845 2846 /* Processor identification */ 2847 spr_register(env, SPR_BOOKE_PIR, "PIR", 2848 SPR_NOACCESS, SPR_NOACCESS, 2849 &spr_read_generic, &spr_write_pir, 2850 0x00000000); 2851 2852 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2853 &spr_read_spefscr, &spr_write_spefscr, 2854 &spr_read_spefscr, &spr_write_spefscr, 2855 0x00000000); 2856 #if !defined(CONFIG_USER_ONLY) 2857 /* Memory management */ 2858 env->nb_pids = 3; 2859 env->nb_ways = 2; 2860 switch (version) { 2861 case fsl_e500v1: 2862 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2863 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2864 break; 2865 case fsl_e500v2: 2866 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2867 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2868 break; 2869 case fsl_e500mc: 2870 case fsl_e5500: 2871 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2872 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2873 break; 2874 case fsl_e6500: 2875 mmucfg = 0x6510B45; 2876 env->nb_pids = 1; 2877 tlbncfg[0] = 0x08052400; 2878 tlbncfg[1] = 0x40028040; 2879 break; 2880 default: 2881 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2882 env->spr[SPR_PVR]); 2883 } 2884 #endif 2885 /* Cache sizes */ 2886 switch (version) { 2887 case fsl_e500v1: 2888 case fsl_e500v2: 2889 env->dcache_line_size = 32; 2890 env->icache_line_size = 32; 2891 break; 2892 case fsl_e500mc: 2893 case fsl_e5500: 2894 env->dcache_line_size = 64; 2895 env->icache_line_size = 64; 2896 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2897 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2898 break; 2899 case fsl_e6500: 2900 env->dcache_line_size = 32; 2901 env->icache_line_size = 32; 2902 l1cfg0 |= 0x0F83820; 2903 l1cfg1 |= 0x0B83820; 2904 break; 2905 default: 2906 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2907 env->spr[SPR_PVR]); 2908 } 2909 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2910 register_usprgh_sprs(env); 2911 2912 spr_register(env, SPR_HID0, "HID0", 2913 SPR_NOACCESS, SPR_NOACCESS, 2914 &spr_read_generic, &spr_write_generic, 2915 0x00000000); 2916 2917 spr_register(env, SPR_HID1, "HID1", 2918 SPR_NOACCESS, SPR_NOACCESS, 2919 &spr_read_generic, &spr_write_generic, 2920 0x00000000); 2921 2922 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2923 SPR_NOACCESS, SPR_NOACCESS, 2924 &spr_read_generic, &spr_write_generic, 2925 0x00000000); 2926 2927 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2928 SPR_NOACCESS, SPR_NOACCESS, 2929 &spr_read_generic, &spr_write_generic, 2930 0x00000000); 2931 2932 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2933 SPR_NOACCESS, SPR_NOACCESS, 2934 &spr_read_generic, &spr_write_generic, 2935 0x00000000); 2936 2937 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2938 SPR_NOACCESS, SPR_NOACCESS, 2939 &spr_read_generic, &spr_write_generic, 2940 0x00000000); 2941 2942 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2943 SPR_NOACCESS, SPR_NOACCESS, 2944 &spr_read_generic, &spr_write_generic, 2945 0x00000000); 2946 2947 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2948 SPR_NOACCESS, SPR_NOACCESS, 2949 &spr_read_generic, &spr_write_generic, 2950 0x00000000); 2951 2952 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2953 &spr_read_generic, SPR_NOACCESS, 2954 &spr_read_generic, SPR_NOACCESS, 2955 l1cfg0); 2956 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2957 &spr_read_generic, SPR_NOACCESS, 2958 &spr_read_generic, SPR_NOACCESS, 2959 l1cfg1); 2960 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2961 SPR_NOACCESS, SPR_NOACCESS, 2962 &spr_read_generic, &spr_write_e500_l1csr0, 2963 0x00000000); 2964 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2965 SPR_NOACCESS, SPR_NOACCESS, 2966 &spr_read_generic, &spr_write_e500_l1csr1, 2967 0x00000000); 2968 if (version != fsl_e500v1 && version != fsl_e500v2) { 2969 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2970 SPR_NOACCESS, SPR_NOACCESS, 2971 &spr_read_generic, &spr_write_e500_l2csr0, 2972 0x00000000); 2973 } 2974 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2975 SPR_NOACCESS, SPR_NOACCESS, 2976 &spr_read_generic, &spr_write_generic, 2977 0x00000000); 2978 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2979 SPR_NOACCESS, SPR_NOACCESS, 2980 &spr_read_generic, &spr_write_generic, 2981 0x00000000); 2982 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2983 SPR_NOACCESS, SPR_NOACCESS, 2984 &spr_read_generic, &spr_write_booke206_mmucsr0, 2985 0x00000000); 2986 spr_register(env, SPR_BOOKE_EPR, "EPR", 2987 SPR_NOACCESS, SPR_NOACCESS, 2988 &spr_read_generic, SPR_NOACCESS, 2989 0x00000000); 2990 /* XXX better abstract into Emb.xxx features */ 2991 if ((version == fsl_e5500) || (version == fsl_e6500)) { 2992 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 2993 SPR_NOACCESS, SPR_NOACCESS, 2994 &spr_read_generic, &spr_write_generic, 2995 0x00000000); 2996 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 2997 SPR_NOACCESS, SPR_NOACCESS, 2998 &spr_read_mas73, &spr_write_mas73, 2999 0x00000000); 3000 ivpr_mask = (target_ulong)~0xFFFFULL; 3001 } 3002 3003 if (version == fsl_e6500) { 3004 /* Thread identification */ 3005 spr_register(env, SPR_TIR, "TIR", 3006 SPR_NOACCESS, SPR_NOACCESS, 3007 &spr_read_generic, SPR_NOACCESS, 3008 0x00000000); 3009 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3010 SPR_NOACCESS, SPR_NOACCESS, 3011 &spr_read_generic, SPR_NOACCESS, 3012 0x00000004); 3013 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3014 SPR_NOACCESS, SPR_NOACCESS, 3015 &spr_read_generic, SPR_NOACCESS, 3016 0x7FFFFFFC); 3017 } 3018 3019 #if !defined(CONFIG_USER_ONLY) 3020 env->nb_tlb = 0; 3021 env->tlb_type = TLB_MAS; 3022 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3023 env->nb_tlb += booke206_tlb_size(env, i); 3024 } 3025 #endif 3026 3027 init_excp_e200(env, ivpr_mask); 3028 /* Allocate hardware IRQ controller */ 3029 ppce500_irq_init(env_archcpu(env)); 3030 } 3031 3032 static void init_proc_e500v1(CPUPPCState *env) 3033 { 3034 init_proc_e500(env, fsl_e500v1); 3035 } 3036 3037 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3038 { 3039 DeviceClass *dc = DEVICE_CLASS(oc); 3040 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3041 3042 dc->desc = "e500v1 core"; 3043 pcc->init_proc = init_proc_e500v1; 3044 pcc->check_pow = check_pow_hid0; 3045 pcc->check_attn = check_attn_none; 3046 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3047 PPC_SPE | PPC_SPE_SINGLE | 3048 PPC_WRTEE | PPC_RFDI | 3049 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3050 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3051 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3052 pcc->insns_flags2 = PPC2_BOOKE206; 3053 pcc->msr_mask = (1ull << MSR_UCLE) | 3054 (1ull << MSR_SPE) | 3055 (1ull << MSR_POW) | 3056 (1ull << MSR_CE) | 3057 (1ull << MSR_EE) | 3058 (1ull << MSR_PR) | 3059 (1ull << MSR_FP) | 3060 (1ull << MSR_ME) | 3061 (1ull << MSR_FE0) | 3062 (1ull << MSR_DWE) | 3063 (1ull << MSR_DE) | 3064 (1ull << MSR_FE1) | 3065 (1ull << MSR_IR) | 3066 (1ull << MSR_DR); 3067 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3068 pcc->excp_model = POWERPC_EXCP_BOOKE; 3069 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3070 pcc->bfd_mach = bfd_mach_ppc_860; 3071 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3072 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3073 POWERPC_FLAG_BUS_CLK; 3074 } 3075 3076 static void init_proc_e500v2(CPUPPCState *env) 3077 { 3078 init_proc_e500(env, fsl_e500v2); 3079 } 3080 3081 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3082 { 3083 DeviceClass *dc = DEVICE_CLASS(oc); 3084 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3085 3086 dc->desc = "e500v2 core"; 3087 pcc->init_proc = init_proc_e500v2; 3088 pcc->check_pow = check_pow_hid0; 3089 pcc->check_attn = check_attn_none; 3090 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3091 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3092 PPC_WRTEE | PPC_RFDI | 3093 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3094 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3095 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3096 pcc->insns_flags2 = PPC2_BOOKE206; 3097 pcc->msr_mask = (1ull << MSR_UCLE) | 3098 (1ull << MSR_SPE) | 3099 (1ull << MSR_POW) | 3100 (1ull << MSR_CE) | 3101 (1ull << MSR_EE) | 3102 (1ull << MSR_PR) | 3103 (1ull << MSR_FP) | 3104 (1ull << MSR_ME) | 3105 (1ull << MSR_FE0) | 3106 (1ull << MSR_DWE) | 3107 (1ull << MSR_DE) | 3108 (1ull << MSR_FE1) | 3109 (1ull << MSR_IR) | 3110 (1ull << MSR_DR); 3111 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3112 pcc->excp_model = POWERPC_EXCP_BOOKE; 3113 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3114 pcc->bfd_mach = bfd_mach_ppc_860; 3115 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3116 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3117 POWERPC_FLAG_BUS_CLK; 3118 } 3119 3120 static void init_proc_e500mc(CPUPPCState *env) 3121 { 3122 init_proc_e500(env, fsl_e500mc); 3123 } 3124 3125 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3126 { 3127 DeviceClass *dc = DEVICE_CLASS(oc); 3128 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3129 3130 dc->desc = "e500mc core"; 3131 pcc->init_proc = init_proc_e500mc; 3132 pcc->check_pow = check_pow_none; 3133 pcc->check_attn = check_attn_none; 3134 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3135 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3136 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3137 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3138 PPC_FLOAT | PPC_FLOAT_FRES | 3139 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3140 PPC_FLOAT_STFIWX | PPC_WAIT | 3141 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3142 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3143 pcc->msr_mask = (1ull << MSR_GS) | 3144 (1ull << MSR_UCLE) | 3145 (1ull << MSR_CE) | 3146 (1ull << MSR_EE) | 3147 (1ull << MSR_PR) | 3148 (1ull << MSR_FP) | 3149 (1ull << MSR_ME) | 3150 (1ull << MSR_FE0) | 3151 (1ull << MSR_DE) | 3152 (1ull << MSR_FE1) | 3153 (1ull << MSR_IR) | 3154 (1ull << MSR_DR) | 3155 (1ull << MSR_PX) | 3156 (1ull << MSR_RI); 3157 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3158 pcc->excp_model = POWERPC_EXCP_BOOKE; 3159 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3160 /* FIXME: figure out the correct flag for e500mc */ 3161 pcc->bfd_mach = bfd_mach_ppc_e500; 3162 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3163 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3164 } 3165 3166 #ifdef TARGET_PPC64 3167 static void init_proc_e5500(CPUPPCState *env) 3168 { 3169 init_proc_e500(env, fsl_e5500); 3170 } 3171 3172 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3173 { 3174 DeviceClass *dc = DEVICE_CLASS(oc); 3175 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3176 3177 dc->desc = "e5500 core"; 3178 pcc->init_proc = init_proc_e5500; 3179 pcc->check_pow = check_pow_none; 3180 pcc->check_attn = check_attn_none; 3181 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3182 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3183 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3184 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3185 PPC_FLOAT | PPC_FLOAT_FRES | 3186 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3187 PPC_FLOAT_STFIWX | PPC_WAIT | 3188 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3189 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3190 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3191 PPC2_FP_CVT_S64; 3192 pcc->msr_mask = (1ull << MSR_CM) | 3193 (1ull << MSR_GS) | 3194 (1ull << MSR_UCLE) | 3195 (1ull << MSR_CE) | 3196 (1ull << MSR_EE) | 3197 (1ull << MSR_PR) | 3198 (1ull << MSR_FP) | 3199 (1ull << MSR_ME) | 3200 (1ull << MSR_FE0) | 3201 (1ull << MSR_DE) | 3202 (1ull << MSR_FE1) | 3203 (1ull << MSR_IR) | 3204 (1ull << MSR_DR) | 3205 (1ull << MSR_PX) | 3206 (1ull << MSR_RI); 3207 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3208 pcc->excp_model = POWERPC_EXCP_BOOKE; 3209 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3210 /* FIXME: figure out the correct flag for e5500 */ 3211 pcc->bfd_mach = bfd_mach_ppc_e500; 3212 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3213 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3214 } 3215 3216 static void init_proc_e6500(CPUPPCState *env) 3217 { 3218 init_proc_e500(env, fsl_e6500); 3219 } 3220 3221 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3222 { 3223 DeviceClass *dc = DEVICE_CLASS(oc); 3224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3225 3226 dc->desc = "e6500 core"; 3227 pcc->init_proc = init_proc_e6500; 3228 pcc->check_pow = check_pow_none; 3229 pcc->check_attn = check_attn_none; 3230 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3231 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3232 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3233 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3234 PPC_FLOAT | PPC_FLOAT_FRES | 3235 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3236 PPC_FLOAT_STFIWX | PPC_WAIT | 3237 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3238 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3239 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3240 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3241 pcc->msr_mask = (1ull << MSR_CM) | 3242 (1ull << MSR_GS) | 3243 (1ull << MSR_UCLE) | 3244 (1ull << MSR_CE) | 3245 (1ull << MSR_EE) | 3246 (1ull << MSR_PR) | 3247 (1ull << MSR_FP) | 3248 (1ull << MSR_ME) | 3249 (1ull << MSR_FE0) | 3250 (1ull << MSR_DE) | 3251 (1ull << MSR_FE1) | 3252 (1ull << MSR_IS) | 3253 (1ull << MSR_DS) | 3254 (1ull << MSR_PX) | 3255 (1ull << MSR_RI) | 3256 (1ull << MSR_VR); 3257 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3258 pcc->excp_model = POWERPC_EXCP_BOOKE; 3259 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3260 pcc->bfd_mach = bfd_mach_ppc_e500; 3261 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3262 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3263 } 3264 3265 #endif 3266 3267 /* Non-embedded PowerPC */ 3268 static void init_proc_603(CPUPPCState *env) 3269 { 3270 register_non_embedded_sprs(env); 3271 register_sdr1_sprs(env); 3272 register_603_sprs(env); 3273 3274 /* Memory management */ 3275 register_low_BATs(env); 3276 register_6xx_7xx_soft_tlb(env, 64, 2); 3277 init_excp_603(env); 3278 env->dcache_line_size = 32; 3279 env->icache_line_size = 32; 3280 /* Allocate hardware IRQ controller */ 3281 ppc6xx_irq_init(env_archcpu(env)); 3282 } 3283 3284 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3285 { 3286 DeviceClass *dc = DEVICE_CLASS(oc); 3287 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3288 3289 dc->desc = "PowerPC 603"; 3290 pcc->init_proc = init_proc_603; 3291 pcc->check_pow = check_pow_hid0; 3292 pcc->check_attn = check_attn_none; 3293 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3294 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3295 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3296 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3297 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3298 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3299 PPC_SEGMENT | PPC_EXTERN; 3300 pcc->msr_mask = (1ull << MSR_POW) | 3301 (1ull << MSR_TGPR) | 3302 (1ull << MSR_ILE) | 3303 (1ull << MSR_EE) | 3304 (1ull << MSR_PR) | 3305 (1ull << MSR_FP) | 3306 (1ull << MSR_ME) | 3307 (1ull << MSR_FE0) | 3308 (1ull << MSR_SE) | 3309 (1ull << MSR_DE) | 3310 (1ull << MSR_FE1) | 3311 (1ull << MSR_EP) | 3312 (1ull << MSR_IR) | 3313 (1ull << MSR_DR) | 3314 (1ull << MSR_RI) | 3315 (1ull << MSR_LE); 3316 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3317 pcc->excp_model = POWERPC_EXCP_6xx; 3318 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3319 pcc->bfd_mach = bfd_mach_ppc_603; 3320 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3321 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3322 } 3323 3324 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3325 { 3326 DeviceClass *dc = DEVICE_CLASS(oc); 3327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3328 3329 dc->desc = "PowerPC 603e"; 3330 pcc->init_proc = init_proc_603; 3331 pcc->check_pow = check_pow_hid0; 3332 pcc->check_attn = check_attn_none; 3333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3334 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3335 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3336 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3337 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3338 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3339 PPC_SEGMENT | PPC_EXTERN; 3340 pcc->msr_mask = (1ull << MSR_POW) | 3341 (1ull << MSR_TGPR) | 3342 (1ull << MSR_ILE) | 3343 (1ull << MSR_EE) | 3344 (1ull << MSR_PR) | 3345 (1ull << MSR_FP) | 3346 (1ull << MSR_ME) | 3347 (1ull << MSR_FE0) | 3348 (1ull << MSR_SE) | 3349 (1ull << MSR_DE) | 3350 (1ull << MSR_FE1) | 3351 (1ull << MSR_EP) | 3352 (1ull << MSR_IR) | 3353 (1ull << MSR_DR) | 3354 (1ull << MSR_RI) | 3355 (1ull << MSR_LE); 3356 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3357 pcc->excp_model = POWERPC_EXCP_6xx; 3358 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3359 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3360 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3361 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3362 } 3363 3364 static void init_proc_e300(CPUPPCState *env) 3365 { 3366 init_proc_603(env); 3367 register_e300_sprs(env); 3368 } 3369 3370 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3371 { 3372 DeviceClass *dc = DEVICE_CLASS(oc); 3373 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3374 3375 dc->desc = "e300 core"; 3376 pcc->init_proc = init_proc_e300; 3377 pcc->check_pow = check_pow_hid0; 3378 pcc->check_attn = check_attn_none; 3379 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3380 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3381 PPC_FLOAT_STFIWX | 3382 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3383 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3384 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3385 PPC_SEGMENT | PPC_EXTERN; 3386 pcc->msr_mask = (1ull << MSR_POW) | 3387 (1ull << MSR_TGPR) | 3388 (1ull << MSR_ILE) | 3389 (1ull << MSR_EE) | 3390 (1ull << MSR_PR) | 3391 (1ull << MSR_FP) | 3392 (1ull << MSR_ME) | 3393 (1ull << MSR_FE0) | 3394 (1ull << MSR_SE) | 3395 (1ull << MSR_DE) | 3396 (1ull << MSR_FE1) | 3397 (1ull << MSR_AL) | 3398 (1ull << MSR_EP) | 3399 (1ull << MSR_IR) | 3400 (1ull << MSR_DR) | 3401 (1ull << MSR_RI) | 3402 (1ull << MSR_LE); 3403 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3404 pcc->excp_model = POWERPC_EXCP_6xx; 3405 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3406 pcc->bfd_mach = bfd_mach_ppc_603; 3407 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3408 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3409 } 3410 3411 static void init_proc_604(CPUPPCState *env) 3412 { 3413 register_non_embedded_sprs(env); 3414 register_sdr1_sprs(env); 3415 register_604_sprs(env); 3416 3417 /* Memory management */ 3418 register_low_BATs(env); 3419 init_excp_604(env); 3420 env->dcache_line_size = 32; 3421 env->icache_line_size = 32; 3422 /* Allocate hardware IRQ controller */ 3423 ppc6xx_irq_init(env_archcpu(env)); 3424 } 3425 3426 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3427 { 3428 DeviceClass *dc = DEVICE_CLASS(oc); 3429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3430 3431 dc->desc = "PowerPC 604"; 3432 pcc->init_proc = init_proc_604; 3433 pcc->check_pow = check_pow_nocheck; 3434 pcc->check_attn = check_attn_none; 3435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3436 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3437 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3438 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3439 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3440 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3441 PPC_SEGMENT | PPC_EXTERN; 3442 pcc->msr_mask = (1ull << MSR_POW) | 3443 (1ull << MSR_ILE) | 3444 (1ull << MSR_EE) | 3445 (1ull << MSR_PR) | 3446 (1ull << MSR_FP) | 3447 (1ull << MSR_ME) | 3448 (1ull << MSR_FE0) | 3449 (1ull << MSR_SE) | 3450 (1ull << MSR_DE) | 3451 (1ull << MSR_FE1) | 3452 (1ull << MSR_EP) | 3453 (1ull << MSR_IR) | 3454 (1ull << MSR_DR) | 3455 (1ull << MSR_PMM) | 3456 (1ull << MSR_RI) | 3457 (1ull << MSR_LE); 3458 pcc->mmu_model = POWERPC_MMU_32B; 3459 pcc->excp_model = POWERPC_EXCP_6xx; 3460 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3461 pcc->bfd_mach = bfd_mach_ppc_604; 3462 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3463 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3464 } 3465 3466 static void init_proc_604E(CPUPPCState *env) 3467 { 3468 init_proc_604(env); 3469 register_604e_sprs(env); 3470 } 3471 3472 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3473 { 3474 DeviceClass *dc = DEVICE_CLASS(oc); 3475 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3476 3477 dc->desc = "PowerPC 604E"; 3478 pcc->init_proc = init_proc_604E; 3479 pcc->check_pow = check_pow_nocheck; 3480 pcc->check_attn = check_attn_none; 3481 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3482 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3483 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3484 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3485 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3486 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3487 PPC_SEGMENT | PPC_EXTERN; 3488 pcc->msr_mask = (1ull << MSR_POW) | 3489 (1ull << MSR_ILE) | 3490 (1ull << MSR_EE) | 3491 (1ull << MSR_PR) | 3492 (1ull << MSR_FP) | 3493 (1ull << MSR_ME) | 3494 (1ull << MSR_FE0) | 3495 (1ull << MSR_SE) | 3496 (1ull << MSR_DE) | 3497 (1ull << MSR_FE1) | 3498 (1ull << MSR_EP) | 3499 (1ull << MSR_IR) | 3500 (1ull << MSR_DR) | 3501 (1ull << MSR_PMM) | 3502 (1ull << MSR_RI) | 3503 (1ull << MSR_LE); 3504 pcc->mmu_model = POWERPC_MMU_32B; 3505 pcc->excp_model = POWERPC_EXCP_6xx; 3506 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3507 pcc->bfd_mach = bfd_mach_ppc_604; 3508 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3509 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3510 } 3511 3512 static void init_proc_740(CPUPPCState *env) 3513 { 3514 register_non_embedded_sprs(env); 3515 register_sdr1_sprs(env); 3516 register_7xx_sprs(env); 3517 /* Thermal management */ 3518 register_thrm_sprs(env); 3519 3520 /* Memory management */ 3521 register_low_BATs(env); 3522 init_excp_7x0(env); 3523 env->dcache_line_size = 32; 3524 env->icache_line_size = 32; 3525 /* Allocate hardware IRQ controller */ 3526 ppc6xx_irq_init(env_archcpu(env)); 3527 } 3528 3529 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3530 { 3531 DeviceClass *dc = DEVICE_CLASS(oc); 3532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3533 3534 dc->desc = "PowerPC 740"; 3535 pcc->init_proc = init_proc_740; 3536 pcc->check_pow = check_pow_hid0; 3537 pcc->check_attn = check_attn_none; 3538 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3539 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3540 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3541 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3542 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3543 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3544 PPC_SEGMENT | PPC_EXTERN; 3545 pcc->msr_mask = (1ull << MSR_POW) | 3546 (1ull << MSR_ILE) | 3547 (1ull << MSR_EE) | 3548 (1ull << MSR_PR) | 3549 (1ull << MSR_FP) | 3550 (1ull << MSR_ME) | 3551 (1ull << MSR_FE0) | 3552 (1ull << MSR_SE) | 3553 (1ull << MSR_DE) | 3554 (1ull << MSR_FE1) | 3555 (1ull << MSR_EP) | 3556 (1ull << MSR_IR) | 3557 (1ull << MSR_DR) | 3558 (1ull << MSR_PMM) | 3559 (1ull << MSR_RI) | 3560 (1ull << MSR_LE); 3561 pcc->mmu_model = POWERPC_MMU_32B; 3562 pcc->excp_model = POWERPC_EXCP_7xx; 3563 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3564 pcc->bfd_mach = bfd_mach_ppc_750; 3565 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3566 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3567 } 3568 3569 static void init_proc_750(CPUPPCState *env) 3570 { 3571 register_non_embedded_sprs(env); 3572 register_sdr1_sprs(env); 3573 register_7xx_sprs(env); 3574 3575 spr_register(env, SPR_L2CR, "L2CR", 3576 SPR_NOACCESS, SPR_NOACCESS, 3577 &spr_read_generic, spr_access_nop, 3578 0x00000000); 3579 /* Thermal management */ 3580 register_thrm_sprs(env); 3581 3582 /* Memory management */ 3583 register_low_BATs(env); 3584 /* 3585 * XXX: high BATs are also present but are known to be bugged on 3586 * die version 1.x 3587 */ 3588 init_excp_7x0(env); 3589 env->dcache_line_size = 32; 3590 env->icache_line_size = 32; 3591 /* Allocate hardware IRQ controller */ 3592 ppc6xx_irq_init(env_archcpu(env)); 3593 } 3594 3595 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3596 { 3597 DeviceClass *dc = DEVICE_CLASS(oc); 3598 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3599 3600 dc->desc = "PowerPC 750"; 3601 pcc->init_proc = init_proc_750; 3602 pcc->check_pow = check_pow_hid0; 3603 pcc->check_attn = check_attn_none; 3604 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3605 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3606 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3607 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3608 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3609 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3610 PPC_SEGMENT | PPC_EXTERN; 3611 pcc->msr_mask = (1ull << MSR_POW) | 3612 (1ull << MSR_ILE) | 3613 (1ull << MSR_EE) | 3614 (1ull << MSR_PR) | 3615 (1ull << MSR_FP) | 3616 (1ull << MSR_ME) | 3617 (1ull << MSR_FE0) | 3618 (1ull << MSR_SE) | 3619 (1ull << MSR_DE) | 3620 (1ull << MSR_FE1) | 3621 (1ull << MSR_EP) | 3622 (1ull << MSR_IR) | 3623 (1ull << MSR_DR) | 3624 (1ull << MSR_PMM) | 3625 (1ull << MSR_RI) | 3626 (1ull << MSR_LE); 3627 pcc->mmu_model = POWERPC_MMU_32B; 3628 pcc->excp_model = POWERPC_EXCP_7xx; 3629 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3630 pcc->bfd_mach = bfd_mach_ppc_750; 3631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3632 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3633 } 3634 3635 static void init_proc_750cl(CPUPPCState *env) 3636 { 3637 register_non_embedded_sprs(env); 3638 register_sdr1_sprs(env); 3639 register_7xx_sprs(env); 3640 3641 spr_register(env, SPR_L2CR, "L2CR", 3642 SPR_NOACCESS, SPR_NOACCESS, 3643 &spr_read_generic, spr_access_nop, 3644 0x00000000); 3645 /* Thermal management */ 3646 /* Those registers are fake on 750CL */ 3647 spr_register(env, SPR_THRM1, "THRM1", 3648 SPR_NOACCESS, SPR_NOACCESS, 3649 &spr_read_generic, &spr_write_generic, 3650 0x00000000); 3651 spr_register(env, SPR_THRM2, "THRM2", 3652 SPR_NOACCESS, SPR_NOACCESS, 3653 &spr_read_generic, &spr_write_generic, 3654 0x00000000); 3655 spr_register(env, SPR_THRM3, "THRM3", 3656 SPR_NOACCESS, SPR_NOACCESS, 3657 &spr_read_generic, &spr_write_generic, 3658 0x00000000); 3659 3660 spr_register(env, SPR_750_TDCL, "TDCL", 3661 SPR_NOACCESS, SPR_NOACCESS, 3662 &spr_read_generic, &spr_write_generic, 3663 0x00000000); 3664 spr_register(env, SPR_750_TDCH, "TDCH", 3665 SPR_NOACCESS, SPR_NOACCESS, 3666 &spr_read_generic, &spr_write_generic, 3667 0x00000000); 3668 /* DMA */ 3669 spr_register(env, SPR_750_WPAR, "WPAR", 3670 SPR_NOACCESS, SPR_NOACCESS, 3671 &spr_read_generic, &spr_write_generic, 3672 0x00000000); 3673 spr_register(env, SPR_750_DMAL, "DMAL", 3674 SPR_NOACCESS, SPR_NOACCESS, 3675 &spr_read_generic, &spr_write_generic, 3676 0x00000000); 3677 spr_register(env, SPR_750_DMAU, "DMAU", 3678 SPR_NOACCESS, SPR_NOACCESS, 3679 &spr_read_generic, &spr_write_generic, 3680 0x00000000); 3681 /* Hardware implementation registers */ 3682 spr_register(env, SPR_750CL_HID2, "HID2", 3683 SPR_NOACCESS, SPR_NOACCESS, 3684 &spr_read_generic, &spr_write_generic, 3685 0x00000000); 3686 3687 spr_register(env, SPR_750CL_HID4, "HID4", 3688 SPR_NOACCESS, SPR_NOACCESS, 3689 &spr_read_generic, &spr_write_generic, 3690 0x00000000); 3691 /* Quantization registers */ 3692 spr_register(env, SPR_750_GQR0, "GQR0", 3693 SPR_NOACCESS, SPR_NOACCESS, 3694 &spr_read_generic, &spr_write_generic, 3695 0x00000000); 3696 3697 spr_register(env, SPR_750_GQR1, "GQR1", 3698 SPR_NOACCESS, SPR_NOACCESS, 3699 &spr_read_generic, &spr_write_generic, 3700 0x00000000); 3701 3702 spr_register(env, SPR_750_GQR2, "GQR2", 3703 SPR_NOACCESS, SPR_NOACCESS, 3704 &spr_read_generic, &spr_write_generic, 3705 0x00000000); 3706 3707 spr_register(env, SPR_750_GQR3, "GQR3", 3708 SPR_NOACCESS, SPR_NOACCESS, 3709 &spr_read_generic, &spr_write_generic, 3710 0x00000000); 3711 3712 spr_register(env, SPR_750_GQR4, "GQR4", 3713 SPR_NOACCESS, SPR_NOACCESS, 3714 &spr_read_generic, &spr_write_generic, 3715 0x00000000); 3716 3717 spr_register(env, SPR_750_GQR5, "GQR5", 3718 SPR_NOACCESS, SPR_NOACCESS, 3719 &spr_read_generic, &spr_write_generic, 3720 0x00000000); 3721 3722 spr_register(env, SPR_750_GQR6, "GQR6", 3723 SPR_NOACCESS, SPR_NOACCESS, 3724 &spr_read_generic, &spr_write_generic, 3725 0x00000000); 3726 3727 spr_register(env, SPR_750_GQR7, "GQR7", 3728 SPR_NOACCESS, SPR_NOACCESS, 3729 &spr_read_generic, &spr_write_generic, 3730 0x00000000); 3731 /* Memory management */ 3732 register_low_BATs(env); 3733 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3734 register_high_BATs(env); 3735 init_excp_750cl(env); 3736 env->dcache_line_size = 32; 3737 env->icache_line_size = 32; 3738 /* Allocate hardware IRQ controller */ 3739 ppc6xx_irq_init(env_archcpu(env)); 3740 } 3741 3742 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3743 { 3744 DeviceClass *dc = DEVICE_CLASS(oc); 3745 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3746 3747 dc->desc = "PowerPC 750 CL"; 3748 pcc->init_proc = init_proc_750cl; 3749 pcc->check_pow = check_pow_hid0; 3750 pcc->check_attn = check_attn_none; 3751 /* 3752 * XXX: not implemented: 3753 * cache lock instructions: 3754 * dcbz_l 3755 * floating point paired instructions 3756 * psq_lux 3757 * psq_lx 3758 * psq_stux 3759 * psq_stx 3760 * ps_abs 3761 * ps_add 3762 * ps_cmpo0 3763 * ps_cmpo1 3764 * ps_cmpu0 3765 * ps_cmpu1 3766 * ps_div 3767 * ps_madd 3768 * ps_madds0 3769 * ps_madds1 3770 * ps_merge00 3771 * ps_merge01 3772 * ps_merge10 3773 * ps_merge11 3774 * ps_mr 3775 * ps_msub 3776 * ps_mul 3777 * ps_muls0 3778 * ps_muls1 3779 * ps_nabs 3780 * ps_neg 3781 * ps_nmadd 3782 * ps_nmsub 3783 * ps_res 3784 * ps_rsqrte 3785 * ps_sel 3786 * ps_sub 3787 * ps_sum0 3788 * ps_sum1 3789 */ 3790 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3791 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3792 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3793 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3794 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3795 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3796 PPC_SEGMENT | PPC_EXTERN; 3797 pcc->msr_mask = (1ull << MSR_POW) | 3798 (1ull << MSR_ILE) | 3799 (1ull << MSR_EE) | 3800 (1ull << MSR_PR) | 3801 (1ull << MSR_FP) | 3802 (1ull << MSR_ME) | 3803 (1ull << MSR_FE0) | 3804 (1ull << MSR_SE) | 3805 (1ull << MSR_DE) | 3806 (1ull << MSR_FE1) | 3807 (1ull << MSR_EP) | 3808 (1ull << MSR_IR) | 3809 (1ull << MSR_DR) | 3810 (1ull << MSR_PMM) | 3811 (1ull << MSR_RI) | 3812 (1ull << MSR_LE); 3813 pcc->mmu_model = POWERPC_MMU_32B; 3814 pcc->excp_model = POWERPC_EXCP_7xx; 3815 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3816 pcc->bfd_mach = bfd_mach_ppc_750; 3817 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3818 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3819 } 3820 3821 static void init_proc_750cx(CPUPPCState *env) 3822 { 3823 register_non_embedded_sprs(env); 3824 register_sdr1_sprs(env); 3825 register_7xx_sprs(env); 3826 3827 spr_register(env, SPR_L2CR, "L2CR", 3828 SPR_NOACCESS, SPR_NOACCESS, 3829 &spr_read_generic, spr_access_nop, 3830 0x00000000); 3831 /* Thermal management */ 3832 register_thrm_sprs(env); 3833 3834 spr_register(env, SPR_SDA, "SDA", 3835 SPR_NOACCESS, SPR_NOACCESS, 3836 &spr_read_generic, &spr_write_generic, 3837 0x00000000); 3838 3839 /* Memory management */ 3840 register_low_BATs(env); 3841 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3842 register_high_BATs(env); 3843 init_excp_750cx(env); 3844 env->dcache_line_size = 32; 3845 env->icache_line_size = 32; 3846 /* Allocate hardware IRQ controller */ 3847 ppc6xx_irq_init(env_archcpu(env)); 3848 } 3849 3850 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3851 { 3852 DeviceClass *dc = DEVICE_CLASS(oc); 3853 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3854 3855 dc->desc = "PowerPC 750CX"; 3856 pcc->init_proc = init_proc_750cx; 3857 pcc->check_pow = check_pow_hid0; 3858 pcc->check_attn = check_attn_none; 3859 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3860 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3861 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3862 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3863 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3864 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3865 PPC_SEGMENT | PPC_EXTERN; 3866 pcc->msr_mask = (1ull << MSR_POW) | 3867 (1ull << MSR_ILE) | 3868 (1ull << MSR_EE) | 3869 (1ull << MSR_PR) | 3870 (1ull << MSR_FP) | 3871 (1ull << MSR_ME) | 3872 (1ull << MSR_FE0) | 3873 (1ull << MSR_SE) | 3874 (1ull << MSR_DE) | 3875 (1ull << MSR_FE1) | 3876 (1ull << MSR_EP) | 3877 (1ull << MSR_IR) | 3878 (1ull << MSR_DR) | 3879 (1ull << MSR_PMM) | 3880 (1ull << MSR_RI) | 3881 (1ull << MSR_LE); 3882 pcc->mmu_model = POWERPC_MMU_32B; 3883 pcc->excp_model = POWERPC_EXCP_7xx; 3884 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3885 pcc->bfd_mach = bfd_mach_ppc_750; 3886 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3887 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3888 } 3889 3890 static void init_proc_750fx(CPUPPCState *env) 3891 { 3892 register_non_embedded_sprs(env); 3893 register_sdr1_sprs(env); 3894 register_7xx_sprs(env); 3895 3896 spr_register(env, SPR_L2CR, "L2CR", 3897 SPR_NOACCESS, SPR_NOACCESS, 3898 &spr_read_generic, spr_access_nop, 3899 0x00000000); 3900 /* Thermal management */ 3901 register_thrm_sprs(env); 3902 3903 spr_register(env, SPR_750_THRM4, "THRM4", 3904 SPR_NOACCESS, SPR_NOACCESS, 3905 &spr_read_generic, &spr_write_generic, 3906 0x00000000); 3907 /* Hardware implementation registers */ 3908 spr_register(env, SPR_750FX_HID2, "HID2", 3909 SPR_NOACCESS, SPR_NOACCESS, 3910 &spr_read_generic, &spr_write_generic, 3911 0x00000000); 3912 /* Memory management */ 3913 register_low_BATs(env); 3914 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3915 register_high_BATs(env); 3916 init_excp_7x0(env); 3917 env->dcache_line_size = 32; 3918 env->icache_line_size = 32; 3919 /* Allocate hardware IRQ controller */ 3920 ppc6xx_irq_init(env_archcpu(env)); 3921 } 3922 3923 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3924 { 3925 DeviceClass *dc = DEVICE_CLASS(oc); 3926 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3927 3928 dc->desc = "PowerPC 750FX"; 3929 pcc->init_proc = init_proc_750fx; 3930 pcc->check_pow = check_pow_hid0; 3931 pcc->check_attn = check_attn_none; 3932 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3933 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3934 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3935 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3936 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3937 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3938 PPC_SEGMENT | PPC_EXTERN; 3939 pcc->msr_mask = (1ull << MSR_POW) | 3940 (1ull << MSR_ILE) | 3941 (1ull << MSR_EE) | 3942 (1ull << MSR_PR) | 3943 (1ull << MSR_FP) | 3944 (1ull << MSR_ME) | 3945 (1ull << MSR_FE0) | 3946 (1ull << MSR_SE) | 3947 (1ull << MSR_DE) | 3948 (1ull << MSR_FE1) | 3949 (1ull << MSR_EP) | 3950 (1ull << MSR_IR) | 3951 (1ull << MSR_DR) | 3952 (1ull << MSR_PMM) | 3953 (1ull << MSR_RI) | 3954 (1ull << MSR_LE); 3955 pcc->mmu_model = POWERPC_MMU_32B; 3956 pcc->excp_model = POWERPC_EXCP_7xx; 3957 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3958 pcc->bfd_mach = bfd_mach_ppc_750; 3959 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3960 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3961 } 3962 3963 static void init_proc_750gx(CPUPPCState *env) 3964 { 3965 register_non_embedded_sprs(env); 3966 register_sdr1_sprs(env); 3967 register_7xx_sprs(env); 3968 3969 spr_register(env, SPR_L2CR, "L2CR", 3970 SPR_NOACCESS, SPR_NOACCESS, 3971 &spr_read_generic, spr_access_nop, 3972 0x00000000); 3973 /* Thermal management */ 3974 register_thrm_sprs(env); 3975 3976 spr_register(env, SPR_750_THRM4, "THRM4", 3977 SPR_NOACCESS, SPR_NOACCESS, 3978 &spr_read_generic, &spr_write_generic, 3979 0x00000000); 3980 /* Hardware implementation registers */ 3981 spr_register(env, SPR_750FX_HID2, "HID2", 3982 SPR_NOACCESS, SPR_NOACCESS, 3983 &spr_read_generic, &spr_write_generic, 3984 0x00000000); 3985 /* Memory management */ 3986 register_low_BATs(env); 3987 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3988 register_high_BATs(env); 3989 init_excp_7x0(env); 3990 env->dcache_line_size = 32; 3991 env->icache_line_size = 32; 3992 /* Allocate hardware IRQ controller */ 3993 ppc6xx_irq_init(env_archcpu(env)); 3994 } 3995 3996 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 3997 { 3998 DeviceClass *dc = DEVICE_CLASS(oc); 3999 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4000 4001 dc->desc = "PowerPC 750GX"; 4002 pcc->init_proc = init_proc_750gx; 4003 pcc->check_pow = check_pow_hid0; 4004 pcc->check_attn = check_attn_none; 4005 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4006 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4007 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4008 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4009 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4010 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4011 PPC_SEGMENT | PPC_EXTERN; 4012 pcc->msr_mask = (1ull << MSR_POW) | 4013 (1ull << MSR_ILE) | 4014 (1ull << MSR_EE) | 4015 (1ull << MSR_PR) | 4016 (1ull << MSR_FP) | 4017 (1ull << MSR_ME) | 4018 (1ull << MSR_FE0) | 4019 (1ull << MSR_SE) | 4020 (1ull << MSR_DE) | 4021 (1ull << MSR_FE1) | 4022 (1ull << MSR_EP) | 4023 (1ull << MSR_IR) | 4024 (1ull << MSR_DR) | 4025 (1ull << MSR_PMM) | 4026 (1ull << MSR_RI) | 4027 (1ull << MSR_LE); 4028 pcc->mmu_model = POWERPC_MMU_32B; 4029 pcc->excp_model = POWERPC_EXCP_7xx; 4030 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4031 pcc->bfd_mach = bfd_mach_ppc_750; 4032 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4033 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4034 } 4035 4036 static void init_proc_745(CPUPPCState *env) 4037 { 4038 register_non_embedded_sprs(env); 4039 register_sdr1_sprs(env); 4040 register_7xx_sprs(env); 4041 register_745_sprs(env); 4042 /* Thermal management */ 4043 register_thrm_sprs(env); 4044 4045 /* Memory management */ 4046 register_low_BATs(env); 4047 register_high_BATs(env); 4048 register_6xx_7xx_soft_tlb(env, 64, 2); 4049 init_excp_7x5(env); 4050 env->dcache_line_size = 32; 4051 env->icache_line_size = 32; 4052 /* Allocate hardware IRQ controller */ 4053 ppc6xx_irq_init(env_archcpu(env)); 4054 } 4055 4056 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4057 { 4058 DeviceClass *dc = DEVICE_CLASS(oc); 4059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4060 4061 dc->desc = "PowerPC 745"; 4062 pcc->init_proc = init_proc_745; 4063 pcc->check_pow = check_pow_hid0; 4064 pcc->check_attn = check_attn_none; 4065 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4067 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4069 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4071 PPC_SEGMENT | PPC_EXTERN; 4072 pcc->msr_mask = (1ull << MSR_POW) | 4073 (1ull << MSR_ILE) | 4074 (1ull << MSR_EE) | 4075 (1ull << MSR_PR) | 4076 (1ull << MSR_FP) | 4077 (1ull << MSR_ME) | 4078 (1ull << MSR_FE0) | 4079 (1ull << MSR_SE) | 4080 (1ull << MSR_DE) | 4081 (1ull << MSR_FE1) | 4082 (1ull << MSR_EP) | 4083 (1ull << MSR_IR) | 4084 (1ull << MSR_DR) | 4085 (1ull << MSR_PMM) | 4086 (1ull << MSR_RI) | 4087 (1ull << MSR_LE); 4088 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4089 pcc->excp_model = POWERPC_EXCP_7xx; 4090 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4091 pcc->bfd_mach = bfd_mach_ppc_750; 4092 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4093 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4094 } 4095 4096 static void init_proc_755(CPUPPCState *env) 4097 { 4098 init_proc_745(env); 4099 register_755_sprs(env); 4100 } 4101 4102 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4103 { 4104 DeviceClass *dc = DEVICE_CLASS(oc); 4105 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4106 4107 dc->desc = "PowerPC 755"; 4108 pcc->init_proc = init_proc_755; 4109 pcc->check_pow = check_pow_hid0; 4110 pcc->check_attn = check_attn_none; 4111 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4112 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4113 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4114 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4115 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4116 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4117 PPC_SEGMENT | PPC_EXTERN; 4118 pcc->msr_mask = (1ull << MSR_POW) | 4119 (1ull << MSR_ILE) | 4120 (1ull << MSR_EE) | 4121 (1ull << MSR_PR) | 4122 (1ull << MSR_FP) | 4123 (1ull << MSR_ME) | 4124 (1ull << MSR_FE0) | 4125 (1ull << MSR_SE) | 4126 (1ull << MSR_DE) | 4127 (1ull << MSR_FE1) | 4128 (1ull << MSR_EP) | 4129 (1ull << MSR_IR) | 4130 (1ull << MSR_DR) | 4131 (1ull << MSR_PMM) | 4132 (1ull << MSR_RI) | 4133 (1ull << MSR_LE); 4134 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4135 pcc->excp_model = POWERPC_EXCP_7xx; 4136 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4137 pcc->bfd_mach = bfd_mach_ppc_750; 4138 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4139 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4140 } 4141 4142 static void init_proc_7400(CPUPPCState *env) 4143 { 4144 register_non_embedded_sprs(env); 4145 register_sdr1_sprs(env); 4146 register_74xx_sprs(env); 4147 vscr_init(env, 0x00010000); 4148 4149 spr_register(env, SPR_UBAMR, "UBAMR", 4150 &spr_read_ureg, SPR_NOACCESS, 4151 &spr_read_ureg, SPR_NOACCESS, 4152 0x00000000); 4153 4154 spr_register(env, SPR_MSSCR1, "MSSCR1", 4155 SPR_NOACCESS, SPR_NOACCESS, 4156 &spr_read_generic, &spr_write_generic, 4157 0x00000000); 4158 /* Thermal management */ 4159 register_thrm_sprs(env); 4160 /* Memory management */ 4161 register_low_BATs(env); 4162 init_excp_7400(env); 4163 env->dcache_line_size = 32; 4164 env->icache_line_size = 32; 4165 /* Allocate hardware IRQ controller */ 4166 ppc6xx_irq_init(env_archcpu(env)); 4167 } 4168 4169 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4170 { 4171 DeviceClass *dc = DEVICE_CLASS(oc); 4172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4173 4174 dc->desc = "PowerPC 7400 (aka G4)"; 4175 pcc->init_proc = init_proc_7400; 4176 pcc->check_pow = check_pow_hid0; 4177 pcc->check_attn = check_attn_none; 4178 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4179 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4180 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4181 PPC_FLOAT_STFIWX | 4182 PPC_CACHE | PPC_CACHE_ICBI | 4183 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4184 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4185 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4186 PPC_MEM_TLBIA | 4187 PPC_SEGMENT | PPC_EXTERN | 4188 PPC_ALTIVEC; 4189 pcc->msr_mask = (1ull << MSR_VR) | 4190 (1ull << MSR_POW) | 4191 (1ull << MSR_ILE) | 4192 (1ull << MSR_EE) | 4193 (1ull << MSR_PR) | 4194 (1ull << MSR_FP) | 4195 (1ull << MSR_ME) | 4196 (1ull << MSR_FE0) | 4197 (1ull << MSR_SE) | 4198 (1ull << MSR_DE) | 4199 (1ull << MSR_FE1) | 4200 (1ull << MSR_EP) | 4201 (1ull << MSR_IR) | 4202 (1ull << MSR_DR) | 4203 (1ull << MSR_PMM) | 4204 (1ull << MSR_RI) | 4205 (1ull << MSR_LE); 4206 pcc->mmu_model = POWERPC_MMU_32B; 4207 pcc->excp_model = POWERPC_EXCP_74xx; 4208 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4209 pcc->bfd_mach = bfd_mach_ppc_7400; 4210 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4211 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4212 POWERPC_FLAG_BUS_CLK; 4213 } 4214 4215 static void init_proc_7410(CPUPPCState *env) 4216 { 4217 register_non_embedded_sprs(env); 4218 register_sdr1_sprs(env); 4219 register_74xx_sprs(env); 4220 vscr_init(env, 0x00010000); 4221 4222 spr_register(env, SPR_UBAMR, "UBAMR", 4223 &spr_read_ureg, SPR_NOACCESS, 4224 &spr_read_ureg, SPR_NOACCESS, 4225 0x00000000); 4226 /* Thermal management */ 4227 register_thrm_sprs(env); 4228 /* L2PMCR */ 4229 4230 spr_register(env, SPR_L2PMCR, "L2PMCR", 4231 SPR_NOACCESS, SPR_NOACCESS, 4232 &spr_read_generic, &spr_write_generic, 4233 0x00000000); 4234 /* LDSTDB */ 4235 4236 spr_register(env, SPR_LDSTDB, "LDSTDB", 4237 SPR_NOACCESS, SPR_NOACCESS, 4238 &spr_read_generic, &spr_write_generic, 4239 0x00000000); 4240 /* Memory management */ 4241 register_low_BATs(env); 4242 init_excp_7400(env); 4243 env->dcache_line_size = 32; 4244 env->icache_line_size = 32; 4245 /* Allocate hardware IRQ controller */ 4246 ppc6xx_irq_init(env_archcpu(env)); 4247 } 4248 4249 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4250 { 4251 DeviceClass *dc = DEVICE_CLASS(oc); 4252 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4253 4254 dc->desc = "PowerPC 7410 (aka G4)"; 4255 pcc->init_proc = init_proc_7410; 4256 pcc->check_pow = check_pow_hid0; 4257 pcc->check_attn = check_attn_none; 4258 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4259 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4260 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4261 PPC_FLOAT_STFIWX | 4262 PPC_CACHE | PPC_CACHE_ICBI | 4263 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4264 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4265 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4266 PPC_MEM_TLBIA | 4267 PPC_SEGMENT | PPC_EXTERN | 4268 PPC_ALTIVEC; 4269 pcc->msr_mask = (1ull << MSR_VR) | 4270 (1ull << MSR_POW) | 4271 (1ull << MSR_ILE) | 4272 (1ull << MSR_EE) | 4273 (1ull << MSR_PR) | 4274 (1ull << MSR_FP) | 4275 (1ull << MSR_ME) | 4276 (1ull << MSR_FE0) | 4277 (1ull << MSR_SE) | 4278 (1ull << MSR_DE) | 4279 (1ull << MSR_FE1) | 4280 (1ull << MSR_EP) | 4281 (1ull << MSR_IR) | 4282 (1ull << MSR_DR) | 4283 (1ull << MSR_PMM) | 4284 (1ull << MSR_RI) | 4285 (1ull << MSR_LE); 4286 pcc->mmu_model = POWERPC_MMU_32B; 4287 pcc->excp_model = POWERPC_EXCP_74xx; 4288 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4289 pcc->bfd_mach = bfd_mach_ppc_7400; 4290 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4291 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4292 POWERPC_FLAG_BUS_CLK; 4293 } 4294 4295 static void init_proc_7440(CPUPPCState *env) 4296 { 4297 register_non_embedded_sprs(env); 4298 register_sdr1_sprs(env); 4299 register_74xx_sprs(env); 4300 vscr_init(env, 0x00010000); 4301 4302 spr_register(env, SPR_UBAMR, "UBAMR", 4303 &spr_read_ureg, SPR_NOACCESS, 4304 &spr_read_ureg, SPR_NOACCESS, 4305 0x00000000); 4306 /* LDSTCR */ 4307 spr_register(env, SPR_LDSTCR, "LDSTCR", 4308 SPR_NOACCESS, SPR_NOACCESS, 4309 &spr_read_generic, &spr_write_generic, 4310 0x00000000); 4311 /* ICTRL */ 4312 spr_register(env, SPR_ICTRL, "ICTRL", 4313 SPR_NOACCESS, SPR_NOACCESS, 4314 &spr_read_generic, &spr_write_generic, 4315 0x00000000); 4316 /* MSSSR0 */ 4317 spr_register(env, SPR_MSSSR0, "MSSSR0", 4318 SPR_NOACCESS, SPR_NOACCESS, 4319 &spr_read_generic, &spr_write_generic, 4320 0x00000000); 4321 /* PMC */ 4322 spr_register(env, SPR_7XX_PMC5, "PMC5", 4323 SPR_NOACCESS, SPR_NOACCESS, 4324 &spr_read_generic, &spr_write_generic, 4325 0x00000000); 4326 4327 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4328 &spr_read_ureg, SPR_NOACCESS, 4329 &spr_read_ureg, SPR_NOACCESS, 4330 0x00000000); 4331 4332 spr_register(env, SPR_7XX_PMC6, "PMC6", 4333 SPR_NOACCESS, SPR_NOACCESS, 4334 &spr_read_generic, &spr_write_generic, 4335 0x00000000); 4336 4337 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4338 &spr_read_ureg, SPR_NOACCESS, 4339 &spr_read_ureg, SPR_NOACCESS, 4340 0x00000000); 4341 /* Memory management */ 4342 register_low_BATs(env); 4343 init_excp_7450(env); 4344 env->dcache_line_size = 32; 4345 env->icache_line_size = 32; 4346 /* Allocate hardware IRQ controller */ 4347 ppc6xx_irq_init(env_archcpu(env)); 4348 } 4349 4350 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4351 { 4352 DeviceClass *dc = DEVICE_CLASS(oc); 4353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4354 4355 dc->desc = "PowerPC 7440 (aka G4)"; 4356 pcc->init_proc = init_proc_7440; 4357 pcc->check_pow = check_pow_hid0_74xx; 4358 pcc->check_attn = check_attn_none; 4359 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4360 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4361 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4362 PPC_FLOAT_STFIWX | 4363 PPC_CACHE | PPC_CACHE_ICBI | 4364 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4365 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4366 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4367 PPC_MEM_TLBIA | 4368 PPC_SEGMENT | PPC_EXTERN | 4369 PPC_ALTIVEC; 4370 pcc->msr_mask = (1ull << MSR_VR) | 4371 (1ull << MSR_POW) | 4372 (1ull << MSR_ILE) | 4373 (1ull << MSR_EE) | 4374 (1ull << MSR_PR) | 4375 (1ull << MSR_FP) | 4376 (1ull << MSR_ME) | 4377 (1ull << MSR_FE0) | 4378 (1ull << MSR_SE) | 4379 (1ull << MSR_DE) | 4380 (1ull << MSR_FE1) | 4381 (1ull << MSR_EP) | 4382 (1ull << MSR_IR) | 4383 (1ull << MSR_DR) | 4384 (1ull << MSR_PMM) | 4385 (1ull << MSR_RI) | 4386 (1ull << MSR_LE); 4387 pcc->mmu_model = POWERPC_MMU_32B; 4388 pcc->excp_model = POWERPC_EXCP_74xx; 4389 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4390 pcc->bfd_mach = bfd_mach_ppc_7400; 4391 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4392 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4393 POWERPC_FLAG_BUS_CLK; 4394 } 4395 4396 static void init_proc_7450(CPUPPCState *env) 4397 { 4398 register_non_embedded_sprs(env); 4399 register_sdr1_sprs(env); 4400 register_74xx_sprs(env); 4401 vscr_init(env, 0x00010000); 4402 /* Level 3 cache control */ 4403 register_l3_ctrl(env); 4404 /* L3ITCR1 */ 4405 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4406 SPR_NOACCESS, SPR_NOACCESS, 4407 &spr_read_generic, &spr_write_generic, 4408 0x00000000); 4409 /* L3ITCR2 */ 4410 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4411 SPR_NOACCESS, SPR_NOACCESS, 4412 &spr_read_generic, &spr_write_generic, 4413 0x00000000); 4414 /* L3ITCR3 */ 4415 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4416 SPR_NOACCESS, SPR_NOACCESS, 4417 &spr_read_generic, &spr_write_generic, 4418 0x00000000); 4419 /* L3OHCR */ 4420 spr_register(env, SPR_L3OHCR, "L3OHCR", 4421 SPR_NOACCESS, SPR_NOACCESS, 4422 &spr_read_generic, &spr_write_generic, 4423 0x00000000); 4424 4425 spr_register(env, SPR_UBAMR, "UBAMR", 4426 &spr_read_ureg, SPR_NOACCESS, 4427 &spr_read_ureg, SPR_NOACCESS, 4428 0x00000000); 4429 /* LDSTCR */ 4430 spr_register(env, SPR_LDSTCR, "LDSTCR", 4431 SPR_NOACCESS, SPR_NOACCESS, 4432 &spr_read_generic, &spr_write_generic, 4433 0x00000000); 4434 /* ICTRL */ 4435 spr_register(env, SPR_ICTRL, "ICTRL", 4436 SPR_NOACCESS, SPR_NOACCESS, 4437 &spr_read_generic, &spr_write_generic, 4438 0x00000000); 4439 /* MSSSR0 */ 4440 spr_register(env, SPR_MSSSR0, "MSSSR0", 4441 SPR_NOACCESS, SPR_NOACCESS, 4442 &spr_read_generic, &spr_write_generic, 4443 0x00000000); 4444 /* PMC */ 4445 spr_register(env, SPR_7XX_PMC5, "PMC5", 4446 SPR_NOACCESS, SPR_NOACCESS, 4447 &spr_read_generic, &spr_write_generic, 4448 0x00000000); 4449 4450 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4451 &spr_read_ureg, SPR_NOACCESS, 4452 &spr_read_ureg, SPR_NOACCESS, 4453 0x00000000); 4454 4455 spr_register(env, SPR_7XX_PMC6, "PMC6", 4456 SPR_NOACCESS, SPR_NOACCESS, 4457 &spr_read_generic, &spr_write_generic, 4458 0x00000000); 4459 4460 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4461 &spr_read_ureg, SPR_NOACCESS, 4462 &spr_read_ureg, SPR_NOACCESS, 4463 0x00000000); 4464 /* Memory management */ 4465 register_low_BATs(env); 4466 init_excp_7450(env); 4467 env->dcache_line_size = 32; 4468 env->icache_line_size = 32; 4469 /* Allocate hardware IRQ controller */ 4470 ppc6xx_irq_init(env_archcpu(env)); 4471 } 4472 4473 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4474 { 4475 DeviceClass *dc = DEVICE_CLASS(oc); 4476 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4477 4478 dc->desc = "PowerPC 7450 (aka G4)"; 4479 pcc->init_proc = init_proc_7450; 4480 pcc->check_pow = check_pow_hid0_74xx; 4481 pcc->check_attn = check_attn_none; 4482 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4483 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4484 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4485 PPC_FLOAT_STFIWX | 4486 PPC_CACHE | PPC_CACHE_ICBI | 4487 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4488 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4489 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4490 PPC_MEM_TLBIA | 4491 PPC_SEGMENT | PPC_EXTERN | 4492 PPC_ALTIVEC; 4493 pcc->msr_mask = (1ull << MSR_VR) | 4494 (1ull << MSR_POW) | 4495 (1ull << MSR_ILE) | 4496 (1ull << MSR_EE) | 4497 (1ull << MSR_PR) | 4498 (1ull << MSR_FP) | 4499 (1ull << MSR_ME) | 4500 (1ull << MSR_FE0) | 4501 (1ull << MSR_SE) | 4502 (1ull << MSR_DE) | 4503 (1ull << MSR_FE1) | 4504 (1ull << MSR_EP) | 4505 (1ull << MSR_IR) | 4506 (1ull << MSR_DR) | 4507 (1ull << MSR_PMM) | 4508 (1ull << MSR_RI) | 4509 (1ull << MSR_LE); 4510 pcc->mmu_model = POWERPC_MMU_32B; 4511 pcc->excp_model = POWERPC_EXCP_74xx; 4512 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4513 pcc->bfd_mach = bfd_mach_ppc_7400; 4514 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4515 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4516 POWERPC_FLAG_BUS_CLK; 4517 } 4518 4519 static void init_proc_7445(CPUPPCState *env) 4520 { 4521 register_non_embedded_sprs(env); 4522 register_sdr1_sprs(env); 4523 register_74xx_sprs(env); 4524 vscr_init(env, 0x00010000); 4525 /* LDSTCR */ 4526 spr_register(env, SPR_LDSTCR, "LDSTCR", 4527 SPR_NOACCESS, SPR_NOACCESS, 4528 &spr_read_generic, &spr_write_generic, 4529 0x00000000); 4530 /* ICTRL */ 4531 spr_register(env, SPR_ICTRL, "ICTRL", 4532 SPR_NOACCESS, SPR_NOACCESS, 4533 &spr_read_generic, &spr_write_generic, 4534 0x00000000); 4535 /* MSSSR0 */ 4536 spr_register(env, SPR_MSSSR0, "MSSSR0", 4537 SPR_NOACCESS, SPR_NOACCESS, 4538 &spr_read_generic, &spr_write_generic, 4539 0x00000000); 4540 /* PMC */ 4541 spr_register(env, SPR_7XX_PMC5, "PMC5", 4542 SPR_NOACCESS, SPR_NOACCESS, 4543 &spr_read_generic, &spr_write_generic, 4544 0x00000000); 4545 4546 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4547 &spr_read_ureg, SPR_NOACCESS, 4548 &spr_read_ureg, SPR_NOACCESS, 4549 0x00000000); 4550 4551 spr_register(env, SPR_7XX_PMC6, "PMC6", 4552 SPR_NOACCESS, SPR_NOACCESS, 4553 &spr_read_generic, &spr_write_generic, 4554 0x00000000); 4555 4556 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4557 &spr_read_ureg, SPR_NOACCESS, 4558 &spr_read_ureg, SPR_NOACCESS, 4559 0x00000000); 4560 /* SPRGs */ 4561 spr_register(env, SPR_SPRG4, "SPRG4", 4562 SPR_NOACCESS, SPR_NOACCESS, 4563 &spr_read_generic, &spr_write_generic, 4564 0x00000000); 4565 spr_register(env, SPR_USPRG4, "USPRG4", 4566 &spr_read_ureg, SPR_NOACCESS, 4567 &spr_read_ureg, SPR_NOACCESS, 4568 0x00000000); 4569 spr_register(env, SPR_SPRG5, "SPRG5", 4570 SPR_NOACCESS, SPR_NOACCESS, 4571 &spr_read_generic, &spr_write_generic, 4572 0x00000000); 4573 spr_register(env, SPR_USPRG5, "USPRG5", 4574 &spr_read_ureg, SPR_NOACCESS, 4575 &spr_read_ureg, SPR_NOACCESS, 4576 0x00000000); 4577 spr_register(env, SPR_SPRG6, "SPRG6", 4578 SPR_NOACCESS, SPR_NOACCESS, 4579 &spr_read_generic, &spr_write_generic, 4580 0x00000000); 4581 spr_register(env, SPR_USPRG6, "USPRG6", 4582 &spr_read_ureg, SPR_NOACCESS, 4583 &spr_read_ureg, SPR_NOACCESS, 4584 0x00000000); 4585 spr_register(env, SPR_SPRG7, "SPRG7", 4586 SPR_NOACCESS, SPR_NOACCESS, 4587 &spr_read_generic, &spr_write_generic, 4588 0x00000000); 4589 spr_register(env, SPR_USPRG7, "USPRG7", 4590 &spr_read_ureg, SPR_NOACCESS, 4591 &spr_read_ureg, SPR_NOACCESS, 4592 0x00000000); 4593 /* Memory management */ 4594 register_low_BATs(env); 4595 register_high_BATs(env); 4596 init_excp_7450(env); 4597 env->dcache_line_size = 32; 4598 env->icache_line_size = 32; 4599 /* Allocate hardware IRQ controller */ 4600 ppc6xx_irq_init(env_archcpu(env)); 4601 } 4602 4603 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4604 { 4605 DeviceClass *dc = DEVICE_CLASS(oc); 4606 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4607 4608 dc->desc = "PowerPC 7445 (aka G4)"; 4609 pcc->init_proc = init_proc_7445; 4610 pcc->check_pow = check_pow_hid0_74xx; 4611 pcc->check_attn = check_attn_none; 4612 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4613 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4614 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4615 PPC_FLOAT_STFIWX | 4616 PPC_CACHE | PPC_CACHE_ICBI | 4617 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4618 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4620 PPC_MEM_TLBIA | 4621 PPC_SEGMENT | PPC_EXTERN | 4622 PPC_ALTIVEC; 4623 pcc->msr_mask = (1ull << MSR_VR) | 4624 (1ull << MSR_POW) | 4625 (1ull << MSR_ILE) | 4626 (1ull << MSR_EE) | 4627 (1ull << MSR_PR) | 4628 (1ull << MSR_FP) | 4629 (1ull << MSR_ME) | 4630 (1ull << MSR_FE0) | 4631 (1ull << MSR_SE) | 4632 (1ull << MSR_DE) | 4633 (1ull << MSR_FE1) | 4634 (1ull << MSR_EP) | 4635 (1ull << MSR_IR) | 4636 (1ull << MSR_DR) | 4637 (1ull << MSR_PMM) | 4638 (1ull << MSR_RI) | 4639 (1ull << MSR_LE); 4640 pcc->mmu_model = POWERPC_MMU_32B; 4641 pcc->excp_model = POWERPC_EXCP_74xx; 4642 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4643 pcc->bfd_mach = bfd_mach_ppc_7400; 4644 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4645 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4646 POWERPC_FLAG_BUS_CLK; 4647 } 4648 4649 static void init_proc_7455(CPUPPCState *env) 4650 { 4651 register_non_embedded_sprs(env); 4652 register_sdr1_sprs(env); 4653 register_74xx_sprs(env); 4654 vscr_init(env, 0x00010000); 4655 /* Level 3 cache control */ 4656 register_l3_ctrl(env); 4657 /* LDSTCR */ 4658 spr_register(env, SPR_LDSTCR, "LDSTCR", 4659 SPR_NOACCESS, SPR_NOACCESS, 4660 &spr_read_generic, &spr_write_generic, 4661 0x00000000); 4662 /* ICTRL */ 4663 spr_register(env, SPR_ICTRL, "ICTRL", 4664 SPR_NOACCESS, SPR_NOACCESS, 4665 &spr_read_generic, &spr_write_generic, 4666 0x00000000); 4667 /* MSSSR0 */ 4668 spr_register(env, SPR_MSSSR0, "MSSSR0", 4669 SPR_NOACCESS, SPR_NOACCESS, 4670 &spr_read_generic, &spr_write_generic, 4671 0x00000000); 4672 /* PMC */ 4673 spr_register(env, SPR_7XX_PMC5, "PMC5", 4674 SPR_NOACCESS, SPR_NOACCESS, 4675 &spr_read_generic, &spr_write_generic, 4676 0x00000000); 4677 4678 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4679 &spr_read_ureg, SPR_NOACCESS, 4680 &spr_read_ureg, SPR_NOACCESS, 4681 0x00000000); 4682 4683 spr_register(env, SPR_7XX_PMC6, "PMC6", 4684 SPR_NOACCESS, SPR_NOACCESS, 4685 &spr_read_generic, &spr_write_generic, 4686 0x00000000); 4687 4688 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4689 &spr_read_ureg, SPR_NOACCESS, 4690 &spr_read_ureg, SPR_NOACCESS, 4691 0x00000000); 4692 /* SPRGs */ 4693 spr_register(env, SPR_SPRG4, "SPRG4", 4694 SPR_NOACCESS, SPR_NOACCESS, 4695 &spr_read_generic, &spr_write_generic, 4696 0x00000000); 4697 spr_register(env, SPR_USPRG4, "USPRG4", 4698 &spr_read_ureg, SPR_NOACCESS, 4699 &spr_read_ureg, SPR_NOACCESS, 4700 0x00000000); 4701 spr_register(env, SPR_SPRG5, "SPRG5", 4702 SPR_NOACCESS, SPR_NOACCESS, 4703 &spr_read_generic, &spr_write_generic, 4704 0x00000000); 4705 spr_register(env, SPR_USPRG5, "USPRG5", 4706 &spr_read_ureg, SPR_NOACCESS, 4707 &spr_read_ureg, SPR_NOACCESS, 4708 0x00000000); 4709 spr_register(env, SPR_SPRG6, "SPRG6", 4710 SPR_NOACCESS, SPR_NOACCESS, 4711 &spr_read_generic, &spr_write_generic, 4712 0x00000000); 4713 spr_register(env, SPR_USPRG6, "USPRG6", 4714 &spr_read_ureg, SPR_NOACCESS, 4715 &spr_read_ureg, SPR_NOACCESS, 4716 0x00000000); 4717 spr_register(env, SPR_SPRG7, "SPRG7", 4718 SPR_NOACCESS, SPR_NOACCESS, 4719 &spr_read_generic, &spr_write_generic, 4720 0x00000000); 4721 spr_register(env, SPR_USPRG7, "USPRG7", 4722 &spr_read_ureg, SPR_NOACCESS, 4723 &spr_read_ureg, SPR_NOACCESS, 4724 0x00000000); 4725 /* Memory management */ 4726 register_low_BATs(env); 4727 register_high_BATs(env); 4728 init_excp_7450(env); 4729 env->dcache_line_size = 32; 4730 env->icache_line_size = 32; 4731 /* Allocate hardware IRQ controller */ 4732 ppc6xx_irq_init(env_archcpu(env)); 4733 } 4734 4735 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4736 { 4737 DeviceClass *dc = DEVICE_CLASS(oc); 4738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4739 4740 dc->desc = "PowerPC 7455 (aka G4)"; 4741 pcc->init_proc = init_proc_7455; 4742 pcc->check_pow = check_pow_hid0_74xx; 4743 pcc->check_attn = check_attn_none; 4744 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4745 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4746 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4747 PPC_FLOAT_STFIWX | 4748 PPC_CACHE | PPC_CACHE_ICBI | 4749 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4750 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4751 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4752 PPC_MEM_TLBIA | 4753 PPC_SEGMENT | PPC_EXTERN | 4754 PPC_ALTIVEC; 4755 pcc->msr_mask = (1ull << MSR_VR) | 4756 (1ull << MSR_POW) | 4757 (1ull << MSR_ILE) | 4758 (1ull << MSR_EE) | 4759 (1ull << MSR_PR) | 4760 (1ull << MSR_FP) | 4761 (1ull << MSR_ME) | 4762 (1ull << MSR_FE0) | 4763 (1ull << MSR_SE) | 4764 (1ull << MSR_DE) | 4765 (1ull << MSR_FE1) | 4766 (1ull << MSR_EP) | 4767 (1ull << MSR_IR) | 4768 (1ull << MSR_DR) | 4769 (1ull << MSR_PMM) | 4770 (1ull << MSR_RI) | 4771 (1ull << MSR_LE); 4772 pcc->mmu_model = POWERPC_MMU_32B; 4773 pcc->excp_model = POWERPC_EXCP_74xx; 4774 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4775 pcc->bfd_mach = bfd_mach_ppc_7400; 4776 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4777 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4778 POWERPC_FLAG_BUS_CLK; 4779 } 4780 4781 static void init_proc_7457(CPUPPCState *env) 4782 { 4783 register_non_embedded_sprs(env); 4784 register_sdr1_sprs(env); 4785 register_74xx_sprs(env); 4786 vscr_init(env, 0x00010000); 4787 /* Level 3 cache control */ 4788 register_l3_ctrl(env); 4789 /* L3ITCR1 */ 4790 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4791 SPR_NOACCESS, SPR_NOACCESS, 4792 &spr_read_generic, &spr_write_generic, 4793 0x00000000); 4794 /* L3ITCR2 */ 4795 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4796 SPR_NOACCESS, SPR_NOACCESS, 4797 &spr_read_generic, &spr_write_generic, 4798 0x00000000); 4799 /* L3ITCR3 */ 4800 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4801 SPR_NOACCESS, SPR_NOACCESS, 4802 &spr_read_generic, &spr_write_generic, 4803 0x00000000); 4804 /* L3OHCR */ 4805 spr_register(env, SPR_L3OHCR, "L3OHCR", 4806 SPR_NOACCESS, SPR_NOACCESS, 4807 &spr_read_generic, &spr_write_generic, 4808 0x00000000); 4809 /* LDSTCR */ 4810 spr_register(env, SPR_LDSTCR, "LDSTCR", 4811 SPR_NOACCESS, SPR_NOACCESS, 4812 &spr_read_generic, &spr_write_generic, 4813 0x00000000); 4814 /* ICTRL */ 4815 spr_register(env, SPR_ICTRL, "ICTRL", 4816 SPR_NOACCESS, SPR_NOACCESS, 4817 &spr_read_generic, &spr_write_generic, 4818 0x00000000); 4819 /* MSSSR0 */ 4820 spr_register(env, SPR_MSSSR0, "MSSSR0", 4821 SPR_NOACCESS, SPR_NOACCESS, 4822 &spr_read_generic, &spr_write_generic, 4823 0x00000000); 4824 /* PMC */ 4825 spr_register(env, SPR_7XX_PMC5, "PMC5", 4826 SPR_NOACCESS, SPR_NOACCESS, 4827 &spr_read_generic, &spr_write_generic, 4828 0x00000000); 4829 4830 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4831 &spr_read_ureg, SPR_NOACCESS, 4832 &spr_read_ureg, SPR_NOACCESS, 4833 0x00000000); 4834 4835 spr_register(env, SPR_7XX_PMC6, "PMC6", 4836 SPR_NOACCESS, SPR_NOACCESS, 4837 &spr_read_generic, &spr_write_generic, 4838 0x00000000); 4839 4840 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4841 &spr_read_ureg, SPR_NOACCESS, 4842 &spr_read_ureg, SPR_NOACCESS, 4843 0x00000000); 4844 /* SPRGs */ 4845 spr_register(env, SPR_SPRG4, "SPRG4", 4846 SPR_NOACCESS, SPR_NOACCESS, 4847 &spr_read_generic, &spr_write_generic, 4848 0x00000000); 4849 spr_register(env, SPR_USPRG4, "USPRG4", 4850 &spr_read_ureg, SPR_NOACCESS, 4851 &spr_read_ureg, SPR_NOACCESS, 4852 0x00000000); 4853 spr_register(env, SPR_SPRG5, "SPRG5", 4854 SPR_NOACCESS, SPR_NOACCESS, 4855 &spr_read_generic, &spr_write_generic, 4856 0x00000000); 4857 spr_register(env, SPR_USPRG5, "USPRG5", 4858 &spr_read_ureg, SPR_NOACCESS, 4859 &spr_read_ureg, SPR_NOACCESS, 4860 0x00000000); 4861 spr_register(env, SPR_SPRG6, "SPRG6", 4862 SPR_NOACCESS, SPR_NOACCESS, 4863 &spr_read_generic, &spr_write_generic, 4864 0x00000000); 4865 spr_register(env, SPR_USPRG6, "USPRG6", 4866 &spr_read_ureg, SPR_NOACCESS, 4867 &spr_read_ureg, SPR_NOACCESS, 4868 0x00000000); 4869 spr_register(env, SPR_SPRG7, "SPRG7", 4870 SPR_NOACCESS, SPR_NOACCESS, 4871 &spr_read_generic, &spr_write_generic, 4872 0x00000000); 4873 spr_register(env, SPR_USPRG7, "USPRG7", 4874 &spr_read_ureg, SPR_NOACCESS, 4875 &spr_read_ureg, SPR_NOACCESS, 4876 0x00000000); 4877 /* Memory management */ 4878 register_low_BATs(env); 4879 register_high_BATs(env); 4880 init_excp_7450(env); 4881 env->dcache_line_size = 32; 4882 env->icache_line_size = 32; 4883 /* Allocate hardware IRQ controller */ 4884 ppc6xx_irq_init(env_archcpu(env)); 4885 } 4886 4887 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4888 { 4889 DeviceClass *dc = DEVICE_CLASS(oc); 4890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4891 4892 dc->desc = "PowerPC 7457 (aka G4)"; 4893 pcc->init_proc = init_proc_7457; 4894 pcc->check_pow = check_pow_hid0_74xx; 4895 pcc->check_attn = check_attn_none; 4896 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4897 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4898 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4899 PPC_FLOAT_STFIWX | 4900 PPC_CACHE | PPC_CACHE_ICBI | 4901 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4902 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4903 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4904 PPC_MEM_TLBIA | 4905 PPC_SEGMENT | PPC_EXTERN | 4906 PPC_ALTIVEC; 4907 pcc->msr_mask = (1ull << MSR_VR) | 4908 (1ull << MSR_POW) | 4909 (1ull << MSR_ILE) | 4910 (1ull << MSR_EE) | 4911 (1ull << MSR_PR) | 4912 (1ull << MSR_FP) | 4913 (1ull << MSR_ME) | 4914 (1ull << MSR_FE0) | 4915 (1ull << MSR_SE) | 4916 (1ull << MSR_DE) | 4917 (1ull << MSR_FE1) | 4918 (1ull << MSR_EP) | 4919 (1ull << MSR_IR) | 4920 (1ull << MSR_DR) | 4921 (1ull << MSR_PMM) | 4922 (1ull << MSR_RI) | 4923 (1ull << MSR_LE); 4924 pcc->mmu_model = POWERPC_MMU_32B; 4925 pcc->excp_model = POWERPC_EXCP_74xx; 4926 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4927 pcc->bfd_mach = bfd_mach_ppc_7400; 4928 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4929 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4930 POWERPC_FLAG_BUS_CLK; 4931 } 4932 4933 static void init_proc_e600(CPUPPCState *env) 4934 { 4935 register_non_embedded_sprs(env); 4936 register_sdr1_sprs(env); 4937 register_74xx_sprs(env); 4938 vscr_init(env, 0x00010000); 4939 4940 spr_register(env, SPR_UBAMR, "UBAMR", 4941 &spr_read_ureg, SPR_NOACCESS, 4942 &spr_read_ureg, SPR_NOACCESS, 4943 0x00000000); 4944 4945 spr_register(env, SPR_LDSTCR, "LDSTCR", 4946 SPR_NOACCESS, SPR_NOACCESS, 4947 &spr_read_generic, &spr_write_generic, 4948 0x00000000); 4949 4950 spr_register(env, SPR_ICTRL, "ICTRL", 4951 SPR_NOACCESS, SPR_NOACCESS, 4952 &spr_read_generic, &spr_write_generic, 4953 0x00000000); 4954 4955 spr_register(env, SPR_MSSSR0, "MSSSR0", 4956 SPR_NOACCESS, SPR_NOACCESS, 4957 &spr_read_generic, &spr_write_generic, 4958 0x00000000); 4959 4960 spr_register(env, SPR_7XX_PMC5, "PMC5", 4961 SPR_NOACCESS, SPR_NOACCESS, 4962 &spr_read_generic, &spr_write_generic, 4963 0x00000000); 4964 4965 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4966 &spr_read_ureg, SPR_NOACCESS, 4967 &spr_read_ureg, SPR_NOACCESS, 4968 0x00000000); 4969 4970 spr_register(env, SPR_7XX_PMC6, "PMC6", 4971 SPR_NOACCESS, SPR_NOACCESS, 4972 &spr_read_generic, &spr_write_generic, 4973 0x00000000); 4974 4975 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4976 &spr_read_ureg, SPR_NOACCESS, 4977 &spr_read_ureg, SPR_NOACCESS, 4978 0x00000000); 4979 /* SPRGs */ 4980 spr_register(env, SPR_SPRG4, "SPRG4", 4981 SPR_NOACCESS, SPR_NOACCESS, 4982 &spr_read_generic, &spr_write_generic, 4983 0x00000000); 4984 spr_register(env, SPR_USPRG4, "USPRG4", 4985 &spr_read_ureg, SPR_NOACCESS, 4986 &spr_read_ureg, SPR_NOACCESS, 4987 0x00000000); 4988 spr_register(env, SPR_SPRG5, "SPRG5", 4989 SPR_NOACCESS, SPR_NOACCESS, 4990 &spr_read_generic, &spr_write_generic, 4991 0x00000000); 4992 spr_register(env, SPR_USPRG5, "USPRG5", 4993 &spr_read_ureg, SPR_NOACCESS, 4994 &spr_read_ureg, SPR_NOACCESS, 4995 0x00000000); 4996 spr_register(env, SPR_SPRG6, "SPRG6", 4997 SPR_NOACCESS, SPR_NOACCESS, 4998 &spr_read_generic, &spr_write_generic, 4999 0x00000000); 5000 spr_register(env, SPR_USPRG6, "USPRG6", 5001 &spr_read_ureg, SPR_NOACCESS, 5002 &spr_read_ureg, SPR_NOACCESS, 5003 0x00000000); 5004 spr_register(env, SPR_SPRG7, "SPRG7", 5005 SPR_NOACCESS, SPR_NOACCESS, 5006 &spr_read_generic, &spr_write_generic, 5007 0x00000000); 5008 spr_register(env, SPR_USPRG7, "USPRG7", 5009 &spr_read_ureg, SPR_NOACCESS, 5010 &spr_read_ureg, SPR_NOACCESS, 5011 0x00000000); 5012 /* Memory management */ 5013 register_low_BATs(env); 5014 register_high_BATs(env); 5015 init_excp_7450(env); 5016 env->dcache_line_size = 32; 5017 env->icache_line_size = 32; 5018 /* Allocate hardware IRQ controller */ 5019 ppc6xx_irq_init(env_archcpu(env)); 5020 } 5021 5022 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5023 { 5024 DeviceClass *dc = DEVICE_CLASS(oc); 5025 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5026 5027 dc->desc = "PowerPC e600"; 5028 pcc->init_proc = init_proc_e600; 5029 pcc->check_pow = check_pow_hid0_74xx; 5030 pcc->check_attn = check_attn_none; 5031 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5032 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5033 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5034 PPC_FLOAT_STFIWX | 5035 PPC_CACHE | PPC_CACHE_ICBI | 5036 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5037 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5038 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5039 PPC_MEM_TLBIA | 5040 PPC_SEGMENT | PPC_EXTERN | 5041 PPC_ALTIVEC; 5042 pcc->insns_flags2 = PPC_NONE; 5043 pcc->msr_mask = (1ull << MSR_VR) | 5044 (1ull << MSR_POW) | 5045 (1ull << MSR_ILE) | 5046 (1ull << MSR_EE) | 5047 (1ull << MSR_PR) | 5048 (1ull << MSR_FP) | 5049 (1ull << MSR_ME) | 5050 (1ull << MSR_FE0) | 5051 (1ull << MSR_SE) | 5052 (1ull << MSR_DE) | 5053 (1ull << MSR_FE1) | 5054 (1ull << MSR_EP) | 5055 (1ull << MSR_IR) | 5056 (1ull << MSR_DR) | 5057 (1ull << MSR_PMM) | 5058 (1ull << MSR_RI) | 5059 (1ull << MSR_LE); 5060 pcc->mmu_model = POWERPC_MMU_32B; 5061 pcc->excp_model = POWERPC_EXCP_74xx; 5062 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5063 pcc->bfd_mach = bfd_mach_ppc_7400; 5064 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5065 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5066 POWERPC_FLAG_BUS_CLK; 5067 } 5068 5069 #if defined(TARGET_PPC64) 5070 #if defined(CONFIG_USER_ONLY) 5071 #define POWERPC970_HID5_INIT 0x00000080 5072 #else 5073 #define POWERPC970_HID5_INIT 0x00000000 5074 #endif 5075 5076 static int check_pow_970(CPUPPCState *env) 5077 { 5078 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5079 return 1; 5080 } 5081 5082 return 0; 5083 } 5084 5085 static void register_970_hid_sprs(CPUPPCState *env) 5086 { 5087 /* Hardware implementation registers */ 5088 spr_register(env, SPR_HID0, "HID0", 5089 SPR_NOACCESS, SPR_NOACCESS, 5090 &spr_read_generic, &spr_write_clear, 5091 0x60000000); 5092 spr_register(env, SPR_HID1, "HID1", 5093 SPR_NOACCESS, SPR_NOACCESS, 5094 &spr_read_generic, &spr_write_generic, 5095 0x00000000); 5096 spr_register(env, SPR_970_HID5, "HID5", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_generic, &spr_write_generic, 5099 POWERPC970_HID5_INIT); 5100 } 5101 5102 static void register_970_hior_sprs(CPUPPCState *env) 5103 { 5104 spr_register(env, SPR_HIOR, "HIOR", 5105 SPR_NOACCESS, SPR_NOACCESS, 5106 &spr_read_hior, &spr_write_hior, 5107 0x00000000); 5108 } 5109 5110 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5111 { 5112 spr_register(env, SPR_CTRL, "CTRL", 5113 SPR_NOACCESS, SPR_NOACCESS, 5114 SPR_NOACCESS, &spr_write_CTRL, 5115 0x00000000); 5116 spr_register(env, SPR_UCTRL, "UCTRL", 5117 &spr_read_ureg, SPR_NOACCESS, 5118 &spr_read_ureg, SPR_NOACCESS, 5119 0x00000000); 5120 } 5121 5122 static void register_book3s_altivec_sprs(CPUPPCState *env) 5123 { 5124 if (!(env->insns_flags & PPC_ALTIVEC)) { 5125 return; 5126 } 5127 5128 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5129 &spr_read_generic, &spr_write_generic32, 5130 &spr_read_generic, &spr_write_generic32, 5131 KVM_REG_PPC_VRSAVE, 0x00000000); 5132 5133 } 5134 5135 static void register_book3s_dbg_sprs(CPUPPCState *env) 5136 { 5137 /* 5138 * TODO: different specs define different scopes for these, 5139 * will have to address this: 5140 * 970: super/write and super/read 5141 * powerisa 2.03..2.04: hypv/write and super/read. 5142 * powerisa 2.05 and newer: hypv/write and hypv/read. 5143 */ 5144 spr_register_kvm(env, SPR_DABR, "DABR", 5145 SPR_NOACCESS, SPR_NOACCESS, 5146 &spr_read_generic, &spr_write_generic, 5147 KVM_REG_PPC_DABR, 0x00000000); 5148 spr_register_kvm(env, SPR_DABRX, "DABRX", 5149 SPR_NOACCESS, SPR_NOACCESS, 5150 &spr_read_generic, &spr_write_generic, 5151 KVM_REG_PPC_DABRX, 0x00000000); 5152 } 5153 5154 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5155 { 5156 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5157 SPR_NOACCESS, SPR_NOACCESS, 5158 SPR_NOACCESS, SPR_NOACCESS, 5159 &spr_read_generic, &spr_write_dawr0, 5160 KVM_REG_PPC_DAWR, 0x00000000); 5161 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5162 SPR_NOACCESS, SPR_NOACCESS, 5163 SPR_NOACCESS, SPR_NOACCESS, 5164 &spr_read_generic, &spr_write_dawrx0, 5165 KVM_REG_PPC_DAWRX, 0x00000000); 5166 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5167 SPR_NOACCESS, SPR_NOACCESS, 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 &spr_read_generic, &spr_write_ciabr, 5170 KVM_REG_PPC_CIABR, 0x00000000); 5171 } 5172 5173 static void register_970_dbg_sprs(CPUPPCState *env) 5174 { 5175 /* Breakpoints */ 5176 spr_register(env, SPR_IABR, "IABR", 5177 SPR_NOACCESS, SPR_NOACCESS, 5178 &spr_read_generic, &spr_write_generic, 5179 0x00000000); 5180 } 5181 5182 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5183 { 5184 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5185 SPR_NOACCESS, SPR_NOACCESS, 5186 &spr_read_generic, &spr_write_MMCR0, 5187 KVM_REG_PPC_MMCR0, 0x80000000); 5188 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5189 SPR_NOACCESS, SPR_NOACCESS, 5190 &spr_read_generic, &spr_write_MMCR1, 5191 KVM_REG_PPC_MMCR1, 0x00000000); 5192 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5193 SPR_NOACCESS, SPR_NOACCESS, 5194 &spr_read_generic, &spr_write_MMCRA, 5195 KVM_REG_PPC_MMCRA, 0x00000000); 5196 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5197 SPR_NOACCESS, SPR_NOACCESS, 5198 &spr_read_PMC, &spr_write_PMC, 5199 KVM_REG_PPC_PMC1, 0x00000000); 5200 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5201 SPR_NOACCESS, SPR_NOACCESS, 5202 &spr_read_PMC, &spr_write_PMC, 5203 KVM_REG_PPC_PMC2, 0x00000000); 5204 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5205 SPR_NOACCESS, SPR_NOACCESS, 5206 &spr_read_PMC, &spr_write_PMC, 5207 KVM_REG_PPC_PMC3, 0x00000000); 5208 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5209 SPR_NOACCESS, SPR_NOACCESS, 5210 &spr_read_PMC, &spr_write_PMC, 5211 KVM_REG_PPC_PMC4, 0x00000000); 5212 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5213 SPR_NOACCESS, SPR_NOACCESS, 5214 &spr_read_PMC, &spr_write_PMC, 5215 KVM_REG_PPC_PMC5, 0x00000000); 5216 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5217 SPR_NOACCESS, SPR_NOACCESS, 5218 &spr_read_PMC, &spr_write_PMC, 5219 KVM_REG_PPC_PMC6, 0x00000000); 5220 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5221 SPR_NOACCESS, SPR_NOACCESS, 5222 &spr_read_generic, &spr_write_generic, 5223 KVM_REG_PPC_SIAR, 0x00000000); 5224 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5225 SPR_NOACCESS, SPR_NOACCESS, 5226 &spr_read_generic, &spr_write_generic, 5227 KVM_REG_PPC_SDAR, 0x00000000); 5228 } 5229 5230 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5231 { 5232 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5233 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5234 &spr_read_ureg, &spr_write_ureg, 5235 0x80000000); 5236 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5237 &spr_read_ureg, SPR_NOACCESS, 5238 &spr_read_ureg, &spr_write_ureg, 5239 0x00000000); 5240 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5241 &spr_read_ureg, SPR_NOACCESS, 5242 &spr_read_ureg, &spr_write_ureg, 5243 0x00000000); 5244 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5245 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5246 &spr_read_ureg, &spr_write_ureg, 5247 0x00000000); 5248 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5249 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5250 &spr_read_ureg, &spr_write_ureg, 5251 0x00000000); 5252 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5253 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5254 &spr_read_ureg, &spr_write_ureg, 5255 0x00000000); 5256 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5257 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5258 &spr_read_ureg, &spr_write_ureg, 5259 0x00000000); 5260 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5261 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5262 &spr_read_ureg, &spr_write_ureg, 5263 0x00000000); 5264 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5265 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5266 &spr_read_ureg, &spr_write_ureg, 5267 0x00000000); 5268 spr_register(env, SPR_POWER_USIAR, "USIAR", 5269 &spr_read_ureg, SPR_NOACCESS, 5270 &spr_read_ureg, &spr_write_ureg, 5271 0x00000000); 5272 spr_register(env, SPR_POWER_USDAR, "USDAR", 5273 &spr_read_ureg, SPR_NOACCESS, 5274 &spr_read_ureg, &spr_write_ureg, 5275 0x00000000); 5276 } 5277 5278 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5279 { 5280 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5281 SPR_NOACCESS, SPR_NOACCESS, 5282 &spr_read_generic, &spr_write_generic, 5283 KVM_REG_PPC_PMC7, 0x00000000); 5284 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5285 SPR_NOACCESS, SPR_NOACCESS, 5286 &spr_read_generic, &spr_write_generic, 5287 KVM_REG_PPC_PMC8, 0x00000000); 5288 } 5289 5290 static void register_970_pmu_user_sprs(CPUPPCState *env) 5291 { 5292 spr_register(env, SPR_970_UPMC7, "UPMC7", 5293 &spr_read_ureg, SPR_NOACCESS, 5294 &spr_read_ureg, &spr_write_ureg, 5295 0x00000000); 5296 spr_register(env, SPR_970_UPMC8, "UPMC8", 5297 &spr_read_ureg, SPR_NOACCESS, 5298 &spr_read_ureg, &spr_write_ureg, 5299 0x00000000); 5300 } 5301 5302 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5303 { 5304 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5305 SPR_NOACCESS, SPR_NOACCESS, 5306 &spr_read_generic, &spr_write_generic, 5307 KVM_REG_PPC_MMCR2, 0x00000000); 5308 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5309 SPR_NOACCESS, SPR_NOACCESS, 5310 &spr_read_generic, &spr_write_generic, 5311 KVM_REG_PPC_MMCRS, 0x00000000); 5312 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5313 SPR_NOACCESS, SPR_NOACCESS, 5314 &spr_read_generic, &spr_write_generic, 5315 KVM_REG_PPC_SIER, 0x00000000); 5316 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5317 SPR_NOACCESS, SPR_NOACCESS, 5318 &spr_read_generic, &spr_write_generic, 5319 KVM_REG_PPC_SPMC1, 0x00000000); 5320 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5321 SPR_NOACCESS, SPR_NOACCESS, 5322 &spr_read_generic, &spr_write_generic, 5323 KVM_REG_PPC_SPMC2, 0x00000000); 5324 spr_register_kvm(env, SPR_TACR, "TACR", 5325 SPR_NOACCESS, SPR_NOACCESS, 5326 &spr_read_generic, &spr_write_generic, 5327 KVM_REG_PPC_TACR, 0x00000000); 5328 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5329 SPR_NOACCESS, SPR_NOACCESS, 5330 &spr_read_generic, &spr_write_generic, 5331 KVM_REG_PPC_TCSCR, 0x00000000); 5332 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5333 SPR_NOACCESS, SPR_NOACCESS, 5334 &spr_read_generic, &spr_write_generic, 5335 KVM_REG_PPC_CSIGR, 0x00000000); 5336 } 5337 5338 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5339 { 5340 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5341 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5342 &spr_read_ureg, &spr_write_ureg, 5343 0x00000000); 5344 spr_register(env, SPR_POWER_USIER, "USIER", 5345 &spr_read_generic, SPR_NOACCESS, 5346 &spr_read_generic, &spr_write_generic, 5347 0x00000000); 5348 } 5349 5350 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5351 { 5352 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5353 SPR_NOACCESS, SPR_NOACCESS, 5354 &spr_read_generic, &spr_write_generic, 5355 KVM_REG_PPC_MMCR3, 0x00000000); 5356 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5357 SPR_NOACCESS, SPR_NOACCESS, 5358 &spr_read_generic, &spr_write_generic, 5359 KVM_REG_PPC_SIER2, 0x00000000); 5360 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5361 SPR_NOACCESS, SPR_NOACCESS, 5362 &spr_read_generic, &spr_write_generic, 5363 KVM_REG_PPC_SIER3, 0x00000000); 5364 } 5365 5366 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5367 { 5368 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5369 &spr_read_generic, &spr_write_generic, 5370 &spr_read_generic, &spr_write_generic, 5371 0x00000000); 5372 spr_register(env, SPR_POWER_USIER2, "USIER2", 5373 &spr_read_generic, SPR_NOACCESS, 5374 &spr_read_generic, &spr_write_generic, 5375 0x00000000); 5376 spr_register(env, SPR_POWER_USIER3, "USIER3", 5377 &spr_read_generic, SPR_NOACCESS, 5378 &spr_read_generic, &spr_write_generic, 5379 0x00000000); 5380 } 5381 5382 static void register_power5p_ear_sprs(CPUPPCState *env) 5383 { 5384 /* External access control */ 5385 spr_register(env, SPR_EAR, "EAR", 5386 SPR_NOACCESS, SPR_NOACCESS, 5387 &spr_read_generic, &spr_write_generic, 5388 0x00000000); 5389 } 5390 5391 static void register_power5p_tb_sprs(CPUPPCState *env) 5392 { 5393 /* TBU40 (High 40 bits of the Timebase register */ 5394 spr_register_hv(env, SPR_TBU40, "TBU40", 5395 SPR_NOACCESS, SPR_NOACCESS, 5396 SPR_NOACCESS, SPR_NOACCESS, 5397 SPR_NOACCESS, &spr_write_tbu40, 5398 0x00000000); 5399 } 5400 5401 static void register_970_lpar_sprs(CPUPPCState *env) 5402 { 5403 #if !defined(CONFIG_USER_ONLY) 5404 /* 5405 * PPC970: HID4 covers things later controlled by the LPCR and 5406 * RMOR in later CPUs, but with a different encoding. We only 5407 * support the 970 in "Apple mode" which has all hypervisor 5408 * facilities disabled by strapping, so we can basically just 5409 * ignore it 5410 */ 5411 spr_register(env, SPR_970_HID4, "HID4", 5412 SPR_NOACCESS, SPR_NOACCESS, 5413 &spr_read_generic, &spr_write_generic, 5414 0x00000000); 5415 #endif 5416 } 5417 5418 static void register_power5p_lpar_sprs(CPUPPCState *env) 5419 { 5420 #if !defined(CONFIG_USER_ONLY) 5421 /* Logical partitioning */ 5422 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5423 SPR_NOACCESS, SPR_NOACCESS, 5424 SPR_NOACCESS, SPR_NOACCESS, 5425 &spr_read_generic, &spr_write_lpcr, 5426 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5427 spr_register_hv(env, SPR_HDEC, "HDEC", 5428 SPR_NOACCESS, SPR_NOACCESS, 5429 SPR_NOACCESS, SPR_NOACCESS, 5430 &spr_read_hdecr, &spr_write_hdecr, 0); 5431 #endif 5432 } 5433 5434 static void register_book3s_ids_sprs(CPUPPCState *env) 5435 { 5436 /* FIXME: Will need to deal with thread vs core only SPRs */ 5437 5438 /* Processor identification */ 5439 spr_register_hv(env, SPR_PIR, "PIR", 5440 SPR_NOACCESS, SPR_NOACCESS, 5441 &spr_read_generic, SPR_NOACCESS, 5442 &spr_read_generic, NULL, 5443 0x00000000); 5444 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5445 SPR_NOACCESS, SPR_NOACCESS, 5446 SPR_NOACCESS, SPR_NOACCESS, 5447 &spr_read_generic, &spr_write_lpidr, 5448 0x00000000); 5449 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5450 SPR_NOACCESS, SPR_NOACCESS, 5451 SPR_NOACCESS, SPR_NOACCESS, 5452 &spr_read_generic, &spr_write_generic, 5453 0x00000000); 5454 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5455 SPR_NOACCESS, SPR_NOACCESS, 5456 SPR_NOACCESS, SPR_NOACCESS, 5457 &spr_read_generic, &spr_core_write_generic32, 5458 0x00000000); 5459 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5460 SPR_NOACCESS, SPR_NOACCESS, 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 &spr_read_generic, &spr_write_generic, 5463 0x00000000); 5464 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5465 SPR_NOACCESS, SPR_NOACCESS, 5466 SPR_NOACCESS, SPR_NOACCESS, 5467 &spr_read_generic, &spr_write_generic, 5468 0x00000000); 5469 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5470 SPR_NOACCESS, SPR_NOACCESS, 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 &spr_read_generic, &spr_write_generic, 5473 0x00000000); 5474 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5475 SPR_NOACCESS, SPR_NOACCESS, 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 &spr_read_generic, &spr_write_generic, 5478 0x00000000); 5479 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5480 SPR_NOACCESS, SPR_NOACCESS, 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 &spr_read_generic, &spr_write_generic, 5483 0x00000000); 5484 spr_register_hv(env, SPR_HDAR, "HDAR", 5485 SPR_NOACCESS, SPR_NOACCESS, 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 &spr_read_generic, &spr_write_generic, 5488 0x00000000); 5489 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5490 SPR_NOACCESS, SPR_NOACCESS, 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 &spr_read_generic, &spr_write_generic32, 5493 0x00000000); 5494 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5495 SPR_NOACCESS, SPR_NOACCESS, 5496 SPR_NOACCESS, SPR_NOACCESS, 5497 &spr_read_generic, &spr_core_write_generic, 5498 0x00000000); 5499 } 5500 5501 static void register_rmor_sprs(CPUPPCState *env) 5502 { 5503 spr_register_hv(env, SPR_RMOR, "RMOR", 5504 SPR_NOACCESS, SPR_NOACCESS, 5505 SPR_NOACCESS, SPR_NOACCESS, 5506 &spr_read_generic, &spr_write_generic, 5507 0x00000000); 5508 } 5509 5510 static void register_power8_ids_sprs(CPUPPCState *env) 5511 { 5512 /* Thread identification */ 5513 spr_register(env, SPR_TIR, "TIR", 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 &spr_read_generic, SPR_NOACCESS, 5516 0x00000000); 5517 } 5518 5519 static void register_book3s_purr_sprs(CPUPPCState *env) 5520 { 5521 #if !defined(CONFIG_USER_ONLY) 5522 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5523 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5524 &spr_read_purr, SPR_NOACCESS, 5525 &spr_read_purr, SPR_NOACCESS, 5526 &spr_read_purr, &spr_write_purr, 5527 KVM_REG_PPC_PURR, 0x00000000); 5528 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5529 &spr_read_purr, SPR_NOACCESS, 5530 &spr_read_purr, SPR_NOACCESS, 5531 &spr_read_purr, &spr_write_purr, 5532 KVM_REG_PPC_SPURR, 0x00000000); 5533 #endif 5534 } 5535 5536 static void register_power6_dbg_sprs(CPUPPCState *env) 5537 { 5538 #if !defined(CONFIG_USER_ONLY) 5539 spr_register(env, SPR_CFAR, "CFAR", 5540 SPR_NOACCESS, SPR_NOACCESS, 5541 &spr_read_cfar, &spr_write_cfar, 5542 0x00000000); 5543 #endif 5544 } 5545 5546 static void register_power5p_common_sprs(CPUPPCState *env) 5547 { 5548 spr_register_kvm(env, SPR_PPR, "PPR", 5549 &spr_read_generic, &spr_write_generic, 5550 &spr_read_generic, &spr_write_generic, 5551 KVM_REG_PPC_PPR, 0x00000000); 5552 } 5553 5554 static void register_power6_common_sprs(CPUPPCState *env) 5555 { 5556 #if !defined(CONFIG_USER_ONLY) 5557 spr_register_kvm(env, SPR_DSCR, "DSCR", 5558 SPR_NOACCESS, SPR_NOACCESS, 5559 &spr_read_generic, &spr_write_generic, 5560 KVM_REG_PPC_DSCR, 0x00000000); 5561 #endif 5562 /* 5563 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5564 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5565 */ 5566 spr_register_hv(env, SPR_PCR, "PCR", 5567 SPR_NOACCESS, SPR_NOACCESS, 5568 SPR_NOACCESS, SPR_NOACCESS, 5569 &spr_read_generic, &spr_write_pcr, 5570 0x00000000); 5571 } 5572 5573 static void register_HEIR32_spr(CPUPPCState *env) 5574 { 5575 spr_register_hv(env, SPR_HEIR, "HEIR", 5576 SPR_NOACCESS, SPR_NOACCESS, 5577 SPR_NOACCESS, SPR_NOACCESS, 5578 &spr_read_generic, &spr_write_generic32, 5579 0x00000000); 5580 } 5581 5582 static void register_HEIR64_spr(CPUPPCState *env) 5583 { 5584 spr_register_hv(env, SPR_HEIR, "HEIR", 5585 SPR_NOACCESS, SPR_NOACCESS, 5586 SPR_NOACCESS, SPR_NOACCESS, 5587 &spr_read_generic, &spr_write_generic, 5588 0x00000000); 5589 } 5590 5591 static void register_power7_common_sprs(CPUPPCState *env) 5592 { 5593 spr_register(env, SPR_PPR32, "PPR32", 5594 &spr_read_ppr32, &spr_write_ppr32, 5595 &spr_read_ppr32, &spr_write_ppr32, 5596 0x00000000); 5597 } 5598 5599 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5600 { 5601 spr_register_kvm(env, SPR_TAR, "TAR", 5602 &spr_read_tar, &spr_write_tar, 5603 &spr_read_generic, &spr_write_generic, 5604 KVM_REG_PPC_TAR, 0x00000000); 5605 } 5606 5607 static void register_power8_tm_sprs(CPUPPCState *env) 5608 { 5609 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5610 &spr_read_tm, &spr_write_tm, 5611 &spr_read_tm, &spr_write_tm, 5612 KVM_REG_PPC_TFHAR, 0x00000000); 5613 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5614 &spr_read_tm, &spr_write_tm, 5615 &spr_read_tm, &spr_write_tm, 5616 KVM_REG_PPC_TFIAR, 0x00000000); 5617 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5618 &spr_read_tm, &spr_write_tm, 5619 &spr_read_tm, &spr_write_tm, 5620 KVM_REG_PPC_TEXASR, 0x00000000); 5621 spr_register(env, SPR_TEXASRU, "TEXASRU", 5622 &spr_read_tm_upper32, &spr_write_tm_upper32, 5623 &spr_read_tm_upper32, &spr_write_tm_upper32, 5624 0x00000000); 5625 } 5626 5627 static void register_power8_ebb_sprs(CPUPPCState *env) 5628 { 5629 spr_register(env, SPR_BESCRS, "BESCRS", 5630 &spr_read_ebb, &spr_write_ebb, 5631 &spr_read_generic, &spr_write_generic, 5632 0x00000000); 5633 spr_register(env, SPR_BESCRSU, "BESCRSU", 5634 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5635 &spr_read_prev_upper32, &spr_write_prev_upper32, 5636 0x00000000); 5637 spr_register(env, SPR_BESCRR, "BESCRR", 5638 &spr_read_ebb, &spr_write_ebb, 5639 &spr_read_generic, &spr_write_generic, 5640 0x00000000); 5641 spr_register(env, SPR_BESCRRU, "BESCRRU", 5642 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5643 &spr_read_prev_upper32, &spr_write_prev_upper32, 5644 0x00000000); 5645 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5646 &spr_read_ebb, &spr_write_ebb, 5647 &spr_read_generic, &spr_write_generic, 5648 KVM_REG_PPC_EBBHR, 0x00000000); 5649 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5650 &spr_read_ebb, &spr_write_ebb, 5651 &spr_read_generic, &spr_write_generic, 5652 KVM_REG_PPC_EBBRR, 0x00000000); 5653 spr_register_kvm(env, SPR_BESCR, "BESCR", 5654 &spr_read_ebb, &spr_write_ebb, 5655 &spr_read_generic, &spr_write_generic, 5656 KVM_REG_PPC_BESCR, 0x00000000); 5657 } 5658 5659 /* Virtual Time Base */ 5660 static void register_vtb_sprs(CPUPPCState *env) 5661 { 5662 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5663 SPR_NOACCESS, SPR_NOACCESS, 5664 &spr_read_vtb, SPR_NOACCESS, 5665 &spr_read_vtb, &spr_write_vtb, 5666 KVM_REG_PPC_VTB, 0x00000000); 5667 } 5668 5669 static void register_power8_fscr_sprs(CPUPPCState *env) 5670 { 5671 #if defined(CONFIG_USER_ONLY) 5672 target_ulong initval = 1ULL << FSCR_TAR; 5673 #else 5674 target_ulong initval = 0; 5675 #endif 5676 spr_register_kvm(env, SPR_FSCR, "FSCR", 5677 SPR_NOACCESS, SPR_NOACCESS, 5678 &spr_read_generic, &spr_write_generic, 5679 KVM_REG_PPC_FSCR, initval); 5680 } 5681 5682 static void register_power8_pspb_sprs(CPUPPCState *env) 5683 { 5684 spr_register_kvm(env, SPR_PSPB, "PSPB", 5685 SPR_NOACCESS, SPR_NOACCESS, 5686 &spr_read_generic, &spr_write_generic32, 5687 KVM_REG_PPC_PSPB, 0); 5688 } 5689 5690 static void register_power8_dpdes_sprs(CPUPPCState *env) 5691 { 5692 #if !defined(CONFIG_USER_ONLY) 5693 /* Directed Privileged Door-bell Exception State, used for IPI */ 5694 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5695 SPR_NOACCESS, SPR_NOACCESS, 5696 &spr_read_dpdes, SPR_NOACCESS, 5697 &spr_read_dpdes, &spr_write_dpdes, 5698 KVM_REG_PPC_DPDES, 0x00000000); 5699 #endif 5700 } 5701 5702 static void register_power8_ic_sprs(CPUPPCState *env) 5703 { 5704 #if !defined(CONFIG_USER_ONLY) 5705 spr_register_hv(env, SPR_IC, "IC", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, SPR_NOACCESS, 5708 &spr_read_generic, &spr_write_generic, 5709 0); 5710 #endif 5711 } 5712 5713 /* SPRs specific to IBM POWER CPUs */ 5714 static void register_power_common_book4_sprs(CPUPPCState *env) 5715 { 5716 #if !defined(CONFIG_USER_ONLY) 5717 spr_register_hv(env, SPR_HID0, "HID0", 5718 SPR_NOACCESS, SPR_NOACCESS, 5719 SPR_NOACCESS, SPR_NOACCESS, 5720 &spr_read_generic, &spr_core_write_generic, 5721 0x00000000); 5722 spr_register_hv(env, SPR_TSCR, "TSCR", 5723 SPR_NOACCESS, SPR_NOACCESS, 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 &spr_read_generic, &spr_core_write_generic32, 5726 0x00000000); 5727 spr_register_hv(env, SPR_HMER, "HMER", 5728 SPR_NOACCESS, SPR_NOACCESS, 5729 SPR_NOACCESS, SPR_NOACCESS, 5730 &spr_read_generic, &spr_write_hmer, 5731 0x00000000); 5732 spr_register_hv(env, SPR_HMEER, "HMEER", 5733 SPR_NOACCESS, SPR_NOACCESS, 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 &spr_read_generic, &spr_core_write_generic, 5736 0x00000000); 5737 spr_register_hv(env, SPR_TFMR, "TFMR", 5738 SPR_NOACCESS, SPR_NOACCESS, 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 &spr_read_tfmr, &spr_write_tfmr, 5741 0x00000000); 5742 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 &spr_access_nop, &spr_write_generic, 5745 &spr_access_nop, &spr_write_generic, 5746 0x00000000); 5747 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5748 SPR_NOACCESS, SPR_NOACCESS, 5749 &spr_access_nop, &spr_write_generic, 5750 &spr_access_nop, &spr_write_generic, 5751 0x00000000); 5752 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5753 SPR_NOACCESS, SPR_NOACCESS, 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 &spr_read_generic, &spr_core_lpar_write_generic, 5756 0x00000000); 5757 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5758 SPR_NOACCESS, SPR_NOACCESS, 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_read_generic, &spr_core_write_generic, 5761 0x00000000); 5762 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5763 SPR_NOACCESS, SPR_NOACCESS, 5764 SPR_NOACCESS, SPR_NOACCESS, 5765 &spr_read_generic, &spr_write_sprc, 5766 0x00000000); 5767 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5768 SPR_NOACCESS, SPR_NOACCESS, 5769 SPR_NOACCESS, SPR_NOACCESS, 5770 &spr_read_sprd, &spr_write_sprd, 5771 0x00000000); 5772 #endif 5773 } 5774 5775 static void register_power9_book4_sprs(CPUPPCState *env) 5776 { 5777 /* Add a number of P9 book4 registers */ 5778 register_power_common_book4_sprs(env); 5779 #if !defined(CONFIG_USER_ONLY) 5780 spr_register_kvm(env, SPR_WORT, "WORT", 5781 SPR_NOACCESS, SPR_NOACCESS, 5782 &spr_read_generic, &spr_write_generic, 5783 KVM_REG_PPC_WORT, 0); 5784 #endif 5785 } 5786 5787 static void register_power8_book4_sprs(CPUPPCState *env) 5788 { 5789 /* Add a number of P8 book4 registers */ 5790 register_power_common_book4_sprs(env); 5791 #if !defined(CONFIG_USER_ONLY) 5792 spr_register_kvm(env, SPR_ACOP, "ACOP", 5793 SPR_NOACCESS, SPR_NOACCESS, 5794 &spr_read_generic, &spr_write_generic, 5795 KVM_REG_PPC_ACOP, 0); 5796 /* PID is only in BookE in ISA v2.07 */ 5797 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5798 SPR_NOACCESS, SPR_NOACCESS, 5799 &spr_read_generic, &spr_write_pidr, 5800 KVM_REG_PPC_PID, 0); 5801 spr_register_kvm(env, SPR_WORT, "WORT", 5802 SPR_NOACCESS, SPR_NOACCESS, 5803 &spr_read_generic, &spr_write_generic, 5804 KVM_REG_PPC_WORT, 0); 5805 #endif 5806 } 5807 5808 static void register_power7_book4_sprs(CPUPPCState *env) 5809 { 5810 /* Add a number of P7 book4 registers */ 5811 #if !defined(CONFIG_USER_ONLY) 5812 register_power_common_book4_sprs(env); 5813 spr_register_kvm(env, SPR_ACOP, "ACOP", 5814 SPR_NOACCESS, SPR_NOACCESS, 5815 &spr_read_generic, &spr_write_generic, 5816 KVM_REG_PPC_ACOP, 0); 5817 /* PID is only in BookE in ISA v2.06 */ 5818 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5819 SPR_NOACCESS, SPR_NOACCESS, 5820 &spr_read_generic, &spr_write_generic32, 5821 KVM_REG_PPC_PID, 0); 5822 #endif 5823 } 5824 5825 static void register_power8_rpr_sprs(CPUPPCState *env) 5826 { 5827 #if !defined(CONFIG_USER_ONLY) 5828 spr_register_hv(env, SPR_RPR, "RPR", 5829 SPR_NOACCESS, SPR_NOACCESS, 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 &spr_read_generic, &spr_core_write_generic, 5832 0x00000103070F1F3F); 5833 #endif 5834 } 5835 5836 static void register_power9_mmu_sprs(CPUPPCState *env) 5837 { 5838 #if !defined(CONFIG_USER_ONLY) 5839 /* Partition Table Control */ 5840 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 &spr_read_generic, &spr_write_ptcr, 5844 KVM_REG_PPC_PTCR, 0x00000000); 5845 /* Address Segment Descriptor Register */ 5846 spr_register_hv(env, SPR_ASDR, "ASDR", 5847 SPR_NOACCESS, SPR_NOACCESS, 5848 SPR_NOACCESS, SPR_NOACCESS, 5849 &spr_read_generic, &spr_write_generic, 5850 0x0000000000000000); 5851 /* PID is part of the BookS ISA from v3.0 */ 5852 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5853 SPR_NOACCESS, SPR_NOACCESS, 5854 &spr_read_generic, &spr_write_pidr, 5855 KVM_REG_PPC_PID, 0); 5856 #endif 5857 } 5858 5859 static void register_power10_hash_sprs(CPUPPCState *env) 5860 { 5861 /* 5862 * it's the OS responsibility to generate a random value for the registers 5863 * in each process' context. So, initialize it with 0 here. 5864 */ 5865 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5866 #if defined(CONFIG_USER_ONLY) 5867 /* in linux-user, setup the hash register with a random value */ 5868 GRand *rand = g_rand_new(); 5869 hashkeyr_initial_value = 5870 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5871 hashpkeyr_initial_value = 5872 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5873 g_rand_free(rand); 5874 #endif 5875 spr_register(env, SPR_HASHKEYR, "HASHKEYR", 5876 SPR_NOACCESS, SPR_NOACCESS, 5877 &spr_read_generic, &spr_write_generic, 5878 hashkeyr_initial_value); 5879 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 SPR_NOACCESS, SPR_NOACCESS, 5882 &spr_read_generic, &spr_write_generic, 5883 hashpkeyr_initial_value); 5884 } 5885 5886 static void register_power10_dexcr_sprs(CPUPPCState *env) 5887 { 5888 spr_register(env, SPR_DEXCR, "DEXCR", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 &spr_read_generic, &spr_write_generic, 5891 0); 5892 5893 spr_register(env, SPR_UDEXCR, "UDEXCR", 5894 &spr_read_dexcr_ureg, SPR_NOACCESS, 5895 &spr_read_dexcr_ureg, SPR_NOACCESS, 5896 0); 5897 5898 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5899 SPR_NOACCESS, SPR_NOACCESS, 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 &spr_read_generic, &spr_write_generic, 5902 0); 5903 5904 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5905 &spr_read_dexcr_ureg, SPR_NOACCESS, 5906 &spr_read_dexcr_ureg, SPR_NOACCESS, 5907 0); 5908 } 5909 5910 /* 5911 * Initialize PMU counter overflow timers for Power8 and 5912 * newer Power chips when using TCG. 5913 */ 5914 static void init_tcg_pmu_power8(CPUPPCState *env) 5915 { 5916 /* Init PMU overflow timers */ 5917 if (tcg_enabled()) { 5918 cpu_ppc_pmu_init(env); 5919 } 5920 } 5921 5922 static void init_proc_book3s_common(CPUPPCState *env) 5923 { 5924 register_non_embedded_sprs(env); 5925 register_book3s_altivec_sprs(env); 5926 register_book3s_pmu_sup_sprs(env); 5927 register_book3s_pmu_user_sprs(env); 5928 register_book3s_ctrl_sprs(env); 5929 /* 5930 * Can't find information on what this should be on reset. This 5931 * value is the one used by 74xx processors. 5932 */ 5933 vscr_init(env, 0x00010000); 5934 5935 spr_register(env, SPR_USPRG3, "USPRG3", 5936 &spr_read_ureg, SPR_NOACCESS, 5937 &spr_read_ureg, SPR_NOACCESS, 5938 0x00000000); 5939 } 5940 5941 static void init_proc_970(CPUPPCState *env) 5942 { 5943 /* Common Registers */ 5944 init_proc_book3s_common(env); 5945 register_sdr1_sprs(env); 5946 register_book3s_dbg_sprs(env); 5947 5948 /* 970 Specific Registers */ 5949 register_970_hid_sprs(env); 5950 register_970_hior_sprs(env); 5951 register_low_BATs(env); 5952 register_970_pmu_sup_sprs(env); 5953 register_970_pmu_user_sprs(env); 5954 register_970_lpar_sprs(env); 5955 register_970_dbg_sprs(env); 5956 5957 /* env variables */ 5958 env->dcache_line_size = 128; 5959 env->icache_line_size = 128; 5960 5961 /* Allocate hardware IRQ controller */ 5962 init_excp_970(env); 5963 ppc970_irq_init(env_archcpu(env)); 5964 } 5965 5966 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5967 { 5968 DeviceClass *dc = DEVICE_CLASS(oc); 5969 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5970 5971 dc->desc = "PowerPC 970"; 5972 pcc->init_proc = init_proc_970; 5973 pcc->check_pow = check_pow_970; 5974 pcc->check_attn = check_attn_hid0; 5975 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5976 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5977 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5978 PPC_FLOAT_STFIWX | 5979 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5980 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5981 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5982 PPC_64B | PPC_ALTIVEC | 5983 PPC_SEGMENT_64B | PPC_SLBI; 5984 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 5985 pcc->msr_mask = (1ull << MSR_SF) | 5986 (1ull << MSR_VR) | 5987 (1ull << MSR_POW) | 5988 (1ull << MSR_EE) | 5989 (1ull << MSR_PR) | 5990 (1ull << MSR_FP) | 5991 (1ull << MSR_ME) | 5992 (1ull << MSR_FE0) | 5993 (1ull << MSR_SE) | 5994 (1ull << MSR_DE) | 5995 (1ull << MSR_FE1) | 5996 (1ull << MSR_IR) | 5997 (1ull << MSR_DR) | 5998 (1ull << MSR_PMM) | 5999 (1ull << MSR_RI); 6000 pcc->mmu_model = POWERPC_MMU_64B; 6001 #if !defined(CONFIG_USER_ONLY) 6002 pcc->hash64_opts = &ppc_hash64_opts_basic; 6003 #endif 6004 pcc->excp_model = POWERPC_EXCP_970; 6005 pcc->bus_model = PPC_FLAGS_INPUT_970; 6006 pcc->bfd_mach = bfd_mach_ppc64; 6007 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6008 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6009 POWERPC_FLAG_BUS_CLK; 6010 pcc->l1_dcache_size = 0x8000; 6011 pcc->l1_icache_size = 0x10000; 6012 } 6013 6014 static void init_proc_power5plus(CPUPPCState *env) 6015 { 6016 /* Common Registers */ 6017 init_proc_book3s_common(env); 6018 register_sdr1_sprs(env); 6019 register_book3s_dbg_sprs(env); 6020 6021 /* POWER5+ Specific Registers */ 6022 register_970_hid_sprs(env); 6023 register_970_hior_sprs(env); 6024 register_low_BATs(env); 6025 register_970_pmu_sup_sprs(env); 6026 register_970_pmu_user_sprs(env); 6027 register_power5p_common_sprs(env); 6028 register_power5p_lpar_sprs(env); 6029 register_power5p_ear_sprs(env); 6030 register_power5p_tb_sprs(env); 6031 6032 /* env variables */ 6033 env->dcache_line_size = 128; 6034 env->icache_line_size = 128; 6035 6036 /* Allocate hardware IRQ controller */ 6037 init_excp_970(env); 6038 ppc970_irq_init(env_archcpu(env)); 6039 } 6040 6041 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6042 { 6043 DeviceClass *dc = DEVICE_CLASS(oc); 6044 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6045 6046 dc->fw_name = "PowerPC,POWER5"; 6047 dc->desc = "POWER5+"; 6048 pcc->init_proc = init_proc_power5plus; 6049 pcc->check_pow = check_pow_970; 6050 pcc->check_attn = check_attn_hid0; 6051 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6052 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6053 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6054 PPC_FLOAT_STFIWX | 6055 PPC_FLOAT_EXT | 6056 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6057 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6058 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6059 PPC_64B | 6060 PPC_POPCNTB | 6061 PPC_SEGMENT_64B | PPC_SLBI; 6062 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6063 pcc->msr_mask = (1ull << MSR_SF) | 6064 (1ull << MSR_VR) | 6065 (1ull << MSR_POW) | 6066 (1ull << MSR_EE) | 6067 (1ull << MSR_PR) | 6068 (1ull << MSR_FP) | 6069 (1ull << MSR_ME) | 6070 (1ull << MSR_FE0) | 6071 (1ull << MSR_SE) | 6072 (1ull << MSR_DE) | 6073 (1ull << MSR_FE1) | 6074 (1ull << MSR_IR) | 6075 (1ull << MSR_DR) | 6076 (1ull << MSR_PMM) | 6077 (1ull << MSR_RI); 6078 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6079 LPCR_RMI | LPCR_HDICE; 6080 pcc->mmu_model = POWERPC_MMU_2_03; 6081 #if !defined(CONFIG_USER_ONLY) 6082 pcc->hash64_opts = &ppc_hash64_opts_basic; 6083 pcc->lrg_decr_bits = 32; 6084 #endif 6085 pcc->excp_model = POWERPC_EXCP_970; 6086 pcc->bus_model = PPC_FLAGS_INPUT_970; 6087 pcc->bfd_mach = bfd_mach_ppc64; 6088 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6089 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6090 POWERPC_FLAG_BUS_CLK; 6091 pcc->l1_dcache_size = 0x8000; 6092 pcc->l1_icache_size = 0x10000; 6093 } 6094 6095 static void init_proc_POWER7(CPUPPCState *env) 6096 { 6097 /* Common Registers */ 6098 init_proc_book3s_common(env); 6099 register_sdr1_sprs(env); 6100 register_book3s_dbg_sprs(env); 6101 6102 /* POWER7 Specific Registers */ 6103 register_book3s_ids_sprs(env); 6104 register_rmor_sprs(env); 6105 register_amr_sprs(env); 6106 register_book3s_purr_sprs(env); 6107 register_power5p_common_sprs(env); 6108 register_power5p_lpar_sprs(env); 6109 register_power5p_ear_sprs(env); 6110 register_power5p_tb_sprs(env); 6111 register_power6_common_sprs(env); 6112 register_HEIR32_spr(env); 6113 register_power6_dbg_sprs(env); 6114 register_power7_common_sprs(env); 6115 register_power7_book4_sprs(env); 6116 6117 /* env variables */ 6118 env->dcache_line_size = 128; 6119 env->icache_line_size = 128; 6120 6121 /* Allocate hardware IRQ controller */ 6122 init_excp_POWER7(env); 6123 ppcPOWER7_irq_init(env_archcpu(env)); 6124 } 6125 6126 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6127 { 6128 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6129 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6130 6131 if (!best) { 6132 if (base == CPU_POWERPC_POWER7_BASE) { 6133 return true; 6134 } 6135 if (base == CPU_POWERPC_POWER7P_BASE) { 6136 return true; 6137 } 6138 } 6139 6140 if (base != pcc_base) { 6141 return false; 6142 } 6143 6144 return true; 6145 } 6146 6147 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6148 { 6149 DeviceClass *dc = DEVICE_CLASS(oc); 6150 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6151 6152 dc->fw_name = "PowerPC,POWER7"; 6153 dc->desc = "POWER7"; 6154 pcc->pvr_match = ppc_pvr_match_power7; 6155 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6156 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6157 pcc->init_proc = init_proc_POWER7; 6158 pcc->check_pow = check_pow_nocheck; 6159 pcc->check_attn = check_attn_hid0; 6160 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6162 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6163 PPC_FLOAT_FRSQRTES | 6164 PPC_FLOAT_STFIWX | 6165 PPC_FLOAT_EXT | 6166 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6167 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6168 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6169 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6170 PPC_SEGMENT_64B | PPC_SLBI | 6171 PPC_POPCNTB | PPC_POPCNTWD | 6172 PPC_CILDST; 6173 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6174 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6175 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6176 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6177 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6178 pcc->msr_mask = (1ull << MSR_SF) | 6179 (1ull << MSR_VR) | 6180 (1ull << MSR_VSX) | 6181 (1ull << MSR_EE) | 6182 (1ull << MSR_PR) | 6183 (1ull << MSR_FP) | 6184 (1ull << MSR_ME) | 6185 (1ull << MSR_FE0) | 6186 (1ull << MSR_SE) | 6187 (1ull << MSR_DE) | 6188 (1ull << MSR_FE1) | 6189 (1ull << MSR_IR) | 6190 (1ull << MSR_DR) | 6191 (1ull << MSR_PMM) | 6192 (1ull << MSR_RI) | 6193 (1ull << MSR_LE); 6194 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6195 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6196 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6197 LPCR_MER | LPCR_TC | 6198 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6199 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6200 pcc->mmu_model = POWERPC_MMU_2_06; 6201 #if !defined(CONFIG_USER_ONLY) 6202 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6203 pcc->lrg_decr_bits = 32; 6204 #endif 6205 pcc->excp_model = POWERPC_EXCP_POWER7; 6206 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6207 pcc->bfd_mach = bfd_mach_ppc64; 6208 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6209 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6210 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6211 POWERPC_FLAG_VSX; 6212 pcc->l1_dcache_size = 0x8000; 6213 pcc->l1_icache_size = 0x8000; 6214 } 6215 6216 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6217 { 6218 if (env->flags & POWERPC_FLAG_BHRB) { 6219 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6220 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6221 } 6222 env->bhrb_num_entries = 1 << num_entries_log2; 6223 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6224 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6225 } 6226 } 6227 6228 static void bhrb_reset_state(CPUPPCState *env) 6229 { 6230 if (env->flags & POWERPC_FLAG_BHRB) { 6231 env->bhrb_offset = 0; 6232 env->bhrb_filter = 0; 6233 memset(env->bhrb, 0, sizeof(env->bhrb)); 6234 } 6235 } 6236 6237 #define POWER8_BHRB_ENTRIES_LOG2 5 6238 static void init_proc_POWER8(CPUPPCState *env) 6239 { 6240 /* Common Registers */ 6241 init_proc_book3s_common(env); 6242 register_sdr1_sprs(env); 6243 register_book3s_207_dbg_sprs(env); 6244 6245 /* Common TCG PMU */ 6246 init_tcg_pmu_power8(env); 6247 6248 /* POWER8 Specific Registers */ 6249 register_book3s_ids_sprs(env); 6250 register_rmor_sprs(env); 6251 register_amr_sprs(env); 6252 register_iamr_sprs(env); 6253 register_book3s_purr_sprs(env); 6254 register_power5p_common_sprs(env); 6255 register_power5p_lpar_sprs(env); 6256 register_power5p_ear_sprs(env); 6257 register_power5p_tb_sprs(env); 6258 register_power6_common_sprs(env); 6259 register_HEIR32_spr(env); 6260 register_power6_dbg_sprs(env); 6261 register_power7_common_sprs(env); 6262 register_power8_tce_address_control_sprs(env); 6263 register_power8_ids_sprs(env); 6264 register_power8_ebb_sprs(env); 6265 register_power8_fscr_sprs(env); 6266 register_power8_pmu_sup_sprs(env); 6267 register_power8_pmu_user_sprs(env); 6268 register_power8_tm_sprs(env); 6269 register_power8_pspb_sprs(env); 6270 register_power8_dpdes_sprs(env); 6271 register_vtb_sprs(env); 6272 register_power8_ic_sprs(env); 6273 register_power8_book4_sprs(env); 6274 register_power8_rpr_sprs(env); 6275 6276 /* env variables */ 6277 env->dcache_line_size = 128; 6278 env->icache_line_size = 128; 6279 6280 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6281 6282 /* Allocate hardware IRQ controller */ 6283 init_excp_POWER8(env); 6284 ppcPOWER7_irq_init(env_archcpu(env)); 6285 } 6286 6287 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6288 { 6289 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6290 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6291 6292 if (!best) { 6293 if (base == CPU_POWERPC_POWER8_BASE) { 6294 return true; 6295 } 6296 if (base == CPU_POWERPC_POWER8E_BASE) { 6297 return true; 6298 } 6299 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6300 return true; 6301 } 6302 } 6303 if (base != pcc_base) { 6304 return false; 6305 } 6306 6307 return true; 6308 } 6309 6310 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6311 { 6312 DeviceClass *dc = DEVICE_CLASS(oc); 6313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6314 6315 dc->fw_name = "PowerPC,POWER8"; 6316 dc->desc = "POWER8"; 6317 pcc->pvr_match = ppc_pvr_match_power8; 6318 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6319 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6320 pcc->init_proc = init_proc_POWER8; 6321 pcc->check_pow = check_pow_nocheck; 6322 pcc->check_attn = check_attn_hid0; 6323 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6325 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6326 PPC_FLOAT_FRSQRTES | 6327 PPC_FLOAT_STFIWX | 6328 PPC_FLOAT_EXT | 6329 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6330 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6331 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6332 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6333 PPC_SEGMENT_64B | PPC_SLBI | 6334 PPC_POPCNTB | PPC_POPCNTWD | 6335 PPC_CILDST; 6336 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6337 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6338 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6339 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6340 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6341 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6342 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6343 PPC2_BCDA_ISA206; 6344 pcc->msr_mask = (1ull << MSR_SF) | 6345 (1ull << MSR_HV) | 6346 (1ull << MSR_TM) | 6347 (1ull << MSR_VR) | 6348 (1ull << MSR_VSX) | 6349 (1ull << MSR_EE) | 6350 (1ull << MSR_PR) | 6351 (1ull << MSR_FP) | 6352 (1ull << MSR_ME) | 6353 (1ull << MSR_FE0) | 6354 (1ull << MSR_SE) | 6355 (1ull << MSR_DE) | 6356 (1ull << MSR_FE1) | 6357 (1ull << MSR_IR) | 6358 (1ull << MSR_DR) | 6359 (1ull << MSR_PMM) | 6360 (1ull << MSR_RI) | 6361 (1ull << MSR_TS0) | 6362 (1ull << MSR_TS1) | 6363 (1ull << MSR_LE); 6364 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6365 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6366 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6367 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6368 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6369 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6370 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6371 pcc->mmu_model = POWERPC_MMU_2_07; 6372 #if !defined(CONFIG_USER_ONLY) 6373 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6374 pcc->lrg_decr_bits = 32; 6375 pcc->n_host_threads = 8; 6376 #endif 6377 pcc->excp_model = POWERPC_EXCP_POWER8; 6378 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6379 pcc->bfd_mach = bfd_mach_ppc64; 6380 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6381 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6382 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6383 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6384 pcc->l1_dcache_size = 0x8000; 6385 pcc->l1_icache_size = 0x8000; 6386 } 6387 6388 #ifndef CONFIG_USER_ONLY 6389 /* 6390 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6391 * Encoded as array of int_32s in the form: 6392 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6393 * x -> AP encoding 6394 * y -> radix mode supported page size (encoded as a shift) 6395 */ 6396 static struct ppc_radix_page_info POWER9_radix_page_info = { 6397 .count = 4, 6398 .entries = { 6399 0x0000000c, /* 4K - enc: 0x0 */ 6400 0xa0000010, /* 64K - enc: 0x5 */ 6401 0x20000015, /* 2M - enc: 0x1 */ 6402 0x4000001e /* 1G - enc: 0x2 */ 6403 } 6404 }; 6405 #endif /* CONFIG_USER_ONLY */ 6406 6407 #define POWER9_BHRB_ENTRIES_LOG2 5 6408 static void init_proc_POWER9(CPUPPCState *env) 6409 { 6410 /* Common Registers */ 6411 init_proc_book3s_common(env); 6412 register_book3s_207_dbg_sprs(env); 6413 6414 /* Common TCG PMU */ 6415 init_tcg_pmu_power8(env); 6416 6417 /* POWER8 Specific Registers */ 6418 register_book3s_ids_sprs(env); 6419 register_amr_sprs(env); 6420 register_iamr_sprs(env); 6421 register_book3s_purr_sprs(env); 6422 register_power5p_common_sprs(env); 6423 register_power5p_lpar_sprs(env); 6424 register_power5p_ear_sprs(env); 6425 register_power5p_tb_sprs(env); 6426 register_power6_common_sprs(env); 6427 register_HEIR32_spr(env); 6428 register_power6_dbg_sprs(env); 6429 register_power7_common_sprs(env); 6430 register_power8_tce_address_control_sprs(env); 6431 register_power8_ids_sprs(env); 6432 register_power8_ebb_sprs(env); 6433 register_power8_fscr_sprs(env); 6434 register_power8_pmu_sup_sprs(env); 6435 register_power8_pmu_user_sprs(env); 6436 register_power8_tm_sprs(env); 6437 register_power8_pspb_sprs(env); 6438 register_power8_dpdes_sprs(env); 6439 register_vtb_sprs(env); 6440 register_power8_ic_sprs(env); 6441 register_power9_book4_sprs(env); 6442 register_power8_rpr_sprs(env); 6443 register_power9_mmu_sprs(env); 6444 6445 /* POWER9 Specific registers */ 6446 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6447 spr_read_generic, spr_write_generic, 6448 KVM_REG_PPC_TIDR, 0); 6449 6450 /* FIXME: Filter fields properly based on privilege level */ 6451 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6452 spr_read_generic, spr_write_generic, 6453 KVM_REG_PPC_PSSCR, 0); 6454 6455 /* env variables */ 6456 env->dcache_line_size = 128; 6457 env->icache_line_size = 128; 6458 6459 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6460 6461 /* Allocate hardware IRQ controller */ 6462 init_excp_POWER9(env); 6463 ppcPOWER9_irq_init(env_archcpu(env)); 6464 } 6465 6466 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6467 { 6468 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6469 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6470 6471 if (!best) { 6472 if (base == CPU_POWERPC_POWER9_BASE) { 6473 return true; 6474 } 6475 } 6476 6477 if (base != pcc_base) { 6478 return false; 6479 } 6480 6481 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6482 /* Major DD version does not match */ 6483 return false; 6484 } 6485 6486 if ((pvr & 0x0f00) == 0x200) { 6487 if ((pvr & 0xf) < 2) { 6488 /* DD2.0, DD2.1 match power9_v2.0 */ 6489 if ((pcc->pvr & 0xf) == 0) { 6490 return true; 6491 } 6492 } else { 6493 /* DD2.2, DD2.3 match power9_v2.2 */ 6494 if ((pcc->pvr & 0xf) == 2) { 6495 return true; 6496 } 6497 } 6498 } 6499 6500 return false; 6501 } 6502 6503 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6504 { 6505 DeviceClass *dc = DEVICE_CLASS(oc); 6506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6507 6508 dc->fw_name = "PowerPC,POWER9"; 6509 dc->desc = "POWER9"; 6510 pcc->pvr_match = ppc_pvr_match_power9; 6511 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6512 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6513 PCR_COMPAT_2_05; 6514 pcc->init_proc = init_proc_POWER9; 6515 pcc->check_pow = check_pow_nocheck; 6516 pcc->check_attn = check_attn_hid0_power9; 6517 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6518 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6519 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6520 PPC_FLOAT_FRSQRTES | 6521 PPC_FLOAT_STFIWX | 6522 PPC_FLOAT_EXT | 6523 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6524 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6525 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6526 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6527 PPC_SEGMENT_64B | PPC_SLBI | 6528 PPC_POPCNTB | PPC_POPCNTWD | 6529 PPC_CILDST; 6530 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6531 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6532 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6533 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6534 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6535 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6536 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC | 6537 PPC2_BCDA_ISA206; 6538 pcc->msr_mask = (1ull << MSR_SF) | 6539 (1ull << MSR_HV) | 6540 (1ull << MSR_TM) | 6541 (1ull << MSR_VR) | 6542 (1ull << MSR_VSX) | 6543 (1ull << MSR_EE) | 6544 (1ull << MSR_PR) | 6545 (1ull << MSR_FP) | 6546 (1ull << MSR_ME) | 6547 (1ull << MSR_FE0) | 6548 (1ull << MSR_SE) | 6549 (1ull << MSR_DE) | 6550 (1ull << MSR_FE1) | 6551 (1ull << MSR_IR) | 6552 (1ull << MSR_DR) | 6553 (1ull << MSR_PMM) | 6554 (1ull << MSR_RI) | 6555 (1ull << MSR_LE); 6556 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6557 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6558 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6559 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6560 LPCR_DEE | LPCR_OEE)) 6561 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6562 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6563 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6564 pcc->mmu_model = POWERPC_MMU_3_00; 6565 #if !defined(CONFIG_USER_ONLY) 6566 /* segment page size remain the same */ 6567 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6568 pcc->radix_page_info = &POWER9_radix_page_info; 6569 pcc->lrg_decr_bits = 56; 6570 pcc->n_host_threads = 4; 6571 #endif 6572 pcc->excp_model = POWERPC_EXCP_POWER9; 6573 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6574 pcc->bfd_mach = bfd_mach_ppc64; 6575 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6576 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6577 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6578 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6579 pcc->l1_dcache_size = 0x8000; 6580 pcc->l1_icache_size = 0x8000; 6581 } 6582 6583 #ifndef CONFIG_USER_ONLY 6584 /* 6585 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6586 * Encoded as array of int_32s in the form: 6587 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6588 * x -> AP encoding 6589 * y -> radix mode supported page size (encoded as a shift) 6590 */ 6591 static struct ppc_radix_page_info POWER10_radix_page_info = { 6592 .count = 4, 6593 .entries = { 6594 0x0000000c, /* 4K - enc: 0x0 */ 6595 0xa0000010, /* 64K - enc: 0x5 */ 6596 0x20000015, /* 2M - enc: 0x1 */ 6597 0x4000001e /* 1G - enc: 0x2 */ 6598 } 6599 }; 6600 #endif /* !CONFIG_USER_ONLY */ 6601 6602 #define POWER10_BHRB_ENTRIES_LOG2 5 6603 static void init_proc_POWER10(CPUPPCState *env) 6604 { 6605 /* Common Registers */ 6606 init_proc_book3s_common(env); 6607 register_book3s_207_dbg_sprs(env); 6608 6609 /* Common TCG PMU */ 6610 init_tcg_pmu_power8(env); 6611 6612 /* POWER8 Specific Registers */ 6613 register_book3s_ids_sprs(env); 6614 register_amr_sprs(env); 6615 register_iamr_sprs(env); 6616 register_book3s_purr_sprs(env); 6617 register_power5p_common_sprs(env); 6618 register_power5p_lpar_sprs(env); 6619 register_power5p_ear_sprs(env); 6620 register_power5p_tb_sprs(env); 6621 register_power6_common_sprs(env); 6622 register_HEIR64_spr(env); 6623 register_power6_dbg_sprs(env); 6624 register_power7_common_sprs(env); 6625 register_power8_tce_address_control_sprs(env); 6626 register_power8_ids_sprs(env); 6627 register_power8_ebb_sprs(env); 6628 register_power8_fscr_sprs(env); 6629 register_power8_pmu_sup_sprs(env); 6630 register_power8_pmu_user_sprs(env); 6631 register_power8_tm_sprs(env); 6632 register_power8_pspb_sprs(env); 6633 register_power8_dpdes_sprs(env); 6634 register_vtb_sprs(env); 6635 register_power8_ic_sprs(env); 6636 register_power9_book4_sprs(env); 6637 register_power8_rpr_sprs(env); 6638 register_power9_mmu_sprs(env); 6639 register_power10_hash_sprs(env); 6640 register_power10_dexcr_sprs(env); 6641 register_power10_pmu_sup_sprs(env); 6642 register_power10_pmu_user_sprs(env); 6643 6644 /* FIXME: Filter fields properly based on privilege level */ 6645 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6646 spr_read_generic, spr_write_generic, 6647 KVM_REG_PPC_PSSCR, 0); 6648 6649 /* env variables */ 6650 env->dcache_line_size = 128; 6651 env->icache_line_size = 128; 6652 6653 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6654 6655 /* Allocate hardware IRQ controller */ 6656 init_excp_POWER10(env); 6657 ppcPOWER9_irq_init(env_archcpu(env)); 6658 } 6659 6660 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6661 { 6662 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6663 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6664 6665 if (!best) { 6666 if (base == CPU_POWERPC_POWER10_BASE) { 6667 return true; 6668 } 6669 } 6670 6671 if (base != pcc_base) { 6672 return false; 6673 } 6674 6675 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6676 /* Major DD version matches power10_v2.0 */ 6677 return true; 6678 } 6679 6680 return false; 6681 } 6682 6683 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6684 { 6685 DeviceClass *dc = DEVICE_CLASS(oc); 6686 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6687 6688 dc->fw_name = "PowerPC,POWER10"; 6689 dc->desc = "POWER10"; 6690 pcc->pvr_match = ppc_pvr_match_power10; 6691 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 6692 PCR_COMPAT_3_00; 6693 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 6694 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6695 pcc->init_proc = init_proc_POWER10; 6696 pcc->check_pow = check_pow_nocheck; 6697 pcc->check_attn = check_attn_hid0_power9; 6698 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6699 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6700 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6701 PPC_FLOAT_FRSQRTES | 6702 PPC_FLOAT_STFIWX | 6703 PPC_FLOAT_EXT | 6704 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6705 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6706 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6707 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6708 PPC_SEGMENT_64B | PPC_SLBI | 6709 PPC_POPCNTB | PPC_POPCNTWD | 6710 PPC_CILDST; 6711 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6712 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6713 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6714 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6715 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6716 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6717 PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | 6718 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6719 pcc->msr_mask = (1ull << MSR_SF) | 6720 (1ull << MSR_HV) | 6721 (1ull << MSR_VR) | 6722 (1ull << MSR_VSX) | 6723 (1ull << MSR_EE) | 6724 (1ull << MSR_PR) | 6725 (1ull << MSR_FP) | 6726 (1ull << MSR_ME) | 6727 (1ull << MSR_FE0) | 6728 (1ull << MSR_SE) | 6729 (1ull << MSR_DE) | 6730 (1ull << MSR_FE1) | 6731 (1ull << MSR_IR) | 6732 (1ull << MSR_DR) | 6733 (1ull << MSR_PMM) | 6734 (1ull << MSR_RI) | 6735 (1ull << MSR_LE); 6736 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6737 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6738 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6739 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6740 LPCR_DEE | LPCR_OEE)) 6741 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6742 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6743 /* DD2 adds an extra HAIL bit */ 6744 pcc->lpcr_mask |= LPCR_HAIL; 6745 6746 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6747 pcc->mmu_model = POWERPC_MMU_3_00; 6748 #if !defined(CONFIG_USER_ONLY) 6749 /* segment page size remain the same */ 6750 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6751 pcc->radix_page_info = &POWER10_radix_page_info; 6752 pcc->lrg_decr_bits = 56; 6753 #endif 6754 pcc->excp_model = POWERPC_EXCP_POWER10; 6755 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6756 pcc->bfd_mach = bfd_mach_ppc64; 6757 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6758 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6759 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6760 POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | 6761 POWERPC_FLAG_BHRB; 6762 pcc->l1_dcache_size = 0x8000; 6763 pcc->l1_icache_size = 0x8000; 6764 } 6765 6766 #if !defined(CONFIG_USER_ONLY) 6767 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6768 { 6769 CPUPPCState *env = &cpu->env; 6770 6771 cpu->vhyp = vhyp; 6772 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6773 6774 /* 6775 * With a virtual hypervisor mode we never allow the CPU to go 6776 * hypervisor mode itself 6777 */ 6778 env->msr_mask &= ~MSR_HVB; 6779 } 6780 6781 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6782 { 6783 CPUPPCState *env = &cpu->env; 6784 6785 /* 6786 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6787 * between threads. 6788 */ 6789 if (env->flags & POWERPC_FLAG_SMT) { 6790 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6791 } 6792 } 6793 #endif /* !defined(CONFIG_USER_ONLY) */ 6794 6795 #endif /* defined(TARGET_PPC64) */ 6796 6797 /*****************************************************************************/ 6798 /* Generic CPU instantiation routine */ 6799 static void init_ppc_proc(PowerPCCPU *cpu) 6800 { 6801 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6802 CPUPPCState *env = &cpu->env; 6803 #if !defined(CONFIG_USER_ONLY) 6804 int i; 6805 6806 /* Set all exception vectors to an invalid address */ 6807 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6808 env->excp_vectors[i] = (target_ulong)(-1ULL); 6809 } 6810 env->ivor_mask = 0x00000000; 6811 env->ivpr_mask = 0x00000000; 6812 /* Default MMU definitions */ 6813 env->nb_BATs = 0; 6814 env->nb_tlb = 0; 6815 env->nb_ways = 0; 6816 env->tlb_type = TLB_NONE; 6817 #endif 6818 /* Register SPR common to all PowerPC implementations */ 6819 register_generic_sprs(cpu); 6820 6821 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6822 (*pcc->init_proc)(env); 6823 6824 /* MSR bits & flags consistency checks */ 6825 if (env->msr_mask & (1 << 25)) { 6826 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6827 case POWERPC_FLAG_SPE: 6828 case POWERPC_FLAG_VRE: 6829 break; 6830 default: 6831 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6832 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6833 exit(1); 6834 } 6835 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6836 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6837 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6838 exit(1); 6839 } 6840 if (env->msr_mask & (1 << 17)) { 6841 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6842 case POWERPC_FLAG_TGPR: 6843 case POWERPC_FLAG_CE: 6844 break; 6845 default: 6846 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6847 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6848 exit(1); 6849 } 6850 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6851 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6852 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6853 exit(1); 6854 } 6855 if (env->msr_mask & (1 << 10)) { 6856 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6857 POWERPC_FLAG_UBLE)) { 6858 case POWERPC_FLAG_SE: 6859 case POWERPC_FLAG_DWE: 6860 case POWERPC_FLAG_UBLE: 6861 break; 6862 default: 6863 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6864 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6865 "POWERPC_FLAG_UBLE\n"); 6866 exit(1); 6867 } 6868 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6869 POWERPC_FLAG_UBLE)) { 6870 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6871 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6872 "POWERPC_FLAG_UBLE\n"); 6873 exit(1); 6874 } 6875 if (env->msr_mask & (1 << 9)) { 6876 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6877 case POWERPC_FLAG_BE: 6878 case POWERPC_FLAG_DE: 6879 break; 6880 default: 6881 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6882 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6883 exit(1); 6884 } 6885 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6886 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6887 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6888 exit(1); 6889 } 6890 if (env->msr_mask & (1 << 2)) { 6891 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6892 case POWERPC_FLAG_PX: 6893 case POWERPC_FLAG_PMM: 6894 break; 6895 default: 6896 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6897 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6898 exit(1); 6899 } 6900 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6901 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6902 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6903 exit(1); 6904 } 6905 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6906 fprintf(stderr, "PowerPC flags inconsistency\n" 6907 "Should define the time-base and decrementer clock source\n"); 6908 exit(1); 6909 } 6910 /* Allocate TLBs buffer when needed */ 6911 #if !defined(CONFIG_USER_ONLY) 6912 if (env->nb_tlb) { 6913 switch (env->tlb_type) { 6914 case TLB_6XX: 6915 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6916 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6917 break; 6918 case TLB_EMB: 6919 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6920 break; 6921 case TLB_MAS: 6922 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6923 break; 6924 } 6925 /* Pre-compute some useful values */ 6926 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6927 } 6928 #endif 6929 if (env->check_pow == NULL) { 6930 warn_report("no power management check handler registered." 6931 " Attempt QEMU to crash very soon !"); 6932 } 6933 6934 if (env->check_attn == NULL) { 6935 warn_report("no attn check handler registered." 6936 " Attempt QEMU to crash very soon !"); 6937 } 6938 } 6939 6940 6941 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6942 { 6943 CPUState *cs = CPU(dev); 6944 PowerPCCPU *cpu = POWERPC_CPU(dev); 6945 CPUPPCState *env = &cpu->env; 6946 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6947 Error *local_err = NULL; 6948 6949 cpu_exec_realizefn(cs, &local_err); 6950 if (local_err != NULL) { 6951 error_propagate(errp, local_err); 6952 return; 6953 } 6954 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6955 cpu->vcpu_id = cs->cpu_index; 6956 } 6957 6958 if (tcg_enabled()) { 6959 if (ppc_fixup_cpu(cpu) != 0) { 6960 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6961 goto unrealize; 6962 } 6963 } 6964 6965 create_ppc_opcodes(cpu, &local_err); 6966 if (local_err != NULL) { 6967 error_propagate(errp, local_err); 6968 goto unrealize; 6969 } 6970 init_ppc_proc(cpu); 6971 6972 ppc_gdb_init(cs, pcc); 6973 qemu_init_vcpu(cs); 6974 6975 pcc->parent_realize(dev, errp); 6976 6977 if (env_cpu(env)->nr_threads > 1) { 6978 env->flags |= POWERPC_FLAG_SMT; 6979 } 6980 6981 return; 6982 6983 unrealize: 6984 cpu_exec_unrealizefn(cs); 6985 } 6986 6987 static void ppc_cpu_unrealize(DeviceState *dev) 6988 { 6989 PowerPCCPU *cpu = POWERPC_CPU(dev); 6990 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6991 6992 pcc->parent_unrealize(dev); 6993 6994 cpu_remove_sync(CPU(cpu)); 6995 6996 destroy_ppc_opcodes(cpu); 6997 } 6998 6999 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7000 { 7001 ObjectClass *oc = (ObjectClass *)a; 7002 uint32_t pvr = *(uint32_t *)b; 7003 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7004 7005 /* -cpu host does a PVR lookup during construction */ 7006 if (unlikely(strcmp(object_class_get_name(oc), 7007 TYPE_HOST_POWERPC_CPU) == 0)) { 7008 return -1; 7009 } 7010 7011 return pcc->pvr == pvr ? 0 : -1; 7012 } 7013 7014 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7015 { 7016 GSList *list, *item; 7017 PowerPCCPUClass *pcc = NULL; 7018 7019 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7020 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7021 if (item != NULL) { 7022 pcc = POWERPC_CPU_CLASS(item->data); 7023 } 7024 g_slist_free(list); 7025 7026 return pcc; 7027 } 7028 7029 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7030 { 7031 ObjectClass *oc = (ObjectClass *)a; 7032 uint32_t pvr = *(uint32_t *)b; 7033 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7034 7035 /* -cpu host does a PVR lookup during construction */ 7036 if (unlikely(strcmp(object_class_get_name(oc), 7037 TYPE_HOST_POWERPC_CPU) == 0)) { 7038 return -1; 7039 } 7040 7041 if (pcc->pvr_match(pcc, pvr, true)) { 7042 return 0; 7043 } 7044 7045 return -1; 7046 } 7047 7048 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7049 { 7050 GSList *list, *item; 7051 PowerPCCPUClass *pcc = NULL; 7052 7053 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7054 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7055 if (item != NULL) { 7056 pcc = POWERPC_CPU_CLASS(item->data); 7057 } 7058 g_slist_free(list); 7059 7060 return pcc; 7061 } 7062 7063 static const char *ppc_cpu_lookup_alias(const char *alias) 7064 { 7065 int ai; 7066 7067 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7068 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7069 return ppc_cpu_aliases[ai].model; 7070 } 7071 } 7072 7073 return NULL; 7074 } 7075 7076 ObjectClass *ppc_cpu_class_by_name(const char *name) 7077 { 7078 char *cpu_model, *typename; 7079 ObjectClass *oc; 7080 const char *p; 7081 unsigned long pvr; 7082 7083 /* 7084 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7085 * 0x prefix if present) 7086 */ 7087 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7088 int len = p - name; 7089 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7090 if ((len == 8) && (*p == '\0')) { 7091 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7092 } 7093 } 7094 7095 /* 7096 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7097 * do not have a "max" CPU with all possible emulated features enabled. 7098 * Return the default CPU type for the machine because that has greater 7099 * chance of being useful as the "max" CPU. 7100 */ 7101 #if !defined(CONFIG_USER_ONLY) 7102 if (strcmp(name, "max") == 0) { 7103 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7104 if (mc) { 7105 return object_class_by_name(mc->default_cpu_type); 7106 } 7107 } 7108 #endif 7109 7110 cpu_model = g_ascii_strdown(name, -1); 7111 p = ppc_cpu_lookup_alias(cpu_model); 7112 if (p) { 7113 g_free(cpu_model); 7114 cpu_model = g_strdup(p); 7115 } 7116 7117 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7118 oc = object_class_by_name(typename); 7119 g_free(typename); 7120 g_free(cpu_model); 7121 7122 return oc; 7123 } 7124 7125 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7126 { 7127 ObjectClass *oc = OBJECT_CLASS(pcc); 7128 7129 while (oc && !object_class_is_abstract(oc)) { 7130 oc = object_class_get_parent(oc); 7131 } 7132 assert(oc); 7133 7134 return POWERPC_CPU_CLASS(oc); 7135 } 7136 7137 /* Sort by PVR, ordering special case "host" last. */ 7138 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7139 { 7140 ObjectClass *oc_a = (ObjectClass *)a; 7141 ObjectClass *oc_b = (ObjectClass *)b; 7142 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7143 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7144 const char *name_a = object_class_get_name(oc_a); 7145 const char *name_b = object_class_get_name(oc_b); 7146 7147 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7148 return 1; 7149 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7150 return -1; 7151 } else { 7152 /* Avoid an integer overflow during subtraction */ 7153 if (pcc_a->pvr < pcc_b->pvr) { 7154 return -1; 7155 } else if (pcc_a->pvr > pcc_b->pvr) { 7156 return 1; 7157 } else { 7158 return 0; 7159 } 7160 } 7161 } 7162 7163 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7164 { 7165 ObjectClass *oc = data; 7166 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7167 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7168 const char *typename = object_class_get_name(oc); 7169 char *name; 7170 int i; 7171 7172 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7173 return; 7174 } 7175 7176 name = cpu_model_from_type(typename); 7177 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7178 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7179 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7180 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7181 7182 if (alias_oc != oc) { 7183 continue; 7184 } 7185 /* 7186 * If running with KVM, we might update the family alias later, so 7187 * avoid printing the wrong alias here and use "preferred" instead 7188 */ 7189 if (strcmp(alias->alias, family->desc) == 0) { 7190 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7191 alias->alias, family->desc); 7192 } else { 7193 qemu_printf(" %-16s (alias for %s)\n", 7194 alias->alias, name); 7195 } 7196 } 7197 g_free(name); 7198 } 7199 7200 void ppc_cpu_list(void) 7201 { 7202 GSList *list; 7203 7204 qemu_printf("Available CPUs:\n"); 7205 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7206 list = g_slist_sort(list, ppc_cpu_list_compare); 7207 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7208 g_slist_free(list); 7209 7210 #ifdef CONFIG_KVM 7211 qemu_printf("\n"); 7212 qemu_printf(" %s\n", "host"); 7213 #endif 7214 } 7215 7216 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7217 { 7218 PowerPCCPU *cpu = POWERPC_CPU(cs); 7219 7220 cpu->env.nip = value; 7221 } 7222 7223 static vaddr ppc_cpu_get_pc(CPUState *cs) 7224 { 7225 PowerPCCPU *cpu = POWERPC_CPU(cs); 7226 7227 return cpu->env.nip; 7228 } 7229 7230 #ifdef CONFIG_TCG 7231 static void ppc_restore_state_to_opc(CPUState *cs, 7232 const TranslationBlock *tb, 7233 const uint64_t *data) 7234 { 7235 PowerPCCPU *cpu = POWERPC_CPU(cs); 7236 7237 cpu->env.nip = data[0]; 7238 } 7239 #endif /* CONFIG_TCG */ 7240 7241 static bool ppc_cpu_has_work(CPUState *cs) 7242 { 7243 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7244 } 7245 7246 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7247 { 7248 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7249 } 7250 7251 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7252 { 7253 CPUState *cs = CPU(obj); 7254 PowerPCCPU *cpu = POWERPC_CPU(cs); 7255 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7256 CPUPPCState *env = &cpu->env; 7257 target_ulong msr; 7258 int i; 7259 7260 if (pcc->parent_phases.hold) { 7261 pcc->parent_phases.hold(obj, type); 7262 } 7263 7264 msr = (target_ulong)0; 7265 msr |= (target_ulong)MSR_HVB; 7266 msr |= (target_ulong)1 << MSR_EP; 7267 #if defined(DO_SINGLE_STEP) && 0 7268 /* Single step trace mode */ 7269 msr |= (target_ulong)1 << MSR_SE; 7270 msr |= (target_ulong)1 << MSR_BE; 7271 #endif 7272 #if defined(CONFIG_USER_ONLY) 7273 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7274 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7275 msr |= (target_ulong)1 << MSR_FE1; 7276 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7277 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7278 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7279 msr |= (target_ulong)1 << MSR_PR; 7280 #if defined(TARGET_PPC64) 7281 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7282 #endif 7283 #if !TARGET_BIG_ENDIAN 7284 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7285 if (!((env->msr_mask >> MSR_LE) & 1)) { 7286 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7287 exit(1); 7288 } 7289 #endif 7290 #endif 7291 7292 #if defined(TARGET_PPC64) 7293 if (mmu_is_64bit(env->mmu_model)) { 7294 msr |= (1ULL << MSR_SF); 7295 } 7296 #endif 7297 7298 hreg_store_msr(env, msr, 1); 7299 7300 #if !defined(CONFIG_USER_ONLY) 7301 env->nip = env->hreset_vector | env->excp_prefix; 7302 7303 if (tcg_enabled()) { 7304 cpu_breakpoint_remove_all(cs, BP_CPU); 7305 cpu_watchpoint_remove_all(cs, BP_CPU); 7306 if (env->mmu_model != POWERPC_MMU_REAL) { 7307 ppc_tlb_invalidate_all(env); 7308 } 7309 pmu_mmcr01a_updated(env); 7310 } 7311 7312 /* clean any pending stop state */ 7313 env->resume_as_sreset = 0; 7314 #endif 7315 hreg_compute_hflags(env); 7316 env->reserve_addr = (target_ulong)-1ULL; 7317 /* Be sure no exception or interrupt is pending */ 7318 env->pending_interrupts = 0; 7319 cs->exception_index = POWERPC_EXCP_NONE; 7320 env->error_code = 0; 7321 ppc_irq_reset(cpu); 7322 7323 /* tininess for underflow is detected before rounding */ 7324 set_float_detect_tininess(float_tininess_before_rounding, 7325 &env->fp_status); 7326 7327 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7328 ppc_spr_t *spr = &env->spr_cb[i]; 7329 7330 if (!spr->name) { 7331 continue; 7332 } 7333 env->spr[i] = spr->default_value; 7334 } 7335 7336 #if defined(TARGET_PPC64) 7337 bhrb_reset_state(env); 7338 #endif 7339 } 7340 7341 #ifndef CONFIG_USER_ONLY 7342 7343 static bool ppc_cpu_is_big_endian(CPUState *cs) 7344 { 7345 cpu_synchronize_state(cs); 7346 7347 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7348 } 7349 7350 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7351 uint64_t **irq_counts, unsigned int *nb_irqs) 7352 { 7353 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7354 7355 *irq_counts = env->excp_stats; 7356 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7357 return true; 7358 } 7359 7360 #ifdef CONFIG_TCG 7361 static void ppc_cpu_exec_enter(CPUState *cs) 7362 { 7363 PowerPCCPU *cpu = POWERPC_CPU(cs); 7364 7365 if (cpu->vhyp) { 7366 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7367 } 7368 } 7369 7370 static void ppc_cpu_exec_exit(CPUState *cs) 7371 { 7372 PowerPCCPU *cpu = POWERPC_CPU(cs); 7373 7374 if (cpu->vhyp) { 7375 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7376 } 7377 } 7378 #endif /* CONFIG_TCG */ 7379 7380 #endif /* !CONFIG_USER_ONLY */ 7381 7382 static void ppc_cpu_instance_init(Object *obj) 7383 { 7384 PowerPCCPU *cpu = POWERPC_CPU(obj); 7385 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7386 CPUPPCState *env = &cpu->env; 7387 7388 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7389 7390 env->msr_mask = pcc->msr_mask; 7391 env->mmu_model = pcc->mmu_model; 7392 env->excp_model = pcc->excp_model; 7393 env->bus_model = pcc->bus_model; 7394 env->insns_flags = pcc->insns_flags; 7395 env->insns_flags2 = pcc->insns_flags2; 7396 env->flags = pcc->flags; 7397 env->bfd_mach = pcc->bfd_mach; 7398 env->check_pow = pcc->check_pow; 7399 env->check_attn = pcc->check_attn; 7400 7401 /* 7402 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7403 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7404 * mode support will remain, thus enforcing that we cannot use 7405 * priv. instructions in guest in PAPR mode. For 970 we currently 7406 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7407 * 970. If we ever want to support 970 HV mode, we'll have to add 7408 * a processor attribute of some sort. 7409 */ 7410 #if !defined(CONFIG_USER_ONLY) 7411 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7412 #endif 7413 7414 ppc_hash64_init(cpu); 7415 } 7416 7417 static void ppc_cpu_instance_finalize(Object *obj) 7418 { 7419 PowerPCCPU *cpu = POWERPC_CPU(obj); 7420 7421 ppc_hash64_finalize(cpu); 7422 } 7423 7424 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7425 { 7426 return pcc->pvr == pvr; 7427 } 7428 7429 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7430 { 7431 CPUPPCState *env = cpu_env(cs); 7432 7433 if ((env->hflags >> MSR_LE) & 1) { 7434 info->endian = BFD_ENDIAN_LITTLE; 7435 } 7436 info->mach = env->bfd_mach; 7437 if (!env->bfd_mach) { 7438 #ifdef TARGET_PPC64 7439 info->mach = bfd_mach_ppc64; 7440 #else 7441 info->mach = bfd_mach_ppc; 7442 #endif 7443 } 7444 7445 info->cap_arch = CS_ARCH_PPC; 7446 #ifdef TARGET_PPC64 7447 info->cap_mode = CS_MODE_64; 7448 #endif 7449 } 7450 7451 static Property ppc_cpu_properties[] = { 7452 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7453 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7454 false), 7455 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7456 false), 7457 DEFINE_PROP_END_OF_LIST(), 7458 }; 7459 7460 #ifndef CONFIG_USER_ONLY 7461 #include "hw/core/sysemu-cpu-ops.h" 7462 7463 static const struct SysemuCPUOps ppc_sysemu_ops = { 7464 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7465 .write_elf32_note = ppc32_cpu_write_elf32_note, 7466 .write_elf64_note = ppc64_cpu_write_elf64_note, 7467 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7468 .legacy_vmsd = &vmstate_ppc_cpu, 7469 }; 7470 #endif 7471 7472 #ifdef CONFIG_TCG 7473 #include "hw/core/tcg-cpu-ops.h" 7474 7475 static const TCGCPUOps ppc_tcg_ops = { 7476 .initialize = ppc_translate_init, 7477 .restore_state_to_opc = ppc_restore_state_to_opc, 7478 7479 #ifdef CONFIG_USER_ONLY 7480 .record_sigsegv = ppc_cpu_record_sigsegv, 7481 #else 7482 .tlb_fill = ppc_cpu_tlb_fill, 7483 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7484 .do_interrupt = ppc_cpu_do_interrupt, 7485 .cpu_exec_enter = ppc_cpu_exec_enter, 7486 .cpu_exec_exit = ppc_cpu_exec_exit, 7487 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7488 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7489 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7490 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7491 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7492 #endif /* !CONFIG_USER_ONLY */ 7493 }; 7494 #endif /* CONFIG_TCG */ 7495 7496 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7497 { 7498 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7499 CPUClass *cc = CPU_CLASS(oc); 7500 DeviceClass *dc = DEVICE_CLASS(oc); 7501 ResettableClass *rc = RESETTABLE_CLASS(oc); 7502 7503 device_class_set_parent_realize(dc, ppc_cpu_realize, 7504 &pcc->parent_realize); 7505 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7506 &pcc->parent_unrealize); 7507 pcc->pvr_match = ppc_pvr_match_default; 7508 device_class_set_props(dc, ppc_cpu_properties); 7509 7510 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7511 &pcc->parent_phases); 7512 7513 cc->class_by_name = ppc_cpu_class_by_name; 7514 cc->has_work = ppc_cpu_has_work; 7515 cc->mmu_index = ppc_cpu_mmu_index; 7516 cc->dump_state = ppc_cpu_dump_state; 7517 cc->set_pc = ppc_cpu_set_pc; 7518 cc->get_pc = ppc_cpu_get_pc; 7519 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7520 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7521 #ifndef CONFIG_USER_ONLY 7522 cc->sysemu_ops = &ppc_sysemu_ops; 7523 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7524 7525 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7526 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7527 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7528 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7529 #endif 7530 7531 cc->gdb_num_core_regs = 71; 7532 #ifdef USE_APPLE_GDB 7533 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7534 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7535 cc->gdb_num_core_regs = 71 + 32; 7536 #endif 7537 7538 cc->gdb_arch_name = ppc_gdb_arch_name; 7539 #if defined(TARGET_PPC64) 7540 cc->gdb_core_xml_file = "power64-core.xml"; 7541 #else 7542 cc->gdb_core_xml_file = "power-core.xml"; 7543 #endif 7544 cc->disas_set_info = ppc_disas_set_info; 7545 7546 dc->fw_name = "PowerPC,UNKNOWN"; 7547 7548 #ifdef CONFIG_TCG 7549 cc->tcg_ops = &ppc_tcg_ops; 7550 #endif /* CONFIG_TCG */ 7551 } 7552 7553 static const TypeInfo ppc_cpu_type_info = { 7554 .name = TYPE_POWERPC_CPU, 7555 .parent = TYPE_CPU, 7556 .instance_size = sizeof(PowerPCCPU), 7557 .instance_align = __alignof__(PowerPCCPU), 7558 .instance_init = ppc_cpu_instance_init, 7559 .instance_finalize = ppc_cpu_instance_finalize, 7560 .abstract = true, 7561 .class_size = sizeof(PowerPCCPUClass), 7562 .class_init = ppc_cpu_class_init, 7563 #ifndef CONFIG_USER_ONLY 7564 .interfaces = (InterfaceInfo[]) { 7565 { TYPE_INTERRUPT_STATS_PROVIDER }, 7566 { } 7567 }, 7568 #endif 7569 }; 7570 7571 #ifndef CONFIG_USER_ONLY 7572 static const TypeInfo ppc_vhyp_type_info = { 7573 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7574 .parent = TYPE_INTERFACE, 7575 .class_size = sizeof(PPCVirtualHypervisorClass), 7576 }; 7577 #endif 7578 7579 static void ppc_cpu_register_types(void) 7580 { 7581 type_register_static(&ppc_cpu_type_info); 7582 #ifndef CONFIG_USER_ONLY 7583 type_register_static(&ppc_vhyp_type_info); 7584 #endif 7585 } 7586 7587 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7588 { 7589 #define RGPL 4 7590 #define RFPL 4 7591 7592 CPUPPCState *env = cpu_env(cs); 7593 int i; 7594 7595 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7596 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7597 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7598 cs->cpu_index); 7599 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7600 "%08x iidx %d didx %d\n", 7601 env->msr, env->spr[SPR_HID0], env->hflags, 7602 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7603 #if !defined(CONFIG_USER_ONLY) 7604 if (env->tb_env) { 7605 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7606 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7607 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7608 } 7609 #else 7610 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7611 cpu_ppc_load_tbl(env)); 7612 #endif 7613 for (i = 0; i < 32; i++) { 7614 if ((i & (RGPL - 1)) == 0) { 7615 qemu_fprintf(f, "GPR%02d", i); 7616 } 7617 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7618 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7619 qemu_fprintf(f, "\n"); 7620 } 7621 } 7622 qemu_fprintf(f, "CR "); 7623 for (i = 0; i < 8; i++) 7624 qemu_fprintf(f, "%01x", env->crf[i]); 7625 qemu_fprintf(f, " ["); 7626 for (i = 0; i < 8; i++) { 7627 char a = '-'; 7628 if (env->crf[i] & 0x08) { 7629 a = 'L'; 7630 } else if (env->crf[i] & 0x04) { 7631 a = 'G'; 7632 } else if (env->crf[i] & 0x02) { 7633 a = 'E'; 7634 } 7635 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7636 } 7637 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7638 (int)env->reserve_length, env->reserve_addr); 7639 7640 if (flags & CPU_DUMP_FPU) { 7641 for (i = 0; i < 32; i++) { 7642 if ((i & (RFPL - 1)) == 0) { 7643 qemu_fprintf(f, "FPR%02d", i); 7644 } 7645 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7646 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7647 qemu_fprintf(f, "\n"); 7648 } 7649 } 7650 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7651 } 7652 7653 #if !defined(CONFIG_USER_ONLY) 7654 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7655 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7656 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7657 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7658 7659 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7660 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7661 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7662 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7663 7664 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7665 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7666 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7667 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7668 7669 switch (env->excp_model) { 7670 #if defined(TARGET_PPC64) 7671 case POWERPC_EXCP_POWER7: 7672 case POWERPC_EXCP_POWER8: 7673 case POWERPC_EXCP_POWER9: 7674 case POWERPC_EXCP_POWER10: 7675 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7676 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7677 break; 7678 #endif 7679 case POWERPC_EXCP_BOOKE: 7680 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7681 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7682 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7683 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7684 7685 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7686 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7687 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7688 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7689 7690 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7691 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7692 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7693 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7694 7695 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7696 " EPR " TARGET_FMT_lx "\n", 7697 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7698 env->spr[SPR_BOOKE_EPR]); 7699 7700 /* FSL-specific */ 7701 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7702 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7703 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7704 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7705 7706 /* 7707 * IVORs are left out as they are large and do not change often -- 7708 * they can be read with "p $ivor0", "p $ivor1", etc. 7709 */ 7710 break; 7711 case POWERPC_EXCP_40x: 7712 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7713 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7714 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7715 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7716 7717 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7718 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7719 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7720 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7721 break; 7722 default: 7723 break; 7724 } 7725 7726 #if defined(TARGET_PPC64) 7727 if (env->flags & POWERPC_FLAG_CFAR) { 7728 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7729 } 7730 #endif 7731 7732 if (env->spr_cb[SPR_LPCR].name) { 7733 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7734 } 7735 7736 switch (env->mmu_model) { 7737 case POWERPC_MMU_32B: 7738 case POWERPC_MMU_SOFT_6xx: 7739 #if defined(TARGET_PPC64) 7740 case POWERPC_MMU_64B: 7741 case POWERPC_MMU_2_03: 7742 case POWERPC_MMU_2_06: 7743 case POWERPC_MMU_2_07: 7744 case POWERPC_MMU_3_00: 7745 #endif 7746 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7747 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7748 } 7749 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7750 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7751 } 7752 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7753 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7754 break; 7755 case POWERPC_MMU_BOOKE206: 7756 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7757 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7758 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7759 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7760 7761 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7762 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7763 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7764 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7765 7766 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7767 " TLB1CFG " TARGET_FMT_lx "\n", 7768 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7769 env->spr[SPR_BOOKE_TLB1CFG]); 7770 break; 7771 default: 7772 break; 7773 } 7774 #endif 7775 7776 #undef RGPL 7777 #undef RFPL 7778 } 7779 type_init(ppc_cpu_register_types) 7780