1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 601 implementation */ 753 static void register_601_sprs(CPUPPCState *env) 754 { 755 /* Multiplication/division register */ 756 /* MQ */ 757 spr_register(env, SPR_MQ, "MQ", 758 &spr_read_generic, &spr_write_generic, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* RTC registers */ 762 spr_register(env, SPR_601_RTCU, "RTCU", 763 SPR_NOACCESS, SPR_NOACCESS, 764 SPR_NOACCESS, &spr_write_601_rtcu, 765 0x00000000); 766 spr_register(env, SPR_601_VRTCU, "RTCU", 767 &spr_read_601_rtcu, SPR_NOACCESS, 768 &spr_read_601_rtcu, SPR_NOACCESS, 769 0x00000000); 770 spr_register(env, SPR_601_RTCL, "RTCL", 771 SPR_NOACCESS, SPR_NOACCESS, 772 SPR_NOACCESS, &spr_write_601_rtcl, 773 0x00000000); 774 spr_register(env, SPR_601_VRTCL, "RTCL", 775 &spr_read_601_rtcl, SPR_NOACCESS, 776 &spr_read_601_rtcl, SPR_NOACCESS, 777 0x00000000); 778 /* Timer */ 779 #if 0 /* ? */ 780 spr_register(env, SPR_601_UDECR, "UDECR", 781 &spr_read_decr, SPR_NOACCESS, 782 &spr_read_decr, SPR_NOACCESS, 783 0x00000000); 784 #endif 785 /* External access control */ 786 /* XXX : not implemented */ 787 spr_register(env, SPR_EAR, "EAR", 788 SPR_NOACCESS, SPR_NOACCESS, 789 &spr_read_generic, &spr_write_generic, 790 0x00000000); 791 /* Memory management */ 792 #if !defined(CONFIG_USER_ONLY) 793 spr_register(env, SPR_IBAT0U, "IBAT0U", 794 SPR_NOACCESS, SPR_NOACCESS, 795 &spr_read_601_ubat, &spr_write_601_ubatu, 796 0x00000000); 797 spr_register(env, SPR_IBAT0L, "IBAT0L", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_601_ubat, &spr_write_601_ubatl, 800 0x00000000); 801 spr_register(env, SPR_IBAT1U, "IBAT1U", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_601_ubat, &spr_write_601_ubatu, 804 0x00000000); 805 spr_register(env, SPR_IBAT1L, "IBAT1L", 806 SPR_NOACCESS, SPR_NOACCESS, 807 &spr_read_601_ubat, &spr_write_601_ubatl, 808 0x00000000); 809 spr_register(env, SPR_IBAT2U, "IBAT2U", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_601_ubat, &spr_write_601_ubatu, 812 0x00000000); 813 spr_register(env, SPR_IBAT2L, "IBAT2L", 814 SPR_NOACCESS, SPR_NOACCESS, 815 &spr_read_601_ubat, &spr_write_601_ubatl, 816 0x00000000); 817 spr_register(env, SPR_IBAT3U, "IBAT3U", 818 SPR_NOACCESS, SPR_NOACCESS, 819 &spr_read_601_ubat, &spr_write_601_ubatu, 820 0x00000000); 821 spr_register(env, SPR_IBAT3L, "IBAT3L", 822 SPR_NOACCESS, SPR_NOACCESS, 823 &spr_read_601_ubat, &spr_write_601_ubatl, 824 0x00000000); 825 env->nb_BATs = 4; 826 #endif 827 } 828 829 static void register_74xx_sprs(CPUPPCState *env) 830 { 831 /* Processor identification */ 832 spr_register(env, SPR_PIR, "PIR", 833 SPR_NOACCESS, SPR_NOACCESS, 834 &spr_read_generic, &spr_write_pir, 835 0x00000000); 836 /* XXX : not implemented */ 837 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 838 SPR_NOACCESS, SPR_NOACCESS, 839 &spr_read_generic, &spr_write_generic, 840 0x00000000); 841 /* XXX : not implemented */ 842 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 843 &spr_read_ureg, SPR_NOACCESS, 844 &spr_read_ureg, SPR_NOACCESS, 845 0x00000000); 846 /* XXX: not implemented */ 847 spr_register(env, SPR_BAMR, "BAMR", 848 SPR_NOACCESS, SPR_NOACCESS, 849 &spr_read_generic, &spr_write_generic, 850 0x00000000); 851 /* XXX : not implemented */ 852 spr_register(env, SPR_MSSCR0, "MSSCR0", 853 SPR_NOACCESS, SPR_NOACCESS, 854 &spr_read_generic, &spr_write_generic, 855 0x00000000); 856 /* Hardware implementation registers */ 857 /* XXX : not implemented */ 858 spr_register(env, SPR_HID0, "HID0", 859 SPR_NOACCESS, SPR_NOACCESS, 860 &spr_read_generic, &spr_write_generic, 861 0x00000000); 862 /* XXX : not implemented */ 863 spr_register(env, SPR_HID1, "HID1", 864 SPR_NOACCESS, SPR_NOACCESS, 865 &spr_read_generic, &spr_write_generic, 866 0x00000000); 867 /* Altivec */ 868 spr_register(env, SPR_VRSAVE, "VRSAVE", 869 &spr_read_generic, &spr_write_generic, 870 &spr_read_generic, &spr_write_generic, 871 0x00000000); 872 /* XXX : not implemented */ 873 spr_register(env, SPR_L2CR, "L2CR", 874 SPR_NOACCESS, SPR_NOACCESS, 875 &spr_read_generic, spr_access_nop, 876 0x00000000); 877 } 878 879 static void register_l3_ctrl(CPUPPCState *env) 880 { 881 /* L3CR */ 882 /* XXX : not implemented */ 883 spr_register(env, SPR_L3CR, "L3CR", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_generic, 886 0x00000000); 887 /* L3ITCR0 */ 888 /* XXX : not implemented */ 889 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, &spr_write_generic, 892 0x00000000); 893 /* L3PM */ 894 /* XXX : not implemented */ 895 spr_register(env, SPR_L3PM, "L3PM", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 } 900 901 static void register_usprg3_sprs(CPUPPCState *env) 902 { 903 spr_register(env, SPR_USPRG3, "USPRG3", 904 &spr_read_ureg, SPR_NOACCESS, 905 &spr_read_ureg, SPR_NOACCESS, 906 0x00000000); 907 } 908 909 static void register_usprgh_sprs(CPUPPCState *env) 910 { 911 spr_register(env, SPR_USPRG4, "USPRG4", 912 &spr_read_ureg, SPR_NOACCESS, 913 &spr_read_ureg, SPR_NOACCESS, 914 0x00000000); 915 spr_register(env, SPR_USPRG5, "USPRG5", 916 &spr_read_ureg, SPR_NOACCESS, 917 &spr_read_ureg, SPR_NOACCESS, 918 0x00000000); 919 spr_register(env, SPR_USPRG6, "USPRG6", 920 &spr_read_ureg, SPR_NOACCESS, 921 &spr_read_ureg, SPR_NOACCESS, 922 0x00000000); 923 spr_register(env, SPR_USPRG7, "USPRG7", 924 &spr_read_ureg, SPR_NOACCESS, 925 &spr_read_ureg, SPR_NOACCESS, 926 0x00000000); 927 } 928 929 /* PowerPC BookE SPR */ 930 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 931 { 932 const char *ivor_names[64] = { 933 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 934 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 935 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 936 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 937 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 938 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 939 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 940 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 941 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 942 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 943 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 944 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 945 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 946 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 947 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 948 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 949 }; 950 #define SPR_BOOKE_IVORxx (-1) 951 int ivor_sprn[64] = { 952 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 953 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 954 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 955 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 956 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 957 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 958 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 959 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 960 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 961 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 962 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 963 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 964 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 965 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 966 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 967 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 968 }; 969 int i; 970 971 /* Interrupt processing */ 972 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_generic, 975 0x00000000); 976 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 977 SPR_NOACCESS, SPR_NOACCESS, 978 &spr_read_generic, &spr_write_generic, 979 0x00000000); 980 /* Debug */ 981 /* XXX : not implemented */ 982 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 983 SPR_NOACCESS, SPR_NOACCESS, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 /* XXX : not implemented */ 987 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 988 SPR_NOACCESS, SPR_NOACCESS, 989 &spr_read_generic, &spr_write_generic, 990 0x00000000); 991 /* XXX : not implemented */ 992 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 993 SPR_NOACCESS, SPR_NOACCESS, 994 &spr_read_generic, &spr_write_generic, 995 0x00000000); 996 /* XXX : not implemented */ 997 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 998 SPR_NOACCESS, SPR_NOACCESS, 999 &spr_read_generic, &spr_write_generic, 1000 0x00000000); 1001 /* XXX : not implemented */ 1002 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_40x_dbcr0, 1005 0x00000000); 1006 /* XXX : not implemented */ 1007 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1008 SPR_NOACCESS, SPR_NOACCESS, 1009 &spr_read_generic, &spr_write_generic, 1010 0x00000000); 1011 /* XXX : not implemented */ 1012 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_generic, &spr_write_generic, 1023 0x00000000); 1024 /* XXX : not implemented */ 1025 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1026 SPR_NOACCESS, SPR_NOACCESS, 1027 &spr_read_generic, &spr_write_clear, 1028 0x00000000); 1029 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1030 SPR_NOACCESS, SPR_NOACCESS, 1031 &spr_read_generic, &spr_write_generic, 1032 0x00000000); 1033 spr_register(env, SPR_BOOKE_ESR, "ESR", 1034 SPR_NOACCESS, SPR_NOACCESS, 1035 &spr_read_generic, &spr_write_generic, 1036 0x00000000); 1037 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1038 SPR_NOACCESS, SPR_NOACCESS, 1039 &spr_read_generic, &spr_write_excp_prefix, 1040 0x00000000); 1041 /* Exception vectors */ 1042 for (i = 0; i < 64; i++) { 1043 if (ivor_mask & (1ULL << i)) { 1044 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1045 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1046 exit(1); 1047 } 1048 spr_register(env, ivor_sprn[i], ivor_names[i], 1049 SPR_NOACCESS, SPR_NOACCESS, 1050 &spr_read_generic, &spr_write_excp_vector, 1051 0x00000000); 1052 } 1053 } 1054 spr_register(env, SPR_BOOKE_PID, "PID", 1055 SPR_NOACCESS, SPR_NOACCESS, 1056 &spr_read_generic, &spr_write_booke_pid, 1057 0x00000000); 1058 spr_register(env, SPR_BOOKE_TCR, "TCR", 1059 SPR_NOACCESS, SPR_NOACCESS, 1060 &spr_read_generic, &spr_write_booke_tcr, 1061 0x00000000); 1062 spr_register(env, SPR_BOOKE_TSR, "TSR", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_booke_tsr, 1065 0x00000000); 1066 /* Timer */ 1067 spr_register(env, SPR_DECR, "DECR", 1068 SPR_NOACCESS, SPR_NOACCESS, 1069 &spr_read_decr, &spr_write_decr, 1070 0x00000000); 1071 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1072 SPR_NOACCESS, SPR_NOACCESS, 1073 SPR_NOACCESS, &spr_write_generic, 1074 0x00000000); 1075 /* SPRGs */ 1076 spr_register(env, SPR_USPRG0, "USPRG0", 1077 &spr_read_generic, &spr_write_generic, 1078 &spr_read_generic, &spr_write_generic, 1079 0x00000000); 1080 spr_register(env, SPR_SPRG4, "SPRG4", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 spr_register(env, SPR_SPRG5, "SPRG5", 1085 SPR_NOACCESS, SPR_NOACCESS, 1086 &spr_read_generic, &spr_write_generic, 1087 0x00000000); 1088 spr_register(env, SPR_SPRG6, "SPRG6", 1089 SPR_NOACCESS, SPR_NOACCESS, 1090 &spr_read_generic, &spr_write_generic, 1091 0x00000000); 1092 spr_register(env, SPR_SPRG7, "SPRG7", 1093 SPR_NOACCESS, SPR_NOACCESS, 1094 &spr_read_generic, &spr_write_generic, 1095 0x00000000); 1096 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_generic, 1099 0x00000000); 1100 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 } 1105 1106 #if !defined(CONFIG_USER_ONLY) 1107 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1108 uint32_t maxsize, uint32_t flags, 1109 uint32_t nentries) 1110 { 1111 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1112 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1113 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1114 flags | nentries; 1115 } 1116 #endif /* !CONFIG_USER_ONLY */ 1117 1118 /* BookE 2.06 storage control registers */ 1119 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1120 uint32_t *tlbncfg, uint32_t mmucfg) 1121 { 1122 #if !defined(CONFIG_USER_ONLY) 1123 const char *mas_names[8] = { 1124 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1125 }; 1126 int mas_sprn[8] = { 1127 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1128 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1129 }; 1130 int i; 1131 1132 /* TLB assist registers */ 1133 /* XXX : not implemented */ 1134 for (i = 0; i < 8; i++) { 1135 if (mas_mask & (1 << i)) { 1136 spr_register(env, mas_sprn[i], mas_names[i], 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, 1139 (i == 2 && (env->insns_flags & PPC_64B)) 1140 ? &spr_write_generic : &spr_write_generic32, 1141 0x00000000); 1142 } 1143 } 1144 if (env->nb_pids > 1) { 1145 /* XXX : not implemented */ 1146 spr_register(env, SPR_BOOKE_PID1, "PID1", 1147 SPR_NOACCESS, SPR_NOACCESS, 1148 &spr_read_generic, &spr_write_booke_pid, 1149 0x00000000); 1150 } 1151 if (env->nb_pids > 2) { 1152 /* XXX : not implemented */ 1153 spr_register(env, SPR_BOOKE_PID2, "PID2", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_booke_pid, 1156 0x00000000); 1157 } 1158 1159 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1160 SPR_NOACCESS, SPR_NOACCESS, 1161 &spr_read_generic, &spr_write_eplc, 1162 0x00000000); 1163 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_epsc, 1166 0x00000000); 1167 1168 /* XXX : not implemented */ 1169 spr_register(env, SPR_MMUCFG, "MMUCFG", 1170 SPR_NOACCESS, SPR_NOACCESS, 1171 &spr_read_generic, SPR_NOACCESS, 1172 mmucfg); 1173 switch (env->nb_ways) { 1174 case 4: 1175 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1176 SPR_NOACCESS, SPR_NOACCESS, 1177 &spr_read_generic, SPR_NOACCESS, 1178 tlbncfg[3]); 1179 /* Fallthru */ 1180 case 3: 1181 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, SPR_NOACCESS, 1184 tlbncfg[2]); 1185 /* Fallthru */ 1186 case 2: 1187 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, SPR_NOACCESS, 1190 tlbncfg[1]); 1191 /* Fallthru */ 1192 case 1: 1193 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1194 SPR_NOACCESS, SPR_NOACCESS, 1195 &spr_read_generic, SPR_NOACCESS, 1196 tlbncfg[0]); 1197 /* Fallthru */ 1198 case 0: 1199 default: 1200 break; 1201 } 1202 #endif 1203 1204 register_usprgh_sprs(env); 1205 } 1206 1207 /* SPR specific to PowerPC 440 implementation */ 1208 static void register_440_sprs(CPUPPCState *env) 1209 { 1210 /* Cache control */ 1211 /* XXX : not implemented */ 1212 spr_register(env, SPR_440_DNV0, "DNV0", 1213 SPR_NOACCESS, SPR_NOACCESS, 1214 &spr_read_generic, &spr_write_generic, 1215 0x00000000); 1216 /* XXX : not implemented */ 1217 spr_register(env, SPR_440_DNV1, "DNV1", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, &spr_write_generic, 1220 0x00000000); 1221 /* XXX : not implemented */ 1222 spr_register(env, SPR_440_DNV2, "DNV2", 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_generic, 1225 0x00000000); 1226 /* XXX : not implemented */ 1227 spr_register(env, SPR_440_DNV3, "DNV3", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_generic, 1230 0x00000000); 1231 /* XXX : not implemented */ 1232 spr_register(env, SPR_440_DTV0, "DTV0", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_generic, 1235 0x00000000); 1236 /* XXX : not implemented */ 1237 spr_register(env, SPR_440_DTV1, "DTV1", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, &spr_write_generic, 1240 0x00000000); 1241 /* XXX : not implemented */ 1242 spr_register(env, SPR_440_DTV2, "DTV2", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 /* XXX : not implemented */ 1247 spr_register(env, SPR_440_DTV3, "DTV3", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, &spr_write_generic, 1250 0x00000000); 1251 /* XXX : not implemented */ 1252 spr_register(env, SPR_440_DVLIM, "DVLIM", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_generic, 1255 0x00000000); 1256 /* XXX : not implemented */ 1257 spr_register(env, SPR_440_INV0, "INV0", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, &spr_write_generic, 1260 0x00000000); 1261 /* XXX : not implemented */ 1262 spr_register(env, SPR_440_INV1, "INV1", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 0x00000000); 1266 /* XXX : not implemented */ 1267 spr_register(env, SPR_440_INV2, "INV2", 1268 SPR_NOACCESS, SPR_NOACCESS, 1269 &spr_read_generic, &spr_write_generic, 1270 0x00000000); 1271 /* XXX : not implemented */ 1272 spr_register(env, SPR_440_INV3, "INV3", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_generic, &spr_write_generic, 1275 0x00000000); 1276 /* XXX : not implemented */ 1277 spr_register(env, SPR_440_ITV0, "ITV0", 1278 SPR_NOACCESS, SPR_NOACCESS, 1279 &spr_read_generic, &spr_write_generic, 1280 0x00000000); 1281 /* XXX : not implemented */ 1282 spr_register(env, SPR_440_ITV1, "ITV1", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 /* XXX : not implemented */ 1287 spr_register(env, SPR_440_ITV2, "ITV2", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, &spr_write_generic, 1290 0x00000000); 1291 /* XXX : not implemented */ 1292 spr_register(env, SPR_440_ITV3, "ITV3", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, &spr_write_generic, 1295 0x00000000); 1296 /* XXX : not implemented */ 1297 spr_register(env, SPR_440_IVLIM, "IVLIM", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 /* Cache debug */ 1302 /* XXX : not implemented */ 1303 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1304 SPR_NOACCESS, SPR_NOACCESS, 1305 &spr_read_generic, SPR_NOACCESS, 1306 0x00000000); 1307 /* XXX : not implemented */ 1308 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1309 SPR_NOACCESS, SPR_NOACCESS, 1310 &spr_read_generic, SPR_NOACCESS, 1311 0x00000000); 1312 /* XXX : not implemented */ 1313 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_generic, SPR_NOACCESS, 1316 0x00000000); 1317 /* XXX : not implemented */ 1318 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, SPR_NOACCESS, 1321 0x00000000); 1322 /* XXX : not implemented */ 1323 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, SPR_NOACCESS, 1326 0x00000000); 1327 /* XXX : not implemented */ 1328 spr_register(env, SPR_440_DBDR, "DBDR", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 /* Processor control */ 1333 spr_register(env, SPR_4xx_CCR0, "CCR0", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1338 SPR_NOACCESS, SPR_NOACCESS, 1339 &spr_read_generic, SPR_NOACCESS, 1340 0x00000000); 1341 /* Storage control */ 1342 spr_register(env, SPR_440_MMUCR, "MMUCR", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, &spr_write_generic, 1345 0x00000000); 1346 } 1347 1348 /* SPR shared between PowerPC 40x implementations */ 1349 static void register_40x_sprs(CPUPPCState *env) 1350 { 1351 /* Cache */ 1352 /* not emulated, as QEMU do not emulate caches */ 1353 spr_register(env, SPR_40x_DCCR, "DCCR", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 /* not emulated, as QEMU do not emulate caches */ 1358 spr_register(env, SPR_40x_ICCR, "ICCR", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 /* not emulated, as QEMU do not emulate caches */ 1363 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, SPR_NOACCESS, 1366 0x00000000); 1367 /* Exception */ 1368 spr_register(env, SPR_40x_DEAR, "DEAR", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 spr_register(env, SPR_40x_ESR, "ESR", 1373 SPR_NOACCESS, SPR_NOACCESS, 1374 &spr_read_generic, &spr_write_generic, 1375 0x00000000); 1376 spr_register(env, SPR_40x_EVPR, "EVPR", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, &spr_write_excp_prefix, 1379 0x00000000); 1380 spr_register(env, SPR_40x_SRR2, "SRR2", 1381 &spr_read_generic, &spr_write_generic, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 spr_register(env, SPR_40x_SRR3, "SRR3", 1385 &spr_read_generic, &spr_write_generic, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 /* Timers */ 1389 spr_register(env, SPR_40x_PIT, "PIT", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_40x_pit, &spr_write_40x_pit, 1392 0x00000000); 1393 spr_register(env, SPR_40x_TCR, "TCR", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_40x_tcr, 1396 0x00000000); 1397 spr_register(env, SPR_40x_TSR, "TSR", 1398 SPR_NOACCESS, SPR_NOACCESS, 1399 &spr_read_generic, &spr_write_40x_tsr, 1400 0x00000000); 1401 } 1402 1403 /* SPR specific to PowerPC 405 implementation */ 1404 static void register_405_sprs(CPUPPCState *env) 1405 { 1406 /* MMU */ 1407 spr_register(env, SPR_40x_PID, "PID", 1408 SPR_NOACCESS, SPR_NOACCESS, 1409 &spr_read_generic, &spr_write_40x_pid, 1410 0x00000000); 1411 spr_register(env, SPR_4xx_CCR0, "CCR0", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, &spr_write_generic, 1414 0x00700000); 1415 /* Debug interface */ 1416 /* XXX : not implemented */ 1417 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1418 SPR_NOACCESS, SPR_NOACCESS, 1419 &spr_read_generic, &spr_write_40x_dbcr0, 1420 0x00000000); 1421 /* XXX : not implemented */ 1422 spr_register(env, SPR_405_DBCR1, "DBCR1", 1423 SPR_NOACCESS, SPR_NOACCESS, 1424 &spr_read_generic, &spr_write_generic, 1425 0x00000000); 1426 /* XXX : not implemented */ 1427 spr_register(env, SPR_40x_DBSR, "DBSR", 1428 SPR_NOACCESS, SPR_NOACCESS, 1429 &spr_read_generic, &spr_write_clear, 1430 /* Last reset was system reset */ 1431 0x00000300); 1432 /* XXX : not implemented */ 1433 spr_register(env, SPR_40x_DAC1, "DAC1", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, &spr_write_generic, 1436 0x00000000); 1437 spr_register(env, SPR_40x_DAC2, "DAC2", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_generic, &spr_write_generic, 1440 0x00000000); 1441 /* XXX : not implemented */ 1442 spr_register(env, SPR_405_DVC1, "DVC1", 1443 SPR_NOACCESS, SPR_NOACCESS, 1444 &spr_read_generic, &spr_write_generic, 1445 0x00000000); 1446 /* XXX : not implemented */ 1447 spr_register(env, SPR_405_DVC2, "DVC2", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, &spr_write_generic, 1450 0x00000000); 1451 /* XXX : not implemented */ 1452 spr_register(env, SPR_40x_IAC1, "IAC1", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 spr_register(env, SPR_40x_IAC2, "IAC2", 1457 SPR_NOACCESS, SPR_NOACCESS, 1458 &spr_read_generic, &spr_write_generic, 1459 0x00000000); 1460 /* XXX : not implemented */ 1461 spr_register(env, SPR_405_IAC3, "IAC3", 1462 SPR_NOACCESS, SPR_NOACCESS, 1463 &spr_read_generic, &spr_write_generic, 1464 0x00000000); 1465 /* XXX : not implemented */ 1466 spr_register(env, SPR_405_IAC4, "IAC4", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_generic, 1469 0x00000000); 1470 /* Storage control */ 1471 /* XXX: TODO: not implemented */ 1472 spr_register(env, SPR_405_SLER, "SLER", 1473 SPR_NOACCESS, SPR_NOACCESS, 1474 &spr_read_generic, &spr_write_40x_sler, 1475 0x00000000); 1476 spr_register(env, SPR_40x_ZPR, "ZPR", 1477 SPR_NOACCESS, SPR_NOACCESS, 1478 &spr_read_generic, &spr_write_generic, 1479 0x00000000); 1480 /* XXX : not implemented */ 1481 spr_register(env, SPR_405_SU0R, "SU0R", 1482 SPR_NOACCESS, SPR_NOACCESS, 1483 &spr_read_generic, &spr_write_generic, 1484 0x00000000); 1485 /* SPRG */ 1486 spr_register(env, SPR_USPRG0, "USPRG0", 1487 &spr_read_ureg, SPR_NOACCESS, 1488 &spr_read_ureg, SPR_NOACCESS, 1489 0x00000000); 1490 spr_register(env, SPR_SPRG4, "SPRG4", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 spr_register(env, SPR_SPRG5, "SPRG5", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 spr_register(env, SPR_SPRG6, "SPRG6", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 spr_register(env, SPR_SPRG7, "SPRG7", 1503 SPR_NOACCESS, SPR_NOACCESS, 1504 spr_read_generic, &spr_write_generic, 1505 0x00000000); 1506 register_usprgh_sprs(env); 1507 } 1508 1509 1510 static void register_5xx_8xx_sprs(CPUPPCState *env) 1511 { 1512 /* Exception processing */ 1513 spr_register_kvm(env, SPR_DSISR, "DSISR", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 KVM_REG_PPC_DSISR, 0x00000000); 1517 spr_register_kvm(env, SPR_DAR, "DAR", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_generic, 1520 KVM_REG_PPC_DAR, 0x00000000); 1521 /* Timer */ 1522 spr_register(env, SPR_DECR, "DECR", 1523 SPR_NOACCESS, SPR_NOACCESS, 1524 &spr_read_decr, &spr_write_decr, 1525 0x00000000); 1526 /* XXX : not implemented */ 1527 spr_register(env, SPR_MPC_EIE, "EIE", 1528 SPR_NOACCESS, SPR_NOACCESS, 1529 &spr_read_generic, &spr_write_generic, 1530 0x00000000); 1531 /* XXX : not implemented */ 1532 spr_register(env, SPR_MPC_EID, "EID", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 /* XXX : not implemented */ 1537 spr_register(env, SPR_MPC_NRI, "NRI", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 /* XXX : not implemented */ 1542 spr_register(env, SPR_MPC_CMPA, "CMPA", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 /* XXX : not implemented */ 1547 spr_register(env, SPR_MPC_CMPB, "CMPB", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00000000); 1551 /* XXX : not implemented */ 1552 spr_register(env, SPR_MPC_CMPC, "CMPC", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 /* XXX : not implemented */ 1557 spr_register(env, SPR_MPC_CMPD, "CMPD", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 /* XXX : not implemented */ 1562 spr_register(env, SPR_MPC_ECR, "ECR", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 /* XXX : not implemented */ 1567 spr_register(env, SPR_MPC_DER, "DER", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 /* XXX : not implemented */ 1572 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 /* XXX : not implemented */ 1577 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 /* XXX : not implemented */ 1582 spr_register(env, SPR_MPC_CMPE, "CMPE", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 /* XXX : not implemented */ 1587 spr_register(env, SPR_MPC_CMPF, "CMPF", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 /* XXX : not implemented */ 1592 spr_register(env, SPR_MPC_CMPG, "CMPG", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 /* XXX : not implemented */ 1597 spr_register(env, SPR_MPC_CMPH, "CMPH", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 /* XXX : not implemented */ 1602 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 /* XXX : not implemented */ 1607 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 /* XXX : not implemented */ 1612 spr_register(env, SPR_MPC_BAR, "BAR", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 /* XXX : not implemented */ 1617 spr_register(env, SPR_MPC_DPDR, "DPDR", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 /* XXX : not implemented */ 1622 spr_register(env, SPR_MPC_IMMR, "IMMR", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 } 1627 1628 static void register_5xx_sprs(CPUPPCState *env) 1629 { 1630 /* XXX : not implemented */ 1631 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1632 SPR_NOACCESS, SPR_NOACCESS, 1633 &spr_read_generic, &spr_write_generic, 1634 0x00000000); 1635 /* XXX : not implemented */ 1636 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 &spr_read_generic, &spr_write_generic, 1639 0x00000000); 1640 /* XXX : not implemented */ 1641 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1642 SPR_NOACCESS, SPR_NOACCESS, 1643 &spr_read_generic, &spr_write_generic, 1644 0x00000000); 1645 /* XXX : not implemented */ 1646 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1647 SPR_NOACCESS, SPR_NOACCESS, 1648 &spr_read_generic, &spr_write_generic, 1649 0x00000000); 1650 /* XXX : not implemented */ 1651 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1652 SPR_NOACCESS, SPR_NOACCESS, 1653 &spr_read_generic, &spr_write_generic, 1654 0x00000000); 1655 /* XXX : not implemented */ 1656 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_generic, 1659 0x00000000); 1660 /* XXX : not implemented */ 1661 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1662 SPR_NOACCESS, SPR_NOACCESS, 1663 &spr_read_generic, &spr_write_generic, 1664 0x00000000); 1665 /* XXX : not implemented */ 1666 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1667 SPR_NOACCESS, SPR_NOACCESS, 1668 &spr_read_generic, &spr_write_generic, 1669 0x00000000); 1670 /* XXX : not implemented */ 1671 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 /* XXX : not implemented */ 1676 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_generic, 1679 0x00000000); 1680 /* XXX : not implemented */ 1681 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1682 SPR_NOACCESS, SPR_NOACCESS, 1683 &spr_read_generic, &spr_write_generic, 1684 0x00000000); 1685 /* XXX : not implemented */ 1686 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1687 SPR_NOACCESS, SPR_NOACCESS, 1688 &spr_read_generic, &spr_write_generic, 1689 0x00000000); 1690 /* XXX : not implemented */ 1691 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1692 SPR_NOACCESS, SPR_NOACCESS, 1693 &spr_read_generic, &spr_write_generic, 1694 0x00000000); 1695 /* XXX : not implemented */ 1696 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1697 SPR_NOACCESS, SPR_NOACCESS, 1698 &spr_read_generic, &spr_write_generic, 1699 0x00000000); 1700 /* XXX : not implemented */ 1701 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1702 SPR_NOACCESS, SPR_NOACCESS, 1703 &spr_read_generic, &spr_write_generic, 1704 0x00000000); 1705 /* XXX : not implemented */ 1706 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1707 SPR_NOACCESS, SPR_NOACCESS, 1708 &spr_read_generic, &spr_write_generic, 1709 0x00000000); 1710 /* XXX : not implemented */ 1711 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1712 SPR_NOACCESS, SPR_NOACCESS, 1713 &spr_read_generic, &spr_write_generic, 1714 0x00000000); 1715 /* XXX : not implemented */ 1716 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_generic, &spr_write_generic, 1719 0x00000000); 1720 /* XXX : not implemented */ 1721 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1722 SPR_NOACCESS, SPR_NOACCESS, 1723 &spr_read_generic, &spr_write_generic, 1724 0x00000000); 1725 /* XXX : not implemented */ 1726 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 /* XXX : not implemented */ 1731 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1732 SPR_NOACCESS, SPR_NOACCESS, 1733 &spr_read_generic, &spr_write_generic, 1734 0x00000000); 1735 } 1736 1737 static void register_8xx_sprs(CPUPPCState *env) 1738 { 1739 /* XXX : not implemented */ 1740 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1741 SPR_NOACCESS, SPR_NOACCESS, 1742 &spr_read_generic, &spr_write_generic, 1743 0x00000000); 1744 /* XXX : not implemented */ 1745 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1746 SPR_NOACCESS, SPR_NOACCESS, 1747 &spr_read_generic, &spr_write_generic, 1748 0x00000000); 1749 /* XXX : not implemented */ 1750 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1751 SPR_NOACCESS, SPR_NOACCESS, 1752 &spr_read_generic, &spr_write_generic, 1753 0x00000000); 1754 /* XXX : not implemented */ 1755 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1756 SPR_NOACCESS, SPR_NOACCESS, 1757 &spr_read_generic, &spr_write_generic, 1758 0x00000000); 1759 /* XXX : not implemented */ 1760 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1761 SPR_NOACCESS, SPR_NOACCESS, 1762 &spr_read_generic, &spr_write_generic, 1763 0x00000000); 1764 /* XXX : not implemented */ 1765 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1766 SPR_NOACCESS, SPR_NOACCESS, 1767 &spr_read_generic, &spr_write_generic, 1768 0x00000000); 1769 /* XXX : not implemented */ 1770 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1771 SPR_NOACCESS, SPR_NOACCESS, 1772 &spr_read_generic, &spr_write_generic, 1773 0x00000000); 1774 /* XXX : not implemented */ 1775 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1776 SPR_NOACCESS, SPR_NOACCESS, 1777 &spr_read_generic, &spr_write_generic, 1778 0x00000000); 1779 /* XXX : not implemented */ 1780 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1781 SPR_NOACCESS, SPR_NOACCESS, 1782 &spr_read_generic, &spr_write_generic, 1783 0x00000000); 1784 /* XXX : not implemented */ 1785 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1786 SPR_NOACCESS, SPR_NOACCESS, 1787 &spr_read_generic, &spr_write_generic, 1788 0x00000000); 1789 /* XXX : not implemented */ 1790 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1791 SPR_NOACCESS, SPR_NOACCESS, 1792 &spr_read_generic, &spr_write_generic, 1793 0x00000000); 1794 /* XXX : not implemented */ 1795 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1796 SPR_NOACCESS, SPR_NOACCESS, 1797 &spr_read_generic, &spr_write_generic, 1798 0x00000000); 1799 /* XXX : not implemented */ 1800 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1801 SPR_NOACCESS, SPR_NOACCESS, 1802 &spr_read_generic, &spr_write_generic, 1803 0x00000000); 1804 /* XXX : not implemented */ 1805 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1806 SPR_NOACCESS, SPR_NOACCESS, 1807 &spr_read_generic, &spr_write_generic, 1808 0x00000000); 1809 /* XXX : not implemented */ 1810 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1811 SPR_NOACCESS, SPR_NOACCESS, 1812 &spr_read_generic, &spr_write_generic, 1813 0x00000000); 1814 /* XXX : not implemented */ 1815 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1816 SPR_NOACCESS, SPR_NOACCESS, 1817 &spr_read_generic, &spr_write_generic, 1818 0x00000000); 1819 /* XXX : not implemented */ 1820 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1821 SPR_NOACCESS, SPR_NOACCESS, 1822 &spr_read_generic, &spr_write_generic, 1823 0x00000000); 1824 /* XXX : not implemented */ 1825 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1826 SPR_NOACCESS, SPR_NOACCESS, 1827 &spr_read_generic, &spr_write_generic, 1828 0x00000000); 1829 /* XXX : not implemented */ 1830 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1831 SPR_NOACCESS, SPR_NOACCESS, 1832 &spr_read_generic, &spr_write_generic, 1833 0x00000000); 1834 /* XXX : not implemented */ 1835 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1836 SPR_NOACCESS, SPR_NOACCESS, 1837 &spr_read_generic, &spr_write_generic, 1838 0x00000000); 1839 /* XXX : not implemented */ 1840 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1841 SPR_NOACCESS, SPR_NOACCESS, 1842 &spr_read_generic, &spr_write_generic, 1843 0x00000000); 1844 /* XXX : not implemented */ 1845 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1846 SPR_NOACCESS, SPR_NOACCESS, 1847 &spr_read_generic, &spr_write_generic, 1848 0x00000000); 1849 /* XXX : not implemented */ 1850 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1851 SPR_NOACCESS, SPR_NOACCESS, 1852 &spr_read_generic, &spr_write_generic, 1853 0x00000000); 1854 /* XXX : not implemented */ 1855 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1856 SPR_NOACCESS, SPR_NOACCESS, 1857 &spr_read_generic, &spr_write_generic, 1858 0x00000000); 1859 /* XXX : not implemented */ 1860 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1861 SPR_NOACCESS, SPR_NOACCESS, 1862 &spr_read_generic, &spr_write_generic, 1863 0x00000000); 1864 } 1865 1866 /* 1867 * AMR => SPR 29 (Power 2.04) 1868 * CTRL => SPR 136 (Power 2.04) 1869 * CTRL => SPR 152 (Power 2.04) 1870 * SCOMC => SPR 276 (64 bits ?) 1871 * SCOMD => SPR 277 (64 bits ?) 1872 * TBU40 => SPR 286 (Power 2.04 hypv) 1873 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1874 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1875 * HDSISR => SPR 306 (Power 2.04 hypv) 1876 * HDAR => SPR 307 (Power 2.04 hypv) 1877 * PURR => SPR 309 (Power 2.04 hypv) 1878 * HDEC => SPR 310 (Power 2.04 hypv) 1879 * HIOR => SPR 311 (hypv) 1880 * RMOR => SPR 312 (970) 1881 * HRMOR => SPR 313 (Power 2.04 hypv) 1882 * HSRR0 => SPR 314 (Power 2.04 hypv) 1883 * HSRR1 => SPR 315 (Power 2.04 hypv) 1884 * LPIDR => SPR 317 (970) 1885 * EPR => SPR 702 (Power 2.04 emb) 1886 * perf => 768-783 (Power 2.04) 1887 * perf => 784-799 (Power 2.04) 1888 * PPR => SPR 896 (Power 2.04) 1889 * DABRX => 1015 (Power 2.04 hypv) 1890 * FPECR => SPR 1022 (?) 1891 * ... and more (thermal management, performance counters, ...) 1892 */ 1893 1894 /*****************************************************************************/ 1895 /* Exception vectors models */ 1896 static void init_excp_4xx_softmmu(CPUPPCState *env) 1897 { 1898 #if !defined(CONFIG_USER_ONLY) 1899 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1900 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1901 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1902 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1903 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1904 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1905 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1906 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1907 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1908 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1909 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1910 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1911 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1912 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1913 env->ivor_mask = 0x0000FFF0UL; 1914 env->ivpr_mask = 0xFFFF0000UL; 1915 /* Hardware reset vector */ 1916 env->hreset_vector = 0xFFFFFFFCUL; 1917 #endif 1918 } 1919 1920 static void init_excp_MPC5xx(CPUPPCState *env) 1921 { 1922 #if !defined(CONFIG_USER_ONLY) 1923 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1924 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1925 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1926 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1927 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1928 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1929 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1930 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1931 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1932 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1933 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1934 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1935 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1936 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1937 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1938 env->ivor_mask = 0x0000FFF0UL; 1939 env->ivpr_mask = 0xFFFF0000UL; 1940 /* Hardware reset vector */ 1941 env->hreset_vector = 0x00000100UL; 1942 #endif 1943 } 1944 1945 static void init_excp_MPC8xx(CPUPPCState *env) 1946 { 1947 #if !defined(CONFIG_USER_ONLY) 1948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1959 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1960 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1961 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1962 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1963 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1964 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1965 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1967 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1968 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1969 env->ivor_mask = 0x0000FFF0UL; 1970 env->ivpr_mask = 0xFFFF0000UL; 1971 /* Hardware reset vector */ 1972 env->hreset_vector = 0x00000100UL; 1973 #endif 1974 } 1975 1976 static void init_excp_G2(CPUPPCState *env) 1977 { 1978 #if !defined(CONFIG_USER_ONLY) 1979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1988 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1991 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1992 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1993 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1994 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1995 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1996 /* Hardware reset vector */ 1997 env->hreset_vector = 0x00000100UL; 1998 #endif 1999 } 2000 2001 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2002 { 2003 #if !defined(CONFIG_USER_ONLY) 2004 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2005 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2008 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2009 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2010 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2011 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2012 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2013 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2014 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2016 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2017 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2018 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2019 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2020 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2021 /* 2022 * These two are the same IVOR as POWERPC_EXCP_VPU and 2023 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2024 * powerpc_excp(). 2025 */ 2026 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2027 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2028 2029 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2030 env->ivor_mask = 0x0000FFF7UL; 2031 env->ivpr_mask = ivpr_mask; 2032 /* Hardware reset vector */ 2033 env->hreset_vector = 0xFFFFFFFCUL; 2034 #endif 2035 } 2036 2037 static void init_excp_BookE(CPUPPCState *env) 2038 { 2039 #if !defined(CONFIG_USER_ONLY) 2040 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2041 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2042 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2043 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2044 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2045 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2046 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2047 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2049 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2050 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2051 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2052 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2053 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2054 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2055 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2056 env->ivor_mask = 0x0000FFF0UL; 2057 env->ivpr_mask = 0xFFFF0000UL; 2058 /* Hardware reset vector */ 2059 env->hreset_vector = 0xFFFFFFFCUL; 2060 #endif 2061 } 2062 2063 static void init_excp_601(CPUPPCState *env) 2064 { 2065 #if !defined(CONFIG_USER_ONLY) 2066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2069 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2075 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2077 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2078 /* Hardware reset vector */ 2079 env->hreset_vector = 0x00000100UL; 2080 #endif 2081 } 2082 2083 static void init_excp_603(CPUPPCState *env) 2084 { 2085 #if !defined(CONFIG_USER_ONLY) 2086 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2087 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2088 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2089 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2090 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2091 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2092 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2093 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2094 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2095 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2096 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2097 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2098 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2099 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2102 /* Hardware reset vector */ 2103 env->hreset_vector = 0x00000100UL; 2104 #endif 2105 } 2106 2107 static void init_excp_604(CPUPPCState *env) 2108 { 2109 #if !defined(CONFIG_USER_ONLY) 2110 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2111 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2112 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2113 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2114 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2115 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2116 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2117 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2118 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2119 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2120 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2121 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2122 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2123 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2124 /* Hardware reset vector */ 2125 env->hreset_vector = 0x00000100UL; 2126 #endif 2127 } 2128 2129 static void init_excp_7x0(CPUPPCState *env) 2130 { 2131 #if !defined(CONFIG_USER_ONLY) 2132 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2133 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2134 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2135 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2136 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2137 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2138 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2139 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2140 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2141 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2142 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2143 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2144 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2145 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2146 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2147 /* Hardware reset vector */ 2148 env->hreset_vector = 0x00000100UL; 2149 #endif 2150 } 2151 2152 static void init_excp_750cl(CPUPPCState *env) 2153 { 2154 #if !defined(CONFIG_USER_ONLY) 2155 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2158 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2163 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2164 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2165 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2166 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2167 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2168 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2169 /* Hardware reset vector */ 2170 env->hreset_vector = 0x00000100UL; 2171 #endif 2172 } 2173 2174 static void init_excp_750cx(CPUPPCState *env) 2175 { 2176 #if !defined(CONFIG_USER_ONLY) 2177 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2178 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2179 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2180 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2181 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2182 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2183 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2184 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2185 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2186 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2187 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2188 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2189 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2191 /* Hardware reset vector */ 2192 env->hreset_vector = 0x00000100UL; 2193 #endif 2194 } 2195 2196 /* XXX: Check if this is correct */ 2197 static void init_excp_7x5(CPUPPCState *env) 2198 { 2199 #if !defined(CONFIG_USER_ONLY) 2200 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2201 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2202 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2203 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2204 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2205 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2206 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2207 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2208 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2212 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2213 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2214 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2215 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2216 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2217 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2218 /* Hardware reset vector */ 2219 env->hreset_vector = 0x00000100UL; 2220 #endif 2221 } 2222 2223 static void init_excp_7400(CPUPPCState *env) 2224 { 2225 #if !defined(CONFIG_USER_ONLY) 2226 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2227 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2228 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2229 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2230 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2231 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2232 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2233 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2234 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2235 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2236 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2237 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2238 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2239 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2240 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2241 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2242 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2243 /* Hardware reset vector */ 2244 env->hreset_vector = 0x00000100UL; 2245 #endif 2246 } 2247 2248 static void init_excp_7450(CPUPPCState *env) 2249 { 2250 #if !defined(CONFIG_USER_ONLY) 2251 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2252 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2253 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2254 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2255 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2256 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2257 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2258 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2259 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2260 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2261 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2262 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2263 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2264 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2265 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2266 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2267 /* Hardware reset vector */ 2268 env->hreset_vector = 0x00000100UL; 2269 #endif 2270 } 2271 2272 #if defined(TARGET_PPC64) 2273 static void init_excp_970(CPUPPCState *env) 2274 { 2275 #if !defined(CONFIG_USER_ONLY) 2276 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2277 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2278 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2279 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2280 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2281 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2282 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2283 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2284 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2285 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2286 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2287 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2288 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2289 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2290 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2291 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2292 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2293 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2294 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2295 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2296 /* Hardware reset vector */ 2297 env->hreset_vector = 0x0000000000000100ULL; 2298 #endif 2299 } 2300 2301 static void init_excp_POWER7(CPUPPCState *env) 2302 { 2303 #if !defined(CONFIG_USER_ONLY) 2304 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2305 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2306 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2307 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2308 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2309 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2310 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2311 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2312 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2313 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2314 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2315 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2316 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2317 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2318 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2319 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2320 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2321 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2322 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2323 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2324 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2325 /* Hardware reset vector */ 2326 env->hreset_vector = 0x0000000000000100ULL; 2327 #endif 2328 } 2329 2330 static void init_excp_POWER8(CPUPPCState *env) 2331 { 2332 init_excp_POWER7(env); 2333 2334 #if !defined(CONFIG_USER_ONLY) 2335 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2336 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2337 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2338 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2339 #endif 2340 } 2341 2342 static void init_excp_POWER9(CPUPPCState *env) 2343 { 2344 init_excp_POWER8(env); 2345 2346 #if !defined(CONFIG_USER_ONLY) 2347 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2348 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2349 #endif 2350 } 2351 2352 static void init_excp_POWER10(CPUPPCState *env) 2353 { 2354 init_excp_POWER9(env); 2355 } 2356 2357 #endif 2358 2359 /*****************************************************************************/ 2360 /* Power management enable checks */ 2361 static int check_pow_none(CPUPPCState *env) 2362 { 2363 return 0; 2364 } 2365 2366 static int check_pow_nocheck(CPUPPCState *env) 2367 { 2368 return 1; 2369 } 2370 2371 static int check_pow_hid0(CPUPPCState *env) 2372 { 2373 if (env->spr[SPR_HID0] & 0x00E00000) { 2374 return 1; 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int check_pow_hid0_74xx(CPUPPCState *env) 2381 { 2382 if (env->spr[SPR_HID0] & 0x00600000) { 2383 return 1; 2384 } 2385 2386 return 0; 2387 } 2388 2389 /*****************************************************************************/ 2390 /* PowerPC implementations definitions */ 2391 2392 #define POWERPC_FAMILY(_name) \ 2393 static void \ 2394 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2395 \ 2396 static const TypeInfo \ 2397 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2398 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2399 .parent = TYPE_POWERPC_CPU, \ 2400 .abstract = true, \ 2401 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2402 }; \ 2403 \ 2404 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2405 { \ 2406 type_register_static( \ 2407 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2408 } \ 2409 \ 2410 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2411 \ 2412 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2413 2414 static void init_proc_405(CPUPPCState *env) 2415 { 2416 /* Time base */ 2417 register_tbl(env); 2418 register_40x_sprs(env); 2419 register_405_sprs(env); 2420 /* Bus access control */ 2421 /* not emulated, as QEMU never does speculative access */ 2422 spr_register(env, SPR_40x_SGR, "SGR", 2423 SPR_NOACCESS, SPR_NOACCESS, 2424 &spr_read_generic, &spr_write_generic, 2425 0xFFFFFFFF); 2426 /* not emulated, as QEMU do not emulate caches */ 2427 spr_register(env, SPR_40x_DCWR, "DCWR", 2428 SPR_NOACCESS, SPR_NOACCESS, 2429 &spr_read_generic, &spr_write_generic, 2430 0x00000000); 2431 /* Memory management */ 2432 #if !defined(CONFIG_USER_ONLY) 2433 env->nb_tlb = 64; 2434 env->nb_ways = 1; 2435 env->id_tlbs = 0; 2436 env->tlb_type = TLB_EMB; 2437 #endif 2438 init_excp_4xx_softmmu(env); 2439 env->dcache_line_size = 32; 2440 env->icache_line_size = 32; 2441 /* Allocate hardware IRQ controller */ 2442 ppc40x_irq_init(env_archcpu(env)); 2443 2444 SET_FIT_PERIOD(8, 12, 16, 20); 2445 SET_WDT_PERIOD(16, 20, 24, 28); 2446 } 2447 2448 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2449 { 2450 DeviceClass *dc = DEVICE_CLASS(oc); 2451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2452 2453 dc->desc = "PowerPC 405"; 2454 pcc->init_proc = init_proc_405; 2455 pcc->check_pow = check_pow_nocheck; 2456 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2457 PPC_DCR | PPC_WRTEE | 2458 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2459 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2460 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2461 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2462 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2463 pcc->msr_mask = (1ull << MSR_WE) | 2464 (1ull << MSR_CE) | 2465 (1ull << MSR_EE) | 2466 (1ull << MSR_PR) | 2467 (1ull << MSR_FP) | 2468 (1ull << MSR_ME) | 2469 (1ull << MSR_DWE) | 2470 (1ull << MSR_DE) | 2471 (1ull << MSR_IR) | 2472 (1ull << MSR_DR); 2473 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2474 pcc->excp_model = POWERPC_EXCP_40x; 2475 pcc->bus_model = PPC_FLAGS_INPUT_405; 2476 pcc->bfd_mach = bfd_mach_ppc_403; 2477 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2478 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2479 } 2480 2481 static void init_proc_440EP(CPUPPCState *env) 2482 { 2483 /* Time base */ 2484 register_tbl(env); 2485 register_BookE_sprs(env, 0x000000000000FFFFULL); 2486 register_440_sprs(env); 2487 register_usprgh_sprs(env); 2488 /* Processor identification */ 2489 spr_register(env, SPR_BOOKE_PIR, "PIR", 2490 SPR_NOACCESS, SPR_NOACCESS, 2491 &spr_read_generic, &spr_write_pir, 2492 0x00000000); 2493 /* XXX : not implemented */ 2494 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2495 SPR_NOACCESS, SPR_NOACCESS, 2496 &spr_read_generic, &spr_write_generic, 2497 0x00000000); 2498 /* XXX : not implemented */ 2499 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2500 SPR_NOACCESS, SPR_NOACCESS, 2501 &spr_read_generic, &spr_write_generic, 2502 0x00000000); 2503 /* XXX : not implemented */ 2504 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2505 SPR_NOACCESS, SPR_NOACCESS, 2506 &spr_read_generic, &spr_write_generic, 2507 0x00000000); 2508 /* XXX : not implemented */ 2509 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2510 SPR_NOACCESS, SPR_NOACCESS, 2511 &spr_read_generic, &spr_write_generic, 2512 0x00000000); 2513 /* XXX : not implemented */ 2514 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2515 SPR_NOACCESS, SPR_NOACCESS, 2516 &spr_read_generic, &spr_write_generic, 2517 0x00000000); 2518 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2519 SPR_NOACCESS, SPR_NOACCESS, 2520 &spr_read_generic, &spr_write_generic, 2521 0x00000000); 2522 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2523 SPR_NOACCESS, SPR_NOACCESS, 2524 &spr_read_generic, &spr_write_generic, 2525 0x00000000); 2526 /* XXX : not implemented */ 2527 spr_register(env, SPR_440_CCR1, "CCR1", 2528 SPR_NOACCESS, SPR_NOACCESS, 2529 &spr_read_generic, &spr_write_generic, 2530 0x00000000); 2531 /* Memory management */ 2532 #if !defined(CONFIG_USER_ONLY) 2533 env->nb_tlb = 64; 2534 env->nb_ways = 1; 2535 env->id_tlbs = 0; 2536 env->tlb_type = TLB_EMB; 2537 #endif 2538 init_excp_BookE(env); 2539 env->dcache_line_size = 32; 2540 env->icache_line_size = 32; 2541 ppc40x_irq_init(env_archcpu(env)); 2542 2543 SET_FIT_PERIOD(12, 16, 20, 24); 2544 SET_WDT_PERIOD(20, 24, 28, 32); 2545 } 2546 2547 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2548 { 2549 DeviceClass *dc = DEVICE_CLASS(oc); 2550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2551 2552 dc->desc = "PowerPC 440 EP"; 2553 pcc->init_proc = init_proc_440EP; 2554 pcc->check_pow = check_pow_nocheck; 2555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2556 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2557 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2558 PPC_FLOAT_STFIWX | 2559 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2560 PPC_CACHE | PPC_CACHE_ICBI | 2561 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2562 PPC_MEM_TLBSYNC | PPC_MFTB | 2563 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2564 PPC_440_SPEC; 2565 pcc->msr_mask = (1ull << MSR_POW) | 2566 (1ull << MSR_CE) | 2567 (1ull << MSR_EE) | 2568 (1ull << MSR_PR) | 2569 (1ull << MSR_FP) | 2570 (1ull << MSR_ME) | 2571 (1ull << MSR_FE0) | 2572 (1ull << MSR_DWE) | 2573 (1ull << MSR_DE) | 2574 (1ull << MSR_FE1) | 2575 (1ull << MSR_IR) | 2576 (1ull << MSR_DR); 2577 pcc->mmu_model = POWERPC_MMU_BOOKE; 2578 pcc->excp_model = POWERPC_EXCP_BOOKE; 2579 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2580 pcc->bfd_mach = bfd_mach_ppc_403; 2581 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2582 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2583 } 2584 2585 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2586 { 2587 DeviceClass *dc = DEVICE_CLASS(oc); 2588 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2589 2590 dc->desc = "PowerPC 460 EX"; 2591 pcc->init_proc = init_proc_440EP; 2592 pcc->check_pow = check_pow_nocheck; 2593 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2594 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2595 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2596 PPC_FLOAT_STFIWX | 2597 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2598 PPC_CACHE | PPC_CACHE_ICBI | 2599 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2600 PPC_MEM_TLBSYNC | PPC_MFTB | 2601 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2602 PPC_440_SPEC; 2603 pcc->msr_mask = (1ull << MSR_POW) | 2604 (1ull << MSR_CE) | 2605 (1ull << MSR_EE) | 2606 (1ull << MSR_PR) | 2607 (1ull << MSR_FP) | 2608 (1ull << MSR_ME) | 2609 (1ull << MSR_FE0) | 2610 (1ull << MSR_DWE) | 2611 (1ull << MSR_DE) | 2612 (1ull << MSR_FE1) | 2613 (1ull << MSR_IR) | 2614 (1ull << MSR_DR); 2615 pcc->mmu_model = POWERPC_MMU_BOOKE; 2616 pcc->excp_model = POWERPC_EXCP_BOOKE; 2617 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2618 pcc->bfd_mach = bfd_mach_ppc_403; 2619 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2621 } 2622 2623 static void init_proc_440GP(CPUPPCState *env) 2624 { 2625 /* Time base */ 2626 register_tbl(env); 2627 register_BookE_sprs(env, 0x000000000000FFFFULL); 2628 register_440_sprs(env); 2629 register_usprgh_sprs(env); 2630 /* Processor identification */ 2631 spr_register(env, SPR_BOOKE_PIR, "PIR", 2632 SPR_NOACCESS, SPR_NOACCESS, 2633 &spr_read_generic, &spr_write_pir, 2634 0x00000000); 2635 /* XXX : not implemented */ 2636 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2637 SPR_NOACCESS, SPR_NOACCESS, 2638 &spr_read_generic, &spr_write_generic, 2639 0x00000000); 2640 /* XXX : not implemented */ 2641 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2642 SPR_NOACCESS, SPR_NOACCESS, 2643 &spr_read_generic, &spr_write_generic, 2644 0x00000000); 2645 /* XXX : not implemented */ 2646 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2647 SPR_NOACCESS, SPR_NOACCESS, 2648 &spr_read_generic, &spr_write_generic, 2649 0x00000000); 2650 /* XXX : not implemented */ 2651 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2652 SPR_NOACCESS, SPR_NOACCESS, 2653 &spr_read_generic, &spr_write_generic, 2654 0x00000000); 2655 /* Memory management */ 2656 #if !defined(CONFIG_USER_ONLY) 2657 env->nb_tlb = 64; 2658 env->nb_ways = 1; 2659 env->id_tlbs = 0; 2660 env->tlb_type = TLB_EMB; 2661 #endif 2662 init_excp_BookE(env); 2663 env->dcache_line_size = 32; 2664 env->icache_line_size = 32; 2665 /* XXX: TODO: allocate internal IRQ controller */ 2666 2667 SET_FIT_PERIOD(12, 16, 20, 24); 2668 SET_WDT_PERIOD(20, 24, 28, 32); 2669 } 2670 2671 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2672 { 2673 DeviceClass *dc = DEVICE_CLASS(oc); 2674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2675 2676 dc->desc = "PowerPC 440 GP"; 2677 pcc->init_proc = init_proc_440GP; 2678 pcc->check_pow = check_pow_nocheck; 2679 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2680 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2681 PPC_CACHE | PPC_CACHE_ICBI | 2682 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2683 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2684 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2685 PPC_440_SPEC; 2686 pcc->msr_mask = (1ull << MSR_POW) | 2687 (1ull << MSR_CE) | 2688 (1ull << MSR_EE) | 2689 (1ull << MSR_PR) | 2690 (1ull << MSR_FP) | 2691 (1ull << MSR_ME) | 2692 (1ull << MSR_FE0) | 2693 (1ull << MSR_DWE) | 2694 (1ull << MSR_DE) | 2695 (1ull << MSR_FE1) | 2696 (1ull << MSR_IR) | 2697 (1ull << MSR_DR); 2698 pcc->mmu_model = POWERPC_MMU_BOOKE; 2699 pcc->excp_model = POWERPC_EXCP_BOOKE; 2700 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2701 pcc->bfd_mach = bfd_mach_ppc_403; 2702 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2703 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2704 } 2705 2706 static void init_proc_440x4(CPUPPCState *env) 2707 { 2708 /* Time base */ 2709 register_tbl(env); 2710 register_BookE_sprs(env, 0x000000000000FFFFULL); 2711 register_440_sprs(env); 2712 register_usprgh_sprs(env); 2713 /* Processor identification */ 2714 spr_register(env, SPR_BOOKE_PIR, "PIR", 2715 SPR_NOACCESS, SPR_NOACCESS, 2716 &spr_read_generic, &spr_write_pir, 2717 0x00000000); 2718 /* XXX : not implemented */ 2719 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2720 SPR_NOACCESS, SPR_NOACCESS, 2721 &spr_read_generic, &spr_write_generic, 2722 0x00000000); 2723 /* XXX : not implemented */ 2724 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2725 SPR_NOACCESS, SPR_NOACCESS, 2726 &spr_read_generic, &spr_write_generic, 2727 0x00000000); 2728 /* XXX : not implemented */ 2729 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2730 SPR_NOACCESS, SPR_NOACCESS, 2731 &spr_read_generic, &spr_write_generic, 2732 0x00000000); 2733 /* XXX : not implemented */ 2734 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2735 SPR_NOACCESS, SPR_NOACCESS, 2736 &spr_read_generic, &spr_write_generic, 2737 0x00000000); 2738 /* Memory management */ 2739 #if !defined(CONFIG_USER_ONLY) 2740 env->nb_tlb = 64; 2741 env->nb_ways = 1; 2742 env->id_tlbs = 0; 2743 env->tlb_type = TLB_EMB; 2744 #endif 2745 init_excp_BookE(env); 2746 env->dcache_line_size = 32; 2747 env->icache_line_size = 32; 2748 /* XXX: TODO: allocate internal IRQ controller */ 2749 2750 SET_FIT_PERIOD(12, 16, 20, 24); 2751 SET_WDT_PERIOD(20, 24, 28, 32); 2752 } 2753 2754 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 2755 { 2756 DeviceClass *dc = DEVICE_CLASS(oc); 2757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2758 2759 dc->desc = "PowerPC 440x4"; 2760 pcc->init_proc = init_proc_440x4; 2761 pcc->check_pow = check_pow_nocheck; 2762 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2763 PPC_DCR | PPC_WRTEE | 2764 PPC_CACHE | PPC_CACHE_ICBI | 2765 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2766 PPC_MEM_TLBSYNC | PPC_MFTB | 2767 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2768 PPC_440_SPEC; 2769 pcc->msr_mask = (1ull << MSR_POW) | 2770 (1ull << MSR_CE) | 2771 (1ull << MSR_EE) | 2772 (1ull << MSR_PR) | 2773 (1ull << MSR_FP) | 2774 (1ull << MSR_ME) | 2775 (1ull << MSR_FE0) | 2776 (1ull << MSR_DWE) | 2777 (1ull << MSR_DE) | 2778 (1ull << MSR_FE1) | 2779 (1ull << MSR_IR) | 2780 (1ull << MSR_DR); 2781 pcc->mmu_model = POWERPC_MMU_BOOKE; 2782 pcc->excp_model = POWERPC_EXCP_BOOKE; 2783 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2784 pcc->bfd_mach = bfd_mach_ppc_403; 2785 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2786 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2787 } 2788 2789 static void init_proc_440x5(CPUPPCState *env) 2790 { 2791 /* Time base */ 2792 register_tbl(env); 2793 register_BookE_sprs(env, 0x000000000000FFFFULL); 2794 register_440_sprs(env); 2795 register_usprgh_sprs(env); 2796 /* Processor identification */ 2797 spr_register(env, SPR_BOOKE_PIR, "PIR", 2798 SPR_NOACCESS, SPR_NOACCESS, 2799 &spr_read_generic, &spr_write_pir, 2800 0x00000000); 2801 /* XXX : not implemented */ 2802 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2803 SPR_NOACCESS, SPR_NOACCESS, 2804 &spr_read_generic, &spr_write_generic, 2805 0x00000000); 2806 /* XXX : not implemented */ 2807 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2808 SPR_NOACCESS, SPR_NOACCESS, 2809 &spr_read_generic, &spr_write_generic, 2810 0x00000000); 2811 /* XXX : not implemented */ 2812 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2813 SPR_NOACCESS, SPR_NOACCESS, 2814 &spr_read_generic, &spr_write_generic, 2815 0x00000000); 2816 /* XXX : not implemented */ 2817 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2818 SPR_NOACCESS, SPR_NOACCESS, 2819 &spr_read_generic, &spr_write_generic, 2820 0x00000000); 2821 /* XXX : not implemented */ 2822 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2823 SPR_NOACCESS, SPR_NOACCESS, 2824 &spr_read_generic, &spr_write_generic, 2825 0x00000000); 2826 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2827 SPR_NOACCESS, SPR_NOACCESS, 2828 &spr_read_generic, &spr_write_generic, 2829 0x00000000); 2830 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2831 SPR_NOACCESS, SPR_NOACCESS, 2832 &spr_read_generic, &spr_write_generic, 2833 0x00000000); 2834 /* XXX : not implemented */ 2835 spr_register(env, SPR_440_CCR1, "CCR1", 2836 SPR_NOACCESS, SPR_NOACCESS, 2837 &spr_read_generic, &spr_write_generic, 2838 0x00000000); 2839 /* Memory management */ 2840 #if !defined(CONFIG_USER_ONLY) 2841 env->nb_tlb = 64; 2842 env->nb_ways = 1; 2843 env->id_tlbs = 0; 2844 env->tlb_type = TLB_EMB; 2845 #endif 2846 init_excp_BookE(env); 2847 env->dcache_line_size = 32; 2848 env->icache_line_size = 32; 2849 ppc40x_irq_init(env_archcpu(env)); 2850 2851 SET_FIT_PERIOD(12, 16, 20, 24); 2852 SET_WDT_PERIOD(20, 24, 28, 32); 2853 } 2854 2855 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2856 { 2857 DeviceClass *dc = DEVICE_CLASS(oc); 2858 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2859 2860 dc->desc = "PowerPC 440x5"; 2861 pcc->init_proc = init_proc_440x5; 2862 pcc->check_pow = check_pow_nocheck; 2863 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2864 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2865 PPC_CACHE | PPC_CACHE_ICBI | 2866 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2867 PPC_MEM_TLBSYNC | PPC_MFTB | 2868 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2869 PPC_440_SPEC; 2870 pcc->msr_mask = (1ull << MSR_POW) | 2871 (1ull << MSR_CE) | 2872 (1ull << MSR_EE) | 2873 (1ull << MSR_PR) | 2874 (1ull << MSR_FP) | 2875 (1ull << MSR_ME) | 2876 (1ull << MSR_FE0) | 2877 (1ull << MSR_DWE) | 2878 (1ull << MSR_DE) | 2879 (1ull << MSR_FE1) | 2880 (1ull << MSR_IR) | 2881 (1ull << MSR_DR); 2882 pcc->mmu_model = POWERPC_MMU_BOOKE; 2883 pcc->excp_model = POWERPC_EXCP_BOOKE; 2884 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2885 pcc->bfd_mach = bfd_mach_ppc_403; 2886 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2887 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2888 } 2889 2890 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2891 { 2892 DeviceClass *dc = DEVICE_CLASS(oc); 2893 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2894 2895 dc->desc = "PowerPC 440x5 with double precision FPU"; 2896 pcc->init_proc = init_proc_440x5; 2897 pcc->check_pow = check_pow_nocheck; 2898 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2899 PPC_FLOAT | PPC_FLOAT_FSQRT | 2900 PPC_FLOAT_STFIWX | 2901 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2902 PPC_CACHE | PPC_CACHE_ICBI | 2903 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2904 PPC_MEM_TLBSYNC | PPC_MFTB | 2905 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2906 PPC_440_SPEC; 2907 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2908 pcc->msr_mask = (1ull << MSR_POW) | 2909 (1ull << MSR_CE) | 2910 (1ull << MSR_EE) | 2911 (1ull << MSR_PR) | 2912 (1ull << MSR_FP) | 2913 (1ull << MSR_ME) | 2914 (1ull << MSR_FE0) | 2915 (1ull << MSR_DWE) | 2916 (1ull << MSR_DE) | 2917 (1ull << MSR_FE1) | 2918 (1ull << MSR_IR) | 2919 (1ull << MSR_DR); 2920 pcc->mmu_model = POWERPC_MMU_BOOKE; 2921 pcc->excp_model = POWERPC_EXCP_BOOKE; 2922 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2923 pcc->bfd_mach = bfd_mach_ppc_403; 2924 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2925 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2926 } 2927 2928 static void init_proc_MPC5xx(CPUPPCState *env) 2929 { 2930 /* Time base */ 2931 register_tbl(env); 2932 register_5xx_8xx_sprs(env); 2933 register_5xx_sprs(env); 2934 init_excp_MPC5xx(env); 2935 env->dcache_line_size = 32; 2936 env->icache_line_size = 32; 2937 /* XXX: TODO: allocate internal IRQ controller */ 2938 } 2939 2940 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2941 { 2942 DeviceClass *dc = DEVICE_CLASS(oc); 2943 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2944 2945 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2946 pcc->init_proc = init_proc_MPC5xx; 2947 pcc->check_pow = check_pow_none; 2948 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2949 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2950 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2951 PPC_MFTB; 2952 pcc->msr_mask = (1ull << MSR_ILE) | 2953 (1ull << MSR_EE) | 2954 (1ull << MSR_PR) | 2955 (1ull << MSR_FP) | 2956 (1ull << MSR_ME) | 2957 (1ull << MSR_FE0) | 2958 (1ull << MSR_SE) | 2959 (1ull << MSR_DE) | 2960 (1ull << MSR_FE1) | 2961 (1ull << MSR_EP) | 2962 (1ull << MSR_RI) | 2963 (1ull << MSR_LE); 2964 pcc->mmu_model = POWERPC_MMU_REAL; 2965 pcc->excp_model = POWERPC_EXCP_603; 2966 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2967 pcc->bfd_mach = bfd_mach_ppc_505; 2968 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2969 POWERPC_FLAG_BUS_CLK; 2970 } 2971 2972 static void init_proc_MPC8xx(CPUPPCState *env) 2973 { 2974 /* Time base */ 2975 register_tbl(env); 2976 register_5xx_8xx_sprs(env); 2977 register_8xx_sprs(env); 2978 init_excp_MPC8xx(env); 2979 env->dcache_line_size = 32; 2980 env->icache_line_size = 32; 2981 /* XXX: TODO: allocate internal IRQ controller */ 2982 } 2983 2984 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2985 { 2986 DeviceClass *dc = DEVICE_CLASS(oc); 2987 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2988 2989 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2990 pcc->init_proc = init_proc_MPC8xx; 2991 pcc->check_pow = check_pow_none; 2992 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2993 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2994 PPC_CACHE_ICBI | PPC_MFTB; 2995 pcc->msr_mask = (1ull << MSR_ILE) | 2996 (1ull << MSR_EE) | 2997 (1ull << MSR_PR) | 2998 (1ull << MSR_FP) | 2999 (1ull << MSR_ME) | 3000 (1ull << MSR_SE) | 3001 (1ull << MSR_DE) | 3002 (1ull << MSR_EP) | 3003 (1ull << MSR_IR) | 3004 (1ull << MSR_DR) | 3005 (1ull << MSR_RI) | 3006 (1ull << MSR_LE); 3007 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3008 pcc->excp_model = POWERPC_EXCP_603; 3009 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3010 pcc->bfd_mach = bfd_mach_ppc_860; 3011 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3012 POWERPC_FLAG_BUS_CLK; 3013 } 3014 3015 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3016 3017 static void init_proc_G2(CPUPPCState *env) 3018 { 3019 register_ne_601_sprs(env); 3020 register_sdr1_sprs(env); 3021 register_G2_755_sprs(env); 3022 register_G2_sprs(env); 3023 /* Time base */ 3024 register_tbl(env); 3025 /* External access control */ 3026 /* XXX : not implemented */ 3027 spr_register(env, SPR_EAR, "EAR", 3028 SPR_NOACCESS, SPR_NOACCESS, 3029 &spr_read_generic, &spr_write_generic, 3030 0x00000000); 3031 /* Hardware implementation register */ 3032 /* XXX : not implemented */ 3033 spr_register(env, SPR_HID0, "HID0", 3034 SPR_NOACCESS, SPR_NOACCESS, 3035 &spr_read_generic, &spr_write_generic, 3036 0x00000000); 3037 /* XXX : not implemented */ 3038 spr_register(env, SPR_HID1, "HID1", 3039 SPR_NOACCESS, SPR_NOACCESS, 3040 &spr_read_generic, &spr_write_generic, 3041 0x00000000); 3042 /* XXX : not implemented */ 3043 spr_register(env, SPR_HID2, "HID2", 3044 SPR_NOACCESS, SPR_NOACCESS, 3045 &spr_read_generic, &spr_write_generic, 3046 0x00000000); 3047 /* Memory management */ 3048 register_low_BATs(env); 3049 register_high_BATs(env); 3050 register_6xx_7xx_soft_tlb(env, 64, 2); 3051 init_excp_G2(env); 3052 env->dcache_line_size = 32; 3053 env->icache_line_size = 32; 3054 /* Allocate hardware IRQ controller */ 3055 ppc6xx_irq_init(env_archcpu(env)); 3056 } 3057 3058 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3059 { 3060 DeviceClass *dc = DEVICE_CLASS(oc); 3061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3062 3063 dc->desc = "PowerPC G2"; 3064 pcc->init_proc = init_proc_G2; 3065 pcc->check_pow = check_pow_hid0; 3066 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3067 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3068 PPC_FLOAT_STFIWX | 3069 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3070 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3071 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3072 PPC_SEGMENT | PPC_EXTERN; 3073 pcc->msr_mask = (1ull << MSR_POW) | 3074 (1ull << MSR_TGPR) | 3075 (1ull << MSR_EE) | 3076 (1ull << MSR_PR) | 3077 (1ull << MSR_FP) | 3078 (1ull << MSR_ME) | 3079 (1ull << MSR_FE0) | 3080 (1ull << MSR_SE) | 3081 (1ull << MSR_DE) | 3082 (1ull << MSR_FE1) | 3083 (1ull << MSR_AL) | 3084 (1ull << MSR_EP) | 3085 (1ull << MSR_IR) | 3086 (1ull << MSR_DR) | 3087 (1ull << MSR_RI); 3088 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3089 pcc->excp_model = POWERPC_EXCP_G2; 3090 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3091 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3092 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3093 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3094 } 3095 3096 static void init_proc_G2LE(CPUPPCState *env) 3097 { 3098 register_ne_601_sprs(env); 3099 register_sdr1_sprs(env); 3100 register_G2_755_sprs(env); 3101 register_G2_sprs(env); 3102 /* Time base */ 3103 register_tbl(env); 3104 /* External access control */ 3105 /* XXX : not implemented */ 3106 spr_register(env, SPR_EAR, "EAR", 3107 SPR_NOACCESS, SPR_NOACCESS, 3108 &spr_read_generic, &spr_write_generic, 3109 0x00000000); 3110 /* Hardware implementation register */ 3111 /* XXX : not implemented */ 3112 spr_register(env, SPR_HID0, "HID0", 3113 SPR_NOACCESS, SPR_NOACCESS, 3114 &spr_read_generic, &spr_write_generic, 3115 0x00000000); 3116 /* XXX : not implemented */ 3117 spr_register(env, SPR_HID1, "HID1", 3118 SPR_NOACCESS, SPR_NOACCESS, 3119 &spr_read_generic, &spr_write_generic, 3120 0x00000000); 3121 /* XXX : not implemented */ 3122 spr_register(env, SPR_HID2, "HID2", 3123 SPR_NOACCESS, SPR_NOACCESS, 3124 &spr_read_generic, &spr_write_generic, 3125 0x00000000); 3126 3127 /* Memory management */ 3128 register_low_BATs(env); 3129 register_high_BATs(env); 3130 register_6xx_7xx_soft_tlb(env, 64, 2); 3131 init_excp_G2(env); 3132 env->dcache_line_size = 32; 3133 env->icache_line_size = 32; 3134 /* Allocate hardware IRQ controller */ 3135 ppc6xx_irq_init(env_archcpu(env)); 3136 } 3137 3138 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3139 { 3140 DeviceClass *dc = DEVICE_CLASS(oc); 3141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3142 3143 dc->desc = "PowerPC G2LE"; 3144 pcc->init_proc = init_proc_G2LE; 3145 pcc->check_pow = check_pow_hid0; 3146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3147 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3148 PPC_FLOAT_STFIWX | 3149 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3150 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3151 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3152 PPC_SEGMENT | PPC_EXTERN; 3153 pcc->msr_mask = (1ull << MSR_POW) | 3154 (1ull << MSR_TGPR) | 3155 (1ull << MSR_ILE) | 3156 (1ull << MSR_EE) | 3157 (1ull << MSR_PR) | 3158 (1ull << MSR_FP) | 3159 (1ull << MSR_ME) | 3160 (1ull << MSR_FE0) | 3161 (1ull << MSR_SE) | 3162 (1ull << MSR_DE) | 3163 (1ull << MSR_FE1) | 3164 (1ull << MSR_AL) | 3165 (1ull << MSR_EP) | 3166 (1ull << MSR_IR) | 3167 (1ull << MSR_DR) | 3168 (1ull << MSR_RI) | 3169 (1ull << MSR_LE); 3170 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3171 pcc->excp_model = POWERPC_EXCP_G2; 3172 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3173 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3174 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3175 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3176 } 3177 3178 static void init_proc_e200(CPUPPCState *env) 3179 { 3180 /* Time base */ 3181 register_tbl(env); 3182 register_BookE_sprs(env, 0x000000070000FFFFULL); 3183 /* XXX : not implemented */ 3184 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3185 &spr_read_spefscr, &spr_write_spefscr, 3186 &spr_read_spefscr, &spr_write_spefscr, 3187 0x00000000); 3188 /* Memory management */ 3189 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3190 /* XXX : not implemented */ 3191 spr_register(env, SPR_HID0, "HID0", 3192 SPR_NOACCESS, SPR_NOACCESS, 3193 &spr_read_generic, &spr_write_generic, 3194 0x00000000); 3195 /* XXX : not implemented */ 3196 spr_register(env, SPR_HID1, "HID1", 3197 SPR_NOACCESS, SPR_NOACCESS, 3198 &spr_read_generic, &spr_write_generic, 3199 0x00000000); 3200 /* XXX : not implemented */ 3201 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3202 SPR_NOACCESS, SPR_NOACCESS, 3203 &spr_read_generic, &spr_write_generic, 3204 0x00000000); 3205 /* XXX : not implemented */ 3206 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3207 SPR_NOACCESS, SPR_NOACCESS, 3208 &spr_read_generic, &spr_write_generic, 3209 0x00000000); 3210 /* XXX : not implemented */ 3211 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3212 SPR_NOACCESS, SPR_NOACCESS, 3213 &spr_read_generic, &spr_write_generic, 3214 0x00000000); 3215 /* XXX : not implemented */ 3216 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3217 SPR_NOACCESS, SPR_NOACCESS, 3218 &spr_read_generic, &spr_write_generic, 3219 0x00000000); 3220 /* XXX : not implemented */ 3221 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3222 SPR_NOACCESS, SPR_NOACCESS, 3223 &spr_read_generic, &spr_write_generic, 3224 0x00000000); 3225 /* XXX : not implemented */ 3226 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3227 &spr_read_generic, SPR_NOACCESS, 3228 &spr_read_generic, SPR_NOACCESS, 3229 0x00000000); 3230 /* XXX : not implemented */ 3231 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3232 SPR_NOACCESS, SPR_NOACCESS, 3233 &spr_read_generic, &spr_write_generic, 3234 0x00000000); 3235 /* XXX : not implemented */ 3236 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3237 SPR_NOACCESS, SPR_NOACCESS, 3238 &spr_read_generic, &spr_write_generic, 3239 0x00000000); 3240 /* XXX : not implemented */ 3241 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3242 SPR_NOACCESS, SPR_NOACCESS, 3243 &spr_read_generic, &spr_write_generic, 3244 0x00000000); 3245 /* XXX : not implemented */ 3246 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3247 SPR_NOACCESS, SPR_NOACCESS, 3248 &spr_read_generic, &spr_write_generic, 3249 0x00000000); 3250 /* XXX : not implemented */ 3251 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3252 SPR_NOACCESS, SPR_NOACCESS, 3253 &spr_read_generic, &spr_write_generic, 3254 0x00000000); 3255 /* XXX : not implemented */ 3256 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3257 SPR_NOACCESS, SPR_NOACCESS, 3258 &spr_read_generic, &spr_write_generic, 3259 0x00000000); 3260 /* XXX : not implemented */ 3261 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3262 SPR_NOACCESS, SPR_NOACCESS, 3263 &spr_read_generic, &spr_write_generic, 3264 0x00000000); /* TOFIX */ 3265 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3266 SPR_NOACCESS, SPR_NOACCESS, 3267 &spr_read_generic, &spr_write_generic, 3268 0x00000000); 3269 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3270 SPR_NOACCESS, SPR_NOACCESS, 3271 &spr_read_generic, &spr_write_generic, 3272 0x00000000); 3273 #if !defined(CONFIG_USER_ONLY) 3274 env->nb_tlb = 64; 3275 env->nb_ways = 1; 3276 env->id_tlbs = 0; 3277 env->tlb_type = TLB_EMB; 3278 #endif 3279 init_excp_e200(env, 0xFFFF0000UL); 3280 env->dcache_line_size = 32; 3281 env->icache_line_size = 32; 3282 /* XXX: TODO: allocate internal IRQ controller */ 3283 } 3284 3285 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3286 { 3287 DeviceClass *dc = DEVICE_CLASS(oc); 3288 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3289 3290 dc->desc = "e200 core"; 3291 pcc->init_proc = init_proc_e200; 3292 pcc->check_pow = check_pow_hid0; 3293 /* 3294 * XXX: unimplemented instructions: 3295 * dcblc 3296 * dcbtlst 3297 * dcbtstls 3298 * icblc 3299 * icbtls 3300 * tlbivax 3301 * all SPE multiply-accumulate instructions 3302 */ 3303 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3304 PPC_SPE | PPC_SPE_SINGLE | 3305 PPC_WRTEE | PPC_RFDI | 3306 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3307 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3308 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3309 PPC_BOOKE; 3310 pcc->msr_mask = (1ull << MSR_UCLE) | 3311 (1ull << MSR_SPE) | 3312 (1ull << MSR_POW) | 3313 (1ull << MSR_CE) | 3314 (1ull << MSR_EE) | 3315 (1ull << MSR_PR) | 3316 (1ull << MSR_FP) | 3317 (1ull << MSR_ME) | 3318 (1ull << MSR_FE0) | 3319 (1ull << MSR_DWE) | 3320 (1ull << MSR_DE) | 3321 (1ull << MSR_FE1) | 3322 (1ull << MSR_IR) | 3323 (1ull << MSR_DR); 3324 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3325 pcc->excp_model = POWERPC_EXCP_BOOKE; 3326 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3327 pcc->bfd_mach = bfd_mach_ppc_860; 3328 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3329 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3330 POWERPC_FLAG_BUS_CLK; 3331 } 3332 3333 static void init_proc_e300(CPUPPCState *env) 3334 { 3335 register_ne_601_sprs(env); 3336 register_sdr1_sprs(env); 3337 register_603_sprs(env); 3338 /* Time base */ 3339 register_tbl(env); 3340 /* hardware implementation registers */ 3341 /* XXX : not implemented */ 3342 spr_register(env, SPR_HID0, "HID0", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_generic, 3345 0x00000000); 3346 /* XXX : not implemented */ 3347 spr_register(env, SPR_HID1, "HID1", 3348 SPR_NOACCESS, SPR_NOACCESS, 3349 &spr_read_generic, &spr_write_generic, 3350 0x00000000); 3351 /* XXX : not implemented */ 3352 spr_register(env, SPR_HID2, "HID2", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_generic, 3355 0x00000000); 3356 /* Breakpoints */ 3357 /* XXX : not implemented */ 3358 spr_register(env, SPR_DABR, "DABR", 3359 SPR_NOACCESS, SPR_NOACCESS, 3360 &spr_read_generic, &spr_write_generic, 3361 0x00000000); 3362 /* XXX : not implemented */ 3363 spr_register(env, SPR_DABR2, "DABR2", 3364 SPR_NOACCESS, SPR_NOACCESS, 3365 &spr_read_generic, &spr_write_generic, 3366 0x00000000); 3367 /* XXX : not implemented */ 3368 spr_register(env, SPR_IABR2, "IABR2", 3369 SPR_NOACCESS, SPR_NOACCESS, 3370 &spr_read_generic, &spr_write_generic, 3371 0x00000000); 3372 /* XXX : not implemented */ 3373 spr_register(env, SPR_IBCR, "IBCR", 3374 SPR_NOACCESS, SPR_NOACCESS, 3375 &spr_read_generic, &spr_write_generic, 3376 0x00000000); 3377 /* XXX : not implemented */ 3378 spr_register(env, SPR_DBCR, "DBCR", 3379 SPR_NOACCESS, SPR_NOACCESS, 3380 &spr_read_generic, &spr_write_generic, 3381 0x00000000); 3382 /* Memory management */ 3383 register_low_BATs(env); 3384 register_high_BATs(env); 3385 register_6xx_7xx_soft_tlb(env, 64, 2); 3386 init_excp_603(env); 3387 env->dcache_line_size = 32; 3388 env->icache_line_size = 32; 3389 /* Allocate hardware IRQ controller */ 3390 ppc6xx_irq_init(env_archcpu(env)); 3391 } 3392 3393 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3394 { 3395 DeviceClass *dc = DEVICE_CLASS(oc); 3396 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3397 3398 dc->desc = "e300 core"; 3399 pcc->init_proc = init_proc_e300; 3400 pcc->check_pow = check_pow_hid0; 3401 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3402 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3403 PPC_FLOAT_STFIWX | 3404 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3405 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3406 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3407 PPC_SEGMENT | PPC_EXTERN; 3408 pcc->msr_mask = (1ull << MSR_POW) | 3409 (1ull << MSR_TGPR) | 3410 (1ull << MSR_ILE) | 3411 (1ull << MSR_EE) | 3412 (1ull << MSR_PR) | 3413 (1ull << MSR_FP) | 3414 (1ull << MSR_ME) | 3415 (1ull << MSR_FE0) | 3416 (1ull << MSR_SE) | 3417 (1ull << MSR_DE) | 3418 (1ull << MSR_FE1) | 3419 (1ull << MSR_AL) | 3420 (1ull << MSR_EP) | 3421 (1ull << MSR_IR) | 3422 (1ull << MSR_DR) | 3423 (1ull << MSR_RI) | 3424 (1ull << MSR_LE); 3425 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3426 pcc->excp_model = POWERPC_EXCP_603; 3427 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3428 pcc->bfd_mach = bfd_mach_ppc_603; 3429 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3430 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3431 } 3432 3433 enum fsl_e500_version { 3434 fsl_e500v1, 3435 fsl_e500v2, 3436 fsl_e500mc, 3437 fsl_e5500, 3438 fsl_e6500, 3439 }; 3440 3441 static void init_proc_e500(CPUPPCState *env, int version) 3442 { 3443 uint32_t tlbncfg[2]; 3444 uint64_t ivor_mask; 3445 uint64_t ivpr_mask = 0xFFFF0000ULL; 3446 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3447 | 0x0020; /* 32 kb */ 3448 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3449 | 0x0020; /* 32 kb */ 3450 uint32_t mmucfg = 0; 3451 #if !defined(CONFIG_USER_ONLY) 3452 int i; 3453 #endif 3454 3455 /* Time base */ 3456 register_tbl(env); 3457 /* 3458 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3459 * complain when accessing them. 3460 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3461 */ 3462 switch (version) { 3463 case fsl_e500v1: 3464 case fsl_e500v2: 3465 default: 3466 ivor_mask = 0x0000000F0000FFFFULL; 3467 break; 3468 case fsl_e500mc: 3469 case fsl_e5500: 3470 ivor_mask = 0x000003FE0000FFFFULL; 3471 break; 3472 case fsl_e6500: 3473 ivor_mask = 0x000003FF0000FFFFULL; 3474 break; 3475 } 3476 register_BookE_sprs(env, ivor_mask); 3477 register_usprg3_sprs(env); 3478 /* Processor identification */ 3479 spr_register(env, SPR_BOOKE_PIR, "PIR", 3480 SPR_NOACCESS, SPR_NOACCESS, 3481 &spr_read_generic, &spr_write_pir, 3482 0x00000000); 3483 /* XXX : not implemented */ 3484 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3485 &spr_read_spefscr, &spr_write_spefscr, 3486 &spr_read_spefscr, &spr_write_spefscr, 3487 0x00000000); 3488 #if !defined(CONFIG_USER_ONLY) 3489 /* Memory management */ 3490 env->nb_pids = 3; 3491 env->nb_ways = 2; 3492 env->id_tlbs = 0; 3493 switch (version) { 3494 case fsl_e500v1: 3495 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3496 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3497 break; 3498 case fsl_e500v2: 3499 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3500 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3501 break; 3502 case fsl_e500mc: 3503 case fsl_e5500: 3504 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3505 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3506 break; 3507 case fsl_e6500: 3508 mmucfg = 0x6510B45; 3509 env->nb_pids = 1; 3510 tlbncfg[0] = 0x08052400; 3511 tlbncfg[1] = 0x40028040; 3512 break; 3513 default: 3514 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3515 env->spr[SPR_PVR]); 3516 } 3517 #endif 3518 /* Cache sizes */ 3519 switch (version) { 3520 case fsl_e500v1: 3521 case fsl_e500v2: 3522 env->dcache_line_size = 32; 3523 env->icache_line_size = 32; 3524 break; 3525 case fsl_e500mc: 3526 case fsl_e5500: 3527 env->dcache_line_size = 64; 3528 env->icache_line_size = 64; 3529 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3530 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3531 break; 3532 case fsl_e6500: 3533 env->dcache_line_size = 32; 3534 env->icache_line_size = 32; 3535 l1cfg0 |= 0x0F83820; 3536 l1cfg1 |= 0x0B83820; 3537 break; 3538 default: 3539 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3540 env->spr[SPR_PVR]); 3541 } 3542 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3543 /* XXX : not implemented */ 3544 spr_register(env, SPR_HID0, "HID0", 3545 SPR_NOACCESS, SPR_NOACCESS, 3546 &spr_read_generic, &spr_write_generic, 3547 0x00000000); 3548 /* XXX : not implemented */ 3549 spr_register(env, SPR_HID1, "HID1", 3550 SPR_NOACCESS, SPR_NOACCESS, 3551 &spr_read_generic, &spr_write_generic, 3552 0x00000000); 3553 /* XXX : not implemented */ 3554 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3555 SPR_NOACCESS, SPR_NOACCESS, 3556 &spr_read_generic, &spr_write_generic, 3557 0x00000000); 3558 /* XXX : not implemented */ 3559 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3560 SPR_NOACCESS, SPR_NOACCESS, 3561 &spr_read_generic, &spr_write_generic, 3562 0x00000000); 3563 /* XXX : not implemented */ 3564 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3565 SPR_NOACCESS, SPR_NOACCESS, 3566 &spr_read_generic, &spr_write_generic, 3567 0x00000000); 3568 /* XXX : not implemented */ 3569 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3570 SPR_NOACCESS, SPR_NOACCESS, 3571 &spr_read_generic, &spr_write_generic, 3572 0x00000000); 3573 /* XXX : not implemented */ 3574 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3575 SPR_NOACCESS, SPR_NOACCESS, 3576 &spr_read_generic, &spr_write_generic, 3577 0x00000000); 3578 /* XXX : not implemented */ 3579 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3580 SPR_NOACCESS, SPR_NOACCESS, 3581 &spr_read_generic, &spr_write_generic, 3582 0x00000000); 3583 /* XXX : not implemented */ 3584 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3585 &spr_read_generic, SPR_NOACCESS, 3586 &spr_read_generic, SPR_NOACCESS, 3587 l1cfg0); 3588 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3589 &spr_read_generic, SPR_NOACCESS, 3590 &spr_read_generic, SPR_NOACCESS, 3591 l1cfg1); 3592 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3593 SPR_NOACCESS, SPR_NOACCESS, 3594 &spr_read_generic, &spr_write_e500_l1csr0, 3595 0x00000000); 3596 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3597 SPR_NOACCESS, SPR_NOACCESS, 3598 &spr_read_generic, &spr_write_e500_l1csr1, 3599 0x00000000); 3600 if (version != fsl_e500v1 && version != fsl_e500v2) { 3601 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3602 SPR_NOACCESS, SPR_NOACCESS, 3603 &spr_read_generic, &spr_write_e500_l2csr0, 3604 0x00000000); 3605 } 3606 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3607 SPR_NOACCESS, SPR_NOACCESS, 3608 &spr_read_generic, &spr_write_generic, 3609 0x00000000); 3610 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3611 SPR_NOACCESS, SPR_NOACCESS, 3612 &spr_read_generic, &spr_write_generic, 3613 0x00000000); 3614 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3615 SPR_NOACCESS, SPR_NOACCESS, 3616 &spr_read_generic, &spr_write_booke206_mmucsr0, 3617 0x00000000); 3618 spr_register(env, SPR_BOOKE_EPR, "EPR", 3619 SPR_NOACCESS, SPR_NOACCESS, 3620 &spr_read_generic, SPR_NOACCESS, 3621 0x00000000); 3622 /* XXX better abstract into Emb.xxx features */ 3623 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3624 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3625 SPR_NOACCESS, SPR_NOACCESS, 3626 &spr_read_generic, &spr_write_generic, 3627 0x00000000); 3628 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3629 SPR_NOACCESS, SPR_NOACCESS, 3630 &spr_read_mas73, &spr_write_mas73, 3631 0x00000000); 3632 ivpr_mask = (target_ulong)~0xFFFFULL; 3633 } 3634 3635 if (version == fsl_e6500) { 3636 /* Thread identification */ 3637 spr_register(env, SPR_TIR, "TIR", 3638 SPR_NOACCESS, SPR_NOACCESS, 3639 &spr_read_generic, SPR_NOACCESS, 3640 0x00000000); 3641 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3642 SPR_NOACCESS, SPR_NOACCESS, 3643 &spr_read_generic, SPR_NOACCESS, 3644 0x00000004); 3645 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3646 SPR_NOACCESS, SPR_NOACCESS, 3647 &spr_read_generic, SPR_NOACCESS, 3648 0x7FFFFFFC); 3649 } 3650 3651 #if !defined(CONFIG_USER_ONLY) 3652 env->nb_tlb = 0; 3653 env->tlb_type = TLB_MAS; 3654 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3655 env->nb_tlb += booke206_tlb_size(env, i); 3656 } 3657 #endif 3658 3659 init_excp_e200(env, ivpr_mask); 3660 /* Allocate hardware IRQ controller */ 3661 ppce500_irq_init(env_archcpu(env)); 3662 } 3663 3664 static void init_proc_e500v1(CPUPPCState *env) 3665 { 3666 init_proc_e500(env, fsl_e500v1); 3667 } 3668 3669 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3670 { 3671 DeviceClass *dc = DEVICE_CLASS(oc); 3672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3673 3674 dc->desc = "e500v1 core"; 3675 pcc->init_proc = init_proc_e500v1; 3676 pcc->check_pow = check_pow_hid0; 3677 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3678 PPC_SPE | PPC_SPE_SINGLE | 3679 PPC_WRTEE | PPC_RFDI | 3680 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3681 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3682 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3683 pcc->insns_flags2 = PPC2_BOOKE206; 3684 pcc->msr_mask = (1ull << MSR_UCLE) | 3685 (1ull << MSR_SPE) | 3686 (1ull << MSR_POW) | 3687 (1ull << MSR_CE) | 3688 (1ull << MSR_EE) | 3689 (1ull << MSR_PR) | 3690 (1ull << MSR_FP) | 3691 (1ull << MSR_ME) | 3692 (1ull << MSR_FE0) | 3693 (1ull << MSR_DWE) | 3694 (1ull << MSR_DE) | 3695 (1ull << MSR_FE1) | 3696 (1ull << MSR_IR) | 3697 (1ull << MSR_DR); 3698 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3699 pcc->excp_model = POWERPC_EXCP_BOOKE; 3700 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3701 pcc->bfd_mach = bfd_mach_ppc_860; 3702 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3703 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3704 POWERPC_FLAG_BUS_CLK; 3705 } 3706 3707 static void init_proc_e500v2(CPUPPCState *env) 3708 { 3709 init_proc_e500(env, fsl_e500v2); 3710 } 3711 3712 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3713 { 3714 DeviceClass *dc = DEVICE_CLASS(oc); 3715 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3716 3717 dc->desc = "e500v2 core"; 3718 pcc->init_proc = init_proc_e500v2; 3719 pcc->check_pow = check_pow_hid0; 3720 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3721 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3722 PPC_WRTEE | PPC_RFDI | 3723 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3724 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3725 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3726 pcc->insns_flags2 = PPC2_BOOKE206; 3727 pcc->msr_mask = (1ull << MSR_UCLE) | 3728 (1ull << MSR_SPE) | 3729 (1ull << MSR_POW) | 3730 (1ull << MSR_CE) | 3731 (1ull << MSR_EE) | 3732 (1ull << MSR_PR) | 3733 (1ull << MSR_FP) | 3734 (1ull << MSR_ME) | 3735 (1ull << MSR_FE0) | 3736 (1ull << MSR_DWE) | 3737 (1ull << MSR_DE) | 3738 (1ull << MSR_FE1) | 3739 (1ull << MSR_IR) | 3740 (1ull << MSR_DR); 3741 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3742 pcc->excp_model = POWERPC_EXCP_BOOKE; 3743 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3744 pcc->bfd_mach = bfd_mach_ppc_860; 3745 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3746 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3747 POWERPC_FLAG_BUS_CLK; 3748 } 3749 3750 static void init_proc_e500mc(CPUPPCState *env) 3751 { 3752 init_proc_e500(env, fsl_e500mc); 3753 } 3754 3755 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3756 { 3757 DeviceClass *dc = DEVICE_CLASS(oc); 3758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3759 3760 dc->desc = "e500mc core"; 3761 pcc->init_proc = init_proc_e500mc; 3762 pcc->check_pow = check_pow_none; 3763 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3764 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3765 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3766 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3767 PPC_FLOAT | PPC_FLOAT_FRES | 3768 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3769 PPC_FLOAT_STFIWX | PPC_WAIT | 3770 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3771 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3772 pcc->msr_mask = (1ull << MSR_GS) | 3773 (1ull << MSR_UCLE) | 3774 (1ull << MSR_CE) | 3775 (1ull << MSR_EE) | 3776 (1ull << MSR_PR) | 3777 (1ull << MSR_FP) | 3778 (1ull << MSR_ME) | 3779 (1ull << MSR_FE0) | 3780 (1ull << MSR_DE) | 3781 (1ull << MSR_FE1) | 3782 (1ull << MSR_IR) | 3783 (1ull << MSR_DR) | 3784 (1ull << MSR_PX) | 3785 (1ull << MSR_RI); 3786 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3787 pcc->excp_model = POWERPC_EXCP_BOOKE; 3788 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3789 /* FIXME: figure out the correct flag for e500mc */ 3790 pcc->bfd_mach = bfd_mach_ppc_e500; 3791 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3792 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3793 } 3794 3795 #ifdef TARGET_PPC64 3796 static void init_proc_e5500(CPUPPCState *env) 3797 { 3798 init_proc_e500(env, fsl_e5500); 3799 } 3800 3801 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3802 { 3803 DeviceClass *dc = DEVICE_CLASS(oc); 3804 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3805 3806 dc->desc = "e5500 core"; 3807 pcc->init_proc = init_proc_e5500; 3808 pcc->check_pow = check_pow_none; 3809 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3810 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3811 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3812 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3813 PPC_FLOAT | PPC_FLOAT_FRES | 3814 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3815 PPC_FLOAT_STFIWX | PPC_WAIT | 3816 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3817 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3818 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3819 PPC2_FP_CVT_S64; 3820 pcc->msr_mask = (1ull << MSR_CM) | 3821 (1ull << MSR_GS) | 3822 (1ull << MSR_UCLE) | 3823 (1ull << MSR_CE) | 3824 (1ull << MSR_EE) | 3825 (1ull << MSR_PR) | 3826 (1ull << MSR_FP) | 3827 (1ull << MSR_ME) | 3828 (1ull << MSR_FE0) | 3829 (1ull << MSR_DE) | 3830 (1ull << MSR_FE1) | 3831 (1ull << MSR_IR) | 3832 (1ull << MSR_DR) | 3833 (1ull << MSR_PX) | 3834 (1ull << MSR_RI); 3835 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3836 pcc->excp_model = POWERPC_EXCP_BOOKE; 3837 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3838 /* FIXME: figure out the correct flag for e5500 */ 3839 pcc->bfd_mach = bfd_mach_ppc_e500; 3840 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3841 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3842 } 3843 3844 static void init_proc_e6500(CPUPPCState *env) 3845 { 3846 init_proc_e500(env, fsl_e6500); 3847 } 3848 3849 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3850 { 3851 DeviceClass *dc = DEVICE_CLASS(oc); 3852 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3853 3854 dc->desc = "e6500 core"; 3855 pcc->init_proc = init_proc_e6500; 3856 pcc->check_pow = check_pow_none; 3857 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3858 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3859 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3860 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3861 PPC_FLOAT | PPC_FLOAT_FRES | 3862 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3863 PPC_FLOAT_STFIWX | PPC_WAIT | 3864 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3865 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3866 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3867 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3868 pcc->msr_mask = (1ull << MSR_CM) | 3869 (1ull << MSR_GS) | 3870 (1ull << MSR_UCLE) | 3871 (1ull << MSR_CE) | 3872 (1ull << MSR_EE) | 3873 (1ull << MSR_PR) | 3874 (1ull << MSR_FP) | 3875 (1ull << MSR_ME) | 3876 (1ull << MSR_FE0) | 3877 (1ull << MSR_DE) | 3878 (1ull << MSR_FE1) | 3879 (1ull << MSR_IS) | 3880 (1ull << MSR_DS) | 3881 (1ull << MSR_PX) | 3882 (1ull << MSR_RI) | 3883 (1ull << MSR_VR); 3884 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3885 pcc->excp_model = POWERPC_EXCP_BOOKE; 3886 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3887 pcc->bfd_mach = bfd_mach_ppc_e500; 3888 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3889 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3890 } 3891 3892 #endif 3893 3894 /* Non-embedded PowerPC */ 3895 3896 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 3897 3898 static void init_proc_601(CPUPPCState *env) 3899 { 3900 register_ne_601_sprs(env); 3901 register_sdr1_sprs(env); 3902 register_601_sprs(env); 3903 /* Hardware implementation registers */ 3904 /* XXX : not implemented */ 3905 spr_register(env, SPR_HID0, "HID0", 3906 SPR_NOACCESS, SPR_NOACCESS, 3907 &spr_read_generic, &spr_write_hid0_601, 3908 0x80010080); 3909 /* XXX : not implemented */ 3910 spr_register(env, SPR_HID1, "HID1", 3911 SPR_NOACCESS, SPR_NOACCESS, 3912 &spr_read_generic, &spr_write_generic, 3913 0x00000000); 3914 /* XXX : not implemented */ 3915 spr_register(env, SPR_601_HID2, "HID2", 3916 SPR_NOACCESS, SPR_NOACCESS, 3917 &spr_read_generic, &spr_write_generic, 3918 0x00000000); 3919 /* XXX : not implemented */ 3920 spr_register(env, SPR_601_HID5, "HID5", 3921 SPR_NOACCESS, SPR_NOACCESS, 3922 &spr_read_generic, &spr_write_generic, 3923 0x00000000); 3924 /* Memory management */ 3925 init_excp_601(env); 3926 /* 3927 * XXX: beware that dcache line size is 64 3928 * but dcbz uses 32 bytes "sectors" 3929 * XXX: this breaks clcs instruction ! 3930 */ 3931 env->dcache_line_size = 32; 3932 env->icache_line_size = 64; 3933 /* Allocate hardware IRQ controller */ 3934 ppc6xx_irq_init(env_archcpu(env)); 3935 } 3936 3937 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 3938 { 3939 DeviceClass *dc = DEVICE_CLASS(oc); 3940 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3941 3942 dc->desc = "PowerPC 601"; 3943 pcc->init_proc = init_proc_601; 3944 pcc->check_pow = check_pow_none; 3945 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 3946 PPC_FLOAT | 3947 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3948 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 3949 PPC_SEGMENT | PPC_EXTERN; 3950 pcc->msr_mask = (1ull << MSR_EE) | 3951 (1ull << MSR_PR) | 3952 (1ull << MSR_FP) | 3953 (1ull << MSR_ME) | 3954 (1ull << MSR_FE0) | 3955 (1ull << MSR_SE) | 3956 (1ull << MSR_FE1) | 3957 (1ull << MSR_EP) | 3958 (1ull << MSR_IR) | 3959 (1ull << MSR_DR); 3960 pcc->mmu_model = POWERPC_MMU_601; 3961 pcc->excp_model = POWERPC_EXCP_601; 3962 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3963 pcc->bfd_mach = bfd_mach_ppc_601; 3964 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 3965 } 3966 3967 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 3968 3969 static void init_proc_601v(CPUPPCState *env) 3970 { 3971 init_proc_601(env); 3972 /* XXX : not implemented */ 3973 spr_register(env, SPR_601_HID15, "HID15", 3974 SPR_NOACCESS, SPR_NOACCESS, 3975 &spr_read_generic, &spr_write_generic, 3976 0x00000000); 3977 } 3978 3979 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 3980 { 3981 DeviceClass *dc = DEVICE_CLASS(oc); 3982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3983 3984 dc->desc = "PowerPC 601v"; 3985 pcc->init_proc = init_proc_601v; 3986 pcc->check_pow = check_pow_none; 3987 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 3988 PPC_FLOAT | 3989 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3990 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 3991 PPC_SEGMENT | PPC_EXTERN; 3992 pcc->msr_mask = (1ull << MSR_EE) | 3993 (1ull << MSR_PR) | 3994 (1ull << MSR_FP) | 3995 (1ull << MSR_ME) | 3996 (1ull << MSR_FE0) | 3997 (1ull << MSR_SE) | 3998 (1ull << MSR_FE1) | 3999 (1ull << MSR_EP) | 4000 (1ull << MSR_IR) | 4001 (1ull << MSR_DR); 4002 pcc->mmu_model = POWERPC_MMU_601; 4003 pcc->excp_model = POWERPC_EXCP_601; 4004 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4005 pcc->bfd_mach = bfd_mach_ppc_601; 4006 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4007 } 4008 4009 static void init_proc_603(CPUPPCState *env) 4010 { 4011 register_ne_601_sprs(env); 4012 register_sdr1_sprs(env); 4013 register_603_sprs(env); 4014 /* Time base */ 4015 register_tbl(env); 4016 /* hardware implementation registers */ 4017 /* XXX : not implemented */ 4018 spr_register(env, SPR_HID0, "HID0", 4019 SPR_NOACCESS, SPR_NOACCESS, 4020 &spr_read_generic, &spr_write_generic, 4021 0x00000000); 4022 /* XXX : not implemented */ 4023 spr_register(env, SPR_HID1, "HID1", 4024 SPR_NOACCESS, SPR_NOACCESS, 4025 &spr_read_generic, &spr_write_generic, 4026 0x00000000); 4027 /* Memory management */ 4028 register_low_BATs(env); 4029 register_6xx_7xx_soft_tlb(env, 64, 2); 4030 init_excp_603(env); 4031 env->dcache_line_size = 32; 4032 env->icache_line_size = 32; 4033 /* Allocate hardware IRQ controller */ 4034 ppc6xx_irq_init(env_archcpu(env)); 4035 } 4036 4037 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4038 { 4039 DeviceClass *dc = DEVICE_CLASS(oc); 4040 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4041 4042 dc->desc = "PowerPC 603"; 4043 pcc->init_proc = init_proc_603; 4044 pcc->check_pow = check_pow_hid0; 4045 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4046 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4047 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4048 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4049 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4050 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4051 PPC_SEGMENT | PPC_EXTERN; 4052 pcc->msr_mask = (1ull << MSR_POW) | 4053 (1ull << MSR_TGPR) | 4054 (1ull << MSR_ILE) | 4055 (1ull << MSR_EE) | 4056 (1ull << MSR_PR) | 4057 (1ull << MSR_FP) | 4058 (1ull << MSR_ME) | 4059 (1ull << MSR_FE0) | 4060 (1ull << MSR_SE) | 4061 (1ull << MSR_DE) | 4062 (1ull << MSR_FE1) | 4063 (1ull << MSR_EP) | 4064 (1ull << MSR_IR) | 4065 (1ull << MSR_DR) | 4066 (1ull << MSR_RI) | 4067 (1ull << MSR_LE); 4068 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4069 pcc->excp_model = POWERPC_EXCP_603; 4070 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4071 pcc->bfd_mach = bfd_mach_ppc_603; 4072 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4073 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4074 } 4075 4076 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4077 { 4078 DeviceClass *dc = DEVICE_CLASS(oc); 4079 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4080 4081 dc->desc = "PowerPC 603e"; 4082 pcc->init_proc = init_proc_603; 4083 pcc->check_pow = check_pow_hid0; 4084 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4085 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4086 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4087 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4088 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4089 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4090 PPC_SEGMENT | PPC_EXTERN; 4091 pcc->msr_mask = (1ull << MSR_POW) | 4092 (1ull << MSR_TGPR) | 4093 (1ull << MSR_ILE) | 4094 (1ull << MSR_EE) | 4095 (1ull << MSR_PR) | 4096 (1ull << MSR_FP) | 4097 (1ull << MSR_ME) | 4098 (1ull << MSR_FE0) | 4099 (1ull << MSR_SE) | 4100 (1ull << MSR_DE) | 4101 (1ull << MSR_FE1) | 4102 (1ull << MSR_EP) | 4103 (1ull << MSR_IR) | 4104 (1ull << MSR_DR) | 4105 (1ull << MSR_RI) | 4106 (1ull << MSR_LE); 4107 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4108 pcc->excp_model = POWERPC_EXCP_603; 4109 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4110 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4111 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4112 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4113 } 4114 4115 static void init_proc_604(CPUPPCState *env) 4116 { 4117 register_ne_601_sprs(env); 4118 register_sdr1_sprs(env); 4119 register_604_sprs(env); 4120 /* Time base */ 4121 register_tbl(env); 4122 /* Hardware implementation registers */ 4123 /* XXX : not implemented */ 4124 spr_register(env, SPR_HID0, "HID0", 4125 SPR_NOACCESS, SPR_NOACCESS, 4126 &spr_read_generic, &spr_write_generic, 4127 0x00000000); 4128 /* Memory management */ 4129 register_low_BATs(env); 4130 init_excp_604(env); 4131 env->dcache_line_size = 32; 4132 env->icache_line_size = 32; 4133 /* Allocate hardware IRQ controller */ 4134 ppc6xx_irq_init(env_archcpu(env)); 4135 } 4136 4137 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4138 { 4139 DeviceClass *dc = DEVICE_CLASS(oc); 4140 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4141 4142 dc->desc = "PowerPC 604"; 4143 pcc->init_proc = init_proc_604; 4144 pcc->check_pow = check_pow_nocheck; 4145 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4146 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4147 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4148 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4149 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4150 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4151 PPC_SEGMENT | PPC_EXTERN; 4152 pcc->msr_mask = (1ull << MSR_POW) | 4153 (1ull << MSR_ILE) | 4154 (1ull << MSR_EE) | 4155 (1ull << MSR_PR) | 4156 (1ull << MSR_FP) | 4157 (1ull << MSR_ME) | 4158 (1ull << MSR_FE0) | 4159 (1ull << MSR_SE) | 4160 (1ull << MSR_DE) | 4161 (1ull << MSR_FE1) | 4162 (1ull << MSR_EP) | 4163 (1ull << MSR_IR) | 4164 (1ull << MSR_DR) | 4165 (1ull << MSR_PMM) | 4166 (1ull << MSR_RI) | 4167 (1ull << MSR_LE); 4168 pcc->mmu_model = POWERPC_MMU_32B; 4169 pcc->excp_model = POWERPC_EXCP_604; 4170 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4171 pcc->bfd_mach = bfd_mach_ppc_604; 4172 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4173 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4174 } 4175 4176 static void init_proc_604E(CPUPPCState *env) 4177 { 4178 register_ne_601_sprs(env); 4179 register_sdr1_sprs(env); 4180 register_604_sprs(env); 4181 /* XXX : not implemented */ 4182 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4183 SPR_NOACCESS, SPR_NOACCESS, 4184 &spr_read_generic, &spr_write_generic, 4185 0x00000000); 4186 /* XXX : not implemented */ 4187 spr_register(env, SPR_7XX_PMC3, "PMC3", 4188 SPR_NOACCESS, SPR_NOACCESS, 4189 &spr_read_generic, &spr_write_generic, 4190 0x00000000); 4191 /* XXX : not implemented */ 4192 spr_register(env, SPR_7XX_PMC4, "PMC4", 4193 SPR_NOACCESS, SPR_NOACCESS, 4194 &spr_read_generic, &spr_write_generic, 4195 0x00000000); 4196 /* Time base */ 4197 register_tbl(env); 4198 /* Hardware implementation registers */ 4199 /* XXX : not implemented */ 4200 spr_register(env, SPR_HID0, "HID0", 4201 SPR_NOACCESS, SPR_NOACCESS, 4202 &spr_read_generic, &spr_write_generic, 4203 0x00000000); 4204 /* XXX : not implemented */ 4205 spr_register(env, SPR_HID1, "HID1", 4206 SPR_NOACCESS, SPR_NOACCESS, 4207 &spr_read_generic, &spr_write_generic, 4208 0x00000000); 4209 /* Memory management */ 4210 register_low_BATs(env); 4211 init_excp_604(env); 4212 env->dcache_line_size = 32; 4213 env->icache_line_size = 32; 4214 /* Allocate hardware IRQ controller */ 4215 ppc6xx_irq_init(env_archcpu(env)); 4216 } 4217 4218 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4219 { 4220 DeviceClass *dc = DEVICE_CLASS(oc); 4221 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4222 4223 dc->desc = "PowerPC 604E"; 4224 pcc->init_proc = init_proc_604E; 4225 pcc->check_pow = check_pow_nocheck; 4226 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4227 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4228 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4229 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4230 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4232 PPC_SEGMENT | PPC_EXTERN; 4233 pcc->msr_mask = (1ull << MSR_POW) | 4234 (1ull << MSR_ILE) | 4235 (1ull << MSR_EE) | 4236 (1ull << MSR_PR) | 4237 (1ull << MSR_FP) | 4238 (1ull << MSR_ME) | 4239 (1ull << MSR_FE0) | 4240 (1ull << MSR_SE) | 4241 (1ull << MSR_DE) | 4242 (1ull << MSR_FE1) | 4243 (1ull << MSR_EP) | 4244 (1ull << MSR_IR) | 4245 (1ull << MSR_DR) | 4246 (1ull << MSR_PMM) | 4247 (1ull << MSR_RI) | 4248 (1ull << MSR_LE); 4249 pcc->mmu_model = POWERPC_MMU_32B; 4250 pcc->excp_model = POWERPC_EXCP_604; 4251 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4252 pcc->bfd_mach = bfd_mach_ppc_604; 4253 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4254 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4255 } 4256 4257 static void init_proc_740(CPUPPCState *env) 4258 { 4259 register_ne_601_sprs(env); 4260 register_sdr1_sprs(env); 4261 register_7xx_sprs(env); 4262 /* Time base */ 4263 register_tbl(env); 4264 /* Thermal management */ 4265 register_thrm_sprs(env); 4266 /* Hardware implementation registers */ 4267 /* XXX : not implemented */ 4268 spr_register(env, SPR_HID0, "HID0", 4269 SPR_NOACCESS, SPR_NOACCESS, 4270 &spr_read_generic, &spr_write_generic, 4271 0x00000000); 4272 /* XXX : not implemented */ 4273 spr_register(env, SPR_HID1, "HID1", 4274 SPR_NOACCESS, SPR_NOACCESS, 4275 &spr_read_generic, &spr_write_generic, 4276 0x00000000); 4277 /* Memory management */ 4278 register_low_BATs(env); 4279 init_excp_7x0(env); 4280 env->dcache_line_size = 32; 4281 env->icache_line_size = 32; 4282 /* Allocate hardware IRQ controller */ 4283 ppc6xx_irq_init(env_archcpu(env)); 4284 } 4285 4286 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 4287 { 4288 DeviceClass *dc = DEVICE_CLASS(oc); 4289 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4290 4291 dc->desc = "PowerPC 740"; 4292 pcc->init_proc = init_proc_740; 4293 pcc->check_pow = check_pow_hid0; 4294 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4295 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4296 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4297 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4298 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4299 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4300 PPC_SEGMENT | PPC_EXTERN; 4301 pcc->msr_mask = (1ull << MSR_POW) | 4302 (1ull << MSR_ILE) | 4303 (1ull << MSR_EE) | 4304 (1ull << MSR_PR) | 4305 (1ull << MSR_FP) | 4306 (1ull << MSR_ME) | 4307 (1ull << MSR_FE0) | 4308 (1ull << MSR_SE) | 4309 (1ull << MSR_DE) | 4310 (1ull << MSR_FE1) | 4311 (1ull << MSR_EP) | 4312 (1ull << MSR_IR) | 4313 (1ull << MSR_DR) | 4314 (1ull << MSR_PMM) | 4315 (1ull << MSR_RI) | 4316 (1ull << MSR_LE); 4317 pcc->mmu_model = POWERPC_MMU_32B; 4318 pcc->excp_model = POWERPC_EXCP_7x0; 4319 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4320 pcc->bfd_mach = bfd_mach_ppc_750; 4321 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4322 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4323 } 4324 4325 static void init_proc_750(CPUPPCState *env) 4326 { 4327 register_ne_601_sprs(env); 4328 register_sdr1_sprs(env); 4329 register_7xx_sprs(env); 4330 /* XXX : not implemented */ 4331 spr_register(env, SPR_L2CR, "L2CR", 4332 SPR_NOACCESS, SPR_NOACCESS, 4333 &spr_read_generic, spr_access_nop, 4334 0x00000000); 4335 /* Time base */ 4336 register_tbl(env); 4337 /* Thermal management */ 4338 register_thrm_sprs(env); 4339 /* Hardware implementation registers */ 4340 /* XXX : not implemented */ 4341 spr_register(env, SPR_HID0, "HID0", 4342 SPR_NOACCESS, SPR_NOACCESS, 4343 &spr_read_generic, &spr_write_generic, 4344 0x00000000); 4345 /* XXX : not implemented */ 4346 spr_register(env, SPR_HID1, "HID1", 4347 SPR_NOACCESS, SPR_NOACCESS, 4348 &spr_read_generic, &spr_write_generic, 4349 0x00000000); 4350 /* Memory management */ 4351 register_low_BATs(env); 4352 /* 4353 * XXX: high BATs are also present but are known to be bugged on 4354 * die version 1.x 4355 */ 4356 init_excp_7x0(env); 4357 env->dcache_line_size = 32; 4358 env->icache_line_size = 32; 4359 /* Allocate hardware IRQ controller */ 4360 ppc6xx_irq_init(env_archcpu(env)); 4361 } 4362 4363 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4364 { 4365 DeviceClass *dc = DEVICE_CLASS(oc); 4366 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4367 4368 dc->desc = "PowerPC 750"; 4369 pcc->init_proc = init_proc_750; 4370 pcc->check_pow = check_pow_hid0; 4371 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4372 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4373 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4374 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4375 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4377 PPC_SEGMENT | PPC_EXTERN; 4378 pcc->msr_mask = (1ull << MSR_POW) | 4379 (1ull << MSR_ILE) | 4380 (1ull << MSR_EE) | 4381 (1ull << MSR_PR) | 4382 (1ull << MSR_FP) | 4383 (1ull << MSR_ME) | 4384 (1ull << MSR_FE0) | 4385 (1ull << MSR_SE) | 4386 (1ull << MSR_DE) | 4387 (1ull << MSR_FE1) | 4388 (1ull << MSR_EP) | 4389 (1ull << MSR_IR) | 4390 (1ull << MSR_DR) | 4391 (1ull << MSR_PMM) | 4392 (1ull << MSR_RI) | 4393 (1ull << MSR_LE); 4394 pcc->mmu_model = POWERPC_MMU_32B; 4395 pcc->excp_model = POWERPC_EXCP_7x0; 4396 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4397 pcc->bfd_mach = bfd_mach_ppc_750; 4398 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4399 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4400 } 4401 4402 static void init_proc_750cl(CPUPPCState *env) 4403 { 4404 register_ne_601_sprs(env); 4405 register_sdr1_sprs(env); 4406 register_7xx_sprs(env); 4407 /* XXX : not implemented */ 4408 spr_register(env, SPR_L2CR, "L2CR", 4409 SPR_NOACCESS, SPR_NOACCESS, 4410 &spr_read_generic, spr_access_nop, 4411 0x00000000); 4412 /* Time base */ 4413 register_tbl(env); 4414 /* Thermal management */ 4415 /* Those registers are fake on 750CL */ 4416 spr_register(env, SPR_THRM1, "THRM1", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, &spr_write_generic, 4419 0x00000000); 4420 spr_register(env, SPR_THRM2, "THRM2", 4421 SPR_NOACCESS, SPR_NOACCESS, 4422 &spr_read_generic, &spr_write_generic, 4423 0x00000000); 4424 spr_register(env, SPR_THRM3, "THRM3", 4425 SPR_NOACCESS, SPR_NOACCESS, 4426 &spr_read_generic, &spr_write_generic, 4427 0x00000000); 4428 /* XXX: not implemented */ 4429 spr_register(env, SPR_750_TDCL, "TDCL", 4430 SPR_NOACCESS, SPR_NOACCESS, 4431 &spr_read_generic, &spr_write_generic, 4432 0x00000000); 4433 spr_register(env, SPR_750_TDCH, "TDCH", 4434 SPR_NOACCESS, SPR_NOACCESS, 4435 &spr_read_generic, &spr_write_generic, 4436 0x00000000); 4437 /* DMA */ 4438 /* XXX : not implemented */ 4439 spr_register(env, SPR_750_WPAR, "WPAR", 4440 SPR_NOACCESS, SPR_NOACCESS, 4441 &spr_read_generic, &spr_write_generic, 4442 0x00000000); 4443 spr_register(env, SPR_750_DMAL, "DMAL", 4444 SPR_NOACCESS, SPR_NOACCESS, 4445 &spr_read_generic, &spr_write_generic, 4446 0x00000000); 4447 spr_register(env, SPR_750_DMAU, "DMAU", 4448 SPR_NOACCESS, SPR_NOACCESS, 4449 &spr_read_generic, &spr_write_generic, 4450 0x00000000); 4451 /* Hardware implementation registers */ 4452 /* XXX : not implemented */ 4453 spr_register(env, SPR_HID0, "HID0", 4454 SPR_NOACCESS, SPR_NOACCESS, 4455 &spr_read_generic, &spr_write_generic, 4456 0x00000000); 4457 /* XXX : not implemented */ 4458 spr_register(env, SPR_HID1, "HID1", 4459 SPR_NOACCESS, SPR_NOACCESS, 4460 &spr_read_generic, &spr_write_generic, 4461 0x00000000); 4462 /* XXX : not implemented */ 4463 spr_register(env, SPR_750CL_HID2, "HID2", 4464 SPR_NOACCESS, SPR_NOACCESS, 4465 &spr_read_generic, &spr_write_generic, 4466 0x00000000); 4467 /* XXX : not implemented */ 4468 spr_register(env, SPR_750CL_HID4, "HID4", 4469 SPR_NOACCESS, SPR_NOACCESS, 4470 &spr_read_generic, &spr_write_generic, 4471 0x00000000); 4472 /* Quantization registers */ 4473 /* XXX : not implemented */ 4474 spr_register(env, SPR_750_GQR0, "GQR0", 4475 SPR_NOACCESS, SPR_NOACCESS, 4476 &spr_read_generic, &spr_write_generic, 4477 0x00000000); 4478 /* XXX : not implemented */ 4479 spr_register(env, SPR_750_GQR1, "GQR1", 4480 SPR_NOACCESS, SPR_NOACCESS, 4481 &spr_read_generic, &spr_write_generic, 4482 0x00000000); 4483 /* XXX : not implemented */ 4484 spr_register(env, SPR_750_GQR2, "GQR2", 4485 SPR_NOACCESS, SPR_NOACCESS, 4486 &spr_read_generic, &spr_write_generic, 4487 0x00000000); 4488 /* XXX : not implemented */ 4489 spr_register(env, SPR_750_GQR3, "GQR3", 4490 SPR_NOACCESS, SPR_NOACCESS, 4491 &spr_read_generic, &spr_write_generic, 4492 0x00000000); 4493 /* XXX : not implemented */ 4494 spr_register(env, SPR_750_GQR4, "GQR4", 4495 SPR_NOACCESS, SPR_NOACCESS, 4496 &spr_read_generic, &spr_write_generic, 4497 0x00000000); 4498 /* XXX : not implemented */ 4499 spr_register(env, SPR_750_GQR5, "GQR5", 4500 SPR_NOACCESS, SPR_NOACCESS, 4501 &spr_read_generic, &spr_write_generic, 4502 0x00000000); 4503 /* XXX : not implemented */ 4504 spr_register(env, SPR_750_GQR6, "GQR6", 4505 SPR_NOACCESS, SPR_NOACCESS, 4506 &spr_read_generic, &spr_write_generic, 4507 0x00000000); 4508 /* XXX : not implemented */ 4509 spr_register(env, SPR_750_GQR7, "GQR7", 4510 SPR_NOACCESS, SPR_NOACCESS, 4511 &spr_read_generic, &spr_write_generic, 4512 0x00000000); 4513 /* Memory management */ 4514 register_low_BATs(env); 4515 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4516 register_high_BATs(env); 4517 init_excp_750cl(env); 4518 env->dcache_line_size = 32; 4519 env->icache_line_size = 32; 4520 /* Allocate hardware IRQ controller */ 4521 ppc6xx_irq_init(env_archcpu(env)); 4522 } 4523 4524 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4525 { 4526 DeviceClass *dc = DEVICE_CLASS(oc); 4527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4528 4529 dc->desc = "PowerPC 750 CL"; 4530 pcc->init_proc = init_proc_750cl; 4531 pcc->check_pow = check_pow_hid0; 4532 /* 4533 * XXX: not implemented: 4534 * cache lock instructions: 4535 * dcbz_l 4536 * floating point paired instructions 4537 * psq_lux 4538 * psq_lx 4539 * psq_stux 4540 * psq_stx 4541 * ps_abs 4542 * ps_add 4543 * ps_cmpo0 4544 * ps_cmpo1 4545 * ps_cmpu0 4546 * ps_cmpu1 4547 * ps_div 4548 * ps_madd 4549 * ps_madds0 4550 * ps_madds1 4551 * ps_merge00 4552 * ps_merge01 4553 * ps_merge10 4554 * ps_merge11 4555 * ps_mr 4556 * ps_msub 4557 * ps_mul 4558 * ps_muls0 4559 * ps_muls1 4560 * ps_nabs 4561 * ps_neg 4562 * ps_nmadd 4563 * ps_nmsub 4564 * ps_res 4565 * ps_rsqrte 4566 * ps_sel 4567 * ps_sub 4568 * ps_sum0 4569 * ps_sum1 4570 */ 4571 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4572 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4573 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4574 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4575 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4576 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4577 PPC_SEGMENT | PPC_EXTERN; 4578 pcc->msr_mask = (1ull << MSR_POW) | 4579 (1ull << MSR_ILE) | 4580 (1ull << MSR_EE) | 4581 (1ull << MSR_PR) | 4582 (1ull << MSR_FP) | 4583 (1ull << MSR_ME) | 4584 (1ull << MSR_FE0) | 4585 (1ull << MSR_SE) | 4586 (1ull << MSR_DE) | 4587 (1ull << MSR_FE1) | 4588 (1ull << MSR_EP) | 4589 (1ull << MSR_IR) | 4590 (1ull << MSR_DR) | 4591 (1ull << MSR_PMM) | 4592 (1ull << MSR_RI) | 4593 (1ull << MSR_LE); 4594 pcc->mmu_model = POWERPC_MMU_32B; 4595 pcc->excp_model = POWERPC_EXCP_7x0; 4596 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4597 pcc->bfd_mach = bfd_mach_ppc_750; 4598 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4599 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4600 } 4601 4602 static void init_proc_750cx(CPUPPCState *env) 4603 { 4604 register_ne_601_sprs(env); 4605 register_sdr1_sprs(env); 4606 register_7xx_sprs(env); 4607 /* XXX : not implemented */ 4608 spr_register(env, SPR_L2CR, "L2CR", 4609 SPR_NOACCESS, SPR_NOACCESS, 4610 &spr_read_generic, spr_access_nop, 4611 0x00000000); 4612 /* Time base */ 4613 register_tbl(env); 4614 /* Thermal management */ 4615 register_thrm_sprs(env); 4616 /* This register is not implemented but is present for compatibility */ 4617 spr_register(env, SPR_SDA, "SDA", 4618 SPR_NOACCESS, SPR_NOACCESS, 4619 &spr_read_generic, &spr_write_generic, 4620 0x00000000); 4621 /* Hardware implementation registers */ 4622 /* XXX : not implemented */ 4623 spr_register(env, SPR_HID0, "HID0", 4624 SPR_NOACCESS, SPR_NOACCESS, 4625 &spr_read_generic, &spr_write_generic, 4626 0x00000000); 4627 /* XXX : not implemented */ 4628 spr_register(env, SPR_HID1, "HID1", 4629 SPR_NOACCESS, SPR_NOACCESS, 4630 &spr_read_generic, &spr_write_generic, 4631 0x00000000); 4632 /* Memory management */ 4633 register_low_BATs(env); 4634 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4635 register_high_BATs(env); 4636 init_excp_750cx(env); 4637 env->dcache_line_size = 32; 4638 env->icache_line_size = 32; 4639 /* Allocate hardware IRQ controller */ 4640 ppc6xx_irq_init(env_archcpu(env)); 4641 } 4642 4643 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4644 { 4645 DeviceClass *dc = DEVICE_CLASS(oc); 4646 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4647 4648 dc->desc = "PowerPC 750CX"; 4649 pcc->init_proc = init_proc_750cx; 4650 pcc->check_pow = check_pow_hid0; 4651 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4652 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4653 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4654 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4655 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4656 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4657 PPC_SEGMENT | PPC_EXTERN; 4658 pcc->msr_mask = (1ull << MSR_POW) | 4659 (1ull << MSR_ILE) | 4660 (1ull << MSR_EE) | 4661 (1ull << MSR_PR) | 4662 (1ull << MSR_FP) | 4663 (1ull << MSR_ME) | 4664 (1ull << MSR_FE0) | 4665 (1ull << MSR_SE) | 4666 (1ull << MSR_DE) | 4667 (1ull << MSR_FE1) | 4668 (1ull << MSR_EP) | 4669 (1ull << MSR_IR) | 4670 (1ull << MSR_DR) | 4671 (1ull << MSR_PMM) | 4672 (1ull << MSR_RI) | 4673 (1ull << MSR_LE); 4674 pcc->mmu_model = POWERPC_MMU_32B; 4675 pcc->excp_model = POWERPC_EXCP_7x0; 4676 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4677 pcc->bfd_mach = bfd_mach_ppc_750; 4678 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4679 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4680 } 4681 4682 static void init_proc_750fx(CPUPPCState *env) 4683 { 4684 register_ne_601_sprs(env); 4685 register_sdr1_sprs(env); 4686 register_7xx_sprs(env); 4687 /* XXX : not implemented */ 4688 spr_register(env, SPR_L2CR, "L2CR", 4689 SPR_NOACCESS, SPR_NOACCESS, 4690 &spr_read_generic, spr_access_nop, 4691 0x00000000); 4692 /* Time base */ 4693 register_tbl(env); 4694 /* Thermal management */ 4695 register_thrm_sprs(env); 4696 /* XXX : not implemented */ 4697 spr_register(env, SPR_750_THRM4, "THRM4", 4698 SPR_NOACCESS, SPR_NOACCESS, 4699 &spr_read_generic, &spr_write_generic, 4700 0x00000000); 4701 /* Hardware implementation registers */ 4702 /* XXX : not implemented */ 4703 spr_register(env, SPR_HID0, "HID0", 4704 SPR_NOACCESS, SPR_NOACCESS, 4705 &spr_read_generic, &spr_write_generic, 4706 0x00000000); 4707 /* XXX : not implemented */ 4708 spr_register(env, SPR_HID1, "HID1", 4709 SPR_NOACCESS, SPR_NOACCESS, 4710 &spr_read_generic, &spr_write_generic, 4711 0x00000000); 4712 /* XXX : not implemented */ 4713 spr_register(env, SPR_750FX_HID2, "HID2", 4714 SPR_NOACCESS, SPR_NOACCESS, 4715 &spr_read_generic, &spr_write_generic, 4716 0x00000000); 4717 /* Memory management */ 4718 register_low_BATs(env); 4719 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4720 register_high_BATs(env); 4721 init_excp_7x0(env); 4722 env->dcache_line_size = 32; 4723 env->icache_line_size = 32; 4724 /* Allocate hardware IRQ controller */ 4725 ppc6xx_irq_init(env_archcpu(env)); 4726 } 4727 4728 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4729 { 4730 DeviceClass *dc = DEVICE_CLASS(oc); 4731 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4732 4733 dc->desc = "PowerPC 750FX"; 4734 pcc->init_proc = init_proc_750fx; 4735 pcc->check_pow = check_pow_hid0; 4736 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4737 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4738 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4739 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4740 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4741 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4742 PPC_SEGMENT | PPC_EXTERN; 4743 pcc->msr_mask = (1ull << MSR_POW) | 4744 (1ull << MSR_ILE) | 4745 (1ull << MSR_EE) | 4746 (1ull << MSR_PR) | 4747 (1ull << MSR_FP) | 4748 (1ull << MSR_ME) | 4749 (1ull << MSR_FE0) | 4750 (1ull << MSR_SE) | 4751 (1ull << MSR_DE) | 4752 (1ull << MSR_FE1) | 4753 (1ull << MSR_EP) | 4754 (1ull << MSR_IR) | 4755 (1ull << MSR_DR) | 4756 (1ull << MSR_PMM) | 4757 (1ull << MSR_RI) | 4758 (1ull << MSR_LE); 4759 pcc->mmu_model = POWERPC_MMU_32B; 4760 pcc->excp_model = POWERPC_EXCP_7x0; 4761 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4762 pcc->bfd_mach = bfd_mach_ppc_750; 4763 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4764 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4765 } 4766 4767 static void init_proc_750gx(CPUPPCState *env) 4768 { 4769 register_ne_601_sprs(env); 4770 register_sdr1_sprs(env); 4771 register_7xx_sprs(env); 4772 /* XXX : not implemented (XXX: different from 750fx) */ 4773 spr_register(env, SPR_L2CR, "L2CR", 4774 SPR_NOACCESS, SPR_NOACCESS, 4775 &spr_read_generic, spr_access_nop, 4776 0x00000000); 4777 /* Time base */ 4778 register_tbl(env); 4779 /* Thermal management */ 4780 register_thrm_sprs(env); 4781 /* XXX : not implemented */ 4782 spr_register(env, SPR_750_THRM4, "THRM4", 4783 SPR_NOACCESS, SPR_NOACCESS, 4784 &spr_read_generic, &spr_write_generic, 4785 0x00000000); 4786 /* Hardware implementation registers */ 4787 /* XXX : not implemented (XXX: different from 750fx) */ 4788 spr_register(env, SPR_HID0, "HID0", 4789 SPR_NOACCESS, SPR_NOACCESS, 4790 &spr_read_generic, &spr_write_generic, 4791 0x00000000); 4792 /* XXX : not implemented */ 4793 spr_register(env, SPR_HID1, "HID1", 4794 SPR_NOACCESS, SPR_NOACCESS, 4795 &spr_read_generic, &spr_write_generic, 4796 0x00000000); 4797 /* XXX : not implemented (XXX: different from 750fx) */ 4798 spr_register(env, SPR_750FX_HID2, "HID2", 4799 SPR_NOACCESS, SPR_NOACCESS, 4800 &spr_read_generic, &spr_write_generic, 4801 0x00000000); 4802 /* Memory management */ 4803 register_low_BATs(env); 4804 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4805 register_high_BATs(env); 4806 init_excp_7x0(env); 4807 env->dcache_line_size = 32; 4808 env->icache_line_size = 32; 4809 /* Allocate hardware IRQ controller */ 4810 ppc6xx_irq_init(env_archcpu(env)); 4811 } 4812 4813 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4814 { 4815 DeviceClass *dc = DEVICE_CLASS(oc); 4816 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4817 4818 dc->desc = "PowerPC 750GX"; 4819 pcc->init_proc = init_proc_750gx; 4820 pcc->check_pow = check_pow_hid0; 4821 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4822 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4823 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4824 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4825 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4826 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4827 PPC_SEGMENT | PPC_EXTERN; 4828 pcc->msr_mask = (1ull << MSR_POW) | 4829 (1ull << MSR_ILE) | 4830 (1ull << MSR_EE) | 4831 (1ull << MSR_PR) | 4832 (1ull << MSR_FP) | 4833 (1ull << MSR_ME) | 4834 (1ull << MSR_FE0) | 4835 (1ull << MSR_SE) | 4836 (1ull << MSR_DE) | 4837 (1ull << MSR_FE1) | 4838 (1ull << MSR_EP) | 4839 (1ull << MSR_IR) | 4840 (1ull << MSR_DR) | 4841 (1ull << MSR_PMM) | 4842 (1ull << MSR_RI) | 4843 (1ull << MSR_LE); 4844 pcc->mmu_model = POWERPC_MMU_32B; 4845 pcc->excp_model = POWERPC_EXCP_7x0; 4846 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4847 pcc->bfd_mach = bfd_mach_ppc_750; 4848 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4849 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4850 } 4851 4852 static void init_proc_745(CPUPPCState *env) 4853 { 4854 register_ne_601_sprs(env); 4855 register_sdr1_sprs(env); 4856 register_7xx_sprs(env); 4857 register_G2_755_sprs(env); 4858 /* Time base */ 4859 register_tbl(env); 4860 /* Thermal management */ 4861 register_thrm_sprs(env); 4862 /* Hardware implementation registers */ 4863 /* XXX : not implemented */ 4864 spr_register(env, SPR_HID0, "HID0", 4865 SPR_NOACCESS, SPR_NOACCESS, 4866 &spr_read_generic, &spr_write_generic, 4867 0x00000000); 4868 /* XXX : not implemented */ 4869 spr_register(env, SPR_HID1, "HID1", 4870 SPR_NOACCESS, SPR_NOACCESS, 4871 &spr_read_generic, &spr_write_generic, 4872 0x00000000); 4873 /* XXX : not implemented */ 4874 spr_register(env, SPR_HID2, "HID2", 4875 SPR_NOACCESS, SPR_NOACCESS, 4876 &spr_read_generic, &spr_write_generic, 4877 0x00000000); 4878 /* Memory management */ 4879 register_low_BATs(env); 4880 register_high_BATs(env); 4881 register_6xx_7xx_soft_tlb(env, 64, 2); 4882 init_excp_7x5(env); 4883 env->dcache_line_size = 32; 4884 env->icache_line_size = 32; 4885 /* Allocate hardware IRQ controller */ 4886 ppc6xx_irq_init(env_archcpu(env)); 4887 } 4888 4889 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4890 { 4891 DeviceClass *dc = DEVICE_CLASS(oc); 4892 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4893 4894 dc->desc = "PowerPC 745"; 4895 pcc->init_proc = init_proc_745; 4896 pcc->check_pow = check_pow_hid0; 4897 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4898 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4899 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4900 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4901 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4902 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4903 PPC_SEGMENT | PPC_EXTERN; 4904 pcc->msr_mask = (1ull << MSR_POW) | 4905 (1ull << MSR_ILE) | 4906 (1ull << MSR_EE) | 4907 (1ull << MSR_PR) | 4908 (1ull << MSR_FP) | 4909 (1ull << MSR_ME) | 4910 (1ull << MSR_FE0) | 4911 (1ull << MSR_SE) | 4912 (1ull << MSR_DE) | 4913 (1ull << MSR_FE1) | 4914 (1ull << MSR_EP) | 4915 (1ull << MSR_IR) | 4916 (1ull << MSR_DR) | 4917 (1ull << MSR_PMM) | 4918 (1ull << MSR_RI) | 4919 (1ull << MSR_LE); 4920 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4921 pcc->excp_model = POWERPC_EXCP_7x5; 4922 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4923 pcc->bfd_mach = bfd_mach_ppc_750; 4924 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4925 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4926 } 4927 4928 static void init_proc_755(CPUPPCState *env) 4929 { 4930 register_ne_601_sprs(env); 4931 register_sdr1_sprs(env); 4932 register_7xx_sprs(env); 4933 register_G2_755_sprs(env); 4934 /* Time base */ 4935 register_tbl(env); 4936 /* L2 cache control */ 4937 /* XXX : not implemented */ 4938 spr_register(env, SPR_L2CR, "L2CR", 4939 SPR_NOACCESS, SPR_NOACCESS, 4940 &spr_read_generic, spr_access_nop, 4941 0x00000000); 4942 /* XXX : not implemented */ 4943 spr_register(env, SPR_L2PMCR, "L2PMCR", 4944 SPR_NOACCESS, SPR_NOACCESS, 4945 &spr_read_generic, &spr_write_generic, 4946 0x00000000); 4947 /* Thermal management */ 4948 register_thrm_sprs(env); 4949 /* Hardware implementation registers */ 4950 /* XXX : not implemented */ 4951 spr_register(env, SPR_HID0, "HID0", 4952 SPR_NOACCESS, SPR_NOACCESS, 4953 &spr_read_generic, &spr_write_generic, 4954 0x00000000); 4955 /* XXX : not implemented */ 4956 spr_register(env, SPR_HID1, "HID1", 4957 SPR_NOACCESS, SPR_NOACCESS, 4958 &spr_read_generic, &spr_write_generic, 4959 0x00000000); 4960 /* XXX : not implemented */ 4961 spr_register(env, SPR_HID2, "HID2", 4962 SPR_NOACCESS, SPR_NOACCESS, 4963 &spr_read_generic, &spr_write_generic, 4964 0x00000000); 4965 /* Memory management */ 4966 register_low_BATs(env); 4967 register_high_BATs(env); 4968 register_6xx_7xx_soft_tlb(env, 64, 2); 4969 init_excp_7x5(env); 4970 env->dcache_line_size = 32; 4971 env->icache_line_size = 32; 4972 /* Allocate hardware IRQ controller */ 4973 ppc6xx_irq_init(env_archcpu(env)); 4974 } 4975 4976 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4977 { 4978 DeviceClass *dc = DEVICE_CLASS(oc); 4979 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4980 4981 dc->desc = "PowerPC 755"; 4982 pcc->init_proc = init_proc_755; 4983 pcc->check_pow = check_pow_hid0; 4984 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4985 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4986 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4987 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4988 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4990 PPC_SEGMENT | PPC_EXTERN; 4991 pcc->msr_mask = (1ull << MSR_POW) | 4992 (1ull << MSR_ILE) | 4993 (1ull << MSR_EE) | 4994 (1ull << MSR_PR) | 4995 (1ull << MSR_FP) | 4996 (1ull << MSR_ME) | 4997 (1ull << MSR_FE0) | 4998 (1ull << MSR_SE) | 4999 (1ull << MSR_DE) | 5000 (1ull << MSR_FE1) | 5001 (1ull << MSR_EP) | 5002 (1ull << MSR_IR) | 5003 (1ull << MSR_DR) | 5004 (1ull << MSR_PMM) | 5005 (1ull << MSR_RI) | 5006 (1ull << MSR_LE); 5007 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5008 pcc->excp_model = POWERPC_EXCP_7x5; 5009 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5010 pcc->bfd_mach = bfd_mach_ppc_750; 5011 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5012 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5013 } 5014 5015 static void init_proc_7400(CPUPPCState *env) 5016 { 5017 register_ne_601_sprs(env); 5018 register_sdr1_sprs(env); 5019 register_7xx_sprs(env); 5020 /* Time base */ 5021 register_tbl(env); 5022 /* 74xx specific SPR */ 5023 register_74xx_sprs(env); 5024 vscr_init(env, 0x00010000); 5025 /* XXX : not implemented */ 5026 spr_register(env, SPR_UBAMR, "UBAMR", 5027 &spr_read_ureg, SPR_NOACCESS, 5028 &spr_read_ureg, SPR_NOACCESS, 5029 0x00000000); 5030 /* XXX: this seems not implemented on all revisions. */ 5031 /* XXX : not implemented */ 5032 spr_register(env, SPR_MSSCR1, "MSSCR1", 5033 SPR_NOACCESS, SPR_NOACCESS, 5034 &spr_read_generic, &spr_write_generic, 5035 0x00000000); 5036 /* Thermal management */ 5037 register_thrm_sprs(env); 5038 /* Memory management */ 5039 register_low_BATs(env); 5040 init_excp_7400(env); 5041 env->dcache_line_size = 32; 5042 env->icache_line_size = 32; 5043 /* Allocate hardware IRQ controller */ 5044 ppc6xx_irq_init(env_archcpu(env)); 5045 } 5046 5047 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5048 { 5049 DeviceClass *dc = DEVICE_CLASS(oc); 5050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5051 5052 dc->desc = "PowerPC 7400 (aka G4)"; 5053 pcc->init_proc = init_proc_7400; 5054 pcc->check_pow = check_pow_hid0; 5055 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5056 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5057 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5058 PPC_FLOAT_STFIWX | 5059 PPC_CACHE | PPC_CACHE_ICBI | 5060 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5061 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5062 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5063 PPC_MEM_TLBIA | 5064 PPC_SEGMENT | PPC_EXTERN | 5065 PPC_ALTIVEC; 5066 pcc->msr_mask = (1ull << MSR_VR) | 5067 (1ull << MSR_POW) | 5068 (1ull << MSR_ILE) | 5069 (1ull << MSR_EE) | 5070 (1ull << MSR_PR) | 5071 (1ull << MSR_FP) | 5072 (1ull << MSR_ME) | 5073 (1ull << MSR_FE0) | 5074 (1ull << MSR_SE) | 5075 (1ull << MSR_DE) | 5076 (1ull << MSR_FE1) | 5077 (1ull << MSR_EP) | 5078 (1ull << MSR_IR) | 5079 (1ull << MSR_DR) | 5080 (1ull << MSR_PMM) | 5081 (1ull << MSR_RI) | 5082 (1ull << MSR_LE); 5083 pcc->mmu_model = POWERPC_MMU_32B; 5084 pcc->excp_model = POWERPC_EXCP_74xx; 5085 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5086 pcc->bfd_mach = bfd_mach_ppc_7400; 5087 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5088 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5089 POWERPC_FLAG_BUS_CLK; 5090 } 5091 5092 static void init_proc_7410(CPUPPCState *env) 5093 { 5094 register_ne_601_sprs(env); 5095 register_sdr1_sprs(env); 5096 register_7xx_sprs(env); 5097 /* Time base */ 5098 register_tbl(env); 5099 /* 74xx specific SPR */ 5100 register_74xx_sprs(env); 5101 vscr_init(env, 0x00010000); 5102 /* XXX : not implemented */ 5103 spr_register(env, SPR_UBAMR, "UBAMR", 5104 &spr_read_ureg, SPR_NOACCESS, 5105 &spr_read_ureg, SPR_NOACCESS, 5106 0x00000000); 5107 /* Thermal management */ 5108 register_thrm_sprs(env); 5109 /* L2PMCR */ 5110 /* XXX : not implemented */ 5111 spr_register(env, SPR_L2PMCR, "L2PMCR", 5112 SPR_NOACCESS, SPR_NOACCESS, 5113 &spr_read_generic, &spr_write_generic, 5114 0x00000000); 5115 /* LDSTDB */ 5116 /* XXX : not implemented */ 5117 spr_register(env, SPR_LDSTDB, "LDSTDB", 5118 SPR_NOACCESS, SPR_NOACCESS, 5119 &spr_read_generic, &spr_write_generic, 5120 0x00000000); 5121 /* Memory management */ 5122 register_low_BATs(env); 5123 init_excp_7400(env); 5124 env->dcache_line_size = 32; 5125 env->icache_line_size = 32; 5126 /* Allocate hardware IRQ controller */ 5127 ppc6xx_irq_init(env_archcpu(env)); 5128 } 5129 5130 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5131 { 5132 DeviceClass *dc = DEVICE_CLASS(oc); 5133 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5134 5135 dc->desc = "PowerPC 7410 (aka G4)"; 5136 pcc->init_proc = init_proc_7410; 5137 pcc->check_pow = check_pow_hid0; 5138 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5139 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5140 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5141 PPC_FLOAT_STFIWX | 5142 PPC_CACHE | PPC_CACHE_ICBI | 5143 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5144 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5145 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5146 PPC_MEM_TLBIA | 5147 PPC_SEGMENT | PPC_EXTERN | 5148 PPC_ALTIVEC; 5149 pcc->msr_mask = (1ull << MSR_VR) | 5150 (1ull << MSR_POW) | 5151 (1ull << MSR_ILE) | 5152 (1ull << MSR_EE) | 5153 (1ull << MSR_PR) | 5154 (1ull << MSR_FP) | 5155 (1ull << MSR_ME) | 5156 (1ull << MSR_FE0) | 5157 (1ull << MSR_SE) | 5158 (1ull << MSR_DE) | 5159 (1ull << MSR_FE1) | 5160 (1ull << MSR_EP) | 5161 (1ull << MSR_IR) | 5162 (1ull << MSR_DR) | 5163 (1ull << MSR_PMM) | 5164 (1ull << MSR_RI) | 5165 (1ull << MSR_LE); 5166 pcc->mmu_model = POWERPC_MMU_32B; 5167 pcc->excp_model = POWERPC_EXCP_74xx; 5168 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5169 pcc->bfd_mach = bfd_mach_ppc_7400; 5170 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5171 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5172 POWERPC_FLAG_BUS_CLK; 5173 } 5174 5175 static void init_proc_7440(CPUPPCState *env) 5176 { 5177 register_ne_601_sprs(env); 5178 register_sdr1_sprs(env); 5179 register_7xx_sprs(env); 5180 /* Time base */ 5181 register_tbl(env); 5182 /* 74xx specific SPR */ 5183 register_74xx_sprs(env); 5184 vscr_init(env, 0x00010000); 5185 /* XXX : not implemented */ 5186 spr_register(env, SPR_UBAMR, "UBAMR", 5187 &spr_read_ureg, SPR_NOACCESS, 5188 &spr_read_ureg, SPR_NOACCESS, 5189 0x00000000); 5190 /* LDSTCR */ 5191 /* XXX : not implemented */ 5192 spr_register(env, SPR_LDSTCR, "LDSTCR", 5193 SPR_NOACCESS, SPR_NOACCESS, 5194 &spr_read_generic, &spr_write_generic, 5195 0x00000000); 5196 /* ICTRL */ 5197 /* XXX : not implemented */ 5198 spr_register(env, SPR_ICTRL, "ICTRL", 5199 SPR_NOACCESS, SPR_NOACCESS, 5200 &spr_read_generic, &spr_write_generic, 5201 0x00000000); 5202 /* MSSSR0 */ 5203 /* XXX : not implemented */ 5204 spr_register(env, SPR_MSSSR0, "MSSSR0", 5205 SPR_NOACCESS, SPR_NOACCESS, 5206 &spr_read_generic, &spr_write_generic, 5207 0x00000000); 5208 /* PMC */ 5209 /* XXX : not implemented */ 5210 spr_register(env, SPR_7XX_PMC5, "PMC5", 5211 SPR_NOACCESS, SPR_NOACCESS, 5212 &spr_read_generic, &spr_write_generic, 5213 0x00000000); 5214 /* XXX : not implemented */ 5215 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5216 &spr_read_ureg, SPR_NOACCESS, 5217 &spr_read_ureg, SPR_NOACCESS, 5218 0x00000000); 5219 /* XXX : not implemented */ 5220 spr_register(env, SPR_7XX_PMC6, "PMC6", 5221 SPR_NOACCESS, SPR_NOACCESS, 5222 &spr_read_generic, &spr_write_generic, 5223 0x00000000); 5224 /* XXX : not implemented */ 5225 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5226 &spr_read_ureg, SPR_NOACCESS, 5227 &spr_read_ureg, SPR_NOACCESS, 5228 0x00000000); 5229 /* Memory management */ 5230 register_low_BATs(env); 5231 init_excp_7450(env); 5232 env->dcache_line_size = 32; 5233 env->icache_line_size = 32; 5234 /* Allocate hardware IRQ controller */ 5235 ppc6xx_irq_init(env_archcpu(env)); 5236 } 5237 5238 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5239 { 5240 DeviceClass *dc = DEVICE_CLASS(oc); 5241 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5242 5243 dc->desc = "PowerPC 7440 (aka G4)"; 5244 pcc->init_proc = init_proc_7440; 5245 pcc->check_pow = check_pow_hid0_74xx; 5246 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5247 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5248 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5249 PPC_FLOAT_STFIWX | 5250 PPC_CACHE | PPC_CACHE_ICBI | 5251 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5252 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5253 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5254 PPC_MEM_TLBIA | 5255 PPC_SEGMENT | PPC_EXTERN | 5256 PPC_ALTIVEC; 5257 pcc->msr_mask = (1ull << MSR_VR) | 5258 (1ull << MSR_POW) | 5259 (1ull << MSR_ILE) | 5260 (1ull << MSR_EE) | 5261 (1ull << MSR_PR) | 5262 (1ull << MSR_FP) | 5263 (1ull << MSR_ME) | 5264 (1ull << MSR_FE0) | 5265 (1ull << MSR_SE) | 5266 (1ull << MSR_DE) | 5267 (1ull << MSR_FE1) | 5268 (1ull << MSR_EP) | 5269 (1ull << MSR_IR) | 5270 (1ull << MSR_DR) | 5271 (1ull << MSR_PMM) | 5272 (1ull << MSR_RI) | 5273 (1ull << MSR_LE); 5274 pcc->mmu_model = POWERPC_MMU_32B; 5275 pcc->excp_model = POWERPC_EXCP_74xx; 5276 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5277 pcc->bfd_mach = bfd_mach_ppc_7400; 5278 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5279 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5280 POWERPC_FLAG_BUS_CLK; 5281 } 5282 5283 static void init_proc_7450(CPUPPCState *env) 5284 { 5285 register_ne_601_sprs(env); 5286 register_sdr1_sprs(env); 5287 register_7xx_sprs(env); 5288 /* Time base */ 5289 register_tbl(env); 5290 /* 74xx specific SPR */ 5291 register_74xx_sprs(env); 5292 vscr_init(env, 0x00010000); 5293 /* Level 3 cache control */ 5294 register_l3_ctrl(env); 5295 /* L3ITCR1 */ 5296 /* XXX : not implemented */ 5297 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5298 SPR_NOACCESS, SPR_NOACCESS, 5299 &spr_read_generic, &spr_write_generic, 5300 0x00000000); 5301 /* L3ITCR2 */ 5302 /* XXX : not implemented */ 5303 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5304 SPR_NOACCESS, SPR_NOACCESS, 5305 &spr_read_generic, &spr_write_generic, 5306 0x00000000); 5307 /* L3ITCR3 */ 5308 /* XXX : not implemented */ 5309 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5310 SPR_NOACCESS, SPR_NOACCESS, 5311 &spr_read_generic, &spr_write_generic, 5312 0x00000000); 5313 /* L3OHCR */ 5314 /* XXX : not implemented */ 5315 spr_register(env, SPR_L3OHCR, "L3OHCR", 5316 SPR_NOACCESS, SPR_NOACCESS, 5317 &spr_read_generic, &spr_write_generic, 5318 0x00000000); 5319 /* XXX : not implemented */ 5320 spr_register(env, SPR_UBAMR, "UBAMR", 5321 &spr_read_ureg, SPR_NOACCESS, 5322 &spr_read_ureg, SPR_NOACCESS, 5323 0x00000000); 5324 /* LDSTCR */ 5325 /* XXX : not implemented */ 5326 spr_register(env, SPR_LDSTCR, "LDSTCR", 5327 SPR_NOACCESS, SPR_NOACCESS, 5328 &spr_read_generic, &spr_write_generic, 5329 0x00000000); 5330 /* ICTRL */ 5331 /* XXX : not implemented */ 5332 spr_register(env, SPR_ICTRL, "ICTRL", 5333 SPR_NOACCESS, SPR_NOACCESS, 5334 &spr_read_generic, &spr_write_generic, 5335 0x00000000); 5336 /* MSSSR0 */ 5337 /* XXX : not implemented */ 5338 spr_register(env, SPR_MSSSR0, "MSSSR0", 5339 SPR_NOACCESS, SPR_NOACCESS, 5340 &spr_read_generic, &spr_write_generic, 5341 0x00000000); 5342 /* PMC */ 5343 /* XXX : not implemented */ 5344 spr_register(env, SPR_7XX_PMC5, "PMC5", 5345 SPR_NOACCESS, SPR_NOACCESS, 5346 &spr_read_generic, &spr_write_generic, 5347 0x00000000); 5348 /* XXX : not implemented */ 5349 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5350 &spr_read_ureg, SPR_NOACCESS, 5351 &spr_read_ureg, SPR_NOACCESS, 5352 0x00000000); 5353 /* XXX : not implemented */ 5354 spr_register(env, SPR_7XX_PMC6, "PMC6", 5355 SPR_NOACCESS, SPR_NOACCESS, 5356 &spr_read_generic, &spr_write_generic, 5357 0x00000000); 5358 /* XXX : not implemented */ 5359 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5360 &spr_read_ureg, SPR_NOACCESS, 5361 &spr_read_ureg, SPR_NOACCESS, 5362 0x00000000); 5363 /* Memory management */ 5364 register_low_BATs(env); 5365 init_excp_7450(env); 5366 env->dcache_line_size = 32; 5367 env->icache_line_size = 32; 5368 /* Allocate hardware IRQ controller */ 5369 ppc6xx_irq_init(env_archcpu(env)); 5370 } 5371 5372 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5373 { 5374 DeviceClass *dc = DEVICE_CLASS(oc); 5375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5376 5377 dc->desc = "PowerPC 7450 (aka G4)"; 5378 pcc->init_proc = init_proc_7450; 5379 pcc->check_pow = check_pow_hid0_74xx; 5380 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5382 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5383 PPC_FLOAT_STFIWX | 5384 PPC_CACHE | PPC_CACHE_ICBI | 5385 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5386 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5387 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5388 PPC_MEM_TLBIA | 5389 PPC_SEGMENT | PPC_EXTERN | 5390 PPC_ALTIVEC; 5391 pcc->msr_mask = (1ull << MSR_VR) | 5392 (1ull << MSR_POW) | 5393 (1ull << MSR_ILE) | 5394 (1ull << MSR_EE) | 5395 (1ull << MSR_PR) | 5396 (1ull << MSR_FP) | 5397 (1ull << MSR_ME) | 5398 (1ull << MSR_FE0) | 5399 (1ull << MSR_SE) | 5400 (1ull << MSR_DE) | 5401 (1ull << MSR_FE1) | 5402 (1ull << MSR_EP) | 5403 (1ull << MSR_IR) | 5404 (1ull << MSR_DR) | 5405 (1ull << MSR_PMM) | 5406 (1ull << MSR_RI) | 5407 (1ull << MSR_LE); 5408 pcc->mmu_model = POWERPC_MMU_32B; 5409 pcc->excp_model = POWERPC_EXCP_74xx; 5410 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5411 pcc->bfd_mach = bfd_mach_ppc_7400; 5412 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5413 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5414 POWERPC_FLAG_BUS_CLK; 5415 } 5416 5417 static void init_proc_7445(CPUPPCState *env) 5418 { 5419 register_ne_601_sprs(env); 5420 register_sdr1_sprs(env); 5421 register_7xx_sprs(env); 5422 /* Time base */ 5423 register_tbl(env); 5424 /* 74xx specific SPR */ 5425 register_74xx_sprs(env); 5426 vscr_init(env, 0x00010000); 5427 /* LDSTCR */ 5428 /* XXX : not implemented */ 5429 spr_register(env, SPR_LDSTCR, "LDSTCR", 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_generic, &spr_write_generic, 5432 0x00000000); 5433 /* ICTRL */ 5434 /* XXX : not implemented */ 5435 spr_register(env, SPR_ICTRL, "ICTRL", 5436 SPR_NOACCESS, SPR_NOACCESS, 5437 &spr_read_generic, &spr_write_generic, 5438 0x00000000); 5439 /* MSSSR0 */ 5440 /* XXX : not implemented */ 5441 spr_register(env, SPR_MSSSR0, "MSSSR0", 5442 SPR_NOACCESS, SPR_NOACCESS, 5443 &spr_read_generic, &spr_write_generic, 5444 0x00000000); 5445 /* PMC */ 5446 /* XXX : not implemented */ 5447 spr_register(env, SPR_7XX_PMC5, "PMC5", 5448 SPR_NOACCESS, SPR_NOACCESS, 5449 &spr_read_generic, &spr_write_generic, 5450 0x00000000); 5451 /* XXX : not implemented */ 5452 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5453 &spr_read_ureg, SPR_NOACCESS, 5454 &spr_read_ureg, SPR_NOACCESS, 5455 0x00000000); 5456 /* XXX : not implemented */ 5457 spr_register(env, SPR_7XX_PMC6, "PMC6", 5458 SPR_NOACCESS, SPR_NOACCESS, 5459 &spr_read_generic, &spr_write_generic, 5460 0x00000000); 5461 /* XXX : not implemented */ 5462 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5463 &spr_read_ureg, SPR_NOACCESS, 5464 &spr_read_ureg, SPR_NOACCESS, 5465 0x00000000); 5466 /* SPRGs */ 5467 spr_register(env, SPR_SPRG4, "SPRG4", 5468 SPR_NOACCESS, SPR_NOACCESS, 5469 &spr_read_generic, &spr_write_generic, 5470 0x00000000); 5471 spr_register(env, SPR_USPRG4, "USPRG4", 5472 &spr_read_ureg, SPR_NOACCESS, 5473 &spr_read_ureg, SPR_NOACCESS, 5474 0x00000000); 5475 spr_register(env, SPR_SPRG5, "SPRG5", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 &spr_read_generic, &spr_write_generic, 5478 0x00000000); 5479 spr_register(env, SPR_USPRG5, "USPRG5", 5480 &spr_read_ureg, SPR_NOACCESS, 5481 &spr_read_ureg, SPR_NOACCESS, 5482 0x00000000); 5483 spr_register(env, SPR_SPRG6, "SPRG6", 5484 SPR_NOACCESS, SPR_NOACCESS, 5485 &spr_read_generic, &spr_write_generic, 5486 0x00000000); 5487 spr_register(env, SPR_USPRG6, "USPRG6", 5488 &spr_read_ureg, SPR_NOACCESS, 5489 &spr_read_ureg, SPR_NOACCESS, 5490 0x00000000); 5491 spr_register(env, SPR_SPRG7, "SPRG7", 5492 SPR_NOACCESS, SPR_NOACCESS, 5493 &spr_read_generic, &spr_write_generic, 5494 0x00000000); 5495 spr_register(env, SPR_USPRG7, "USPRG7", 5496 &spr_read_ureg, SPR_NOACCESS, 5497 &spr_read_ureg, SPR_NOACCESS, 5498 0x00000000); 5499 /* Memory management */ 5500 register_low_BATs(env); 5501 register_high_BATs(env); 5502 init_excp_7450(env); 5503 env->dcache_line_size = 32; 5504 env->icache_line_size = 32; 5505 /* Allocate hardware IRQ controller */ 5506 ppc6xx_irq_init(env_archcpu(env)); 5507 } 5508 5509 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5510 { 5511 DeviceClass *dc = DEVICE_CLASS(oc); 5512 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5513 5514 dc->desc = "PowerPC 7445 (aka G4)"; 5515 pcc->init_proc = init_proc_7445; 5516 pcc->check_pow = check_pow_hid0_74xx; 5517 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5518 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5519 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5520 PPC_FLOAT_STFIWX | 5521 PPC_CACHE | PPC_CACHE_ICBI | 5522 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5523 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5524 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5525 PPC_MEM_TLBIA | 5526 PPC_SEGMENT | PPC_EXTERN | 5527 PPC_ALTIVEC; 5528 pcc->msr_mask = (1ull << MSR_VR) | 5529 (1ull << MSR_POW) | 5530 (1ull << MSR_ILE) | 5531 (1ull << MSR_EE) | 5532 (1ull << MSR_PR) | 5533 (1ull << MSR_FP) | 5534 (1ull << MSR_ME) | 5535 (1ull << MSR_FE0) | 5536 (1ull << MSR_SE) | 5537 (1ull << MSR_DE) | 5538 (1ull << MSR_FE1) | 5539 (1ull << MSR_EP) | 5540 (1ull << MSR_IR) | 5541 (1ull << MSR_DR) | 5542 (1ull << MSR_PMM) | 5543 (1ull << MSR_RI) | 5544 (1ull << MSR_LE); 5545 pcc->mmu_model = POWERPC_MMU_32B; 5546 pcc->excp_model = POWERPC_EXCP_74xx; 5547 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5548 pcc->bfd_mach = bfd_mach_ppc_7400; 5549 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5550 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5551 POWERPC_FLAG_BUS_CLK; 5552 } 5553 5554 static void init_proc_7455(CPUPPCState *env) 5555 { 5556 register_ne_601_sprs(env); 5557 register_sdr1_sprs(env); 5558 register_7xx_sprs(env); 5559 /* Time base */ 5560 register_tbl(env); 5561 /* 74xx specific SPR */ 5562 register_74xx_sprs(env); 5563 vscr_init(env, 0x00010000); 5564 /* Level 3 cache control */ 5565 register_l3_ctrl(env); 5566 /* LDSTCR */ 5567 /* XXX : not implemented */ 5568 spr_register(env, SPR_LDSTCR, "LDSTCR", 5569 SPR_NOACCESS, SPR_NOACCESS, 5570 &spr_read_generic, &spr_write_generic, 5571 0x00000000); 5572 /* ICTRL */ 5573 /* XXX : not implemented */ 5574 spr_register(env, SPR_ICTRL, "ICTRL", 5575 SPR_NOACCESS, SPR_NOACCESS, 5576 &spr_read_generic, &spr_write_generic, 5577 0x00000000); 5578 /* MSSSR0 */ 5579 /* XXX : not implemented */ 5580 spr_register(env, SPR_MSSSR0, "MSSSR0", 5581 SPR_NOACCESS, SPR_NOACCESS, 5582 &spr_read_generic, &spr_write_generic, 5583 0x00000000); 5584 /* PMC */ 5585 /* XXX : not implemented */ 5586 spr_register(env, SPR_7XX_PMC5, "PMC5", 5587 SPR_NOACCESS, SPR_NOACCESS, 5588 &spr_read_generic, &spr_write_generic, 5589 0x00000000); 5590 /* XXX : not implemented */ 5591 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5592 &spr_read_ureg, SPR_NOACCESS, 5593 &spr_read_ureg, SPR_NOACCESS, 5594 0x00000000); 5595 /* XXX : not implemented */ 5596 spr_register(env, SPR_7XX_PMC6, "PMC6", 5597 SPR_NOACCESS, SPR_NOACCESS, 5598 &spr_read_generic, &spr_write_generic, 5599 0x00000000); 5600 /* XXX : not implemented */ 5601 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5602 &spr_read_ureg, SPR_NOACCESS, 5603 &spr_read_ureg, SPR_NOACCESS, 5604 0x00000000); 5605 /* SPRGs */ 5606 spr_register(env, SPR_SPRG4, "SPRG4", 5607 SPR_NOACCESS, SPR_NOACCESS, 5608 &spr_read_generic, &spr_write_generic, 5609 0x00000000); 5610 spr_register(env, SPR_USPRG4, "USPRG4", 5611 &spr_read_ureg, SPR_NOACCESS, 5612 &spr_read_ureg, SPR_NOACCESS, 5613 0x00000000); 5614 spr_register(env, SPR_SPRG5, "SPRG5", 5615 SPR_NOACCESS, SPR_NOACCESS, 5616 &spr_read_generic, &spr_write_generic, 5617 0x00000000); 5618 spr_register(env, SPR_USPRG5, "USPRG5", 5619 &spr_read_ureg, SPR_NOACCESS, 5620 &spr_read_ureg, SPR_NOACCESS, 5621 0x00000000); 5622 spr_register(env, SPR_SPRG6, "SPRG6", 5623 SPR_NOACCESS, SPR_NOACCESS, 5624 &spr_read_generic, &spr_write_generic, 5625 0x00000000); 5626 spr_register(env, SPR_USPRG6, "USPRG6", 5627 &spr_read_ureg, SPR_NOACCESS, 5628 &spr_read_ureg, SPR_NOACCESS, 5629 0x00000000); 5630 spr_register(env, SPR_SPRG7, "SPRG7", 5631 SPR_NOACCESS, SPR_NOACCESS, 5632 &spr_read_generic, &spr_write_generic, 5633 0x00000000); 5634 spr_register(env, SPR_USPRG7, "USPRG7", 5635 &spr_read_ureg, SPR_NOACCESS, 5636 &spr_read_ureg, SPR_NOACCESS, 5637 0x00000000); 5638 /* Memory management */ 5639 register_low_BATs(env); 5640 register_high_BATs(env); 5641 init_excp_7450(env); 5642 env->dcache_line_size = 32; 5643 env->icache_line_size = 32; 5644 /* Allocate hardware IRQ controller */ 5645 ppc6xx_irq_init(env_archcpu(env)); 5646 } 5647 5648 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5649 { 5650 DeviceClass *dc = DEVICE_CLASS(oc); 5651 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5652 5653 dc->desc = "PowerPC 7455 (aka G4)"; 5654 pcc->init_proc = init_proc_7455; 5655 pcc->check_pow = check_pow_hid0_74xx; 5656 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5657 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5658 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5659 PPC_FLOAT_STFIWX | 5660 PPC_CACHE | PPC_CACHE_ICBI | 5661 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5662 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5663 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5664 PPC_MEM_TLBIA | 5665 PPC_SEGMENT | PPC_EXTERN | 5666 PPC_ALTIVEC; 5667 pcc->msr_mask = (1ull << MSR_VR) | 5668 (1ull << MSR_POW) | 5669 (1ull << MSR_ILE) | 5670 (1ull << MSR_EE) | 5671 (1ull << MSR_PR) | 5672 (1ull << MSR_FP) | 5673 (1ull << MSR_ME) | 5674 (1ull << MSR_FE0) | 5675 (1ull << MSR_SE) | 5676 (1ull << MSR_DE) | 5677 (1ull << MSR_FE1) | 5678 (1ull << MSR_EP) | 5679 (1ull << MSR_IR) | 5680 (1ull << MSR_DR) | 5681 (1ull << MSR_PMM) | 5682 (1ull << MSR_RI) | 5683 (1ull << MSR_LE); 5684 pcc->mmu_model = POWERPC_MMU_32B; 5685 pcc->excp_model = POWERPC_EXCP_74xx; 5686 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5687 pcc->bfd_mach = bfd_mach_ppc_7400; 5688 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5689 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5690 POWERPC_FLAG_BUS_CLK; 5691 } 5692 5693 static void init_proc_7457(CPUPPCState *env) 5694 { 5695 register_ne_601_sprs(env); 5696 register_sdr1_sprs(env); 5697 register_7xx_sprs(env); 5698 /* Time base */ 5699 register_tbl(env); 5700 /* 74xx specific SPR */ 5701 register_74xx_sprs(env); 5702 vscr_init(env, 0x00010000); 5703 /* Level 3 cache control */ 5704 register_l3_ctrl(env); 5705 /* L3ITCR1 */ 5706 /* XXX : not implemented */ 5707 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5708 SPR_NOACCESS, SPR_NOACCESS, 5709 &spr_read_generic, &spr_write_generic, 5710 0x00000000); 5711 /* L3ITCR2 */ 5712 /* XXX : not implemented */ 5713 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 &spr_read_generic, &spr_write_generic, 5716 0x00000000); 5717 /* L3ITCR3 */ 5718 /* XXX : not implemented */ 5719 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_generic, &spr_write_generic, 5722 0x00000000); 5723 /* L3OHCR */ 5724 /* XXX : not implemented */ 5725 spr_register(env, SPR_L3OHCR, "L3OHCR", 5726 SPR_NOACCESS, SPR_NOACCESS, 5727 &spr_read_generic, &spr_write_generic, 5728 0x00000000); 5729 /* LDSTCR */ 5730 /* XXX : not implemented */ 5731 spr_register(env, SPR_LDSTCR, "LDSTCR", 5732 SPR_NOACCESS, SPR_NOACCESS, 5733 &spr_read_generic, &spr_write_generic, 5734 0x00000000); 5735 /* ICTRL */ 5736 /* XXX : not implemented */ 5737 spr_register(env, SPR_ICTRL, "ICTRL", 5738 SPR_NOACCESS, SPR_NOACCESS, 5739 &spr_read_generic, &spr_write_generic, 5740 0x00000000); 5741 /* MSSSR0 */ 5742 /* XXX : not implemented */ 5743 spr_register(env, SPR_MSSSR0, "MSSSR0", 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_read_generic, &spr_write_generic, 5746 0x00000000); 5747 /* PMC */ 5748 /* XXX : not implemented */ 5749 spr_register(env, SPR_7XX_PMC5, "PMC5", 5750 SPR_NOACCESS, SPR_NOACCESS, 5751 &spr_read_generic, &spr_write_generic, 5752 0x00000000); 5753 /* XXX : not implemented */ 5754 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5755 &spr_read_ureg, SPR_NOACCESS, 5756 &spr_read_ureg, SPR_NOACCESS, 5757 0x00000000); 5758 /* XXX : not implemented */ 5759 spr_register(env, SPR_7XX_PMC6, "PMC6", 5760 SPR_NOACCESS, SPR_NOACCESS, 5761 &spr_read_generic, &spr_write_generic, 5762 0x00000000); 5763 /* XXX : not implemented */ 5764 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5765 &spr_read_ureg, SPR_NOACCESS, 5766 &spr_read_ureg, SPR_NOACCESS, 5767 0x00000000); 5768 /* SPRGs */ 5769 spr_register(env, SPR_SPRG4, "SPRG4", 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_generic, &spr_write_generic, 5772 0x00000000); 5773 spr_register(env, SPR_USPRG4, "USPRG4", 5774 &spr_read_ureg, SPR_NOACCESS, 5775 &spr_read_ureg, SPR_NOACCESS, 5776 0x00000000); 5777 spr_register(env, SPR_SPRG5, "SPRG5", 5778 SPR_NOACCESS, SPR_NOACCESS, 5779 &spr_read_generic, &spr_write_generic, 5780 0x00000000); 5781 spr_register(env, SPR_USPRG5, "USPRG5", 5782 &spr_read_ureg, SPR_NOACCESS, 5783 &spr_read_ureg, SPR_NOACCESS, 5784 0x00000000); 5785 spr_register(env, SPR_SPRG6, "SPRG6", 5786 SPR_NOACCESS, SPR_NOACCESS, 5787 &spr_read_generic, &spr_write_generic, 5788 0x00000000); 5789 spr_register(env, SPR_USPRG6, "USPRG6", 5790 &spr_read_ureg, SPR_NOACCESS, 5791 &spr_read_ureg, SPR_NOACCESS, 5792 0x00000000); 5793 spr_register(env, SPR_SPRG7, "SPRG7", 5794 SPR_NOACCESS, SPR_NOACCESS, 5795 &spr_read_generic, &spr_write_generic, 5796 0x00000000); 5797 spr_register(env, SPR_USPRG7, "USPRG7", 5798 &spr_read_ureg, SPR_NOACCESS, 5799 &spr_read_ureg, SPR_NOACCESS, 5800 0x00000000); 5801 /* Memory management */ 5802 register_low_BATs(env); 5803 register_high_BATs(env); 5804 init_excp_7450(env); 5805 env->dcache_line_size = 32; 5806 env->icache_line_size = 32; 5807 /* Allocate hardware IRQ controller */ 5808 ppc6xx_irq_init(env_archcpu(env)); 5809 } 5810 5811 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5812 { 5813 DeviceClass *dc = DEVICE_CLASS(oc); 5814 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5815 5816 dc->desc = "PowerPC 7457 (aka G4)"; 5817 pcc->init_proc = init_proc_7457; 5818 pcc->check_pow = check_pow_hid0_74xx; 5819 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5820 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5821 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5822 PPC_FLOAT_STFIWX | 5823 PPC_CACHE | PPC_CACHE_ICBI | 5824 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5825 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5826 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5827 PPC_MEM_TLBIA | 5828 PPC_SEGMENT | PPC_EXTERN | 5829 PPC_ALTIVEC; 5830 pcc->msr_mask = (1ull << MSR_VR) | 5831 (1ull << MSR_POW) | 5832 (1ull << MSR_ILE) | 5833 (1ull << MSR_EE) | 5834 (1ull << MSR_PR) | 5835 (1ull << MSR_FP) | 5836 (1ull << MSR_ME) | 5837 (1ull << MSR_FE0) | 5838 (1ull << MSR_SE) | 5839 (1ull << MSR_DE) | 5840 (1ull << MSR_FE1) | 5841 (1ull << MSR_EP) | 5842 (1ull << MSR_IR) | 5843 (1ull << MSR_DR) | 5844 (1ull << MSR_PMM) | 5845 (1ull << MSR_RI) | 5846 (1ull << MSR_LE); 5847 pcc->mmu_model = POWERPC_MMU_32B; 5848 pcc->excp_model = POWERPC_EXCP_74xx; 5849 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5850 pcc->bfd_mach = bfd_mach_ppc_7400; 5851 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5852 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5853 POWERPC_FLAG_BUS_CLK; 5854 } 5855 5856 static void init_proc_e600(CPUPPCState *env) 5857 { 5858 register_ne_601_sprs(env); 5859 register_sdr1_sprs(env); 5860 register_7xx_sprs(env); 5861 /* Time base */ 5862 register_tbl(env); 5863 /* 74xx specific SPR */ 5864 register_74xx_sprs(env); 5865 vscr_init(env, 0x00010000); 5866 /* XXX : not implemented */ 5867 spr_register(env, SPR_UBAMR, "UBAMR", 5868 &spr_read_ureg, SPR_NOACCESS, 5869 &spr_read_ureg, SPR_NOACCESS, 5870 0x00000000); 5871 /* XXX : not implemented */ 5872 spr_register(env, SPR_LDSTCR, "LDSTCR", 5873 SPR_NOACCESS, SPR_NOACCESS, 5874 &spr_read_generic, &spr_write_generic, 5875 0x00000000); 5876 /* XXX : not implemented */ 5877 spr_register(env, SPR_ICTRL, "ICTRL", 5878 SPR_NOACCESS, SPR_NOACCESS, 5879 &spr_read_generic, &spr_write_generic, 5880 0x00000000); 5881 /* XXX : not implemented */ 5882 spr_register(env, SPR_MSSSR0, "MSSSR0", 5883 SPR_NOACCESS, SPR_NOACCESS, 5884 &spr_read_generic, &spr_write_generic, 5885 0x00000000); 5886 /* XXX : not implemented */ 5887 spr_register(env, SPR_7XX_PMC5, "PMC5", 5888 SPR_NOACCESS, SPR_NOACCESS, 5889 &spr_read_generic, &spr_write_generic, 5890 0x00000000); 5891 /* XXX : not implemented */ 5892 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5893 &spr_read_ureg, SPR_NOACCESS, 5894 &spr_read_ureg, SPR_NOACCESS, 5895 0x00000000); 5896 /* XXX : not implemented */ 5897 spr_register(env, SPR_7XX_PMC6, "PMC6", 5898 SPR_NOACCESS, SPR_NOACCESS, 5899 &spr_read_generic, &spr_write_generic, 5900 0x00000000); 5901 /* XXX : not implemented */ 5902 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5903 &spr_read_ureg, SPR_NOACCESS, 5904 &spr_read_ureg, SPR_NOACCESS, 5905 0x00000000); 5906 /* SPRGs */ 5907 spr_register(env, SPR_SPRG4, "SPRG4", 5908 SPR_NOACCESS, SPR_NOACCESS, 5909 &spr_read_generic, &spr_write_generic, 5910 0x00000000); 5911 spr_register(env, SPR_USPRG4, "USPRG4", 5912 &spr_read_ureg, SPR_NOACCESS, 5913 &spr_read_ureg, SPR_NOACCESS, 5914 0x00000000); 5915 spr_register(env, SPR_SPRG5, "SPRG5", 5916 SPR_NOACCESS, SPR_NOACCESS, 5917 &spr_read_generic, &spr_write_generic, 5918 0x00000000); 5919 spr_register(env, SPR_USPRG5, "USPRG5", 5920 &spr_read_ureg, SPR_NOACCESS, 5921 &spr_read_ureg, SPR_NOACCESS, 5922 0x00000000); 5923 spr_register(env, SPR_SPRG6, "SPRG6", 5924 SPR_NOACCESS, SPR_NOACCESS, 5925 &spr_read_generic, &spr_write_generic, 5926 0x00000000); 5927 spr_register(env, SPR_USPRG6, "USPRG6", 5928 &spr_read_ureg, SPR_NOACCESS, 5929 &spr_read_ureg, SPR_NOACCESS, 5930 0x00000000); 5931 spr_register(env, SPR_SPRG7, "SPRG7", 5932 SPR_NOACCESS, SPR_NOACCESS, 5933 &spr_read_generic, &spr_write_generic, 5934 0x00000000); 5935 spr_register(env, SPR_USPRG7, "USPRG7", 5936 &spr_read_ureg, SPR_NOACCESS, 5937 &spr_read_ureg, SPR_NOACCESS, 5938 0x00000000); 5939 /* Memory management */ 5940 register_low_BATs(env); 5941 register_high_BATs(env); 5942 init_excp_7450(env); 5943 env->dcache_line_size = 32; 5944 env->icache_line_size = 32; 5945 /* Allocate hardware IRQ controller */ 5946 ppc6xx_irq_init(env_archcpu(env)); 5947 } 5948 5949 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5950 { 5951 DeviceClass *dc = DEVICE_CLASS(oc); 5952 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5953 5954 dc->desc = "PowerPC e600"; 5955 pcc->init_proc = init_proc_e600; 5956 pcc->check_pow = check_pow_hid0_74xx; 5957 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5958 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5959 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5960 PPC_FLOAT_STFIWX | 5961 PPC_CACHE | PPC_CACHE_ICBI | 5962 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5963 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5965 PPC_MEM_TLBIA | 5966 PPC_SEGMENT | PPC_EXTERN | 5967 PPC_ALTIVEC; 5968 pcc->insns_flags2 = PPC_NONE; 5969 pcc->msr_mask = (1ull << MSR_VR) | 5970 (1ull << MSR_POW) | 5971 (1ull << MSR_ILE) | 5972 (1ull << MSR_EE) | 5973 (1ull << MSR_PR) | 5974 (1ull << MSR_FP) | 5975 (1ull << MSR_ME) | 5976 (1ull << MSR_FE0) | 5977 (1ull << MSR_SE) | 5978 (1ull << MSR_DE) | 5979 (1ull << MSR_FE1) | 5980 (1ull << MSR_EP) | 5981 (1ull << MSR_IR) | 5982 (1ull << MSR_DR) | 5983 (1ull << MSR_PMM) | 5984 (1ull << MSR_RI) | 5985 (1ull << MSR_LE); 5986 pcc->mmu_model = POWERPC_MMU_32B; 5987 pcc->excp_model = POWERPC_EXCP_74xx; 5988 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5989 pcc->bfd_mach = bfd_mach_ppc_7400; 5990 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5991 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5992 POWERPC_FLAG_BUS_CLK; 5993 } 5994 5995 #if defined(TARGET_PPC64) 5996 #if defined(CONFIG_USER_ONLY) 5997 #define POWERPC970_HID5_INIT 0x00000080 5998 #else 5999 #define POWERPC970_HID5_INIT 0x00000000 6000 #endif 6001 6002 static int check_pow_970(CPUPPCState *env) 6003 { 6004 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6005 return 1; 6006 } 6007 6008 return 0; 6009 } 6010 6011 static void register_970_hid_sprs(CPUPPCState *env) 6012 { 6013 /* Hardware implementation registers */ 6014 /* XXX : not implemented */ 6015 spr_register(env, SPR_HID0, "HID0", 6016 SPR_NOACCESS, SPR_NOACCESS, 6017 &spr_read_generic, &spr_write_clear, 6018 0x60000000); 6019 spr_register(env, SPR_HID1, "HID1", 6020 SPR_NOACCESS, SPR_NOACCESS, 6021 &spr_read_generic, &spr_write_generic, 6022 0x00000000); 6023 spr_register(env, SPR_970_HID5, "HID5", 6024 SPR_NOACCESS, SPR_NOACCESS, 6025 &spr_read_generic, &spr_write_generic, 6026 POWERPC970_HID5_INIT); 6027 } 6028 6029 static void register_970_hior_sprs(CPUPPCState *env) 6030 { 6031 spr_register(env, SPR_HIOR, "SPR_HIOR", 6032 SPR_NOACCESS, SPR_NOACCESS, 6033 &spr_read_hior, &spr_write_hior, 6034 0x00000000); 6035 } 6036 6037 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6038 { 6039 spr_register(env, SPR_CTRL, "SPR_CTRL", 6040 SPR_NOACCESS, SPR_NOACCESS, 6041 SPR_NOACCESS, &spr_write_CTRL, 6042 0x00000000); 6043 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6044 &spr_read_ureg, SPR_NOACCESS, 6045 &spr_read_ureg, SPR_NOACCESS, 6046 0x00000000); 6047 } 6048 6049 static void register_book3s_altivec_sprs(CPUPPCState *env) 6050 { 6051 if (!(env->insns_flags & PPC_ALTIVEC)) { 6052 return; 6053 } 6054 6055 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6056 &spr_read_generic, &spr_write_generic, 6057 &spr_read_generic, &spr_write_generic, 6058 KVM_REG_PPC_VRSAVE, 0x00000000); 6059 6060 } 6061 6062 static void register_book3s_dbg_sprs(CPUPPCState *env) 6063 { 6064 /* 6065 * TODO: different specs define different scopes for these, 6066 * will have to address this: 6067 * 970: super/write and super/read 6068 * powerisa 2.03..2.04: hypv/write and super/read. 6069 * powerisa 2.05 and newer: hypv/write and hypv/read. 6070 */ 6071 spr_register_kvm(env, SPR_DABR, "DABR", 6072 SPR_NOACCESS, SPR_NOACCESS, 6073 &spr_read_generic, &spr_write_generic, 6074 KVM_REG_PPC_DABR, 0x00000000); 6075 spr_register_kvm(env, SPR_DABRX, "DABRX", 6076 SPR_NOACCESS, SPR_NOACCESS, 6077 &spr_read_generic, &spr_write_generic, 6078 KVM_REG_PPC_DABRX, 0x00000000); 6079 } 6080 6081 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6082 { 6083 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6084 SPR_NOACCESS, SPR_NOACCESS, 6085 SPR_NOACCESS, SPR_NOACCESS, 6086 &spr_read_generic, &spr_write_generic, 6087 KVM_REG_PPC_DAWR, 0x00000000); 6088 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6089 SPR_NOACCESS, SPR_NOACCESS, 6090 SPR_NOACCESS, SPR_NOACCESS, 6091 &spr_read_generic, &spr_write_generic, 6092 KVM_REG_PPC_DAWRX, 0x00000000); 6093 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6094 SPR_NOACCESS, SPR_NOACCESS, 6095 SPR_NOACCESS, SPR_NOACCESS, 6096 &spr_read_generic, &spr_write_generic, 6097 KVM_REG_PPC_CIABR, 0x00000000); 6098 } 6099 6100 static void register_970_dbg_sprs(CPUPPCState *env) 6101 { 6102 /* Breakpoints */ 6103 spr_register(env, SPR_IABR, "IABR", 6104 SPR_NOACCESS, SPR_NOACCESS, 6105 &spr_read_generic, &spr_write_generic, 6106 0x00000000); 6107 } 6108 6109 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6110 { 6111 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6112 SPR_NOACCESS, SPR_NOACCESS, 6113 &spr_read_generic, &spr_write_MMCR0, 6114 KVM_REG_PPC_MMCR0, 0x80000000); 6115 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6116 SPR_NOACCESS, SPR_NOACCESS, 6117 &spr_read_generic, &spr_write_MMCR1, 6118 KVM_REG_PPC_MMCR1, 0x00000000); 6119 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6120 SPR_NOACCESS, SPR_NOACCESS, 6121 &spr_read_generic, &spr_write_generic, 6122 KVM_REG_PPC_MMCRA, 0x00000000); 6123 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6124 SPR_NOACCESS, SPR_NOACCESS, 6125 &spr_read_PMC, &spr_write_PMC, 6126 KVM_REG_PPC_PMC1, 0x00000000); 6127 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6128 SPR_NOACCESS, SPR_NOACCESS, 6129 &spr_read_PMC, &spr_write_PMC, 6130 KVM_REG_PPC_PMC2, 0x00000000); 6131 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6132 SPR_NOACCESS, SPR_NOACCESS, 6133 &spr_read_PMC, &spr_write_PMC, 6134 KVM_REG_PPC_PMC3, 0x00000000); 6135 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6136 SPR_NOACCESS, SPR_NOACCESS, 6137 &spr_read_PMC, &spr_write_PMC, 6138 KVM_REG_PPC_PMC4, 0x00000000); 6139 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6140 SPR_NOACCESS, SPR_NOACCESS, 6141 &spr_read_PMC, &spr_write_PMC, 6142 KVM_REG_PPC_PMC5, 0x00000000); 6143 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6144 SPR_NOACCESS, SPR_NOACCESS, 6145 &spr_read_PMC, &spr_write_PMC, 6146 KVM_REG_PPC_PMC6, 0x00000000); 6147 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6148 SPR_NOACCESS, SPR_NOACCESS, 6149 &spr_read_generic, &spr_write_generic, 6150 KVM_REG_PPC_SIAR, 0x00000000); 6151 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6152 SPR_NOACCESS, SPR_NOACCESS, 6153 &spr_read_generic, &spr_write_generic, 6154 KVM_REG_PPC_SDAR, 0x00000000); 6155 } 6156 6157 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6158 { 6159 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6160 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 6161 &spr_read_ureg, &spr_write_ureg, 6162 0x80000000); 6163 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6164 &spr_read_ureg, SPR_NOACCESS, 6165 &spr_read_ureg, &spr_write_ureg, 6166 0x00000000); 6167 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6168 &spr_read_ureg, SPR_NOACCESS, 6169 &spr_read_ureg, &spr_write_ureg, 6170 0x00000000); 6171 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6172 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6173 &spr_read_ureg, &spr_write_ureg, 6174 0x00000000); 6175 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6176 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6177 &spr_read_ureg, &spr_write_ureg, 6178 0x00000000); 6179 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6180 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6181 &spr_read_ureg, &spr_write_ureg, 6182 0x00000000); 6183 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6184 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6185 &spr_read_ureg, &spr_write_ureg, 6186 0x00000000); 6187 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6188 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6189 &spr_read_ureg, &spr_write_ureg, 6190 0x00000000); 6191 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6192 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6193 &spr_read_ureg, &spr_write_ureg, 6194 0x00000000); 6195 spr_register(env, SPR_POWER_USIAR, "USIAR", 6196 &spr_read_ureg, SPR_NOACCESS, 6197 &spr_read_ureg, &spr_write_ureg, 6198 0x00000000); 6199 spr_register(env, SPR_POWER_USDAR, "USDAR", 6200 &spr_read_ureg, SPR_NOACCESS, 6201 &spr_read_ureg, &spr_write_ureg, 6202 0x00000000); 6203 } 6204 6205 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6206 { 6207 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6208 SPR_NOACCESS, SPR_NOACCESS, 6209 &spr_read_generic, &spr_write_generic, 6210 KVM_REG_PPC_PMC7, 0x00000000); 6211 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6212 SPR_NOACCESS, SPR_NOACCESS, 6213 &spr_read_generic, &spr_write_generic, 6214 KVM_REG_PPC_PMC8, 0x00000000); 6215 } 6216 6217 static void register_970_pmu_user_sprs(CPUPPCState *env) 6218 { 6219 spr_register(env, SPR_970_UPMC7, "UPMC7", 6220 &spr_read_ureg, SPR_NOACCESS, 6221 &spr_read_ureg, &spr_write_ureg, 6222 0x00000000); 6223 spr_register(env, SPR_970_UPMC8, "UPMC8", 6224 &spr_read_ureg, SPR_NOACCESS, 6225 &spr_read_ureg, &spr_write_ureg, 6226 0x00000000); 6227 } 6228 6229 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6230 { 6231 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6232 SPR_NOACCESS, SPR_NOACCESS, 6233 &spr_read_generic, &spr_write_generic, 6234 KVM_REG_PPC_MMCR2, 0x00000000); 6235 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6236 SPR_NOACCESS, SPR_NOACCESS, 6237 &spr_read_generic, &spr_write_generic, 6238 KVM_REG_PPC_MMCRS, 0x00000000); 6239 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 6240 SPR_NOACCESS, SPR_NOACCESS, 6241 &spr_read_generic, &spr_write_generic, 6242 KVM_REG_PPC_SIER, 0x00000000); 6243 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 6244 SPR_NOACCESS, SPR_NOACCESS, 6245 &spr_read_generic, &spr_write_generic, 6246 KVM_REG_PPC_SPMC1, 0x00000000); 6247 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 6248 SPR_NOACCESS, SPR_NOACCESS, 6249 &spr_read_generic, &spr_write_generic, 6250 KVM_REG_PPC_SPMC2, 0x00000000); 6251 spr_register_kvm(env, SPR_TACR, "TACR", 6252 SPR_NOACCESS, SPR_NOACCESS, 6253 &spr_read_generic, &spr_write_generic, 6254 KVM_REG_PPC_TACR, 0x00000000); 6255 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 6256 SPR_NOACCESS, SPR_NOACCESS, 6257 &spr_read_generic, &spr_write_generic, 6258 KVM_REG_PPC_TCSCR, 0x00000000); 6259 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 6260 SPR_NOACCESS, SPR_NOACCESS, 6261 &spr_read_generic, &spr_write_generic, 6262 KVM_REG_PPC_CSIGR, 0x00000000); 6263 } 6264 6265 static void register_power8_pmu_user_sprs(CPUPPCState *env) 6266 { 6267 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 6268 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 6269 &spr_read_ureg, &spr_write_ureg, 6270 0x00000000); 6271 spr_register(env, SPR_POWER_USIER, "USIER", 6272 &spr_read_generic, SPR_NOACCESS, 6273 &spr_read_generic, &spr_write_generic, 6274 0x00000000); 6275 } 6276 6277 static void register_power5p_ear_sprs(CPUPPCState *env) 6278 { 6279 /* External access control */ 6280 spr_register(env, SPR_EAR, "EAR", 6281 SPR_NOACCESS, SPR_NOACCESS, 6282 &spr_read_generic, &spr_write_generic, 6283 0x00000000); 6284 } 6285 6286 static void register_power5p_tb_sprs(CPUPPCState *env) 6287 { 6288 /* TBU40 (High 40 bits of the Timebase register */ 6289 spr_register_hv(env, SPR_TBU40, "TBU40", 6290 SPR_NOACCESS, SPR_NOACCESS, 6291 SPR_NOACCESS, SPR_NOACCESS, 6292 SPR_NOACCESS, &spr_write_tbu40, 6293 0x00000000); 6294 } 6295 6296 static void register_970_lpar_sprs(CPUPPCState *env) 6297 { 6298 #if !defined(CONFIG_USER_ONLY) 6299 /* 6300 * PPC970: HID4 covers things later controlled by the LPCR and 6301 * RMOR in later CPUs, but with a different encoding. We only 6302 * support the 970 in "Apple mode" which has all hypervisor 6303 * facilities disabled by strapping, so we can basically just 6304 * ignore it 6305 */ 6306 spr_register(env, SPR_970_HID4, "HID4", 6307 SPR_NOACCESS, SPR_NOACCESS, 6308 &spr_read_generic, &spr_write_generic, 6309 0x00000000); 6310 #endif 6311 } 6312 6313 static void register_power5p_lpar_sprs(CPUPPCState *env) 6314 { 6315 #if !defined(CONFIG_USER_ONLY) 6316 /* Logical partitionning */ 6317 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 6318 SPR_NOACCESS, SPR_NOACCESS, 6319 SPR_NOACCESS, SPR_NOACCESS, 6320 &spr_read_generic, &spr_write_lpcr, 6321 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 6322 spr_register_hv(env, SPR_HDEC, "HDEC", 6323 SPR_NOACCESS, SPR_NOACCESS, 6324 SPR_NOACCESS, SPR_NOACCESS, 6325 &spr_read_hdecr, &spr_write_hdecr, 0); 6326 #endif 6327 } 6328 6329 static void register_book3s_ids_sprs(CPUPPCState *env) 6330 { 6331 /* FIXME: Will need to deal with thread vs core only SPRs */ 6332 6333 /* Processor identification */ 6334 spr_register_hv(env, SPR_PIR, "PIR", 6335 SPR_NOACCESS, SPR_NOACCESS, 6336 &spr_read_generic, SPR_NOACCESS, 6337 &spr_read_generic, NULL, 6338 0x00000000); 6339 spr_register_hv(env, SPR_HID0, "HID0", 6340 SPR_NOACCESS, SPR_NOACCESS, 6341 SPR_NOACCESS, SPR_NOACCESS, 6342 &spr_read_generic, &spr_write_generic, 6343 0x00000000); 6344 spr_register_hv(env, SPR_TSCR, "TSCR", 6345 SPR_NOACCESS, SPR_NOACCESS, 6346 SPR_NOACCESS, SPR_NOACCESS, 6347 &spr_read_generic, &spr_write_generic, 6348 0x00000000); 6349 spr_register_hv(env, SPR_HMER, "HMER", 6350 SPR_NOACCESS, SPR_NOACCESS, 6351 SPR_NOACCESS, SPR_NOACCESS, 6352 &spr_read_generic, &spr_write_hmer, 6353 0x00000000); 6354 spr_register_hv(env, SPR_HMEER, "HMEER", 6355 SPR_NOACCESS, SPR_NOACCESS, 6356 SPR_NOACCESS, SPR_NOACCESS, 6357 &spr_read_generic, &spr_write_generic, 6358 0x00000000); 6359 spr_register_hv(env, SPR_TFMR, "TFMR", 6360 SPR_NOACCESS, SPR_NOACCESS, 6361 SPR_NOACCESS, SPR_NOACCESS, 6362 &spr_read_generic, &spr_write_generic, 6363 0x00000000); 6364 spr_register_hv(env, SPR_LPIDR, "LPIDR", 6365 SPR_NOACCESS, SPR_NOACCESS, 6366 SPR_NOACCESS, SPR_NOACCESS, 6367 &spr_read_generic, &spr_write_lpidr, 6368 0x00000000); 6369 spr_register_hv(env, SPR_HFSCR, "HFSCR", 6370 SPR_NOACCESS, SPR_NOACCESS, 6371 SPR_NOACCESS, SPR_NOACCESS, 6372 &spr_read_generic, &spr_write_generic, 6373 0x00000000); 6374 spr_register_hv(env, SPR_MMCRC, "MMCRC", 6375 SPR_NOACCESS, SPR_NOACCESS, 6376 SPR_NOACCESS, SPR_NOACCESS, 6377 &spr_read_generic, &spr_write_generic, 6378 0x00000000); 6379 spr_register_hv(env, SPR_MMCRH, "MMCRH", 6380 SPR_NOACCESS, SPR_NOACCESS, 6381 SPR_NOACCESS, SPR_NOACCESS, 6382 &spr_read_generic, &spr_write_generic, 6383 0x00000000); 6384 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6385 SPR_NOACCESS, SPR_NOACCESS, 6386 SPR_NOACCESS, SPR_NOACCESS, 6387 &spr_read_generic, &spr_write_generic, 6388 0x00000000); 6389 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6390 SPR_NOACCESS, SPR_NOACCESS, 6391 SPR_NOACCESS, SPR_NOACCESS, 6392 &spr_read_generic, &spr_write_generic, 6393 0x00000000); 6394 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6395 SPR_NOACCESS, SPR_NOACCESS, 6396 SPR_NOACCESS, SPR_NOACCESS, 6397 &spr_read_generic, &spr_write_generic, 6398 0x00000000); 6399 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6400 SPR_NOACCESS, SPR_NOACCESS, 6401 SPR_NOACCESS, SPR_NOACCESS, 6402 &spr_read_generic, &spr_write_generic, 6403 0x00000000); 6404 spr_register_hv(env, SPR_HDAR, "HDAR", 6405 SPR_NOACCESS, SPR_NOACCESS, 6406 SPR_NOACCESS, SPR_NOACCESS, 6407 &spr_read_generic, &spr_write_generic, 6408 0x00000000); 6409 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6410 SPR_NOACCESS, SPR_NOACCESS, 6411 SPR_NOACCESS, SPR_NOACCESS, 6412 &spr_read_generic, &spr_write_generic, 6413 0x00000000); 6414 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6415 SPR_NOACCESS, SPR_NOACCESS, 6416 SPR_NOACCESS, SPR_NOACCESS, 6417 &spr_read_generic, &spr_write_generic, 6418 0x00000000); 6419 } 6420 6421 static void register_rmor_sprs(CPUPPCState *env) 6422 { 6423 spr_register_hv(env, SPR_RMOR, "RMOR", 6424 SPR_NOACCESS, SPR_NOACCESS, 6425 SPR_NOACCESS, SPR_NOACCESS, 6426 &spr_read_generic, &spr_write_generic, 6427 0x00000000); 6428 } 6429 6430 static void register_power8_ids_sprs(CPUPPCState *env) 6431 { 6432 /* Thread identification */ 6433 spr_register(env, SPR_TIR, "TIR", 6434 SPR_NOACCESS, SPR_NOACCESS, 6435 &spr_read_generic, SPR_NOACCESS, 6436 0x00000000); 6437 } 6438 6439 static void register_book3s_purr_sprs(CPUPPCState *env) 6440 { 6441 #if !defined(CONFIG_USER_ONLY) 6442 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6443 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6444 &spr_read_purr, SPR_NOACCESS, 6445 &spr_read_purr, SPR_NOACCESS, 6446 &spr_read_purr, &spr_write_purr, 6447 KVM_REG_PPC_PURR, 0x00000000); 6448 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6449 &spr_read_purr, SPR_NOACCESS, 6450 &spr_read_purr, SPR_NOACCESS, 6451 &spr_read_purr, &spr_write_purr, 6452 KVM_REG_PPC_SPURR, 0x00000000); 6453 #endif 6454 } 6455 6456 static void register_power6_dbg_sprs(CPUPPCState *env) 6457 { 6458 #if !defined(CONFIG_USER_ONLY) 6459 spr_register(env, SPR_CFAR, "SPR_CFAR", 6460 SPR_NOACCESS, SPR_NOACCESS, 6461 &spr_read_cfar, &spr_write_cfar, 6462 0x00000000); 6463 #endif 6464 } 6465 6466 static void register_power5p_common_sprs(CPUPPCState *env) 6467 { 6468 spr_register_kvm(env, SPR_PPR, "PPR", 6469 &spr_read_generic, &spr_write_generic, 6470 &spr_read_generic, &spr_write_generic, 6471 KVM_REG_PPC_PPR, 0x00000000); 6472 } 6473 6474 static void register_power6_common_sprs(CPUPPCState *env) 6475 { 6476 #if !defined(CONFIG_USER_ONLY) 6477 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6478 SPR_NOACCESS, SPR_NOACCESS, 6479 &spr_read_generic, &spr_write_generic, 6480 KVM_REG_PPC_DSCR, 0x00000000); 6481 #endif 6482 /* 6483 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6484 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6485 */ 6486 spr_register_hv(env, SPR_PCR, "PCR", 6487 SPR_NOACCESS, SPR_NOACCESS, 6488 SPR_NOACCESS, SPR_NOACCESS, 6489 &spr_read_generic, &spr_write_pcr, 6490 0x00000000); 6491 } 6492 6493 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6494 { 6495 spr_register_kvm(env, SPR_TAR, "TAR", 6496 &spr_read_tar, &spr_write_tar, 6497 &spr_read_generic, &spr_write_generic, 6498 KVM_REG_PPC_TAR, 0x00000000); 6499 } 6500 6501 static void register_power8_tm_sprs(CPUPPCState *env) 6502 { 6503 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6504 &spr_read_tm, &spr_write_tm, 6505 &spr_read_tm, &spr_write_tm, 6506 KVM_REG_PPC_TFHAR, 0x00000000); 6507 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6508 &spr_read_tm, &spr_write_tm, 6509 &spr_read_tm, &spr_write_tm, 6510 KVM_REG_PPC_TFIAR, 0x00000000); 6511 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6512 &spr_read_tm, &spr_write_tm, 6513 &spr_read_tm, &spr_write_tm, 6514 KVM_REG_PPC_TEXASR, 0x00000000); 6515 spr_register(env, SPR_TEXASRU, "TEXASRU", 6516 &spr_read_tm_upper32, &spr_write_tm_upper32, 6517 &spr_read_tm_upper32, &spr_write_tm_upper32, 6518 0x00000000); 6519 } 6520 6521 static void register_power8_ebb_sprs(CPUPPCState *env) 6522 { 6523 spr_register(env, SPR_BESCRS, "BESCRS", 6524 &spr_read_ebb, &spr_write_ebb, 6525 &spr_read_generic, &spr_write_generic, 6526 0x00000000); 6527 spr_register(env, SPR_BESCRSU, "BESCRSU", 6528 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6529 &spr_read_prev_upper32, &spr_write_prev_upper32, 6530 0x00000000); 6531 spr_register(env, SPR_BESCRR, "BESCRR", 6532 &spr_read_ebb, &spr_write_ebb, 6533 &spr_read_generic, &spr_write_generic, 6534 0x00000000); 6535 spr_register(env, SPR_BESCRRU, "BESCRRU", 6536 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6537 &spr_read_prev_upper32, &spr_write_prev_upper32, 6538 0x00000000); 6539 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6540 &spr_read_ebb, &spr_write_ebb, 6541 &spr_read_generic, &spr_write_generic, 6542 KVM_REG_PPC_EBBHR, 0x00000000); 6543 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6544 &spr_read_ebb, &spr_write_ebb, 6545 &spr_read_generic, &spr_write_generic, 6546 KVM_REG_PPC_EBBRR, 0x00000000); 6547 spr_register_kvm(env, SPR_BESCR, "BESCR", 6548 &spr_read_ebb, &spr_write_ebb, 6549 &spr_read_generic, &spr_write_generic, 6550 KVM_REG_PPC_BESCR, 0x00000000); 6551 } 6552 6553 /* Virtual Time Base */ 6554 static void register_vtb_sprs(CPUPPCState *env) 6555 { 6556 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6557 SPR_NOACCESS, SPR_NOACCESS, 6558 &spr_read_vtb, SPR_NOACCESS, 6559 &spr_read_vtb, &spr_write_vtb, 6560 KVM_REG_PPC_VTB, 0x00000000); 6561 } 6562 6563 static void register_power8_fscr_sprs(CPUPPCState *env) 6564 { 6565 #if defined(CONFIG_USER_ONLY) 6566 target_ulong initval = 1ULL << FSCR_TAR; 6567 #else 6568 target_ulong initval = 0; 6569 #endif 6570 spr_register_kvm(env, SPR_FSCR, "FSCR", 6571 SPR_NOACCESS, SPR_NOACCESS, 6572 &spr_read_generic, &spr_write_generic, 6573 KVM_REG_PPC_FSCR, initval); 6574 } 6575 6576 static void register_power8_pspb_sprs(CPUPPCState *env) 6577 { 6578 spr_register_kvm(env, SPR_PSPB, "PSPB", 6579 SPR_NOACCESS, SPR_NOACCESS, 6580 &spr_read_generic, &spr_write_generic32, 6581 KVM_REG_PPC_PSPB, 0); 6582 } 6583 6584 static void register_power8_dpdes_sprs(CPUPPCState *env) 6585 { 6586 #if !defined(CONFIG_USER_ONLY) 6587 /* Directed Privileged Door-bell Exception State, used for IPI */ 6588 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6589 SPR_NOACCESS, SPR_NOACCESS, 6590 &spr_read_dpdes, SPR_NOACCESS, 6591 &spr_read_dpdes, &spr_write_dpdes, 6592 KVM_REG_PPC_DPDES, 0x00000000); 6593 #endif 6594 } 6595 6596 static void register_power8_ic_sprs(CPUPPCState *env) 6597 { 6598 #if !defined(CONFIG_USER_ONLY) 6599 spr_register_hv(env, SPR_IC, "IC", 6600 SPR_NOACCESS, SPR_NOACCESS, 6601 &spr_read_generic, SPR_NOACCESS, 6602 &spr_read_generic, &spr_write_generic, 6603 0); 6604 #endif 6605 } 6606 6607 static void register_power8_book4_sprs(CPUPPCState *env) 6608 { 6609 /* Add a number of P8 book4 registers */ 6610 #if !defined(CONFIG_USER_ONLY) 6611 spr_register_kvm(env, SPR_ACOP, "ACOP", 6612 SPR_NOACCESS, SPR_NOACCESS, 6613 &spr_read_generic, &spr_write_generic, 6614 KVM_REG_PPC_ACOP, 0); 6615 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6616 SPR_NOACCESS, SPR_NOACCESS, 6617 &spr_read_generic, &spr_write_pidr, 6618 KVM_REG_PPC_PID, 0); 6619 spr_register_kvm(env, SPR_WORT, "WORT", 6620 SPR_NOACCESS, SPR_NOACCESS, 6621 &spr_read_generic, &spr_write_generic, 6622 KVM_REG_PPC_WORT, 0); 6623 #endif 6624 } 6625 6626 static void register_power7_book4_sprs(CPUPPCState *env) 6627 { 6628 /* Add a number of P7 book4 registers */ 6629 #if !defined(CONFIG_USER_ONLY) 6630 spr_register_kvm(env, SPR_ACOP, "ACOP", 6631 SPR_NOACCESS, SPR_NOACCESS, 6632 &spr_read_generic, &spr_write_generic, 6633 KVM_REG_PPC_ACOP, 0); 6634 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6635 SPR_NOACCESS, SPR_NOACCESS, 6636 &spr_read_generic, &spr_write_generic, 6637 KVM_REG_PPC_PID, 0); 6638 #endif 6639 } 6640 6641 static void register_power8_rpr_sprs(CPUPPCState *env) 6642 { 6643 #if !defined(CONFIG_USER_ONLY) 6644 spr_register_hv(env, SPR_RPR, "RPR", 6645 SPR_NOACCESS, SPR_NOACCESS, 6646 SPR_NOACCESS, SPR_NOACCESS, 6647 &spr_read_generic, &spr_write_generic, 6648 0x00000103070F1F3F); 6649 #endif 6650 } 6651 6652 static void register_power9_mmu_sprs(CPUPPCState *env) 6653 { 6654 #if !defined(CONFIG_USER_ONLY) 6655 /* Partition Table Control */ 6656 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6657 SPR_NOACCESS, SPR_NOACCESS, 6658 SPR_NOACCESS, SPR_NOACCESS, 6659 &spr_read_generic, &spr_write_ptcr, 6660 KVM_REG_PPC_PTCR, 0x00000000); 6661 /* Address Segment Descriptor Register */ 6662 spr_register_hv(env, SPR_ASDR, "ASDR", 6663 SPR_NOACCESS, SPR_NOACCESS, 6664 SPR_NOACCESS, SPR_NOACCESS, 6665 &spr_read_generic, &spr_write_generic, 6666 0x0000000000000000); 6667 #endif 6668 } 6669 6670 /* 6671 * Initialize PMU counter overflow timers for Power8 and 6672 * newer Power chips when using TCG. 6673 */ 6674 static void init_tcg_pmu_power8(CPUPPCState *env) 6675 { 6676 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6677 /* Init PMU overflow timers */ 6678 if (!kvm_enabled()) { 6679 cpu_ppc_pmu_init(env); 6680 } 6681 #endif 6682 } 6683 6684 static void init_proc_book3s_common(CPUPPCState *env) 6685 { 6686 register_ne_601_sprs(env); 6687 register_tbl(env); 6688 register_usprg3_sprs(env); 6689 register_book3s_altivec_sprs(env); 6690 register_book3s_pmu_sup_sprs(env); 6691 register_book3s_pmu_user_sprs(env); 6692 register_book3s_ctrl_sprs(env); 6693 /* 6694 * Can't find information on what this should be on reset. This 6695 * value is the one used by 74xx processors. 6696 */ 6697 vscr_init(env, 0x00010000); 6698 } 6699 6700 static void init_proc_970(CPUPPCState *env) 6701 { 6702 /* Common Registers */ 6703 init_proc_book3s_common(env); 6704 register_sdr1_sprs(env); 6705 register_book3s_dbg_sprs(env); 6706 6707 /* 970 Specific Registers */ 6708 register_970_hid_sprs(env); 6709 register_970_hior_sprs(env); 6710 register_low_BATs(env); 6711 register_970_pmu_sup_sprs(env); 6712 register_970_pmu_user_sprs(env); 6713 register_970_lpar_sprs(env); 6714 register_970_dbg_sprs(env); 6715 6716 /* env variables */ 6717 env->dcache_line_size = 128; 6718 env->icache_line_size = 128; 6719 6720 /* Allocate hardware IRQ controller */ 6721 init_excp_970(env); 6722 ppc970_irq_init(env_archcpu(env)); 6723 } 6724 6725 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6726 { 6727 DeviceClass *dc = DEVICE_CLASS(oc); 6728 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6729 6730 dc->desc = "PowerPC 970"; 6731 pcc->init_proc = init_proc_970; 6732 pcc->check_pow = check_pow_970; 6733 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6734 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6735 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6736 PPC_FLOAT_STFIWX | 6737 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6738 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6739 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6740 PPC_64B | PPC_ALTIVEC | 6741 PPC_SEGMENT_64B | PPC_SLBI; 6742 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6743 pcc->msr_mask = (1ull << MSR_SF) | 6744 (1ull << MSR_VR) | 6745 (1ull << MSR_POW) | 6746 (1ull << MSR_EE) | 6747 (1ull << MSR_PR) | 6748 (1ull << MSR_FP) | 6749 (1ull << MSR_ME) | 6750 (1ull << MSR_FE0) | 6751 (1ull << MSR_SE) | 6752 (1ull << MSR_DE) | 6753 (1ull << MSR_FE1) | 6754 (1ull << MSR_IR) | 6755 (1ull << MSR_DR) | 6756 (1ull << MSR_PMM) | 6757 (1ull << MSR_RI); 6758 pcc->mmu_model = POWERPC_MMU_64B; 6759 #if defined(CONFIG_SOFTMMU) 6760 pcc->hash64_opts = &ppc_hash64_opts_basic; 6761 #endif 6762 pcc->excp_model = POWERPC_EXCP_970; 6763 pcc->bus_model = PPC_FLAGS_INPUT_970; 6764 pcc->bfd_mach = bfd_mach_ppc64; 6765 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6766 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6767 POWERPC_FLAG_BUS_CLK; 6768 pcc->l1_dcache_size = 0x8000; 6769 pcc->l1_icache_size = 0x10000; 6770 } 6771 6772 static void init_proc_power5plus(CPUPPCState *env) 6773 { 6774 /* Common Registers */ 6775 init_proc_book3s_common(env); 6776 register_sdr1_sprs(env); 6777 register_book3s_dbg_sprs(env); 6778 6779 /* POWER5+ Specific Registers */ 6780 register_970_hid_sprs(env); 6781 register_970_hior_sprs(env); 6782 register_low_BATs(env); 6783 register_970_pmu_sup_sprs(env); 6784 register_970_pmu_user_sprs(env); 6785 register_power5p_common_sprs(env); 6786 register_power5p_lpar_sprs(env); 6787 register_power5p_ear_sprs(env); 6788 register_power5p_tb_sprs(env); 6789 6790 /* env variables */ 6791 env->dcache_line_size = 128; 6792 env->icache_line_size = 128; 6793 6794 /* Allocate hardware IRQ controller */ 6795 init_excp_970(env); 6796 ppc970_irq_init(env_archcpu(env)); 6797 } 6798 6799 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6800 { 6801 DeviceClass *dc = DEVICE_CLASS(oc); 6802 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6803 6804 dc->fw_name = "PowerPC,POWER5"; 6805 dc->desc = "POWER5+"; 6806 pcc->init_proc = init_proc_power5plus; 6807 pcc->check_pow = check_pow_970; 6808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6809 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6810 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6811 PPC_FLOAT_STFIWX | 6812 PPC_FLOAT_EXT | 6813 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6814 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6815 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6816 PPC_64B | 6817 PPC_POPCNTB | 6818 PPC_SEGMENT_64B | PPC_SLBI; 6819 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6820 pcc->msr_mask = (1ull << MSR_SF) | 6821 (1ull << MSR_VR) | 6822 (1ull << MSR_POW) | 6823 (1ull << MSR_EE) | 6824 (1ull << MSR_PR) | 6825 (1ull << MSR_FP) | 6826 (1ull << MSR_ME) | 6827 (1ull << MSR_FE0) | 6828 (1ull << MSR_SE) | 6829 (1ull << MSR_DE) | 6830 (1ull << MSR_FE1) | 6831 (1ull << MSR_IR) | 6832 (1ull << MSR_DR) | 6833 (1ull << MSR_PMM) | 6834 (1ull << MSR_RI); 6835 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6836 LPCR_RMI | LPCR_HDICE; 6837 pcc->mmu_model = POWERPC_MMU_2_03; 6838 #if defined(CONFIG_SOFTMMU) 6839 pcc->hash64_opts = &ppc_hash64_opts_basic; 6840 pcc->lrg_decr_bits = 32; 6841 #endif 6842 pcc->excp_model = POWERPC_EXCP_970; 6843 pcc->bus_model = PPC_FLAGS_INPUT_970; 6844 pcc->bfd_mach = bfd_mach_ppc64; 6845 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6846 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6847 POWERPC_FLAG_BUS_CLK; 6848 pcc->l1_dcache_size = 0x8000; 6849 pcc->l1_icache_size = 0x10000; 6850 } 6851 6852 static void init_proc_POWER7(CPUPPCState *env) 6853 { 6854 /* Common Registers */ 6855 init_proc_book3s_common(env); 6856 register_sdr1_sprs(env); 6857 register_book3s_dbg_sprs(env); 6858 6859 /* POWER7 Specific Registers */ 6860 register_book3s_ids_sprs(env); 6861 register_rmor_sprs(env); 6862 register_amr_sprs(env); 6863 register_book3s_purr_sprs(env); 6864 register_power5p_common_sprs(env); 6865 register_power5p_lpar_sprs(env); 6866 register_power5p_ear_sprs(env); 6867 register_power5p_tb_sprs(env); 6868 register_power6_common_sprs(env); 6869 register_power6_dbg_sprs(env); 6870 register_power7_book4_sprs(env); 6871 6872 /* env variables */ 6873 env->dcache_line_size = 128; 6874 env->icache_line_size = 128; 6875 6876 /* Allocate hardware IRQ controller */ 6877 init_excp_POWER7(env); 6878 ppcPOWER7_irq_init(env_archcpu(env)); 6879 } 6880 6881 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6882 { 6883 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6884 return true; 6885 } 6886 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6887 return true; 6888 } 6889 return false; 6890 } 6891 6892 static bool cpu_has_work_POWER7(CPUState *cs) 6893 { 6894 PowerPCCPU *cpu = POWERPC_CPU(cs); 6895 CPUPPCState *env = &cpu->env; 6896 6897 if (cs->halted) { 6898 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6899 return false; 6900 } 6901 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6902 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6903 return true; 6904 } 6905 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6906 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6907 return true; 6908 } 6909 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6910 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6911 return true; 6912 } 6913 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6914 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6915 return true; 6916 } 6917 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6918 return true; 6919 } 6920 return false; 6921 } else { 6922 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6923 } 6924 } 6925 6926 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6927 { 6928 DeviceClass *dc = DEVICE_CLASS(oc); 6929 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6930 CPUClass *cc = CPU_CLASS(oc); 6931 6932 dc->fw_name = "PowerPC,POWER7"; 6933 dc->desc = "POWER7"; 6934 pcc->pvr_match = ppc_pvr_match_power7; 6935 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6936 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6937 pcc->init_proc = init_proc_POWER7; 6938 pcc->check_pow = check_pow_nocheck; 6939 cc->has_work = cpu_has_work_POWER7; 6940 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6941 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6942 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6943 PPC_FLOAT_FRSQRTES | 6944 PPC_FLOAT_STFIWX | 6945 PPC_FLOAT_EXT | 6946 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6947 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6948 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6949 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6950 PPC_SEGMENT_64B | PPC_SLBI | 6951 PPC_POPCNTB | PPC_POPCNTWD | 6952 PPC_CILDST; 6953 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6954 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6955 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6956 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6957 PPC2_PM_ISA206; 6958 pcc->msr_mask = (1ull << MSR_SF) | 6959 (1ull << MSR_VR) | 6960 (1ull << MSR_VSX) | 6961 (1ull << MSR_EE) | 6962 (1ull << MSR_PR) | 6963 (1ull << MSR_FP) | 6964 (1ull << MSR_ME) | 6965 (1ull << MSR_FE0) | 6966 (1ull << MSR_SE) | 6967 (1ull << MSR_DE) | 6968 (1ull << MSR_FE1) | 6969 (1ull << MSR_IR) | 6970 (1ull << MSR_DR) | 6971 (1ull << MSR_PMM) | 6972 (1ull << MSR_RI) | 6973 (1ull << MSR_LE); 6974 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6975 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6976 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6977 LPCR_MER | LPCR_TC | 6978 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6979 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6980 pcc->mmu_model = POWERPC_MMU_2_06; 6981 #if defined(CONFIG_SOFTMMU) 6982 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6983 pcc->lrg_decr_bits = 32; 6984 #endif 6985 pcc->excp_model = POWERPC_EXCP_POWER7; 6986 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6987 pcc->bfd_mach = bfd_mach_ppc64; 6988 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6989 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6990 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6991 POWERPC_FLAG_VSX; 6992 pcc->l1_dcache_size = 0x8000; 6993 pcc->l1_icache_size = 0x8000; 6994 } 6995 6996 static void init_proc_POWER8(CPUPPCState *env) 6997 { 6998 /* Common Registers */ 6999 init_proc_book3s_common(env); 7000 register_sdr1_sprs(env); 7001 register_book3s_207_dbg_sprs(env); 7002 7003 /* Common TCG PMU */ 7004 init_tcg_pmu_power8(env); 7005 7006 /* POWER8 Specific Registers */ 7007 register_book3s_ids_sprs(env); 7008 register_rmor_sprs(env); 7009 register_amr_sprs(env); 7010 register_iamr_sprs(env); 7011 register_book3s_purr_sprs(env); 7012 register_power5p_common_sprs(env); 7013 register_power5p_lpar_sprs(env); 7014 register_power5p_ear_sprs(env); 7015 register_power5p_tb_sprs(env); 7016 register_power6_common_sprs(env); 7017 register_power6_dbg_sprs(env); 7018 register_power8_tce_address_control_sprs(env); 7019 register_power8_ids_sprs(env); 7020 register_power8_ebb_sprs(env); 7021 register_power8_fscr_sprs(env); 7022 register_power8_pmu_sup_sprs(env); 7023 register_power8_pmu_user_sprs(env); 7024 register_power8_tm_sprs(env); 7025 register_power8_pspb_sprs(env); 7026 register_power8_dpdes_sprs(env); 7027 register_vtb_sprs(env); 7028 register_power8_ic_sprs(env); 7029 register_power8_book4_sprs(env); 7030 register_power8_rpr_sprs(env); 7031 7032 /* env variables */ 7033 env->dcache_line_size = 128; 7034 env->icache_line_size = 128; 7035 7036 /* Allocate hardware IRQ controller */ 7037 init_excp_POWER8(env); 7038 ppcPOWER7_irq_init(env_archcpu(env)); 7039 } 7040 7041 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7042 { 7043 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7044 return true; 7045 } 7046 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7047 return true; 7048 } 7049 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7050 return true; 7051 } 7052 return false; 7053 } 7054 7055 static bool cpu_has_work_POWER8(CPUState *cs) 7056 { 7057 PowerPCCPU *cpu = POWERPC_CPU(cs); 7058 CPUPPCState *env = &cpu->env; 7059 7060 if (cs->halted) { 7061 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7062 return false; 7063 } 7064 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7065 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7066 return true; 7067 } 7068 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7069 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7070 return true; 7071 } 7072 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7073 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7074 return true; 7075 } 7076 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7077 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7078 return true; 7079 } 7080 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7081 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7082 return true; 7083 } 7084 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7085 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7086 return true; 7087 } 7088 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7089 return true; 7090 } 7091 return false; 7092 } else { 7093 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7094 } 7095 } 7096 7097 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7098 { 7099 DeviceClass *dc = DEVICE_CLASS(oc); 7100 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7101 CPUClass *cc = CPU_CLASS(oc); 7102 7103 dc->fw_name = "PowerPC,POWER8"; 7104 dc->desc = "POWER8"; 7105 pcc->pvr_match = ppc_pvr_match_power8; 7106 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7107 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7108 pcc->init_proc = init_proc_POWER8; 7109 pcc->check_pow = check_pow_nocheck; 7110 cc->has_work = cpu_has_work_POWER8; 7111 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7112 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7113 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7114 PPC_FLOAT_FRSQRTES | 7115 PPC_FLOAT_STFIWX | 7116 PPC_FLOAT_EXT | 7117 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7118 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7119 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7120 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7121 PPC_SEGMENT_64B | PPC_SLBI | 7122 PPC_POPCNTB | PPC_POPCNTWD | 7123 PPC_CILDST; 7124 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7125 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7126 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7127 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7128 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7129 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7130 PPC2_TM | PPC2_PM_ISA206; 7131 pcc->msr_mask = (1ull << MSR_SF) | 7132 (1ull << MSR_HV) | 7133 (1ull << MSR_TM) | 7134 (1ull << MSR_VR) | 7135 (1ull << MSR_VSX) | 7136 (1ull << MSR_EE) | 7137 (1ull << MSR_PR) | 7138 (1ull << MSR_FP) | 7139 (1ull << MSR_ME) | 7140 (1ull << MSR_FE0) | 7141 (1ull << MSR_SE) | 7142 (1ull << MSR_DE) | 7143 (1ull << MSR_FE1) | 7144 (1ull << MSR_IR) | 7145 (1ull << MSR_DR) | 7146 (1ull << MSR_PMM) | 7147 (1ull << MSR_RI) | 7148 (1ull << MSR_TS0) | 7149 (1ull << MSR_TS1) | 7150 (1ull << MSR_LE); 7151 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7152 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7153 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7154 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7155 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7156 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7157 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7158 pcc->mmu_model = POWERPC_MMU_2_07; 7159 #if defined(CONFIG_SOFTMMU) 7160 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7161 pcc->lrg_decr_bits = 32; 7162 pcc->n_host_threads = 8; 7163 #endif 7164 pcc->excp_model = POWERPC_EXCP_POWER8; 7165 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7166 pcc->bfd_mach = bfd_mach_ppc64; 7167 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7168 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7169 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7170 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7171 pcc->l1_dcache_size = 0x8000; 7172 pcc->l1_icache_size = 0x8000; 7173 } 7174 7175 #ifdef CONFIG_SOFTMMU 7176 /* 7177 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7178 * Encoded as array of int_32s in the form: 7179 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7180 * x -> AP encoding 7181 * y -> radix mode supported page size (encoded as a shift) 7182 */ 7183 static struct ppc_radix_page_info POWER9_radix_page_info = { 7184 .count = 4, 7185 .entries = { 7186 0x0000000c, /* 4K - enc: 0x0 */ 7187 0xa0000010, /* 64K - enc: 0x5 */ 7188 0x20000015, /* 2M - enc: 0x1 */ 7189 0x4000001e /* 1G - enc: 0x2 */ 7190 } 7191 }; 7192 #endif /* CONFIG_SOFTMMU */ 7193 7194 static void init_proc_POWER9(CPUPPCState *env) 7195 { 7196 /* Common Registers */ 7197 init_proc_book3s_common(env); 7198 register_book3s_207_dbg_sprs(env); 7199 7200 /* Common TCG PMU */ 7201 init_tcg_pmu_power8(env); 7202 7203 /* POWER8 Specific Registers */ 7204 register_book3s_ids_sprs(env); 7205 register_amr_sprs(env); 7206 register_iamr_sprs(env); 7207 register_book3s_purr_sprs(env); 7208 register_power5p_common_sprs(env); 7209 register_power5p_lpar_sprs(env); 7210 register_power5p_ear_sprs(env); 7211 register_power5p_tb_sprs(env); 7212 register_power6_common_sprs(env); 7213 register_power6_dbg_sprs(env); 7214 register_power8_tce_address_control_sprs(env); 7215 register_power8_ids_sprs(env); 7216 register_power8_ebb_sprs(env); 7217 register_power8_fscr_sprs(env); 7218 register_power8_pmu_sup_sprs(env); 7219 register_power8_pmu_user_sprs(env); 7220 register_power8_tm_sprs(env); 7221 register_power8_pspb_sprs(env); 7222 register_power8_dpdes_sprs(env); 7223 register_vtb_sprs(env); 7224 register_power8_ic_sprs(env); 7225 register_power8_book4_sprs(env); 7226 register_power8_rpr_sprs(env); 7227 register_power9_mmu_sprs(env); 7228 7229 /* POWER9 Specific registers */ 7230 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7231 spr_read_generic, spr_write_generic, 7232 KVM_REG_PPC_TIDR, 0); 7233 7234 /* FIXME: Filter fields properly based on privilege level */ 7235 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7236 spr_read_generic, spr_write_generic, 7237 KVM_REG_PPC_PSSCR, 0); 7238 7239 /* env variables */ 7240 env->dcache_line_size = 128; 7241 env->icache_line_size = 128; 7242 7243 /* Allocate hardware IRQ controller */ 7244 init_excp_POWER9(env); 7245 ppcPOWER9_irq_init(env_archcpu(env)); 7246 } 7247 7248 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7249 { 7250 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7251 return true; 7252 } 7253 return false; 7254 } 7255 7256 static bool cpu_has_work_POWER9(CPUState *cs) 7257 { 7258 PowerPCCPU *cpu = POWERPC_CPU(cs); 7259 CPUPPCState *env = &cpu->env; 7260 7261 if (cs->halted) { 7262 uint64_t psscr = env->spr[SPR_PSSCR]; 7263 7264 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7265 return false; 7266 } 7267 7268 /* If EC is clear, just return true on any pending interrupt */ 7269 if (!(psscr & PSSCR_EC)) { 7270 return true; 7271 } 7272 /* External Exception */ 7273 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7274 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7275 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7276 if (heic == 0 || !msr_hv || msr_pr) { 7277 return true; 7278 } 7279 } 7280 /* Decrementer Exception */ 7281 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7282 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7283 return true; 7284 } 7285 /* Machine Check or Hypervisor Maintenance Exception */ 7286 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7287 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7288 return true; 7289 } 7290 /* Privileged Doorbell Exception */ 7291 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7292 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7293 return true; 7294 } 7295 /* Hypervisor Doorbell Exception */ 7296 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7297 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7298 return true; 7299 } 7300 /* Hypervisor virtualization exception */ 7301 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7302 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7303 return true; 7304 } 7305 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7306 return true; 7307 } 7308 return false; 7309 } else { 7310 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7311 } 7312 } 7313 7314 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 7315 { 7316 DeviceClass *dc = DEVICE_CLASS(oc); 7317 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7318 CPUClass *cc = CPU_CLASS(oc); 7319 7320 dc->fw_name = "PowerPC,POWER9"; 7321 dc->desc = "POWER9"; 7322 pcc->pvr_match = ppc_pvr_match_power9; 7323 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 7324 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 7325 PCR_COMPAT_2_05; 7326 pcc->init_proc = init_proc_POWER9; 7327 pcc->check_pow = check_pow_nocheck; 7328 cc->has_work = cpu_has_work_POWER9; 7329 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7331 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7332 PPC_FLOAT_FRSQRTES | 7333 PPC_FLOAT_STFIWX | 7334 PPC_FLOAT_EXT | 7335 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7336 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7337 PPC_MEM_TLBSYNC | 7338 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7339 PPC_SEGMENT_64B | PPC_SLBI | 7340 PPC_POPCNTB | PPC_POPCNTWD | 7341 PPC_CILDST; 7342 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7343 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7344 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7345 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7346 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7347 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7348 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 7349 pcc->msr_mask = (1ull << MSR_SF) | 7350 (1ull << MSR_HV) | 7351 (1ull << MSR_TM) | 7352 (1ull << MSR_VR) | 7353 (1ull << MSR_VSX) | 7354 (1ull << MSR_EE) | 7355 (1ull << MSR_PR) | 7356 (1ull << MSR_FP) | 7357 (1ull << MSR_ME) | 7358 (1ull << MSR_FE0) | 7359 (1ull << MSR_SE) | 7360 (1ull << MSR_DE) | 7361 (1ull << MSR_FE1) | 7362 (1ull << MSR_IR) | 7363 (1ull << MSR_DR) | 7364 (1ull << MSR_PMM) | 7365 (1ull << MSR_RI) | 7366 (1ull << MSR_LE); 7367 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7368 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7369 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7370 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7371 LPCR_DEE | LPCR_OEE)) 7372 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7373 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7374 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7375 pcc->mmu_model = POWERPC_MMU_3_00; 7376 #if defined(CONFIG_SOFTMMU) 7377 /* segment page size remain the same */ 7378 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7379 pcc->radix_page_info = &POWER9_radix_page_info; 7380 pcc->lrg_decr_bits = 56; 7381 pcc->n_host_threads = 4; 7382 #endif 7383 pcc->excp_model = POWERPC_EXCP_POWER9; 7384 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7385 pcc->bfd_mach = bfd_mach_ppc64; 7386 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7387 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7388 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7389 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7390 pcc->l1_dcache_size = 0x8000; 7391 pcc->l1_icache_size = 0x8000; 7392 } 7393 7394 #ifdef CONFIG_SOFTMMU 7395 /* 7396 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7397 * Encoded as array of int_32s in the form: 7398 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7399 * x -> AP encoding 7400 * y -> radix mode supported page size (encoded as a shift) 7401 */ 7402 static struct ppc_radix_page_info POWER10_radix_page_info = { 7403 .count = 4, 7404 .entries = { 7405 0x0000000c, /* 4K - enc: 0x0 */ 7406 0xa0000010, /* 64K - enc: 0x5 */ 7407 0x20000015, /* 2M - enc: 0x1 */ 7408 0x4000001e /* 1G - enc: 0x2 */ 7409 } 7410 }; 7411 #endif /* CONFIG_SOFTMMU */ 7412 7413 static void init_proc_POWER10(CPUPPCState *env) 7414 { 7415 /* Common Registers */ 7416 init_proc_book3s_common(env); 7417 register_book3s_207_dbg_sprs(env); 7418 7419 /* Common TCG PMU */ 7420 init_tcg_pmu_power8(env); 7421 7422 /* POWER8 Specific Registers */ 7423 register_book3s_ids_sprs(env); 7424 register_amr_sprs(env); 7425 register_iamr_sprs(env); 7426 register_book3s_purr_sprs(env); 7427 register_power5p_common_sprs(env); 7428 register_power5p_lpar_sprs(env); 7429 register_power5p_ear_sprs(env); 7430 register_power6_common_sprs(env); 7431 register_power6_dbg_sprs(env); 7432 register_power8_tce_address_control_sprs(env); 7433 register_power8_ids_sprs(env); 7434 register_power8_ebb_sprs(env); 7435 register_power8_fscr_sprs(env); 7436 register_power8_pmu_sup_sprs(env); 7437 register_power8_pmu_user_sprs(env); 7438 register_power8_tm_sprs(env); 7439 register_power8_pspb_sprs(env); 7440 register_vtb_sprs(env); 7441 register_power8_ic_sprs(env); 7442 register_power8_book4_sprs(env); 7443 register_power8_rpr_sprs(env); 7444 register_power9_mmu_sprs(env); 7445 7446 /* FIXME: Filter fields properly based on privilege level */ 7447 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7448 spr_read_generic, spr_write_generic, 7449 KVM_REG_PPC_PSSCR, 0); 7450 7451 /* env variables */ 7452 env->dcache_line_size = 128; 7453 env->icache_line_size = 128; 7454 7455 /* Allocate hardware IRQ controller */ 7456 init_excp_POWER10(env); 7457 ppcPOWER9_irq_init(env_archcpu(env)); 7458 } 7459 7460 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7461 { 7462 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7463 return true; 7464 } 7465 return false; 7466 } 7467 7468 static bool cpu_has_work_POWER10(CPUState *cs) 7469 { 7470 PowerPCCPU *cpu = POWERPC_CPU(cs); 7471 CPUPPCState *env = &cpu->env; 7472 7473 if (cs->halted) { 7474 uint64_t psscr = env->spr[SPR_PSSCR]; 7475 7476 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7477 return false; 7478 } 7479 7480 /* If EC is clear, just return true on any pending interrupt */ 7481 if (!(psscr & PSSCR_EC)) { 7482 return true; 7483 } 7484 /* External Exception */ 7485 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7486 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7487 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7488 if (heic == 0 || !msr_hv || msr_pr) { 7489 return true; 7490 } 7491 } 7492 /* Decrementer Exception */ 7493 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7494 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7495 return true; 7496 } 7497 /* Machine Check or Hypervisor Maintenance Exception */ 7498 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7499 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7500 return true; 7501 } 7502 /* Privileged Doorbell Exception */ 7503 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7504 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7505 return true; 7506 } 7507 /* Hypervisor Doorbell Exception */ 7508 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7509 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7510 return true; 7511 } 7512 /* Hypervisor virtualization exception */ 7513 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7514 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7515 return true; 7516 } 7517 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7518 return true; 7519 } 7520 return false; 7521 } else { 7522 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7523 } 7524 } 7525 7526 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7527 { 7528 DeviceClass *dc = DEVICE_CLASS(oc); 7529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7530 CPUClass *cc = CPU_CLASS(oc); 7531 7532 dc->fw_name = "PowerPC,POWER10"; 7533 dc->desc = "POWER10"; 7534 pcc->pvr_match = ppc_pvr_match_power10; 7535 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7536 PCR_COMPAT_3_00; 7537 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7538 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7539 pcc->init_proc = init_proc_POWER10; 7540 pcc->check_pow = check_pow_nocheck; 7541 cc->has_work = cpu_has_work_POWER10; 7542 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7543 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7544 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7545 PPC_FLOAT_FRSQRTES | 7546 PPC_FLOAT_STFIWX | 7547 PPC_FLOAT_EXT | 7548 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7549 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7550 PPC_MEM_TLBSYNC | 7551 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7552 PPC_SEGMENT_64B | PPC_SLBI | 7553 PPC_POPCNTB | PPC_POPCNTWD | 7554 PPC_CILDST; 7555 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7556 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7557 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7558 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7559 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7560 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7561 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7562 pcc->msr_mask = (1ull << MSR_SF) | 7563 (1ull << MSR_HV) | 7564 (1ull << MSR_TM) | 7565 (1ull << MSR_VR) | 7566 (1ull << MSR_VSX) | 7567 (1ull << MSR_EE) | 7568 (1ull << MSR_PR) | 7569 (1ull << MSR_FP) | 7570 (1ull << MSR_ME) | 7571 (1ull << MSR_FE0) | 7572 (1ull << MSR_SE) | 7573 (1ull << MSR_DE) | 7574 (1ull << MSR_FE1) | 7575 (1ull << MSR_IR) | 7576 (1ull << MSR_DR) | 7577 (1ull << MSR_PMM) | 7578 (1ull << MSR_RI) | 7579 (1ull << MSR_LE); 7580 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7581 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7582 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7583 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7584 LPCR_DEE | LPCR_OEE)) 7585 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7586 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7587 /* DD2 adds an extra HAIL bit */ 7588 pcc->lpcr_mask |= LPCR_HAIL; 7589 7590 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7591 pcc->mmu_model = POWERPC_MMU_3_00; 7592 #if defined(CONFIG_SOFTMMU) 7593 /* segment page size remain the same */ 7594 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7595 pcc->radix_page_info = &POWER10_radix_page_info; 7596 pcc->lrg_decr_bits = 56; 7597 #endif 7598 pcc->excp_model = POWERPC_EXCP_POWER10; 7599 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7600 pcc->bfd_mach = bfd_mach_ppc64; 7601 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7602 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7603 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7604 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7605 pcc->l1_dcache_size = 0x8000; 7606 pcc->l1_icache_size = 0x8000; 7607 } 7608 7609 #if !defined(CONFIG_USER_ONLY) 7610 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7611 { 7612 CPUPPCState *env = &cpu->env; 7613 7614 cpu->vhyp = vhyp; 7615 7616 /* 7617 * With a virtual hypervisor mode we never allow the CPU to go 7618 * hypervisor mode itself 7619 */ 7620 env->msr_mask &= ~MSR_HVB; 7621 } 7622 7623 #endif /* !defined(CONFIG_USER_ONLY) */ 7624 7625 #endif /* defined(TARGET_PPC64) */ 7626 7627 /*****************************************************************************/ 7628 /* Generic CPU instantiation routine */ 7629 static void init_ppc_proc(PowerPCCPU *cpu) 7630 { 7631 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7632 CPUPPCState *env = &cpu->env; 7633 #if !defined(CONFIG_USER_ONLY) 7634 int i; 7635 7636 env->irq_inputs = NULL; 7637 /* Set all exception vectors to an invalid address */ 7638 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7639 env->excp_vectors[i] = (target_ulong)(-1ULL); 7640 } 7641 env->ivor_mask = 0x00000000; 7642 env->ivpr_mask = 0x00000000; 7643 /* Default MMU definitions */ 7644 env->nb_BATs = 0; 7645 env->nb_tlb = 0; 7646 env->nb_ways = 0; 7647 env->tlb_type = TLB_NONE; 7648 #endif 7649 /* Register SPR common to all PowerPC implementations */ 7650 register_generic_sprs(env); 7651 spr_register(env, SPR_PVR, "PVR", 7652 /* Linux permits userspace to read PVR */ 7653 #if defined(CONFIG_LINUX_USER) 7654 &spr_read_generic, 7655 #else 7656 SPR_NOACCESS, 7657 #endif 7658 SPR_NOACCESS, 7659 &spr_read_generic, SPR_NOACCESS, 7660 pcc->pvr); 7661 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7662 if (pcc->svr != POWERPC_SVR_NONE) { 7663 if (pcc->svr & POWERPC_SVR_E500) { 7664 spr_register(env, SPR_E500_SVR, "SVR", 7665 SPR_NOACCESS, SPR_NOACCESS, 7666 &spr_read_generic, SPR_NOACCESS, 7667 pcc->svr & ~POWERPC_SVR_E500); 7668 } else { 7669 spr_register(env, SPR_SVR, "SVR", 7670 SPR_NOACCESS, SPR_NOACCESS, 7671 &spr_read_generic, SPR_NOACCESS, 7672 pcc->svr); 7673 } 7674 } 7675 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7676 (*pcc->init_proc)(env); 7677 7678 #if !defined(CONFIG_USER_ONLY) 7679 ppc_gdb_gen_spr_xml(cpu); 7680 #endif 7681 7682 /* MSR bits & flags consistency checks */ 7683 if (env->msr_mask & (1 << 25)) { 7684 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7685 case POWERPC_FLAG_SPE: 7686 case POWERPC_FLAG_VRE: 7687 break; 7688 default: 7689 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7690 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7691 exit(1); 7692 } 7693 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7694 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7695 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7696 exit(1); 7697 } 7698 if (env->msr_mask & (1 << 17)) { 7699 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7700 case POWERPC_FLAG_TGPR: 7701 case POWERPC_FLAG_CE: 7702 break; 7703 default: 7704 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7705 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7706 exit(1); 7707 } 7708 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7709 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7710 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7711 exit(1); 7712 } 7713 if (env->msr_mask & (1 << 10)) { 7714 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7715 POWERPC_FLAG_UBLE)) { 7716 case POWERPC_FLAG_SE: 7717 case POWERPC_FLAG_DWE: 7718 case POWERPC_FLAG_UBLE: 7719 break; 7720 default: 7721 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7722 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7723 "POWERPC_FLAG_UBLE\n"); 7724 exit(1); 7725 } 7726 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7727 POWERPC_FLAG_UBLE)) { 7728 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7729 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7730 "POWERPC_FLAG_UBLE\n"); 7731 exit(1); 7732 } 7733 if (env->msr_mask & (1 << 9)) { 7734 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7735 case POWERPC_FLAG_BE: 7736 case POWERPC_FLAG_DE: 7737 break; 7738 default: 7739 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7740 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7741 exit(1); 7742 } 7743 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7744 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7745 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7746 exit(1); 7747 } 7748 if (env->msr_mask & (1 << 2)) { 7749 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7750 case POWERPC_FLAG_PX: 7751 case POWERPC_FLAG_PMM: 7752 break; 7753 default: 7754 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7755 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7756 exit(1); 7757 } 7758 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7759 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7760 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7761 exit(1); 7762 } 7763 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 7764 fprintf(stderr, "PowerPC flags inconsistency\n" 7765 "Should define the time-base and decrementer clock source\n"); 7766 exit(1); 7767 } 7768 /* Allocate TLBs buffer when needed */ 7769 #if !defined(CONFIG_USER_ONLY) 7770 if (env->nb_tlb != 0) { 7771 int nb_tlb = env->nb_tlb; 7772 if (env->id_tlbs != 0) { 7773 nb_tlb *= 2; 7774 } 7775 switch (env->tlb_type) { 7776 case TLB_6XX: 7777 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7778 break; 7779 case TLB_EMB: 7780 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7781 break; 7782 case TLB_MAS: 7783 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7784 break; 7785 } 7786 /* Pre-compute some useful values */ 7787 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7788 } 7789 if (env->irq_inputs == NULL) { 7790 warn_report("no internal IRQ controller registered." 7791 " Attempt QEMU to crash very soon !"); 7792 } 7793 #endif 7794 if (env->check_pow == NULL) { 7795 warn_report("no power management check handler registered." 7796 " Attempt QEMU to crash very soon !"); 7797 } 7798 } 7799 7800 7801 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7802 { 7803 CPUState *cs = CPU(dev); 7804 PowerPCCPU *cpu = POWERPC_CPU(dev); 7805 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7806 Error *local_err = NULL; 7807 7808 cpu_exec_realizefn(cs, &local_err); 7809 if (local_err != NULL) { 7810 error_propagate(errp, local_err); 7811 return; 7812 } 7813 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7814 cpu->vcpu_id = cs->cpu_index; 7815 } 7816 7817 if (tcg_enabled()) { 7818 if (ppc_fixup_cpu(cpu) != 0) { 7819 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7820 goto unrealize; 7821 } 7822 } 7823 7824 create_ppc_opcodes(cpu, &local_err); 7825 if (local_err != NULL) { 7826 error_propagate(errp, local_err); 7827 goto unrealize; 7828 } 7829 init_ppc_proc(cpu); 7830 7831 ppc_gdb_init(cs, pcc); 7832 qemu_init_vcpu(cs); 7833 7834 pcc->parent_realize(dev, errp); 7835 7836 return; 7837 7838 unrealize: 7839 cpu_exec_unrealizefn(cs); 7840 } 7841 7842 static void ppc_cpu_unrealize(DeviceState *dev) 7843 { 7844 PowerPCCPU *cpu = POWERPC_CPU(dev); 7845 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7846 7847 pcc->parent_unrealize(dev); 7848 7849 cpu_remove_sync(CPU(cpu)); 7850 7851 destroy_ppc_opcodes(cpu); 7852 } 7853 7854 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7855 { 7856 ObjectClass *oc = (ObjectClass *)a; 7857 uint32_t pvr = *(uint32_t *)b; 7858 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7859 7860 /* -cpu host does a PVR lookup during construction */ 7861 if (unlikely(strcmp(object_class_get_name(oc), 7862 TYPE_HOST_POWERPC_CPU) == 0)) { 7863 return -1; 7864 } 7865 7866 return pcc->pvr == pvr ? 0 : -1; 7867 } 7868 7869 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7870 { 7871 GSList *list, *item; 7872 PowerPCCPUClass *pcc = NULL; 7873 7874 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7875 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7876 if (item != NULL) { 7877 pcc = POWERPC_CPU_CLASS(item->data); 7878 } 7879 g_slist_free(list); 7880 7881 return pcc; 7882 } 7883 7884 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7885 { 7886 ObjectClass *oc = (ObjectClass *)a; 7887 uint32_t pvr = *(uint32_t *)b; 7888 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7889 7890 /* -cpu host does a PVR lookup during construction */ 7891 if (unlikely(strcmp(object_class_get_name(oc), 7892 TYPE_HOST_POWERPC_CPU) == 0)) { 7893 return -1; 7894 } 7895 7896 if (pcc->pvr_match(pcc, pvr)) { 7897 return 0; 7898 } 7899 7900 return -1; 7901 } 7902 7903 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7904 { 7905 GSList *list, *item; 7906 PowerPCCPUClass *pcc = NULL; 7907 7908 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7909 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7910 if (item != NULL) { 7911 pcc = POWERPC_CPU_CLASS(item->data); 7912 } 7913 g_slist_free(list); 7914 7915 return pcc; 7916 } 7917 7918 static const char *ppc_cpu_lookup_alias(const char *alias) 7919 { 7920 int ai; 7921 7922 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7923 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7924 return ppc_cpu_aliases[ai].model; 7925 } 7926 } 7927 7928 return NULL; 7929 } 7930 7931 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7932 { 7933 char *cpu_model, *typename; 7934 ObjectClass *oc; 7935 const char *p; 7936 unsigned long pvr; 7937 7938 /* 7939 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7940 * 0x prefix if present) 7941 */ 7942 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7943 int len = p - name; 7944 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7945 if ((len == 8) && (*p == '\0')) { 7946 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7947 } 7948 } 7949 7950 cpu_model = g_ascii_strdown(name, -1); 7951 p = ppc_cpu_lookup_alias(cpu_model); 7952 if (p) { 7953 g_free(cpu_model); 7954 cpu_model = g_strdup(p); 7955 } 7956 7957 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7958 oc = object_class_by_name(typename); 7959 g_free(typename); 7960 g_free(cpu_model); 7961 7962 return oc; 7963 } 7964 7965 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7966 { 7967 ObjectClass *oc = OBJECT_CLASS(pcc); 7968 7969 while (oc && !object_class_is_abstract(oc)) { 7970 oc = object_class_get_parent(oc); 7971 } 7972 assert(oc); 7973 7974 return POWERPC_CPU_CLASS(oc); 7975 } 7976 7977 /* Sort by PVR, ordering special case "host" last. */ 7978 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7979 { 7980 ObjectClass *oc_a = (ObjectClass *)a; 7981 ObjectClass *oc_b = (ObjectClass *)b; 7982 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7983 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7984 const char *name_a = object_class_get_name(oc_a); 7985 const char *name_b = object_class_get_name(oc_b); 7986 7987 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7988 return 1; 7989 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7990 return -1; 7991 } else { 7992 /* Avoid an integer overflow during subtraction */ 7993 if (pcc_a->pvr < pcc_b->pvr) { 7994 return -1; 7995 } else if (pcc_a->pvr > pcc_b->pvr) { 7996 return 1; 7997 } else { 7998 return 0; 7999 } 8000 } 8001 } 8002 8003 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8004 { 8005 ObjectClass *oc = data; 8006 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8007 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8008 const char *typename = object_class_get_name(oc); 8009 char *name; 8010 int i; 8011 8012 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8013 return; 8014 } 8015 8016 name = g_strndup(typename, 8017 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8018 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8019 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8020 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8021 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8022 8023 if (alias_oc != oc) { 8024 continue; 8025 } 8026 /* 8027 * If running with KVM, we might update the family alias later, so 8028 * avoid printing the wrong alias here and use "preferred" instead 8029 */ 8030 if (strcmp(alias->alias, family->desc) == 0) { 8031 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8032 alias->alias, family->desc); 8033 } else { 8034 qemu_printf("PowerPC %-16s (alias for %s)\n", 8035 alias->alias, name); 8036 } 8037 } 8038 g_free(name); 8039 } 8040 8041 void ppc_cpu_list(void) 8042 { 8043 GSList *list; 8044 8045 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8046 list = g_slist_sort(list, ppc_cpu_list_compare); 8047 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 8048 g_slist_free(list); 8049 8050 #ifdef CONFIG_KVM 8051 qemu_printf("\n"); 8052 qemu_printf("PowerPC %s\n", "host"); 8053 #endif 8054 } 8055 8056 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 8057 { 8058 ObjectClass *oc = data; 8059 CpuDefinitionInfoList **first = user_data; 8060 const char *typename; 8061 CpuDefinitionInfo *info; 8062 8063 typename = object_class_get_name(oc); 8064 info = g_malloc0(sizeof(*info)); 8065 info->name = g_strndup(typename, 8066 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8067 8068 QAPI_LIST_PREPEND(*first, info); 8069 } 8070 8071 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8072 { 8073 CpuDefinitionInfoList *cpu_list = NULL; 8074 GSList *list; 8075 int i; 8076 8077 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8078 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 8079 g_slist_free(list); 8080 8081 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8082 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8083 ObjectClass *oc; 8084 CpuDefinitionInfo *info; 8085 8086 oc = ppc_cpu_class_by_name(alias->model); 8087 if (oc == NULL) { 8088 continue; 8089 } 8090 8091 info = g_malloc0(sizeof(*info)); 8092 info->name = g_strdup(alias->alias); 8093 info->q_typename = g_strdup(object_class_get_name(oc)); 8094 8095 QAPI_LIST_PREPEND(cpu_list, info); 8096 } 8097 8098 return cpu_list; 8099 } 8100 8101 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8102 { 8103 PowerPCCPU *cpu = POWERPC_CPU(cs); 8104 8105 cpu->env.nip = value; 8106 } 8107 8108 static bool ppc_cpu_has_work(CPUState *cs) 8109 { 8110 PowerPCCPU *cpu = POWERPC_CPU(cs); 8111 CPUPPCState *env = &cpu->env; 8112 8113 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8114 } 8115 8116 static void ppc_cpu_reset(DeviceState *dev) 8117 { 8118 CPUState *s = CPU(dev); 8119 PowerPCCPU *cpu = POWERPC_CPU(s); 8120 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8121 CPUPPCState *env = &cpu->env; 8122 target_ulong msr; 8123 int i; 8124 8125 pcc->parent_reset(dev); 8126 8127 msr = (target_ulong)0; 8128 msr |= (target_ulong)MSR_HVB; 8129 msr |= (target_ulong)1 << MSR_EP; 8130 #if defined(DO_SINGLE_STEP) && 0 8131 /* Single step trace mode */ 8132 msr |= (target_ulong)1 << MSR_SE; 8133 msr |= (target_ulong)1 << MSR_BE; 8134 #endif 8135 #if defined(CONFIG_USER_ONLY) 8136 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8137 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8138 msr |= (target_ulong)1 << MSR_FE1; 8139 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8140 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8141 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8142 msr |= (target_ulong)1 << MSR_PR; 8143 #if defined(TARGET_PPC64) 8144 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8145 #endif 8146 #if !defined(TARGET_WORDS_BIGENDIAN) 8147 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8148 if (!((env->msr_mask >> MSR_LE) & 1)) { 8149 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8150 exit(1); 8151 } 8152 #endif 8153 #endif 8154 8155 #if defined(TARGET_PPC64) 8156 if (mmu_is_64bit(env->mmu_model)) { 8157 msr |= (1ULL << MSR_SF); 8158 } 8159 #endif 8160 8161 hreg_store_msr(env, msr, 1); 8162 8163 #if !defined(CONFIG_USER_ONLY) 8164 env->nip = env->hreset_vector | env->excp_prefix; 8165 #if defined(CONFIG_TCG) 8166 if (env->mmu_model != POWERPC_MMU_REAL) { 8167 ppc_tlb_invalidate_all(env); 8168 } 8169 #endif /* CONFIG_TCG */ 8170 #endif 8171 8172 pmu_update_summaries(env); 8173 hreg_compute_hflags(env); 8174 env->reserve_addr = (target_ulong)-1ULL; 8175 /* Be sure no exception or interrupt is pending */ 8176 env->pending_interrupts = 0; 8177 s->exception_index = POWERPC_EXCP_NONE; 8178 env->error_code = 0; 8179 ppc_irq_reset(cpu); 8180 8181 /* tininess for underflow is detected before rounding */ 8182 set_float_detect_tininess(float_tininess_before_rounding, 8183 &env->fp_status); 8184 8185 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8186 ppc_spr_t *spr = &env->spr_cb[i]; 8187 8188 if (!spr->name) { 8189 continue; 8190 } 8191 env->spr[i] = spr->default_value; 8192 } 8193 } 8194 8195 #ifndef CONFIG_USER_ONLY 8196 8197 static bool ppc_cpu_is_big_endian(CPUState *cs) 8198 { 8199 PowerPCCPU *cpu = POWERPC_CPU(cs); 8200 CPUPPCState *env = &cpu->env; 8201 8202 cpu_synchronize_state(cs); 8203 8204 return !msr_le; 8205 } 8206 8207 #ifdef CONFIG_TCG 8208 static void ppc_cpu_exec_enter(CPUState *cs) 8209 { 8210 PowerPCCPU *cpu = POWERPC_CPU(cs); 8211 8212 if (cpu->vhyp) { 8213 PPCVirtualHypervisorClass *vhc = 8214 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8215 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8216 } 8217 } 8218 8219 static void ppc_cpu_exec_exit(CPUState *cs) 8220 { 8221 PowerPCCPU *cpu = POWERPC_CPU(cs); 8222 8223 if (cpu->vhyp) { 8224 PPCVirtualHypervisorClass *vhc = 8225 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8226 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8227 } 8228 } 8229 #endif /* CONFIG_TCG */ 8230 8231 #endif /* !CONFIG_USER_ONLY */ 8232 8233 static void ppc_cpu_instance_init(Object *obj) 8234 { 8235 PowerPCCPU *cpu = POWERPC_CPU(obj); 8236 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8237 CPUPPCState *env = &cpu->env; 8238 8239 cpu_set_cpustate_pointers(cpu); 8240 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8241 8242 env->msr_mask = pcc->msr_mask; 8243 env->mmu_model = pcc->mmu_model; 8244 env->excp_model = pcc->excp_model; 8245 env->bus_model = pcc->bus_model; 8246 env->insns_flags = pcc->insns_flags; 8247 env->insns_flags2 = pcc->insns_flags2; 8248 env->flags = pcc->flags; 8249 env->bfd_mach = pcc->bfd_mach; 8250 env->check_pow = pcc->check_pow; 8251 8252 /* 8253 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8254 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8255 * mode support will remain, thus enforcing that we cannot use 8256 * priv. instructions in guest in PAPR mode. For 970 we currently 8257 * simply don't set HV in msr_mask thus simulating an "Apple mode" 8258 * 970. If we ever want to support 970 HV mode, we'll have to add 8259 * a processor attribute of some sort. 8260 */ 8261 #if !defined(CONFIG_USER_ONLY) 8262 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 8263 #endif 8264 8265 ppc_hash64_init(cpu); 8266 } 8267 8268 static void ppc_cpu_instance_finalize(Object *obj) 8269 { 8270 PowerPCCPU *cpu = POWERPC_CPU(obj); 8271 8272 ppc_hash64_finalize(cpu); 8273 } 8274 8275 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 8276 { 8277 return pcc->pvr == pvr; 8278 } 8279 8280 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 8281 { 8282 PowerPCCPU *cpu = POWERPC_CPU(cs); 8283 CPUPPCState *env = &cpu->env; 8284 8285 if ((env->hflags >> MSR_LE) & 1) { 8286 info->endian = BFD_ENDIAN_LITTLE; 8287 } 8288 info->mach = env->bfd_mach; 8289 if (!env->bfd_mach) { 8290 #ifdef TARGET_PPC64 8291 info->mach = bfd_mach_ppc64; 8292 #else 8293 info->mach = bfd_mach_ppc; 8294 #endif 8295 } 8296 info->disassembler_options = (char *)"any"; 8297 info->print_insn = print_insn_ppc; 8298 8299 info->cap_arch = CS_ARCH_PPC; 8300 #ifdef TARGET_PPC64 8301 info->cap_mode = CS_MODE_64; 8302 #endif 8303 } 8304 8305 static Property ppc_cpu_properties[] = { 8306 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 8307 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 8308 false), 8309 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 8310 false), 8311 DEFINE_PROP_END_OF_LIST(), 8312 }; 8313 8314 #ifndef CONFIG_USER_ONLY 8315 #include "hw/core/sysemu-cpu-ops.h" 8316 8317 static const struct SysemuCPUOps ppc_sysemu_ops = { 8318 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 8319 .write_elf32_note = ppc32_cpu_write_elf32_note, 8320 .write_elf64_note = ppc64_cpu_write_elf64_note, 8321 .virtio_is_big_endian = ppc_cpu_is_big_endian, 8322 .legacy_vmsd = &vmstate_ppc_cpu, 8323 }; 8324 #endif 8325 8326 #ifdef CONFIG_TCG 8327 #include "hw/core/tcg-cpu-ops.h" 8328 8329 static const struct TCGCPUOps ppc_tcg_ops = { 8330 .initialize = ppc_translate_init, 8331 8332 #ifdef CONFIG_USER_ONLY 8333 .record_sigsegv = ppc_cpu_record_sigsegv, 8334 #else 8335 .tlb_fill = ppc_cpu_tlb_fill, 8336 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 8337 .do_interrupt = ppc_cpu_do_interrupt, 8338 .cpu_exec_enter = ppc_cpu_exec_enter, 8339 .cpu_exec_exit = ppc_cpu_exec_exit, 8340 .do_unaligned_access = ppc_cpu_do_unaligned_access, 8341 #endif /* !CONFIG_USER_ONLY */ 8342 }; 8343 #endif /* CONFIG_TCG */ 8344 8345 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 8346 { 8347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8348 CPUClass *cc = CPU_CLASS(oc); 8349 DeviceClass *dc = DEVICE_CLASS(oc); 8350 8351 device_class_set_parent_realize(dc, ppc_cpu_realize, 8352 &pcc->parent_realize); 8353 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 8354 &pcc->parent_unrealize); 8355 pcc->pvr_match = ppc_pvr_match_default; 8356 device_class_set_props(dc, ppc_cpu_properties); 8357 8358 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 8359 8360 cc->class_by_name = ppc_cpu_class_by_name; 8361 cc->has_work = ppc_cpu_has_work; 8362 cc->dump_state = ppc_cpu_dump_state; 8363 cc->set_pc = ppc_cpu_set_pc; 8364 cc->gdb_read_register = ppc_cpu_gdb_read_register; 8365 cc->gdb_write_register = ppc_cpu_gdb_write_register; 8366 #ifndef CONFIG_USER_ONLY 8367 cc->sysemu_ops = &ppc_sysemu_ops; 8368 #endif 8369 8370 cc->gdb_num_core_regs = 71; 8371 #ifndef CONFIG_USER_ONLY 8372 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 8373 #endif 8374 #ifdef USE_APPLE_GDB 8375 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 8376 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 8377 cc->gdb_num_core_regs = 71 + 32; 8378 #endif 8379 8380 cc->gdb_arch_name = ppc_gdb_arch_name; 8381 #if defined(TARGET_PPC64) 8382 cc->gdb_core_xml_file = "power64-core.xml"; 8383 #else 8384 cc->gdb_core_xml_file = "power-core.xml"; 8385 #endif 8386 cc->disas_set_info = ppc_disas_set_info; 8387 8388 dc->fw_name = "PowerPC,UNKNOWN"; 8389 8390 #ifdef CONFIG_TCG 8391 cc->tcg_ops = &ppc_tcg_ops; 8392 #endif /* CONFIG_TCG */ 8393 } 8394 8395 static const TypeInfo ppc_cpu_type_info = { 8396 .name = TYPE_POWERPC_CPU, 8397 .parent = TYPE_CPU, 8398 .instance_size = sizeof(PowerPCCPU), 8399 .instance_align = __alignof__(PowerPCCPU), 8400 .instance_init = ppc_cpu_instance_init, 8401 .instance_finalize = ppc_cpu_instance_finalize, 8402 .abstract = true, 8403 .class_size = sizeof(PowerPCCPUClass), 8404 .class_init = ppc_cpu_class_init, 8405 }; 8406 8407 #ifndef CONFIG_USER_ONLY 8408 static const TypeInfo ppc_vhyp_type_info = { 8409 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8410 .parent = TYPE_INTERFACE, 8411 .class_size = sizeof(PPCVirtualHypervisorClass), 8412 }; 8413 #endif 8414 8415 static void ppc_cpu_register_types(void) 8416 { 8417 type_register_static(&ppc_cpu_type_info); 8418 #ifndef CONFIG_USER_ONLY 8419 type_register_static(&ppc_vhyp_type_info); 8420 #endif 8421 } 8422 8423 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8424 { 8425 #define RGPL 4 8426 #define RFPL 4 8427 8428 PowerPCCPU *cpu = POWERPC_CPU(cs); 8429 CPUPPCState *env = &cpu->env; 8430 int i; 8431 8432 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8433 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8434 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8435 cs->cpu_index); 8436 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8437 "%08x iidx %d didx %d\n", 8438 env->msr, env->spr[SPR_HID0], env->hflags, 8439 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8440 #if !defined(NO_TIMER_DUMP) 8441 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8442 #if !defined(CONFIG_USER_ONLY) 8443 " DECR " TARGET_FMT_lu 8444 #endif 8445 "\n", 8446 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8447 #if !defined(CONFIG_USER_ONLY) 8448 , cpu_ppc_load_decr(env) 8449 #endif 8450 ); 8451 #endif 8452 for (i = 0; i < 32; i++) { 8453 if ((i & (RGPL - 1)) == 0) { 8454 qemu_fprintf(f, "GPR%02d", i); 8455 } 8456 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8457 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8458 qemu_fprintf(f, "\n"); 8459 } 8460 } 8461 qemu_fprintf(f, "CR "); 8462 for (i = 0; i < 8; i++) 8463 qemu_fprintf(f, "%01x", env->crf[i]); 8464 qemu_fprintf(f, " ["); 8465 for (i = 0; i < 8; i++) { 8466 char a = '-'; 8467 if (env->crf[i] & 0x08) { 8468 a = 'L'; 8469 } else if (env->crf[i] & 0x04) { 8470 a = 'G'; 8471 } else if (env->crf[i] & 0x02) { 8472 a = 'E'; 8473 } 8474 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8475 } 8476 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8477 env->reserve_addr); 8478 8479 if (flags & CPU_DUMP_FPU) { 8480 for (i = 0; i < 32; i++) { 8481 if ((i & (RFPL - 1)) == 0) { 8482 qemu_fprintf(f, "FPR%02d", i); 8483 } 8484 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8485 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8486 qemu_fprintf(f, "\n"); 8487 } 8488 } 8489 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8490 } 8491 8492 #if !defined(CONFIG_USER_ONLY) 8493 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8494 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8495 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8496 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8497 8498 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8499 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8500 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8501 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8502 8503 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8504 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8505 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8506 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8507 8508 switch (env->excp_model) { 8509 #if defined(TARGET_PPC64) 8510 case POWERPC_EXCP_POWER7: 8511 case POWERPC_EXCP_POWER8: 8512 case POWERPC_EXCP_POWER9: 8513 case POWERPC_EXCP_POWER10: 8514 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8515 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8516 break; 8517 #endif 8518 case POWERPC_EXCP_BOOKE: 8519 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8520 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8521 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8522 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8523 8524 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8525 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8526 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8527 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8528 8529 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8530 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8531 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8532 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8533 8534 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8535 " EPR " TARGET_FMT_lx "\n", 8536 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8537 env->spr[SPR_BOOKE_EPR]); 8538 8539 /* FSL-specific */ 8540 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8541 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8542 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8543 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8544 8545 /* 8546 * IVORs are left out as they are large and do not change often -- 8547 * they can be read with "p $ivor0", "p $ivor1", etc. 8548 */ 8549 break; 8550 case POWERPC_EXCP_40x: 8551 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8552 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8553 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8554 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8555 8556 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8557 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8558 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8559 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8560 break; 8561 default: 8562 break; 8563 } 8564 8565 #if defined(TARGET_PPC64) 8566 if (env->flags & POWERPC_FLAG_CFAR) { 8567 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8568 } 8569 #endif 8570 8571 if (env->spr_cb[SPR_LPCR].name) { 8572 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8573 } 8574 8575 switch (env->mmu_model) { 8576 case POWERPC_MMU_32B: 8577 case POWERPC_MMU_601: 8578 case POWERPC_MMU_SOFT_6xx: 8579 #if defined(TARGET_PPC64) 8580 case POWERPC_MMU_64B: 8581 case POWERPC_MMU_2_03: 8582 case POWERPC_MMU_2_06: 8583 case POWERPC_MMU_2_07: 8584 case POWERPC_MMU_3_00: 8585 #endif 8586 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8587 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8588 } 8589 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8590 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8591 } 8592 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8593 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8594 break; 8595 case POWERPC_MMU_BOOKE206: 8596 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8597 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8598 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8599 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8600 8601 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8602 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8603 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8604 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8605 8606 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8607 " TLB1CFG " TARGET_FMT_lx "\n", 8608 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8609 env->spr[SPR_BOOKE_TLB1CFG]); 8610 break; 8611 default: 8612 break; 8613 } 8614 #endif 8615 8616 #undef RGPL 8617 #undef RFPL 8618 } 8619 type_init(ppc_cpu_register_types) 8620