xref: /openbmc/qemu/target/ppc/cpu_init.c (revision 11906557) 
1 /*
2  *  PowerPC CPU initialization for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *  Copyright 2011 Freescale Semiconductor, Inc.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/hw_accel.h"
28 #include "sysemu/tcg.h"
29 #include "cpu-models.h"
30 #include "mmu-hash32.h"
31 #include "mmu-hash64.h"
32 #include "qemu/error-report.h"
33 #include "qemu/module.h"
34 #include "qemu/qemu-print.h"
35 #include "qapi/error.h"
36 #include "qapi/qmp/qnull.h"
37 #include "qapi/visitor.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/ppc/ppc.h"
40 #include "mmu-book3s-v3.h"
41 #include "qemu/cutils.h"
42 #include "disas/capstone.h"
43 #include "fpu/softfloat.h"
44 #include "qapi/qapi-commands-machine-target.h"
45 
46 #include "exec/helper-proto.h"
47 #include "helper_regs.h"
48 #include "internal.h"
49 #include "spr_tcg.h"
50 
51 /* #define PPC_DEBUG_SPR */
52 /* #define USE_APPLE_GDB */
53 
54 static inline void vscr_init(CPUPPCState *env, uint32_t val)
55 {
56     /* Altivec always uses round-to-nearest */
57     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
58     ppc_store_vscr(env, val);
59 }
60 
61 /**
62  * _spr_register
63  *
64  * Register an SPR with all the callbacks required for tcg,
65  * and the ID number for KVM.
66  *
67  * The reason for the conditional compilation is that the tcg functions
68  * may be compiled out, and the system kvm header may not be available
69  * for supplying the ID numbers.  This is ugly, but the best we can do.
70  */
71 
72 #ifdef CONFIG_TCG
73 # define USR_ARG(X)    X,
74 # ifdef CONFIG_USER_ONLY
75 #  define SYS_ARG(X)
76 # else
77 #  define SYS_ARG(X)   X,
78 # endif
79 #else
80 # define USR_ARG(X)
81 # define SYS_ARG(X)
82 #endif
83 #ifdef CONFIG_KVM
84 # define KVM_ARG(X)    X,
85 #else
86 # define KVM_ARG(X)
87 #endif
88 
89 typedef void spr_callback(DisasContext *, int, int);
90 
91 static void _spr_register(CPUPPCState *env, int num, const char *name,
92                           USR_ARG(spr_callback *uea_read)
93                           USR_ARG(spr_callback *uea_write)
94                           SYS_ARG(spr_callback *oea_read)
95                           SYS_ARG(spr_callback *oea_write)
96                           SYS_ARG(spr_callback *hea_read)
97                           SYS_ARG(spr_callback *hea_write)
98                           KVM_ARG(uint64_t one_reg_id)
99                           target_ulong initial_value)
100 {
101     ppc_spr_t *spr = &env->spr_cb[num];
102 
103     /* No SPR should be registered twice. */
104     assert(spr->name == NULL);
105     assert(name != NULL);
106 
107     spr->name = name;
108     spr->default_value = initial_value;
109     env->spr[num] = initial_value;
110 
111 #ifdef CONFIG_TCG
112     spr->uea_read = uea_read;
113     spr->uea_write = uea_write;
114 # ifndef CONFIG_USER_ONLY
115     spr->oea_read = oea_read;
116     spr->oea_write = oea_write;
117     spr->hea_read = hea_read;
118     spr->hea_write = hea_write;
119 # endif
120 #endif
121 #ifdef CONFIG_KVM
122     spr->one_reg_id = one_reg_id;
123 #endif
124 }
125 
126 /* spr_register_kvm_hv passes all required arguments. */
127 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write,             \
128                             oea_read, oea_write, hea_read, hea_write,        \
129                             one_reg_id, initial_value)                       \
130     _spr_register(env, num, name,                                            \
131                   USR_ARG(uea_read) USR_ARG(uea_write)                       \
132                   SYS_ARG(oea_read) SYS_ARG(oea_write)                       \
133                   SYS_ARG(hea_read) SYS_ARG(hea_write)                       \
134                   KVM_ARG(one_reg_id) initial_value)
135 
136 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
137 #define spr_register_kvm(env, num, name, uea_read, uea_write,                \
138                          oea_read, oea_write, one_reg_id, ival)              \
139     spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read,       \
140                         oea_write, oea_read, oea_write, one_reg_id, ival)
141 
142 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
143 #define spr_register_hv(env, num, name, uea_read, uea_write,                 \
144                         oea_read, oea_write, hea_read, hea_write, ival)      \
145     spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read,       \
146                         oea_write, hea_read, hea_write, 0, ival)
147 
148 #define spr_register(env, num, name, uea_read, uea_write,                    \
149                      oea_read, oea_write, ival)                              \
150     spr_register_kvm(env, num, name, uea_read, uea_write,                    \
151                      oea_read, oea_write, 0, ival)
152 
153 /* Generic PowerPC SPRs */
154 static void register_generic_sprs(CPUPPCState *env)
155 {
156     /* Integer processing */
157     spr_register(env, SPR_XER, "XER",
158                  &spr_read_xer, &spr_write_xer,
159                  &spr_read_xer, &spr_write_xer,
160                  0x00000000);
161     /* Branch control */
162     spr_register(env, SPR_LR, "LR",
163                  &spr_read_lr, &spr_write_lr,
164                  &spr_read_lr, &spr_write_lr,
165                  0x00000000);
166     spr_register(env, SPR_CTR, "CTR",
167                  &spr_read_ctr, &spr_write_ctr,
168                  &spr_read_ctr, &spr_write_ctr,
169                  0x00000000);
170     /* Interrupt processing */
171     spr_register(env, SPR_SRR0, "SRR0",
172                  SPR_NOACCESS, SPR_NOACCESS,
173                  &spr_read_generic, &spr_write_generic,
174                  0x00000000);
175     spr_register(env, SPR_SRR1, "SRR1",
176                  SPR_NOACCESS, SPR_NOACCESS,
177                  &spr_read_generic, &spr_write_generic,
178                  0x00000000);
179     /* Processor control */
180     spr_register(env, SPR_SPRG0, "SPRG0",
181                  SPR_NOACCESS, SPR_NOACCESS,
182                  &spr_read_generic, &spr_write_generic,
183                  0x00000000);
184     spr_register(env, SPR_SPRG1, "SPRG1",
185                  SPR_NOACCESS, SPR_NOACCESS,
186                  &spr_read_generic, &spr_write_generic,
187                  0x00000000);
188     spr_register(env, SPR_SPRG2, "SPRG2",
189                  SPR_NOACCESS, SPR_NOACCESS,
190                  &spr_read_generic, &spr_write_generic,
191                  0x00000000);
192     spr_register(env, SPR_SPRG3, "SPRG3",
193                  SPR_NOACCESS, SPR_NOACCESS,
194                  &spr_read_generic, &spr_write_generic,
195                  0x00000000);
196 }
197 
198 /* SPR common to all non-embedded PowerPC, including 601 */
199 static void register_ne_601_sprs(CPUPPCState *env)
200 {
201     /* Exception processing */
202     spr_register_kvm(env, SPR_DSISR, "DSISR",
203                      SPR_NOACCESS, SPR_NOACCESS,
204                      &spr_read_generic, &spr_write_generic,
205                      KVM_REG_PPC_DSISR, 0x00000000);
206     spr_register_kvm(env, SPR_DAR, "DAR",
207                      SPR_NOACCESS, SPR_NOACCESS,
208                      &spr_read_generic, &spr_write_generic,
209                      KVM_REG_PPC_DAR, 0x00000000);
210     /* Timer */
211     spr_register(env, SPR_DECR, "DECR",
212                  SPR_NOACCESS, SPR_NOACCESS,
213                  &spr_read_decr, &spr_write_decr,
214                  0x00000000);
215 }
216 
217 /* Storage Description Register 1 */
218 static void register_sdr1_sprs(CPUPPCState *env)
219 {
220 #ifndef CONFIG_USER_ONLY
221     if (env->has_hv_mode) {
222         /*
223          * SDR1 is a hypervisor resource on CPUs which have a
224          * hypervisor mode
225          */
226         spr_register_hv(env, SPR_SDR1, "SDR1",
227                         SPR_NOACCESS, SPR_NOACCESS,
228                         SPR_NOACCESS, SPR_NOACCESS,
229                         &spr_read_generic, &spr_write_sdr1,
230                         0x00000000);
231     } else {
232         spr_register(env, SPR_SDR1, "SDR1",
233                      SPR_NOACCESS, SPR_NOACCESS,
234                      &spr_read_generic, &spr_write_sdr1,
235                      0x00000000);
236     }
237 #endif
238 }
239 
240 /* BATs 0-3 */
241 static void register_low_BATs(CPUPPCState *env)
242 {
243 #if !defined(CONFIG_USER_ONLY)
244     spr_register(env, SPR_IBAT0U, "IBAT0U",
245                  SPR_NOACCESS, SPR_NOACCESS,
246                  &spr_read_ibat, &spr_write_ibatu,
247                  0x00000000);
248     spr_register(env, SPR_IBAT0L, "IBAT0L",
249                  SPR_NOACCESS, SPR_NOACCESS,
250                  &spr_read_ibat, &spr_write_ibatl,
251                  0x00000000);
252     spr_register(env, SPR_IBAT1U, "IBAT1U",
253                  SPR_NOACCESS, SPR_NOACCESS,
254                  &spr_read_ibat, &spr_write_ibatu,
255                  0x00000000);
256     spr_register(env, SPR_IBAT1L, "IBAT1L",
257                  SPR_NOACCESS, SPR_NOACCESS,
258                  &spr_read_ibat, &spr_write_ibatl,
259                  0x00000000);
260     spr_register(env, SPR_IBAT2U, "IBAT2U",
261                  SPR_NOACCESS, SPR_NOACCESS,
262                  &spr_read_ibat, &spr_write_ibatu,
263                  0x00000000);
264     spr_register(env, SPR_IBAT2L, "IBAT2L",
265                  SPR_NOACCESS, SPR_NOACCESS,
266                  &spr_read_ibat, &spr_write_ibatl,
267                  0x00000000);
268     spr_register(env, SPR_IBAT3U, "IBAT3U",
269                  SPR_NOACCESS, SPR_NOACCESS,
270                  &spr_read_ibat, &spr_write_ibatu,
271                  0x00000000);
272     spr_register(env, SPR_IBAT3L, "IBAT3L",
273                  SPR_NOACCESS, SPR_NOACCESS,
274                  &spr_read_ibat, &spr_write_ibatl,
275                  0x00000000);
276     spr_register(env, SPR_DBAT0U, "DBAT0U",
277                  SPR_NOACCESS, SPR_NOACCESS,
278                  &spr_read_dbat, &spr_write_dbatu,
279                  0x00000000);
280     spr_register(env, SPR_DBAT0L, "DBAT0L",
281                  SPR_NOACCESS, SPR_NOACCESS,
282                  &spr_read_dbat, &spr_write_dbatl,
283                  0x00000000);
284     spr_register(env, SPR_DBAT1U, "DBAT1U",
285                  SPR_NOACCESS, SPR_NOACCESS,
286                  &spr_read_dbat, &spr_write_dbatu,
287                  0x00000000);
288     spr_register(env, SPR_DBAT1L, "DBAT1L",
289                  SPR_NOACCESS, SPR_NOACCESS,
290                  &spr_read_dbat, &spr_write_dbatl,
291                  0x00000000);
292     spr_register(env, SPR_DBAT2U, "DBAT2U",
293                  SPR_NOACCESS, SPR_NOACCESS,
294                  &spr_read_dbat, &spr_write_dbatu,
295                  0x00000000);
296     spr_register(env, SPR_DBAT2L, "DBAT2L",
297                  SPR_NOACCESS, SPR_NOACCESS,
298                  &spr_read_dbat, &spr_write_dbatl,
299                  0x00000000);
300     spr_register(env, SPR_DBAT3U, "DBAT3U",
301                  SPR_NOACCESS, SPR_NOACCESS,
302                  &spr_read_dbat, &spr_write_dbatu,
303                  0x00000000);
304     spr_register(env, SPR_DBAT3L, "DBAT3L",
305                  SPR_NOACCESS, SPR_NOACCESS,
306                  &spr_read_dbat, &spr_write_dbatl,
307                  0x00000000);
308     env->nb_BATs += 4;
309 #endif
310 }
311 
312 /* BATs 4-7 */
313 static void register_high_BATs(CPUPPCState *env)
314 {
315 #if !defined(CONFIG_USER_ONLY)
316     spr_register(env, SPR_IBAT4U, "IBAT4U",
317                  SPR_NOACCESS, SPR_NOACCESS,
318                  &spr_read_ibat_h, &spr_write_ibatu_h,
319                  0x00000000);
320     spr_register(env, SPR_IBAT4L, "IBAT4L",
321                  SPR_NOACCESS, SPR_NOACCESS,
322                  &spr_read_ibat_h, &spr_write_ibatl_h,
323                  0x00000000);
324     spr_register(env, SPR_IBAT5U, "IBAT5U",
325                  SPR_NOACCESS, SPR_NOACCESS,
326                  &spr_read_ibat_h, &spr_write_ibatu_h,
327                  0x00000000);
328     spr_register(env, SPR_IBAT5L, "IBAT5L",
329                  SPR_NOACCESS, SPR_NOACCESS,
330                  &spr_read_ibat_h, &spr_write_ibatl_h,
331                  0x00000000);
332     spr_register(env, SPR_IBAT6U, "IBAT6U",
333                  SPR_NOACCESS, SPR_NOACCESS,
334                  &spr_read_ibat_h, &spr_write_ibatu_h,
335                  0x00000000);
336     spr_register(env, SPR_IBAT6L, "IBAT6L",
337                  SPR_NOACCESS, SPR_NOACCESS,
338                  &spr_read_ibat_h, &spr_write_ibatl_h,
339                  0x00000000);
340     spr_register(env, SPR_IBAT7U, "IBAT7U",
341                  SPR_NOACCESS, SPR_NOACCESS,
342                  &spr_read_ibat_h, &spr_write_ibatu_h,
343                  0x00000000);
344     spr_register(env, SPR_IBAT7L, "IBAT7L",
345                  SPR_NOACCESS, SPR_NOACCESS,
346                  &spr_read_ibat_h, &spr_write_ibatl_h,
347                  0x00000000);
348     spr_register(env, SPR_DBAT4U, "DBAT4U",
349                  SPR_NOACCESS, SPR_NOACCESS,
350                  &spr_read_dbat_h, &spr_write_dbatu_h,
351                  0x00000000);
352     spr_register(env, SPR_DBAT4L, "DBAT4L",
353                  SPR_NOACCESS, SPR_NOACCESS,
354                  &spr_read_dbat_h, &spr_write_dbatl_h,
355                  0x00000000);
356     spr_register(env, SPR_DBAT5U, "DBAT5U",
357                  SPR_NOACCESS, SPR_NOACCESS,
358                  &spr_read_dbat_h, &spr_write_dbatu_h,
359                  0x00000000);
360     spr_register(env, SPR_DBAT5L, "DBAT5L",
361                  SPR_NOACCESS, SPR_NOACCESS,
362                  &spr_read_dbat_h, &spr_write_dbatl_h,
363                  0x00000000);
364     spr_register(env, SPR_DBAT6U, "DBAT6U",
365                  SPR_NOACCESS, SPR_NOACCESS,
366                  &spr_read_dbat_h, &spr_write_dbatu_h,
367                  0x00000000);
368     spr_register(env, SPR_DBAT6L, "DBAT6L",
369                  SPR_NOACCESS, SPR_NOACCESS,
370                  &spr_read_dbat_h, &spr_write_dbatl_h,
371                  0x00000000);
372     spr_register(env, SPR_DBAT7U, "DBAT7U",
373                  SPR_NOACCESS, SPR_NOACCESS,
374                  &spr_read_dbat_h, &spr_write_dbatu_h,
375                  0x00000000);
376     spr_register(env, SPR_DBAT7L, "DBAT7L",
377                  SPR_NOACCESS, SPR_NOACCESS,
378                  &spr_read_dbat_h, &spr_write_dbatl_h,
379                  0x00000000);
380     env->nb_BATs += 4;
381 #endif
382 }
383 
384 /* Generic PowerPC time base */
385 static void register_tbl(CPUPPCState *env)
386 {
387     spr_register(env, SPR_VTBL,  "TBL",
388                  &spr_read_tbl, SPR_NOACCESS,
389                  &spr_read_tbl, SPR_NOACCESS,
390                  0x00000000);
391     spr_register(env, SPR_TBL,   "TBL",
392                  &spr_read_tbl, SPR_NOACCESS,
393                  &spr_read_tbl, &spr_write_tbl,
394                  0x00000000);
395     spr_register(env, SPR_VTBU,  "TBU",
396                  &spr_read_tbu, SPR_NOACCESS,
397                  &spr_read_tbu, SPR_NOACCESS,
398                  0x00000000);
399     spr_register(env, SPR_TBU,   "TBU",
400                  &spr_read_tbu, SPR_NOACCESS,
401                  &spr_read_tbu, &spr_write_tbu,
402                  0x00000000);
403 }
404 
405 /* Softare table search registers */
406 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
407 {
408 #if !defined(CONFIG_USER_ONLY)
409     env->nb_tlb = nb_tlbs;
410     env->nb_ways = nb_ways;
411     env->id_tlbs = 1;
412     env->tlb_type = TLB_6XX;
413     spr_register(env, SPR_DMISS, "DMISS",
414                  SPR_NOACCESS, SPR_NOACCESS,
415                  &spr_read_generic, SPR_NOACCESS,
416                  0x00000000);
417     spr_register(env, SPR_DCMP, "DCMP",
418                  SPR_NOACCESS, SPR_NOACCESS,
419                  &spr_read_generic, SPR_NOACCESS,
420                  0x00000000);
421     spr_register(env, SPR_HASH1, "HASH1",
422                  SPR_NOACCESS, SPR_NOACCESS,
423                  &spr_read_generic, SPR_NOACCESS,
424                  0x00000000);
425     spr_register(env, SPR_HASH2, "HASH2",
426                  SPR_NOACCESS, SPR_NOACCESS,
427                  &spr_read_generic, SPR_NOACCESS,
428                  0x00000000);
429     spr_register(env, SPR_IMISS, "IMISS",
430                  SPR_NOACCESS, SPR_NOACCESS,
431                  &spr_read_generic, SPR_NOACCESS,
432                  0x00000000);
433     spr_register(env, SPR_ICMP, "ICMP",
434                  SPR_NOACCESS, SPR_NOACCESS,
435                  &spr_read_generic, SPR_NOACCESS,
436                  0x00000000);
437     spr_register(env, SPR_RPA, "RPA",
438                  SPR_NOACCESS, SPR_NOACCESS,
439                  &spr_read_generic, &spr_write_generic,
440                  0x00000000);
441 #endif
442 }
443 
444 /* SPR common to MPC755 and G2 */
445 static void register_G2_755_sprs(CPUPPCState *env)
446 {
447     /* SGPRs */
448     spr_register(env, SPR_SPRG4, "SPRG4",
449                  SPR_NOACCESS, SPR_NOACCESS,
450                  &spr_read_generic, &spr_write_generic,
451                  0x00000000);
452     spr_register(env, SPR_SPRG5, "SPRG5",
453                  SPR_NOACCESS, SPR_NOACCESS,
454                  &spr_read_generic, &spr_write_generic,
455                  0x00000000);
456     spr_register(env, SPR_SPRG6, "SPRG6",
457                  SPR_NOACCESS, SPR_NOACCESS,
458                  &spr_read_generic, &spr_write_generic,
459                  0x00000000);
460     spr_register(env, SPR_SPRG7, "SPRG7",
461                  SPR_NOACCESS, SPR_NOACCESS,
462                  &spr_read_generic, &spr_write_generic,
463                  0x00000000);
464 }
465 
466 /* SPR common to all 7xx PowerPC implementations */
467 static void register_7xx_sprs(CPUPPCState *env)
468 {
469     /* Breakpoints */
470     /* XXX : not implemented */
471     spr_register_kvm(env, SPR_DABR, "DABR",
472                      SPR_NOACCESS, SPR_NOACCESS,
473                      &spr_read_generic, &spr_write_generic,
474                      KVM_REG_PPC_DABR, 0x00000000);
475     /* XXX : not implemented */
476     spr_register(env, SPR_IABR, "IABR",
477                  SPR_NOACCESS, SPR_NOACCESS,
478                  &spr_read_generic, &spr_write_generic,
479                  0x00000000);
480     /* Cache management */
481     /* XXX : not implemented */
482     spr_register(env, SPR_ICTC, "ICTC",
483                  SPR_NOACCESS, SPR_NOACCESS,
484                  &spr_read_generic, &spr_write_generic,
485                  0x00000000);
486     /* Performance monitors */
487     /* XXX : not implemented */
488     spr_register(env, SPR_7XX_MMCR0, "MMCR0",
489                  SPR_NOACCESS, SPR_NOACCESS,
490                  &spr_read_generic, &spr_write_generic,
491                  0x00000000);
492     /* XXX : not implemented */
493     spr_register(env, SPR_7XX_MMCR1, "MMCR1",
494                  SPR_NOACCESS, SPR_NOACCESS,
495                  &spr_read_generic, &spr_write_generic,
496                  0x00000000);
497     /* XXX : not implemented */
498     spr_register(env, SPR_7XX_PMC1, "PMC1",
499                  SPR_NOACCESS, SPR_NOACCESS,
500                  &spr_read_generic, &spr_write_generic,
501                  0x00000000);
502     /* XXX : not implemented */
503     spr_register(env, SPR_7XX_PMC2, "PMC2",
504                  SPR_NOACCESS, SPR_NOACCESS,
505                  &spr_read_generic, &spr_write_generic,
506                  0x00000000);
507     /* XXX : not implemented */
508     spr_register(env, SPR_7XX_PMC3, "PMC3",
509                  SPR_NOACCESS, SPR_NOACCESS,
510                  &spr_read_generic, &spr_write_generic,
511                  0x00000000);
512     /* XXX : not implemented */
513     spr_register(env, SPR_7XX_PMC4, "PMC4",
514                  SPR_NOACCESS, SPR_NOACCESS,
515                  &spr_read_generic, &spr_write_generic,
516                  0x00000000);
517     /* XXX : not implemented */
518     spr_register(env, SPR_7XX_SIAR, "SIAR",
519                  SPR_NOACCESS, SPR_NOACCESS,
520                  &spr_read_generic, SPR_NOACCESS,
521                  0x00000000);
522     /* XXX : not implemented */
523     spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
524                  &spr_read_ureg, SPR_NOACCESS,
525                  &spr_read_ureg, SPR_NOACCESS,
526                  0x00000000);
527     /* XXX : not implemented */
528     spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
529                  &spr_read_ureg, SPR_NOACCESS,
530                  &spr_read_ureg, SPR_NOACCESS,
531                  0x00000000);
532     /* XXX : not implemented */
533     spr_register(env, SPR_7XX_UPMC1, "UPMC1",
534                  &spr_read_ureg, SPR_NOACCESS,
535                  &spr_read_ureg, SPR_NOACCESS,
536                  0x00000000);
537     /* XXX : not implemented */
538     spr_register(env, SPR_7XX_UPMC2, "UPMC2",
539                  &spr_read_ureg, SPR_NOACCESS,
540                  &spr_read_ureg, SPR_NOACCESS,
541                  0x00000000);
542     /* XXX : not implemented */
543     spr_register(env, SPR_7XX_UPMC3, "UPMC3",
544                  &spr_read_ureg, SPR_NOACCESS,
545                  &spr_read_ureg, SPR_NOACCESS,
546                  0x00000000);
547     /* XXX : not implemented */
548     spr_register(env, SPR_7XX_UPMC4, "UPMC4",
549                  &spr_read_ureg, SPR_NOACCESS,
550                  &spr_read_ureg, SPR_NOACCESS,
551                  0x00000000);
552     /* XXX : not implemented */
553     spr_register(env, SPR_7XX_USIAR, "USIAR",
554                  &spr_read_ureg, SPR_NOACCESS,
555                  &spr_read_ureg, SPR_NOACCESS,
556                  0x00000000);
557     /* External access control */
558     /* XXX : not implemented */
559     spr_register(env, SPR_EAR, "EAR",
560                  SPR_NOACCESS, SPR_NOACCESS,
561                  &spr_read_generic, &spr_write_generic,
562                  0x00000000);
563 }
564 
565 #ifdef TARGET_PPC64
566 static void register_amr_sprs(CPUPPCState *env)
567 {
568 #ifndef CONFIG_USER_ONLY
569     /*
570      * Virtual Page Class Key protection
571      *
572      * The AMR is accessible either via SPR 13 or SPR 29.  13 is
573      * userspace accessible, 29 is privileged.  So we only need to set
574      * the kvm ONE_REG id on one of them, we use 29
575      */
576     spr_register(env, SPR_UAMR, "UAMR",
577                  &spr_read_generic, &spr_write_amr,
578                  &spr_read_generic, &spr_write_amr,
579                  0);
580     spr_register_kvm_hv(env, SPR_AMR, "AMR",
581                      SPR_NOACCESS, SPR_NOACCESS,
582                      &spr_read_generic, &spr_write_amr,
583                      &spr_read_generic, &spr_write_generic,
584                      KVM_REG_PPC_AMR, 0);
585     spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
586                      SPR_NOACCESS, SPR_NOACCESS,
587                      &spr_read_generic, &spr_write_uamor,
588                      &spr_read_generic, &spr_write_generic,
589                      KVM_REG_PPC_UAMOR, 0);
590     spr_register_hv(env, SPR_AMOR, "AMOR",
591                     SPR_NOACCESS, SPR_NOACCESS,
592                     SPR_NOACCESS, SPR_NOACCESS,
593                     &spr_read_generic, &spr_write_generic,
594                     0);
595 #endif /* !CONFIG_USER_ONLY */
596 }
597 
598 static void register_iamr_sprs(CPUPPCState *env)
599 {
600 #ifndef CONFIG_USER_ONLY
601     spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
602                         SPR_NOACCESS, SPR_NOACCESS,
603                         &spr_read_generic, &spr_write_iamr,
604                         &spr_read_generic, &spr_write_generic,
605                         KVM_REG_PPC_IAMR, 0);
606 #endif /* !CONFIG_USER_ONLY */
607 }
608 #endif /* TARGET_PPC64 */
609 
610 static void register_thrm_sprs(CPUPPCState *env)
611 {
612     /* Thermal management */
613     /* XXX : not implemented */
614     spr_register(env, SPR_THRM1, "THRM1",
615                  SPR_NOACCESS, SPR_NOACCESS,
616                  &spr_read_thrm, &spr_write_generic,
617                  0x00000000);
618     /* XXX : not implemented */
619     spr_register(env, SPR_THRM2, "THRM2",
620                  SPR_NOACCESS, SPR_NOACCESS,
621                  &spr_read_thrm, &spr_write_generic,
622                  0x00000000);
623     /* XXX : not implemented */
624     spr_register(env, SPR_THRM3, "THRM3",
625                  SPR_NOACCESS, SPR_NOACCESS,
626                  &spr_read_thrm, &spr_write_generic,
627                  0x00000000);
628 }
629 
630 /* SPR specific to PowerPC 604 implementation */
631 static void register_604_sprs(CPUPPCState *env)
632 {
633     /* Processor identification */
634     spr_register(env, SPR_PIR, "PIR",
635                  SPR_NOACCESS, SPR_NOACCESS,
636                  &spr_read_generic, &spr_write_pir,
637                  0x00000000);
638     /* Breakpoints */
639     /* XXX : not implemented */
640     spr_register(env, SPR_IABR, "IABR",
641                  SPR_NOACCESS, SPR_NOACCESS,
642                  &spr_read_generic, &spr_write_generic,
643                  0x00000000);
644     /* XXX : not implemented */
645     spr_register_kvm(env, SPR_DABR, "DABR",
646                      SPR_NOACCESS, SPR_NOACCESS,
647                      &spr_read_generic, &spr_write_generic,
648                      KVM_REG_PPC_DABR, 0x00000000);
649     /* Performance counters */
650     /* XXX : not implemented */
651     spr_register(env, SPR_7XX_MMCR0, "MMCR0",
652                  SPR_NOACCESS, SPR_NOACCESS,
653                  &spr_read_generic, &spr_write_generic,
654                  0x00000000);
655     /* XXX : not implemented */
656     spr_register(env, SPR_7XX_PMC1, "PMC1",
657                  SPR_NOACCESS, SPR_NOACCESS,
658                  &spr_read_generic, &spr_write_generic,
659                  0x00000000);
660     /* XXX : not implemented */
661     spr_register(env, SPR_7XX_PMC2, "PMC2",
662                  SPR_NOACCESS, SPR_NOACCESS,
663                  &spr_read_generic, &spr_write_generic,
664                  0x00000000);
665     /* XXX : not implemented */
666     spr_register(env, SPR_7XX_SIAR, "SIAR",
667                  SPR_NOACCESS, SPR_NOACCESS,
668                  &spr_read_generic, SPR_NOACCESS,
669                  0x00000000);
670     /* XXX : not implemented */
671     spr_register(env, SPR_SDA, "SDA",
672                  SPR_NOACCESS, SPR_NOACCESS,
673                  &spr_read_generic, SPR_NOACCESS,
674                  0x00000000);
675     /* External access control */
676     /* XXX : not implemented */
677     spr_register(env, SPR_EAR, "EAR",
678                  SPR_NOACCESS, SPR_NOACCESS,
679                  &spr_read_generic, &spr_write_generic,
680                  0x00000000);
681 }
682 
683 /* SPR specific to PowerPC 603 implementation */
684 static void register_603_sprs(CPUPPCState *env)
685 {
686     /* External access control */
687     /* XXX : not implemented */
688     spr_register(env, SPR_EAR, "EAR",
689                  SPR_NOACCESS, SPR_NOACCESS,
690                  &spr_read_generic, &spr_write_generic,
691                  0x00000000);
692     /* Breakpoints */
693     /* XXX : not implemented */
694     spr_register(env, SPR_IABR, "IABR",
695                  SPR_NOACCESS, SPR_NOACCESS,
696                  &spr_read_generic, &spr_write_generic,
697                  0x00000000);
698 
699 }
700 
701 /* SPR specific to PowerPC G2 implementation */
702 static void register_G2_sprs(CPUPPCState *env)
703 {
704     /* Memory base address */
705     /* MBAR */
706     /* XXX : not implemented */
707     spr_register(env, SPR_MBAR, "MBAR",
708                  SPR_NOACCESS, SPR_NOACCESS,
709                  &spr_read_generic, &spr_write_generic,
710                  0x00000000);
711     /* Exception processing */
712     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
713                  SPR_NOACCESS, SPR_NOACCESS,
714                  &spr_read_generic, &spr_write_generic,
715                  0x00000000);
716     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
717                  SPR_NOACCESS, SPR_NOACCESS,
718                  &spr_read_generic, &spr_write_generic,
719                  0x00000000);
720     /* Breakpoints */
721     /* XXX : not implemented */
722     spr_register(env, SPR_DABR, "DABR",
723                  SPR_NOACCESS, SPR_NOACCESS,
724                  &spr_read_generic, &spr_write_generic,
725                  0x00000000);
726     /* XXX : not implemented */
727     spr_register(env, SPR_DABR2, "DABR2",
728                  SPR_NOACCESS, SPR_NOACCESS,
729                  &spr_read_generic, &spr_write_generic,
730                  0x00000000);
731     /* XXX : not implemented */
732     spr_register(env, SPR_IABR, "IABR",
733                  SPR_NOACCESS, SPR_NOACCESS,
734                  &spr_read_generic, &spr_write_generic,
735                  0x00000000);
736     /* XXX : not implemented */
737     spr_register(env, SPR_IABR2, "IABR2",
738                  SPR_NOACCESS, SPR_NOACCESS,
739                  &spr_read_generic, &spr_write_generic,
740                  0x00000000);
741     /* XXX : not implemented */
742     spr_register(env, SPR_IBCR, "IBCR",
743                  SPR_NOACCESS, SPR_NOACCESS,
744                  &spr_read_generic, &spr_write_generic,
745                  0x00000000);
746     /* XXX : not implemented */
747     spr_register(env, SPR_DBCR, "DBCR",
748                  SPR_NOACCESS, SPR_NOACCESS,
749                  &spr_read_generic, &spr_write_generic,
750                  0x00000000);
751 }
752 
753 /* SPR specific to PowerPC 602 implementation */
754 static void register_602_sprs(CPUPPCState *env)
755 {
756     /* ESA registers */
757     /* XXX : not implemented */
758     spr_register(env, SPR_SER, "SER",
759                  SPR_NOACCESS, SPR_NOACCESS,
760                  &spr_read_generic, &spr_write_generic,
761                  0x00000000);
762     /* XXX : not implemented */
763     spr_register(env, SPR_SEBR, "SEBR",
764                  SPR_NOACCESS, SPR_NOACCESS,
765                  &spr_read_generic, &spr_write_generic,
766                  0x00000000);
767     /* XXX : not implemented */
768     spr_register(env, SPR_ESASRR, "ESASRR",
769                  SPR_NOACCESS, SPR_NOACCESS,
770                  &spr_read_generic, &spr_write_generic,
771                  0x00000000);
772     /* Floating point status */
773     /* XXX : not implemented */
774     spr_register(env, SPR_SP, "SP",
775                  SPR_NOACCESS, SPR_NOACCESS,
776                  &spr_read_generic, &spr_write_generic,
777                  0x00000000);
778     /* XXX : not implemented */
779     spr_register(env, SPR_LT, "LT",
780                  SPR_NOACCESS, SPR_NOACCESS,
781                  &spr_read_generic, &spr_write_generic,
782                  0x00000000);
783     /* Watchdog timer */
784     /* XXX : not implemented */
785     spr_register(env, SPR_TCR, "TCR",
786                  SPR_NOACCESS, SPR_NOACCESS,
787                  &spr_read_generic, &spr_write_generic,
788                  0x00000000);
789     /* Interrupt base */
790     spr_register(env, SPR_IBR, "IBR",
791                  SPR_NOACCESS, SPR_NOACCESS,
792                  &spr_read_generic, &spr_write_generic,
793                  0x00000000);
794     /* XXX : not implemented */
795     spr_register(env, SPR_IABR, "IABR",
796                  SPR_NOACCESS, SPR_NOACCESS,
797                  &spr_read_generic, &spr_write_generic,
798                  0x00000000);
799 }
800 
801 /* SPR specific to PowerPC 601 implementation */
802 static void register_601_sprs(CPUPPCState *env)
803 {
804     /* Multiplication/division register */
805     /* MQ */
806     spr_register(env, SPR_MQ, "MQ",
807                  &spr_read_generic, &spr_write_generic,
808                  &spr_read_generic, &spr_write_generic,
809                  0x00000000);
810     /* RTC registers */
811     spr_register(env, SPR_601_RTCU, "RTCU",
812                  SPR_NOACCESS, SPR_NOACCESS,
813                  SPR_NOACCESS, &spr_write_601_rtcu,
814                  0x00000000);
815     spr_register(env, SPR_601_VRTCU, "RTCU",
816                  &spr_read_601_rtcu, SPR_NOACCESS,
817                  &spr_read_601_rtcu, SPR_NOACCESS,
818                  0x00000000);
819     spr_register(env, SPR_601_RTCL, "RTCL",
820                  SPR_NOACCESS, SPR_NOACCESS,
821                  SPR_NOACCESS, &spr_write_601_rtcl,
822                  0x00000000);
823     spr_register(env, SPR_601_VRTCL, "RTCL",
824                  &spr_read_601_rtcl, SPR_NOACCESS,
825                  &spr_read_601_rtcl, SPR_NOACCESS,
826                  0x00000000);
827     /* Timer */
828 #if 0 /* ? */
829     spr_register(env, SPR_601_UDECR, "UDECR",
830                  &spr_read_decr, SPR_NOACCESS,
831                  &spr_read_decr, SPR_NOACCESS,
832                  0x00000000);
833 #endif
834     /* External access control */
835     /* XXX : not implemented */
836     spr_register(env, SPR_EAR, "EAR",
837                  SPR_NOACCESS, SPR_NOACCESS,
838                  &spr_read_generic, &spr_write_generic,
839                  0x00000000);
840     /* Memory management */
841 #if !defined(CONFIG_USER_ONLY)
842     spr_register(env, SPR_IBAT0U, "IBAT0U",
843                  SPR_NOACCESS, SPR_NOACCESS,
844                  &spr_read_601_ubat, &spr_write_601_ubatu,
845                  0x00000000);
846     spr_register(env, SPR_IBAT0L, "IBAT0L",
847                  SPR_NOACCESS, SPR_NOACCESS,
848                  &spr_read_601_ubat, &spr_write_601_ubatl,
849                  0x00000000);
850     spr_register(env, SPR_IBAT1U, "IBAT1U",
851                  SPR_NOACCESS, SPR_NOACCESS,
852                  &spr_read_601_ubat, &spr_write_601_ubatu,
853                  0x00000000);
854     spr_register(env, SPR_IBAT1L, "IBAT1L",
855                  SPR_NOACCESS, SPR_NOACCESS,
856                  &spr_read_601_ubat, &spr_write_601_ubatl,
857                  0x00000000);
858     spr_register(env, SPR_IBAT2U, "IBAT2U",
859                  SPR_NOACCESS, SPR_NOACCESS,
860                  &spr_read_601_ubat, &spr_write_601_ubatu,
861                  0x00000000);
862     spr_register(env, SPR_IBAT2L, "IBAT2L",
863                  SPR_NOACCESS, SPR_NOACCESS,
864                  &spr_read_601_ubat, &spr_write_601_ubatl,
865                  0x00000000);
866     spr_register(env, SPR_IBAT3U, "IBAT3U",
867                  SPR_NOACCESS, SPR_NOACCESS,
868                  &spr_read_601_ubat, &spr_write_601_ubatu,
869                  0x00000000);
870     spr_register(env, SPR_IBAT3L, "IBAT3L",
871                  SPR_NOACCESS, SPR_NOACCESS,
872                  &spr_read_601_ubat, &spr_write_601_ubatl,
873                  0x00000000);
874     env->nb_BATs = 4;
875 #endif
876 }
877 
878 static void register_74xx_sprs(CPUPPCState *env)
879 {
880     /* Processor identification */
881     spr_register(env, SPR_PIR, "PIR",
882                  SPR_NOACCESS, SPR_NOACCESS,
883                  &spr_read_generic, &spr_write_pir,
884                  0x00000000);
885     /* XXX : not implemented */
886     spr_register(env, SPR_74XX_MMCR2, "MMCR2",
887                  SPR_NOACCESS, SPR_NOACCESS,
888                  &spr_read_generic, &spr_write_generic,
889                  0x00000000);
890     /* XXX : not implemented */
891     spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
892                  &spr_read_ureg, SPR_NOACCESS,
893                  &spr_read_ureg, SPR_NOACCESS,
894                  0x00000000);
895     /* XXX: not implemented */
896     spr_register(env, SPR_BAMR, "BAMR",
897                  SPR_NOACCESS, SPR_NOACCESS,
898                  &spr_read_generic, &spr_write_generic,
899                  0x00000000);
900     /* XXX : not implemented */
901     spr_register(env, SPR_MSSCR0, "MSSCR0",
902                  SPR_NOACCESS, SPR_NOACCESS,
903                  &spr_read_generic, &spr_write_generic,
904                  0x00000000);
905     /* Hardware implementation registers */
906     /* XXX : not implemented */
907     spr_register(env, SPR_HID0, "HID0",
908                  SPR_NOACCESS, SPR_NOACCESS,
909                  &spr_read_generic, &spr_write_generic,
910                  0x00000000);
911     /* XXX : not implemented */
912     spr_register(env, SPR_HID1, "HID1",
913                  SPR_NOACCESS, SPR_NOACCESS,
914                  &spr_read_generic, &spr_write_generic,
915                  0x00000000);
916     /* Altivec */
917     spr_register(env, SPR_VRSAVE, "VRSAVE",
918                  &spr_read_generic, &spr_write_generic,
919                  &spr_read_generic, &spr_write_generic,
920                  0x00000000);
921     /* XXX : not implemented */
922     spr_register(env, SPR_L2CR, "L2CR",
923                  SPR_NOACCESS, SPR_NOACCESS,
924                  &spr_read_generic, spr_access_nop,
925                  0x00000000);
926 }
927 
928 static void register_l3_ctrl(CPUPPCState *env)
929 {
930     /* L3CR */
931     /* XXX : not implemented */
932     spr_register(env, SPR_L3CR, "L3CR",
933                  SPR_NOACCESS, SPR_NOACCESS,
934                  &spr_read_generic, &spr_write_generic,
935                  0x00000000);
936     /* L3ITCR0 */
937     /* XXX : not implemented */
938     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
939                  SPR_NOACCESS, SPR_NOACCESS,
940                  &spr_read_generic, &spr_write_generic,
941                  0x00000000);
942     /* L3PM */
943     /* XXX : not implemented */
944     spr_register(env, SPR_L3PM, "L3PM",
945                  SPR_NOACCESS, SPR_NOACCESS,
946                  &spr_read_generic, &spr_write_generic,
947                  0x00000000);
948 }
949 
950 static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
951 {
952 #if !defined(CONFIG_USER_ONLY)
953     env->nb_tlb = nb_tlbs;
954     env->nb_ways = nb_ways;
955     env->id_tlbs = 1;
956     env->tlb_type = TLB_6XX;
957     /* XXX : not implemented */
958     spr_register(env, SPR_PTEHI, "PTEHI",
959                  SPR_NOACCESS, SPR_NOACCESS,
960                  &spr_read_generic, &spr_write_generic,
961                  0x00000000);
962     /* XXX : not implemented */
963     spr_register(env, SPR_PTELO, "PTELO",
964                  SPR_NOACCESS, SPR_NOACCESS,
965                  &spr_read_generic, &spr_write_generic,
966                  0x00000000);
967     /* XXX : not implemented */
968     spr_register(env, SPR_TLBMISS, "TLBMISS",
969                  SPR_NOACCESS, SPR_NOACCESS,
970                  &spr_read_generic, &spr_write_generic,
971                  0x00000000);
972 #endif
973 }
974 
975 static void register_usprg3_sprs(CPUPPCState *env)
976 {
977     spr_register(env, SPR_USPRG3, "USPRG3",
978                  &spr_read_ureg, SPR_NOACCESS,
979                  &spr_read_ureg, SPR_NOACCESS,
980                  0x00000000);
981 }
982 
983 static void register_usprgh_sprs(CPUPPCState *env)
984 {
985     spr_register(env, SPR_USPRG4, "USPRG4",
986                  &spr_read_ureg, SPR_NOACCESS,
987                  &spr_read_ureg, SPR_NOACCESS,
988                  0x00000000);
989     spr_register(env, SPR_USPRG5, "USPRG5",
990                  &spr_read_ureg, SPR_NOACCESS,
991                  &spr_read_ureg, SPR_NOACCESS,
992                  0x00000000);
993     spr_register(env, SPR_USPRG6, "USPRG6",
994                  &spr_read_ureg, SPR_NOACCESS,
995                  &spr_read_ureg, SPR_NOACCESS,
996                  0x00000000);
997     spr_register(env, SPR_USPRG7, "USPRG7",
998                  &spr_read_ureg, SPR_NOACCESS,
999                  &spr_read_ureg, SPR_NOACCESS,
1000                  0x00000000);
1001 }
1002 
1003 /* PowerPC BookE SPR */
1004 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1005 {
1006     const char *ivor_names[64] = {
1007         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1008         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1009         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1010         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1011         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1012         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1013         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1014         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1015         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1016         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1017         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1018         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1019         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1020         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1021         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1022         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1023     };
1024 #define SPR_BOOKE_IVORxx (-1)
1025     int ivor_sprn[64] = {
1026         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1027         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1028         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1029         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1030         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1031         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1032         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1033         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1034         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1035         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1036         SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1037         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1038         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1039         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1040         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1041         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1042     };
1043     int i;
1044 
1045     /* Interrupt processing */
1046     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1047                  SPR_NOACCESS, SPR_NOACCESS,
1048                  &spr_read_generic, &spr_write_generic,
1049                  0x00000000);
1050     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1051                  SPR_NOACCESS, SPR_NOACCESS,
1052                  &spr_read_generic, &spr_write_generic,
1053                  0x00000000);
1054     /* Debug */
1055     /* XXX : not implemented */
1056     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1057                  SPR_NOACCESS, SPR_NOACCESS,
1058                  &spr_read_generic, &spr_write_generic,
1059                  0x00000000);
1060     /* XXX : not implemented */
1061     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1062                  SPR_NOACCESS, SPR_NOACCESS,
1063                  &spr_read_generic, &spr_write_generic,
1064                  0x00000000);
1065     /* XXX : not implemented */
1066     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1067                  SPR_NOACCESS, SPR_NOACCESS,
1068                  &spr_read_generic, &spr_write_generic,
1069                  0x00000000);
1070     /* XXX : not implemented */
1071     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1072                  SPR_NOACCESS, SPR_NOACCESS,
1073                  &spr_read_generic, &spr_write_generic,
1074                  0x00000000);
1075     /* XXX : not implemented */
1076     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1077                  SPR_NOACCESS, SPR_NOACCESS,
1078                  &spr_read_generic, &spr_write_40x_dbcr0,
1079                  0x00000000);
1080     /* XXX : not implemented */
1081     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1082                  SPR_NOACCESS, SPR_NOACCESS,
1083                  &spr_read_generic, &spr_write_generic,
1084                  0x00000000);
1085     /* XXX : not implemented */
1086     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1087                  SPR_NOACCESS, SPR_NOACCESS,
1088                  &spr_read_generic, &spr_write_generic,
1089                  0x00000000);
1090     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1091                  SPR_NOACCESS, SPR_NOACCESS,
1092                  &spr_read_generic, &spr_write_generic,
1093                  0x00000000);
1094     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1095                  SPR_NOACCESS, SPR_NOACCESS,
1096                  &spr_read_generic, &spr_write_generic,
1097                  0x00000000);
1098     /* XXX : not implemented */
1099     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1100                  SPR_NOACCESS, SPR_NOACCESS,
1101                  &spr_read_generic, &spr_write_clear,
1102                  0x00000000);
1103     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1104                  SPR_NOACCESS, SPR_NOACCESS,
1105                  &spr_read_generic, &spr_write_generic,
1106                  0x00000000);
1107     spr_register(env, SPR_BOOKE_ESR, "ESR",
1108                  SPR_NOACCESS, SPR_NOACCESS,
1109                  &spr_read_generic, &spr_write_generic,
1110                  0x00000000);
1111     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1112                  SPR_NOACCESS, SPR_NOACCESS,
1113                  &spr_read_generic, &spr_write_excp_prefix,
1114                  0x00000000);
1115     /* Exception vectors */
1116     for (i = 0; i < 64; i++) {
1117         if (ivor_mask & (1ULL << i)) {
1118             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1119                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1120                 exit(1);
1121             }
1122             spr_register(env, ivor_sprn[i], ivor_names[i],
1123                          SPR_NOACCESS, SPR_NOACCESS,
1124                          &spr_read_generic, &spr_write_excp_vector,
1125                          0x00000000);
1126         }
1127     }
1128     spr_register(env, SPR_BOOKE_PID, "PID",
1129                  SPR_NOACCESS, SPR_NOACCESS,
1130                  &spr_read_generic, &spr_write_booke_pid,
1131                  0x00000000);
1132     spr_register(env, SPR_BOOKE_TCR, "TCR",
1133                  SPR_NOACCESS, SPR_NOACCESS,
1134                  &spr_read_generic, &spr_write_booke_tcr,
1135                  0x00000000);
1136     spr_register(env, SPR_BOOKE_TSR, "TSR",
1137                  SPR_NOACCESS, SPR_NOACCESS,
1138                  &spr_read_generic, &spr_write_booke_tsr,
1139                  0x00000000);
1140     /* Timer */
1141     spr_register(env, SPR_DECR, "DECR",
1142                  SPR_NOACCESS, SPR_NOACCESS,
1143                  &spr_read_decr, &spr_write_decr,
1144                  0x00000000);
1145     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1146                  SPR_NOACCESS, SPR_NOACCESS,
1147                  SPR_NOACCESS, &spr_write_generic,
1148                  0x00000000);
1149     /* SPRGs */
1150     spr_register(env, SPR_USPRG0, "USPRG0",
1151                  &spr_read_generic, &spr_write_generic,
1152                  &spr_read_generic, &spr_write_generic,
1153                  0x00000000);
1154     spr_register(env, SPR_SPRG4, "SPRG4",
1155                  SPR_NOACCESS, SPR_NOACCESS,
1156                  &spr_read_generic, &spr_write_generic,
1157                  0x00000000);
1158     spr_register(env, SPR_SPRG5, "SPRG5",
1159                  SPR_NOACCESS, SPR_NOACCESS,
1160                  &spr_read_generic, &spr_write_generic,
1161                  0x00000000);
1162     spr_register(env, SPR_SPRG6, "SPRG6",
1163                  SPR_NOACCESS, SPR_NOACCESS,
1164                  &spr_read_generic, &spr_write_generic,
1165                  0x00000000);
1166     spr_register(env, SPR_SPRG7, "SPRG7",
1167                  SPR_NOACCESS, SPR_NOACCESS,
1168                  &spr_read_generic, &spr_write_generic,
1169                  0x00000000);
1170     spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1171                  SPR_NOACCESS, SPR_NOACCESS,
1172                  &spr_read_generic, &spr_write_generic,
1173                  0x00000000);
1174     spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1175                  SPR_NOACCESS, SPR_NOACCESS,
1176                  &spr_read_generic, &spr_write_generic,
1177                  0x00000000);
1178 }
1179 
1180 #if !defined(CONFIG_USER_ONLY)
1181 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1182                                    uint32_t maxsize, uint32_t flags,
1183                                    uint32_t nentries)
1184 {
1185     return (assoc << TLBnCFG_ASSOC_SHIFT) |
1186            (minsize << TLBnCFG_MINSIZE_SHIFT) |
1187            (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1188            flags | nentries;
1189 }
1190 #endif /* !CONFIG_USER_ONLY */
1191 
1192 /* BookE 2.06 storage control registers */
1193 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1194                              uint32_t *tlbncfg, uint32_t mmucfg)
1195 {
1196 #if !defined(CONFIG_USER_ONLY)
1197     const char *mas_names[8] = {
1198         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1199     };
1200     int mas_sprn[8] = {
1201         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1202         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1203     };
1204     int i;
1205 
1206     /* TLB assist registers */
1207     /* XXX : not implemented */
1208     for (i = 0; i < 8; i++) {
1209         void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1210             &spr_write_generic32;
1211         if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1212             uea_write = &spr_write_generic;
1213         }
1214         if (mas_mask & (1 << i)) {
1215             spr_register(env, mas_sprn[i], mas_names[i],
1216                          SPR_NOACCESS, SPR_NOACCESS,
1217                          &spr_read_generic, uea_write,
1218                          0x00000000);
1219         }
1220     }
1221     if (env->nb_pids > 1) {
1222         /* XXX : not implemented */
1223         spr_register(env, SPR_BOOKE_PID1, "PID1",
1224                      SPR_NOACCESS, SPR_NOACCESS,
1225                      &spr_read_generic, &spr_write_booke_pid,
1226                      0x00000000);
1227     }
1228     if (env->nb_pids > 2) {
1229         /* XXX : not implemented */
1230         spr_register(env, SPR_BOOKE_PID2, "PID2",
1231                      SPR_NOACCESS, SPR_NOACCESS,
1232                      &spr_read_generic, &spr_write_booke_pid,
1233                      0x00000000);
1234     }
1235 
1236     spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1237                  SPR_NOACCESS, SPR_NOACCESS,
1238                  &spr_read_generic, &spr_write_eplc,
1239                  0x00000000);
1240     spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1241                  SPR_NOACCESS, SPR_NOACCESS,
1242                  &spr_read_generic, &spr_write_epsc,
1243                  0x00000000);
1244 
1245     /* XXX : not implemented */
1246     spr_register(env, SPR_MMUCFG, "MMUCFG",
1247                  SPR_NOACCESS, SPR_NOACCESS,
1248                  &spr_read_generic, SPR_NOACCESS,
1249                  mmucfg);
1250     switch (env->nb_ways) {
1251     case 4:
1252         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1253                      SPR_NOACCESS, SPR_NOACCESS,
1254                      &spr_read_generic, SPR_NOACCESS,
1255                      tlbncfg[3]);
1256         /* Fallthru */
1257     case 3:
1258         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1259                      SPR_NOACCESS, SPR_NOACCESS,
1260                      &spr_read_generic, SPR_NOACCESS,
1261                      tlbncfg[2]);
1262         /* Fallthru */
1263     case 2:
1264         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1265                      SPR_NOACCESS, SPR_NOACCESS,
1266                      &spr_read_generic, SPR_NOACCESS,
1267                      tlbncfg[1]);
1268         /* Fallthru */
1269     case 1:
1270         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1271                      SPR_NOACCESS, SPR_NOACCESS,
1272                      &spr_read_generic, SPR_NOACCESS,
1273                      tlbncfg[0]);
1274         /* Fallthru */
1275     case 0:
1276     default:
1277         break;
1278     }
1279 #endif
1280 
1281     register_usprgh_sprs(env);
1282 }
1283 
1284 /* SPR specific to PowerPC 440 implementation */
1285 static void register_440_sprs(CPUPPCState *env)
1286 {
1287     /* Cache control */
1288     /* XXX : not implemented */
1289     spr_register(env, SPR_440_DNV0, "DNV0",
1290                  SPR_NOACCESS, SPR_NOACCESS,
1291                  &spr_read_generic, &spr_write_generic,
1292                  0x00000000);
1293     /* XXX : not implemented */
1294     spr_register(env, SPR_440_DNV1, "DNV1",
1295                  SPR_NOACCESS, SPR_NOACCESS,
1296                  &spr_read_generic, &spr_write_generic,
1297                  0x00000000);
1298     /* XXX : not implemented */
1299     spr_register(env, SPR_440_DNV2, "DNV2",
1300                  SPR_NOACCESS, SPR_NOACCESS,
1301                  &spr_read_generic, &spr_write_generic,
1302                  0x00000000);
1303     /* XXX : not implemented */
1304     spr_register(env, SPR_440_DNV3, "DNV3",
1305                  SPR_NOACCESS, SPR_NOACCESS,
1306                  &spr_read_generic, &spr_write_generic,
1307                  0x00000000);
1308     /* XXX : not implemented */
1309     spr_register(env, SPR_440_DTV0, "DTV0",
1310                  SPR_NOACCESS, SPR_NOACCESS,
1311                  &spr_read_generic, &spr_write_generic,
1312                  0x00000000);
1313     /* XXX : not implemented */
1314     spr_register(env, SPR_440_DTV1, "DTV1",
1315                  SPR_NOACCESS, SPR_NOACCESS,
1316                  &spr_read_generic, &spr_write_generic,
1317                  0x00000000);
1318     /* XXX : not implemented */
1319     spr_register(env, SPR_440_DTV2, "DTV2",
1320                  SPR_NOACCESS, SPR_NOACCESS,
1321                  &spr_read_generic, &spr_write_generic,
1322                  0x00000000);
1323     /* XXX : not implemented */
1324     spr_register(env, SPR_440_DTV3, "DTV3",
1325                  SPR_NOACCESS, SPR_NOACCESS,
1326                  &spr_read_generic, &spr_write_generic,
1327                  0x00000000);
1328     /* XXX : not implemented */
1329     spr_register(env, SPR_440_DVLIM, "DVLIM",
1330                  SPR_NOACCESS, SPR_NOACCESS,
1331                  &spr_read_generic, &spr_write_generic,
1332                  0x00000000);
1333     /* XXX : not implemented */
1334     spr_register(env, SPR_440_INV0, "INV0",
1335                  SPR_NOACCESS, SPR_NOACCESS,
1336                  &spr_read_generic, &spr_write_generic,
1337                  0x00000000);
1338     /* XXX : not implemented */
1339     spr_register(env, SPR_440_INV1, "INV1",
1340                  SPR_NOACCESS, SPR_NOACCESS,
1341                  &spr_read_generic, &spr_write_generic,
1342                  0x00000000);
1343     /* XXX : not implemented */
1344     spr_register(env, SPR_440_INV2, "INV2",
1345                  SPR_NOACCESS, SPR_NOACCESS,
1346                  &spr_read_generic, &spr_write_generic,
1347                  0x00000000);
1348     /* XXX : not implemented */
1349     spr_register(env, SPR_440_INV3, "INV3",
1350                  SPR_NOACCESS, SPR_NOACCESS,
1351                  &spr_read_generic, &spr_write_generic,
1352                  0x00000000);
1353     /* XXX : not implemented */
1354     spr_register(env, SPR_440_ITV0, "ITV0",
1355                  SPR_NOACCESS, SPR_NOACCESS,
1356                  &spr_read_generic, &spr_write_generic,
1357                  0x00000000);
1358     /* XXX : not implemented */
1359     spr_register(env, SPR_440_ITV1, "ITV1",
1360                  SPR_NOACCESS, SPR_NOACCESS,
1361                  &spr_read_generic, &spr_write_generic,
1362                  0x00000000);
1363     /* XXX : not implemented */
1364     spr_register(env, SPR_440_ITV2, "ITV2",
1365                  SPR_NOACCESS, SPR_NOACCESS,
1366                  &spr_read_generic, &spr_write_generic,
1367                  0x00000000);
1368     /* XXX : not implemented */
1369     spr_register(env, SPR_440_ITV3, "ITV3",
1370                  SPR_NOACCESS, SPR_NOACCESS,
1371                  &spr_read_generic, &spr_write_generic,
1372                  0x00000000);
1373     /* XXX : not implemented */
1374     spr_register(env, SPR_440_IVLIM, "IVLIM",
1375                  SPR_NOACCESS, SPR_NOACCESS,
1376                  &spr_read_generic, &spr_write_generic,
1377                  0x00000000);
1378     /* Cache debug */
1379     /* XXX : not implemented */
1380     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1381                  SPR_NOACCESS, SPR_NOACCESS,
1382                  &spr_read_generic, SPR_NOACCESS,
1383                  0x00000000);
1384     /* XXX : not implemented */
1385     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1386                  SPR_NOACCESS, SPR_NOACCESS,
1387                  &spr_read_generic, SPR_NOACCESS,
1388                  0x00000000);
1389     /* XXX : not implemented */
1390     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1391                  SPR_NOACCESS, SPR_NOACCESS,
1392                  &spr_read_generic, SPR_NOACCESS,
1393                  0x00000000);
1394     /* XXX : not implemented */
1395     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1396                  SPR_NOACCESS, SPR_NOACCESS,
1397                  &spr_read_generic, SPR_NOACCESS,
1398                  0x00000000);
1399     /* XXX : not implemented */
1400     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1401                  SPR_NOACCESS, SPR_NOACCESS,
1402                  &spr_read_generic, SPR_NOACCESS,
1403                  0x00000000);
1404     /* XXX : not implemented */
1405     spr_register(env, SPR_440_DBDR, "DBDR",
1406                  SPR_NOACCESS, SPR_NOACCESS,
1407                  &spr_read_generic, &spr_write_generic,
1408                  0x00000000);
1409     /* Processor control */
1410     spr_register(env, SPR_4xx_CCR0, "CCR0",
1411                  SPR_NOACCESS, SPR_NOACCESS,
1412                  &spr_read_generic, &spr_write_generic,
1413                  0x00000000);
1414     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1415                  SPR_NOACCESS, SPR_NOACCESS,
1416                  &spr_read_generic, SPR_NOACCESS,
1417                  0x00000000);
1418     /* Storage control */
1419     spr_register(env, SPR_440_MMUCR, "MMUCR",
1420                  SPR_NOACCESS, SPR_NOACCESS,
1421                  &spr_read_generic, &spr_write_generic,
1422                  0x00000000);
1423 }
1424 
1425 /* SPR shared between PowerPC 40x implementations */
1426 static void register_40x_sprs(CPUPPCState *env)
1427 {
1428     /* Cache */
1429     /* not emulated, as QEMU do not emulate caches */
1430     spr_register(env, SPR_40x_DCCR, "DCCR",
1431                  SPR_NOACCESS, SPR_NOACCESS,
1432                  &spr_read_generic, &spr_write_generic,
1433                  0x00000000);
1434     /* not emulated, as QEMU do not emulate caches */
1435     spr_register(env, SPR_40x_ICCR, "ICCR",
1436                  SPR_NOACCESS, SPR_NOACCESS,
1437                  &spr_read_generic, &spr_write_generic,
1438                  0x00000000);
1439     /* not emulated, as QEMU do not emulate caches */
1440     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1441                  SPR_NOACCESS, SPR_NOACCESS,
1442                  &spr_read_generic, SPR_NOACCESS,
1443                  0x00000000);
1444     /* Exception */
1445     spr_register(env, SPR_40x_DEAR, "DEAR",
1446                  SPR_NOACCESS, SPR_NOACCESS,
1447                  &spr_read_generic, &spr_write_generic,
1448                  0x00000000);
1449     spr_register(env, SPR_40x_ESR, "ESR",
1450                  SPR_NOACCESS, SPR_NOACCESS,
1451                  &spr_read_generic, &spr_write_generic,
1452                  0x00000000);
1453     spr_register(env, SPR_40x_EVPR, "EVPR",
1454                  SPR_NOACCESS, SPR_NOACCESS,
1455                  &spr_read_generic, &spr_write_excp_prefix,
1456                  0x00000000);
1457     spr_register(env, SPR_40x_SRR2, "SRR2",
1458                  &spr_read_generic, &spr_write_generic,
1459                  &spr_read_generic, &spr_write_generic,
1460                  0x00000000);
1461     spr_register(env, SPR_40x_SRR3, "SRR3",
1462                  &spr_read_generic, &spr_write_generic,
1463                  &spr_read_generic, &spr_write_generic,
1464                  0x00000000);
1465     /* Timers */
1466     spr_register(env, SPR_40x_PIT, "PIT",
1467                  SPR_NOACCESS, SPR_NOACCESS,
1468                  &spr_read_40x_pit, &spr_write_40x_pit,
1469                  0x00000000);
1470     spr_register(env, SPR_40x_TCR, "TCR",
1471                  SPR_NOACCESS, SPR_NOACCESS,
1472                  &spr_read_generic, &spr_write_booke_tcr,
1473                  0x00000000);
1474     spr_register(env, SPR_40x_TSR, "TSR",
1475                  SPR_NOACCESS, SPR_NOACCESS,
1476                  &spr_read_generic, &spr_write_booke_tsr,
1477                  0x00000000);
1478 }
1479 
1480 /* SPR specific to PowerPC 405 implementation */
1481 static void register_405_sprs(CPUPPCState *env)
1482 {
1483     /* MMU */
1484     spr_register(env, SPR_40x_PID, "PID",
1485                  SPR_NOACCESS, SPR_NOACCESS,
1486                  &spr_read_generic, &spr_write_generic,
1487                  0x00000000);
1488     spr_register(env, SPR_4xx_CCR0, "CCR0",
1489                  SPR_NOACCESS, SPR_NOACCESS,
1490                  &spr_read_generic, &spr_write_generic,
1491                  0x00700000);
1492     /* Debug interface */
1493     /* XXX : not implemented */
1494     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1495                  SPR_NOACCESS, SPR_NOACCESS,
1496                  &spr_read_generic, &spr_write_40x_dbcr0,
1497                  0x00000000);
1498     /* XXX : not implemented */
1499     spr_register(env, SPR_405_DBCR1, "DBCR1",
1500                  SPR_NOACCESS, SPR_NOACCESS,
1501                  &spr_read_generic, &spr_write_generic,
1502                  0x00000000);
1503     /* XXX : not implemented */
1504     spr_register(env, SPR_40x_DBSR, "DBSR",
1505                  SPR_NOACCESS, SPR_NOACCESS,
1506                  &spr_read_generic, &spr_write_clear,
1507                  /* Last reset was system reset */
1508                  0x00000300);
1509     /* XXX : not implemented */
1510     spr_register(env, SPR_40x_DAC1, "DAC1",
1511                  SPR_NOACCESS, SPR_NOACCESS,
1512                  &spr_read_generic, &spr_write_generic,
1513                  0x00000000);
1514     spr_register(env, SPR_40x_DAC2, "DAC2",
1515                  SPR_NOACCESS, SPR_NOACCESS,
1516                  &spr_read_generic, &spr_write_generic,
1517                  0x00000000);
1518     /* XXX : not implemented */
1519     spr_register(env, SPR_405_DVC1, "DVC1",
1520                  SPR_NOACCESS, SPR_NOACCESS,
1521                  &spr_read_generic, &spr_write_generic,
1522                  0x00000000);
1523     /* XXX : not implemented */
1524     spr_register(env, SPR_405_DVC2, "DVC2",
1525                  SPR_NOACCESS, SPR_NOACCESS,
1526                  &spr_read_generic, &spr_write_generic,
1527                  0x00000000);
1528     /* XXX : not implemented */
1529     spr_register(env, SPR_40x_IAC1, "IAC1",
1530                  SPR_NOACCESS, SPR_NOACCESS,
1531                  &spr_read_generic, &spr_write_generic,
1532                  0x00000000);
1533     spr_register(env, SPR_40x_IAC2, "IAC2",
1534                  SPR_NOACCESS, SPR_NOACCESS,
1535                  &spr_read_generic, &spr_write_generic,
1536                  0x00000000);
1537     /* XXX : not implemented */
1538     spr_register(env, SPR_405_IAC3, "IAC3",
1539                  SPR_NOACCESS, SPR_NOACCESS,
1540                  &spr_read_generic, &spr_write_generic,
1541                  0x00000000);
1542     /* XXX : not implemented */
1543     spr_register(env, SPR_405_IAC4, "IAC4",
1544                  SPR_NOACCESS, SPR_NOACCESS,
1545                  &spr_read_generic, &spr_write_generic,
1546                  0x00000000);
1547     /* Storage control */
1548     /* XXX: TODO: not implemented */
1549     spr_register(env, SPR_405_SLER, "SLER",
1550                  SPR_NOACCESS, SPR_NOACCESS,
1551                  &spr_read_generic, &spr_write_40x_sler,
1552                  0x00000000);
1553     spr_register(env, SPR_40x_ZPR, "ZPR",
1554                  SPR_NOACCESS, SPR_NOACCESS,
1555                  &spr_read_generic, &spr_write_generic,
1556                  0x00000000);
1557     /* XXX : not implemented */
1558     spr_register(env, SPR_405_SU0R, "SU0R",
1559                  SPR_NOACCESS, SPR_NOACCESS,
1560                  &spr_read_generic, &spr_write_generic,
1561                  0x00000000);
1562     /* SPRG */
1563     spr_register(env, SPR_USPRG0, "USPRG0",
1564                  &spr_read_ureg, SPR_NOACCESS,
1565                  &spr_read_ureg, SPR_NOACCESS,
1566                  0x00000000);
1567     spr_register(env, SPR_SPRG4, "SPRG4",
1568                  SPR_NOACCESS, SPR_NOACCESS,
1569                  &spr_read_generic, &spr_write_generic,
1570                  0x00000000);
1571     spr_register(env, SPR_SPRG5, "SPRG5",
1572                  SPR_NOACCESS, SPR_NOACCESS,
1573                  spr_read_generic, &spr_write_generic,
1574                  0x00000000);
1575     spr_register(env, SPR_SPRG6, "SPRG6",
1576                  SPR_NOACCESS, SPR_NOACCESS,
1577                  spr_read_generic, &spr_write_generic,
1578                  0x00000000);
1579     spr_register(env, SPR_SPRG7, "SPRG7",
1580                  SPR_NOACCESS, SPR_NOACCESS,
1581                  spr_read_generic, &spr_write_generic,
1582                  0x00000000);
1583     register_usprgh_sprs(env);
1584 }
1585 
1586 /* SPR shared between PowerPC 401 & 403 implementations */
1587 static void register_401_403_sprs(CPUPPCState *env)
1588 {
1589     /* Time base */
1590     spr_register(env, SPR_403_VTBL,  "TBL",
1591                  &spr_read_tbl, SPR_NOACCESS,
1592                  &spr_read_tbl, SPR_NOACCESS,
1593                  0x00000000);
1594     spr_register(env, SPR_403_TBL,   "TBL",
1595                  SPR_NOACCESS, SPR_NOACCESS,
1596                  SPR_NOACCESS, &spr_write_tbl,
1597                  0x00000000);
1598     spr_register(env, SPR_403_VTBU,  "TBU",
1599                  &spr_read_tbu, SPR_NOACCESS,
1600                  &spr_read_tbu, SPR_NOACCESS,
1601                  0x00000000);
1602     spr_register(env, SPR_403_TBU,   "TBU",
1603                  SPR_NOACCESS, SPR_NOACCESS,
1604                  SPR_NOACCESS, &spr_write_tbu,
1605                  0x00000000);
1606     /* Debug */
1607     /* not emulated, as QEMU do not emulate caches */
1608     spr_register(env, SPR_403_CDBCR, "CDBCR",
1609                  SPR_NOACCESS, SPR_NOACCESS,
1610                  &spr_read_generic, &spr_write_generic,
1611                  0x00000000);
1612 }
1613 
1614 /* SPR specific to PowerPC 401 implementation */
1615 static void register_401_sprs(CPUPPCState *env)
1616 {
1617     /* Debug interface */
1618     /* XXX : not implemented */
1619     spr_register(env, SPR_40x_DBCR0, "DBCR",
1620                  SPR_NOACCESS, SPR_NOACCESS,
1621                  &spr_read_generic, &spr_write_40x_dbcr0,
1622                  0x00000000);
1623     /* XXX : not implemented */
1624     spr_register(env, SPR_40x_DBSR, "DBSR",
1625                  SPR_NOACCESS, SPR_NOACCESS,
1626                  &spr_read_generic, &spr_write_clear,
1627                  /* Last reset was system reset */
1628                  0x00000300);
1629     /* XXX : not implemented */
1630     spr_register(env, SPR_40x_DAC1, "DAC",
1631                  SPR_NOACCESS, SPR_NOACCESS,
1632                  &spr_read_generic, &spr_write_generic,
1633                  0x00000000);
1634     /* XXX : not implemented */
1635     spr_register(env, SPR_40x_IAC1, "IAC",
1636                  SPR_NOACCESS, SPR_NOACCESS,
1637                  &spr_read_generic, &spr_write_generic,
1638                  0x00000000);
1639     /* Storage control */
1640     /* XXX: TODO: not implemented */
1641     spr_register(env, SPR_405_SLER, "SLER",
1642                  SPR_NOACCESS, SPR_NOACCESS,
1643                  &spr_read_generic, &spr_write_40x_sler,
1644                  0x00000000);
1645     /* not emulated, as QEMU never does speculative access */
1646     spr_register(env, SPR_40x_SGR, "SGR",
1647                  SPR_NOACCESS, SPR_NOACCESS,
1648                  &spr_read_generic, &spr_write_generic,
1649                  0xFFFFFFFF);
1650     /* not emulated, as QEMU do not emulate caches */
1651     spr_register(env, SPR_40x_DCWR, "DCWR",
1652                  SPR_NOACCESS, SPR_NOACCESS,
1653                  &spr_read_generic, &spr_write_generic,
1654                  0x00000000);
1655 }
1656 
1657 static void register_401x2_sprs(CPUPPCState *env)
1658 {
1659     register_401_sprs(env);
1660     spr_register(env, SPR_40x_PID, "PID",
1661                  SPR_NOACCESS, SPR_NOACCESS,
1662                  &spr_read_generic, &spr_write_generic,
1663                  0x00000000);
1664     spr_register(env, SPR_40x_ZPR, "ZPR",
1665                  SPR_NOACCESS, SPR_NOACCESS,
1666                  &spr_read_generic, &spr_write_generic,
1667                  0x00000000);
1668 }
1669 
1670 /* SPR specific to PowerPC 403 implementation */
1671 static void register_403_sprs(CPUPPCState *env)
1672 {
1673     /* Debug interface */
1674     /* XXX : not implemented */
1675     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1676                  SPR_NOACCESS, SPR_NOACCESS,
1677                  &spr_read_generic, &spr_write_40x_dbcr0,
1678                  0x00000000);
1679     /* XXX : not implemented */
1680     spr_register(env, SPR_40x_DBSR, "DBSR",
1681                  SPR_NOACCESS, SPR_NOACCESS,
1682                  &spr_read_generic, &spr_write_clear,
1683                  /* Last reset was system reset */
1684                  0x00000300);
1685     /* XXX : not implemented */
1686     spr_register(env, SPR_40x_DAC1, "DAC1",
1687                  SPR_NOACCESS, SPR_NOACCESS,
1688                  &spr_read_generic, &spr_write_generic,
1689                  0x00000000);
1690     /* XXX : not implemented */
1691     spr_register(env, SPR_40x_DAC2, "DAC2",
1692                  SPR_NOACCESS, SPR_NOACCESS,
1693                  &spr_read_generic, &spr_write_generic,
1694                  0x00000000);
1695     /* XXX : not implemented */
1696     spr_register(env, SPR_40x_IAC1, "IAC1",
1697                  SPR_NOACCESS, SPR_NOACCESS,
1698                  &spr_read_generic, &spr_write_generic,
1699                  0x00000000);
1700     /* XXX : not implemented */
1701     spr_register(env, SPR_40x_IAC2, "IAC2",
1702                  SPR_NOACCESS, SPR_NOACCESS,
1703                  &spr_read_generic, &spr_write_generic,
1704                  0x00000000);
1705 }
1706 
1707 static void register_403_real_sprs(CPUPPCState *env)
1708 {
1709     spr_register(env, SPR_403_PBL1,  "PBL1",
1710                  SPR_NOACCESS, SPR_NOACCESS,
1711                  &spr_read_403_pbr, &spr_write_403_pbr,
1712                  0x00000000);
1713     spr_register(env, SPR_403_PBU1,  "PBU1",
1714                  SPR_NOACCESS, SPR_NOACCESS,
1715                  &spr_read_403_pbr, &spr_write_403_pbr,
1716                  0x00000000);
1717     spr_register(env, SPR_403_PBL2,  "PBL2",
1718                  SPR_NOACCESS, SPR_NOACCESS,
1719                  &spr_read_403_pbr, &spr_write_403_pbr,
1720                  0x00000000);
1721     spr_register(env, SPR_403_PBU2,  "PBU2",
1722                  SPR_NOACCESS, SPR_NOACCESS,
1723                  &spr_read_403_pbr, &spr_write_403_pbr,
1724                  0x00000000);
1725 }
1726 
1727 static void register_403_mmu_sprs(CPUPPCState *env)
1728 {
1729     /* MMU */
1730     spr_register(env, SPR_40x_PID, "PID",
1731                  SPR_NOACCESS, SPR_NOACCESS,
1732                  &spr_read_generic, &spr_write_generic,
1733                  0x00000000);
1734     spr_register(env, SPR_40x_ZPR, "ZPR",
1735                  SPR_NOACCESS, SPR_NOACCESS,
1736                  &spr_read_generic, &spr_write_generic,
1737                  0x00000000);
1738 }
1739 
1740 /* SPR specific to PowerPC compression coprocessor extension */
1741 static void register_compress_sprs(CPUPPCState *env)
1742 {
1743     /* XXX : not implemented */
1744     spr_register(env, SPR_401_SKR, "SKR",
1745                  SPR_NOACCESS, SPR_NOACCESS,
1746                  &spr_read_generic, &spr_write_generic,
1747                  0x00000000);
1748 }
1749 
1750 static void register_5xx_8xx_sprs(CPUPPCState *env)
1751 {
1752     /* Exception processing */
1753     spr_register_kvm(env, SPR_DSISR, "DSISR",
1754                      SPR_NOACCESS, SPR_NOACCESS,
1755                      &spr_read_generic, &spr_write_generic,
1756                      KVM_REG_PPC_DSISR, 0x00000000);
1757     spr_register_kvm(env, SPR_DAR, "DAR",
1758                      SPR_NOACCESS, SPR_NOACCESS,
1759                      &spr_read_generic, &spr_write_generic,
1760                      KVM_REG_PPC_DAR, 0x00000000);
1761     /* Timer */
1762     spr_register(env, SPR_DECR, "DECR",
1763                  SPR_NOACCESS, SPR_NOACCESS,
1764                  &spr_read_decr, &spr_write_decr,
1765                  0x00000000);
1766     /* XXX : not implemented */
1767     spr_register(env, SPR_MPC_EIE, "EIE",
1768                  SPR_NOACCESS, SPR_NOACCESS,
1769                  &spr_read_generic, &spr_write_generic,
1770                  0x00000000);
1771     /* XXX : not implemented */
1772     spr_register(env, SPR_MPC_EID, "EID",
1773                  SPR_NOACCESS, SPR_NOACCESS,
1774                  &spr_read_generic, &spr_write_generic,
1775                  0x00000000);
1776     /* XXX : not implemented */
1777     spr_register(env, SPR_MPC_NRI, "NRI",
1778                  SPR_NOACCESS, SPR_NOACCESS,
1779                  &spr_read_generic, &spr_write_generic,
1780                  0x00000000);
1781     /* XXX : not implemented */
1782     spr_register(env, SPR_MPC_CMPA, "CMPA",
1783                  SPR_NOACCESS, SPR_NOACCESS,
1784                  &spr_read_generic, &spr_write_generic,
1785                  0x00000000);
1786     /* XXX : not implemented */
1787     spr_register(env, SPR_MPC_CMPB, "CMPB",
1788                  SPR_NOACCESS, SPR_NOACCESS,
1789                  &spr_read_generic, &spr_write_generic,
1790                  0x00000000);
1791     /* XXX : not implemented */
1792     spr_register(env, SPR_MPC_CMPC, "CMPC",
1793                  SPR_NOACCESS, SPR_NOACCESS,
1794                  &spr_read_generic, &spr_write_generic,
1795                  0x00000000);
1796     /* XXX : not implemented */
1797     spr_register(env, SPR_MPC_CMPD, "CMPD",
1798                  SPR_NOACCESS, SPR_NOACCESS,
1799                  &spr_read_generic, &spr_write_generic,
1800                  0x00000000);
1801     /* XXX : not implemented */
1802     spr_register(env, SPR_MPC_ECR, "ECR",
1803                  SPR_NOACCESS, SPR_NOACCESS,
1804                  &spr_read_generic, &spr_write_generic,
1805                  0x00000000);
1806     /* XXX : not implemented */
1807     spr_register(env, SPR_MPC_DER, "DER",
1808                  SPR_NOACCESS, SPR_NOACCESS,
1809                  &spr_read_generic, &spr_write_generic,
1810                  0x00000000);
1811     /* XXX : not implemented */
1812     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1813                  SPR_NOACCESS, SPR_NOACCESS,
1814                  &spr_read_generic, &spr_write_generic,
1815                  0x00000000);
1816     /* XXX : not implemented */
1817     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1818                  SPR_NOACCESS, SPR_NOACCESS,
1819                  &spr_read_generic, &spr_write_generic,
1820                  0x00000000);
1821     /* XXX : not implemented */
1822     spr_register(env, SPR_MPC_CMPE, "CMPE",
1823                  SPR_NOACCESS, SPR_NOACCESS,
1824                  &spr_read_generic, &spr_write_generic,
1825                  0x00000000);
1826     /* XXX : not implemented */
1827     spr_register(env, SPR_MPC_CMPF, "CMPF",
1828                  SPR_NOACCESS, SPR_NOACCESS,
1829                  &spr_read_generic, &spr_write_generic,
1830                  0x00000000);
1831     /* XXX : not implemented */
1832     spr_register(env, SPR_MPC_CMPG, "CMPG",
1833                  SPR_NOACCESS, SPR_NOACCESS,
1834                  &spr_read_generic, &spr_write_generic,
1835                  0x00000000);
1836     /* XXX : not implemented */
1837     spr_register(env, SPR_MPC_CMPH, "CMPH",
1838                  SPR_NOACCESS, SPR_NOACCESS,
1839                  &spr_read_generic, &spr_write_generic,
1840                  0x00000000);
1841     /* XXX : not implemented */
1842     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1843                  SPR_NOACCESS, SPR_NOACCESS,
1844                  &spr_read_generic, &spr_write_generic,
1845                  0x00000000);
1846     /* XXX : not implemented */
1847     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1848                  SPR_NOACCESS, SPR_NOACCESS,
1849                  &spr_read_generic, &spr_write_generic,
1850                  0x00000000);
1851     /* XXX : not implemented */
1852     spr_register(env, SPR_MPC_BAR, "BAR",
1853                  SPR_NOACCESS, SPR_NOACCESS,
1854                  &spr_read_generic, &spr_write_generic,
1855                  0x00000000);
1856     /* XXX : not implemented */
1857     spr_register(env, SPR_MPC_DPDR, "DPDR",
1858                  SPR_NOACCESS, SPR_NOACCESS,
1859                  &spr_read_generic, &spr_write_generic,
1860                  0x00000000);
1861     /* XXX : not implemented */
1862     spr_register(env, SPR_MPC_IMMR, "IMMR",
1863                  SPR_NOACCESS, SPR_NOACCESS,
1864                  &spr_read_generic, &spr_write_generic,
1865                  0x00000000);
1866 }
1867 
1868 static void register_5xx_sprs(CPUPPCState *env)
1869 {
1870     /* XXX : not implemented */
1871     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1872                  SPR_NOACCESS, SPR_NOACCESS,
1873                  &spr_read_generic, &spr_write_generic,
1874                  0x00000000);
1875     /* XXX : not implemented */
1876     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1877                  SPR_NOACCESS, SPR_NOACCESS,
1878                  &spr_read_generic, &spr_write_generic,
1879                  0x00000000);
1880     /* XXX : not implemented */
1881     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1882                  SPR_NOACCESS, SPR_NOACCESS,
1883                  &spr_read_generic, &spr_write_generic,
1884                  0x00000000);
1885     /* XXX : not implemented */
1886     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1887                  SPR_NOACCESS, SPR_NOACCESS,
1888                  &spr_read_generic, &spr_write_generic,
1889                  0x00000000);
1890     /* XXX : not implemented */
1891     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1892                  SPR_NOACCESS, SPR_NOACCESS,
1893                  &spr_read_generic, &spr_write_generic,
1894                  0x00000000);
1895     /* XXX : not implemented */
1896     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1897                  SPR_NOACCESS, SPR_NOACCESS,
1898                  &spr_read_generic, &spr_write_generic,
1899                  0x00000000);
1900     /* XXX : not implemented */
1901     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1902                  SPR_NOACCESS, SPR_NOACCESS,
1903                  &spr_read_generic, &spr_write_generic,
1904                  0x00000000);
1905     /* XXX : not implemented */
1906     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1907                  SPR_NOACCESS, SPR_NOACCESS,
1908                  &spr_read_generic, &spr_write_generic,
1909                  0x00000000);
1910     /* XXX : not implemented */
1911     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1912                  SPR_NOACCESS, SPR_NOACCESS,
1913                  &spr_read_generic, &spr_write_generic,
1914                  0x00000000);
1915     /* XXX : not implemented */
1916     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1917                  SPR_NOACCESS, SPR_NOACCESS,
1918                  &spr_read_generic, &spr_write_generic,
1919                  0x00000000);
1920     /* XXX : not implemented */
1921     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1922                  SPR_NOACCESS, SPR_NOACCESS,
1923                  &spr_read_generic, &spr_write_generic,
1924                  0x00000000);
1925     /* XXX : not implemented */
1926     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1927                  SPR_NOACCESS, SPR_NOACCESS,
1928                  &spr_read_generic, &spr_write_generic,
1929                  0x00000000);
1930     /* XXX : not implemented */
1931     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1932                  SPR_NOACCESS, SPR_NOACCESS,
1933                  &spr_read_generic, &spr_write_generic,
1934                  0x00000000);
1935     /* XXX : not implemented */
1936     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1937                  SPR_NOACCESS, SPR_NOACCESS,
1938                  &spr_read_generic, &spr_write_generic,
1939                  0x00000000);
1940     /* XXX : not implemented */
1941     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1942                  SPR_NOACCESS, SPR_NOACCESS,
1943                  &spr_read_generic, &spr_write_generic,
1944                  0x00000000);
1945     /* XXX : not implemented */
1946     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1947                  SPR_NOACCESS, SPR_NOACCESS,
1948                  &spr_read_generic, &spr_write_generic,
1949                  0x00000000);
1950     /* XXX : not implemented */
1951     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1952                  SPR_NOACCESS, SPR_NOACCESS,
1953                  &spr_read_generic, &spr_write_generic,
1954                  0x00000000);
1955     /* XXX : not implemented */
1956     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1957                  SPR_NOACCESS, SPR_NOACCESS,
1958                  &spr_read_generic, &spr_write_generic,
1959                  0x00000000);
1960     /* XXX : not implemented */
1961     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1962                  SPR_NOACCESS, SPR_NOACCESS,
1963                  &spr_read_generic, &spr_write_generic,
1964                  0x00000000);
1965     /* XXX : not implemented */
1966     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1967                  SPR_NOACCESS, SPR_NOACCESS,
1968                  &spr_read_generic, &spr_write_generic,
1969                  0x00000000);
1970     /* XXX : not implemented */
1971     spr_register(env, SPR_RCPU_FPECR, "FPECR",
1972                  SPR_NOACCESS, SPR_NOACCESS,
1973                  &spr_read_generic, &spr_write_generic,
1974                  0x00000000);
1975 }
1976 
1977 static void register_8xx_sprs(CPUPPCState *env)
1978 {
1979     /* XXX : not implemented */
1980     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1981                  SPR_NOACCESS, SPR_NOACCESS,
1982                  &spr_read_generic, &spr_write_generic,
1983                  0x00000000);
1984     /* XXX : not implemented */
1985     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1986                  SPR_NOACCESS, SPR_NOACCESS,
1987                  &spr_read_generic, &spr_write_generic,
1988                  0x00000000);
1989     /* XXX : not implemented */
1990     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1991                  SPR_NOACCESS, SPR_NOACCESS,
1992                  &spr_read_generic, &spr_write_generic,
1993                  0x00000000);
1994     /* XXX : not implemented */
1995     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1996                  SPR_NOACCESS, SPR_NOACCESS,
1997                  &spr_read_generic, &spr_write_generic,
1998                  0x00000000);
1999     /* XXX : not implemented */
2000     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2001                  SPR_NOACCESS, SPR_NOACCESS,
2002                  &spr_read_generic, &spr_write_generic,
2003                  0x00000000);
2004     /* XXX : not implemented */
2005     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2006                  SPR_NOACCESS, SPR_NOACCESS,
2007                  &spr_read_generic, &spr_write_generic,
2008                  0x00000000);
2009     /* XXX : not implemented */
2010     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2011                  SPR_NOACCESS, SPR_NOACCESS,
2012                  &spr_read_generic, &spr_write_generic,
2013                  0x00000000);
2014     /* XXX : not implemented */
2015     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2016                  SPR_NOACCESS, SPR_NOACCESS,
2017                  &spr_read_generic, &spr_write_generic,
2018                  0x00000000);
2019     /* XXX : not implemented */
2020     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2021                  SPR_NOACCESS, SPR_NOACCESS,
2022                  &spr_read_generic, &spr_write_generic,
2023                  0x00000000);
2024     /* XXX : not implemented */
2025     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2026                  SPR_NOACCESS, SPR_NOACCESS,
2027                  &spr_read_generic, &spr_write_generic,
2028                  0x00000000);
2029     /* XXX : not implemented */
2030     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2031                  SPR_NOACCESS, SPR_NOACCESS,
2032                  &spr_read_generic, &spr_write_generic,
2033                  0x00000000);
2034     /* XXX : not implemented */
2035     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2036                  SPR_NOACCESS, SPR_NOACCESS,
2037                  &spr_read_generic, &spr_write_generic,
2038                  0x00000000);
2039     /* XXX : not implemented */
2040     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2041                  SPR_NOACCESS, SPR_NOACCESS,
2042                  &spr_read_generic, &spr_write_generic,
2043                  0x00000000);
2044     /* XXX : not implemented */
2045     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2046                  SPR_NOACCESS, SPR_NOACCESS,
2047                  &spr_read_generic, &spr_write_generic,
2048                  0x00000000);
2049     /* XXX : not implemented */
2050     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2051                  SPR_NOACCESS, SPR_NOACCESS,
2052                  &spr_read_generic, &spr_write_generic,
2053                  0x00000000);
2054     /* XXX : not implemented */
2055     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2056                  SPR_NOACCESS, SPR_NOACCESS,
2057                  &spr_read_generic, &spr_write_generic,
2058                  0x00000000);
2059     /* XXX : not implemented */
2060     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2061                  SPR_NOACCESS, SPR_NOACCESS,
2062                  &spr_read_generic, &spr_write_generic,
2063                  0x00000000);
2064     /* XXX : not implemented */
2065     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2066                  SPR_NOACCESS, SPR_NOACCESS,
2067                  &spr_read_generic, &spr_write_generic,
2068                  0x00000000);
2069     /* XXX : not implemented */
2070     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2071                  SPR_NOACCESS, SPR_NOACCESS,
2072                  &spr_read_generic, &spr_write_generic,
2073                  0x00000000);
2074     /* XXX : not implemented */
2075     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2076                  SPR_NOACCESS, SPR_NOACCESS,
2077                  &spr_read_generic, &spr_write_generic,
2078                  0x00000000);
2079     /* XXX : not implemented */
2080     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2081                  SPR_NOACCESS, SPR_NOACCESS,
2082                  &spr_read_generic, &spr_write_generic,
2083                  0x00000000);
2084     /* XXX : not implemented */
2085     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2086                  SPR_NOACCESS, SPR_NOACCESS,
2087                  &spr_read_generic, &spr_write_generic,
2088                  0x00000000);
2089     /* XXX : not implemented */
2090     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2091                  SPR_NOACCESS, SPR_NOACCESS,
2092                  &spr_read_generic, &spr_write_generic,
2093                  0x00000000);
2094     /* XXX : not implemented */
2095     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2096                  SPR_NOACCESS, SPR_NOACCESS,
2097                  &spr_read_generic, &spr_write_generic,
2098                  0x00000000);
2099     /* XXX : not implemented */
2100     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2101                  SPR_NOACCESS, SPR_NOACCESS,
2102                  &spr_read_generic, &spr_write_generic,
2103                  0x00000000);
2104 }
2105 
2106 /*
2107  * AMR     => SPR 29 (Power 2.04)
2108  * CTRL    => SPR 136 (Power 2.04)
2109  * CTRL    => SPR 152 (Power 2.04)
2110  * SCOMC   => SPR 276 (64 bits ?)
2111  * SCOMD   => SPR 277 (64 bits ?)
2112  * TBU40   => SPR 286 (Power 2.04 hypv)
2113  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2114  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2115  * HDSISR  => SPR 306 (Power 2.04 hypv)
2116  * HDAR    => SPR 307 (Power 2.04 hypv)
2117  * PURR    => SPR 309 (Power 2.04 hypv)
2118  * HDEC    => SPR 310 (Power 2.04 hypv)
2119  * HIOR    => SPR 311 (hypv)
2120  * RMOR    => SPR 312 (970)
2121  * HRMOR   => SPR 313 (Power 2.04 hypv)
2122  * HSRR0   => SPR 314 (Power 2.04 hypv)
2123  * HSRR1   => SPR 315 (Power 2.04 hypv)
2124  * LPIDR   => SPR 317 (970)
2125  * EPR     => SPR 702 (Power 2.04 emb)
2126  * perf    => 768-783 (Power 2.04)
2127  * perf    => 784-799 (Power 2.04)
2128  * PPR     => SPR 896 (Power 2.04)
2129  * DABRX   => 1015    (Power 2.04 hypv)
2130  * FPECR   => SPR 1022 (?)
2131  * ... and more (thermal management, performance counters, ...)
2132  */
2133 
2134 /*****************************************************************************/
2135 /* Exception vectors models                                                  */
2136 static void init_excp_4xx_real(CPUPPCState *env)
2137 {
2138 #if !defined(CONFIG_USER_ONLY)
2139     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2140     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2141     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2142     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2143     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2144     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2145     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2146     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2147     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2148     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2149     env->ivor_mask = 0x0000FFF0UL;
2150     env->ivpr_mask = 0xFFFF0000UL;
2151     /* Hardware reset vector */
2152     env->hreset_vector = 0xFFFFFFFCUL;
2153 #endif
2154 }
2155 
2156 static void init_excp_4xx_softmmu(CPUPPCState *env)
2157 {
2158 #if !defined(CONFIG_USER_ONLY)
2159     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2160     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2161     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2162     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2163     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2164     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2165     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2166     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2167     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2168     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2169     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2170     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2171     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2172     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2173     env->ivor_mask = 0x0000FFF0UL;
2174     env->ivpr_mask = 0xFFFF0000UL;
2175     /* Hardware reset vector */
2176     env->hreset_vector = 0xFFFFFFFCUL;
2177 #endif
2178 }
2179 
2180 static void init_excp_MPC5xx(CPUPPCState *env)
2181 {
2182 #if !defined(CONFIG_USER_ONLY)
2183     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2184     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2185     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2186     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2187     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2188     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2189     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2190     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2191     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2192     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2193     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2194     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2195     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2196     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2197     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2198     env->ivor_mask = 0x0000FFF0UL;
2199     env->ivpr_mask = 0xFFFF0000UL;
2200     /* Hardware reset vector */
2201     env->hreset_vector = 0x00000100UL;
2202 #endif
2203 }
2204 
2205 static void init_excp_MPC8xx(CPUPPCState *env)
2206 {
2207 #if !defined(CONFIG_USER_ONLY)
2208     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2209     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2210     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2211     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2212     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2213     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2214     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2215     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2216     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2217     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2218     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2219     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2220     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2221     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2222     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2223     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2224     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2225     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2226     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2227     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2228     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2229     env->ivor_mask = 0x0000FFF0UL;
2230     env->ivpr_mask = 0xFFFF0000UL;
2231     /* Hardware reset vector */
2232     env->hreset_vector = 0x00000100UL;
2233 #endif
2234 }
2235 
2236 static void init_excp_G2(CPUPPCState *env)
2237 {
2238 #if !defined(CONFIG_USER_ONLY)
2239     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2240     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2241     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2242     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2243     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2244     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2245     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2246     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2247     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2248     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2249     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2250     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2251     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2252     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2253     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2254     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2255     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2256     /* Hardware reset vector */
2257     env->hreset_vector = 0x00000100UL;
2258 #endif
2259 }
2260 
2261 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2262 {
2263 #if !defined(CONFIG_USER_ONLY)
2264     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2265     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2266     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2267     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2268     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2269     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2270     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2271     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2272     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2273     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2274     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2275     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2276     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2277     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2278     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2279     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2280     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2281     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2282     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2283     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2284     env->ivor_mask = 0x0000FFF7UL;
2285     env->ivpr_mask = ivpr_mask;
2286     /* Hardware reset vector */
2287     env->hreset_vector = 0xFFFFFFFCUL;
2288 #endif
2289 }
2290 
2291 static void init_excp_BookE(CPUPPCState *env)
2292 {
2293 #if !defined(CONFIG_USER_ONLY)
2294     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2295     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2296     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2297     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2298     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2299     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2300     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2301     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2302     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2303     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2304     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2305     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2306     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2307     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2308     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2309     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2310     env->ivor_mask = 0x0000FFF0UL;
2311     env->ivpr_mask = 0xFFFF0000UL;
2312     /* Hardware reset vector */
2313     env->hreset_vector = 0xFFFFFFFCUL;
2314 #endif
2315 }
2316 
2317 static void init_excp_601(CPUPPCState *env)
2318 {
2319 #if !defined(CONFIG_USER_ONLY)
2320     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2321     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2322     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2323     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2324     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2325     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2326     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2327     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2328     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2329     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2330     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2331     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2332     /* Hardware reset vector */
2333     env->hreset_vector = 0x00000100UL;
2334 #endif
2335 }
2336 
2337 static void init_excp_602(CPUPPCState *env)
2338 {
2339 #if !defined(CONFIG_USER_ONLY)
2340     /* XXX: exception prefix has a special behavior on 602 */
2341     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2342     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2343     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2344     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2345     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2346     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2347     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2348     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2349     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2350     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2351     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2352     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2353     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2354     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2355     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2356     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2357     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2358     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2359     /* Hardware reset vector */
2360     env->hreset_vector = 0x00000100UL;
2361 #endif
2362 }
2363 
2364 static void init_excp_603(CPUPPCState *env)
2365 {
2366 #if !defined(CONFIG_USER_ONLY)
2367     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2368     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2369     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2370     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2371     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2372     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2373     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2374     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2375     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2376     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2377     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2378     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2379     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2380     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2381     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2382     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2383     /* Hardware reset vector */
2384     env->hreset_vector = 0x00000100UL;
2385 #endif
2386 }
2387 
2388 static void init_excp_604(CPUPPCState *env)
2389 {
2390 #if !defined(CONFIG_USER_ONLY)
2391     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2392     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2393     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2394     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2395     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2396     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2397     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2398     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2399     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2400     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2401     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2402     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2403     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2404     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2405     /* Hardware reset vector */
2406     env->hreset_vector = 0x00000100UL;
2407 #endif
2408 }
2409 
2410 static void init_excp_7x0(CPUPPCState *env)
2411 {
2412 #if !defined(CONFIG_USER_ONLY)
2413     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2414     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2415     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2416     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2417     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2418     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2419     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2420     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2421     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2422     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2423     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2424     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2425     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2426     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2427     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2428     /* Hardware reset vector */
2429     env->hreset_vector = 0x00000100UL;
2430 #endif
2431 }
2432 
2433 static void init_excp_750cl(CPUPPCState *env)
2434 {
2435 #if !defined(CONFIG_USER_ONLY)
2436     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2437     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2438     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2439     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2440     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2441     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2442     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2443     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2444     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2445     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2446     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2447     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2448     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2449     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2450     /* Hardware reset vector */
2451     env->hreset_vector = 0x00000100UL;
2452 #endif
2453 }
2454 
2455 static void init_excp_750cx(CPUPPCState *env)
2456 {
2457 #if !defined(CONFIG_USER_ONLY)
2458     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2459     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2460     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2461     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2462     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2463     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2464     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2465     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2466     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2467     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2468     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2469     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2470     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2471     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2472     /* Hardware reset vector */
2473     env->hreset_vector = 0x00000100UL;
2474 #endif
2475 }
2476 
2477 /* XXX: Check if this is correct */
2478 static void init_excp_7x5(CPUPPCState *env)
2479 {
2480 #if !defined(CONFIG_USER_ONLY)
2481     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2482     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2483     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2484     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2485     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2486     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2487     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2488     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2489     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2490     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2491     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2492     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2493     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2494     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2495     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2496     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2497     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2498     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2499     /* Hardware reset vector */
2500     env->hreset_vector = 0x00000100UL;
2501 #endif
2502 }
2503 
2504 static void init_excp_7400(CPUPPCState *env)
2505 {
2506 #if !defined(CONFIG_USER_ONLY)
2507     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2508     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2509     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2510     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2511     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2512     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2513     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2514     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2515     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2516     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2517     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2518     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2519     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2520     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2521     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2522     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2523     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2524     /* Hardware reset vector */
2525     env->hreset_vector = 0x00000100UL;
2526 #endif
2527 }
2528 
2529 static void init_excp_7450(CPUPPCState *env)
2530 {
2531 #if !defined(CONFIG_USER_ONLY)
2532     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2533     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2534     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2535     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2536     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2537     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2538     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2539     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2540     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2541     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2542     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2543     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2544     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2545     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2546     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2547     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2548     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2549     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2550     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2551     /* Hardware reset vector */
2552     env->hreset_vector = 0x00000100UL;
2553 #endif
2554 }
2555 
2556 #if defined(TARGET_PPC64)
2557 static void init_excp_970(CPUPPCState *env)
2558 {
2559 #if !defined(CONFIG_USER_ONLY)
2560     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2561     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2562     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2563     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2564     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2565     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2566     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2567     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2568     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2569     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2570     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2571     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2572     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2573     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2574     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2575     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2576     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2577     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2578     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2579     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2580     /* Hardware reset vector */
2581     env->hreset_vector = 0x0000000000000100ULL;
2582 #endif
2583 }
2584 
2585 static void init_excp_POWER7(CPUPPCState *env)
2586 {
2587 #if !defined(CONFIG_USER_ONLY)
2588     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2589     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2590     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2591     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2592     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2593     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2594     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2595     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2596     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2597     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2598     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2599     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2600     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2601     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2602     env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
2603     env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
2604     env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
2605     env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2606     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2607     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2608     env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
2609     /* Hardware reset vector */
2610     env->hreset_vector = 0x0000000000000100ULL;
2611 #endif
2612 }
2613 
2614 static void init_excp_POWER8(CPUPPCState *env)
2615 {
2616     init_excp_POWER7(env);
2617 
2618 #if !defined(CONFIG_USER_ONLY)
2619     env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
2620     env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
2621     env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
2622     env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2623 #endif
2624 }
2625 
2626 static void init_excp_POWER9(CPUPPCState *env)
2627 {
2628     init_excp_POWER8(env);
2629 
2630 #if !defined(CONFIG_USER_ONLY)
2631     env->excp_vectors[POWERPC_EXCP_HVIRT]    = 0x00000EA0;
2632     env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2633 #endif
2634 }
2635 
2636 static void init_excp_POWER10(CPUPPCState *env)
2637 {
2638     init_excp_POWER9(env);
2639 }
2640 
2641 #endif
2642 
2643 /*****************************************************************************/
2644 /* Power management enable checks                                            */
2645 static int check_pow_none(CPUPPCState *env)
2646 {
2647     return 0;
2648 }
2649 
2650 static int check_pow_nocheck(CPUPPCState *env)
2651 {
2652     return 1;
2653 }
2654 
2655 static int check_pow_hid0(CPUPPCState *env)
2656 {
2657     if (env->spr[SPR_HID0] & 0x00E00000) {
2658         return 1;
2659     }
2660 
2661     return 0;
2662 }
2663 
2664 static int check_pow_hid0_74xx(CPUPPCState *env)
2665 {
2666     if (env->spr[SPR_HID0] & 0x00600000) {
2667         return 1;
2668     }
2669 
2670     return 0;
2671 }
2672 
2673 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
2674 {
2675     return true;
2676 }
2677 
2678 #ifdef TARGET_PPC64
2679 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
2680 {
2681     return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
2682 }
2683 #endif
2684 
2685 /*****************************************************************************/
2686 /* PowerPC implementations definitions                                       */
2687 
2688 #define POWERPC_FAMILY(_name)                                               \
2689     static void                                                             \
2690     glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2691                                                                             \
2692     static const TypeInfo                                                   \
2693     glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
2694         .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
2695         .parent = TYPE_POWERPC_CPU,                                         \
2696         .abstract = true,                                                   \
2697         .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
2698     };                                                                      \
2699                                                                             \
2700     static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
2701     {                                                                       \
2702         type_register_static(                                               \
2703             &glue(glue(ppc_, _name), _cpu_family_type_info));               \
2704     }                                                                       \
2705                                                                             \
2706     type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
2707                                                                             \
2708     static void glue(glue(ppc_, _name), _cpu_family_class_init)
2709 
2710 static void init_proc_401(CPUPPCState *env)
2711 {
2712     register_40x_sprs(env);
2713     register_401_403_sprs(env);
2714     register_401_sprs(env);
2715     init_excp_4xx_real(env);
2716     env->dcache_line_size = 32;
2717     env->icache_line_size = 32;
2718     /* Allocate hardware IRQ controller */
2719     ppc40x_irq_init(env_archcpu(env));
2720 
2721     SET_FIT_PERIOD(12, 16, 20, 24);
2722     SET_WDT_PERIOD(16, 20, 24, 28);
2723 }
2724 
2725 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
2726 {
2727     DeviceClass *dc = DEVICE_CLASS(oc);
2728     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2729 
2730     dc->desc = "PowerPC 401";
2731     pcc->init_proc = init_proc_401;
2732     pcc->check_pow = check_pow_nocheck;
2733     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2734                        PPC_WRTEE | PPC_DCR |
2735                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2736                        PPC_CACHE_DCBZ |
2737                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
2738                        PPC_4xx_COMMON | PPC_40x_EXCP;
2739     pcc->msr_mask = (1ull << MSR_KEY) |
2740                     (1ull << MSR_POW) |
2741                     (1ull << MSR_CE) |
2742                     (1ull << MSR_ILE) |
2743                     (1ull << MSR_EE) |
2744                     (1ull << MSR_PR) |
2745                     (1ull << MSR_ME) |
2746                     (1ull << MSR_DE) |
2747                     (1ull << MSR_LE);
2748     pcc->mmu_model = POWERPC_MMU_REAL;
2749     pcc->excp_model = POWERPC_EXCP_40x;
2750     pcc->bus_model = PPC_FLAGS_INPUT_401;
2751     pcc->bfd_mach = bfd_mach_ppc_403;
2752     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2753                  POWERPC_FLAG_BUS_CLK;
2754 }
2755 
2756 static void init_proc_401x2(CPUPPCState *env)
2757 {
2758     register_40x_sprs(env);
2759     register_401_403_sprs(env);
2760     register_401x2_sprs(env);
2761     register_compress_sprs(env);
2762     /* Memory management */
2763 #if !defined(CONFIG_USER_ONLY)
2764     env->nb_tlb = 64;
2765     env->nb_ways = 1;
2766     env->id_tlbs = 0;
2767     env->tlb_type = TLB_EMB;
2768 #endif
2769     init_excp_4xx_softmmu(env);
2770     env->dcache_line_size = 32;
2771     env->icache_line_size = 32;
2772     /* Allocate hardware IRQ controller */
2773     ppc40x_irq_init(env_archcpu(env));
2774 
2775     SET_FIT_PERIOD(12, 16, 20, 24);
2776     SET_WDT_PERIOD(16, 20, 24, 28);
2777 }
2778 
2779 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
2780 {
2781     DeviceClass *dc = DEVICE_CLASS(oc);
2782     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2783 
2784     dc->desc = "PowerPC 401x2";
2785     pcc->init_proc = init_proc_401x2;
2786     pcc->check_pow = check_pow_nocheck;
2787     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2788                        PPC_DCR | PPC_WRTEE |
2789                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2790                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2791                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
2792                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2793                        PPC_4xx_COMMON | PPC_40x_EXCP;
2794     pcc->msr_mask = (1ull << 20) |
2795                     (1ull << MSR_KEY) |
2796                     (1ull << MSR_POW) |
2797                     (1ull << MSR_CE) |
2798                     (1ull << MSR_ILE) |
2799                     (1ull << MSR_EE) |
2800                     (1ull << MSR_PR) |
2801                     (1ull << MSR_ME) |
2802                     (1ull << MSR_DE) |
2803                     (1ull << MSR_IR) |
2804                     (1ull << MSR_DR) |
2805                     (1ull << MSR_LE);
2806     pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2807     pcc->excp_model = POWERPC_EXCP_40x;
2808     pcc->bus_model = PPC_FLAGS_INPUT_401;
2809     pcc->bfd_mach = bfd_mach_ppc_403;
2810     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2811                  POWERPC_FLAG_BUS_CLK;
2812 }
2813 
2814 static void init_proc_401x3(CPUPPCState *env)
2815 {
2816     register_40x_sprs(env);
2817     register_401_403_sprs(env);
2818     register_401_sprs(env);
2819     register_401x2_sprs(env);
2820     register_compress_sprs(env);
2821     init_excp_4xx_softmmu(env);
2822     env->dcache_line_size = 32;
2823     env->icache_line_size = 32;
2824     /* Allocate hardware IRQ controller */
2825     ppc40x_irq_init(env_archcpu(env));
2826 
2827     SET_FIT_PERIOD(12, 16, 20, 24);
2828     SET_WDT_PERIOD(16, 20, 24, 28);
2829 }
2830 
2831 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
2832 {
2833     DeviceClass *dc = DEVICE_CLASS(oc);
2834     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2835 
2836     dc->desc = "PowerPC 401x3";
2837     pcc->init_proc = init_proc_401x3;
2838     pcc->check_pow = check_pow_nocheck;
2839     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2840                        PPC_DCR | PPC_WRTEE |
2841                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2842                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2843                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
2844                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2845                        PPC_4xx_COMMON | PPC_40x_EXCP;
2846     pcc->msr_mask = (1ull << 20) |
2847                     (1ull << MSR_KEY) |
2848                     (1ull << MSR_POW) |
2849                     (1ull << MSR_CE) |
2850                     (1ull << MSR_ILE) |
2851                     (1ull << MSR_EE) |
2852                     (1ull << MSR_PR) |
2853                     (1ull << MSR_ME) |
2854                     (1ull << MSR_DWE) |
2855                     (1ull << MSR_DE) |
2856                     (1ull << MSR_IR) |
2857                     (1ull << MSR_DR) |
2858                     (1ull << MSR_LE);
2859     pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2860     pcc->excp_model = POWERPC_EXCP_40x;
2861     pcc->bus_model = PPC_FLAGS_INPUT_401;
2862     pcc->bfd_mach = bfd_mach_ppc_403;
2863     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2864                  POWERPC_FLAG_BUS_CLK;
2865 }
2866 
2867 static void init_proc_IOP480(CPUPPCState *env)
2868 {
2869     register_40x_sprs(env);
2870     register_401_403_sprs(env);
2871     register_401x2_sprs(env);
2872     register_compress_sprs(env);
2873     /* Memory management */
2874 #if !defined(CONFIG_USER_ONLY)
2875     env->nb_tlb = 64;
2876     env->nb_ways = 1;
2877     env->id_tlbs = 0;
2878     env->tlb_type = TLB_EMB;
2879 #endif
2880     init_excp_4xx_softmmu(env);
2881     env->dcache_line_size = 32;
2882     env->icache_line_size = 32;
2883     /* Allocate hardware IRQ controller */
2884     ppc40x_irq_init(env_archcpu(env));
2885 
2886     SET_FIT_PERIOD(8, 12, 16, 20);
2887     SET_WDT_PERIOD(16, 20, 24, 28);
2888 }
2889 
2890 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
2891 {
2892     DeviceClass *dc = DEVICE_CLASS(oc);
2893     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2894 
2895     dc->desc = "IOP480";
2896     pcc->init_proc = init_proc_IOP480;
2897     pcc->check_pow = check_pow_nocheck;
2898     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2899                        PPC_DCR | PPC_WRTEE |
2900                        PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
2901                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2902                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
2903                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2904                        PPC_4xx_COMMON | PPC_40x_EXCP;
2905     pcc->msr_mask = (1ull << 20) |
2906                     (1ull << MSR_KEY) |
2907                     (1ull << MSR_POW) |
2908                     (1ull << MSR_CE) |
2909                     (1ull << MSR_ILE) |
2910                     (1ull << MSR_EE) |
2911                     (1ull << MSR_PR) |
2912                     (1ull << MSR_ME) |
2913                     (1ull << MSR_DE) |
2914                     (1ull << MSR_IR) |
2915                     (1ull << MSR_DR) |
2916                     (1ull << MSR_LE);
2917     pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
2918     pcc->excp_model = POWERPC_EXCP_40x;
2919     pcc->bus_model = PPC_FLAGS_INPUT_401;
2920     pcc->bfd_mach = bfd_mach_ppc_403;
2921     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
2922                  POWERPC_FLAG_BUS_CLK;
2923 }
2924 
2925 static void init_proc_403(CPUPPCState *env)
2926 {
2927     register_40x_sprs(env);
2928     register_401_403_sprs(env);
2929     register_403_sprs(env);
2930     register_403_real_sprs(env);
2931     init_excp_4xx_real(env);
2932     env->dcache_line_size = 32;
2933     env->icache_line_size = 32;
2934     /* Allocate hardware IRQ controller */
2935     ppc40x_irq_init(env_archcpu(env));
2936 
2937     SET_FIT_PERIOD(8, 12, 16, 20);
2938     SET_WDT_PERIOD(16, 20, 24, 28);
2939 }
2940 
2941 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
2942 {
2943     DeviceClass *dc = DEVICE_CLASS(oc);
2944     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2945 
2946     dc->desc = "PowerPC 403";
2947     pcc->init_proc = init_proc_403;
2948     pcc->check_pow = check_pow_nocheck;
2949     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2950                        PPC_DCR | PPC_WRTEE |
2951                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2952                        PPC_CACHE_DCBZ |
2953                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
2954                        PPC_4xx_COMMON | PPC_40x_EXCP;
2955     pcc->msr_mask = (1ull << MSR_POW) |
2956                     (1ull << MSR_CE) |
2957                     (1ull << MSR_ILE) |
2958                     (1ull << MSR_EE) |
2959                     (1ull << MSR_PR) |
2960                     (1ull << MSR_ME) |
2961                     (1ull << MSR_PE) |
2962                     (1ull << MSR_PX) |
2963                     (1ull << MSR_LE);
2964     pcc->mmu_model = POWERPC_MMU_REAL;
2965     pcc->excp_model = POWERPC_EXCP_40x;
2966     pcc->bus_model = PPC_FLAGS_INPUT_401;
2967     pcc->bfd_mach = bfd_mach_ppc_403;
2968     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
2969                  POWERPC_FLAG_BUS_CLK;
2970 }
2971 
2972 static void init_proc_403GCX(CPUPPCState *env)
2973 {
2974     register_40x_sprs(env);
2975     register_401_403_sprs(env);
2976     register_403_sprs(env);
2977     register_403_real_sprs(env);
2978     register_403_mmu_sprs(env);
2979     /* Bus access control */
2980     /* not emulated, as QEMU never does speculative access */
2981     spr_register(env, SPR_40x_SGR, "SGR",
2982                  SPR_NOACCESS, SPR_NOACCESS,
2983                  &spr_read_generic, &spr_write_generic,
2984                  0xFFFFFFFF);
2985     /* not emulated, as QEMU do not emulate caches */
2986     spr_register(env, SPR_40x_DCWR, "DCWR",
2987                  SPR_NOACCESS, SPR_NOACCESS,
2988                  &spr_read_generic, &spr_write_generic,
2989                  0x00000000);
2990     /* Memory management */
2991 #if !defined(CONFIG_USER_ONLY)
2992     env->nb_tlb = 64;
2993     env->nb_ways = 1;
2994     env->id_tlbs = 0;
2995     env->tlb_type = TLB_EMB;
2996 #endif
2997     init_excp_4xx_softmmu(env);
2998     env->dcache_line_size = 32;
2999     env->icache_line_size = 32;
3000     /* Allocate hardware IRQ controller */
3001     ppc40x_irq_init(env_archcpu(env));
3002 
3003     SET_FIT_PERIOD(8, 12, 16, 20);
3004     SET_WDT_PERIOD(16, 20, 24, 28);
3005 }
3006 
3007 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3008 {
3009     DeviceClass *dc = DEVICE_CLASS(oc);
3010     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3011 
3012     dc->desc = "PowerPC 403 GCX";
3013     pcc->init_proc = init_proc_403GCX;
3014     pcc->check_pow = check_pow_nocheck;
3015     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3016                        PPC_DCR | PPC_WRTEE |
3017                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3018                        PPC_CACHE_DCBZ |
3019                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
3020                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3021                        PPC_4xx_COMMON | PPC_40x_EXCP;
3022     pcc->msr_mask = (1ull << MSR_POW) |
3023                     (1ull << MSR_CE) |
3024                     (1ull << MSR_ILE) |
3025                     (1ull << MSR_EE) |
3026                     (1ull << MSR_PR) |
3027                     (1ull << MSR_ME) |
3028                     (1ull << MSR_PE) |
3029                     (1ull << MSR_PX) |
3030                     (1ull << MSR_LE);
3031     pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3032     pcc->excp_model = POWERPC_EXCP_40x;
3033     pcc->bus_model = PPC_FLAGS_INPUT_401;
3034     pcc->bfd_mach = bfd_mach_ppc_403;
3035     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3036                  POWERPC_FLAG_BUS_CLK;
3037 }
3038 
3039 static void init_proc_405(CPUPPCState *env)
3040 {
3041     /* Time base */
3042     register_tbl(env);
3043     register_40x_sprs(env);
3044     register_405_sprs(env);
3045     /* Bus access control */
3046     /* not emulated, as QEMU never does speculative access */
3047     spr_register(env, SPR_40x_SGR, "SGR",
3048                  SPR_NOACCESS, SPR_NOACCESS,
3049                  &spr_read_generic, &spr_write_generic,
3050                  0xFFFFFFFF);
3051     /* not emulated, as QEMU do not emulate caches */
3052     spr_register(env, SPR_40x_DCWR, "DCWR",
3053                  SPR_NOACCESS, SPR_NOACCESS,
3054                  &spr_read_generic, &spr_write_generic,
3055                  0x00000000);
3056     /* Memory management */
3057 #if !defined(CONFIG_USER_ONLY)
3058     env->nb_tlb = 64;
3059     env->nb_ways = 1;
3060     env->id_tlbs = 0;
3061     env->tlb_type = TLB_EMB;
3062 #endif
3063     init_excp_4xx_softmmu(env);
3064     env->dcache_line_size = 32;
3065     env->icache_line_size = 32;
3066     /* Allocate hardware IRQ controller */
3067     ppc40x_irq_init(env_archcpu(env));
3068 
3069     SET_FIT_PERIOD(8, 12, 16, 20);
3070     SET_WDT_PERIOD(16, 20, 24, 28);
3071 }
3072 
3073 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3074 {
3075     DeviceClass *dc = DEVICE_CLASS(oc);
3076     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3077 
3078     dc->desc = "PowerPC 405";
3079     pcc->init_proc = init_proc_405;
3080     pcc->check_pow = check_pow_nocheck;
3081     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3082                        PPC_DCR | PPC_WRTEE |
3083                        PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3084                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3085                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
3086                        PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3087                        PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3088     pcc->msr_mask = (1ull << MSR_POW) |
3089                     (1ull << MSR_CE) |
3090                     (1ull << MSR_EE) |
3091                     (1ull << MSR_PR) |
3092                     (1ull << MSR_FP) |
3093                     (1ull << MSR_DWE) |
3094                     (1ull << MSR_DE) |
3095                     (1ull << MSR_IR) |
3096                     (1ull << MSR_DR);
3097     pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3098     pcc->excp_model = POWERPC_EXCP_40x;
3099     pcc->bus_model = PPC_FLAGS_INPUT_405;
3100     pcc->bfd_mach = bfd_mach_ppc_403;
3101     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3102                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3103 }
3104 
3105 static void init_proc_440EP(CPUPPCState *env)
3106 {
3107     /* Time base */
3108     register_tbl(env);
3109     register_BookE_sprs(env, 0x000000000000FFFFULL);
3110     register_440_sprs(env);
3111     register_usprgh_sprs(env);
3112     /* Processor identification */
3113     spr_register(env, SPR_BOOKE_PIR, "PIR",
3114                  SPR_NOACCESS, SPR_NOACCESS,
3115                  &spr_read_generic, &spr_write_pir,
3116                  0x00000000);
3117     /* XXX : not implemented */
3118     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3119                  SPR_NOACCESS, SPR_NOACCESS,
3120                  &spr_read_generic, &spr_write_generic,
3121                  0x00000000);
3122     /* XXX : not implemented */
3123     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3124                  SPR_NOACCESS, SPR_NOACCESS,
3125                  &spr_read_generic, &spr_write_generic,
3126                  0x00000000);
3127     /* XXX : not implemented */
3128     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3129                  SPR_NOACCESS, SPR_NOACCESS,
3130                  &spr_read_generic, &spr_write_generic,
3131                  0x00000000);
3132     /* XXX : not implemented */
3133     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3134                  SPR_NOACCESS, SPR_NOACCESS,
3135                  &spr_read_generic, &spr_write_generic,
3136                  0x00000000);
3137     /* XXX : not implemented */
3138     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3139                  SPR_NOACCESS, SPR_NOACCESS,
3140                  &spr_read_generic, &spr_write_generic,
3141                  0x00000000);
3142     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3143                  SPR_NOACCESS, SPR_NOACCESS,
3144                  &spr_read_generic, &spr_write_generic,
3145                  0x00000000);
3146     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3147                  SPR_NOACCESS, SPR_NOACCESS,
3148                  &spr_read_generic, &spr_write_generic,
3149                  0x00000000);
3150     /* XXX : not implemented */
3151     spr_register(env, SPR_440_CCR1, "CCR1",
3152                  SPR_NOACCESS, SPR_NOACCESS,
3153                  &spr_read_generic, &spr_write_generic,
3154                  0x00000000);
3155     /* Memory management */
3156 #if !defined(CONFIG_USER_ONLY)
3157     env->nb_tlb = 64;
3158     env->nb_ways = 1;
3159     env->id_tlbs = 0;
3160     env->tlb_type = TLB_EMB;
3161 #endif
3162     init_excp_BookE(env);
3163     env->dcache_line_size = 32;
3164     env->icache_line_size = 32;
3165     ppc40x_irq_init(env_archcpu(env));
3166 
3167     SET_FIT_PERIOD(12, 16, 20, 24);
3168     SET_WDT_PERIOD(20, 24, 28, 32);
3169 }
3170 
3171 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3172 {
3173     DeviceClass *dc = DEVICE_CLASS(oc);
3174     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3175 
3176     dc->desc = "PowerPC 440 EP";
3177     pcc->init_proc = init_proc_440EP;
3178     pcc->check_pow = check_pow_nocheck;
3179     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3180                        PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3181                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3182                        PPC_FLOAT_STFIWX |
3183                        PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3184                        PPC_CACHE | PPC_CACHE_ICBI |
3185                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3186                        PPC_MEM_TLBSYNC | PPC_MFTB |
3187                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3188                        PPC_440_SPEC;
3189     pcc->msr_mask = (1ull << MSR_POW) |
3190                     (1ull << MSR_CE) |
3191                     (1ull << MSR_EE) |
3192                     (1ull << MSR_PR) |
3193                     (1ull << MSR_FP) |
3194                     (1ull << MSR_ME) |
3195                     (1ull << MSR_FE0) |
3196                     (1ull << MSR_DWE) |
3197                     (1ull << MSR_DE) |
3198                     (1ull << MSR_FE1) |
3199                     (1ull << MSR_IR) |
3200                     (1ull << MSR_DR);
3201     pcc->mmu_model = POWERPC_MMU_BOOKE;
3202     pcc->excp_model = POWERPC_EXCP_BOOKE;
3203     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3204     pcc->bfd_mach = bfd_mach_ppc_403;
3205     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3206                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3207 }
3208 
3209 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3210 {
3211     DeviceClass *dc = DEVICE_CLASS(oc);
3212     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3213 
3214     dc->desc = "PowerPC 460 EX";
3215     pcc->init_proc = init_proc_440EP;
3216     pcc->check_pow = check_pow_nocheck;
3217     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3218                        PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3219                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3220                        PPC_FLOAT_STFIWX |
3221                        PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3222                        PPC_CACHE | PPC_CACHE_ICBI |
3223                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3224                        PPC_MEM_TLBSYNC | PPC_MFTB |
3225                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3226                        PPC_440_SPEC;
3227     pcc->msr_mask = (1ull << MSR_POW) |
3228                     (1ull << MSR_CE) |
3229                     (1ull << MSR_EE) |
3230                     (1ull << MSR_PR) |
3231                     (1ull << MSR_FP) |
3232                     (1ull << MSR_ME) |
3233                     (1ull << MSR_FE0) |
3234                     (1ull << MSR_DWE) |
3235                     (1ull << MSR_DE) |
3236                     (1ull << MSR_FE1) |
3237                     (1ull << MSR_IR) |
3238                     (1ull << MSR_DR);
3239     pcc->mmu_model = POWERPC_MMU_BOOKE;
3240     pcc->excp_model = POWERPC_EXCP_BOOKE;
3241     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3242     pcc->bfd_mach = bfd_mach_ppc_403;
3243     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3244                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3245 }
3246 
3247 static void init_proc_440GP(CPUPPCState *env)
3248 {
3249     /* Time base */
3250     register_tbl(env);
3251     register_BookE_sprs(env, 0x000000000000FFFFULL);
3252     register_440_sprs(env);
3253     register_usprgh_sprs(env);
3254     /* Processor identification */
3255     spr_register(env, SPR_BOOKE_PIR, "PIR",
3256                  SPR_NOACCESS, SPR_NOACCESS,
3257                  &spr_read_generic, &spr_write_pir,
3258                  0x00000000);
3259     /* XXX : not implemented */
3260     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3261                  SPR_NOACCESS, SPR_NOACCESS,
3262                  &spr_read_generic, &spr_write_generic,
3263                  0x00000000);
3264     /* XXX : not implemented */
3265     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3266                  SPR_NOACCESS, SPR_NOACCESS,
3267                  &spr_read_generic, &spr_write_generic,
3268                  0x00000000);
3269     /* XXX : not implemented */
3270     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3271                  SPR_NOACCESS, SPR_NOACCESS,
3272                  &spr_read_generic, &spr_write_generic,
3273                  0x00000000);
3274     /* XXX : not implemented */
3275     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3276                  SPR_NOACCESS, SPR_NOACCESS,
3277                  &spr_read_generic, &spr_write_generic,
3278                  0x00000000);
3279     /* Memory management */
3280 #if !defined(CONFIG_USER_ONLY)
3281     env->nb_tlb = 64;
3282     env->nb_ways = 1;
3283     env->id_tlbs = 0;
3284     env->tlb_type = TLB_EMB;
3285 #endif
3286     init_excp_BookE(env);
3287     env->dcache_line_size = 32;
3288     env->icache_line_size = 32;
3289     /* XXX: TODO: allocate internal IRQ controller */
3290 
3291     SET_FIT_PERIOD(12, 16, 20, 24);
3292     SET_WDT_PERIOD(20, 24, 28, 32);
3293 }
3294 
3295 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3296 {
3297     DeviceClass *dc = DEVICE_CLASS(oc);
3298     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3299 
3300     dc->desc = "PowerPC 440 GP";
3301     pcc->init_proc = init_proc_440GP;
3302     pcc->check_pow = check_pow_nocheck;
3303     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3304                        PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3305                        PPC_CACHE | PPC_CACHE_ICBI |
3306                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3307                        PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3308                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3309                        PPC_440_SPEC;
3310     pcc->msr_mask = (1ull << MSR_POW) |
3311                     (1ull << MSR_CE) |
3312                     (1ull << MSR_EE) |
3313                     (1ull << MSR_PR) |
3314                     (1ull << MSR_FP) |
3315                     (1ull << MSR_ME) |
3316                     (1ull << MSR_FE0) |
3317                     (1ull << MSR_DWE) |
3318                     (1ull << MSR_DE) |
3319                     (1ull << MSR_FE1) |
3320                     (1ull << MSR_IR) |
3321                     (1ull << MSR_DR);
3322     pcc->mmu_model = POWERPC_MMU_BOOKE;
3323     pcc->excp_model = POWERPC_EXCP_BOOKE;
3324     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3325     pcc->bfd_mach = bfd_mach_ppc_403;
3326     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3327                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3328 }
3329 
3330 static void init_proc_440x4(CPUPPCState *env)
3331 {
3332     /* Time base */
3333     register_tbl(env);
3334     register_BookE_sprs(env, 0x000000000000FFFFULL);
3335     register_440_sprs(env);
3336     register_usprgh_sprs(env);
3337     /* Processor identification */
3338     spr_register(env, SPR_BOOKE_PIR, "PIR",
3339                  SPR_NOACCESS, SPR_NOACCESS,
3340                  &spr_read_generic, &spr_write_pir,
3341                  0x00000000);
3342     /* XXX : not implemented */
3343     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3344                  SPR_NOACCESS, SPR_NOACCESS,
3345                  &spr_read_generic, &spr_write_generic,
3346                  0x00000000);
3347     /* XXX : not implemented */
3348     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3349                  SPR_NOACCESS, SPR_NOACCESS,
3350                  &spr_read_generic, &spr_write_generic,
3351                  0x00000000);
3352     /* XXX : not implemented */
3353     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3354                  SPR_NOACCESS, SPR_NOACCESS,
3355                  &spr_read_generic, &spr_write_generic,
3356                  0x00000000);
3357     /* XXX : not implemented */
3358     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3359                  SPR_NOACCESS, SPR_NOACCESS,
3360                  &spr_read_generic, &spr_write_generic,
3361                  0x00000000);
3362     /* Memory management */
3363 #if !defined(CONFIG_USER_ONLY)
3364     env->nb_tlb = 64;
3365     env->nb_ways = 1;
3366     env->id_tlbs = 0;
3367     env->tlb_type = TLB_EMB;
3368 #endif
3369     init_excp_BookE(env);
3370     env->dcache_line_size = 32;
3371     env->icache_line_size = 32;
3372     /* XXX: TODO: allocate internal IRQ controller */
3373 
3374     SET_FIT_PERIOD(12, 16, 20, 24);
3375     SET_WDT_PERIOD(20, 24, 28, 32);
3376 }
3377 
3378 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3379 {
3380     DeviceClass *dc = DEVICE_CLASS(oc);
3381     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3382 
3383     dc->desc = "PowerPC 440x4";
3384     pcc->init_proc = init_proc_440x4;
3385     pcc->check_pow = check_pow_nocheck;
3386     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3387                        PPC_DCR | PPC_WRTEE |
3388                        PPC_CACHE | PPC_CACHE_ICBI |
3389                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3390                        PPC_MEM_TLBSYNC | PPC_MFTB |
3391                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3392                        PPC_440_SPEC;
3393     pcc->msr_mask = (1ull << MSR_POW) |
3394                     (1ull << MSR_CE) |
3395                     (1ull << MSR_EE) |
3396                     (1ull << MSR_PR) |
3397                     (1ull << MSR_FP) |
3398                     (1ull << MSR_ME) |
3399                     (1ull << MSR_FE0) |
3400                     (1ull << MSR_DWE) |
3401                     (1ull << MSR_DE) |
3402                     (1ull << MSR_FE1) |
3403                     (1ull << MSR_IR) |
3404                     (1ull << MSR_DR);
3405     pcc->mmu_model = POWERPC_MMU_BOOKE;
3406     pcc->excp_model = POWERPC_EXCP_BOOKE;
3407     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3408     pcc->bfd_mach = bfd_mach_ppc_403;
3409     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3410                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3411 }
3412 
3413 static void init_proc_440x5(CPUPPCState *env)
3414 {
3415     /* Time base */
3416     register_tbl(env);
3417     register_BookE_sprs(env, 0x000000000000FFFFULL);
3418     register_440_sprs(env);
3419     register_usprgh_sprs(env);
3420     /* Processor identification */
3421     spr_register(env, SPR_BOOKE_PIR, "PIR",
3422                  SPR_NOACCESS, SPR_NOACCESS,
3423                  &spr_read_generic, &spr_write_pir,
3424                  0x00000000);
3425     /* XXX : not implemented */
3426     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3427                  SPR_NOACCESS, SPR_NOACCESS,
3428                  &spr_read_generic, &spr_write_generic,
3429                  0x00000000);
3430     /* XXX : not implemented */
3431     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3432                  SPR_NOACCESS, SPR_NOACCESS,
3433                  &spr_read_generic, &spr_write_generic,
3434                  0x00000000);
3435     /* XXX : not implemented */
3436     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3437                  SPR_NOACCESS, SPR_NOACCESS,
3438                  &spr_read_generic, &spr_write_generic,
3439                  0x00000000);
3440     /* XXX : not implemented */
3441     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3442                  SPR_NOACCESS, SPR_NOACCESS,
3443                  &spr_read_generic, &spr_write_generic,
3444                  0x00000000);
3445     /* XXX : not implemented */
3446     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3447                  SPR_NOACCESS, SPR_NOACCESS,
3448                  &spr_read_generic, &spr_write_generic,
3449                  0x00000000);
3450     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3451                  SPR_NOACCESS, SPR_NOACCESS,
3452                  &spr_read_generic, &spr_write_generic,
3453                  0x00000000);
3454     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3455                  SPR_NOACCESS, SPR_NOACCESS,
3456                  &spr_read_generic, &spr_write_generic,
3457                  0x00000000);
3458     /* XXX : not implemented */
3459     spr_register(env, SPR_440_CCR1, "CCR1",
3460                  SPR_NOACCESS, SPR_NOACCESS,
3461                  &spr_read_generic, &spr_write_generic,
3462                  0x00000000);
3463     /* Memory management */
3464 #if !defined(CONFIG_USER_ONLY)
3465     env->nb_tlb = 64;
3466     env->nb_ways = 1;
3467     env->id_tlbs = 0;
3468     env->tlb_type = TLB_EMB;
3469 #endif
3470     init_excp_BookE(env);
3471     env->dcache_line_size = 32;
3472     env->icache_line_size = 32;
3473     ppc40x_irq_init(env_archcpu(env));
3474 
3475     SET_FIT_PERIOD(12, 16, 20, 24);
3476     SET_WDT_PERIOD(20, 24, 28, 32);
3477 }
3478 
3479 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3480 {
3481     DeviceClass *dc = DEVICE_CLASS(oc);
3482     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3483 
3484     dc->desc = "PowerPC 440x5";
3485     pcc->init_proc = init_proc_440x5;
3486     pcc->check_pow = check_pow_nocheck;
3487     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3488                        PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3489                        PPC_CACHE | PPC_CACHE_ICBI |
3490                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3491                        PPC_MEM_TLBSYNC | PPC_MFTB |
3492                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3493                        PPC_440_SPEC;
3494     pcc->msr_mask = (1ull << MSR_POW) |
3495                     (1ull << MSR_CE) |
3496                     (1ull << MSR_EE) |
3497                     (1ull << MSR_PR) |
3498                     (1ull << MSR_FP) |
3499                     (1ull << MSR_ME) |
3500                     (1ull << MSR_FE0) |
3501                     (1ull << MSR_DWE) |
3502                     (1ull << MSR_DE) |
3503                     (1ull << MSR_FE1) |
3504                     (1ull << MSR_IR) |
3505                     (1ull << MSR_DR);
3506     pcc->mmu_model = POWERPC_MMU_BOOKE;
3507     pcc->excp_model = POWERPC_EXCP_BOOKE;
3508     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3509     pcc->bfd_mach = bfd_mach_ppc_403;
3510     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3511                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3512 }
3513 
3514 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
3515 {
3516     DeviceClass *dc = DEVICE_CLASS(oc);
3517     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3518 
3519     dc->desc = "PowerPC 440x5 with double precision FPU";
3520     pcc->init_proc = init_proc_440x5;
3521     pcc->check_pow = check_pow_nocheck;
3522     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3523                        PPC_FLOAT | PPC_FLOAT_FSQRT |
3524                        PPC_FLOAT_STFIWX |
3525                        PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3526                        PPC_CACHE | PPC_CACHE_ICBI |
3527                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3528                        PPC_MEM_TLBSYNC | PPC_MFTB |
3529                        PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3530                        PPC_440_SPEC;
3531     pcc->insns_flags2 = PPC2_FP_CVT_S64;
3532     pcc->msr_mask = (1ull << MSR_POW) |
3533                     (1ull << MSR_CE) |
3534                     (1ull << MSR_EE) |
3535                     (1ull << MSR_PR) |
3536                     (1ull << MSR_FP) |
3537                     (1ull << MSR_ME) |
3538                     (1ull << MSR_FE0) |
3539                     (1ull << MSR_DWE) |
3540                     (1ull << MSR_DE) |
3541                     (1ull << MSR_FE1) |
3542                     (1ull << MSR_IR) |
3543                     (1ull << MSR_DR);
3544     pcc->mmu_model = POWERPC_MMU_BOOKE;
3545     pcc->excp_model = POWERPC_EXCP_BOOKE;
3546     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3547     pcc->bfd_mach = bfd_mach_ppc_403;
3548     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3549                  POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3550 }
3551 
3552 static void init_proc_MPC5xx(CPUPPCState *env)
3553 {
3554     /* Time base */
3555     register_tbl(env);
3556     register_5xx_8xx_sprs(env);
3557     register_5xx_sprs(env);
3558     init_excp_MPC5xx(env);
3559     env->dcache_line_size = 32;
3560     env->icache_line_size = 32;
3561     /* XXX: TODO: allocate internal IRQ controller */
3562 }
3563 
3564 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3565 {
3566     DeviceClass *dc = DEVICE_CLASS(oc);
3567     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3568 
3569     dc->desc = "Freescale 5xx cores (aka RCPU)";
3570     pcc->init_proc = init_proc_MPC5xx;
3571     pcc->check_pow = check_pow_none;
3572     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3573                        PPC_MEM_EIEIO | PPC_MEM_SYNC |
3574                        PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3575                        PPC_MFTB;
3576     pcc->msr_mask = (1ull << MSR_ILE) |
3577                     (1ull << MSR_EE) |
3578                     (1ull << MSR_PR) |
3579                     (1ull << MSR_FP) |
3580                     (1ull << MSR_ME) |
3581                     (1ull << MSR_FE0) |
3582                     (1ull << MSR_SE) |
3583                     (1ull << MSR_DE) |
3584                     (1ull << MSR_FE1) |
3585                     (1ull << MSR_EP) |
3586                     (1ull << MSR_RI) |
3587                     (1ull << MSR_LE);
3588     pcc->mmu_model = POWERPC_MMU_REAL;
3589     pcc->excp_model = POWERPC_EXCP_603;
3590     pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3591     pcc->bfd_mach = bfd_mach_ppc_505;
3592     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3593                  POWERPC_FLAG_BUS_CLK;
3594 }
3595 
3596 static void init_proc_MPC8xx(CPUPPCState *env)
3597 {
3598     /* Time base */
3599     register_tbl(env);
3600     register_5xx_8xx_sprs(env);
3601     register_8xx_sprs(env);
3602     init_excp_MPC8xx(env);
3603     env->dcache_line_size = 32;
3604     env->icache_line_size = 32;
3605     /* XXX: TODO: allocate internal IRQ controller */
3606 }
3607 
3608 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
3609 {
3610     DeviceClass *dc = DEVICE_CLASS(oc);
3611     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3612 
3613     dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
3614     pcc->init_proc = init_proc_MPC8xx;
3615     pcc->check_pow = check_pow_none;
3616     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
3617                        PPC_MEM_EIEIO | PPC_MEM_SYNC |
3618                        PPC_CACHE_ICBI | PPC_MFTB;
3619     pcc->msr_mask = (1ull << MSR_ILE) |
3620                     (1ull << MSR_EE) |
3621                     (1ull << MSR_PR) |
3622                     (1ull << MSR_FP) |
3623                     (1ull << MSR_ME) |
3624                     (1ull << MSR_SE) |
3625                     (1ull << MSR_DE) |
3626                     (1ull << MSR_EP) |
3627                     (1ull << MSR_IR) |
3628                     (1ull << MSR_DR) |
3629                     (1ull << MSR_RI) |
3630                     (1ull << MSR_LE);
3631     pcc->mmu_model = POWERPC_MMU_MPC8xx;
3632     pcc->excp_model = POWERPC_EXCP_603;
3633     pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3634     pcc->bfd_mach = bfd_mach_ppc_860;
3635     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3636                  POWERPC_FLAG_BUS_CLK;
3637 }
3638 
3639 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3640 
3641 static void init_proc_G2(CPUPPCState *env)
3642 {
3643     register_ne_601_sprs(env);
3644     register_sdr1_sprs(env);
3645     register_G2_755_sprs(env);
3646     register_G2_sprs(env);
3647     /* Time base */
3648     register_tbl(env);
3649     /* External access control */
3650     /* XXX : not implemented */
3651     spr_register(env, SPR_EAR, "EAR",
3652                  SPR_NOACCESS, SPR_NOACCESS,
3653                  &spr_read_generic, &spr_write_generic,
3654                  0x00000000);
3655     /* Hardware implementation register */
3656     /* XXX : not implemented */
3657     spr_register(env, SPR_HID0, "HID0",
3658                  SPR_NOACCESS, SPR_NOACCESS,
3659                  &spr_read_generic, &spr_write_generic,
3660                  0x00000000);
3661     /* XXX : not implemented */
3662     spr_register(env, SPR_HID1, "HID1",
3663                  SPR_NOACCESS, SPR_NOACCESS,
3664                  &spr_read_generic, &spr_write_generic,
3665                  0x00000000);
3666     /* XXX : not implemented */
3667     spr_register(env, SPR_HID2, "HID2",
3668                  SPR_NOACCESS, SPR_NOACCESS,
3669                  &spr_read_generic, &spr_write_generic,
3670                  0x00000000);
3671     /* Memory management */
3672     register_low_BATs(env);
3673     register_high_BATs(env);
3674     register_6xx_7xx_soft_tlb(env, 64, 2);
3675     init_excp_G2(env);
3676     env->dcache_line_size = 32;
3677     env->icache_line_size = 32;
3678     /* Allocate hardware IRQ controller */
3679     ppc6xx_irq_init(env_archcpu(env));
3680 }
3681 
3682 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3683 {
3684     DeviceClass *dc = DEVICE_CLASS(oc);
3685     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3686 
3687     dc->desc = "PowerPC G2";
3688     pcc->init_proc = init_proc_G2;
3689     pcc->check_pow = check_pow_hid0;
3690     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3691                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3692                        PPC_FLOAT_STFIWX |
3693                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3694                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
3695                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3696                        PPC_SEGMENT | PPC_EXTERN;
3697     pcc->msr_mask = (1ull << MSR_POW) |
3698                     (1ull << MSR_TGPR) |
3699                     (1ull << MSR_EE) |
3700                     (1ull << MSR_PR) |
3701                     (1ull << MSR_FP) |
3702                     (1ull << MSR_ME) |
3703                     (1ull << MSR_FE0) |
3704                     (1ull << MSR_SE) |
3705                     (1ull << MSR_DE) |
3706                     (1ull << MSR_FE1) |
3707                     (1ull << MSR_AL) |
3708                     (1ull << MSR_EP) |
3709                     (1ull << MSR_IR) |
3710                     (1ull << MSR_DR) |
3711                     (1ull << MSR_RI);
3712     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3713     pcc->excp_model = POWERPC_EXCP_G2;
3714     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3715     pcc->bfd_mach = bfd_mach_ppc_ec603e;
3716     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3717                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3718 }
3719 
3720 static void init_proc_G2LE(CPUPPCState *env)
3721 {
3722     register_ne_601_sprs(env);
3723     register_sdr1_sprs(env);
3724     register_G2_755_sprs(env);
3725     register_G2_sprs(env);
3726     /* Time base */
3727     register_tbl(env);
3728     /* External access control */
3729     /* XXX : not implemented */
3730     spr_register(env, SPR_EAR, "EAR",
3731                  SPR_NOACCESS, SPR_NOACCESS,
3732                  &spr_read_generic, &spr_write_generic,
3733                  0x00000000);
3734     /* Hardware implementation register */
3735     /* XXX : not implemented */
3736     spr_register(env, SPR_HID0, "HID0",
3737                  SPR_NOACCESS, SPR_NOACCESS,
3738                  &spr_read_generic, &spr_write_generic,
3739                  0x00000000);
3740     /* XXX : not implemented */
3741     spr_register(env, SPR_HID1, "HID1",
3742                  SPR_NOACCESS, SPR_NOACCESS,
3743                  &spr_read_generic, &spr_write_generic,
3744                  0x00000000);
3745     /* XXX : not implemented */
3746     spr_register(env, SPR_HID2, "HID2",
3747                  SPR_NOACCESS, SPR_NOACCESS,
3748                  &spr_read_generic, &spr_write_generic,
3749                  0x00000000);
3750 
3751     /* Memory management */
3752     register_low_BATs(env);
3753     register_high_BATs(env);
3754     register_6xx_7xx_soft_tlb(env, 64, 2);
3755     init_excp_G2(env);
3756     env->dcache_line_size = 32;
3757     env->icache_line_size = 32;
3758     /* Allocate hardware IRQ controller */
3759     ppc6xx_irq_init(env_archcpu(env));
3760 }
3761 
3762 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3763 {
3764     DeviceClass *dc = DEVICE_CLASS(oc);
3765     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3766 
3767     dc->desc = "PowerPC G2LE";
3768     pcc->init_proc = init_proc_G2LE;
3769     pcc->check_pow = check_pow_hid0;
3770     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3771                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3772                        PPC_FLOAT_STFIWX |
3773                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3774                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
3775                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3776                        PPC_SEGMENT | PPC_EXTERN;
3777     pcc->msr_mask = (1ull << MSR_POW) |
3778                     (1ull << MSR_TGPR) |
3779                     (1ull << MSR_ILE) |
3780                     (1ull << MSR_EE) |
3781                     (1ull << MSR_PR) |
3782                     (1ull << MSR_FP) |
3783                     (1ull << MSR_ME) |
3784                     (1ull << MSR_FE0) |
3785                     (1ull << MSR_SE) |
3786                     (1ull << MSR_DE) |
3787                     (1ull << MSR_FE1) |
3788                     (1ull << MSR_AL) |
3789                     (1ull << MSR_EP) |
3790                     (1ull << MSR_IR) |
3791                     (1ull << MSR_DR) |
3792                     (1ull << MSR_RI) |
3793                     (1ull << MSR_LE);
3794     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3795     pcc->excp_model = POWERPC_EXCP_G2;
3796     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3797     pcc->bfd_mach = bfd_mach_ppc_ec603e;
3798     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3799                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3800 }
3801 
3802 static void init_proc_e200(CPUPPCState *env)
3803 {
3804     /* Time base */
3805     register_tbl(env);
3806     register_BookE_sprs(env, 0x000000070000FFFFULL);
3807     /* XXX : not implemented */
3808     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3809                  &spr_read_spefscr, &spr_write_spefscr,
3810                  &spr_read_spefscr, &spr_write_spefscr,
3811                  0x00000000);
3812     /* Memory management */
3813     register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3814     /* XXX : not implemented */
3815     spr_register(env, SPR_HID0, "HID0",
3816                  SPR_NOACCESS, SPR_NOACCESS,
3817                  &spr_read_generic, &spr_write_generic,
3818                  0x00000000);
3819     /* XXX : not implemented */
3820     spr_register(env, SPR_HID1, "HID1",
3821                  SPR_NOACCESS, SPR_NOACCESS,
3822                  &spr_read_generic, &spr_write_generic,
3823                  0x00000000);
3824     /* XXX : not implemented */
3825     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3826                  SPR_NOACCESS, SPR_NOACCESS,
3827                  &spr_read_generic, &spr_write_generic,
3828                  0x00000000);
3829     /* XXX : not implemented */
3830     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3831                  SPR_NOACCESS, SPR_NOACCESS,
3832                  &spr_read_generic, &spr_write_generic,
3833                  0x00000000);
3834     /* XXX : not implemented */
3835     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3836                  SPR_NOACCESS, SPR_NOACCESS,
3837                  &spr_read_generic, &spr_write_generic,
3838                  0x00000000);
3839     /* XXX : not implemented */
3840     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3841                  SPR_NOACCESS, SPR_NOACCESS,
3842                  &spr_read_generic, &spr_write_generic,
3843                  0x00000000);
3844     /* XXX : not implemented */
3845     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3846                  SPR_NOACCESS, SPR_NOACCESS,
3847                  &spr_read_generic, &spr_write_generic,
3848                  0x00000000);
3849     /* XXX : not implemented */
3850     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3851                  &spr_read_generic, SPR_NOACCESS,
3852                  &spr_read_generic, SPR_NOACCESS,
3853                  0x00000000);
3854     /* XXX : not implemented */
3855     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3856                  SPR_NOACCESS, SPR_NOACCESS,
3857                  &spr_read_generic, &spr_write_generic,
3858                  0x00000000);
3859     /* XXX : not implemented */
3860     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3861                  SPR_NOACCESS, SPR_NOACCESS,
3862                  &spr_read_generic, &spr_write_generic,
3863                  0x00000000);
3864     /* XXX : not implemented */
3865     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3866                  SPR_NOACCESS, SPR_NOACCESS,
3867                  &spr_read_generic, &spr_write_generic,
3868                  0x00000000);
3869     /* XXX : not implemented */
3870     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3871                  SPR_NOACCESS, SPR_NOACCESS,
3872                  &spr_read_generic, &spr_write_generic,
3873                  0x00000000);
3874     /* XXX : not implemented */
3875     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3876                  SPR_NOACCESS, SPR_NOACCESS,
3877                  &spr_read_generic, &spr_write_generic,
3878                  0x00000000);
3879     /* XXX : not implemented */
3880     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3881                  SPR_NOACCESS, SPR_NOACCESS,
3882                  &spr_read_generic, &spr_write_generic,
3883                  0x00000000);
3884     /* XXX : not implemented */
3885     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3886                  SPR_NOACCESS, SPR_NOACCESS,
3887                  &spr_read_generic, &spr_write_generic,
3888                  0x00000000); /* TOFIX */
3889     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3890                  SPR_NOACCESS, SPR_NOACCESS,
3891                  &spr_read_generic, &spr_write_generic,
3892                  0x00000000);
3893     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3894                  SPR_NOACCESS, SPR_NOACCESS,
3895                  &spr_read_generic, &spr_write_generic,
3896                  0x00000000);
3897 #if !defined(CONFIG_USER_ONLY)
3898     env->nb_tlb = 64;
3899     env->nb_ways = 1;
3900     env->id_tlbs = 0;
3901     env->tlb_type = TLB_EMB;
3902 #endif
3903     init_excp_e200(env, 0xFFFF0000UL);
3904     env->dcache_line_size = 32;
3905     env->icache_line_size = 32;
3906     /* XXX: TODO: allocate internal IRQ controller */
3907 }
3908 
3909 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3910 {
3911     DeviceClass *dc = DEVICE_CLASS(oc);
3912     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3913 
3914     dc->desc = "e200 core";
3915     pcc->init_proc = init_proc_e200;
3916     pcc->check_pow = check_pow_hid0;
3917     /*
3918      * XXX: unimplemented instructions:
3919      * dcblc
3920      * dcbtlst
3921      * dcbtstls
3922      * icblc
3923      * icbtls
3924      * tlbivax
3925      * all SPE multiply-accumulate instructions
3926      */
3927     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3928                        PPC_SPE | PPC_SPE_SINGLE |
3929                        PPC_WRTEE | PPC_RFDI |
3930                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3931                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3932                        PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3933                        PPC_BOOKE;
3934     pcc->msr_mask = (1ull << MSR_UCLE) |
3935                     (1ull << MSR_SPE) |
3936                     (1ull << MSR_POW) |
3937                     (1ull << MSR_CE) |
3938                     (1ull << MSR_EE) |
3939                     (1ull << MSR_PR) |
3940                     (1ull << MSR_FP) |
3941                     (1ull << MSR_ME) |
3942                     (1ull << MSR_FE0) |
3943                     (1ull << MSR_DWE) |
3944                     (1ull << MSR_DE) |
3945                     (1ull << MSR_FE1) |
3946                     (1ull << MSR_IR) |
3947                     (1ull << MSR_DR);
3948     pcc->mmu_model = POWERPC_MMU_BOOKE206;
3949     pcc->excp_model = POWERPC_EXCP_BOOKE;
3950     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3951     pcc->bfd_mach = bfd_mach_ppc_860;
3952     pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3953                  POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3954                  POWERPC_FLAG_BUS_CLK;
3955 }
3956 
3957 static void init_proc_e300(CPUPPCState *env)
3958 {
3959     register_ne_601_sprs(env);
3960     register_sdr1_sprs(env);
3961     register_603_sprs(env);
3962     /* Time base */
3963     register_tbl(env);
3964     /* hardware implementation registers */
3965     /* XXX : not implemented */
3966     spr_register(env, SPR_HID0, "HID0",
3967                  SPR_NOACCESS, SPR_NOACCESS,
3968                  &spr_read_generic, &spr_write_generic,
3969                  0x00000000);
3970     /* XXX : not implemented */
3971     spr_register(env, SPR_HID1, "HID1",
3972                  SPR_NOACCESS, SPR_NOACCESS,
3973                  &spr_read_generic, &spr_write_generic,
3974                  0x00000000);
3975     /* XXX : not implemented */
3976     spr_register(env, SPR_HID2, "HID2",
3977                  SPR_NOACCESS, SPR_NOACCESS,
3978                  &spr_read_generic, &spr_write_generic,
3979                  0x00000000);
3980     /* Breakpoints */
3981     /* XXX : not implemented */
3982     spr_register(env, SPR_DABR, "DABR",
3983                  SPR_NOACCESS, SPR_NOACCESS,
3984                  &spr_read_generic, &spr_write_generic,
3985                  0x00000000);
3986     /* XXX : not implemented */
3987     spr_register(env, SPR_DABR2, "DABR2",
3988                  SPR_NOACCESS, SPR_NOACCESS,
3989                  &spr_read_generic, &spr_write_generic,
3990                  0x00000000);
3991     /* XXX : not implemented */
3992     spr_register(env, SPR_IABR2, "IABR2",
3993                  SPR_NOACCESS, SPR_NOACCESS,
3994                  &spr_read_generic, &spr_write_generic,
3995                  0x00000000);
3996     /* XXX : not implemented */
3997     spr_register(env, SPR_IBCR, "IBCR",
3998                  SPR_NOACCESS, SPR_NOACCESS,
3999                  &spr_read_generic, &spr_write_generic,
4000                  0x00000000);
4001     /* XXX : not implemented */
4002     spr_register(env, SPR_DBCR, "DBCR",
4003                  SPR_NOACCESS, SPR_NOACCESS,
4004                  &spr_read_generic, &spr_write_generic,
4005                  0x00000000);
4006     /* Memory management */
4007     register_low_BATs(env);
4008     register_high_BATs(env);
4009     register_6xx_7xx_soft_tlb(env, 64, 2);
4010     init_excp_603(env);
4011     env->dcache_line_size = 32;
4012     env->icache_line_size = 32;
4013     /* Allocate hardware IRQ controller */
4014     ppc6xx_irq_init(env_archcpu(env));
4015 }
4016 
4017 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4018 {
4019     DeviceClass *dc = DEVICE_CLASS(oc);
4020     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4021 
4022     dc->desc = "e300 core";
4023     pcc->init_proc = init_proc_e300;
4024     pcc->check_pow = check_pow_hid0;
4025     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4026                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4027                        PPC_FLOAT_STFIWX |
4028                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4029                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4030                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4031                        PPC_SEGMENT | PPC_EXTERN;
4032     pcc->msr_mask = (1ull << MSR_POW) |
4033                     (1ull << MSR_TGPR) |
4034                     (1ull << MSR_ILE) |
4035                     (1ull << MSR_EE) |
4036                     (1ull << MSR_PR) |
4037                     (1ull << MSR_FP) |
4038                     (1ull << MSR_ME) |
4039                     (1ull << MSR_FE0) |
4040                     (1ull << MSR_SE) |
4041                     (1ull << MSR_DE) |
4042                     (1ull << MSR_FE1) |
4043                     (1ull << MSR_AL) |
4044                     (1ull << MSR_EP) |
4045                     (1ull << MSR_IR) |
4046                     (1ull << MSR_DR) |
4047                     (1ull << MSR_RI) |
4048                     (1ull << MSR_LE);
4049     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4050     pcc->excp_model = POWERPC_EXCP_603;
4051     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4052     pcc->bfd_mach = bfd_mach_ppc_603;
4053     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4054                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4055 }
4056 
4057 enum fsl_e500_version {
4058     fsl_e500v1,
4059     fsl_e500v2,
4060     fsl_e500mc,
4061     fsl_e5500,
4062     fsl_e6500,
4063 };
4064 
4065 static void init_proc_e500(CPUPPCState *env, int version)
4066 {
4067     uint32_t tlbncfg[2];
4068     uint64_t ivor_mask;
4069     uint64_t ivpr_mask = 0xFFFF0000ULL;
4070     uint32_t l1cfg0 = 0x3800  /* 8 ways */
4071                     | 0x0020; /* 32 kb */
4072     uint32_t l1cfg1 = 0x3800  /* 8 ways */
4073                     | 0x0020; /* 32 kb */
4074     uint32_t mmucfg = 0;
4075 #if !defined(CONFIG_USER_ONLY)
4076     int i;
4077 #endif
4078 
4079     /* Time base */
4080     register_tbl(env);
4081     /*
4082      * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4083      *     complain when accessing them.
4084      * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
4085      */
4086     switch (version) {
4087     case fsl_e500v1:
4088     case fsl_e500v2:
4089     default:
4090         ivor_mask = 0x0000000F0000FFFFULL;
4091         break;
4092     case fsl_e500mc:
4093     case fsl_e5500:
4094         ivor_mask = 0x000003FE0000FFFFULL;
4095         break;
4096     case fsl_e6500:
4097         ivor_mask = 0x000003FF0000FFFFULL;
4098         break;
4099     }
4100     register_BookE_sprs(env, ivor_mask);
4101     register_usprg3_sprs(env);
4102     /* Processor identification */
4103     spr_register(env, SPR_BOOKE_PIR, "PIR",
4104                  SPR_NOACCESS, SPR_NOACCESS,
4105                  &spr_read_generic, &spr_write_pir,
4106                  0x00000000);
4107     /* XXX : not implemented */
4108     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4109                  &spr_read_spefscr, &spr_write_spefscr,
4110                  &spr_read_spefscr, &spr_write_spefscr,
4111                  0x00000000);
4112 #if !defined(CONFIG_USER_ONLY)
4113     /* Memory management */
4114     env->nb_pids = 3;
4115     env->nb_ways = 2;
4116     env->id_tlbs = 0;
4117     switch (version) {
4118     case fsl_e500v1:
4119         tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
4120         tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4121         break;
4122     case fsl_e500v2:
4123         tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4124         tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4125         break;
4126     case fsl_e500mc:
4127     case fsl_e5500:
4128         tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
4129         tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4130         break;
4131     case fsl_e6500:
4132         mmucfg = 0x6510B45;
4133         env->nb_pids = 1;
4134         tlbncfg[0] = 0x08052400;
4135         tlbncfg[1] = 0x40028040;
4136         break;
4137     default:
4138         cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4139                   env->spr[SPR_PVR]);
4140     }
4141 #endif
4142     /* Cache sizes */
4143     switch (version) {
4144     case fsl_e500v1:
4145     case fsl_e500v2:
4146         env->dcache_line_size = 32;
4147         env->icache_line_size = 32;
4148         break;
4149     case fsl_e500mc:
4150     case fsl_e5500:
4151         env->dcache_line_size = 64;
4152         env->icache_line_size = 64;
4153         l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4154         l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4155         break;
4156     case fsl_e6500:
4157         env->dcache_line_size = 32;
4158         env->icache_line_size = 32;
4159         l1cfg0 |= 0x0F83820;
4160         l1cfg1 |= 0x0B83820;
4161         break;
4162     default:
4163         cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
4164                   env->spr[SPR_PVR]);
4165     }
4166     register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
4167     /* XXX : not implemented */
4168     spr_register(env, SPR_HID0, "HID0",
4169                  SPR_NOACCESS, SPR_NOACCESS,
4170                  &spr_read_generic, &spr_write_generic,
4171                  0x00000000);
4172     /* XXX : not implemented */
4173     spr_register(env, SPR_HID1, "HID1",
4174                  SPR_NOACCESS, SPR_NOACCESS,
4175                  &spr_read_generic, &spr_write_generic,
4176                  0x00000000);
4177     /* XXX : not implemented */
4178     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4179                  SPR_NOACCESS, SPR_NOACCESS,
4180                  &spr_read_generic, &spr_write_generic,
4181                  0x00000000);
4182     /* XXX : not implemented */
4183     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4184                  SPR_NOACCESS, SPR_NOACCESS,
4185                  &spr_read_generic, &spr_write_generic,
4186                  0x00000000);
4187     /* XXX : not implemented */
4188     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4189                  SPR_NOACCESS, SPR_NOACCESS,
4190                  &spr_read_generic, &spr_write_generic,
4191                  0x00000000);
4192     /* XXX : not implemented */
4193     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4194                  SPR_NOACCESS, SPR_NOACCESS,
4195                  &spr_read_generic, &spr_write_generic,
4196                  0x00000000);
4197     /* XXX : not implemented */
4198     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4199                  SPR_NOACCESS, SPR_NOACCESS,
4200                  &spr_read_generic, &spr_write_generic,
4201                  0x00000000);
4202     /* XXX : not implemented */
4203     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4204                  SPR_NOACCESS, SPR_NOACCESS,
4205                  &spr_read_generic, &spr_write_generic,
4206                  0x00000000);
4207     /* XXX : not implemented */
4208     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4209                  &spr_read_generic, SPR_NOACCESS,
4210                  &spr_read_generic, SPR_NOACCESS,
4211                  l1cfg0);
4212     spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4213                  &spr_read_generic, SPR_NOACCESS,
4214                  &spr_read_generic, SPR_NOACCESS,
4215                  l1cfg1);
4216     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4217                  SPR_NOACCESS, SPR_NOACCESS,
4218                  &spr_read_generic, &spr_write_e500_l1csr0,
4219                  0x00000000);
4220     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4221                  SPR_NOACCESS, SPR_NOACCESS,
4222                  &spr_read_generic, &spr_write_e500_l1csr1,
4223                  0x00000000);
4224     if (version != fsl_e500v1 && version != fsl_e500v2) {
4225         spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
4226                      SPR_NOACCESS, SPR_NOACCESS,
4227                      &spr_read_generic, &spr_write_e500_l2csr0,
4228                      0x00000000);
4229     }
4230     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4231                  SPR_NOACCESS, SPR_NOACCESS,
4232                  &spr_read_generic, &spr_write_generic,
4233                  0x00000000);
4234     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4235                  SPR_NOACCESS, SPR_NOACCESS,
4236                  &spr_read_generic, &spr_write_generic,
4237                  0x00000000);
4238     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4239                  SPR_NOACCESS, SPR_NOACCESS,
4240                  &spr_read_generic, &spr_write_booke206_mmucsr0,
4241                  0x00000000);
4242     spr_register(env, SPR_BOOKE_EPR, "EPR",
4243                  SPR_NOACCESS, SPR_NOACCESS,
4244                  &spr_read_generic, SPR_NOACCESS,
4245                  0x00000000);
4246     /* XXX better abstract into Emb.xxx features */
4247     if ((version == fsl_e5500) || (version == fsl_e6500)) {
4248         spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4249                      SPR_NOACCESS, SPR_NOACCESS,
4250                      &spr_read_generic, &spr_write_generic,
4251                      0x00000000);
4252         spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4253                      SPR_NOACCESS, SPR_NOACCESS,
4254                      &spr_read_mas73, &spr_write_mas73,
4255                      0x00000000);
4256         ivpr_mask = (target_ulong)~0xFFFFULL;
4257     }
4258 
4259     if (version == fsl_e6500) {
4260         /* Thread identification */
4261         spr_register(env, SPR_TIR, "TIR",
4262                      SPR_NOACCESS, SPR_NOACCESS,
4263                      &spr_read_generic, SPR_NOACCESS,
4264                      0x00000000);
4265         spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
4266                      SPR_NOACCESS, SPR_NOACCESS,
4267                      &spr_read_generic, SPR_NOACCESS,
4268                      0x00000004);
4269         spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
4270                      SPR_NOACCESS, SPR_NOACCESS,
4271                      &spr_read_generic, SPR_NOACCESS,
4272                      0x7FFFFFFC);
4273     }
4274 
4275 #if !defined(CONFIG_USER_ONLY)
4276     env->nb_tlb = 0;
4277     env->tlb_type = TLB_MAS;
4278     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4279         env->nb_tlb += booke206_tlb_size(env, i);
4280     }
4281 #endif
4282 
4283     init_excp_e200(env, ivpr_mask);
4284     /* Allocate hardware IRQ controller */
4285     ppce500_irq_init(env_archcpu(env));
4286 }
4287 
4288 static void init_proc_e500v1(CPUPPCState *env)
4289 {
4290     init_proc_e500(env, fsl_e500v1);
4291 }
4292 
4293 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4294 {
4295     DeviceClass *dc = DEVICE_CLASS(oc);
4296     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4297 
4298     dc->desc = "e500v1 core";
4299     pcc->init_proc = init_proc_e500v1;
4300     pcc->check_pow = check_pow_hid0;
4301     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4302                        PPC_SPE | PPC_SPE_SINGLE |
4303                        PPC_WRTEE | PPC_RFDI |
4304                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4305                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4306                        PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4307     pcc->insns_flags2 = PPC2_BOOKE206;
4308     pcc->msr_mask = (1ull << MSR_UCLE) |
4309                     (1ull << MSR_SPE) |
4310                     (1ull << MSR_POW) |
4311                     (1ull << MSR_CE) |
4312                     (1ull << MSR_EE) |
4313                     (1ull << MSR_PR) |
4314                     (1ull << MSR_FP) |
4315                     (1ull << MSR_ME) |
4316                     (1ull << MSR_FE0) |
4317                     (1ull << MSR_DWE) |
4318                     (1ull << MSR_DE) |
4319                     (1ull << MSR_FE1) |
4320                     (1ull << MSR_IR) |
4321                     (1ull << MSR_DR);
4322     pcc->mmu_model = POWERPC_MMU_BOOKE206;
4323     pcc->excp_model = POWERPC_EXCP_BOOKE;
4324     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4325     pcc->bfd_mach = bfd_mach_ppc_860;
4326     pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4327                  POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4328                  POWERPC_FLAG_BUS_CLK;
4329 }
4330 
4331 static void init_proc_e500v2(CPUPPCState *env)
4332 {
4333     init_proc_e500(env, fsl_e500v2);
4334 }
4335 
4336 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4337 {
4338     DeviceClass *dc = DEVICE_CLASS(oc);
4339     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4340 
4341     dc->desc = "e500v2 core";
4342     pcc->init_proc = init_proc_e500v2;
4343     pcc->check_pow = check_pow_hid0;
4344     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4345                        PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4346                        PPC_WRTEE | PPC_RFDI |
4347                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4348                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4349                        PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4350     pcc->insns_flags2 = PPC2_BOOKE206;
4351     pcc->msr_mask = (1ull << MSR_UCLE) |
4352                     (1ull << MSR_SPE) |
4353                     (1ull << MSR_POW) |
4354                     (1ull << MSR_CE) |
4355                     (1ull << MSR_EE) |
4356                     (1ull << MSR_PR) |
4357                     (1ull << MSR_FP) |
4358                     (1ull << MSR_ME) |
4359                     (1ull << MSR_FE0) |
4360                     (1ull << MSR_DWE) |
4361                     (1ull << MSR_DE) |
4362                     (1ull << MSR_FE1) |
4363                     (1ull << MSR_IR) |
4364                     (1ull << MSR_DR);
4365     pcc->mmu_model = POWERPC_MMU_BOOKE206;
4366     pcc->excp_model = POWERPC_EXCP_BOOKE;
4367     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4368     pcc->bfd_mach = bfd_mach_ppc_860;
4369     pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4370                  POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4371                  POWERPC_FLAG_BUS_CLK;
4372 }
4373 
4374 static void init_proc_e500mc(CPUPPCState *env)
4375 {
4376     init_proc_e500(env, fsl_e500mc);
4377 }
4378 
4379 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4380 {
4381     DeviceClass *dc = DEVICE_CLASS(oc);
4382     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4383 
4384     dc->desc = "e500mc core";
4385     pcc->init_proc = init_proc_e500mc;
4386     pcc->check_pow = check_pow_none;
4387     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4388                        PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4389                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4390                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4391                        PPC_FLOAT | PPC_FLOAT_FRES |
4392                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4393                        PPC_FLOAT_STFIWX | PPC_WAIT |
4394                        PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4395     pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4396     pcc->msr_mask = (1ull << MSR_GS) |
4397                     (1ull << MSR_UCLE) |
4398                     (1ull << MSR_CE) |
4399                     (1ull << MSR_EE) |
4400                     (1ull << MSR_PR) |
4401                     (1ull << MSR_FP) |
4402                     (1ull << MSR_ME) |
4403                     (1ull << MSR_FE0) |
4404                     (1ull << MSR_DE) |
4405                     (1ull << MSR_FE1) |
4406                     (1ull << MSR_IR) |
4407                     (1ull << MSR_DR) |
4408                     (1ull << MSR_PX) |
4409                     (1ull << MSR_RI);
4410     pcc->mmu_model = POWERPC_MMU_BOOKE206;
4411     pcc->excp_model = POWERPC_EXCP_BOOKE;
4412     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4413     /* FIXME: figure out the correct flag for e500mc */
4414     pcc->bfd_mach = bfd_mach_ppc_e500;
4415     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4416                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4417 }
4418 
4419 #ifdef TARGET_PPC64
4420 static void init_proc_e5500(CPUPPCState *env)
4421 {
4422     init_proc_e500(env, fsl_e5500);
4423 }
4424 
4425 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4426 {
4427     DeviceClass *dc = DEVICE_CLASS(oc);
4428     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4429 
4430     dc->desc = "e5500 core";
4431     pcc->init_proc = init_proc_e5500;
4432     pcc->check_pow = check_pow_none;
4433     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4434                        PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4435                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4436                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4437                        PPC_FLOAT | PPC_FLOAT_FRES |
4438                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4439                        PPC_FLOAT_STFIWX | PPC_WAIT |
4440                        PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4441                        PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4442     pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4443                         PPC2_FP_CVT_S64;
4444     pcc->msr_mask = (1ull << MSR_CM) |
4445                     (1ull << MSR_GS) |
4446                     (1ull << MSR_UCLE) |
4447                     (1ull << MSR_CE) |
4448                     (1ull << MSR_EE) |
4449                     (1ull << MSR_PR) |
4450                     (1ull << MSR_FP) |
4451                     (1ull << MSR_ME) |
4452                     (1ull << MSR_FE0) |
4453                     (1ull << MSR_DE) |
4454                     (1ull << MSR_FE1) |
4455                     (1ull << MSR_IR) |
4456                     (1ull << MSR_DR) |
4457                     (1ull << MSR_PX) |
4458                     (1ull << MSR_RI);
4459     pcc->mmu_model = POWERPC_MMU_BOOKE206;
4460     pcc->excp_model = POWERPC_EXCP_BOOKE;
4461     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4462     /* FIXME: figure out the correct flag for e5500 */
4463     pcc->bfd_mach = bfd_mach_ppc_e500;
4464     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4465                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4466 }
4467 
4468 static void init_proc_e6500(CPUPPCState *env)
4469 {
4470     init_proc_e500(env, fsl_e6500);
4471 }
4472 
4473 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
4474 {
4475     DeviceClass *dc = DEVICE_CLASS(oc);
4476     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4477 
4478     dc->desc = "e6500 core";
4479     pcc->init_proc = init_proc_e6500;
4480     pcc->check_pow = check_pow_none;
4481     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
4482                        PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4483                        PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4484                        PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4485                        PPC_FLOAT | PPC_FLOAT_FRES |
4486                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4487                        PPC_FLOAT_STFIWX | PPC_WAIT |
4488                        PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4489                        PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
4490     pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4491                         PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
4492     pcc->msr_mask = (1ull << MSR_CM) |
4493                     (1ull << MSR_GS) |
4494                     (1ull << MSR_UCLE) |
4495                     (1ull << MSR_CE) |
4496                     (1ull << MSR_EE) |
4497                     (1ull << MSR_PR) |
4498                     (1ull << MSR_FP) |
4499                     (1ull << MSR_ME) |
4500                     (1ull << MSR_FE0) |
4501                     (1ull << MSR_DE) |
4502                     (1ull << MSR_FE1) |
4503                     (1ull << MSR_IS) |
4504                     (1ull << MSR_DS) |
4505                     (1ull << MSR_PX) |
4506                     (1ull << MSR_RI) |
4507                     (1ull << MSR_VR);
4508     pcc->mmu_model = POWERPC_MMU_BOOKE206;
4509     pcc->excp_model = POWERPC_EXCP_BOOKE;
4510     pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4511     pcc->bfd_mach = bfd_mach_ppc_e500;
4512     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4513                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
4514 }
4515 
4516 #endif
4517 
4518 /* Non-embedded PowerPC                                                      */
4519 
4520 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4521 
4522 static void init_proc_601(CPUPPCState *env)
4523 {
4524     register_ne_601_sprs(env);
4525     register_sdr1_sprs(env);
4526     register_601_sprs(env);
4527     /* Hardware implementation registers */
4528     /* XXX : not implemented */
4529     spr_register(env, SPR_HID0, "HID0",
4530                  SPR_NOACCESS, SPR_NOACCESS,
4531                  &spr_read_generic, &spr_write_hid0_601,
4532                  0x80010080);
4533     /* XXX : not implemented */
4534     spr_register(env, SPR_HID1, "HID1",
4535                  SPR_NOACCESS, SPR_NOACCESS,
4536                  &spr_read_generic, &spr_write_generic,
4537                  0x00000000);
4538     /* XXX : not implemented */
4539     spr_register(env, SPR_601_HID2, "HID2",
4540                  SPR_NOACCESS, SPR_NOACCESS,
4541                  &spr_read_generic, &spr_write_generic,
4542                  0x00000000);
4543     /* XXX : not implemented */
4544     spr_register(env, SPR_601_HID5, "HID5",
4545                  SPR_NOACCESS, SPR_NOACCESS,
4546                  &spr_read_generic, &spr_write_generic,
4547                  0x00000000);
4548     /* Memory management */
4549     init_excp_601(env);
4550     /*
4551      * XXX: beware that dcache line size is 64
4552      *      but dcbz uses 32 bytes "sectors"
4553      * XXX: this breaks clcs instruction !
4554      */
4555     env->dcache_line_size = 32;
4556     env->icache_line_size = 64;
4557     /* Allocate hardware IRQ controller */
4558     ppc6xx_irq_init(env_archcpu(env));
4559 }
4560 
4561 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4562 {
4563     DeviceClass *dc = DEVICE_CLASS(oc);
4564     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4565 
4566     dc->desc = "PowerPC 601";
4567     pcc->init_proc = init_proc_601;
4568     pcc->check_pow = check_pow_none;
4569     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4570                        PPC_FLOAT |
4571                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4572                        PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4573                        PPC_SEGMENT | PPC_EXTERN;
4574     pcc->msr_mask = (1ull << MSR_EE) |
4575                     (1ull << MSR_PR) |
4576                     (1ull << MSR_FP) |
4577                     (1ull << MSR_ME) |
4578                     (1ull << MSR_FE0) |
4579                     (1ull << MSR_SE) |
4580                     (1ull << MSR_FE1) |
4581                     (1ull << MSR_EP) |
4582                     (1ull << MSR_IR) |
4583                     (1ull << MSR_DR);
4584     pcc->mmu_model = POWERPC_MMU_601;
4585 #if defined(CONFIG_SOFTMMU)
4586     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4587 #endif
4588     pcc->excp_model = POWERPC_EXCP_601;
4589     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4590     pcc->bfd_mach = bfd_mach_ppc_601;
4591     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4592 }
4593 
4594 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4595 
4596 static void init_proc_601v(CPUPPCState *env)
4597 {
4598     init_proc_601(env);
4599     /* XXX : not implemented */
4600     spr_register(env, SPR_601_HID15, "HID15",
4601                  SPR_NOACCESS, SPR_NOACCESS,
4602                  &spr_read_generic, &spr_write_generic,
4603                  0x00000000);
4604 }
4605 
4606 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4607 {
4608     DeviceClass *dc = DEVICE_CLASS(oc);
4609     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4610 
4611     dc->desc = "PowerPC 601v";
4612     pcc->init_proc = init_proc_601v;
4613     pcc->check_pow = check_pow_none;
4614     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4615                        PPC_FLOAT |
4616                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4617                        PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4618                        PPC_SEGMENT | PPC_EXTERN;
4619     pcc->msr_mask = (1ull << MSR_EE) |
4620                     (1ull << MSR_PR) |
4621                     (1ull << MSR_FP) |
4622                     (1ull << MSR_ME) |
4623                     (1ull << MSR_FE0) |
4624                     (1ull << MSR_SE) |
4625                     (1ull << MSR_FE1) |
4626                     (1ull << MSR_EP) |
4627                     (1ull << MSR_IR) |
4628                     (1ull << MSR_DR);
4629     pcc->mmu_model = POWERPC_MMU_601;
4630 #if defined(CONFIG_SOFTMMU)
4631     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4632 #endif
4633     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4634     pcc->bfd_mach = bfd_mach_ppc_601;
4635     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4636 }
4637 
4638 static void init_proc_602(CPUPPCState *env)
4639 {
4640     register_ne_601_sprs(env);
4641     register_sdr1_sprs(env);
4642     register_602_sprs(env);
4643     /* Time base */
4644     register_tbl(env);
4645     /* hardware implementation registers */
4646     /* XXX : not implemented */
4647     spr_register(env, SPR_HID0, "HID0",
4648                  SPR_NOACCESS, SPR_NOACCESS,
4649                  &spr_read_generic, &spr_write_generic,
4650                  0x00000000);
4651     /* XXX : not implemented */
4652     spr_register(env, SPR_HID1, "HID1",
4653                  SPR_NOACCESS, SPR_NOACCESS,
4654                  &spr_read_generic, &spr_write_generic,
4655                  0x00000000);
4656     /* Memory management */
4657     register_low_BATs(env);
4658     register_6xx_7xx_soft_tlb(env, 64, 2);
4659     init_excp_602(env);
4660     env->dcache_line_size = 32;
4661     env->icache_line_size = 32;
4662     /* Allocate hardware IRQ controller */
4663     ppc6xx_irq_init(env_archcpu(env));
4664 }
4665 
4666 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4667 {
4668     DeviceClass *dc = DEVICE_CLASS(oc);
4669     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4670 
4671     dc->desc = "PowerPC 602";
4672     pcc->init_proc = init_proc_602;
4673     pcc->check_pow = check_pow_hid0;
4674     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4675                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4676                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4677                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4678                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4679                        PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4680                        PPC_SEGMENT | PPC_602_SPEC;
4681     pcc->msr_mask = (1ull << MSR_VSX) |
4682                     (1ull << MSR_SA) |
4683                     (1ull << MSR_POW) |
4684                     (1ull << MSR_TGPR) |
4685                     (1ull << MSR_ILE) |
4686                     (1ull << MSR_EE) |
4687                     (1ull << MSR_PR) |
4688                     (1ull << MSR_FP) |
4689                     (1ull << MSR_ME) |
4690                     (1ull << MSR_FE0) |
4691                     (1ull << MSR_SE) |
4692                     (1ull << MSR_DE) |
4693                     (1ull << MSR_FE1) |
4694                     (1ull << MSR_EP) |
4695                     (1ull << MSR_IR) |
4696                     (1ull << MSR_DR) |
4697                     (1ull << MSR_RI) |
4698                     (1ull << MSR_LE);
4699     /* XXX: 602 MMU is quite specific. Should add a special case */
4700     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4701     pcc->excp_model = POWERPC_EXCP_602;
4702     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4703     pcc->bfd_mach = bfd_mach_ppc_602;
4704     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4705                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4706 }
4707 
4708 static void init_proc_603(CPUPPCState *env)
4709 {
4710     register_ne_601_sprs(env);
4711     register_sdr1_sprs(env);
4712     register_603_sprs(env);
4713     /* Time base */
4714     register_tbl(env);
4715     /* hardware implementation registers */
4716     /* XXX : not implemented */
4717     spr_register(env, SPR_HID0, "HID0",
4718                  SPR_NOACCESS, SPR_NOACCESS,
4719                  &spr_read_generic, &spr_write_generic,
4720                  0x00000000);
4721     /* XXX : not implemented */
4722     spr_register(env, SPR_HID1, "HID1",
4723                  SPR_NOACCESS, SPR_NOACCESS,
4724                  &spr_read_generic, &spr_write_generic,
4725                  0x00000000);
4726     /* Memory management */
4727     register_low_BATs(env);
4728     register_6xx_7xx_soft_tlb(env, 64, 2);
4729     init_excp_603(env);
4730     env->dcache_line_size = 32;
4731     env->icache_line_size = 32;
4732     /* Allocate hardware IRQ controller */
4733     ppc6xx_irq_init(env_archcpu(env));
4734 }
4735 
4736 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4737 {
4738     DeviceClass *dc = DEVICE_CLASS(oc);
4739     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4740 
4741     dc->desc = "PowerPC 603";
4742     pcc->init_proc = init_proc_603;
4743     pcc->check_pow = check_pow_hid0;
4744     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4745                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4746                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4747                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4748                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4749                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4750                        PPC_SEGMENT | PPC_EXTERN;
4751     pcc->msr_mask = (1ull << MSR_POW) |
4752                     (1ull << MSR_TGPR) |
4753                     (1ull << MSR_ILE) |
4754                     (1ull << MSR_EE) |
4755                     (1ull << MSR_PR) |
4756                     (1ull << MSR_FP) |
4757                     (1ull << MSR_ME) |
4758                     (1ull << MSR_FE0) |
4759                     (1ull << MSR_SE) |
4760                     (1ull << MSR_DE) |
4761                     (1ull << MSR_FE1) |
4762                     (1ull << MSR_EP) |
4763                     (1ull << MSR_IR) |
4764                     (1ull << MSR_DR) |
4765                     (1ull << MSR_RI) |
4766                     (1ull << MSR_LE);
4767     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4768     pcc->excp_model = POWERPC_EXCP_603;
4769     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4770     pcc->bfd_mach = bfd_mach_ppc_603;
4771     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4772                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4773 }
4774 
4775 static void init_proc_603E(CPUPPCState *env)
4776 {
4777     register_ne_601_sprs(env);
4778     register_sdr1_sprs(env);
4779     register_603_sprs(env);
4780     /* Time base */
4781     register_tbl(env);
4782     /* hardware implementation registers */
4783     /* XXX : not implemented */
4784     spr_register(env, SPR_HID0, "HID0",
4785                  SPR_NOACCESS, SPR_NOACCESS,
4786                  &spr_read_generic, &spr_write_generic,
4787                  0x00000000);
4788     /* XXX : not implemented */
4789     spr_register(env, SPR_HID1, "HID1",
4790                  SPR_NOACCESS, SPR_NOACCESS,
4791                  &spr_read_generic, &spr_write_generic,
4792                  0x00000000);
4793     /* Memory management */
4794     register_low_BATs(env);
4795     register_6xx_7xx_soft_tlb(env, 64, 2);
4796     init_excp_603(env);
4797     env->dcache_line_size = 32;
4798     env->icache_line_size = 32;
4799     /* Allocate hardware IRQ controller */
4800     ppc6xx_irq_init(env_archcpu(env));
4801 }
4802 
4803 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4804 {
4805     DeviceClass *dc = DEVICE_CLASS(oc);
4806     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4807 
4808     dc->desc = "PowerPC 603e";
4809     pcc->init_proc = init_proc_603E;
4810     pcc->check_pow = check_pow_hid0;
4811     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4812                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4813                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4814                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4815                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4816                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4817                        PPC_SEGMENT | PPC_EXTERN;
4818     pcc->msr_mask = (1ull << MSR_POW) |
4819                     (1ull << MSR_TGPR) |
4820                     (1ull << MSR_ILE) |
4821                     (1ull << MSR_EE) |
4822                     (1ull << MSR_PR) |
4823                     (1ull << MSR_FP) |
4824                     (1ull << MSR_ME) |
4825                     (1ull << MSR_FE0) |
4826                     (1ull << MSR_SE) |
4827                     (1ull << MSR_DE) |
4828                     (1ull << MSR_FE1) |
4829                     (1ull << MSR_EP) |
4830                     (1ull << MSR_IR) |
4831                     (1ull << MSR_DR) |
4832                     (1ull << MSR_RI) |
4833                     (1ull << MSR_LE);
4834     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4835     pcc->excp_model = POWERPC_EXCP_603E;
4836     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4837     pcc->bfd_mach = bfd_mach_ppc_ec603e;
4838     pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4839                  POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4840 }
4841 
4842 static void init_proc_604(CPUPPCState *env)
4843 {
4844     register_ne_601_sprs(env);
4845     register_sdr1_sprs(env);
4846     register_604_sprs(env);
4847     /* Time base */
4848     register_tbl(env);
4849     /* Hardware implementation registers */
4850     /* XXX : not implemented */
4851     spr_register(env, SPR_HID0, "HID0",
4852                  SPR_NOACCESS, SPR_NOACCESS,
4853                  &spr_read_generic, &spr_write_generic,
4854                  0x00000000);
4855     /* Memory management */
4856     register_low_BATs(env);
4857     init_excp_604(env);
4858     env->dcache_line_size = 32;
4859     env->icache_line_size = 32;
4860     /* Allocate hardware IRQ controller */
4861     ppc6xx_irq_init(env_archcpu(env));
4862 }
4863 
4864 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
4865 {
4866     DeviceClass *dc = DEVICE_CLASS(oc);
4867     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4868 
4869     dc->desc = "PowerPC 604";
4870     pcc->init_proc = init_proc_604;
4871     pcc->check_pow = check_pow_nocheck;
4872     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4873                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4874                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4875                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4876                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4877                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4878                        PPC_SEGMENT | PPC_EXTERN;
4879     pcc->msr_mask = (1ull << MSR_POW) |
4880                     (1ull << MSR_ILE) |
4881                     (1ull << MSR_EE) |
4882                     (1ull << MSR_PR) |
4883                     (1ull << MSR_FP) |
4884                     (1ull << MSR_ME) |
4885                     (1ull << MSR_FE0) |
4886                     (1ull << MSR_SE) |
4887                     (1ull << MSR_DE) |
4888                     (1ull << MSR_FE1) |
4889                     (1ull << MSR_EP) |
4890                     (1ull << MSR_IR) |
4891                     (1ull << MSR_DR) |
4892                     (1ull << MSR_PMM) |
4893                     (1ull << MSR_RI) |
4894                     (1ull << MSR_LE);
4895     pcc->mmu_model = POWERPC_MMU_32B;
4896 #if defined(CONFIG_SOFTMMU)
4897     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4898 #endif
4899     pcc->excp_model = POWERPC_EXCP_604;
4900     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4901     pcc->bfd_mach = bfd_mach_ppc_604;
4902     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4903                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4904 }
4905 
4906 static void init_proc_604E(CPUPPCState *env)
4907 {
4908     register_ne_601_sprs(env);
4909     register_sdr1_sprs(env);
4910     register_604_sprs(env);
4911     /* XXX : not implemented */
4912     spr_register(env, SPR_7XX_MMCR1, "MMCR1",
4913                  SPR_NOACCESS, SPR_NOACCESS,
4914                  &spr_read_generic, &spr_write_generic,
4915                  0x00000000);
4916     /* XXX : not implemented */
4917     spr_register(env, SPR_7XX_PMC3, "PMC3",
4918                  SPR_NOACCESS, SPR_NOACCESS,
4919                  &spr_read_generic, &spr_write_generic,
4920                  0x00000000);
4921     /* XXX : not implemented */
4922     spr_register(env, SPR_7XX_PMC4, "PMC4",
4923                  SPR_NOACCESS, SPR_NOACCESS,
4924                  &spr_read_generic, &spr_write_generic,
4925                  0x00000000);
4926     /* Time base */
4927     register_tbl(env);
4928     /* Hardware implementation registers */
4929     /* XXX : not implemented */
4930     spr_register(env, SPR_HID0, "HID0",
4931                  SPR_NOACCESS, SPR_NOACCESS,
4932                  &spr_read_generic, &spr_write_generic,
4933                  0x00000000);
4934     /* XXX : not implemented */
4935     spr_register(env, SPR_HID1, "HID1",
4936                  SPR_NOACCESS, SPR_NOACCESS,
4937                  &spr_read_generic, &spr_write_generic,
4938                  0x00000000);
4939     /* Memory management */
4940     register_low_BATs(env);
4941     init_excp_604(env);
4942     env->dcache_line_size = 32;
4943     env->icache_line_size = 32;
4944     /* Allocate hardware IRQ controller */
4945     ppc6xx_irq_init(env_archcpu(env));
4946 }
4947 
4948 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
4949 {
4950     DeviceClass *dc = DEVICE_CLASS(oc);
4951     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4952 
4953     dc->desc = "PowerPC 604E";
4954     pcc->init_proc = init_proc_604E;
4955     pcc->check_pow = check_pow_nocheck;
4956     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4957                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4958                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4959                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4960                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
4961                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4962                        PPC_SEGMENT | PPC_EXTERN;
4963     pcc->msr_mask = (1ull << MSR_POW) |
4964                     (1ull << MSR_ILE) |
4965                     (1ull << MSR_EE) |
4966                     (1ull << MSR_PR) |
4967                     (1ull << MSR_FP) |
4968                     (1ull << MSR_ME) |
4969                     (1ull << MSR_FE0) |
4970                     (1ull << MSR_SE) |
4971                     (1ull << MSR_DE) |
4972                     (1ull << MSR_FE1) |
4973                     (1ull << MSR_EP) |
4974                     (1ull << MSR_IR) |
4975                     (1ull << MSR_DR) |
4976                     (1ull << MSR_PMM) |
4977                     (1ull << MSR_RI) |
4978                     (1ull << MSR_LE);
4979     pcc->mmu_model = POWERPC_MMU_32B;
4980 #if defined(CONFIG_SOFTMMU)
4981     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4982 #endif
4983     pcc->excp_model = POWERPC_EXCP_604;
4984     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4985     pcc->bfd_mach = bfd_mach_ppc_604;
4986     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4987                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4988 }
4989 
4990 static void init_proc_740(CPUPPCState *env)
4991 {
4992     register_ne_601_sprs(env);
4993     register_sdr1_sprs(env);
4994     register_7xx_sprs(env);
4995     /* Time base */
4996     register_tbl(env);
4997     /* Thermal management */
4998     register_thrm_sprs(env);
4999     /* Hardware implementation registers */
5000     /* XXX : not implemented */
5001     spr_register(env, SPR_HID0, "HID0",
5002                  SPR_NOACCESS, SPR_NOACCESS,
5003                  &spr_read_generic, &spr_write_generic,
5004                  0x00000000);
5005     /* XXX : not implemented */
5006     spr_register(env, SPR_HID1, "HID1",
5007                  SPR_NOACCESS, SPR_NOACCESS,
5008                  &spr_read_generic, &spr_write_generic,
5009                  0x00000000);
5010     /* Memory management */
5011     register_low_BATs(env);
5012     init_excp_7x0(env);
5013     env->dcache_line_size = 32;
5014     env->icache_line_size = 32;
5015     /* Allocate hardware IRQ controller */
5016     ppc6xx_irq_init(env_archcpu(env));
5017 }
5018 
5019 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5020 {
5021     DeviceClass *dc = DEVICE_CLASS(oc);
5022     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5023 
5024     dc->desc = "PowerPC 740";
5025     pcc->init_proc = init_proc_740;
5026     pcc->check_pow = check_pow_hid0;
5027     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5028                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5029                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5030                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5031                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5032                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5033                        PPC_SEGMENT | PPC_EXTERN;
5034     pcc->msr_mask = (1ull << MSR_POW) |
5035                     (1ull << MSR_ILE) |
5036                     (1ull << MSR_EE) |
5037                     (1ull << MSR_PR) |
5038                     (1ull << MSR_FP) |
5039                     (1ull << MSR_ME) |
5040                     (1ull << MSR_FE0) |
5041                     (1ull << MSR_SE) |
5042                     (1ull << MSR_DE) |
5043                     (1ull << MSR_FE1) |
5044                     (1ull << MSR_EP) |
5045                     (1ull << MSR_IR) |
5046                     (1ull << MSR_DR) |
5047                     (1ull << MSR_PMM) |
5048                     (1ull << MSR_RI) |
5049                     (1ull << MSR_LE);
5050     pcc->mmu_model = POWERPC_MMU_32B;
5051 #if defined(CONFIG_SOFTMMU)
5052     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5053 #endif
5054     pcc->excp_model = POWERPC_EXCP_7x0;
5055     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5056     pcc->bfd_mach = bfd_mach_ppc_750;
5057     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5058                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5059 }
5060 
5061 static void init_proc_750(CPUPPCState *env)
5062 {
5063     register_ne_601_sprs(env);
5064     register_sdr1_sprs(env);
5065     register_7xx_sprs(env);
5066     /* XXX : not implemented */
5067     spr_register(env, SPR_L2CR, "L2CR",
5068                  SPR_NOACCESS, SPR_NOACCESS,
5069                  &spr_read_generic, spr_access_nop,
5070                  0x00000000);
5071     /* Time base */
5072     register_tbl(env);
5073     /* Thermal management */
5074     register_thrm_sprs(env);
5075     /* Hardware implementation registers */
5076     /* XXX : not implemented */
5077     spr_register(env, SPR_HID0, "HID0",
5078                  SPR_NOACCESS, SPR_NOACCESS,
5079                  &spr_read_generic, &spr_write_generic,
5080                  0x00000000);
5081     /* XXX : not implemented */
5082     spr_register(env, SPR_HID1, "HID1",
5083                  SPR_NOACCESS, SPR_NOACCESS,
5084                  &spr_read_generic, &spr_write_generic,
5085                  0x00000000);
5086     /* Memory management */
5087     register_low_BATs(env);
5088     /*
5089      * XXX: high BATs are also present but are known to be bugged on
5090      *      die version 1.x
5091      */
5092     init_excp_7x0(env);
5093     env->dcache_line_size = 32;
5094     env->icache_line_size = 32;
5095     /* Allocate hardware IRQ controller */
5096     ppc6xx_irq_init(env_archcpu(env));
5097 }
5098 
5099 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5100 {
5101     DeviceClass *dc = DEVICE_CLASS(oc);
5102     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5103 
5104     dc->desc = "PowerPC 750";
5105     pcc->init_proc = init_proc_750;
5106     pcc->check_pow = check_pow_hid0;
5107     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5108                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5109                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5110                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5111                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5112                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5113                        PPC_SEGMENT | PPC_EXTERN;
5114     pcc->msr_mask = (1ull << MSR_POW) |
5115                     (1ull << MSR_ILE) |
5116                     (1ull << MSR_EE) |
5117                     (1ull << MSR_PR) |
5118                     (1ull << MSR_FP) |
5119                     (1ull << MSR_ME) |
5120                     (1ull << MSR_FE0) |
5121                     (1ull << MSR_SE) |
5122                     (1ull << MSR_DE) |
5123                     (1ull << MSR_FE1) |
5124                     (1ull << MSR_EP) |
5125                     (1ull << MSR_IR) |
5126                     (1ull << MSR_DR) |
5127                     (1ull << MSR_PMM) |
5128                     (1ull << MSR_RI) |
5129                     (1ull << MSR_LE);
5130     pcc->mmu_model = POWERPC_MMU_32B;
5131 #if defined(CONFIG_SOFTMMU)
5132     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5133 #endif
5134     pcc->excp_model = POWERPC_EXCP_7x0;
5135     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5136     pcc->bfd_mach = bfd_mach_ppc_750;
5137     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5138                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5139 }
5140 
5141 static void init_proc_750cl(CPUPPCState *env)
5142 {
5143     register_ne_601_sprs(env);
5144     register_sdr1_sprs(env);
5145     register_7xx_sprs(env);
5146     /* XXX : not implemented */
5147     spr_register(env, SPR_L2CR, "L2CR",
5148                  SPR_NOACCESS, SPR_NOACCESS,
5149                  &spr_read_generic, spr_access_nop,
5150                  0x00000000);
5151     /* Time base */
5152     register_tbl(env);
5153     /* Thermal management */
5154     /* Those registers are fake on 750CL */
5155     spr_register(env, SPR_THRM1, "THRM1",
5156                  SPR_NOACCESS, SPR_NOACCESS,
5157                  &spr_read_generic, &spr_write_generic,
5158                  0x00000000);
5159     spr_register(env, SPR_THRM2, "THRM2",
5160                  SPR_NOACCESS, SPR_NOACCESS,
5161                  &spr_read_generic, &spr_write_generic,
5162                  0x00000000);
5163     spr_register(env, SPR_THRM3, "THRM3",
5164                  SPR_NOACCESS, SPR_NOACCESS,
5165                  &spr_read_generic, &spr_write_generic,
5166                  0x00000000);
5167     /* XXX: not implemented */
5168     spr_register(env, SPR_750_TDCL, "TDCL",
5169                  SPR_NOACCESS, SPR_NOACCESS,
5170                  &spr_read_generic, &spr_write_generic,
5171                  0x00000000);
5172     spr_register(env, SPR_750_TDCH, "TDCH",
5173                  SPR_NOACCESS, SPR_NOACCESS,
5174                  &spr_read_generic, &spr_write_generic,
5175                  0x00000000);
5176     /* DMA */
5177     /* XXX : not implemented */
5178     spr_register(env, SPR_750_WPAR, "WPAR",
5179                  SPR_NOACCESS, SPR_NOACCESS,
5180                  &spr_read_generic, &spr_write_generic,
5181                  0x00000000);
5182     spr_register(env, SPR_750_DMAL, "DMAL",
5183                  SPR_NOACCESS, SPR_NOACCESS,
5184                  &spr_read_generic, &spr_write_generic,
5185                  0x00000000);
5186     spr_register(env, SPR_750_DMAU, "DMAU",
5187                  SPR_NOACCESS, SPR_NOACCESS,
5188                  &spr_read_generic, &spr_write_generic,
5189                  0x00000000);
5190     /* Hardware implementation registers */
5191     /* XXX : not implemented */
5192     spr_register(env, SPR_HID0, "HID0",
5193                  SPR_NOACCESS, SPR_NOACCESS,
5194                  &spr_read_generic, &spr_write_generic,
5195                  0x00000000);
5196     /* XXX : not implemented */
5197     spr_register(env, SPR_HID1, "HID1",
5198                  SPR_NOACCESS, SPR_NOACCESS,
5199                  &spr_read_generic, &spr_write_generic,
5200                  0x00000000);
5201     /* XXX : not implemented */
5202     spr_register(env, SPR_750CL_HID2, "HID2",
5203                  SPR_NOACCESS, SPR_NOACCESS,
5204                  &spr_read_generic, &spr_write_generic,
5205                  0x00000000);
5206     /* XXX : not implemented */
5207     spr_register(env, SPR_750CL_HID4, "HID4",
5208                  SPR_NOACCESS, SPR_NOACCESS,
5209                  &spr_read_generic, &spr_write_generic,
5210                  0x00000000);
5211     /* Quantization registers */
5212     /* XXX : not implemented */
5213     spr_register(env, SPR_750_GQR0, "GQR0",
5214                  SPR_NOACCESS, SPR_NOACCESS,
5215                  &spr_read_generic, &spr_write_generic,
5216                  0x00000000);
5217     /* XXX : not implemented */
5218     spr_register(env, SPR_750_GQR1, "GQR1",
5219                  SPR_NOACCESS, SPR_NOACCESS,
5220                  &spr_read_generic, &spr_write_generic,
5221                  0x00000000);
5222     /* XXX : not implemented */
5223     spr_register(env, SPR_750_GQR2, "GQR2",
5224                  SPR_NOACCESS, SPR_NOACCESS,
5225                  &spr_read_generic, &spr_write_generic,
5226                  0x00000000);
5227     /* XXX : not implemented */
5228     spr_register(env, SPR_750_GQR3, "GQR3",
5229                  SPR_NOACCESS, SPR_NOACCESS,
5230                  &spr_read_generic, &spr_write_generic,
5231                  0x00000000);
5232     /* XXX : not implemented */
5233     spr_register(env, SPR_750_GQR4, "GQR4",
5234                  SPR_NOACCESS, SPR_NOACCESS,
5235                  &spr_read_generic, &spr_write_generic,
5236                  0x00000000);
5237     /* XXX : not implemented */
5238     spr_register(env, SPR_750_GQR5, "GQR5",
5239                  SPR_NOACCESS, SPR_NOACCESS,
5240                  &spr_read_generic, &spr_write_generic,
5241                  0x00000000);
5242     /* XXX : not implemented */
5243     spr_register(env, SPR_750_GQR6, "GQR6",
5244                  SPR_NOACCESS, SPR_NOACCESS,
5245                  &spr_read_generic, &spr_write_generic,
5246                  0x00000000);
5247     /* XXX : not implemented */
5248     spr_register(env, SPR_750_GQR7, "GQR7",
5249                  SPR_NOACCESS, SPR_NOACCESS,
5250                  &spr_read_generic, &spr_write_generic,
5251                  0x00000000);
5252     /* Memory management */
5253     register_low_BATs(env);
5254     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5255     register_high_BATs(env);
5256     init_excp_750cl(env);
5257     env->dcache_line_size = 32;
5258     env->icache_line_size = 32;
5259     /* Allocate hardware IRQ controller */
5260     ppc6xx_irq_init(env_archcpu(env));
5261 }
5262 
5263 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5264 {
5265     DeviceClass *dc = DEVICE_CLASS(oc);
5266     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5267 
5268     dc->desc = "PowerPC 750 CL";
5269     pcc->init_proc = init_proc_750cl;
5270     pcc->check_pow = check_pow_hid0;
5271     /*
5272      * XXX: not implemented:
5273      * cache lock instructions:
5274      * dcbz_l
5275      * floating point paired instructions
5276      * psq_lux
5277      * psq_lx
5278      * psq_stux
5279      * psq_stx
5280      * ps_abs
5281      * ps_add
5282      * ps_cmpo0
5283      * ps_cmpo1
5284      * ps_cmpu0
5285      * ps_cmpu1
5286      * ps_div
5287      * ps_madd
5288      * ps_madds0
5289      * ps_madds1
5290      * ps_merge00
5291      * ps_merge01
5292      * ps_merge10
5293      * ps_merge11
5294      * ps_mr
5295      * ps_msub
5296      * ps_mul
5297      * ps_muls0
5298      * ps_muls1
5299      * ps_nabs
5300      * ps_neg
5301      * ps_nmadd
5302      * ps_nmsub
5303      * ps_res
5304      * ps_rsqrte
5305      * ps_sel
5306      * ps_sub
5307      * ps_sum0
5308      * ps_sum1
5309      */
5310     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5311                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5312                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5313                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5314                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5315                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5316                        PPC_SEGMENT | PPC_EXTERN;
5317     pcc->msr_mask = (1ull << MSR_POW) |
5318                     (1ull << MSR_ILE) |
5319                     (1ull << MSR_EE) |
5320                     (1ull << MSR_PR) |
5321                     (1ull << MSR_FP) |
5322                     (1ull << MSR_ME) |
5323                     (1ull << MSR_FE0) |
5324                     (1ull << MSR_SE) |
5325                     (1ull << MSR_DE) |
5326                     (1ull << MSR_FE1) |
5327                     (1ull << MSR_EP) |
5328                     (1ull << MSR_IR) |
5329                     (1ull << MSR_DR) |
5330                     (1ull << MSR_PMM) |
5331                     (1ull << MSR_RI) |
5332                     (1ull << MSR_LE);
5333     pcc->mmu_model = POWERPC_MMU_32B;
5334 #if defined(CONFIG_SOFTMMU)
5335     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5336 #endif
5337     pcc->excp_model = POWERPC_EXCP_7x0;
5338     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5339     pcc->bfd_mach = bfd_mach_ppc_750;
5340     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5341                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5342 }
5343 
5344 static void init_proc_750cx(CPUPPCState *env)
5345 {
5346     register_ne_601_sprs(env);
5347     register_sdr1_sprs(env);
5348     register_7xx_sprs(env);
5349     /* XXX : not implemented */
5350     spr_register(env, SPR_L2CR, "L2CR",
5351                  SPR_NOACCESS, SPR_NOACCESS,
5352                  &spr_read_generic, spr_access_nop,
5353                  0x00000000);
5354     /* Time base */
5355     register_tbl(env);
5356     /* Thermal management */
5357     register_thrm_sprs(env);
5358     /* This register is not implemented but is present for compatibility */
5359     spr_register(env, SPR_SDA, "SDA",
5360                  SPR_NOACCESS, SPR_NOACCESS,
5361                  &spr_read_generic, &spr_write_generic,
5362                  0x00000000);
5363     /* Hardware implementation registers */
5364     /* XXX : not implemented */
5365     spr_register(env, SPR_HID0, "HID0",
5366                  SPR_NOACCESS, SPR_NOACCESS,
5367                  &spr_read_generic, &spr_write_generic,
5368                  0x00000000);
5369     /* XXX : not implemented */
5370     spr_register(env, SPR_HID1, "HID1",
5371                  SPR_NOACCESS, SPR_NOACCESS,
5372                  &spr_read_generic, &spr_write_generic,
5373                  0x00000000);
5374     /* Memory management */
5375     register_low_BATs(env);
5376     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5377     register_high_BATs(env);
5378     init_excp_750cx(env);
5379     env->dcache_line_size = 32;
5380     env->icache_line_size = 32;
5381     /* Allocate hardware IRQ controller */
5382     ppc6xx_irq_init(env_archcpu(env));
5383 }
5384 
5385 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5386 {
5387     DeviceClass *dc = DEVICE_CLASS(oc);
5388     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5389 
5390     dc->desc = "PowerPC 750CX";
5391     pcc->init_proc = init_proc_750cx;
5392     pcc->check_pow = check_pow_hid0;
5393     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5394                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5395                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5396                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5397                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5398                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5399                        PPC_SEGMENT | PPC_EXTERN;
5400     pcc->msr_mask = (1ull << MSR_POW) |
5401                     (1ull << MSR_ILE) |
5402                     (1ull << MSR_EE) |
5403                     (1ull << MSR_PR) |
5404                     (1ull << MSR_FP) |
5405                     (1ull << MSR_ME) |
5406                     (1ull << MSR_FE0) |
5407                     (1ull << MSR_SE) |
5408                     (1ull << MSR_DE) |
5409                     (1ull << MSR_FE1) |
5410                     (1ull << MSR_EP) |
5411                     (1ull << MSR_IR) |
5412                     (1ull << MSR_DR) |
5413                     (1ull << MSR_PMM) |
5414                     (1ull << MSR_RI) |
5415                     (1ull << MSR_LE);
5416     pcc->mmu_model = POWERPC_MMU_32B;
5417 #if defined(CONFIG_SOFTMMU)
5418     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5419 #endif
5420     pcc->excp_model = POWERPC_EXCP_7x0;
5421     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5422     pcc->bfd_mach = bfd_mach_ppc_750;
5423     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5424                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5425 }
5426 
5427 static void init_proc_750fx(CPUPPCState *env)
5428 {
5429     register_ne_601_sprs(env);
5430     register_sdr1_sprs(env);
5431     register_7xx_sprs(env);
5432     /* XXX : not implemented */
5433     spr_register(env, SPR_L2CR, "L2CR",
5434                  SPR_NOACCESS, SPR_NOACCESS,
5435                  &spr_read_generic, spr_access_nop,
5436                  0x00000000);
5437     /* Time base */
5438     register_tbl(env);
5439     /* Thermal management */
5440     register_thrm_sprs(env);
5441     /* XXX : not implemented */
5442     spr_register(env, SPR_750_THRM4, "THRM4",
5443                  SPR_NOACCESS, SPR_NOACCESS,
5444                  &spr_read_generic, &spr_write_generic,
5445                  0x00000000);
5446     /* Hardware implementation registers */
5447     /* XXX : not implemented */
5448     spr_register(env, SPR_HID0, "HID0",
5449                  SPR_NOACCESS, SPR_NOACCESS,
5450                  &spr_read_generic, &spr_write_generic,
5451                  0x00000000);
5452     /* XXX : not implemented */
5453     spr_register(env, SPR_HID1, "HID1",
5454                  SPR_NOACCESS, SPR_NOACCESS,
5455                  &spr_read_generic, &spr_write_generic,
5456                  0x00000000);
5457     /* XXX : not implemented */
5458     spr_register(env, SPR_750FX_HID2, "HID2",
5459                  SPR_NOACCESS, SPR_NOACCESS,
5460                  &spr_read_generic, &spr_write_generic,
5461                  0x00000000);
5462     /* Memory management */
5463     register_low_BATs(env);
5464     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5465     register_high_BATs(env);
5466     init_excp_7x0(env);
5467     env->dcache_line_size = 32;
5468     env->icache_line_size = 32;
5469     /* Allocate hardware IRQ controller */
5470     ppc6xx_irq_init(env_archcpu(env));
5471 }
5472 
5473 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5474 {
5475     DeviceClass *dc = DEVICE_CLASS(oc);
5476     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5477 
5478     dc->desc = "PowerPC 750FX";
5479     pcc->init_proc = init_proc_750fx;
5480     pcc->check_pow = check_pow_hid0;
5481     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5482                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5483                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5484                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5485                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5486                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5487                        PPC_SEGMENT | PPC_EXTERN;
5488     pcc->msr_mask = (1ull << MSR_POW) |
5489                     (1ull << MSR_ILE) |
5490                     (1ull << MSR_EE) |
5491                     (1ull << MSR_PR) |
5492                     (1ull << MSR_FP) |
5493                     (1ull << MSR_ME) |
5494                     (1ull << MSR_FE0) |
5495                     (1ull << MSR_SE) |
5496                     (1ull << MSR_DE) |
5497                     (1ull << MSR_FE1) |
5498                     (1ull << MSR_EP) |
5499                     (1ull << MSR_IR) |
5500                     (1ull << MSR_DR) |
5501                     (1ull << MSR_PMM) |
5502                     (1ull << MSR_RI) |
5503                     (1ull << MSR_LE);
5504     pcc->mmu_model = POWERPC_MMU_32B;
5505 #if defined(CONFIG_SOFTMMU)
5506     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5507 #endif
5508     pcc->excp_model = POWERPC_EXCP_7x0;
5509     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5510     pcc->bfd_mach = bfd_mach_ppc_750;
5511     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5512                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5513 }
5514 
5515 static void init_proc_750gx(CPUPPCState *env)
5516 {
5517     register_ne_601_sprs(env);
5518     register_sdr1_sprs(env);
5519     register_7xx_sprs(env);
5520     /* XXX : not implemented (XXX: different from 750fx) */
5521     spr_register(env, SPR_L2CR, "L2CR",
5522                  SPR_NOACCESS, SPR_NOACCESS,
5523                  &spr_read_generic, spr_access_nop,
5524                  0x00000000);
5525     /* Time base */
5526     register_tbl(env);
5527     /* Thermal management */
5528     register_thrm_sprs(env);
5529     /* XXX : not implemented */
5530     spr_register(env, SPR_750_THRM4, "THRM4",
5531                  SPR_NOACCESS, SPR_NOACCESS,
5532                  &spr_read_generic, &spr_write_generic,
5533                  0x00000000);
5534     /* Hardware implementation registers */
5535     /* XXX : not implemented (XXX: different from 750fx) */
5536     spr_register(env, SPR_HID0, "HID0",
5537                  SPR_NOACCESS, SPR_NOACCESS,
5538                  &spr_read_generic, &spr_write_generic,
5539                  0x00000000);
5540     /* XXX : not implemented */
5541     spr_register(env, SPR_HID1, "HID1",
5542                  SPR_NOACCESS, SPR_NOACCESS,
5543                  &spr_read_generic, &spr_write_generic,
5544                  0x00000000);
5545     /* XXX : not implemented (XXX: different from 750fx) */
5546     spr_register(env, SPR_750FX_HID2, "HID2",
5547                  SPR_NOACCESS, SPR_NOACCESS,
5548                  &spr_read_generic, &spr_write_generic,
5549                  0x00000000);
5550     /* Memory management */
5551     register_low_BATs(env);
5552     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5553     register_high_BATs(env);
5554     init_excp_7x0(env);
5555     env->dcache_line_size = 32;
5556     env->icache_line_size = 32;
5557     /* Allocate hardware IRQ controller */
5558     ppc6xx_irq_init(env_archcpu(env));
5559 }
5560 
5561 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5562 {
5563     DeviceClass *dc = DEVICE_CLASS(oc);
5564     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5565 
5566     dc->desc = "PowerPC 750GX";
5567     pcc->init_proc = init_proc_750gx;
5568     pcc->check_pow = check_pow_hid0;
5569     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5570                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5571                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5572                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5573                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5574                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5575                        PPC_SEGMENT | PPC_EXTERN;
5576     pcc->msr_mask = (1ull << MSR_POW) |
5577                     (1ull << MSR_ILE) |
5578                     (1ull << MSR_EE) |
5579                     (1ull << MSR_PR) |
5580                     (1ull << MSR_FP) |
5581                     (1ull << MSR_ME) |
5582                     (1ull << MSR_FE0) |
5583                     (1ull << MSR_SE) |
5584                     (1ull << MSR_DE) |
5585                     (1ull << MSR_FE1) |
5586                     (1ull << MSR_EP) |
5587                     (1ull << MSR_IR) |
5588                     (1ull << MSR_DR) |
5589                     (1ull << MSR_PMM) |
5590                     (1ull << MSR_RI) |
5591                     (1ull << MSR_LE);
5592     pcc->mmu_model = POWERPC_MMU_32B;
5593 #if defined(CONFIG_SOFTMMU)
5594     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5595 #endif
5596     pcc->excp_model = POWERPC_EXCP_7x0;
5597     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5598     pcc->bfd_mach = bfd_mach_ppc_750;
5599     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5600                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5601 }
5602 
5603 static void init_proc_745(CPUPPCState *env)
5604 {
5605     register_ne_601_sprs(env);
5606     register_sdr1_sprs(env);
5607     register_7xx_sprs(env);
5608     register_G2_755_sprs(env);
5609     /* Time base */
5610     register_tbl(env);
5611     /* Thermal management */
5612     register_thrm_sprs(env);
5613     /* Hardware implementation registers */
5614     /* XXX : not implemented */
5615     spr_register(env, SPR_HID0, "HID0",
5616                  SPR_NOACCESS, SPR_NOACCESS,
5617                  &spr_read_generic, &spr_write_generic,
5618                  0x00000000);
5619     /* XXX : not implemented */
5620     spr_register(env, SPR_HID1, "HID1",
5621                  SPR_NOACCESS, SPR_NOACCESS,
5622                  &spr_read_generic, &spr_write_generic,
5623                  0x00000000);
5624     /* XXX : not implemented */
5625     spr_register(env, SPR_HID2, "HID2",
5626                  SPR_NOACCESS, SPR_NOACCESS,
5627                  &spr_read_generic, &spr_write_generic,
5628                  0x00000000);
5629     /* Memory management */
5630     register_low_BATs(env);
5631     register_high_BATs(env);
5632     register_6xx_7xx_soft_tlb(env, 64, 2);
5633     init_excp_7x5(env);
5634     env->dcache_line_size = 32;
5635     env->icache_line_size = 32;
5636     /* Allocate hardware IRQ controller */
5637     ppc6xx_irq_init(env_archcpu(env));
5638 }
5639 
5640 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5641 {
5642     DeviceClass *dc = DEVICE_CLASS(oc);
5643     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5644 
5645     dc->desc = "PowerPC 745";
5646     pcc->init_proc = init_proc_745;
5647     pcc->check_pow = check_pow_hid0;
5648     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5649                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5650                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5651                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5652                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5653                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5654                        PPC_SEGMENT | PPC_EXTERN;
5655     pcc->msr_mask = (1ull << MSR_POW) |
5656                     (1ull << MSR_ILE) |
5657                     (1ull << MSR_EE) |
5658                     (1ull << MSR_PR) |
5659                     (1ull << MSR_FP) |
5660                     (1ull << MSR_ME) |
5661                     (1ull << MSR_FE0) |
5662                     (1ull << MSR_SE) |
5663                     (1ull << MSR_DE) |
5664                     (1ull << MSR_FE1) |
5665                     (1ull << MSR_EP) |
5666                     (1ull << MSR_IR) |
5667                     (1ull << MSR_DR) |
5668                     (1ull << MSR_PMM) |
5669                     (1ull << MSR_RI) |
5670                     (1ull << MSR_LE);
5671     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5672     pcc->excp_model = POWERPC_EXCP_7x5;
5673     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5674     pcc->bfd_mach = bfd_mach_ppc_750;
5675     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5676                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5677 }
5678 
5679 static void init_proc_755(CPUPPCState *env)
5680 {
5681     register_ne_601_sprs(env);
5682     register_sdr1_sprs(env);
5683     register_7xx_sprs(env);
5684     register_G2_755_sprs(env);
5685     /* Time base */
5686     register_tbl(env);
5687     /* L2 cache control */
5688     /* XXX : not implemented */
5689     spr_register(env, SPR_L2CR, "L2CR",
5690                  SPR_NOACCESS, SPR_NOACCESS,
5691                  &spr_read_generic, spr_access_nop,
5692                  0x00000000);
5693     /* XXX : not implemented */
5694     spr_register(env, SPR_L2PMCR, "L2PMCR",
5695                  SPR_NOACCESS, SPR_NOACCESS,
5696                  &spr_read_generic, &spr_write_generic,
5697                  0x00000000);
5698     /* Thermal management */
5699     register_thrm_sprs(env);
5700     /* Hardware implementation registers */
5701     /* XXX : not implemented */
5702     spr_register(env, SPR_HID0, "HID0",
5703                  SPR_NOACCESS, SPR_NOACCESS,
5704                  &spr_read_generic, &spr_write_generic,
5705                  0x00000000);
5706     /* XXX : not implemented */
5707     spr_register(env, SPR_HID1, "HID1",
5708                  SPR_NOACCESS, SPR_NOACCESS,
5709                  &spr_read_generic, &spr_write_generic,
5710                  0x00000000);
5711     /* XXX : not implemented */
5712     spr_register(env, SPR_HID2, "HID2",
5713                  SPR_NOACCESS, SPR_NOACCESS,
5714                  &spr_read_generic, &spr_write_generic,
5715                  0x00000000);
5716     /* Memory management */
5717     register_low_BATs(env);
5718     register_high_BATs(env);
5719     register_6xx_7xx_soft_tlb(env, 64, 2);
5720     init_excp_7x5(env);
5721     env->dcache_line_size = 32;
5722     env->icache_line_size = 32;
5723     /* Allocate hardware IRQ controller */
5724     ppc6xx_irq_init(env_archcpu(env));
5725 }
5726 
5727 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5728 {
5729     DeviceClass *dc = DEVICE_CLASS(oc);
5730     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5731 
5732     dc->desc = "PowerPC 755";
5733     pcc->init_proc = init_proc_755;
5734     pcc->check_pow = check_pow_hid0;
5735     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5736                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5737                        PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5738                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5739                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5740                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5741                        PPC_SEGMENT | PPC_EXTERN;
5742     pcc->msr_mask = (1ull << MSR_POW) |
5743                     (1ull << MSR_ILE) |
5744                     (1ull << MSR_EE) |
5745                     (1ull << MSR_PR) |
5746                     (1ull << MSR_FP) |
5747                     (1ull << MSR_ME) |
5748                     (1ull << MSR_FE0) |
5749                     (1ull << MSR_SE) |
5750                     (1ull << MSR_DE) |
5751                     (1ull << MSR_FE1) |
5752                     (1ull << MSR_EP) |
5753                     (1ull << MSR_IR) |
5754                     (1ull << MSR_DR) |
5755                     (1ull << MSR_PMM) |
5756                     (1ull << MSR_RI) |
5757                     (1ull << MSR_LE);
5758     pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5759     pcc->excp_model = POWERPC_EXCP_7x5;
5760     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5761     pcc->bfd_mach = bfd_mach_ppc_750;
5762     pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5763                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5764 }
5765 
5766 static void init_proc_7400(CPUPPCState *env)
5767 {
5768     register_ne_601_sprs(env);
5769     register_sdr1_sprs(env);
5770     register_7xx_sprs(env);
5771     /* Time base */
5772     register_tbl(env);
5773     /* 74xx specific SPR */
5774     register_74xx_sprs(env);
5775     vscr_init(env, 0x00010000);
5776     /* XXX : not implemented */
5777     spr_register(env, SPR_UBAMR, "UBAMR",
5778                  &spr_read_ureg, SPR_NOACCESS,
5779                  &spr_read_ureg, SPR_NOACCESS,
5780                  0x00000000);
5781     /* XXX: this seems not implemented on all revisions. */
5782     /* XXX : not implemented */
5783     spr_register(env, SPR_MSSCR1, "MSSCR1",
5784                  SPR_NOACCESS, SPR_NOACCESS,
5785                  &spr_read_generic, &spr_write_generic,
5786                  0x00000000);
5787     /* Thermal management */
5788     register_thrm_sprs(env);
5789     /* Memory management */
5790     register_low_BATs(env);
5791     init_excp_7400(env);
5792     env->dcache_line_size = 32;
5793     env->icache_line_size = 32;
5794     /* Allocate hardware IRQ controller */
5795     ppc6xx_irq_init(env_archcpu(env));
5796 }
5797 
5798 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5799 {
5800     DeviceClass *dc = DEVICE_CLASS(oc);
5801     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5802 
5803     dc->desc = "PowerPC 7400 (aka G4)";
5804     pcc->init_proc = init_proc_7400;
5805     pcc->check_pow = check_pow_hid0;
5806     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5807                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5808                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5809                        PPC_FLOAT_STFIWX |
5810                        PPC_CACHE | PPC_CACHE_ICBI |
5811                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5812                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5813                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5814                        PPC_MEM_TLBIA |
5815                        PPC_SEGMENT | PPC_EXTERN |
5816                        PPC_ALTIVEC;
5817     pcc->msr_mask = (1ull << MSR_VR) |
5818                     (1ull << MSR_POW) |
5819                     (1ull << MSR_ILE) |
5820                     (1ull << MSR_EE) |
5821                     (1ull << MSR_PR) |
5822                     (1ull << MSR_FP) |
5823                     (1ull << MSR_ME) |
5824                     (1ull << MSR_FE0) |
5825                     (1ull << MSR_SE) |
5826                     (1ull << MSR_DE) |
5827                     (1ull << MSR_FE1) |
5828                     (1ull << MSR_EP) |
5829                     (1ull << MSR_IR) |
5830                     (1ull << MSR_DR) |
5831                     (1ull << MSR_PMM) |
5832                     (1ull << MSR_RI) |
5833                     (1ull << MSR_LE);
5834     pcc->mmu_model = POWERPC_MMU_32B;
5835 #if defined(CONFIG_SOFTMMU)
5836     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5837 #endif
5838     pcc->excp_model = POWERPC_EXCP_74xx;
5839     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5840     pcc->bfd_mach = bfd_mach_ppc_7400;
5841     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5842                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5843                  POWERPC_FLAG_BUS_CLK;
5844 }
5845 
5846 static void init_proc_7410(CPUPPCState *env)
5847 {
5848     register_ne_601_sprs(env);
5849     register_sdr1_sprs(env);
5850     register_7xx_sprs(env);
5851     /* Time base */
5852     register_tbl(env);
5853     /* 74xx specific SPR */
5854     register_74xx_sprs(env);
5855     vscr_init(env, 0x00010000);
5856     /* XXX : not implemented */
5857     spr_register(env, SPR_UBAMR, "UBAMR",
5858                  &spr_read_ureg, SPR_NOACCESS,
5859                  &spr_read_ureg, SPR_NOACCESS,
5860                  0x00000000);
5861     /* Thermal management */
5862     register_thrm_sprs(env);
5863     /* L2PMCR */
5864     /* XXX : not implemented */
5865     spr_register(env, SPR_L2PMCR, "L2PMCR",
5866                  SPR_NOACCESS, SPR_NOACCESS,
5867                  &spr_read_generic, &spr_write_generic,
5868                  0x00000000);
5869     /* LDSTDB */
5870     /* XXX : not implemented */
5871     spr_register(env, SPR_LDSTDB, "LDSTDB",
5872                  SPR_NOACCESS, SPR_NOACCESS,
5873                  &spr_read_generic, &spr_write_generic,
5874                  0x00000000);
5875     /* Memory management */
5876     register_low_BATs(env);
5877     init_excp_7400(env);
5878     env->dcache_line_size = 32;
5879     env->icache_line_size = 32;
5880     /* Allocate hardware IRQ controller */
5881     ppc6xx_irq_init(env_archcpu(env));
5882 }
5883 
5884 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5885 {
5886     DeviceClass *dc = DEVICE_CLASS(oc);
5887     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5888 
5889     dc->desc = "PowerPC 7410 (aka G4)";
5890     pcc->init_proc = init_proc_7410;
5891     pcc->check_pow = check_pow_hid0;
5892     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5893                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5894                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5895                        PPC_FLOAT_STFIWX |
5896                        PPC_CACHE | PPC_CACHE_ICBI |
5897                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5898                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
5899                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5900                        PPC_MEM_TLBIA |
5901                        PPC_SEGMENT | PPC_EXTERN |
5902                        PPC_ALTIVEC;
5903     pcc->msr_mask = (1ull << MSR_VR) |
5904                     (1ull << MSR_POW) |
5905                     (1ull << MSR_ILE) |
5906                     (1ull << MSR_EE) |
5907                     (1ull << MSR_PR) |
5908                     (1ull << MSR_FP) |
5909                     (1ull << MSR_ME) |
5910                     (1ull << MSR_FE0) |
5911                     (1ull << MSR_SE) |
5912                     (1ull << MSR_DE) |
5913                     (1ull << MSR_FE1) |
5914                     (1ull << MSR_EP) |
5915                     (1ull << MSR_IR) |
5916                     (1ull << MSR_DR) |
5917                     (1ull << MSR_PMM) |
5918                     (1ull << MSR_RI) |
5919                     (1ull << MSR_LE);
5920     pcc->mmu_model = POWERPC_MMU_32B;
5921 #if defined(CONFIG_SOFTMMU)
5922     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5923 #endif
5924     pcc->excp_model = POWERPC_EXCP_74xx;
5925     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5926     pcc->bfd_mach = bfd_mach_ppc_7400;
5927     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5928                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5929                  POWERPC_FLAG_BUS_CLK;
5930 }
5931 
5932 static void init_proc_7440(CPUPPCState *env)
5933 {
5934     register_ne_601_sprs(env);
5935     register_sdr1_sprs(env);
5936     register_7xx_sprs(env);
5937     /* Time base */
5938     register_tbl(env);
5939     /* 74xx specific SPR */
5940     register_74xx_sprs(env);
5941     vscr_init(env, 0x00010000);
5942     /* XXX : not implemented */
5943     spr_register(env, SPR_UBAMR, "UBAMR",
5944                  &spr_read_ureg, SPR_NOACCESS,
5945                  &spr_read_ureg, SPR_NOACCESS,
5946                  0x00000000);
5947     /* LDSTCR */
5948     /* XXX : not implemented */
5949     spr_register(env, SPR_LDSTCR, "LDSTCR",
5950                  SPR_NOACCESS, SPR_NOACCESS,
5951                  &spr_read_generic, &spr_write_generic,
5952                  0x00000000);
5953     /* ICTRL */
5954     /* XXX : not implemented */
5955     spr_register(env, SPR_ICTRL, "ICTRL",
5956                  SPR_NOACCESS, SPR_NOACCESS,
5957                  &spr_read_generic, &spr_write_generic,
5958                  0x00000000);
5959     /* MSSSR0 */
5960     /* XXX : not implemented */
5961     spr_register(env, SPR_MSSSR0, "MSSSR0",
5962                  SPR_NOACCESS, SPR_NOACCESS,
5963                  &spr_read_generic, &spr_write_generic,
5964                  0x00000000);
5965     /* PMC */
5966     /* XXX : not implemented */
5967     spr_register(env, SPR_7XX_PMC5, "PMC5",
5968                  SPR_NOACCESS, SPR_NOACCESS,
5969                  &spr_read_generic, &spr_write_generic,
5970                  0x00000000);
5971     /* XXX : not implemented */
5972     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5973                  &spr_read_ureg, SPR_NOACCESS,
5974                  &spr_read_ureg, SPR_NOACCESS,
5975                  0x00000000);
5976     /* XXX : not implemented */
5977     spr_register(env, SPR_7XX_PMC6, "PMC6",
5978                  SPR_NOACCESS, SPR_NOACCESS,
5979                  &spr_read_generic, &spr_write_generic,
5980                  0x00000000);
5981     /* XXX : not implemented */
5982     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5983                  &spr_read_ureg, SPR_NOACCESS,
5984                  &spr_read_ureg, SPR_NOACCESS,
5985                  0x00000000);
5986     /* Memory management */
5987     register_low_BATs(env);
5988     register_74xx_soft_tlb(env, 128, 2);
5989     init_excp_7450(env);
5990     env->dcache_line_size = 32;
5991     env->icache_line_size = 32;
5992     /* Allocate hardware IRQ controller */
5993     ppc6xx_irq_init(env_archcpu(env));
5994 }
5995 
5996 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5997 {
5998     DeviceClass *dc = DEVICE_CLASS(oc);
5999     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6000 
6001     dc->desc = "PowerPC 7440 (aka G4)";
6002     pcc->init_proc = init_proc_7440;
6003     pcc->check_pow = check_pow_hid0_74xx;
6004     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6005                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6006                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6007                        PPC_FLOAT_STFIWX |
6008                        PPC_CACHE | PPC_CACHE_ICBI |
6009                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6010                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6011                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6012                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6013                        PPC_SEGMENT | PPC_EXTERN |
6014                        PPC_ALTIVEC;
6015     pcc->msr_mask = (1ull << MSR_VR) |
6016                     (1ull << MSR_POW) |
6017                     (1ull << MSR_ILE) |
6018                     (1ull << MSR_EE) |
6019                     (1ull << MSR_PR) |
6020                     (1ull << MSR_FP) |
6021                     (1ull << MSR_ME) |
6022                     (1ull << MSR_FE0) |
6023                     (1ull << MSR_SE) |
6024                     (1ull << MSR_DE) |
6025                     (1ull << MSR_FE1) |
6026                     (1ull << MSR_EP) |
6027                     (1ull << MSR_IR) |
6028                     (1ull << MSR_DR) |
6029                     (1ull << MSR_PMM) |
6030                     (1ull << MSR_RI) |
6031                     (1ull << MSR_LE);
6032     pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6033     pcc->excp_model = POWERPC_EXCP_74xx;
6034     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6035     pcc->bfd_mach = bfd_mach_ppc_7400;
6036     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6037                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6038                  POWERPC_FLAG_BUS_CLK;
6039 }
6040 
6041 static void init_proc_7450(CPUPPCState *env)
6042 {
6043     register_ne_601_sprs(env);
6044     register_sdr1_sprs(env);
6045     register_7xx_sprs(env);
6046     /* Time base */
6047     register_tbl(env);
6048     /* 74xx specific SPR */
6049     register_74xx_sprs(env);
6050     vscr_init(env, 0x00010000);
6051     /* Level 3 cache control */
6052     register_l3_ctrl(env);
6053     /* L3ITCR1 */
6054     /* XXX : not implemented */
6055     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6056                  SPR_NOACCESS, SPR_NOACCESS,
6057                  &spr_read_generic, &spr_write_generic,
6058                  0x00000000);
6059     /* L3ITCR2 */
6060     /* XXX : not implemented */
6061     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6062                  SPR_NOACCESS, SPR_NOACCESS,
6063                  &spr_read_generic, &spr_write_generic,
6064                  0x00000000);
6065     /* L3ITCR3 */
6066     /* XXX : not implemented */
6067     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6068                  SPR_NOACCESS, SPR_NOACCESS,
6069                  &spr_read_generic, &spr_write_generic,
6070                  0x00000000);
6071     /* L3OHCR */
6072     /* XXX : not implemented */
6073     spr_register(env, SPR_L3OHCR, "L3OHCR",
6074                  SPR_NOACCESS, SPR_NOACCESS,
6075                  &spr_read_generic, &spr_write_generic,
6076                  0x00000000);
6077     /* XXX : not implemented */
6078     spr_register(env, SPR_UBAMR, "UBAMR",
6079                  &spr_read_ureg, SPR_NOACCESS,
6080                  &spr_read_ureg, SPR_NOACCESS,
6081                  0x00000000);
6082     /* LDSTCR */
6083     /* XXX : not implemented */
6084     spr_register(env, SPR_LDSTCR, "LDSTCR",
6085                  SPR_NOACCESS, SPR_NOACCESS,
6086                  &spr_read_generic, &spr_write_generic,
6087                  0x00000000);
6088     /* ICTRL */
6089     /* XXX : not implemented */
6090     spr_register(env, SPR_ICTRL, "ICTRL",
6091                  SPR_NOACCESS, SPR_NOACCESS,
6092                  &spr_read_generic, &spr_write_generic,
6093                  0x00000000);
6094     /* MSSSR0 */
6095     /* XXX : not implemented */
6096     spr_register(env, SPR_MSSSR0, "MSSSR0",
6097                  SPR_NOACCESS, SPR_NOACCESS,
6098                  &spr_read_generic, &spr_write_generic,
6099                  0x00000000);
6100     /* PMC */
6101     /* XXX : not implemented */
6102     spr_register(env, SPR_7XX_PMC5, "PMC5",
6103                  SPR_NOACCESS, SPR_NOACCESS,
6104                  &spr_read_generic, &spr_write_generic,
6105                  0x00000000);
6106     /* XXX : not implemented */
6107     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6108                  &spr_read_ureg, SPR_NOACCESS,
6109                  &spr_read_ureg, SPR_NOACCESS,
6110                  0x00000000);
6111     /* XXX : not implemented */
6112     spr_register(env, SPR_7XX_PMC6, "PMC6",
6113                  SPR_NOACCESS, SPR_NOACCESS,
6114                  &spr_read_generic, &spr_write_generic,
6115                  0x00000000);
6116     /* XXX : not implemented */
6117     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6118                  &spr_read_ureg, SPR_NOACCESS,
6119                  &spr_read_ureg, SPR_NOACCESS,
6120                  0x00000000);
6121     /* Memory management */
6122     register_low_BATs(env);
6123     register_74xx_soft_tlb(env, 128, 2);
6124     init_excp_7450(env);
6125     env->dcache_line_size = 32;
6126     env->icache_line_size = 32;
6127     /* Allocate hardware IRQ controller */
6128     ppc6xx_irq_init(env_archcpu(env));
6129 }
6130 
6131 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6132 {
6133     DeviceClass *dc = DEVICE_CLASS(oc);
6134     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6135 
6136     dc->desc = "PowerPC 7450 (aka G4)";
6137     pcc->init_proc = init_proc_7450;
6138     pcc->check_pow = check_pow_hid0_74xx;
6139     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6140                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6141                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6142                        PPC_FLOAT_STFIWX |
6143                        PPC_CACHE | PPC_CACHE_ICBI |
6144                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6145                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6146                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6147                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6148                        PPC_SEGMENT | PPC_EXTERN |
6149                        PPC_ALTIVEC;
6150     pcc->msr_mask = (1ull << MSR_VR) |
6151                     (1ull << MSR_POW) |
6152                     (1ull << MSR_ILE) |
6153                     (1ull << MSR_EE) |
6154                     (1ull << MSR_PR) |
6155                     (1ull << MSR_FP) |
6156                     (1ull << MSR_ME) |
6157                     (1ull << MSR_FE0) |
6158                     (1ull << MSR_SE) |
6159                     (1ull << MSR_DE) |
6160                     (1ull << MSR_FE1) |
6161                     (1ull << MSR_EP) |
6162                     (1ull << MSR_IR) |
6163                     (1ull << MSR_DR) |
6164                     (1ull << MSR_PMM) |
6165                     (1ull << MSR_RI) |
6166                     (1ull << MSR_LE);
6167     pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6168     pcc->excp_model = POWERPC_EXCP_74xx;
6169     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6170     pcc->bfd_mach = bfd_mach_ppc_7400;
6171     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6172                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6173                  POWERPC_FLAG_BUS_CLK;
6174 }
6175 
6176 static void init_proc_7445(CPUPPCState *env)
6177 {
6178     register_ne_601_sprs(env);
6179     register_sdr1_sprs(env);
6180     register_7xx_sprs(env);
6181     /* Time base */
6182     register_tbl(env);
6183     /* 74xx specific SPR */
6184     register_74xx_sprs(env);
6185     vscr_init(env, 0x00010000);
6186     /* LDSTCR */
6187     /* XXX : not implemented */
6188     spr_register(env, SPR_LDSTCR, "LDSTCR",
6189                  SPR_NOACCESS, SPR_NOACCESS,
6190                  &spr_read_generic, &spr_write_generic,
6191                  0x00000000);
6192     /* ICTRL */
6193     /* XXX : not implemented */
6194     spr_register(env, SPR_ICTRL, "ICTRL",
6195                  SPR_NOACCESS, SPR_NOACCESS,
6196                  &spr_read_generic, &spr_write_generic,
6197                  0x00000000);
6198     /* MSSSR0 */
6199     /* XXX : not implemented */
6200     spr_register(env, SPR_MSSSR0, "MSSSR0",
6201                  SPR_NOACCESS, SPR_NOACCESS,
6202                  &spr_read_generic, &spr_write_generic,
6203                  0x00000000);
6204     /* PMC */
6205     /* XXX : not implemented */
6206     spr_register(env, SPR_7XX_PMC5, "PMC5",
6207                  SPR_NOACCESS, SPR_NOACCESS,
6208                  &spr_read_generic, &spr_write_generic,
6209                  0x00000000);
6210     /* XXX : not implemented */
6211     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6212                  &spr_read_ureg, SPR_NOACCESS,
6213                  &spr_read_ureg, SPR_NOACCESS,
6214                  0x00000000);
6215     /* XXX : not implemented */
6216     spr_register(env, SPR_7XX_PMC6, "PMC6",
6217                  SPR_NOACCESS, SPR_NOACCESS,
6218                  &spr_read_generic, &spr_write_generic,
6219                  0x00000000);
6220     /* XXX : not implemented */
6221     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6222                  &spr_read_ureg, SPR_NOACCESS,
6223                  &spr_read_ureg, SPR_NOACCESS,
6224                  0x00000000);
6225     /* SPRGs */
6226     spr_register(env, SPR_SPRG4, "SPRG4",
6227                  SPR_NOACCESS, SPR_NOACCESS,
6228                  &spr_read_generic, &spr_write_generic,
6229                  0x00000000);
6230     spr_register(env, SPR_USPRG4, "USPRG4",
6231                  &spr_read_ureg, SPR_NOACCESS,
6232                  &spr_read_ureg, SPR_NOACCESS,
6233                  0x00000000);
6234     spr_register(env, SPR_SPRG5, "SPRG5",
6235                  SPR_NOACCESS, SPR_NOACCESS,
6236                  &spr_read_generic, &spr_write_generic,
6237                  0x00000000);
6238     spr_register(env, SPR_USPRG5, "USPRG5",
6239                  &spr_read_ureg, SPR_NOACCESS,
6240                  &spr_read_ureg, SPR_NOACCESS,
6241                  0x00000000);
6242     spr_register(env, SPR_SPRG6, "SPRG6",
6243                  SPR_NOACCESS, SPR_NOACCESS,
6244                  &spr_read_generic, &spr_write_generic,
6245                  0x00000000);
6246     spr_register(env, SPR_USPRG6, "USPRG6",
6247                  &spr_read_ureg, SPR_NOACCESS,
6248                  &spr_read_ureg, SPR_NOACCESS,
6249                  0x00000000);
6250     spr_register(env, SPR_SPRG7, "SPRG7",
6251                  SPR_NOACCESS, SPR_NOACCESS,
6252                  &spr_read_generic, &spr_write_generic,
6253                  0x00000000);
6254     spr_register(env, SPR_USPRG7, "USPRG7",
6255                  &spr_read_ureg, SPR_NOACCESS,
6256                  &spr_read_ureg, SPR_NOACCESS,
6257                  0x00000000);
6258     /* Memory management */
6259     register_low_BATs(env);
6260     register_high_BATs(env);
6261     register_74xx_soft_tlb(env, 128, 2);
6262     init_excp_7450(env);
6263     env->dcache_line_size = 32;
6264     env->icache_line_size = 32;
6265     /* Allocate hardware IRQ controller */
6266     ppc6xx_irq_init(env_archcpu(env));
6267 }
6268 
6269 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6270 {
6271     DeviceClass *dc = DEVICE_CLASS(oc);
6272     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6273 
6274     dc->desc = "PowerPC 7445 (aka G4)";
6275     pcc->init_proc = init_proc_7445;
6276     pcc->check_pow = check_pow_hid0_74xx;
6277     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6278                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6279                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6280                        PPC_FLOAT_STFIWX |
6281                        PPC_CACHE | PPC_CACHE_ICBI |
6282                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6283                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6284                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6285                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6286                        PPC_SEGMENT | PPC_EXTERN |
6287                        PPC_ALTIVEC;
6288     pcc->msr_mask = (1ull << MSR_VR) |
6289                     (1ull << MSR_POW) |
6290                     (1ull << MSR_ILE) |
6291                     (1ull << MSR_EE) |
6292                     (1ull << MSR_PR) |
6293                     (1ull << MSR_FP) |
6294                     (1ull << MSR_ME) |
6295                     (1ull << MSR_FE0) |
6296                     (1ull << MSR_SE) |
6297                     (1ull << MSR_DE) |
6298                     (1ull << MSR_FE1) |
6299                     (1ull << MSR_EP) |
6300                     (1ull << MSR_IR) |
6301                     (1ull << MSR_DR) |
6302                     (1ull << MSR_PMM) |
6303                     (1ull << MSR_RI) |
6304                     (1ull << MSR_LE);
6305     pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6306     pcc->excp_model = POWERPC_EXCP_74xx;
6307     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6308     pcc->bfd_mach = bfd_mach_ppc_7400;
6309     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6310                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6311                  POWERPC_FLAG_BUS_CLK;
6312 }
6313 
6314 static void init_proc_7455(CPUPPCState *env)
6315 {
6316     register_ne_601_sprs(env);
6317     register_sdr1_sprs(env);
6318     register_7xx_sprs(env);
6319     /* Time base */
6320     register_tbl(env);
6321     /* 74xx specific SPR */
6322     register_74xx_sprs(env);
6323     vscr_init(env, 0x00010000);
6324     /* Level 3 cache control */
6325     register_l3_ctrl(env);
6326     /* LDSTCR */
6327     /* XXX : not implemented */
6328     spr_register(env, SPR_LDSTCR, "LDSTCR",
6329                  SPR_NOACCESS, SPR_NOACCESS,
6330                  &spr_read_generic, &spr_write_generic,
6331                  0x00000000);
6332     /* ICTRL */
6333     /* XXX : not implemented */
6334     spr_register(env, SPR_ICTRL, "ICTRL",
6335                  SPR_NOACCESS, SPR_NOACCESS,
6336                  &spr_read_generic, &spr_write_generic,
6337                  0x00000000);
6338     /* MSSSR0 */
6339     /* XXX : not implemented */
6340     spr_register(env, SPR_MSSSR0, "MSSSR0",
6341                  SPR_NOACCESS, SPR_NOACCESS,
6342                  &spr_read_generic, &spr_write_generic,
6343                  0x00000000);
6344     /* PMC */
6345     /* XXX : not implemented */
6346     spr_register(env, SPR_7XX_PMC5, "PMC5",
6347                  SPR_NOACCESS, SPR_NOACCESS,
6348                  &spr_read_generic, &spr_write_generic,
6349                  0x00000000);
6350     /* XXX : not implemented */
6351     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6352                  &spr_read_ureg, SPR_NOACCESS,
6353                  &spr_read_ureg, SPR_NOACCESS,
6354                  0x00000000);
6355     /* XXX : not implemented */
6356     spr_register(env, SPR_7XX_PMC6, "PMC6",
6357                  SPR_NOACCESS, SPR_NOACCESS,
6358                  &spr_read_generic, &spr_write_generic,
6359                  0x00000000);
6360     /* XXX : not implemented */
6361     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6362                  &spr_read_ureg, SPR_NOACCESS,
6363                  &spr_read_ureg, SPR_NOACCESS,
6364                  0x00000000);
6365     /* SPRGs */
6366     spr_register(env, SPR_SPRG4, "SPRG4",
6367                  SPR_NOACCESS, SPR_NOACCESS,
6368                  &spr_read_generic, &spr_write_generic,
6369                  0x00000000);
6370     spr_register(env, SPR_USPRG4, "USPRG4",
6371                  &spr_read_ureg, SPR_NOACCESS,
6372                  &spr_read_ureg, SPR_NOACCESS,
6373                  0x00000000);
6374     spr_register(env, SPR_SPRG5, "SPRG5",
6375                  SPR_NOACCESS, SPR_NOACCESS,
6376                  &spr_read_generic, &spr_write_generic,
6377                  0x00000000);
6378     spr_register(env, SPR_USPRG5, "USPRG5",
6379                  &spr_read_ureg, SPR_NOACCESS,
6380                  &spr_read_ureg, SPR_NOACCESS,
6381                  0x00000000);
6382     spr_register(env, SPR_SPRG6, "SPRG6",
6383                  SPR_NOACCESS, SPR_NOACCESS,
6384                  &spr_read_generic, &spr_write_generic,
6385                  0x00000000);
6386     spr_register(env, SPR_USPRG6, "USPRG6",
6387                  &spr_read_ureg, SPR_NOACCESS,
6388                  &spr_read_ureg, SPR_NOACCESS,
6389                  0x00000000);
6390     spr_register(env, SPR_SPRG7, "SPRG7",
6391                  SPR_NOACCESS, SPR_NOACCESS,
6392                  &spr_read_generic, &spr_write_generic,
6393                  0x00000000);
6394     spr_register(env, SPR_USPRG7, "USPRG7",
6395                  &spr_read_ureg, SPR_NOACCESS,
6396                  &spr_read_ureg, SPR_NOACCESS,
6397                  0x00000000);
6398     /* Memory management */
6399     register_low_BATs(env);
6400     register_high_BATs(env);
6401     register_74xx_soft_tlb(env, 128, 2);
6402     init_excp_7450(env);
6403     env->dcache_line_size = 32;
6404     env->icache_line_size = 32;
6405     /* Allocate hardware IRQ controller */
6406     ppc6xx_irq_init(env_archcpu(env));
6407 }
6408 
6409 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6410 {
6411     DeviceClass *dc = DEVICE_CLASS(oc);
6412     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6413 
6414     dc->desc = "PowerPC 7455 (aka G4)";
6415     pcc->init_proc = init_proc_7455;
6416     pcc->check_pow = check_pow_hid0_74xx;
6417     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6418                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6419                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6420                        PPC_FLOAT_STFIWX |
6421                        PPC_CACHE | PPC_CACHE_ICBI |
6422                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6423                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6424                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6425                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6426                        PPC_SEGMENT | PPC_EXTERN |
6427                        PPC_ALTIVEC;
6428     pcc->msr_mask = (1ull << MSR_VR) |
6429                     (1ull << MSR_POW) |
6430                     (1ull << MSR_ILE) |
6431                     (1ull << MSR_EE) |
6432                     (1ull << MSR_PR) |
6433                     (1ull << MSR_FP) |
6434                     (1ull << MSR_ME) |
6435                     (1ull << MSR_FE0) |
6436                     (1ull << MSR_SE) |
6437                     (1ull << MSR_DE) |
6438                     (1ull << MSR_FE1) |
6439                     (1ull << MSR_EP) |
6440                     (1ull << MSR_IR) |
6441                     (1ull << MSR_DR) |
6442                     (1ull << MSR_PMM) |
6443                     (1ull << MSR_RI) |
6444                     (1ull << MSR_LE);
6445     pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6446     pcc->excp_model = POWERPC_EXCP_74xx;
6447     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6448     pcc->bfd_mach = bfd_mach_ppc_7400;
6449     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6450                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6451                  POWERPC_FLAG_BUS_CLK;
6452 }
6453 
6454 static void init_proc_7457(CPUPPCState *env)
6455 {
6456     register_ne_601_sprs(env);
6457     register_sdr1_sprs(env);
6458     register_7xx_sprs(env);
6459     /* Time base */
6460     register_tbl(env);
6461     /* 74xx specific SPR */
6462     register_74xx_sprs(env);
6463     vscr_init(env, 0x00010000);
6464     /* Level 3 cache control */
6465     register_l3_ctrl(env);
6466     /* L3ITCR1 */
6467     /* XXX : not implemented */
6468     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6469                  SPR_NOACCESS, SPR_NOACCESS,
6470                  &spr_read_generic, &spr_write_generic,
6471                  0x00000000);
6472     /* L3ITCR2 */
6473     /* XXX : not implemented */
6474     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6475                  SPR_NOACCESS, SPR_NOACCESS,
6476                  &spr_read_generic, &spr_write_generic,
6477                  0x00000000);
6478     /* L3ITCR3 */
6479     /* XXX : not implemented */
6480     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6481                  SPR_NOACCESS, SPR_NOACCESS,
6482                  &spr_read_generic, &spr_write_generic,
6483                  0x00000000);
6484     /* L3OHCR */
6485     /* XXX : not implemented */
6486     spr_register(env, SPR_L3OHCR, "L3OHCR",
6487                  SPR_NOACCESS, SPR_NOACCESS,
6488                  &spr_read_generic, &spr_write_generic,
6489                  0x00000000);
6490     /* LDSTCR */
6491     /* XXX : not implemented */
6492     spr_register(env, SPR_LDSTCR, "LDSTCR",
6493                  SPR_NOACCESS, SPR_NOACCESS,
6494                  &spr_read_generic, &spr_write_generic,
6495                  0x00000000);
6496     /* ICTRL */
6497     /* XXX : not implemented */
6498     spr_register(env, SPR_ICTRL, "ICTRL",
6499                  SPR_NOACCESS, SPR_NOACCESS,
6500                  &spr_read_generic, &spr_write_generic,
6501                  0x00000000);
6502     /* MSSSR0 */
6503     /* XXX : not implemented */
6504     spr_register(env, SPR_MSSSR0, "MSSSR0",
6505                  SPR_NOACCESS, SPR_NOACCESS,
6506                  &spr_read_generic, &spr_write_generic,
6507                  0x00000000);
6508     /* PMC */
6509     /* XXX : not implemented */
6510     spr_register(env, SPR_7XX_PMC5, "PMC5",
6511                  SPR_NOACCESS, SPR_NOACCESS,
6512                  &spr_read_generic, &spr_write_generic,
6513                  0x00000000);
6514     /* XXX : not implemented */
6515     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6516                  &spr_read_ureg, SPR_NOACCESS,
6517                  &spr_read_ureg, SPR_NOACCESS,
6518                  0x00000000);
6519     /* XXX : not implemented */
6520     spr_register(env, SPR_7XX_PMC6, "PMC6",
6521                  SPR_NOACCESS, SPR_NOACCESS,
6522                  &spr_read_generic, &spr_write_generic,
6523                  0x00000000);
6524     /* XXX : not implemented */
6525     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6526                  &spr_read_ureg, SPR_NOACCESS,
6527                  &spr_read_ureg, SPR_NOACCESS,
6528                  0x00000000);
6529     /* SPRGs */
6530     spr_register(env, SPR_SPRG4, "SPRG4",
6531                  SPR_NOACCESS, SPR_NOACCESS,
6532                  &spr_read_generic, &spr_write_generic,
6533                  0x00000000);
6534     spr_register(env, SPR_USPRG4, "USPRG4",
6535                  &spr_read_ureg, SPR_NOACCESS,
6536                  &spr_read_ureg, SPR_NOACCESS,
6537                  0x00000000);
6538     spr_register(env, SPR_SPRG5, "SPRG5",
6539                  SPR_NOACCESS, SPR_NOACCESS,
6540                  &spr_read_generic, &spr_write_generic,
6541                  0x00000000);
6542     spr_register(env, SPR_USPRG5, "USPRG5",
6543                  &spr_read_ureg, SPR_NOACCESS,
6544                  &spr_read_ureg, SPR_NOACCESS,
6545                  0x00000000);
6546     spr_register(env, SPR_SPRG6, "SPRG6",
6547                  SPR_NOACCESS, SPR_NOACCESS,
6548                  &spr_read_generic, &spr_write_generic,
6549                  0x00000000);
6550     spr_register(env, SPR_USPRG6, "USPRG6",
6551                  &spr_read_ureg, SPR_NOACCESS,
6552                  &spr_read_ureg, SPR_NOACCESS,
6553                  0x00000000);
6554     spr_register(env, SPR_SPRG7, "SPRG7",
6555                  SPR_NOACCESS, SPR_NOACCESS,
6556                  &spr_read_generic, &spr_write_generic,
6557                  0x00000000);
6558     spr_register(env, SPR_USPRG7, "USPRG7",
6559                  &spr_read_ureg, SPR_NOACCESS,
6560                  &spr_read_ureg, SPR_NOACCESS,
6561                  0x00000000);
6562     /* Memory management */
6563     register_low_BATs(env);
6564     register_high_BATs(env);
6565     register_74xx_soft_tlb(env, 128, 2);
6566     init_excp_7450(env);
6567     env->dcache_line_size = 32;
6568     env->icache_line_size = 32;
6569     /* Allocate hardware IRQ controller */
6570     ppc6xx_irq_init(env_archcpu(env));
6571 }
6572 
6573 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6574 {
6575     DeviceClass *dc = DEVICE_CLASS(oc);
6576     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6577 
6578     dc->desc = "PowerPC 7457 (aka G4)";
6579     pcc->init_proc = init_proc_7457;
6580     pcc->check_pow = check_pow_hid0_74xx;
6581     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6582                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6583                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6584                        PPC_FLOAT_STFIWX |
6585                        PPC_CACHE | PPC_CACHE_ICBI |
6586                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6587                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6588                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6589                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6590                        PPC_SEGMENT | PPC_EXTERN |
6591                        PPC_ALTIVEC;
6592     pcc->msr_mask = (1ull << MSR_VR) |
6593                     (1ull << MSR_POW) |
6594                     (1ull << MSR_ILE) |
6595                     (1ull << MSR_EE) |
6596                     (1ull << MSR_PR) |
6597                     (1ull << MSR_FP) |
6598                     (1ull << MSR_ME) |
6599                     (1ull << MSR_FE0) |
6600                     (1ull << MSR_SE) |
6601                     (1ull << MSR_DE) |
6602                     (1ull << MSR_FE1) |
6603                     (1ull << MSR_EP) |
6604                     (1ull << MSR_IR) |
6605                     (1ull << MSR_DR) |
6606                     (1ull << MSR_PMM) |
6607                     (1ull << MSR_RI) |
6608                     (1ull << MSR_LE);
6609     pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6610     pcc->excp_model = POWERPC_EXCP_74xx;
6611     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6612     pcc->bfd_mach = bfd_mach_ppc_7400;
6613     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6614                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6615                  POWERPC_FLAG_BUS_CLK;
6616 }
6617 
6618 static void init_proc_e600(CPUPPCState *env)
6619 {
6620     register_ne_601_sprs(env);
6621     register_sdr1_sprs(env);
6622     register_7xx_sprs(env);
6623     /* Time base */
6624     register_tbl(env);
6625     /* 74xx specific SPR */
6626     register_74xx_sprs(env);
6627     vscr_init(env, 0x00010000);
6628     /* XXX : not implemented */
6629     spr_register(env, SPR_UBAMR, "UBAMR",
6630                  &spr_read_ureg, SPR_NOACCESS,
6631                  &spr_read_ureg, SPR_NOACCESS,
6632                  0x00000000);
6633     /* XXX : not implemented */
6634     spr_register(env, SPR_LDSTCR, "LDSTCR",
6635                  SPR_NOACCESS, SPR_NOACCESS,
6636                  &spr_read_generic, &spr_write_generic,
6637                  0x00000000);
6638     /* XXX : not implemented */
6639     spr_register(env, SPR_ICTRL, "ICTRL",
6640                  SPR_NOACCESS, SPR_NOACCESS,
6641                  &spr_read_generic, &spr_write_generic,
6642                  0x00000000);
6643     /* XXX : not implemented */
6644     spr_register(env, SPR_MSSSR0, "MSSSR0",
6645                  SPR_NOACCESS, SPR_NOACCESS,
6646                  &spr_read_generic, &spr_write_generic,
6647                  0x00000000);
6648     /* XXX : not implemented */
6649     spr_register(env, SPR_7XX_PMC5, "PMC5",
6650                  SPR_NOACCESS, SPR_NOACCESS,
6651                  &spr_read_generic, &spr_write_generic,
6652                  0x00000000);
6653     /* XXX : not implemented */
6654     spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6655                  &spr_read_ureg, SPR_NOACCESS,
6656                  &spr_read_ureg, SPR_NOACCESS,
6657                  0x00000000);
6658     /* XXX : not implemented */
6659     spr_register(env, SPR_7XX_PMC6, "PMC6",
6660                  SPR_NOACCESS, SPR_NOACCESS,
6661                  &spr_read_generic, &spr_write_generic,
6662                  0x00000000);
6663     /* XXX : not implemented */
6664     spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6665                  &spr_read_ureg, SPR_NOACCESS,
6666                  &spr_read_ureg, SPR_NOACCESS,
6667                  0x00000000);
6668     /* SPRGs */
6669     spr_register(env, SPR_SPRG4, "SPRG4",
6670                  SPR_NOACCESS, SPR_NOACCESS,
6671                  &spr_read_generic, &spr_write_generic,
6672                  0x00000000);
6673     spr_register(env, SPR_USPRG4, "USPRG4",
6674                  &spr_read_ureg, SPR_NOACCESS,
6675                  &spr_read_ureg, SPR_NOACCESS,
6676                  0x00000000);
6677     spr_register(env, SPR_SPRG5, "SPRG5",
6678                  SPR_NOACCESS, SPR_NOACCESS,
6679                  &spr_read_generic, &spr_write_generic,
6680                  0x00000000);
6681     spr_register(env, SPR_USPRG5, "USPRG5",
6682                  &spr_read_ureg, SPR_NOACCESS,
6683                  &spr_read_ureg, SPR_NOACCESS,
6684                  0x00000000);
6685     spr_register(env, SPR_SPRG6, "SPRG6",
6686                  SPR_NOACCESS, SPR_NOACCESS,
6687                  &spr_read_generic, &spr_write_generic,
6688                  0x00000000);
6689     spr_register(env, SPR_USPRG6, "USPRG6",
6690                  &spr_read_ureg, SPR_NOACCESS,
6691                  &spr_read_ureg, SPR_NOACCESS,
6692                  0x00000000);
6693     spr_register(env, SPR_SPRG7, "SPRG7",
6694                  SPR_NOACCESS, SPR_NOACCESS,
6695                  &spr_read_generic, &spr_write_generic,
6696                  0x00000000);
6697     spr_register(env, SPR_USPRG7, "USPRG7",
6698                  &spr_read_ureg, SPR_NOACCESS,
6699                  &spr_read_ureg, SPR_NOACCESS,
6700                  0x00000000);
6701     /* Memory management */
6702     register_low_BATs(env);
6703     register_high_BATs(env);
6704     register_74xx_soft_tlb(env, 128, 2);
6705     init_excp_7450(env);
6706     env->dcache_line_size = 32;
6707     env->icache_line_size = 32;
6708     /* Allocate hardware IRQ controller */
6709     ppc6xx_irq_init(env_archcpu(env));
6710 }
6711 
6712 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6713 {
6714     DeviceClass *dc = DEVICE_CLASS(oc);
6715     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6716 
6717     dc->desc = "PowerPC e600";
6718     pcc->init_proc = init_proc_e600;
6719     pcc->check_pow = check_pow_hid0_74xx;
6720     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6721                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6722                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6723                        PPC_FLOAT_STFIWX |
6724                        PPC_CACHE | PPC_CACHE_ICBI |
6725                        PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6726                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
6727                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6728                        PPC_MEM_TLBIA | PPC_74xx_TLB |
6729                        PPC_SEGMENT | PPC_EXTERN |
6730                        PPC_ALTIVEC;
6731     pcc->insns_flags2 = PPC_NONE;
6732     pcc->msr_mask = (1ull << MSR_VR) |
6733                     (1ull << MSR_POW) |
6734                     (1ull << MSR_ILE) |
6735                     (1ull << MSR_EE) |
6736                     (1ull << MSR_PR) |
6737                     (1ull << MSR_FP) |
6738                     (1ull << MSR_ME) |
6739                     (1ull << MSR_FE0) |
6740                     (1ull << MSR_SE) |
6741                     (1ull << MSR_DE) |
6742                     (1ull << MSR_FE1) |
6743                     (1ull << MSR_EP) |
6744                     (1ull << MSR_IR) |
6745                     (1ull << MSR_DR) |
6746                     (1ull << MSR_PMM) |
6747                     (1ull << MSR_RI) |
6748                     (1ull << MSR_LE);
6749     pcc->mmu_model = POWERPC_MMU_32B;
6750 #if defined(CONFIG_SOFTMMU)
6751     pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6752 #endif
6753     pcc->excp_model = POWERPC_EXCP_74xx;
6754     pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6755     pcc->bfd_mach = bfd_mach_ppc_7400;
6756     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6757                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6758                  POWERPC_FLAG_BUS_CLK;
6759 }
6760 
6761 #if defined(TARGET_PPC64)
6762 #if defined(CONFIG_USER_ONLY)
6763 #define POWERPC970_HID5_INIT 0x00000080
6764 #else
6765 #define POWERPC970_HID5_INIT 0x00000000
6766 #endif
6767 
6768 static int check_pow_970(CPUPPCState *env)
6769 {
6770     if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
6771         return 1;
6772     }
6773 
6774     return 0;
6775 }
6776 
6777 static void register_970_hid_sprs(CPUPPCState *env)
6778 {
6779     /* Hardware implementation registers */
6780     /* XXX : not implemented */
6781     spr_register(env, SPR_HID0, "HID0",
6782                  SPR_NOACCESS, SPR_NOACCESS,
6783                  &spr_read_generic, &spr_write_clear,
6784                  0x60000000);
6785     spr_register(env, SPR_HID1, "HID1",
6786                  SPR_NOACCESS, SPR_NOACCESS,
6787                  &spr_read_generic, &spr_write_generic,
6788                  0x00000000);
6789     spr_register(env, SPR_970_HID5, "HID5",
6790                  SPR_NOACCESS, SPR_NOACCESS,
6791                  &spr_read_generic, &spr_write_generic,
6792                  POWERPC970_HID5_INIT);
6793 }
6794 
6795 static void register_970_hior_sprs(CPUPPCState *env)
6796 {
6797     spr_register(env, SPR_HIOR, "SPR_HIOR",
6798                  SPR_NOACCESS, SPR_NOACCESS,
6799                  &spr_read_hior, &spr_write_hior,
6800                  0x00000000);
6801 }
6802 
6803 static void register_book3s_ctrl_sprs(CPUPPCState *env)
6804 {
6805     spr_register(env, SPR_CTRL, "SPR_CTRL",
6806                  SPR_NOACCESS, SPR_NOACCESS,
6807                  SPR_NOACCESS, &spr_write_generic,
6808                  0x00000000);
6809     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6810                  &spr_read_ureg, SPR_NOACCESS,
6811                  &spr_read_ureg, SPR_NOACCESS,
6812                  0x00000000);
6813 }
6814 
6815 static void register_book3s_altivec_sprs(CPUPPCState *env)
6816 {
6817     if (!(env->insns_flags & PPC_ALTIVEC)) {
6818         return;
6819     }
6820 
6821     spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
6822                      &spr_read_generic, &spr_write_generic,
6823                      &spr_read_generic, &spr_write_generic,
6824                      KVM_REG_PPC_VRSAVE, 0x00000000);
6825 
6826 }
6827 
6828 static void register_book3s_dbg_sprs(CPUPPCState *env)
6829 {
6830     /*
6831      * TODO: different specs define different scopes for these,
6832      * will have to address this:
6833      * 970: super/write and super/read
6834      * powerisa 2.03..2.04: hypv/write and super/read.
6835      * powerisa 2.05 and newer: hypv/write and hypv/read.
6836      */
6837     spr_register_kvm(env, SPR_DABR, "DABR",
6838                      SPR_NOACCESS, SPR_NOACCESS,
6839                      &spr_read_generic, &spr_write_generic,
6840                      KVM_REG_PPC_DABR, 0x00000000);
6841     spr_register_kvm(env, SPR_DABRX, "DABRX",
6842                      SPR_NOACCESS, SPR_NOACCESS,
6843                      &spr_read_generic, &spr_write_generic,
6844                      KVM_REG_PPC_DABRX, 0x00000000);
6845 }
6846 
6847 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
6848 {
6849     spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
6850                         SPR_NOACCESS, SPR_NOACCESS,
6851                         SPR_NOACCESS, SPR_NOACCESS,
6852                         &spr_read_generic, &spr_write_generic,
6853                         KVM_REG_PPC_DAWR, 0x00000000);
6854     spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
6855                         SPR_NOACCESS, SPR_NOACCESS,
6856                         SPR_NOACCESS, SPR_NOACCESS,
6857                         &spr_read_generic, &spr_write_generic,
6858                         KVM_REG_PPC_DAWRX, 0x00000000);
6859     spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
6860                         SPR_NOACCESS, SPR_NOACCESS,
6861                         SPR_NOACCESS, SPR_NOACCESS,
6862                         &spr_read_generic, &spr_write_generic,
6863                         KVM_REG_PPC_CIABR, 0x00000000);
6864 }
6865 
6866 static void register_970_dbg_sprs(CPUPPCState *env)
6867 {
6868     /* Breakpoints */
6869     spr_register(env, SPR_IABR, "IABR",
6870                  SPR_NOACCESS, SPR_NOACCESS,
6871                  &spr_read_generic, &spr_write_generic,
6872                  0x00000000);
6873 }
6874 
6875 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
6876 {
6877     spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
6878                      SPR_NOACCESS, SPR_NOACCESS,
6879                      &spr_read_generic, &spr_write_generic,
6880                      KVM_REG_PPC_MMCR0, 0x00000000);
6881     spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
6882                      SPR_NOACCESS, SPR_NOACCESS,
6883                      &spr_read_generic, &spr_write_generic,
6884                      KVM_REG_PPC_MMCR1, 0x00000000);
6885     spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
6886                      SPR_NOACCESS, SPR_NOACCESS,
6887                      &spr_read_generic, &spr_write_generic,
6888                      KVM_REG_PPC_MMCRA, 0x00000000);
6889     spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
6890                      SPR_NOACCESS, SPR_NOACCESS,
6891                      &spr_read_generic, &spr_write_generic,
6892                      KVM_REG_PPC_PMC1, 0x00000000);
6893     spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
6894                      SPR_NOACCESS, SPR_NOACCESS,
6895                      &spr_read_generic, &spr_write_generic,
6896                      KVM_REG_PPC_PMC2, 0x00000000);
6897     spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
6898                      SPR_NOACCESS, SPR_NOACCESS,
6899                      &spr_read_generic, &spr_write_generic,
6900                      KVM_REG_PPC_PMC3, 0x00000000);
6901     spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
6902                      SPR_NOACCESS, SPR_NOACCESS,
6903                      &spr_read_generic, &spr_write_generic,
6904                      KVM_REG_PPC_PMC4, 0x00000000);
6905     spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
6906                      SPR_NOACCESS, SPR_NOACCESS,
6907                      &spr_read_generic, &spr_write_generic,
6908                      KVM_REG_PPC_PMC5, 0x00000000);
6909     spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
6910                      SPR_NOACCESS, SPR_NOACCESS,
6911                      &spr_read_generic, &spr_write_generic,
6912                      KVM_REG_PPC_PMC6, 0x00000000);
6913     spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
6914                      SPR_NOACCESS, SPR_NOACCESS,
6915                      &spr_read_generic, &spr_write_generic,
6916                      KVM_REG_PPC_SIAR, 0x00000000);
6917     spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
6918                      SPR_NOACCESS, SPR_NOACCESS,
6919                      &spr_read_generic, &spr_write_generic,
6920                      KVM_REG_PPC_SDAR, 0x00000000);
6921 }
6922 
6923 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
6924 {
6925     spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
6926                  &spr_read_ureg, SPR_NOACCESS,
6927                  &spr_read_ureg, &spr_write_ureg,
6928                  0x00000000);
6929     spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
6930                  &spr_read_ureg, SPR_NOACCESS,
6931                  &spr_read_ureg, &spr_write_ureg,
6932                  0x00000000);
6933     spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
6934                  &spr_read_ureg, SPR_NOACCESS,
6935                  &spr_read_ureg, &spr_write_ureg,
6936                  0x00000000);
6937     spr_register(env, SPR_POWER_UPMC1, "UPMC1",
6938                  &spr_read_ureg, SPR_NOACCESS,
6939                  &spr_read_ureg, &spr_write_ureg,
6940                  0x00000000);
6941     spr_register(env, SPR_POWER_UPMC2, "UPMC2",
6942                  &spr_read_ureg, SPR_NOACCESS,
6943                  &spr_read_ureg, &spr_write_ureg,
6944                  0x00000000);
6945     spr_register(env, SPR_POWER_UPMC3, "UPMC3",
6946                  &spr_read_ureg, SPR_NOACCESS,
6947                  &spr_read_ureg, &spr_write_ureg,
6948                  0x00000000);
6949     spr_register(env, SPR_POWER_UPMC4, "UPMC4",
6950                  &spr_read_ureg, SPR_NOACCESS,
6951                  &spr_read_ureg, &spr_write_ureg,
6952                  0x00000000);
6953     spr_register(env, SPR_POWER_UPMC5, "UPMC5",
6954                  &spr_read_ureg, SPR_NOACCESS,
6955                  &spr_read_ureg, &spr_write_ureg,
6956                  0x00000000);
6957     spr_register(env, SPR_POWER_UPMC6, "UPMC6",
6958                  &spr_read_ureg, SPR_NOACCESS,
6959                  &spr_read_ureg, &spr_write_ureg,
6960                  0x00000000);
6961     spr_register(env, SPR_POWER_USIAR, "USIAR",
6962                  &spr_read_ureg, SPR_NOACCESS,
6963                  &spr_read_ureg, &spr_write_ureg,
6964                  0x00000000);
6965     spr_register(env, SPR_POWER_USDAR, "USDAR",
6966                  &spr_read_ureg, SPR_NOACCESS,
6967                  &spr_read_ureg, &spr_write_ureg,
6968                  0x00000000);
6969 }
6970 
6971 static void register_970_pmu_sup_sprs(CPUPPCState *env)
6972 {
6973     spr_register_kvm(env, SPR_970_PMC7, "PMC7",
6974                      SPR_NOACCESS, SPR_NOACCESS,
6975                      &spr_read_generic, &spr_write_generic,
6976                      KVM_REG_PPC_PMC7, 0x00000000);
6977     spr_register_kvm(env, SPR_970_PMC8, "PMC8",
6978                      SPR_NOACCESS, SPR_NOACCESS,
6979                      &spr_read_generic, &spr_write_generic,
6980                      KVM_REG_PPC_PMC8, 0x00000000);
6981 }
6982 
6983 static void register_970_pmu_user_sprs(CPUPPCState *env)
6984 {
6985     spr_register(env, SPR_970_UPMC7, "UPMC7",
6986                  &spr_read_ureg, SPR_NOACCESS,
6987                  &spr_read_ureg, &spr_write_ureg,
6988                  0x00000000);
6989     spr_register(env, SPR_970_UPMC8, "UPMC8",
6990                  &spr_read_ureg, SPR_NOACCESS,
6991                  &spr_read_ureg, &spr_write_ureg,
6992                  0x00000000);
6993 }
6994 
6995 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
6996 {
6997     spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
6998                      SPR_NOACCESS, SPR_NOACCESS,
6999                      &spr_read_generic, &spr_write_generic,
7000                      KVM_REG_PPC_MMCR2, 0x00000000);
7001     spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7002                      SPR_NOACCESS, SPR_NOACCESS,
7003                      &spr_read_generic, &spr_write_generic,
7004                      KVM_REG_PPC_MMCRS, 0x00000000);
7005     spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7006                      SPR_NOACCESS, SPR_NOACCESS,
7007                      &spr_read_generic, &spr_write_generic,
7008                      KVM_REG_PPC_SIER, 0x00000000);
7009     spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7010                      SPR_NOACCESS, SPR_NOACCESS,
7011                      &spr_read_generic, &spr_write_generic,
7012                      KVM_REG_PPC_SPMC1, 0x00000000);
7013     spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7014                      SPR_NOACCESS, SPR_NOACCESS,
7015                      &spr_read_generic, &spr_write_generic,
7016                      KVM_REG_PPC_SPMC2, 0x00000000);
7017     spr_register_kvm(env, SPR_TACR, "TACR",
7018                      SPR_NOACCESS, SPR_NOACCESS,
7019                      &spr_read_generic, &spr_write_generic,
7020                      KVM_REG_PPC_TACR, 0x00000000);
7021     spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7022                      SPR_NOACCESS, SPR_NOACCESS,
7023                      &spr_read_generic, &spr_write_generic,
7024                      KVM_REG_PPC_TCSCR, 0x00000000);
7025     spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7026                      SPR_NOACCESS, SPR_NOACCESS,
7027                      &spr_read_generic, &spr_write_generic,
7028                      KVM_REG_PPC_CSIGR, 0x00000000);
7029 }
7030 
7031 static void register_power8_pmu_user_sprs(CPUPPCState *env)
7032 {
7033     spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7034                  &spr_read_ureg, SPR_NOACCESS,
7035                  &spr_read_ureg, &spr_write_ureg,
7036                  0x00000000);
7037     spr_register(env, SPR_POWER_USIER, "USIER",
7038                  &spr_read_generic, SPR_NOACCESS,
7039                  &spr_read_generic, &spr_write_generic,
7040                  0x00000000);
7041 }
7042 
7043 static void register_power5p_ear_sprs(CPUPPCState *env)
7044 {
7045     /* External access control */
7046     spr_register(env, SPR_EAR, "EAR",
7047                  SPR_NOACCESS, SPR_NOACCESS,
7048                  &spr_read_generic, &spr_write_generic,
7049                  0x00000000);
7050 }
7051 
7052 static void register_power5p_tb_sprs(CPUPPCState *env)
7053 {
7054     /* TBU40 (High 40 bits of the Timebase register */
7055     spr_register_hv(env, SPR_TBU40, "TBU40",
7056                     SPR_NOACCESS, SPR_NOACCESS,
7057                     SPR_NOACCESS, SPR_NOACCESS,
7058                     SPR_NOACCESS, &spr_write_tbu40,
7059                     0x00000000);
7060 }
7061 
7062 static void register_970_lpar_sprs(CPUPPCState *env)
7063 {
7064 #if !defined(CONFIG_USER_ONLY)
7065     /*
7066      * PPC970: HID4 covers things later controlled by the LPCR and
7067      * RMOR in later CPUs, but with a different encoding.  We only
7068      * support the 970 in "Apple mode" which has all hypervisor
7069      * facilities disabled by strapping, so we can basically just
7070      * ignore it
7071      */
7072     spr_register(env, SPR_970_HID4, "HID4",
7073                  SPR_NOACCESS, SPR_NOACCESS,
7074                  &spr_read_generic, &spr_write_generic,
7075                  0x00000000);
7076 #endif
7077 }
7078 
7079 static void register_power5p_lpar_sprs(CPUPPCState *env)
7080 {
7081 #if !defined(CONFIG_USER_ONLY)
7082     /* Logical partitionning */
7083     spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7084                         SPR_NOACCESS, SPR_NOACCESS,
7085                         SPR_NOACCESS, SPR_NOACCESS,
7086                         &spr_read_generic, &spr_write_lpcr,
7087                         KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7088     spr_register_hv(env, SPR_HDEC, "HDEC",
7089                     SPR_NOACCESS, SPR_NOACCESS,
7090                     SPR_NOACCESS, SPR_NOACCESS,
7091                     &spr_read_hdecr, &spr_write_hdecr, 0);
7092 #endif
7093 }
7094 
7095 static void register_book3s_ids_sprs(CPUPPCState *env)
7096 {
7097     /* FIXME: Will need to deal with thread vs core only SPRs */
7098 
7099     /* Processor identification */
7100     spr_register_hv(env, SPR_PIR, "PIR",
7101                  SPR_NOACCESS, SPR_NOACCESS,
7102                  &spr_read_generic, SPR_NOACCESS,
7103                  &spr_read_generic, NULL,
7104                  0x00000000);
7105     spr_register_hv(env, SPR_HID0, "HID0",
7106                  SPR_NOACCESS, SPR_NOACCESS,
7107                  SPR_NOACCESS, SPR_NOACCESS,
7108                  &spr_read_generic, &spr_write_generic,
7109                  0x00000000);
7110     spr_register_hv(env, SPR_TSCR, "TSCR",
7111                  SPR_NOACCESS, SPR_NOACCESS,
7112                  SPR_NOACCESS, SPR_NOACCESS,
7113                  &spr_read_generic, &spr_write_generic,
7114                  0x00000000);
7115     spr_register_hv(env, SPR_HMER, "HMER",
7116                  SPR_NOACCESS, SPR_NOACCESS,
7117                  SPR_NOACCESS, SPR_NOACCESS,
7118                  &spr_read_generic, &spr_write_hmer,
7119                  0x00000000);
7120     spr_register_hv(env, SPR_HMEER, "HMEER",
7121                  SPR_NOACCESS, SPR_NOACCESS,
7122                  SPR_NOACCESS, SPR_NOACCESS,
7123                  &spr_read_generic, &spr_write_generic,
7124                  0x00000000);
7125     spr_register_hv(env, SPR_TFMR, "TFMR",
7126                  SPR_NOACCESS, SPR_NOACCESS,
7127                  SPR_NOACCESS, SPR_NOACCESS,
7128                  &spr_read_generic, &spr_write_generic,
7129                  0x00000000);
7130     spr_register_hv(env, SPR_LPIDR, "LPIDR",
7131                  SPR_NOACCESS, SPR_NOACCESS,
7132                  SPR_NOACCESS, SPR_NOACCESS,
7133                  &spr_read_generic, &spr_write_lpidr,
7134                  0x00000000);
7135     spr_register_hv(env, SPR_HFSCR, "HFSCR",
7136                  SPR_NOACCESS, SPR_NOACCESS,
7137                  SPR_NOACCESS, SPR_NOACCESS,
7138                  &spr_read_generic, &spr_write_generic,
7139                  0x00000000);
7140     spr_register_hv(env, SPR_MMCRC, "MMCRC",
7141                  SPR_NOACCESS, SPR_NOACCESS,
7142                  SPR_NOACCESS, SPR_NOACCESS,
7143                  &spr_read_generic, &spr_write_generic,
7144                  0x00000000);
7145     spr_register_hv(env, SPR_MMCRH, "MMCRH",
7146                  SPR_NOACCESS, SPR_NOACCESS,
7147                  SPR_NOACCESS, SPR_NOACCESS,
7148                  &spr_read_generic, &spr_write_generic,
7149                  0x00000000);
7150     spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7151                  SPR_NOACCESS, SPR_NOACCESS,
7152                  SPR_NOACCESS, SPR_NOACCESS,
7153                  &spr_read_generic, &spr_write_generic,
7154                  0x00000000);
7155     spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7156                  SPR_NOACCESS, SPR_NOACCESS,
7157                  SPR_NOACCESS, SPR_NOACCESS,
7158                  &spr_read_generic, &spr_write_generic,
7159                  0x00000000);
7160     spr_register_hv(env, SPR_HSRR0, "HSRR0",
7161                  SPR_NOACCESS, SPR_NOACCESS,
7162                  SPR_NOACCESS, SPR_NOACCESS,
7163                  &spr_read_generic, &spr_write_generic,
7164                  0x00000000);
7165     spr_register_hv(env, SPR_HSRR1, "HSRR1",
7166                  SPR_NOACCESS, SPR_NOACCESS,
7167                  SPR_NOACCESS, SPR_NOACCESS,
7168                  &spr_read_generic, &spr_write_generic,
7169                  0x00000000);
7170     spr_register_hv(env, SPR_HDAR, "HDAR",
7171                  SPR_NOACCESS, SPR_NOACCESS,
7172                  SPR_NOACCESS, SPR_NOACCESS,
7173                  &spr_read_generic, &spr_write_generic,
7174                  0x00000000);
7175     spr_register_hv(env, SPR_HDSISR, "HDSISR",
7176                  SPR_NOACCESS, SPR_NOACCESS,
7177                  SPR_NOACCESS, SPR_NOACCESS,
7178                  &spr_read_generic, &spr_write_generic,
7179                  0x00000000);
7180     spr_register_hv(env, SPR_HRMOR, "HRMOR",
7181                  SPR_NOACCESS, SPR_NOACCESS,
7182                  SPR_NOACCESS, SPR_NOACCESS,
7183                  &spr_read_generic, &spr_write_generic,
7184                  0x00000000);
7185 }
7186 
7187 static void register_rmor_sprs(CPUPPCState *env)
7188 {
7189     spr_register_hv(env, SPR_RMOR, "RMOR",
7190                  SPR_NOACCESS, SPR_NOACCESS,
7191                  SPR_NOACCESS, SPR_NOACCESS,
7192                  &spr_read_generic, &spr_write_generic,
7193                  0x00000000);
7194 }
7195 
7196 static void register_power8_ids_sprs(CPUPPCState *env)
7197 {
7198     /* Thread identification */
7199     spr_register(env, SPR_TIR, "TIR",
7200                  SPR_NOACCESS, SPR_NOACCESS,
7201                  &spr_read_generic, SPR_NOACCESS,
7202                  0x00000000);
7203 }
7204 
7205 static void register_book3s_purr_sprs(CPUPPCState *env)
7206 {
7207 #if !defined(CONFIG_USER_ONLY)
7208     /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7209     spr_register_kvm_hv(env, SPR_PURR,   "PURR",
7210                         &spr_read_purr, SPR_NOACCESS,
7211                         &spr_read_purr, SPR_NOACCESS,
7212                         &spr_read_purr, &spr_write_purr,
7213                         KVM_REG_PPC_PURR, 0x00000000);
7214     spr_register_kvm_hv(env, SPR_SPURR,   "SPURR",
7215                         &spr_read_purr, SPR_NOACCESS,
7216                         &spr_read_purr, SPR_NOACCESS,
7217                         &spr_read_purr, &spr_write_purr,
7218                         KVM_REG_PPC_SPURR, 0x00000000);
7219 #endif
7220 }
7221 
7222 static void register_power6_dbg_sprs(CPUPPCState *env)
7223 {
7224 #if !defined(CONFIG_USER_ONLY)
7225     spr_register(env, SPR_CFAR, "SPR_CFAR",
7226                  SPR_NOACCESS, SPR_NOACCESS,
7227                  &spr_read_cfar, &spr_write_cfar,
7228                  0x00000000);
7229 #endif
7230 }
7231 
7232 static void register_power5p_common_sprs(CPUPPCState *env)
7233 {
7234     spr_register_kvm(env, SPR_PPR, "PPR",
7235                      &spr_read_generic, &spr_write_generic,
7236                      &spr_read_generic, &spr_write_generic,
7237                      KVM_REG_PPC_PPR, 0x00000000);
7238 }
7239 
7240 static void register_power6_common_sprs(CPUPPCState *env)
7241 {
7242 #if !defined(CONFIG_USER_ONLY)
7243     spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7244                      SPR_NOACCESS, SPR_NOACCESS,
7245                      &spr_read_generic, &spr_write_generic,
7246                      KVM_REG_PPC_DSCR, 0x00000000);
7247 #endif
7248     /*
7249      * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7250      * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
7251      */
7252     spr_register_hv(env, SPR_PCR, "PCR",
7253                  SPR_NOACCESS, SPR_NOACCESS,
7254                  SPR_NOACCESS, SPR_NOACCESS,
7255                  &spr_read_generic, &spr_write_pcr,
7256                  0x00000000);
7257 }
7258 
7259 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
7260 {
7261     spr_register_kvm(env, SPR_TAR, "TAR",
7262                      &spr_read_tar, &spr_write_tar,
7263                      &spr_read_generic, &spr_write_generic,
7264                      KVM_REG_PPC_TAR, 0x00000000);
7265 }
7266 
7267 static void register_power8_tm_sprs(CPUPPCState *env)
7268 {
7269     spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7270                      &spr_read_tm, &spr_write_tm,
7271                      &spr_read_tm, &spr_write_tm,
7272                      KVM_REG_PPC_TFHAR, 0x00000000);
7273     spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7274                      &spr_read_tm, &spr_write_tm,
7275                      &spr_read_tm, &spr_write_tm,
7276                      KVM_REG_PPC_TFIAR, 0x00000000);
7277     spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7278                      &spr_read_tm, &spr_write_tm,
7279                      &spr_read_tm, &spr_write_tm,
7280                      KVM_REG_PPC_TEXASR, 0x00000000);
7281     spr_register(env, SPR_TEXASRU, "TEXASRU",
7282                  &spr_read_tm_upper32, &spr_write_tm_upper32,
7283                  &spr_read_tm_upper32, &spr_write_tm_upper32,
7284                  0x00000000);
7285 }
7286 
7287 static void register_power8_ebb_sprs(CPUPPCState *env)
7288 {
7289     spr_register(env, SPR_BESCRS, "BESCRS",
7290                  &spr_read_ebb, &spr_write_ebb,
7291                  &spr_read_generic, &spr_write_generic,
7292                  0x00000000);
7293     spr_register(env, SPR_BESCRSU, "BESCRSU",
7294                  &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7295                  &spr_read_prev_upper32, &spr_write_prev_upper32,
7296                  0x00000000);
7297     spr_register(env, SPR_BESCRR, "BESCRR",
7298                  &spr_read_ebb, &spr_write_ebb,
7299                  &spr_read_generic, &spr_write_generic,
7300                  0x00000000);
7301     spr_register(env, SPR_BESCRRU, "BESCRRU",
7302                  &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7303                  &spr_read_prev_upper32, &spr_write_prev_upper32,
7304                  0x00000000);
7305     spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7306                      &spr_read_ebb, &spr_write_ebb,
7307                      &spr_read_generic, &spr_write_generic,
7308                      KVM_REG_PPC_EBBHR, 0x00000000);
7309     spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7310                      &spr_read_ebb, &spr_write_ebb,
7311                      &spr_read_generic, &spr_write_generic,
7312                      KVM_REG_PPC_EBBRR, 0x00000000);
7313     spr_register_kvm(env, SPR_BESCR, "BESCR",
7314                      &spr_read_ebb, &spr_write_ebb,
7315                      &spr_read_generic, &spr_write_generic,
7316                      KVM_REG_PPC_BESCR, 0x00000000);
7317 }
7318 
7319 /* Virtual Time Base */
7320 static void register_vtb_sprs(CPUPPCState *env)
7321 {
7322     spr_register_kvm_hv(env, SPR_VTB, "VTB",
7323                         SPR_NOACCESS, SPR_NOACCESS,
7324                         &spr_read_vtb, SPR_NOACCESS,
7325                         &spr_read_vtb, &spr_write_vtb,
7326                         KVM_REG_PPC_VTB, 0x00000000);
7327 }
7328 
7329 static void register_power8_fscr_sprs(CPUPPCState *env)
7330 {
7331 #if defined(CONFIG_USER_ONLY)
7332     target_ulong initval = 1ULL << FSCR_TAR;
7333 #else
7334     target_ulong initval = 0;
7335 #endif
7336     spr_register_kvm(env, SPR_FSCR, "FSCR",
7337                      SPR_NOACCESS, SPR_NOACCESS,
7338                      &spr_read_generic, &spr_write_generic,
7339                      KVM_REG_PPC_FSCR, initval);
7340 }
7341 
7342 static void register_power8_pspb_sprs(CPUPPCState *env)
7343 {
7344     spr_register_kvm(env, SPR_PSPB, "PSPB",
7345                      SPR_NOACCESS, SPR_NOACCESS,
7346                      &spr_read_generic, &spr_write_generic32,
7347                      KVM_REG_PPC_PSPB, 0);
7348 }
7349 
7350 static void register_power8_dpdes_sprs(CPUPPCState *env)
7351 {
7352 #if !defined(CONFIG_USER_ONLY)
7353     /* Directed Privileged Door-bell Exception State, used for IPI */
7354     spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
7355                         SPR_NOACCESS, SPR_NOACCESS,
7356                         &spr_read_dpdes, SPR_NOACCESS,
7357                         &spr_read_dpdes, &spr_write_dpdes,
7358                         KVM_REG_PPC_DPDES, 0x00000000);
7359 #endif
7360 }
7361 
7362 static void register_power8_ic_sprs(CPUPPCState *env)
7363 {
7364 #if !defined(CONFIG_USER_ONLY)
7365     spr_register_hv(env, SPR_IC, "IC",
7366                     SPR_NOACCESS, SPR_NOACCESS,
7367                     &spr_read_generic, SPR_NOACCESS,
7368                     &spr_read_generic, &spr_write_generic,
7369                     0);
7370 #endif
7371 }
7372 
7373 static void register_power8_book4_sprs(CPUPPCState *env)
7374 {
7375     /* Add a number of P8 book4 registers */
7376 #if !defined(CONFIG_USER_ONLY)
7377     spr_register_kvm(env, SPR_ACOP, "ACOP",
7378                      SPR_NOACCESS, SPR_NOACCESS,
7379                      &spr_read_generic, &spr_write_generic,
7380                      KVM_REG_PPC_ACOP, 0);
7381     spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7382                      SPR_NOACCESS, SPR_NOACCESS,
7383                      &spr_read_generic, &spr_write_pidr,
7384                      KVM_REG_PPC_PID, 0);
7385     spr_register_kvm(env, SPR_WORT, "WORT",
7386                      SPR_NOACCESS, SPR_NOACCESS,
7387                      &spr_read_generic, &spr_write_generic,
7388                      KVM_REG_PPC_WORT, 0);
7389 #endif
7390 }
7391 
7392 static void register_power7_book4_sprs(CPUPPCState *env)
7393 {
7394     /* Add a number of P7 book4 registers */
7395 #if !defined(CONFIG_USER_ONLY)
7396     spr_register_kvm(env, SPR_ACOP, "ACOP",
7397                      SPR_NOACCESS, SPR_NOACCESS,
7398                      &spr_read_generic, &spr_write_generic,
7399                      KVM_REG_PPC_ACOP, 0);
7400     spr_register_kvm(env, SPR_BOOKS_PID, "PID",
7401                      SPR_NOACCESS, SPR_NOACCESS,
7402                      &spr_read_generic, &spr_write_generic,
7403                      KVM_REG_PPC_PID, 0);
7404 #endif
7405 }
7406 
7407 static void register_power8_rpr_sprs(CPUPPCState *env)
7408 {
7409 #if !defined(CONFIG_USER_ONLY)
7410     spr_register_hv(env, SPR_RPR, "RPR",
7411                     SPR_NOACCESS, SPR_NOACCESS,
7412                     SPR_NOACCESS, SPR_NOACCESS,
7413                     &spr_read_generic, &spr_write_generic,
7414                     0x00000103070F1F3F);
7415 #endif
7416 }
7417 
7418 static void register_power9_mmu_sprs(CPUPPCState *env)
7419 {
7420 #if !defined(CONFIG_USER_ONLY)
7421     /* Partition Table Control */
7422     spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
7423                         SPR_NOACCESS, SPR_NOACCESS,
7424                         SPR_NOACCESS, SPR_NOACCESS,
7425                         &spr_read_generic, &spr_write_ptcr,
7426                         KVM_REG_PPC_PTCR, 0x00000000);
7427     /* Address Segment Descriptor Register */
7428     spr_register_hv(env, SPR_ASDR, "ASDR",
7429                     SPR_NOACCESS, SPR_NOACCESS,
7430                     SPR_NOACCESS, SPR_NOACCESS,
7431                     &spr_read_generic, &spr_write_generic,
7432                     0x0000000000000000);
7433 #endif
7434 }
7435 
7436 static void init_proc_book3s_common(CPUPPCState *env)
7437 {
7438     register_ne_601_sprs(env);
7439     register_tbl(env);
7440     register_usprg3_sprs(env);
7441     register_book3s_altivec_sprs(env);
7442     register_book3s_pmu_sup_sprs(env);
7443     register_book3s_pmu_user_sprs(env);
7444     register_book3s_ctrl_sprs(env);
7445     /*
7446      * Can't find information on what this should be on reset.  This
7447      * value is the one used by 74xx processors.
7448      */
7449     vscr_init(env, 0x00010000);
7450 }
7451 
7452 static void init_proc_970(CPUPPCState *env)
7453 {
7454     /* Common Registers */
7455     init_proc_book3s_common(env);
7456     register_sdr1_sprs(env);
7457     register_book3s_dbg_sprs(env);
7458 
7459     /* 970 Specific Registers */
7460     register_970_hid_sprs(env);
7461     register_970_hior_sprs(env);
7462     register_low_BATs(env);
7463     register_970_pmu_sup_sprs(env);
7464     register_970_pmu_user_sprs(env);
7465     register_970_lpar_sprs(env);
7466     register_970_dbg_sprs(env);
7467 
7468     /* env variables */
7469     env->dcache_line_size = 128;
7470     env->icache_line_size = 128;
7471 
7472     /* Allocate hardware IRQ controller */
7473     init_excp_970(env);
7474     ppc970_irq_init(env_archcpu(env));
7475 }
7476 
7477 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7478 {
7479     DeviceClass *dc = DEVICE_CLASS(oc);
7480     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7481 
7482     dc->desc = "PowerPC 970";
7483     pcc->init_proc = init_proc_970;
7484     pcc->check_pow = check_pow_970;
7485     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7486                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7487                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7488                        PPC_FLOAT_STFIWX |
7489                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7490                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
7491                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7492                        PPC_64B | PPC_ALTIVEC |
7493                        PPC_SEGMENT_64B | PPC_SLBI;
7494     pcc->insns_flags2 = PPC2_FP_CVT_S64;
7495     pcc->msr_mask = (1ull << MSR_SF) |
7496                     (1ull << MSR_VR) |
7497                     (1ull << MSR_POW) |
7498                     (1ull << MSR_EE) |
7499                     (1ull << MSR_PR) |
7500                     (1ull << MSR_FP) |
7501                     (1ull << MSR_ME) |
7502                     (1ull << MSR_FE0) |
7503                     (1ull << MSR_SE) |
7504                     (1ull << MSR_DE) |
7505                     (1ull << MSR_FE1) |
7506                     (1ull << MSR_IR) |
7507                     (1ull << MSR_DR) |
7508                     (1ull << MSR_PMM) |
7509                     (1ull << MSR_RI);
7510     pcc->mmu_model = POWERPC_MMU_64B;
7511 #if defined(CONFIG_SOFTMMU)
7512     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7513     pcc->hash64_opts = &ppc_hash64_opts_basic;
7514 #endif
7515     pcc->excp_model = POWERPC_EXCP_970;
7516     pcc->bus_model = PPC_FLAGS_INPUT_970;
7517     pcc->bfd_mach = bfd_mach_ppc64;
7518     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7519                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7520                  POWERPC_FLAG_BUS_CLK;
7521     pcc->l1_dcache_size = 0x8000;
7522     pcc->l1_icache_size = 0x10000;
7523 }
7524 
7525 static void init_proc_power5plus(CPUPPCState *env)
7526 {
7527     /* Common Registers */
7528     init_proc_book3s_common(env);
7529     register_sdr1_sprs(env);
7530     register_book3s_dbg_sprs(env);
7531 
7532     /* POWER5+ Specific Registers */
7533     register_970_hid_sprs(env);
7534     register_970_hior_sprs(env);
7535     register_low_BATs(env);
7536     register_970_pmu_sup_sprs(env);
7537     register_970_pmu_user_sprs(env);
7538     register_power5p_common_sprs(env);
7539     register_power5p_lpar_sprs(env);
7540     register_power5p_ear_sprs(env);
7541     register_power5p_tb_sprs(env);
7542 
7543     /* env variables */
7544     env->dcache_line_size = 128;
7545     env->icache_line_size = 128;
7546 
7547     /* Allocate hardware IRQ controller */
7548     init_excp_970(env);
7549     ppc970_irq_init(env_archcpu(env));
7550 }
7551 
7552 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7553 {
7554     DeviceClass *dc = DEVICE_CLASS(oc);
7555     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7556 
7557     dc->fw_name = "PowerPC,POWER5";
7558     dc->desc = "POWER5+";
7559     pcc->init_proc = init_proc_power5plus;
7560     pcc->check_pow = check_pow_970;
7561     pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7562                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7563                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7564                        PPC_FLOAT_STFIWX |
7565                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7566                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
7567                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7568                        PPC_64B |
7569                        PPC_SEGMENT_64B | PPC_SLBI;
7570     pcc->insns_flags2 = PPC2_FP_CVT_S64;
7571     pcc->msr_mask = (1ull << MSR_SF) |
7572                     (1ull << MSR_VR) |
7573                     (1ull << MSR_POW) |
7574                     (1ull << MSR_EE) |
7575                     (1ull << MSR_PR) |
7576                     (1ull << MSR_FP) |
7577                     (1ull << MSR_ME) |
7578                     (1ull << MSR_FE0) |
7579                     (1ull << MSR_SE) |
7580                     (1ull << MSR_DE) |
7581                     (1ull << MSR_FE1) |
7582                     (1ull << MSR_IR) |
7583                     (1ull << MSR_DR) |
7584                     (1ull << MSR_PMM) |
7585                     (1ull << MSR_RI);
7586     pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
7587         LPCR_RMI | LPCR_HDICE;
7588     pcc->mmu_model = POWERPC_MMU_2_03;
7589 #if defined(CONFIG_SOFTMMU)
7590     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7591     pcc->hash64_opts = &ppc_hash64_opts_basic;
7592     pcc->lrg_decr_bits = 32;
7593 #endif
7594     pcc->excp_model = POWERPC_EXCP_970;
7595     pcc->bus_model = PPC_FLAGS_INPUT_970;
7596     pcc->bfd_mach = bfd_mach_ppc64;
7597     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7598                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7599                  POWERPC_FLAG_BUS_CLK;
7600     pcc->l1_dcache_size = 0x8000;
7601     pcc->l1_icache_size = 0x10000;
7602 }
7603 
7604 static void init_proc_POWER7(CPUPPCState *env)
7605 {
7606     /* Common Registers */
7607     init_proc_book3s_common(env);
7608     register_sdr1_sprs(env);
7609     register_book3s_dbg_sprs(env);
7610 
7611     /* POWER7 Specific Registers */
7612     register_book3s_ids_sprs(env);
7613     register_rmor_sprs(env);
7614     register_amr_sprs(env);
7615     register_book3s_purr_sprs(env);
7616     register_power5p_common_sprs(env);
7617     register_power5p_lpar_sprs(env);
7618     register_power5p_ear_sprs(env);
7619     register_power5p_tb_sprs(env);
7620     register_power6_common_sprs(env);
7621     register_power6_dbg_sprs(env);
7622     register_power7_book4_sprs(env);
7623 
7624     /* env variables */
7625     env->dcache_line_size = 128;
7626     env->icache_line_size = 128;
7627 
7628     /* Allocate hardware IRQ controller */
7629     init_excp_POWER7(env);
7630     ppcPOWER7_irq_init(env_archcpu(env));
7631 }
7632 
7633 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
7634 {
7635     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
7636         return true;
7637     }
7638     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
7639         return true;
7640     }
7641     return false;
7642 }
7643 
7644 static bool cpu_has_work_POWER7(CPUState *cs)
7645 {
7646     PowerPCCPU *cpu = POWERPC_CPU(cs);
7647     CPUPPCState *env = &cpu->env;
7648 
7649     if (cs->halted) {
7650         if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7651             return false;
7652         }
7653         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7654             (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
7655             return true;
7656         }
7657         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7658             (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
7659             return true;
7660         }
7661         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7662             (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7663             return true;
7664         }
7665         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7666             (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7667             return true;
7668         }
7669         if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7670             return true;
7671         }
7672         return false;
7673     } else {
7674         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7675     }
7676 }
7677 
7678 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7679 {
7680     DeviceClass *dc = DEVICE_CLASS(oc);
7681     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7682     CPUClass *cc = CPU_CLASS(oc);
7683 
7684     dc->fw_name = "PowerPC,POWER7";
7685     dc->desc = "POWER7";
7686     pcc->pvr_match = ppc_pvr_match_power7;
7687     pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
7688     pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7689     pcc->init_proc = init_proc_POWER7;
7690     pcc->check_pow = check_pow_nocheck;
7691     cc->has_work = cpu_has_work_POWER7;
7692     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7693                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7694                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7695                        PPC_FLOAT_FRSQRTES |
7696                        PPC_FLOAT_STFIWX |
7697                        PPC_FLOAT_EXT |
7698                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7699                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
7700                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7701                        PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7702                        PPC_SEGMENT_64B | PPC_SLBI |
7703                        PPC_POPCNTB | PPC_POPCNTWD |
7704                        PPC_CILDST;
7705     pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7706                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7707                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7708                         PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
7709                         PPC2_PM_ISA206;
7710     pcc->msr_mask = (1ull << MSR_SF) |
7711                     (1ull << MSR_VR) |
7712                     (1ull << MSR_VSX) |
7713                     (1ull << MSR_EE) |
7714                     (1ull << MSR_PR) |
7715                     (1ull << MSR_FP) |
7716                     (1ull << MSR_ME) |
7717                     (1ull << MSR_FE0) |
7718                     (1ull << MSR_SE) |
7719                     (1ull << MSR_DE) |
7720                     (1ull << MSR_FE1) |
7721                     (1ull << MSR_IR) |
7722                     (1ull << MSR_DR) |
7723                     (1ull << MSR_PMM) |
7724                     (1ull << MSR_RI) |
7725                     (1ull << MSR_LE);
7726     pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
7727         LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7728         LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
7729         LPCR_MER | LPCR_TC |
7730         LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
7731     pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
7732     pcc->mmu_model = POWERPC_MMU_2_06;
7733 #if defined(CONFIG_SOFTMMU)
7734     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7735     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7736     pcc->lrg_decr_bits = 32;
7737 #endif
7738     pcc->excp_model = POWERPC_EXCP_POWER7;
7739     pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7740     pcc->bfd_mach = bfd_mach_ppc64;
7741     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7742                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7743                  POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7744                  POWERPC_FLAG_VSX;
7745     pcc->l1_dcache_size = 0x8000;
7746     pcc->l1_icache_size = 0x8000;
7747     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7748 }
7749 
7750 static void init_proc_POWER8(CPUPPCState *env)
7751 {
7752     /* Common Registers */
7753     init_proc_book3s_common(env);
7754     register_sdr1_sprs(env);
7755     register_book3s_207_dbg_sprs(env);
7756 
7757     /* POWER8 Specific Registers */
7758     register_book3s_ids_sprs(env);
7759     register_rmor_sprs(env);
7760     register_amr_sprs(env);
7761     register_iamr_sprs(env);
7762     register_book3s_purr_sprs(env);
7763     register_power5p_common_sprs(env);
7764     register_power5p_lpar_sprs(env);
7765     register_power5p_ear_sprs(env);
7766     register_power5p_tb_sprs(env);
7767     register_power6_common_sprs(env);
7768     register_power6_dbg_sprs(env);
7769     register_power8_tce_address_control_sprs(env);
7770     register_power8_ids_sprs(env);
7771     register_power8_ebb_sprs(env);
7772     register_power8_fscr_sprs(env);
7773     register_power8_pmu_sup_sprs(env);
7774     register_power8_pmu_user_sprs(env);
7775     register_power8_tm_sprs(env);
7776     register_power8_pspb_sprs(env);
7777     register_power8_dpdes_sprs(env);
7778     register_vtb_sprs(env);
7779     register_power8_ic_sprs(env);
7780     register_power8_book4_sprs(env);
7781     register_power8_rpr_sprs(env);
7782 
7783     /* env variables */
7784     env->dcache_line_size = 128;
7785     env->icache_line_size = 128;
7786 
7787     /* Allocate hardware IRQ controller */
7788     init_excp_POWER8(env);
7789     ppcPOWER7_irq_init(env_archcpu(env));
7790 }
7791 
7792 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
7793 {
7794     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
7795         return true;
7796     }
7797     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
7798         return true;
7799     }
7800     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
7801         return true;
7802     }
7803     return false;
7804 }
7805 
7806 static bool cpu_has_work_POWER8(CPUState *cs)
7807 {
7808     PowerPCCPU *cpu = POWERPC_CPU(cs);
7809     CPUPPCState *env = &cpu->env;
7810 
7811     if (cs->halted) {
7812         if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7813             return false;
7814         }
7815         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7816             (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
7817             return true;
7818         }
7819         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7820             (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
7821             return true;
7822         }
7823         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7824             (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7825             return true;
7826         }
7827         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7828             (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7829             return true;
7830         }
7831         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7832             (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
7833             return true;
7834         }
7835         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7836             (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
7837             return true;
7838         }
7839         if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7840             return true;
7841         }
7842         return false;
7843     } else {
7844         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7845     }
7846 }
7847 
7848 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7849 {
7850     DeviceClass *dc = DEVICE_CLASS(oc);
7851     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7852     CPUClass *cc = CPU_CLASS(oc);
7853 
7854     dc->fw_name = "PowerPC,POWER8";
7855     dc->desc = "POWER8";
7856     pcc->pvr_match = ppc_pvr_match_power8;
7857     pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7858     pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7859     pcc->init_proc = init_proc_POWER8;
7860     pcc->check_pow = check_pow_nocheck;
7861     cc->has_work = cpu_has_work_POWER8;
7862     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7863                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7864                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7865                        PPC_FLOAT_FRSQRTES |
7866                        PPC_FLOAT_STFIWX |
7867                        PPC_FLOAT_EXT |
7868                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7869                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
7870                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7871                        PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7872                        PPC_SEGMENT_64B | PPC_SLBI |
7873                        PPC_POPCNTB | PPC_POPCNTWD |
7874                        PPC_CILDST;
7875     pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7876                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7877                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7878                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7879                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7880                         PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7881                         PPC2_TM | PPC2_PM_ISA206;
7882     pcc->msr_mask = (1ull << MSR_SF) |
7883                     (1ull << MSR_HV) |
7884                     (1ull << MSR_TM) |
7885                     (1ull << MSR_VR) |
7886                     (1ull << MSR_VSX) |
7887                     (1ull << MSR_EE) |
7888                     (1ull << MSR_PR) |
7889                     (1ull << MSR_FP) |
7890                     (1ull << MSR_ME) |
7891                     (1ull << MSR_FE0) |
7892                     (1ull << MSR_SE) |
7893                     (1ull << MSR_DE) |
7894                     (1ull << MSR_FE1) |
7895                     (1ull << MSR_IR) |
7896                     (1ull << MSR_DR) |
7897                     (1ull << MSR_PMM) |
7898                     (1ull << MSR_RI) |
7899                     (1ull << MSR_TS0) |
7900                     (1ull << MSR_TS1) |
7901                     (1ull << MSR_LE);
7902     pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
7903         LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7904         LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
7905         LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
7906         LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
7907     pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
7908                    LPCR_P8_PECE3 | LPCR_P8_PECE4;
7909     pcc->mmu_model = POWERPC_MMU_2_07;
7910 #if defined(CONFIG_SOFTMMU)
7911     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7912     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7913     pcc->lrg_decr_bits = 32;
7914     pcc->n_host_threads = 8;
7915 #endif
7916     pcc->excp_model = POWERPC_EXCP_POWER8;
7917     pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7918     pcc->bfd_mach = bfd_mach_ppc64;
7919     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7920                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7921                  POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7922                  POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
7923     pcc->l1_dcache_size = 0x8000;
7924     pcc->l1_icache_size = 0x8000;
7925     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7926 }
7927 
7928 #ifdef CONFIG_SOFTMMU
7929 /*
7930  * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7931  * Encoded as array of int_32s in the form:
7932  *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7933  *  x -> AP encoding
7934  *  y -> radix mode supported page size (encoded as a shift)
7935  */
7936 static struct ppc_radix_page_info POWER9_radix_page_info = {
7937     .count = 4,
7938     .entries = {
7939         0x0000000c, /*  4K - enc: 0x0 */
7940         0xa0000010, /* 64K - enc: 0x5 */
7941         0x20000015, /*  2M - enc: 0x1 */
7942         0x4000001e  /*  1G - enc: 0x2 */
7943     }
7944 };
7945 #endif /* CONFIG_SOFTMMU */
7946 
7947 static void init_proc_POWER9(CPUPPCState *env)
7948 {
7949     /* Common Registers */
7950     init_proc_book3s_common(env);
7951     register_book3s_207_dbg_sprs(env);
7952 
7953     /* POWER8 Specific Registers */
7954     register_book3s_ids_sprs(env);
7955     register_amr_sprs(env);
7956     register_iamr_sprs(env);
7957     register_book3s_purr_sprs(env);
7958     register_power5p_common_sprs(env);
7959     register_power5p_lpar_sprs(env);
7960     register_power5p_ear_sprs(env);
7961     register_power5p_tb_sprs(env);
7962     register_power6_common_sprs(env);
7963     register_power6_dbg_sprs(env);
7964     register_power8_tce_address_control_sprs(env);
7965     register_power8_ids_sprs(env);
7966     register_power8_ebb_sprs(env);
7967     register_power8_fscr_sprs(env);
7968     register_power8_pmu_sup_sprs(env);
7969     register_power8_pmu_user_sprs(env);
7970     register_power8_tm_sprs(env);
7971     register_power8_pspb_sprs(env);
7972     register_power8_dpdes_sprs(env);
7973     register_vtb_sprs(env);
7974     register_power8_ic_sprs(env);
7975     register_power8_book4_sprs(env);
7976     register_power8_rpr_sprs(env);
7977     register_power9_mmu_sprs(env);
7978 
7979     /* POWER9 Specific registers */
7980     spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
7981                      spr_read_generic, spr_write_generic,
7982                      KVM_REG_PPC_TIDR, 0);
7983 
7984     /* FIXME: Filter fields properly based on privilege level */
7985     spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7986                         spr_read_generic, spr_write_generic,
7987                         KVM_REG_PPC_PSSCR, 0);
7988 
7989     /* env variables */
7990     env->dcache_line_size = 128;
7991     env->icache_line_size = 128;
7992 
7993     /* Allocate hardware IRQ controller */
7994     init_excp_POWER9(env);
7995     ppcPOWER9_irq_init(env_archcpu(env));
7996 }
7997 
7998 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
7999 {
8000     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8001         return true;
8002     }
8003     return false;
8004 }
8005 
8006 static bool cpu_has_work_POWER9(CPUState *cs)
8007 {
8008     PowerPCCPU *cpu = POWERPC_CPU(cs);
8009     CPUPPCState *env = &cpu->env;
8010 
8011     if (cs->halted) {
8012         uint64_t psscr = env->spr[SPR_PSSCR];
8013 
8014         if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8015             return false;
8016         }
8017 
8018         /* If EC is clear, just return true on any pending interrupt */
8019         if (!(psscr & PSSCR_EC)) {
8020             return true;
8021         }
8022         /* External Exception */
8023         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8024             (env->spr[SPR_LPCR] & LPCR_EEE)) {
8025             bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8026             if (heic == 0 || !msr_hv || msr_pr) {
8027                 return true;
8028             }
8029         }
8030         /* Decrementer Exception */
8031         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8032             (env->spr[SPR_LPCR] & LPCR_DEE)) {
8033             return true;
8034         }
8035         /* Machine Check or Hypervisor Maintenance Exception */
8036         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8037             1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8038             return true;
8039         }
8040         /* Privileged Doorbell Exception */
8041         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8042             (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8043             return true;
8044         }
8045         /* Hypervisor Doorbell Exception */
8046         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8047             (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8048             return true;
8049         }
8050         /* Hypervisor virtualization exception */
8051         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8052             (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8053             return true;
8054         }
8055         if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8056             return true;
8057         }
8058         return false;
8059     } else {
8060         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8061     }
8062 }
8063 
8064 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8065 {
8066     DeviceClass *dc = DEVICE_CLASS(oc);
8067     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8068     CPUClass *cc = CPU_CLASS(oc);
8069 
8070     dc->fw_name = "PowerPC,POWER9";
8071     dc->desc = "POWER9";
8072     pcc->pvr_match = ppc_pvr_match_power9;
8073     pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8074     pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8075                          PCR_COMPAT_2_05;
8076     pcc->init_proc = init_proc_POWER9;
8077     pcc->check_pow = check_pow_nocheck;
8078     cc->has_work = cpu_has_work_POWER9;
8079     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8080                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8081                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8082                        PPC_FLOAT_FRSQRTES |
8083                        PPC_FLOAT_STFIWX |
8084                        PPC_FLOAT_EXT |
8085                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8086                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
8087                        PPC_MEM_TLBSYNC |
8088                        PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8089                        PPC_SEGMENT_64B | PPC_SLBI |
8090                        PPC_POPCNTB | PPC_POPCNTWD |
8091                        PPC_CILDST;
8092     pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8093                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8094                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8095                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8096                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8097                         PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8098                         PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
8099     pcc->msr_mask = (1ull << MSR_SF) |
8100                     (1ull << MSR_HV) |
8101                     (1ull << MSR_TM) |
8102                     (1ull << MSR_VR) |
8103                     (1ull << MSR_VSX) |
8104                     (1ull << MSR_EE) |
8105                     (1ull << MSR_PR) |
8106                     (1ull << MSR_FP) |
8107                     (1ull << MSR_ME) |
8108                     (1ull << MSR_FE0) |
8109                     (1ull << MSR_SE) |
8110                     (1ull << MSR_DE) |
8111                     (1ull << MSR_FE1) |
8112                     (1ull << MSR_IR) |
8113                     (1ull << MSR_DR) |
8114                     (1ull << MSR_PMM) |
8115                     (1ull << MSR_RI) |
8116                     (1ull << MSR_LE);
8117     pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8118         (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8119         LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8120         (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8121                              LPCR_DEE | LPCR_OEE))
8122         | LPCR_MER | LPCR_GTSE | LPCR_TC |
8123         LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8124     pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8125     pcc->mmu_model = POWERPC_MMU_3_00;
8126 #if defined(CONFIG_SOFTMMU)
8127     pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8128     /* segment page size remain the same */
8129     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8130     pcc->radix_page_info = &POWER9_radix_page_info;
8131     pcc->lrg_decr_bits = 56;
8132     pcc->n_host_threads = 4;
8133 #endif
8134     pcc->excp_model = POWERPC_EXCP_POWER9;
8135     pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8136     pcc->bfd_mach = bfd_mach_ppc64;
8137     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8138                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8139                  POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8140                  POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8141     pcc->l1_dcache_size = 0x8000;
8142     pcc->l1_icache_size = 0x8000;
8143     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8144 }
8145 
8146 #ifdef CONFIG_SOFTMMU
8147 /*
8148  * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8149  * Encoded as array of int_32s in the form:
8150  *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8151  *  x -> AP encoding
8152  *  y -> radix mode supported page size (encoded as a shift)
8153  */
8154 static struct ppc_radix_page_info POWER10_radix_page_info = {
8155     .count = 4,
8156     .entries = {
8157         0x0000000c, /*  4K - enc: 0x0 */
8158         0xa0000010, /* 64K - enc: 0x5 */
8159         0x20000015, /*  2M - enc: 0x1 */
8160         0x4000001e  /*  1G - enc: 0x2 */
8161     }
8162 };
8163 #endif /* CONFIG_SOFTMMU */
8164 
8165 static void init_proc_POWER10(CPUPPCState *env)
8166 {
8167     /* Common Registers */
8168     init_proc_book3s_common(env);
8169     register_book3s_207_dbg_sprs(env);
8170 
8171     /* POWER8 Specific Registers */
8172     register_book3s_ids_sprs(env);
8173     register_amr_sprs(env);
8174     register_iamr_sprs(env);
8175     register_book3s_purr_sprs(env);
8176     register_power5p_common_sprs(env);
8177     register_power5p_lpar_sprs(env);
8178     register_power5p_ear_sprs(env);
8179     register_power6_common_sprs(env);
8180     register_power6_dbg_sprs(env);
8181     register_power8_tce_address_control_sprs(env);
8182     register_power8_ids_sprs(env);
8183     register_power8_ebb_sprs(env);
8184     register_power8_fscr_sprs(env);
8185     register_power8_pmu_sup_sprs(env);
8186     register_power8_pmu_user_sprs(env);
8187     register_power8_tm_sprs(env);
8188     register_power8_pspb_sprs(env);
8189     register_vtb_sprs(env);
8190     register_power8_ic_sprs(env);
8191     register_power8_book4_sprs(env);
8192     register_power8_rpr_sprs(env);
8193     register_power9_mmu_sprs(env);
8194 
8195     /* FIXME: Filter fields properly based on privilege level */
8196     spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8197                         spr_read_generic, spr_write_generic,
8198                         KVM_REG_PPC_PSSCR, 0);
8199 
8200     /* env variables */
8201     env->dcache_line_size = 128;
8202     env->icache_line_size = 128;
8203 
8204     /* Allocate hardware IRQ controller */
8205     init_excp_POWER10(env);
8206     ppcPOWER9_irq_init(env_archcpu(env));
8207 }
8208 
8209 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
8210 {
8211     if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
8212         return true;
8213     }
8214     return false;
8215 }
8216 
8217 static bool cpu_has_work_POWER10(CPUState *cs)
8218 {
8219     PowerPCCPU *cpu = POWERPC_CPU(cs);
8220     CPUPPCState *env = &cpu->env;
8221 
8222     if (cs->halted) {
8223         uint64_t psscr = env->spr[SPR_PSSCR];
8224 
8225         if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8226             return false;
8227         }
8228 
8229         /* If EC is clear, just return true on any pending interrupt */
8230         if (!(psscr & PSSCR_EC)) {
8231             return true;
8232         }
8233         /* External Exception */
8234         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8235             (env->spr[SPR_LPCR] & LPCR_EEE)) {
8236             bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
8237             if (heic == 0 || !msr_hv || msr_pr) {
8238                 return true;
8239             }
8240         }
8241         /* Decrementer Exception */
8242         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8243             (env->spr[SPR_LPCR] & LPCR_DEE)) {
8244             return true;
8245         }
8246         /* Machine Check or Hypervisor Maintenance Exception */
8247         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8248             1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8249             return true;
8250         }
8251         /* Privileged Doorbell Exception */
8252         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8253             (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8254             return true;
8255         }
8256         /* Hypervisor Doorbell Exception */
8257         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8258             (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8259             return true;
8260         }
8261         /* Hypervisor virtualization exception */
8262         if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
8263             (env->spr[SPR_LPCR] & LPCR_HVEE)) {
8264             return true;
8265         }
8266         if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8267             return true;
8268         }
8269         return false;
8270     } else {
8271         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8272     }
8273 }
8274 
8275 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
8276 {
8277     DeviceClass *dc = DEVICE_CLASS(oc);
8278     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8279     CPUClass *cc = CPU_CLASS(oc);
8280 
8281     dc->fw_name = "PowerPC,POWER10";
8282     dc->desc = "POWER10";
8283     pcc->pvr_match = ppc_pvr_match_power10;
8284     pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
8285                     PCR_COMPAT_3_00;
8286     pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
8287                          PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8288     pcc->init_proc = init_proc_POWER10;
8289     pcc->check_pow = check_pow_nocheck;
8290     cc->has_work = cpu_has_work_POWER10;
8291     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8292                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8293                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8294                        PPC_FLOAT_FRSQRTES |
8295                        PPC_FLOAT_STFIWX |
8296                        PPC_FLOAT_EXT |
8297                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8298                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
8299                        PPC_MEM_TLBSYNC |
8300                        PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8301                        PPC_SEGMENT_64B | PPC_SLBI |
8302                        PPC_POPCNTB | PPC_POPCNTWD |
8303                        PPC_CILDST;
8304     pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8305                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8306                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8307                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8308                         PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8309                         PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8310                         PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
8311     pcc->msr_mask = (1ull << MSR_SF) |
8312                     (1ull << MSR_HV) |
8313                     (1ull << MSR_TM) |
8314                     (1ull << MSR_VR) |
8315                     (1ull << MSR_VSX) |
8316                     (1ull << MSR_EE) |
8317                     (1ull << MSR_PR) |
8318                     (1ull << MSR_FP) |
8319                     (1ull << MSR_ME) |
8320                     (1ull << MSR_FE0) |
8321                     (1ull << MSR_SE) |
8322                     (1ull << MSR_DE) |
8323                     (1ull << MSR_FE1) |
8324                     (1ull << MSR_IR) |
8325                     (1ull << MSR_DR) |
8326                     (1ull << MSR_PMM) |
8327                     (1ull << MSR_RI) |
8328                     (1ull << MSR_LE);
8329     pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
8330         (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
8331         LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
8332         (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
8333                              LPCR_DEE | LPCR_OEE))
8334         | LPCR_MER | LPCR_GTSE | LPCR_TC |
8335         LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
8336     pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
8337     pcc->mmu_model = POWERPC_MMU_3_00;
8338 #if defined(CONFIG_SOFTMMU)
8339     pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8340     /* segment page size remain the same */
8341     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
8342     pcc->radix_page_info = &POWER10_radix_page_info;
8343     pcc->lrg_decr_bits = 56;
8344 #endif
8345     pcc->excp_model = POWERPC_EXCP_POWER10;
8346     pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8347     pcc->bfd_mach = bfd_mach_ppc64;
8348     pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8349                  POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8350                  POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8351                  POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8352     pcc->l1_dcache_size = 0x8000;
8353     pcc->l1_icache_size = 0x8000;
8354     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8355 }
8356 
8357 #if !defined(CONFIG_USER_ONLY)
8358 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8359 {
8360     CPUPPCState *env = &cpu->env;
8361 
8362     cpu->vhyp = vhyp;
8363 
8364     /*
8365      * With a virtual hypervisor mode we never allow the CPU to go
8366      * hypervisor mode itself
8367      */
8368     env->msr_mask &= ~MSR_HVB;
8369 }
8370 
8371 #endif /* !defined(CONFIG_USER_ONLY) */
8372 
8373 #endif /* defined(TARGET_PPC64) */
8374 
8375 /*****************************************************************************/
8376 /* Generic CPU instantiation routine                                         */
8377 static void init_ppc_proc(PowerPCCPU *cpu)
8378 {
8379     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8380     CPUPPCState *env = &cpu->env;
8381 #if !defined(CONFIG_USER_ONLY)
8382     int i;
8383 
8384     env->irq_inputs = NULL;
8385     /* Set all exception vectors to an invalid address */
8386     for (i = 0; i < POWERPC_EXCP_NB; i++) {
8387         env->excp_vectors[i] = (target_ulong)(-1ULL);
8388     }
8389     env->ivor_mask = 0x00000000;
8390     env->ivpr_mask = 0x00000000;
8391     /* Default MMU definitions */
8392     env->nb_BATs = 0;
8393     env->nb_tlb = 0;
8394     env->nb_ways = 0;
8395     env->tlb_type = TLB_NONE;
8396 #endif
8397     /* Register SPR common to all PowerPC implementations */
8398     register_generic_sprs(env);
8399     spr_register(env, SPR_PVR, "PVR",
8400                  /* Linux permits userspace to read PVR */
8401 #if defined(CONFIG_LINUX_USER)
8402                  &spr_read_generic,
8403 #else
8404                  SPR_NOACCESS,
8405 #endif
8406                  SPR_NOACCESS,
8407                  &spr_read_generic, SPR_NOACCESS,
8408                  pcc->pvr);
8409     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8410     if (pcc->svr != POWERPC_SVR_NONE) {
8411         if (pcc->svr & POWERPC_SVR_E500) {
8412             spr_register(env, SPR_E500_SVR, "SVR",
8413                          SPR_NOACCESS, SPR_NOACCESS,
8414                          &spr_read_generic, SPR_NOACCESS,
8415                          pcc->svr & ~POWERPC_SVR_E500);
8416         } else {
8417             spr_register(env, SPR_SVR, "SVR",
8418                          SPR_NOACCESS, SPR_NOACCESS,
8419                          &spr_read_generic, SPR_NOACCESS,
8420                          pcc->svr);
8421         }
8422     }
8423     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8424     (*pcc->init_proc)(env);
8425 
8426 #if !defined(CONFIG_USER_ONLY)
8427     ppc_gdb_gen_spr_xml(cpu);
8428 #endif
8429 
8430     /* MSR bits & flags consistency checks */
8431     if (env->msr_mask & (1 << 25)) {
8432         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8433         case POWERPC_FLAG_SPE:
8434         case POWERPC_FLAG_VRE:
8435             break;
8436         default:
8437             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8438                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8439             exit(1);
8440         }
8441     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8442         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8443                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8444         exit(1);
8445     }
8446     if (env->msr_mask & (1 << 17)) {
8447         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8448         case POWERPC_FLAG_TGPR:
8449         case POWERPC_FLAG_CE:
8450             break;
8451         default:
8452             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8453                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8454             exit(1);
8455         }
8456     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8457         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8458                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8459         exit(1);
8460     }
8461     if (env->msr_mask & (1 << 10)) {
8462         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8463                               POWERPC_FLAG_UBLE)) {
8464         case POWERPC_FLAG_SE:
8465         case POWERPC_FLAG_DWE:
8466         case POWERPC_FLAG_UBLE:
8467             break;
8468         default:
8469             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8470                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8471                     "POWERPC_FLAG_UBLE\n");
8472             exit(1);
8473         }
8474     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8475                              POWERPC_FLAG_UBLE)) {
8476         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8477                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8478                 "POWERPC_FLAG_UBLE\n");
8479             exit(1);
8480     }
8481     if (env->msr_mask & (1 << 9)) {
8482         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8483         case POWERPC_FLAG_BE:
8484         case POWERPC_FLAG_DE:
8485             break;
8486         default:
8487             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8488                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8489             exit(1);
8490         }
8491     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8492         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8493                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8494         exit(1);
8495     }
8496     if (env->msr_mask & (1 << 2)) {
8497         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8498         case POWERPC_FLAG_PX:
8499         case POWERPC_FLAG_PMM:
8500             break;
8501         default:
8502             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8503                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8504             exit(1);
8505         }
8506     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8507         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8508                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8509         exit(1);
8510     }
8511     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8512         fprintf(stderr, "PowerPC flags inconsistency\n"
8513                 "Should define the time-base and decrementer clock source\n");
8514         exit(1);
8515     }
8516     /* Allocate TLBs buffer when needed */
8517 #if !defined(CONFIG_USER_ONLY)
8518     if (env->nb_tlb != 0) {
8519         int nb_tlb = env->nb_tlb;
8520         if (env->id_tlbs != 0) {
8521             nb_tlb *= 2;
8522         }
8523         switch (env->tlb_type) {
8524         case TLB_6XX:
8525             env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
8526             break;
8527         case TLB_EMB:
8528             env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
8529             break;
8530         case TLB_MAS:
8531             env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
8532             break;
8533         }
8534         /* Pre-compute some useful values */
8535         env->tlb_per_way = env->nb_tlb / env->nb_ways;
8536     }
8537     if (env->irq_inputs == NULL) {
8538         warn_report("no internal IRQ controller registered."
8539                     " Attempt QEMU to crash very soon !");
8540     }
8541 #endif
8542     if (env->check_pow == NULL) {
8543         warn_report("no power management check handler registered."
8544                     " Attempt QEMU to crash very soon !");
8545     }
8546 }
8547 
8548 #if defined(PPC_DUMP_CPU)
8549 static void dump_ppc_sprs(CPUPPCState *env)
8550 {
8551     ppc_spr_t *spr;
8552 #if !defined(CONFIG_USER_ONLY)
8553     uint32_t sr, sw;
8554 #endif
8555     uint32_t ur, uw;
8556     int i, j, n;
8557 
8558     printf("Special purpose registers:\n");
8559     for (i = 0; i < 32; i++) {
8560         for (j = 0; j < 32; j++) {
8561             n = (i << 5) | j;
8562             spr = &env->spr_cb[n];
8563             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8564             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8565 #if !defined(CONFIG_USER_ONLY)
8566             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8567             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8568             if (sw || sr || uw || ur) {
8569                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8570                        (i << 5) | j, (i << 5) | j, spr->name,
8571                        sw ? 'w' : '-', sr ? 'r' : '-',
8572                        uw ? 'w' : '-', ur ? 'r' : '-');
8573             }
8574 #else
8575             if (uw || ur) {
8576                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8577                        (i << 5) | j, (i << 5) | j, spr->name,
8578                        uw ? 'w' : '-', ur ? 'r' : '-');
8579             }
8580 #endif
8581         }
8582     }
8583     fflush(stdout);
8584     fflush(stderr);
8585 }
8586 #endif
8587 
8588 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
8589 {
8590     CPUState *cs = CPU(dev);
8591     PowerPCCPU *cpu = POWERPC_CPU(dev);
8592     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8593     Error *local_err = NULL;
8594 
8595     cpu_exec_realizefn(cs, &local_err);
8596     if (local_err != NULL) {
8597         error_propagate(errp, local_err);
8598         return;
8599     }
8600     if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
8601         cpu->vcpu_id = cs->cpu_index;
8602     }
8603 
8604     if (tcg_enabled()) {
8605         if (ppc_fixup_cpu(cpu) != 0) {
8606             error_setg(errp, "Unable to emulate selected CPU with TCG");
8607             goto unrealize;
8608         }
8609     }
8610 
8611     create_ppc_opcodes(cpu, &local_err);
8612     if (local_err != NULL) {
8613         error_propagate(errp, local_err);
8614         goto unrealize;
8615     }
8616     init_ppc_proc(cpu);
8617 
8618     ppc_gdb_init(cs, pcc);
8619     qemu_init_vcpu(cs);
8620 
8621     pcc->parent_realize(dev, errp);
8622 
8623 #if defined(PPC_DUMP_CPU)
8624     {
8625         CPUPPCState *env = &cpu->env;
8626         const char *mmu_model, *excp_model, *bus_model;
8627         switch (env->mmu_model) {
8628         case POWERPC_MMU_32B:
8629             mmu_model = "PowerPC 32";
8630             break;
8631         case POWERPC_MMU_SOFT_6xx:
8632             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8633             break;
8634         case POWERPC_MMU_SOFT_74xx:
8635             mmu_model = "PowerPC 74xx with software driven TLBs";
8636             break;
8637         case POWERPC_MMU_SOFT_4xx:
8638             mmu_model = "PowerPC 4xx with software driven TLBs";
8639             break;
8640         case POWERPC_MMU_SOFT_4xx_Z:
8641             mmu_model = "PowerPC 4xx with software driven TLBs "
8642                 "and zones protections";
8643             break;
8644         case POWERPC_MMU_REAL:
8645             mmu_model = "PowerPC real mode only";
8646             break;
8647         case POWERPC_MMU_MPC8xx:
8648             mmu_model = "PowerPC MPC8xx";
8649             break;
8650         case POWERPC_MMU_BOOKE:
8651             mmu_model = "PowerPC BookE";
8652             break;
8653         case POWERPC_MMU_BOOKE206:
8654             mmu_model = "PowerPC BookE 2.06";
8655             break;
8656         case POWERPC_MMU_601:
8657             mmu_model = "PowerPC 601";
8658             break;
8659 #if defined(TARGET_PPC64)
8660         case POWERPC_MMU_64B:
8661             mmu_model = "PowerPC 64";
8662             break;
8663 #endif
8664         default:
8665             mmu_model = "Unknown or invalid";
8666             break;
8667         }
8668         switch (env->excp_model) {
8669         case POWERPC_EXCP_STD:
8670             excp_model = "PowerPC";
8671             break;
8672         case POWERPC_EXCP_40x:
8673             excp_model = "PowerPC 40x";
8674             break;
8675         case POWERPC_EXCP_601:
8676             excp_model = "PowerPC 601";
8677             break;
8678         case POWERPC_EXCP_602:
8679             excp_model = "PowerPC 602";
8680             break;
8681         case POWERPC_EXCP_603:
8682             excp_model = "PowerPC 603";
8683             break;
8684         case POWERPC_EXCP_603E:
8685             excp_model = "PowerPC 603e";
8686             break;
8687         case POWERPC_EXCP_604:
8688             excp_model = "PowerPC 604";
8689             break;
8690         case POWERPC_EXCP_7x0:
8691             excp_model = "PowerPC 740/750";
8692             break;
8693         case POWERPC_EXCP_7x5:
8694             excp_model = "PowerPC 745/755";
8695             break;
8696         case POWERPC_EXCP_74xx:
8697             excp_model = "PowerPC 74xx";
8698             break;
8699         case POWERPC_EXCP_BOOKE:
8700             excp_model = "PowerPC BookE";
8701             break;
8702 #if defined(TARGET_PPC64)
8703         case POWERPC_EXCP_970:
8704             excp_model = "PowerPC 970";
8705             break;
8706 #endif
8707         default:
8708             excp_model = "Unknown or invalid";
8709             break;
8710         }
8711         switch (env->bus_model) {
8712         case PPC_FLAGS_INPUT_6xx:
8713             bus_model = "PowerPC 6xx";
8714             break;
8715         case PPC_FLAGS_INPUT_BookE:
8716             bus_model = "PowerPC BookE";
8717             break;
8718         case PPC_FLAGS_INPUT_405:
8719             bus_model = "PowerPC 405";
8720             break;
8721         case PPC_FLAGS_INPUT_401:
8722             bus_model = "PowerPC 401/403";
8723             break;
8724         case PPC_FLAGS_INPUT_RCPU:
8725             bus_model = "RCPU / MPC8xx";
8726             break;
8727 #if defined(TARGET_PPC64)
8728         case PPC_FLAGS_INPUT_970:
8729             bus_model = "PowerPC 970";
8730             break;
8731 #endif
8732         default:
8733             bus_model = "Unknown or invalid";
8734             break;
8735         }
8736         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8737                "    MMU model        : %s\n",
8738                object_class_get_name(OBJECT_CLASS(pcc)),
8739                pcc->pvr, pcc->msr_mask, mmu_model);
8740 #if !defined(CONFIG_USER_ONLY)
8741         if (env->tlb.tlb6) {
8742             printf("                       %d %s TLB in %d ways\n",
8743                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8744                    env->nb_ways);
8745         }
8746 #endif
8747         printf("    Exceptions model : %s\n"
8748                "    Bus model        : %s\n",
8749                excp_model, bus_model);
8750         printf("    MSR features     :\n");
8751         if (env->flags & POWERPC_FLAG_SPE) {
8752             printf("                        signal processing engine enable"
8753                    "\n");
8754         } else if (env->flags & POWERPC_FLAG_VRE) {
8755             printf("                        vector processor enable\n");
8756         }
8757         if (env->flags & POWERPC_FLAG_TGPR) {
8758             printf("                        temporary GPRs\n");
8759         } else if (env->flags & POWERPC_FLAG_CE) {
8760             printf("                        critical input enable\n");
8761         }
8762         if (env->flags & POWERPC_FLAG_SE) {
8763             printf("                        single-step trace mode\n");
8764         } else if (env->flags & POWERPC_FLAG_DWE) {
8765             printf("                        debug wait enable\n");
8766         } else if (env->flags & POWERPC_FLAG_UBLE) {
8767             printf("                        user BTB lock enable\n");
8768         }
8769         if (env->flags & POWERPC_FLAG_BE) {
8770             printf("                        branch-step trace mode\n");
8771         } else if (env->flags & POWERPC_FLAG_DE) {
8772             printf("                        debug interrupt enable\n");
8773         }
8774         if (env->flags & POWERPC_FLAG_PX) {
8775             printf("                        inclusive protection\n");
8776         } else if (env->flags & POWERPC_FLAG_PMM) {
8777             printf("                        performance monitor mark\n");
8778         }
8779         if (env->flags == POWERPC_FLAG_NONE) {
8780             printf("                        none\n");
8781         }
8782         printf("    Time-base/decrementer clock source: %s\n",
8783                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8784         dump_ppc_insns(env);
8785         dump_ppc_sprs(env);
8786         fflush(stdout);
8787     }
8788 #endif
8789     return;
8790 
8791 unrealize:
8792     cpu_exec_unrealizefn(cs);
8793 }
8794 
8795 static void ppc_cpu_unrealize(DeviceState *dev)
8796 {
8797     PowerPCCPU *cpu = POWERPC_CPU(dev);
8798     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8799 
8800     pcc->parent_unrealize(dev);
8801 
8802     cpu_remove_sync(CPU(cpu));
8803 
8804     destroy_ppc_opcodes(cpu);
8805 }
8806 
8807 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8808 {
8809     ObjectClass *oc = (ObjectClass *)a;
8810     uint32_t pvr = *(uint32_t *)b;
8811     PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8812 
8813     /* -cpu host does a PVR lookup during construction */
8814     if (unlikely(strcmp(object_class_get_name(oc),
8815                         TYPE_HOST_POWERPC_CPU) == 0)) {
8816         return -1;
8817     }
8818 
8819     return pcc->pvr == pvr ? 0 : -1;
8820 }
8821 
8822 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8823 {
8824     GSList *list, *item;
8825     PowerPCCPUClass *pcc = NULL;
8826 
8827     list = object_class_get_list(TYPE_POWERPC_CPU, false);
8828     item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8829     if (item != NULL) {
8830         pcc = POWERPC_CPU_CLASS(item->data);
8831     }
8832     g_slist_free(list);
8833 
8834     return pcc;
8835 }
8836 
8837 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8838 {
8839     ObjectClass *oc = (ObjectClass *)a;
8840     uint32_t pvr = *(uint32_t *)b;
8841     PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8842 
8843     /* -cpu host does a PVR lookup during construction */
8844     if (unlikely(strcmp(object_class_get_name(oc),
8845                         TYPE_HOST_POWERPC_CPU) == 0)) {
8846         return -1;
8847     }
8848 
8849     if (pcc->pvr_match(pcc, pvr)) {
8850         return 0;
8851     }
8852 
8853     return -1;
8854 }
8855 
8856 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8857 {
8858     GSList *list, *item;
8859     PowerPCCPUClass *pcc = NULL;
8860 
8861     list = object_class_get_list(TYPE_POWERPC_CPU, true);
8862     item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8863     if (item != NULL) {
8864         pcc = POWERPC_CPU_CLASS(item->data);
8865     }
8866     g_slist_free(list);
8867 
8868     return pcc;
8869 }
8870 
8871 static const char *ppc_cpu_lookup_alias(const char *alias)
8872 {
8873     int ai;
8874 
8875     for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
8876         if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
8877             return ppc_cpu_aliases[ai].model;
8878         }
8879     }
8880 
8881     return NULL;
8882 }
8883 
8884 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8885 {
8886     char *cpu_model, *typename;
8887     ObjectClass *oc;
8888     const char *p;
8889     unsigned long pvr;
8890 
8891     /*
8892      * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
8893      * 0x prefix if present)
8894      */
8895     if (!qemu_strtoul(name, &p, 16, &pvr)) {
8896         int len = p - name;
8897         len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
8898         if ((len == 8) && (*p == '\0')) {
8899             return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
8900         }
8901     }
8902 
8903     cpu_model = g_ascii_strdown(name, -1);
8904     p = ppc_cpu_lookup_alias(cpu_model);
8905     if (p) {
8906         g_free(cpu_model);
8907         cpu_model = g_strdup(p);
8908     }
8909 
8910     typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
8911     oc = object_class_by_name(typename);
8912     g_free(typename);
8913     g_free(cpu_model);
8914 
8915     return oc;
8916 }
8917 
8918 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
8919 {
8920     ObjectClass *oc = OBJECT_CLASS(pcc);
8921 
8922     while (oc && !object_class_is_abstract(oc)) {
8923         oc = object_class_get_parent(oc);
8924     }
8925     assert(oc);
8926 
8927     return POWERPC_CPU_CLASS(oc);
8928 }
8929 
8930 /* Sort by PVR, ordering special case "host" last. */
8931 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8932 {
8933     ObjectClass *oc_a = (ObjectClass *)a;
8934     ObjectClass *oc_b = (ObjectClass *)b;
8935     PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8936     PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8937     const char *name_a = object_class_get_name(oc_a);
8938     const char *name_b = object_class_get_name(oc_b);
8939 
8940     if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8941         return 1;
8942     } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8943         return -1;
8944     } else {
8945         /* Avoid an integer overflow during subtraction */
8946         if (pcc_a->pvr < pcc_b->pvr) {
8947             return -1;
8948         } else if (pcc_a->pvr > pcc_b->pvr) {
8949             return 1;
8950         } else {
8951             return 0;
8952         }
8953     }
8954 }
8955 
8956 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8957 {
8958     ObjectClass *oc = data;
8959     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8960     DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
8961     const char *typename = object_class_get_name(oc);
8962     char *name;
8963     int i;
8964 
8965     if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8966         return;
8967     }
8968 
8969     name = g_strndup(typename,
8970                      strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8971     qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
8972     for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8973         PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8974         ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8975 
8976         if (alias_oc != oc) {
8977             continue;
8978         }
8979         /*
8980          * If running with KVM, we might update the family alias later, so
8981          * avoid printing the wrong alias here and use "preferred" instead
8982          */
8983         if (strcmp(alias->alias, family->desc) == 0) {
8984             qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
8985                         alias->alias, family->desc);
8986         } else {
8987             qemu_printf("PowerPC %-16s (alias for %s)\n",
8988                         alias->alias, name);
8989         }
8990     }
8991     g_free(name);
8992 }
8993 
8994 void ppc_cpu_list(void)
8995 {
8996     GSList *list;
8997 
8998     list = object_class_get_list(TYPE_POWERPC_CPU, false);
8999     list = g_slist_sort(list, ppc_cpu_list_compare);
9000     g_slist_foreach(list, ppc_cpu_list_entry, NULL);
9001     g_slist_free(list);
9002 
9003 #ifdef CONFIG_KVM
9004     qemu_printf("\n");
9005     qemu_printf("PowerPC %-16s\n", "host");
9006 #endif
9007 }
9008 
9009 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9010 {
9011     ObjectClass *oc = data;
9012     CpuDefinitionInfoList **first = user_data;
9013     const char *typename;
9014     CpuDefinitionInfo *info;
9015 
9016     typename = object_class_get_name(oc);
9017     info = g_malloc0(sizeof(*info));
9018     info->name = g_strndup(typename,
9019                            strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
9020 
9021     QAPI_LIST_PREPEND(*first, info);
9022 }
9023 
9024 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
9025 {
9026     CpuDefinitionInfoList *cpu_list = NULL;
9027     GSList *list;
9028     int i;
9029 
9030     list = object_class_get_list(TYPE_POWERPC_CPU, false);
9031     g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9032     g_slist_free(list);
9033 
9034     for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9035         PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9036         ObjectClass *oc;
9037         CpuDefinitionInfo *info;
9038 
9039         oc = ppc_cpu_class_by_name(alias->model);
9040         if (oc == NULL) {
9041             continue;
9042         }
9043 
9044         info = g_malloc0(sizeof(*info));
9045         info->name = g_strdup(alias->alias);
9046         info->q_typename = g_strdup(object_class_get_name(oc));
9047 
9048         QAPI_LIST_PREPEND(cpu_list, info);
9049     }
9050 
9051     return cpu_list;
9052 }
9053 
9054 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9055 {
9056     PowerPCCPU *cpu = POWERPC_CPU(cs);
9057 
9058     cpu->env.nip = value;
9059 }
9060 
9061 static bool ppc_cpu_has_work(CPUState *cs)
9062 {
9063     PowerPCCPU *cpu = POWERPC_CPU(cs);
9064     CPUPPCState *env = &cpu->env;
9065 
9066     return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9067 }
9068 
9069 static void ppc_cpu_reset(DeviceState *dev)
9070 {
9071     CPUState *s = CPU(dev);
9072     PowerPCCPU *cpu = POWERPC_CPU(s);
9073     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9074     CPUPPCState *env = &cpu->env;
9075     target_ulong msr;
9076     int i;
9077 
9078     pcc->parent_reset(dev);
9079 
9080     msr = (target_ulong)0;
9081     msr |= (target_ulong)MSR_HVB;
9082     msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9083     msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9084     msr |= (target_ulong)1 << MSR_EP;
9085 #if defined(DO_SINGLE_STEP) && 0
9086     /* Single step trace mode */
9087     msr |= (target_ulong)1 << MSR_SE;
9088     msr |= (target_ulong)1 << MSR_BE;
9089 #endif
9090 #if defined(CONFIG_USER_ONLY)
9091     msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9092     msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
9093     msr |= (target_ulong)1 << MSR_FE1;
9094     msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9095     msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9096     msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9097     msr |= (target_ulong)1 << MSR_PR;
9098 #if defined(TARGET_PPC64)
9099     msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9100 #endif
9101 #if !defined(TARGET_WORDS_BIGENDIAN)
9102     msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9103     if (!((env->msr_mask >> MSR_LE) & 1)) {
9104         fprintf(stderr, "Selected CPU does not support little-endian.\n");
9105         exit(1);
9106     }
9107 #endif
9108 #endif
9109 
9110 #if defined(TARGET_PPC64)
9111     if (mmu_is_64bit(env->mmu_model)) {
9112         msr |= (1ULL << MSR_SF);
9113     }
9114 #endif
9115 
9116     hreg_store_msr(env, msr, 1);
9117 
9118 #if !defined(CONFIG_USER_ONLY)
9119     env->nip = env->hreset_vector | env->excp_prefix;
9120     if (env->mmu_model != POWERPC_MMU_REAL) {
9121         ppc_tlb_invalidate_all(env);
9122     }
9123 #endif
9124 
9125     hreg_compute_hflags(env);
9126     env->reserve_addr = (target_ulong)-1ULL;
9127     /* Be sure no exception or interrupt is pending */
9128     env->pending_interrupts = 0;
9129     s->exception_index = POWERPC_EXCP_NONE;
9130     env->error_code = 0;
9131     ppc_irq_reset(cpu);
9132 
9133     /* tininess for underflow is detected before rounding */
9134     set_float_detect_tininess(float_tininess_before_rounding,
9135                               &env->fp_status);
9136 
9137     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9138         ppc_spr_t *spr = &env->spr_cb[i];
9139 
9140         if (!spr->name) {
9141             continue;
9142         }
9143         env->spr[i] = spr->default_value;
9144     }
9145 }
9146 
9147 #ifndef CONFIG_USER_ONLY
9148 
9149 static bool ppc_cpu_is_big_endian(CPUState *cs)
9150 {
9151     PowerPCCPU *cpu = POWERPC_CPU(cs);
9152     CPUPPCState *env = &cpu->env;
9153 
9154     cpu_synchronize_state(cs);
9155 
9156     return !msr_le;
9157 }
9158 
9159 #ifdef CONFIG_TCG
9160 static void ppc_cpu_exec_enter(CPUState *cs)
9161 {
9162     PowerPCCPU *cpu = POWERPC_CPU(cs);
9163 
9164     if (cpu->vhyp) {
9165         PPCVirtualHypervisorClass *vhc =
9166             PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
9167         vhc->cpu_exec_enter(cpu->vhyp, cpu);
9168     }
9169 }
9170 
9171 static void ppc_cpu_exec_exit(CPUState *cs)
9172 {
9173     PowerPCCPU *cpu = POWERPC_CPU(cs);
9174 
9175     if (cpu->vhyp) {
9176         PPCVirtualHypervisorClass *vhc =
9177             PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
9178         vhc->cpu_exec_exit(cpu->vhyp, cpu);
9179     }
9180 }
9181 #endif /* CONFIG_TCG */
9182 
9183 #endif /* !CONFIG_USER_ONLY */
9184 
9185 static void ppc_cpu_instance_init(Object *obj)
9186 {
9187     PowerPCCPU *cpu = POWERPC_CPU(obj);
9188     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9189     CPUPPCState *env = &cpu->env;
9190 
9191     cpu_set_cpustate_pointers(cpu);
9192     cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
9193 
9194     env->msr_mask = pcc->msr_mask;
9195     env->mmu_model = pcc->mmu_model;
9196     env->excp_model = pcc->excp_model;
9197     env->bus_model = pcc->bus_model;
9198     env->insns_flags = pcc->insns_flags;
9199     env->insns_flags2 = pcc->insns_flags2;
9200     env->flags = pcc->flags;
9201     env->bfd_mach = pcc->bfd_mach;
9202     env->check_pow = pcc->check_pow;
9203 
9204     /*
9205      * Mark HV mode as supported if the CPU has an MSR_HV bit in the
9206      * msr_mask. The mask can later be cleared by PAPR mode but the hv
9207      * mode support will remain, thus enforcing that we cannot use
9208      * priv. instructions in guest in PAPR mode. For 970 we currently
9209      * simply don't set HV in msr_mask thus simulating an "Apple mode"
9210      * 970. If we ever want to support 970 HV mode, we'll have to add
9211      * a processor attribute of some sort.
9212      */
9213 #if !defined(CONFIG_USER_ONLY)
9214     env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
9215 #endif
9216 
9217     ppc_hash64_init(cpu);
9218 }
9219 
9220 static void ppc_cpu_instance_finalize(Object *obj)
9221 {
9222     PowerPCCPU *cpu = POWERPC_CPU(obj);
9223 
9224     ppc_hash64_finalize(cpu);
9225 }
9226 
9227 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
9228 {
9229     return pcc->pvr == pvr;
9230 }
9231 
9232 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
9233 {
9234     PowerPCCPU *cpu = POWERPC_CPU(cs);
9235     CPUPPCState *env = &cpu->env;
9236 
9237     if ((env->hflags >> MSR_LE) & 1) {
9238         info->endian = BFD_ENDIAN_LITTLE;
9239     }
9240     info->mach = env->bfd_mach;
9241     if (!env->bfd_mach) {
9242 #ifdef TARGET_PPC64
9243         info->mach = bfd_mach_ppc64;
9244 #else
9245         info->mach = bfd_mach_ppc;
9246 #endif
9247     }
9248     info->disassembler_options = (char *)"any";
9249     info->print_insn = print_insn_ppc;
9250 
9251     info->cap_arch = CS_ARCH_PPC;
9252 #ifdef TARGET_PPC64
9253     info->cap_mode = CS_MODE_64;
9254 #endif
9255 }
9256 
9257 static Property ppc_cpu_properties[] = {
9258     DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
9259     DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
9260                      false),
9261     DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
9262                      false),
9263     DEFINE_PROP_END_OF_LIST(),
9264 };
9265 
9266 #ifndef CONFIG_USER_ONLY
9267 #include "hw/core/sysemu-cpu-ops.h"
9268 
9269 static const struct SysemuCPUOps ppc_sysemu_ops = {
9270     .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
9271     .write_elf32_note = ppc32_cpu_write_elf32_note,
9272     .write_elf64_note = ppc64_cpu_write_elf64_note,
9273     .virtio_is_big_endian = ppc_cpu_is_big_endian,
9274     .legacy_vmsd = &vmstate_ppc_cpu,
9275 };
9276 #endif
9277 
9278 #ifdef CONFIG_TCG
9279 #include "hw/core/tcg-cpu-ops.h"
9280 
9281 static const struct TCGCPUOps ppc_tcg_ops = {
9282   .initialize = ppc_translate_init,
9283   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
9284   .tlb_fill = ppc_cpu_tlb_fill,
9285 
9286 #ifndef CONFIG_USER_ONLY
9287   .do_interrupt = ppc_cpu_do_interrupt,
9288   .cpu_exec_enter = ppc_cpu_exec_enter,
9289   .cpu_exec_exit = ppc_cpu_exec_exit,
9290   .do_unaligned_access = ppc_cpu_do_unaligned_access,
9291 #endif /* !CONFIG_USER_ONLY */
9292 };
9293 #endif /* CONFIG_TCG */
9294 
9295 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9296 {
9297     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9298     CPUClass *cc = CPU_CLASS(oc);
9299     DeviceClass *dc = DEVICE_CLASS(oc);
9300 
9301     device_class_set_parent_realize(dc, ppc_cpu_realize,
9302                                     &pcc->parent_realize);
9303     device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
9304                                       &pcc->parent_unrealize);
9305     pcc->pvr_match = ppc_pvr_match_default;
9306     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
9307     device_class_set_props(dc, ppc_cpu_properties);
9308 
9309     device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
9310 
9311     cc->class_by_name = ppc_cpu_class_by_name;
9312     cc->has_work = ppc_cpu_has_work;
9313     cc->dump_state = ppc_cpu_dump_state;
9314     cc->dump_statistics = ppc_cpu_dump_statistics;
9315     cc->set_pc = ppc_cpu_set_pc;
9316     cc->gdb_read_register = ppc_cpu_gdb_read_register;
9317     cc->gdb_write_register = ppc_cpu_gdb_write_register;
9318 #ifndef CONFIG_USER_ONLY
9319     cc->sysemu_ops = &ppc_sysemu_ops;
9320 #endif
9321 
9322     cc->gdb_num_core_regs = 71;
9323 #ifndef CONFIG_USER_ONLY
9324     cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
9325 #endif
9326 #ifdef USE_APPLE_GDB
9327     cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
9328     cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
9329     cc->gdb_num_core_regs = 71 + 32;
9330 #endif
9331 
9332     cc->gdb_arch_name = ppc_gdb_arch_name;
9333 #if defined(TARGET_PPC64)
9334     cc->gdb_core_xml_file = "power64-core.xml";
9335 #else
9336     cc->gdb_core_xml_file = "power-core.xml";
9337 #endif
9338     cc->disas_set_info = ppc_disas_set_info;
9339 
9340     dc->fw_name = "PowerPC,UNKNOWN";
9341 
9342 #ifdef CONFIG_TCG
9343     cc->tcg_ops = &ppc_tcg_ops;
9344 #endif /* CONFIG_TCG */
9345 }
9346 
9347 static const TypeInfo ppc_cpu_type_info = {
9348     .name = TYPE_POWERPC_CPU,
9349     .parent = TYPE_CPU,
9350     .instance_size = sizeof(PowerPCCPU),
9351     .instance_align = __alignof__(PowerPCCPU),
9352     .instance_init = ppc_cpu_instance_init,
9353     .instance_finalize = ppc_cpu_instance_finalize,
9354     .abstract = true,
9355     .class_size = sizeof(PowerPCCPUClass),
9356     .class_init = ppc_cpu_class_init,
9357 };
9358 
9359 #ifndef CONFIG_USER_ONLY
9360 static const TypeInfo ppc_vhyp_type_info = {
9361     .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
9362     .parent = TYPE_INTERFACE,
9363     .class_size = sizeof(PPCVirtualHypervisorClass),
9364 };
9365 #endif
9366 
9367 static void ppc_cpu_register_types(void)
9368 {
9369     type_register_static(&ppc_cpu_type_info);
9370 #ifndef CONFIG_USER_ONLY
9371     type_register_static(&ppc_vhyp_type_info);
9372 #endif
9373 }
9374 
9375 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
9376 {
9377 #define RGPL  4
9378 #define RFPL  4
9379 
9380     PowerPCCPU *cpu = POWERPC_CPU(cs);
9381     CPUPPCState *env = &cpu->env;
9382     int i;
9383 
9384     qemu_fprintf(f, "NIP " TARGET_FMT_lx "   LR " TARGET_FMT_lx " CTR "
9385                  TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
9386                  env->nip, env->lr, env->ctr, cpu_read_xer(env),
9387                  cs->cpu_index);
9388     qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx "  HF "
9389                  "%08x iidx %d didx %d\n",
9390                  env->msr, env->spr[SPR_HID0], env->hflags,
9391                  cpu_mmu_index(env, true), cpu_mmu_index(env, false));
9392 #if !defined(NO_TIMER_DUMP)
9393     qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9394 #if !defined(CONFIG_USER_ONLY)
9395                  " DECR " TARGET_FMT_lu
9396 #endif
9397                  "\n",
9398                  cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9399 #if !defined(CONFIG_USER_ONLY)
9400                  , cpu_ppc_load_decr(env)
9401 #endif
9402         );
9403 #endif
9404     for (i = 0; i < 32; i++) {
9405         if ((i & (RGPL - 1)) == 0) {
9406             qemu_fprintf(f, "GPR%02d", i);
9407         }
9408         qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9409         if ((i & (RGPL - 1)) == (RGPL - 1)) {
9410             qemu_fprintf(f, "\n");
9411         }
9412     }
9413     qemu_fprintf(f, "CR ");
9414     for (i = 0; i < 8; i++)
9415         qemu_fprintf(f, "%01x", env->crf[i]);
9416     qemu_fprintf(f, "  [");
9417     for (i = 0; i < 8; i++) {
9418         char a = '-';
9419         if (env->crf[i] & 0x08) {
9420             a = 'L';
9421         } else if (env->crf[i] & 0x04) {
9422             a = 'G';
9423         } else if (env->crf[i] & 0x02) {
9424             a = 'E';
9425         }
9426         qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9427     }
9428     qemu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
9429                  env->reserve_addr);
9430 
9431     if (flags & CPU_DUMP_FPU) {
9432         for (i = 0; i < 32; i++) {
9433             if ((i & (RFPL - 1)) == 0) {
9434                 qemu_fprintf(f, "FPR%02d", i);
9435             }
9436             qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
9437             if ((i & (RFPL - 1)) == (RFPL - 1)) {
9438                 qemu_fprintf(f, "\n");
9439             }
9440         }
9441         qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9442     }
9443 
9444 #if !defined(CONFIG_USER_ONLY)
9445     qemu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
9446                  "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9447                  env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9448                  env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9449 
9450     qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9451                  "  SPRG2 " TARGET_FMT_lx "  SPRG3 " TARGET_FMT_lx "\n",
9452                  env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9453                  env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9454 
9455     qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9456                  "  SPRG6 " TARGET_FMT_lx "  SPRG7 " TARGET_FMT_lx "\n",
9457                  env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9458                  env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9459 
9460 #if defined(TARGET_PPC64)
9461     if (env->excp_model == POWERPC_EXCP_POWER7 ||
9462         env->excp_model == POWERPC_EXCP_POWER8 ||
9463         env->excp_model == POWERPC_EXCP_POWER9 ||
9464         env->excp_model == POWERPC_EXCP_POWER10)  {
9465         qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
9466                      env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
9467     }
9468 #endif
9469     if (env->excp_model == POWERPC_EXCP_BOOKE) {
9470         qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9471                      " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9472                      env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9473                      env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9474 
9475         qemu_fprintf(f, "  TCR " TARGET_FMT_lx "   TSR " TARGET_FMT_lx
9476                      "    ESR " TARGET_FMT_lx "   DEAR " TARGET_FMT_lx "\n",
9477                      env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9478                      env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9479 
9480         qemu_fprintf(f, "  PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9481                      "   IVPR " TARGET_FMT_lx "   EPCR " TARGET_FMT_lx "\n",
9482                      env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9483                      env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9484 
9485         qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9486                      "    EPR " TARGET_FMT_lx "\n",
9487                      env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9488                      env->spr[SPR_BOOKE_EPR]);
9489 
9490         /* FSL-specific */
9491         qemu_fprintf(f, " MCAR " TARGET_FMT_lx "  PID1 " TARGET_FMT_lx
9492                      "   PID2 " TARGET_FMT_lx "    SVR " TARGET_FMT_lx "\n",
9493                      env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9494                      env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9495 
9496         /*
9497          * IVORs are left out as they are large and do not change often --
9498          * they can be read with "p $ivor0", "p $ivor1", etc.
9499          */
9500     }
9501 
9502 #if defined(TARGET_PPC64)
9503     if (env->flags & POWERPC_FLAG_CFAR) {
9504         qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9505     }
9506 #endif
9507 
9508     if (env->spr_cb[SPR_LPCR].name) {
9509         qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
9510     }
9511 
9512     switch (env->mmu_model) {
9513     case POWERPC_MMU_32B:
9514     case POWERPC_MMU_601:
9515     case POWERPC_MMU_SOFT_6xx:
9516     case POWERPC_MMU_SOFT_74xx:
9517 #if defined(TARGET_PPC64)
9518     case POWERPC_MMU_64B:
9519     case POWERPC_MMU_2_03:
9520     case POWERPC_MMU_2_06:
9521     case POWERPC_MMU_2_07:
9522     case POWERPC_MMU_3_00:
9523 #endif
9524         if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
9525             qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
9526         }
9527         if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
9528             qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
9529         }
9530         qemu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
9531                      env->spr[SPR_DAR], env->spr[SPR_DSISR]);
9532         break;
9533     case POWERPC_MMU_BOOKE206:
9534         qemu_fprintf(f, " MAS0 " TARGET_FMT_lx "  MAS1 " TARGET_FMT_lx
9535                      "   MAS2 " TARGET_FMT_lx "   MAS3 " TARGET_FMT_lx "\n",
9536                      env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9537                      env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9538 
9539         qemu_fprintf(f, " MAS4 " TARGET_FMT_lx "  MAS6 " TARGET_FMT_lx
9540                      "   MAS7 " TARGET_FMT_lx "    PID " TARGET_FMT_lx "\n",
9541                      env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9542                      env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9543 
9544         qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9545                      " TLB1CFG " TARGET_FMT_lx "\n",
9546                      env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9547                      env->spr[SPR_BOOKE_TLB1CFG]);
9548         break;
9549     default:
9550         break;
9551     }
9552 #endif
9553 
9554 #undef RGPL
9555 #undef RFPL
9556 }
9557 type_init(ppc_cpu_register_types)
9558