1
2 /*
3 * PowerPC CPU initialization for qemu.
4 *
5 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "disas/dis-asm.h"
24 #include "gdbstub/helpers.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43
44 #include "helper_regs.h"
45 #include "internal.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
48
49 #ifndef CONFIG_USER_ONLY
50 #include "hw/boards.h"
51 #include "hw/intc/intc.h"
52 #include "kvm_ppc.h"
53 #endif
54
55 #include "cpu_init.h"
56 /* #define PPC_DEBUG_SPR */
57 /* #define USE_APPLE_GDB */
58
vscr_init(CPUPPCState * env,uint32_t val)59 static inline void vscr_init(CPUPPCState *env, uint32_t val)
60 {
61 /* Altivec always uses round-to-nearest */
62 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
63 ppc_store_vscr(env, val);
64 }
65
register_745_sprs(CPUPPCState * env)66 static void register_745_sprs(CPUPPCState *env)
67 {
68 /* SGPRs */
69 spr_register(env, SPR_SPRG4, "SPRG4",
70 SPR_NOACCESS, SPR_NOACCESS,
71 &spr_read_generic, &spr_write_generic,
72 0x00000000);
73 spr_register(env, SPR_SPRG5, "SPRG5",
74 SPR_NOACCESS, SPR_NOACCESS,
75 &spr_read_generic, &spr_write_generic,
76 0x00000000);
77 spr_register(env, SPR_SPRG6, "SPRG6",
78 SPR_NOACCESS, SPR_NOACCESS,
79 &spr_read_generic, &spr_write_generic,
80 0x00000000);
81 spr_register(env, SPR_SPRG7, "SPRG7",
82 SPR_NOACCESS, SPR_NOACCESS,
83 &spr_read_generic, &spr_write_generic,
84 0x00000000);
85
86 /* Hardware implementation registers */
87 spr_register(env, SPR_HID0, "HID0",
88 SPR_NOACCESS, SPR_NOACCESS,
89 &spr_read_generic, &spr_write_generic,
90 0x00000000);
91
92 spr_register(env, SPR_HID1, "HID1",
93 SPR_NOACCESS, SPR_NOACCESS,
94 &spr_read_generic, &spr_write_generic,
95 0x00000000);
96
97 spr_register(env, SPR_HID2, "HID2",
98 SPR_NOACCESS, SPR_NOACCESS,
99 &spr_read_generic, &spr_write_generic,
100 0x00000000);
101 }
102
register_755_sprs(CPUPPCState * env)103 static void register_755_sprs(CPUPPCState *env)
104 {
105 /* L2 cache control */
106 spr_register(env, SPR_L2CR, "L2CR",
107 SPR_NOACCESS, SPR_NOACCESS,
108 &spr_read_generic, spr_access_nop,
109 0x00000000);
110
111 spr_register(env, SPR_L2PMCR, "L2PMCR",
112 SPR_NOACCESS, SPR_NOACCESS,
113 &spr_read_generic, &spr_write_generic,
114 0x00000000);
115 }
116
117 /* SPR common to all 7xx PowerPC implementations */
register_7xx_sprs(CPUPPCState * env)118 static void register_7xx_sprs(CPUPPCState *env)
119 {
120 /* Breakpoints */
121 spr_register_kvm(env, SPR_DABR, "DABR",
122 SPR_NOACCESS, SPR_NOACCESS,
123 &spr_read_generic, &spr_write_generic,
124 KVM_REG_PPC_DABR, 0x00000000);
125
126 spr_register(env, SPR_IABR, "IABR",
127 SPR_NOACCESS, SPR_NOACCESS,
128 &spr_read_generic, &spr_write_generic,
129 0x00000000);
130 /* Cache management */
131 spr_register(env, SPR_ICTC, "ICTC",
132 SPR_NOACCESS, SPR_NOACCESS,
133 &spr_read_generic, &spr_write_generic,
134 0x00000000);
135 /* Performance monitors */
136 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
137 SPR_NOACCESS, SPR_NOACCESS,
138 &spr_read_generic, &spr_write_generic,
139 0x00000000);
140
141 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
142 SPR_NOACCESS, SPR_NOACCESS,
143 &spr_read_generic, &spr_write_generic,
144 0x00000000);
145
146 spr_register(env, SPR_7XX_PMC1, "PMC1",
147 SPR_NOACCESS, SPR_NOACCESS,
148 &spr_read_generic, &spr_write_generic,
149 0x00000000);
150
151 spr_register(env, SPR_7XX_PMC2, "PMC2",
152 SPR_NOACCESS, SPR_NOACCESS,
153 &spr_read_generic, &spr_write_generic,
154 0x00000000);
155
156 spr_register(env, SPR_7XX_PMC3, "PMC3",
157 SPR_NOACCESS, SPR_NOACCESS,
158 &spr_read_generic, &spr_write_generic,
159 0x00000000);
160
161 spr_register(env, SPR_7XX_PMC4, "PMC4",
162 SPR_NOACCESS, SPR_NOACCESS,
163 &spr_read_generic, &spr_write_generic,
164 0x00000000);
165
166 spr_register(env, SPR_7XX_SIAR, "SIAR",
167 SPR_NOACCESS, SPR_NOACCESS,
168 &spr_read_generic, SPR_NOACCESS,
169 0x00000000);
170
171 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
172 &spr_read_ureg, SPR_NOACCESS,
173 &spr_read_ureg, SPR_NOACCESS,
174 0x00000000);
175
176 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
177 &spr_read_ureg, SPR_NOACCESS,
178 &spr_read_ureg, SPR_NOACCESS,
179 0x00000000);
180
181 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
182 &spr_read_ureg, SPR_NOACCESS,
183 &spr_read_ureg, SPR_NOACCESS,
184 0x00000000);
185
186 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
187 &spr_read_ureg, SPR_NOACCESS,
188 &spr_read_ureg, SPR_NOACCESS,
189 0x00000000);
190
191 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
192 &spr_read_ureg, SPR_NOACCESS,
193 &spr_read_ureg, SPR_NOACCESS,
194 0x00000000);
195
196 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
197 &spr_read_ureg, SPR_NOACCESS,
198 &spr_read_ureg, SPR_NOACCESS,
199 0x00000000);
200
201 spr_register(env, SPR_7XX_USIAR, "USIAR",
202 &spr_read_ureg, SPR_NOACCESS,
203 &spr_read_ureg, SPR_NOACCESS,
204 0x00000000);
205 /* External access control */
206 spr_register(env, SPR_EAR, "EAR",
207 SPR_NOACCESS, SPR_NOACCESS,
208 &spr_read_generic, &spr_write_generic,
209 0x00000000);
210
211 /* Hardware implementation registers */
212 spr_register(env, SPR_HID0, "HID0",
213 SPR_NOACCESS, SPR_NOACCESS,
214 &spr_read_generic, &spr_write_generic,
215 0x00000000);
216
217 spr_register(env, SPR_HID1, "HID1",
218 SPR_NOACCESS, SPR_NOACCESS,
219 &spr_read_generic, &spr_write_generic,
220 0x00000000);
221 }
222
223 #ifdef TARGET_PPC64
register_amr_sprs(CPUPPCState * env)224 static void register_amr_sprs(CPUPPCState *env)
225 {
226 #ifndef CONFIG_USER_ONLY
227 /*
228 * Virtual Page Class Key protection
229 *
230 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
231 * userspace accessible, 29 is privileged. So we only need to set
232 * the kvm ONE_REG id on one of them, we use 29
233 */
234 spr_register(env, SPR_UAMR, "UAMR",
235 &spr_read_generic, &spr_write_amr,
236 &spr_read_generic, &spr_write_amr,
237 0);
238 spr_register_kvm_hv(env, SPR_AMR, "AMR",
239 SPR_NOACCESS, SPR_NOACCESS,
240 &spr_read_generic, &spr_write_amr,
241 &spr_read_generic, &spr_write_generic,
242 KVM_REG_PPC_AMR, 0);
243 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
244 SPR_NOACCESS, SPR_NOACCESS,
245 &spr_read_generic, &spr_write_uamor,
246 &spr_read_generic, &spr_write_generic,
247 KVM_REG_PPC_UAMOR, 0);
248 spr_register_hv(env, SPR_AMOR, "AMOR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 SPR_NOACCESS, SPR_NOACCESS,
251 &spr_read_generic, &spr_core_lpar_write_generic,
252 0);
253 #endif /* !CONFIG_USER_ONLY */
254 }
255
register_iamr_sprs(CPUPPCState * env)256 static void register_iamr_sprs(CPUPPCState *env)
257 {
258 #ifndef CONFIG_USER_ONLY
259 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
260 SPR_NOACCESS, SPR_NOACCESS,
261 &spr_read_generic, &spr_write_iamr,
262 &spr_read_generic, &spr_write_generic,
263 KVM_REG_PPC_IAMR, 0);
264 #endif /* !CONFIG_USER_ONLY */
265 }
266 #endif /* TARGET_PPC64 */
267
268 /* SPR specific to PowerPC 604 implementation */
register_604_sprs(CPUPPCState * env)269 static void register_604_sprs(CPUPPCState *env)
270 {
271 /* Processor identification */
272 spr_register(env, SPR_PIR, "PIR",
273 SPR_NOACCESS, SPR_NOACCESS,
274 &spr_read_generic, &spr_write_pir,
275 0x00000000);
276 /* Breakpoints */
277 spr_register(env, SPR_IABR, "IABR",
278 SPR_NOACCESS, SPR_NOACCESS,
279 &spr_read_generic, &spr_write_generic,
280 0x00000000);
281
282 spr_register_kvm(env, SPR_DABR, "DABR",
283 SPR_NOACCESS, SPR_NOACCESS,
284 &spr_read_generic, &spr_write_generic,
285 KVM_REG_PPC_DABR, 0x00000000);
286 /* Performance counters */
287 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
288 SPR_NOACCESS, SPR_NOACCESS,
289 &spr_read_generic, &spr_write_generic,
290 0x00000000);
291
292 spr_register(env, SPR_7XX_PMC1, "PMC1",
293 SPR_NOACCESS, SPR_NOACCESS,
294 &spr_read_generic, &spr_write_generic,
295 0x00000000);
296
297 spr_register(env, SPR_7XX_PMC2, "PMC2",
298 SPR_NOACCESS, SPR_NOACCESS,
299 &spr_read_generic, &spr_write_generic,
300 0x00000000);
301
302 spr_register(env, SPR_7XX_SIAR, "SIAR",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_generic, SPR_NOACCESS,
305 0x00000000);
306
307 spr_register(env, SPR_SDA, "SDA",
308 SPR_NOACCESS, SPR_NOACCESS,
309 &spr_read_generic, SPR_NOACCESS,
310 0x00000000);
311 /* External access control */
312 spr_register(env, SPR_EAR, "EAR",
313 SPR_NOACCESS, SPR_NOACCESS,
314 &spr_read_generic, &spr_write_generic,
315 0x00000000);
316
317 /* Hardware implementation registers */
318 spr_register(env, SPR_HID0, "HID0",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_generic, &spr_write_generic,
321 0x00000000);
322 }
323
register_604e_sprs(CPUPPCState * env)324 static void register_604e_sprs(CPUPPCState *env)
325 {
326 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_generic, &spr_write_generic,
329 0x00000000);
330
331 spr_register(env, SPR_7XX_PMC3, "PMC3",
332 SPR_NOACCESS, SPR_NOACCESS,
333 &spr_read_generic, &spr_write_generic,
334 0x00000000);
335
336 spr_register(env, SPR_7XX_PMC4, "PMC4",
337 SPR_NOACCESS, SPR_NOACCESS,
338 &spr_read_generic, &spr_write_generic,
339 0x00000000);
340 /* Hardware implementation registers */
341 spr_register(env, SPR_HID1, "HID1",
342 SPR_NOACCESS, SPR_NOACCESS,
343 &spr_read_generic, &spr_write_generic,
344 0x00000000);
345 }
346
347 /* SPR specific to PowerPC 603 implementation */
register_603_sprs(CPUPPCState * env)348 static void register_603_sprs(CPUPPCState *env)
349 {
350 /* External access control */
351 spr_register(env, SPR_EAR, "EAR",
352 SPR_NOACCESS, SPR_NOACCESS,
353 &spr_read_generic, &spr_write_generic,
354 0x00000000);
355 /* Breakpoints */
356 spr_register(env, SPR_IABR, "IABR",
357 SPR_NOACCESS, SPR_NOACCESS,
358 &spr_read_generic, &spr_write_generic,
359 0x00000000);
360
361 spr_register(env, SPR_HID0, "HID0",
362 SPR_NOACCESS, SPR_NOACCESS,
363 &spr_read_generic, &spr_write_generic,
364 0x00000000);
365
366 spr_register(env, SPR_HID1, "HID1",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_generic, &spr_write_generic,
369 0x00000000);
370 }
371
register_e300_sprs(CPUPPCState * env)372 static void register_e300_sprs(CPUPPCState *env)
373 {
374 /* hardware implementation registers */
375 spr_register(env, SPR_HID2, "HID2",
376 SPR_NOACCESS, SPR_NOACCESS,
377 &spr_read_generic, &spr_write_generic,
378 0x00000000);
379 /* Breakpoints */
380 spr_register(env, SPR_DABR, "DABR",
381 SPR_NOACCESS, SPR_NOACCESS,
382 &spr_read_generic, &spr_write_generic,
383 0x00000000);
384
385 spr_register(env, SPR_DABR2, "DABR2",
386 SPR_NOACCESS, SPR_NOACCESS,
387 &spr_read_generic, &spr_write_generic,
388 0x00000000);
389
390 spr_register(env, SPR_IABR2, "IABR2",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_generic, &spr_write_generic,
393 0x00000000);
394
395 spr_register(env, SPR_IBCR, "IBCR",
396 SPR_NOACCESS, SPR_NOACCESS,
397 &spr_read_generic, &spr_write_generic,
398 0x00000000);
399
400 spr_register(env, SPR_DBCR, "DBCR",
401 SPR_NOACCESS, SPR_NOACCESS,
402 &spr_read_generic, &spr_write_generic,
403 0x00000000);
404 }
405
406 /* SPR specific to PowerPC G2 implementation */
register_G2_sprs(CPUPPCState * env)407 static void register_G2_sprs(CPUPPCState *env)
408 {
409 /* Memory base address */
410 /* MBAR */
411 spr_register(env, SPR_MBAR, "MBAR",
412 SPR_NOACCESS, SPR_NOACCESS,
413 &spr_read_generic, &spr_write_generic,
414 0x00000000);
415 /* Exception processing */
416 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
417 SPR_NOACCESS, SPR_NOACCESS,
418 &spr_read_generic, &spr_write_generic,
419 0x00000000);
420 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
421 SPR_NOACCESS, SPR_NOACCESS,
422 &spr_read_generic, &spr_write_generic,
423 0x00000000);
424 /* Breakpoints */
425 spr_register(env, SPR_DABR, "DABR",
426 SPR_NOACCESS, SPR_NOACCESS,
427 &spr_read_generic, &spr_write_generic,
428 0x00000000);
429
430 spr_register(env, SPR_DABR2, "DABR2",
431 SPR_NOACCESS, SPR_NOACCESS,
432 &spr_read_generic, &spr_write_generic,
433 0x00000000);
434
435 spr_register(env, SPR_IABR, "IABR",
436 SPR_NOACCESS, SPR_NOACCESS,
437 &spr_read_generic, &spr_write_generic,
438 0x00000000);
439
440 spr_register(env, SPR_IABR2, "IABR2",
441 SPR_NOACCESS, SPR_NOACCESS,
442 &spr_read_generic, &spr_write_generic,
443 0x00000000);
444
445 spr_register(env, SPR_IBCR, "IBCR",
446 SPR_NOACCESS, SPR_NOACCESS,
447 &spr_read_generic, &spr_write_generic,
448 0x00000000);
449
450 spr_register(env, SPR_DBCR, "DBCR",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454
455 /* External access control */
456 spr_register(env, SPR_EAR, "EAR",
457 SPR_NOACCESS, SPR_NOACCESS,
458 &spr_read_generic, &spr_write_generic,
459 0x00000000);
460 /* Hardware implementation register */
461 spr_register(env, SPR_HID0, "HID0",
462 SPR_NOACCESS, SPR_NOACCESS,
463 &spr_read_generic, &spr_write_generic,
464 0x00000000);
465
466 spr_register(env, SPR_HID1, "HID1",
467 SPR_NOACCESS, SPR_NOACCESS,
468 &spr_read_generic, &spr_write_generic,
469 0x00000000);
470
471 spr_register(env, SPR_HID2, "HID2",
472 SPR_NOACCESS, SPR_NOACCESS,
473 &spr_read_generic, &spr_write_generic,
474 0x00000000);
475
476 /* SGPRs */
477 spr_register(env, SPR_SPRG4, "SPRG4",
478 SPR_NOACCESS, SPR_NOACCESS,
479 &spr_read_generic, &spr_write_generic,
480 0x00000000);
481 spr_register(env, SPR_SPRG5, "SPRG5",
482 SPR_NOACCESS, SPR_NOACCESS,
483 &spr_read_generic, &spr_write_generic,
484 0x00000000);
485 spr_register(env, SPR_SPRG6, "SPRG6",
486 SPR_NOACCESS, SPR_NOACCESS,
487 &spr_read_generic, &spr_write_generic,
488 0x00000000);
489 spr_register(env, SPR_SPRG7, "SPRG7",
490 SPR_NOACCESS, SPR_NOACCESS,
491 &spr_read_generic, &spr_write_generic,
492 0x00000000);
493 }
494
register_74xx_sprs(CPUPPCState * env)495 static void register_74xx_sprs(CPUPPCState *env)
496 {
497 /* Breakpoints */
498 spr_register_kvm(env, SPR_DABR, "DABR",
499 SPR_NOACCESS, SPR_NOACCESS,
500 &spr_read_generic, &spr_write_generic,
501 KVM_REG_PPC_DABR, 0x00000000);
502
503 spr_register(env, SPR_IABR, "IABR",
504 SPR_NOACCESS, SPR_NOACCESS,
505 &spr_read_generic, &spr_write_generic,
506 0x00000000);
507 /* Cache management */
508 spr_register(env, SPR_ICTC, "ICTC",
509 SPR_NOACCESS, SPR_NOACCESS,
510 &spr_read_generic, &spr_write_generic,
511 0x00000000);
512 /* Performance monitors */
513 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
514 SPR_NOACCESS, SPR_NOACCESS,
515 &spr_read_generic, &spr_write_generic,
516 0x00000000);
517
518 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
519 SPR_NOACCESS, SPR_NOACCESS,
520 &spr_read_generic, &spr_write_generic,
521 0x00000000);
522
523 spr_register(env, SPR_7XX_PMC1, "PMC1",
524 SPR_NOACCESS, SPR_NOACCESS,
525 &spr_read_generic, &spr_write_generic,
526 0x00000000);
527
528 spr_register(env, SPR_7XX_PMC2, "PMC2",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_generic, &spr_write_generic,
531 0x00000000);
532
533 spr_register(env, SPR_7XX_PMC3, "PMC3",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_generic, &spr_write_generic,
536 0x00000000);
537
538 spr_register(env, SPR_7XX_PMC4, "PMC4",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_generic, &spr_write_generic,
541 0x00000000);
542
543 spr_register(env, SPR_7XX_SIAR, "SIAR",
544 SPR_NOACCESS, SPR_NOACCESS,
545 &spr_read_generic, SPR_NOACCESS,
546 0x00000000);
547
548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
549 &spr_read_ureg, SPR_NOACCESS,
550 &spr_read_ureg, SPR_NOACCESS,
551 0x00000000);
552
553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
554 &spr_read_ureg, SPR_NOACCESS,
555 &spr_read_ureg, SPR_NOACCESS,
556 0x00000000);
557
558 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
559 &spr_read_ureg, SPR_NOACCESS,
560 &spr_read_ureg, SPR_NOACCESS,
561 0x00000000);
562
563 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
564 &spr_read_ureg, SPR_NOACCESS,
565 &spr_read_ureg, SPR_NOACCESS,
566 0x00000000);
567
568 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
569 &spr_read_ureg, SPR_NOACCESS,
570 &spr_read_ureg, SPR_NOACCESS,
571 0x00000000);
572
573 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
574 &spr_read_ureg, SPR_NOACCESS,
575 &spr_read_ureg, SPR_NOACCESS,
576 0x00000000);
577
578 spr_register(env, SPR_7XX_USIAR, "USIAR",
579 &spr_read_ureg, SPR_NOACCESS,
580 &spr_read_ureg, SPR_NOACCESS,
581 0x00000000);
582 /* External access control */
583 spr_register(env, SPR_EAR, "EAR",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_generic, &spr_write_generic,
586 0x00000000);
587
588 /* Processor identification */
589 spr_register(env, SPR_PIR, "PIR",
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_generic, &spr_write_pir,
592 0x00000000);
593
594 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_generic, &spr_write_generic,
597 0x00000000);
598
599 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
600 &spr_read_ureg, SPR_NOACCESS,
601 &spr_read_ureg, SPR_NOACCESS,
602 0x00000000);
603
604 spr_register(env, SPR_BAMR, "BAMR",
605 SPR_NOACCESS, SPR_NOACCESS,
606 &spr_read_generic, &spr_write_generic,
607 0x00000000);
608
609 spr_register(env, SPR_MSSCR0, "MSSCR0",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_generic, &spr_write_generic,
612 0x00000000);
613 /* Hardware implementation registers */
614 spr_register(env, SPR_HID0, "HID0",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_generic, &spr_write_generic,
617 0x00000000);
618
619 spr_register(env, SPR_HID1, "HID1",
620 SPR_NOACCESS, SPR_NOACCESS,
621 &spr_read_generic, &spr_write_generic,
622 0x00000000);
623 /* Altivec */
624 spr_register(env, SPR_VRSAVE, "VRSAVE",
625 &spr_read_generic, &spr_write_generic,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628
629 spr_register(env, SPR_L2CR, "L2CR",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_generic, spr_access_nop,
632 0x00000000);
633 }
634
register_l3_ctrl(CPUPPCState * env)635 static void register_l3_ctrl(CPUPPCState *env)
636 {
637 /* L3CR */
638 spr_register(env, SPR_L3CR, "L3CR",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 /* L3ITCR0 */
643 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 0x00000000);
647 /* L3PM */
648 spr_register(env, SPR_L3PM, "L3PM",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_generic, &spr_write_generic,
651 0x00000000);
652 }
653
654 /* PowerPC BookE SPR */
register_BookE_sprs(CPUPPCState * env,uint64_t ivor_mask)655 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
656 {
657 const char *ivor_names[64] = {
658 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
659 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
660 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
661 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
662 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
663 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
664 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
665 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
666 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
667 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
668 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
669 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
670 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
671 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
672 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
673 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
674 };
675 #define SPR_BOOKE_IVORxx (-1)
676 int ivor_sprn[64] = {
677 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
678 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
679 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
680 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
685 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
686 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
687 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
693 };
694 int i;
695
696 /* Interrupt processing */
697 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, &spr_write_generic,
700 0x00000000);
701 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, &spr_write_generic,
704 0x00000000);
705 /* Debug */
706 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
707 SPR_NOACCESS, SPR_NOACCESS,
708 &spr_read_generic, &spr_write_generic,
709 0x00000000);
710
711 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715
716 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, &spr_write_generic,
719 0x00000000);
720
721 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_generic, &spr_write_generic,
724 0x00000000);
725
726 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_40x_dbcr0,
729 0x00000000);
730
731 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_generic, &spr_write_generic,
734 0x00000000);
735
736 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_generic, &spr_write_generic,
747 0x00000000);
748
749 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_generic, &spr_write_clear,
752 0x00000000);
753 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757 spr_register(env, SPR_BOOKE_ESR, "ESR",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_generic, &spr_write_generic,
760 0x00000000);
761 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_excp_prefix,
764 0x00000000);
765 /* Exception vectors */
766 for (i = 0; i < 64; i++) {
767 if (ivor_mask & (1ULL << i)) {
768 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
769 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
770 exit(1);
771 }
772 spr_register(env, ivor_sprn[i], ivor_names[i],
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_generic, &spr_write_excp_vector,
775 0x00000000);
776 }
777 }
778 spr_register(env, SPR_BOOKE_PID, "PID",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_booke_pid,
781 0x00000000);
782 spr_register(env, SPR_BOOKE_TCR, "TCR",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_generic, &spr_write_booke_tcr,
785 0x00000000);
786 spr_register(env, SPR_BOOKE_TSR, "TSR",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_generic, &spr_write_booke_tsr,
789 0x00000000);
790 /* Timer */
791 spr_register(env, SPR_DECR, "DECR",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_decr, &spr_write_decr,
794 0x00000000);
795 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
796 SPR_NOACCESS, SPR_NOACCESS,
797 SPR_NOACCESS, &spr_write_generic32,
798 0x00000000);
799 /* SPRGs */
800 spr_register(env, SPR_USPRG0, "USPRG0",
801 &spr_read_generic, &spr_write_generic,
802 &spr_read_generic, &spr_write_generic,
803 0x00000000);
804 spr_register(env, SPR_SPRG4, "SPRG4",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 spr_register(env, SPR_SPRG5, "SPRG5",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_generic, &spr_write_generic,
811 0x00000000);
812 spr_register(env, SPR_SPRG6, "SPRG6",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816 spr_register(env, SPR_SPRG7, "SPRG7",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_generic, &spr_write_generic,
823 0x00000000);
824 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828 }
829
830 #if !defined(CONFIG_USER_ONLY)
register_tlbncfg(uint32_t assoc,uint32_t minsize,uint32_t maxsize,uint32_t flags,uint32_t nentries)831 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
832 uint32_t maxsize, uint32_t flags,
833 uint32_t nentries)
834 {
835 return (assoc << TLBnCFG_ASSOC_SHIFT) |
836 (minsize << TLBnCFG_MINSIZE_SHIFT) |
837 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
838 flags | nentries;
839 }
840 #endif /* !CONFIG_USER_ONLY */
841
842 /* BookE 2.06 storage control registers */
register_BookE206_sprs(CPUPPCState * env,uint32_t mas_mask,uint32_t * tlbncfg,uint32_t mmucfg)843 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
844 uint32_t *tlbncfg, uint32_t mmucfg)
845 {
846 #if !defined(CONFIG_USER_ONLY)
847 const char *mas_names[8] = {
848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
849 };
850 int mas_sprn[8] = {
851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
853 };
854 int i;
855
856 /* TLB assist registers */
857 for (i = 0; i < 8; i++) {
858 if (mas_mask & (1 << i)) {
859 spr_register(env, mas_sprn[i], mas_names[i],
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic,
862 (i == 2 && (env->insns_flags & PPC_64B))
863 ? &spr_write_generic : &spr_write_generic32,
864 0x00000000);
865 }
866 }
867 if (env->nb_pids > 1) {
868 spr_register(env, SPR_BOOKE_PID1, "PID1",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, &spr_write_booke_pid,
871 0x00000000);
872 }
873 if (env->nb_pids > 2) {
874 spr_register(env, SPR_BOOKE_PID2, "PID2",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, &spr_write_booke_pid,
877 0x00000000);
878 }
879
880 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_eplc,
883 0x00000000);
884 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_epsc,
887 0x00000000);
888
889 spr_register(env, SPR_MMUCFG, "MMUCFG",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 mmucfg);
893 switch (env->nb_ways) {
894 case 4:
895 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 tlbncfg[3]);
899 /* Fallthru */
900 case 3:
901 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 tlbncfg[2]);
905 /* Fallthru */
906 case 2:
907 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, SPR_NOACCESS,
910 tlbncfg[1]);
911 /* Fallthru */
912 case 1:
913 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, SPR_NOACCESS,
916 tlbncfg[0]);
917 /* Fallthru */
918 case 0:
919 default:
920 break;
921 }
922 #endif
923 }
924
925 /* SPR specific to PowerPC 440 implementation */
register_440_sprs(CPUPPCState * env)926 static void register_440_sprs(CPUPPCState *env)
927 {
928 /* Cache control */
929 spr_register(env, SPR_440_DNV0, "DNV0",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933
934 spr_register(env, SPR_440_DNV1, "DNV1",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938
939 spr_register(env, SPR_440_DNV2, "DNV2",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943
944 spr_register(env, SPR_440_DNV3, "DNV3",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948
949 spr_register(env, SPR_440_DTV0, "DTV0",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953
954 spr_register(env, SPR_440_DTV1, "DTV1",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958
959 spr_register(env, SPR_440_DTV2, "DTV2",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963
964 spr_register(env, SPR_440_DTV3, "DTV3",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968
969 spr_register(env, SPR_440_DVLIM, "DVLIM",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973
974 spr_register(env, SPR_440_INV0, "INV0",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978
979 spr_register(env, SPR_440_INV1, "INV1",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983
984 spr_register(env, SPR_440_INV2, "INV2",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988
989 spr_register(env, SPR_440_INV3, "INV3",
990 SPR_NOACCESS, SPR_NOACCESS,
991 &spr_read_generic, &spr_write_generic,
992 0x00000000);
993
994 spr_register(env, SPR_440_ITV0, "ITV0",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998
999 spr_register(env, SPR_440_ITV1, "ITV1",
1000 SPR_NOACCESS, SPR_NOACCESS,
1001 &spr_read_generic, &spr_write_generic,
1002 0x00000000);
1003
1004 spr_register(env, SPR_440_ITV2, "ITV2",
1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008
1009 spr_register(env, SPR_440_ITV3, "ITV3",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013
1014 spr_register(env, SPR_440_IVLIM, "IVLIM",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* Cache debug */
1019 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, SPR_NOACCESS,
1022 0x00000000);
1023
1024 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, SPR_NOACCESS,
1027 0x00000000);
1028
1029 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, SPR_NOACCESS,
1032 0x00000000);
1033
1034 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, SPR_NOACCESS,
1037 0x00000000);
1038
1039 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, SPR_NOACCESS,
1042 0x00000000);
1043
1044 spr_register(env, SPR_440_DBDR, "DBDR",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 /* Processor control */
1049 spr_register(env, SPR_4xx_CCR0, "CCR0",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_generic, &spr_write_generic,
1052 0x00000000);
1053 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1054 SPR_NOACCESS, SPR_NOACCESS,
1055 &spr_read_generic, SPR_NOACCESS,
1056 0x00000000);
1057 /* Storage control */
1058 spr_register(env, SPR_440_MMUCR, "MMUCR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062
1063 /* Processor identification */
1064 spr_register(env, SPR_BOOKE_PIR, "PIR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_pir,
1067 0x00000000);
1068
1069 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073
1074 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_generic, &spr_write_generic,
1077 0x00000000);
1078
1079 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083
1084 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_generic,
1087 0x00000000);
1088 }
1089
1090 /* SPR shared between PowerPC 40x implementations */
register_40x_sprs(CPUPPCState * env)1091 static void register_40x_sprs(CPUPPCState *env)
1092 {
1093 /* Cache */
1094 /* not emulated, as QEMU do not emulate caches */
1095 spr_register(env, SPR_40x_DCCR, "DCCR",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 /* not emulated, as QEMU do not emulate caches */
1100 spr_register(env, SPR_40x_ICCR, "ICCR",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* not emulated, as QEMU do not emulate caches */
1105 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, SPR_NOACCESS,
1108 0x00000000);
1109 /* Exception */
1110 spr_register(env, SPR_40x_DEAR, "DEAR",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 spr_register(env, SPR_40x_ESR, "ESR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 spr_register(env, SPR_40x_EVPR, "EVPR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 &spr_read_generic, &spr_write_excp_prefix,
1121 0x00000000);
1122 spr_register(env, SPR_40x_SRR2, "SRR2",
1123 &spr_read_generic, &spr_write_generic,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 spr_register(env, SPR_40x_SRR3, "SRR3",
1127 &spr_read_generic, &spr_write_generic,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* Timers */
1131 spr_register(env, SPR_40x_PIT, "PIT",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_40x_pit, &spr_write_40x_pit,
1134 0x00000000);
1135 spr_register(env, SPR_40x_TCR, "TCR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_40x_tcr,
1138 0x00000000);
1139 spr_register(env, SPR_40x_TSR, "TSR",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_generic, &spr_write_40x_tsr,
1142 0x00000000);
1143 }
1144
1145 /* SPR specific to PowerPC 405 implementation */
register_405_sprs(CPUPPCState * env)1146 static void register_405_sprs(CPUPPCState *env)
1147 {
1148 /* MMU */
1149 spr_register(env, SPR_40x_PID, "PID",
1150 SPR_NOACCESS, SPR_NOACCESS,
1151 &spr_read_generic, &spr_write_40x_pid,
1152 0x00000000);
1153 spr_register(env, SPR_4xx_CCR0, "CCR0",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_generic,
1156 0x00700000);
1157 /* Debug interface */
1158 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_40x_dbcr0,
1161 0x00000000);
1162
1163 spr_register(env, SPR_405_DBCR1, "DBCR1",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
1168 spr_register(env, SPR_40x_DBSR, "DBSR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_clear,
1171 /* Last reset was system reset */
1172 0x00000300);
1173
1174 spr_register(env, SPR_40x_DAC1, "DAC1",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 spr_register(env, SPR_40x_DAC2, "DAC2",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182
1183 spr_register(env, SPR_405_DVC1, "DVC1",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187
1188 spr_register(env, SPR_405_DVC2, "DVC2",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192
1193 spr_register(env, SPR_40x_IAC1, "IAC1",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 spr_register(env, SPR_40x_IAC2, "IAC2",
1198 SPR_NOACCESS, SPR_NOACCESS,
1199 &spr_read_generic, &spr_write_generic,
1200 0x00000000);
1201
1202 spr_register(env, SPR_405_IAC3, "IAC3",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206
1207 spr_register(env, SPR_405_IAC4, "IAC4",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 /* Storage control */
1212 spr_register(env, SPR_405_SLER, "SLER",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_40x_sler,
1215 0x00000000);
1216 spr_register(env, SPR_40x_ZPR, "ZPR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220
1221 spr_register(env, SPR_405_SU0R, "SU0R",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* SPRG */
1226 spr_register(env, SPR_USPRG0, "USPRG0",
1227 &spr_read_ureg, SPR_NOACCESS,
1228 &spr_read_ureg, SPR_NOACCESS,
1229 0x00000000);
1230 spr_register(env, SPR_SPRG4, "SPRG4",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0x00000000);
1234 spr_register(env, SPR_SPRG5, "SPRG5",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 spr_register(env, SPR_SPRG6, "SPRG6",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 spr_read_generic, &spr_write_generic,
1241 0x00000000);
1242 spr_register(env, SPR_SPRG7, "SPRG7",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246
1247 /* Bus access control */
1248 /* not emulated, as QEMU never does speculative access */
1249 spr_register(env, SPR_40x_SGR, "SGR",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0xFFFFFFFF);
1253 /* not emulated, as QEMU do not emulate caches */
1254 spr_register(env, SPR_40x_DCWR, "DCWR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 }
1259
1260
register_5xx_8xx_sprs(CPUPPCState * env)1261 static void register_5xx_8xx_sprs(CPUPPCState *env)
1262 {
1263 /* Exception processing */
1264 spr_register_kvm(env, SPR_DSISR, "DSISR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 KVM_REG_PPC_DSISR, 0x00000000);
1268 spr_register_kvm(env, SPR_DAR, "DAR",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 KVM_REG_PPC_DAR, 0x00000000);
1272 /* Timer */
1273 spr_register(env, SPR_DECR, "DECR",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_decr, &spr_write_decr,
1276 0x00000000);
1277
1278 spr_register(env, SPR_MPC_EIE, "EIE",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
1282
1283 spr_register(env, SPR_MPC_EID, "EID",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287
1288 spr_register(env, SPR_MPC_NRI, "NRI",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292
1293 spr_register(env, SPR_MPC_CMPA, "CMPA",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297
1298 spr_register(env, SPR_MPC_CMPB, "CMPB",
1299 SPR_NOACCESS, SPR_NOACCESS,
1300 &spr_read_generic, &spr_write_generic,
1301 0x00000000);
1302
1303 spr_register(env, SPR_MPC_CMPC, "CMPC",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307
1308 spr_register(env, SPR_MPC_CMPD, "CMPD",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312
1313 spr_register(env, SPR_MPC_ECR, "ECR",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317
1318 spr_register(env, SPR_MPC_DER, "DER",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322
1323 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327
1328 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332
1333 spr_register(env, SPR_MPC_CMPE, "CMPE",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_generic, &spr_write_generic,
1336 0x00000000);
1337
1338 spr_register(env, SPR_MPC_CMPF, "CMPF",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342
1343 spr_register(env, SPR_MPC_CMPG, "CMPG",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347
1348 spr_register(env, SPR_MPC_CMPH, "CMPH",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352
1353 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357
1358 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362
1363 spr_register(env, SPR_MPC_BAR, "BAR",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367
1368 spr_register(env, SPR_MPC_DPDR, "DPDR",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372
1373 spr_register(env, SPR_MPC_IMMR, "IMMR",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 }
1378
register_5xx_sprs(CPUPPCState * env)1379 static void register_5xx_sprs(CPUPPCState *env)
1380 {
1381 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385
1386 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390
1391 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395
1396 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400
1401 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_generic,
1404 0x00000000);
1405
1406 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410
1411 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415
1416 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000);
1420
1421 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425
1426 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_generic,
1429 0x00000000);
1430
1431 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435
1436 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440
1441 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445
1446 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
1450
1451 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455
1456 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460
1461 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465
1466 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470
1471 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475
1476 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480
1481 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 }
1486
register_8xx_sprs(CPUPPCState * env)1487 static void register_8xx_sprs(CPUPPCState *env)
1488 {
1489
1490 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494
1495 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499
1500 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504
1505 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509
1510 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514
1515 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_generic,
1518 0x00000000);
1519
1520 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524
1525 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1526 SPR_NOACCESS, SPR_NOACCESS,
1527 &spr_read_generic, &spr_write_generic,
1528 0x00000000);
1529
1530 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534
1535 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539
1540 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 &spr_read_generic, &spr_write_generic,
1543 0x00000000);
1544
1545 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549
1550 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554
1555 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559
1560 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564
1565 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1566 SPR_NOACCESS, SPR_NOACCESS,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569
1570 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574
1575 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1576 SPR_NOACCESS, SPR_NOACCESS,
1577 &spr_read_generic, &spr_write_generic,
1578 0x00000000);
1579
1580 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584
1585 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_generic,
1588 0x00000000);
1589
1590 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594
1595 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599
1600 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_generic,
1603 0x00000000);
1604
1605 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609
1610 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614 }
1615
1616 /*
1617 * AMR => SPR 29 (Power 2.04)
1618 * CTRL => SPR 136 (Power 2.04)
1619 * CTRL => SPR 152 (Power 2.04)
1620 * SCOMC => SPR 276 (64 bits ?)
1621 * SCOMD => SPR 277 (64 bits ?)
1622 * TBU40 => SPR 286 (Power 2.04 hypv)
1623 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1624 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1625 * HDSISR => SPR 306 (Power 2.04 hypv)
1626 * HDAR => SPR 307 (Power 2.04 hypv)
1627 * PURR => SPR 309 (Power 2.04 hypv)
1628 * HDEC => SPR 310 (Power 2.04 hypv)
1629 * HIOR => SPR 311 (hypv)
1630 * RMOR => SPR 312 (970)
1631 * HRMOR => SPR 313 (Power 2.04 hypv)
1632 * HSRR0 => SPR 314 (Power 2.04 hypv)
1633 * HSRR1 => SPR 315 (Power 2.04 hypv)
1634 * LPIDR => SPR 317 (970)
1635 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1636 * EPR => SPR 702 (Power 2.04 emb)
1637 * perf => 768-783 (Power 2.04)
1638 * perf => 784-799 (Power 2.04)
1639 * PPR => SPR 896 (Power 2.04)
1640 * DABRX => 1015 (Power 2.04 hypv)
1641 * FPECR => SPR 1022 (?)
1642 * ... and more (thermal management, performance counters, ...)
1643 */
1644
1645 /*****************************************************************************/
1646 /* Exception vectors models */
init_excp_4xx(CPUPPCState * env)1647 static void init_excp_4xx(CPUPPCState *env)
1648 {
1649 #if !defined(CONFIG_USER_ONLY)
1650 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1651 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1652 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1653 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1654 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1655 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1656 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1657 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1658 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1659 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1660 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1661 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1662 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1663 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1664 env->ivor_mask = 0x0000FFF0UL;
1665 env->ivpr_mask = 0xFFFF0000UL;
1666 /* Hardware reset vector */
1667 env->hreset_vector = 0xFFFFFFFCUL;
1668 #endif
1669 }
1670
init_excp_MPC5xx(CPUPPCState * env)1671 static void init_excp_MPC5xx(CPUPPCState *env)
1672 {
1673 #if !defined(CONFIG_USER_ONLY)
1674 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1675 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1676 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1677 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1678 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1679 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1680 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1681 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1682 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1683 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1684 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1685 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1686 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1687 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1688 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1689 env->ivor_mask = 0x0000FFF0UL;
1690 env->ivpr_mask = 0xFFFF0000UL;
1691 /* Hardware reset vector */
1692 env->hreset_vector = 0x00000100UL;
1693 #endif
1694 }
1695
init_excp_MPC8xx(CPUPPCState * env)1696 static void init_excp_MPC8xx(CPUPPCState *env)
1697 {
1698 #if !defined(CONFIG_USER_ONLY)
1699 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1700 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1701 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1702 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1703 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1704 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1705 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1706 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1707 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1709 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1710 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1711 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1713 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1714 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1715 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1716 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1717 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1718 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1719 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1720 env->ivor_mask = 0x0000FFF0UL;
1721 env->ivpr_mask = 0xFFFF0000UL;
1722 /* Hardware reset vector */
1723 env->hreset_vector = 0x00000100UL;
1724 #endif
1725 }
1726
init_excp_G2(CPUPPCState * env)1727 static void init_excp_G2(CPUPPCState *env)
1728 {
1729 #if !defined(CONFIG_USER_ONLY)
1730 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1731 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1732 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1733 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1734 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1735 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1736 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1737 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1738 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1739 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1740 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1741 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1742 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1743 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1744 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1745 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1746 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1747 /* Hardware reset vector */
1748 env->hreset_vector = 0x00000100UL;
1749 #endif
1750 }
1751
init_excp_e200(CPUPPCState * env,target_ulong ivpr_mask)1752 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1753 {
1754 #if !defined(CONFIG_USER_ONLY)
1755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1772 /*
1773 * These two are the same IVOR as POWERPC_EXCP_VPU and
1774 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1775 * powerpc_excp().
1776 */
1777 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1778 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1779
1780 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1781 env->ivor_mask = 0x0000FFF7UL;
1782 env->ivpr_mask = ivpr_mask;
1783 /* Hardware reset vector */
1784 env->hreset_vector = 0xFFFFFFFCUL;
1785 #endif
1786 }
1787
init_excp_BookE(CPUPPCState * env)1788 static void init_excp_BookE(CPUPPCState *env)
1789 {
1790 #if !defined(CONFIG_USER_ONLY)
1791 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1804 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1805 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1806 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1807 env->ivor_mask = 0x0000FFF0UL;
1808 env->ivpr_mask = 0xFFFF0000UL;
1809 /* Hardware reset vector */
1810 env->hreset_vector = 0xFFFFFFFCUL;
1811 #endif
1812 }
1813
init_excp_603(CPUPPCState * env)1814 static void init_excp_603(CPUPPCState *env)
1815 {
1816 #if !defined(CONFIG_USER_ONLY)
1817 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1818 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1819 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1820 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1821 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1822 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1823 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1824 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1825 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1826 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1827 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1828 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1829 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1830 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1831 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1832 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1833 /* Hardware reset vector */
1834 env->hreset_vector = 0x00000100UL;
1835 #endif
1836 }
1837
init_excp_604(CPUPPCState * env)1838 static void init_excp_604(CPUPPCState *env)
1839 {
1840 #if !defined(CONFIG_USER_ONLY)
1841 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1849 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1850 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1851 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1852 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1853 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1854 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1855 /* Hardware reset vector */
1856 env->hreset_vector = 0x00000100UL;
1857 #endif
1858 }
1859
init_excp_7x0(CPUPPCState * env)1860 static void init_excp_7x0(CPUPPCState *env)
1861 {
1862 #if !defined(CONFIG_USER_ONLY)
1863 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1864 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1865 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1866 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1867 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1868 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1869 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1870 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1871 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1872 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1873 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1874 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1875 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1876 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1877 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1878 /* Hardware reset vector */
1879 env->hreset_vector = 0x00000100UL;
1880 #endif
1881 }
1882
init_excp_750cl(CPUPPCState * env)1883 static void init_excp_750cl(CPUPPCState *env)
1884 {
1885 #if !defined(CONFIG_USER_ONLY)
1886 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1887 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1888 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1889 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1890 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1891 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1892 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1893 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1894 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1895 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1896 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1897 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1900 /* Hardware reset vector */
1901 env->hreset_vector = 0x00000100UL;
1902 #endif
1903 }
1904
init_excp_750cx(CPUPPCState * env)1905 static void init_excp_750cx(CPUPPCState *env)
1906 {
1907 #if !defined(CONFIG_USER_ONLY)
1908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1918 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1919 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1920 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1921 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1922 /* Hardware reset vector */
1923 env->hreset_vector = 0x00000100UL;
1924 #endif
1925 }
1926
1927 /* XXX: Check if this is correct */
init_excp_7x5(CPUPPCState * env)1928 static void init_excp_7x5(CPUPPCState *env)
1929 {
1930 #if !defined(CONFIG_USER_ONLY)
1931 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1932 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1933 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1934 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1935 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1936 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1937 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1938 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1939 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1940 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1941 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1942 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1943 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1944 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1945 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1946 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1947 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1948 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1949 /* Hardware reset vector */
1950 env->hreset_vector = 0x00000100UL;
1951 #endif
1952 }
1953
init_excp_7400(CPUPPCState * env)1954 static void init_excp_7400(CPUPPCState *env)
1955 {
1956 #if !defined(CONFIG_USER_ONLY)
1957 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1958 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1959 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1960 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1961 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1962 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1963 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1964 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1965 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1966 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1967 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1968 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1969 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1970 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1971 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1972 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1973 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1974 /* Hardware reset vector */
1975 env->hreset_vector = 0x00000100UL;
1976 #endif
1977 }
1978
init_excp_7450(CPUPPCState * env)1979 static void init_excp_7450(CPUPPCState *env)
1980 {
1981 #if !defined(CONFIG_USER_ONLY)
1982 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1983 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1984 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1985 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1986 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1987 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1988 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1989 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1990 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1991 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1992 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1993 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1994 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1998 /* Hardware reset vector */
1999 env->hreset_vector = 0x00000100UL;
2000 #endif
2001 }
2002
2003 #if defined(TARGET_PPC64)
init_excp_970(CPUPPCState * env)2004 static void init_excp_970(CPUPPCState *env)
2005 {
2006 #if !defined(CONFIG_USER_ONLY)
2007 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2008 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2009 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2010 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2011 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2012 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2018 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2021 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2022 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2024 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2025 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2026 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2027 /* Hardware reset vector */
2028 env->hreset_vector = 0x0000000000000100ULL;
2029 #endif
2030 }
2031
init_excp_POWER7(CPUPPCState * env)2032 static void init_excp_POWER7(CPUPPCState *env)
2033 {
2034 #if !defined(CONFIG_USER_ONLY)
2035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2038 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2040 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2046 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2049 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2050 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2051 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2052 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2053 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2054 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2055 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2056 /* Hardware reset vector */
2057 env->hreset_vector = 0x0000000000000100ULL;
2058 #endif
2059 }
2060
init_excp_POWER8(CPUPPCState * env)2061 static void init_excp_POWER8(CPUPPCState *env)
2062 {
2063 init_excp_POWER7(env);
2064
2065 #if !defined(CONFIG_USER_ONLY)
2066 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2067 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2068 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2069 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2070
2071 /* Userland exceptions without vector value in PowerISA v3.1 */
2072 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2073 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2074 #endif
2075 }
2076
init_excp_POWER9(CPUPPCState * env)2077 static void init_excp_POWER9(CPUPPCState *env)
2078 {
2079 init_excp_POWER8(env);
2080
2081 #if !defined(CONFIG_USER_ONLY)
2082 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2083 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2084 #endif
2085 }
2086
init_excp_POWER10(CPUPPCState * env)2087 static void init_excp_POWER10(CPUPPCState *env)
2088 {
2089 init_excp_POWER9(env);
2090 }
2091
2092 #endif
2093
check_pow_hid0(CPUPPCState * env)2094 static int check_pow_hid0(CPUPPCState *env)
2095 {
2096 if (env->spr[SPR_HID0] & 0x00E00000) {
2097 return 1;
2098 }
2099
2100 return 0;
2101 }
2102
check_pow_hid0_74xx(CPUPPCState * env)2103 static int check_pow_hid0_74xx(CPUPPCState *env)
2104 {
2105 if (env->spr[SPR_HID0] & 0x00600000) {
2106 return 1;
2107 }
2108
2109 return 0;
2110 }
2111
2112 #if defined(TARGET_PPC64)
check_attn_hid0(CPUPPCState * env)2113 static int check_attn_hid0(CPUPPCState *env)
2114 {
2115 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) {
2116 return 1;
2117 }
2118
2119 return 0;
2120 }
2121
check_attn_hid0_power9(CPUPPCState * env)2122 static int check_attn_hid0_power9(CPUPPCState *env)
2123 {
2124 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) {
2125 return 1;
2126 }
2127
2128 return 0;
2129 }
2130 #endif
2131
init_tlbs_emb(CPUPPCState * env)2132 static void init_tlbs_emb(CPUPPCState *env)
2133 {
2134 #ifndef CONFIG_USER_ONLY
2135 env->nb_tlb = 64;
2136 env->nb_ways = 1;
2137 env->tlb_type = TLB_EMB;
2138 #endif
2139 }
2140
init_proc_405(CPUPPCState * env)2141 static void init_proc_405(CPUPPCState *env)
2142 {
2143 register_40x_sprs(env);
2144 register_405_sprs(env);
2145 register_usprgh_sprs(env);
2146
2147 init_tlbs_emb(env);
2148 init_excp_4xx(env);
2149 env->dcache_line_size = 32;
2150 env->icache_line_size = 32;
2151 /* Allocate hardware IRQ controller */
2152 ppc40x_irq_init(env_archcpu(env));
2153
2154 SET_FIT_PERIOD(8, 12, 16, 20);
2155 SET_WDT_PERIOD(16, 20, 24, 28);
2156 }
2157
2158 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2159 {
2160 DeviceClass *dc = DEVICE_CLASS(oc);
2161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2162
2163 dc->desc = "PowerPC 405";
2164 pcc->init_proc = init_proc_405;
2165 pcc->check_pow = check_pow_nocheck;
2166 pcc->check_attn = check_attn_none;
2167 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2168 PPC_DCR | PPC_WRTEE |
2169 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2170 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2171 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2172 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2173 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2174 pcc->msr_mask = (1ull << MSR_WE) |
2175 (1ull << MSR_CE) |
2176 (1ull << MSR_EE) |
2177 (1ull << MSR_PR) |
2178 (1ull << MSR_FP) |
2179 (1ull << MSR_ME) |
2180 (1ull << MSR_DWE) |
2181 (1ull << MSR_DE) |
2182 (1ull << MSR_IR) |
2183 (1ull << MSR_DR);
2184 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2185 pcc->excp_model = POWERPC_EXCP_40x;
2186 pcc->bus_model = PPC_FLAGS_INPUT_405;
2187 pcc->bfd_mach = bfd_mach_ppc_403;
2188 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2189 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2190 }
2191
init_proc_440EP(CPUPPCState * env)2192 static void init_proc_440EP(CPUPPCState *env)
2193 {
2194 register_BookE_sprs(env, 0x000000000000FFFFULL);
2195 register_440_sprs(env);
2196 register_usprgh_sprs(env);
2197
2198 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210
2211 spr_register(env, SPR_440_CCR1, "CCR1",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215
2216 init_tlbs_emb(env);
2217 init_excp_BookE(env);
2218 env->dcache_line_size = 32;
2219 env->icache_line_size = 32;
2220 ppc40x_irq_init(env_archcpu(env));
2221
2222 SET_FIT_PERIOD(12, 16, 20, 24);
2223 SET_WDT_PERIOD(20, 24, 28, 32);
2224 }
2225
2226 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2227 {
2228 DeviceClass *dc = DEVICE_CLASS(oc);
2229 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2230
2231 dc->desc = "PowerPC 440 EP";
2232 pcc->init_proc = init_proc_440EP;
2233 pcc->check_pow = check_pow_nocheck;
2234 pcc->check_attn = check_attn_none;
2235 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2236 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2237 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2238 PPC_FLOAT_STFIWX |
2239 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2240 PPC_CACHE | PPC_CACHE_ICBI |
2241 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2242 PPC_MEM_TLBSYNC | PPC_MFTB |
2243 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2244 PPC_440_SPEC;
2245 pcc->msr_mask = (1ull << MSR_POW) |
2246 (1ull << MSR_CE) |
2247 (1ull << MSR_EE) |
2248 (1ull << MSR_PR) |
2249 (1ull << MSR_FP) |
2250 (1ull << MSR_ME) |
2251 (1ull << MSR_FE0) |
2252 (1ull << MSR_DWE) |
2253 (1ull << MSR_DE) |
2254 (1ull << MSR_FE1) |
2255 (1ull << MSR_IR) |
2256 (1ull << MSR_DR);
2257 pcc->mmu_model = POWERPC_MMU_BOOKE;
2258 pcc->excp_model = POWERPC_EXCP_BOOKE;
2259 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2260 pcc->bfd_mach = bfd_mach_ppc_403;
2261 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2262 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2263 }
2264
2265 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2266 {
2267 DeviceClass *dc = DEVICE_CLASS(oc);
2268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2269
2270 dc->desc = "PowerPC 460 EX";
2271 pcc->init_proc = init_proc_440EP;
2272 pcc->check_pow = check_pow_nocheck;
2273 pcc->check_attn = check_attn_none;
2274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2275 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2276 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2277 PPC_FLOAT_STFIWX |
2278 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2279 PPC_CACHE | PPC_CACHE_ICBI |
2280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2281 PPC_MEM_TLBSYNC | PPC_MFTB |
2282 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2283 PPC_440_SPEC;
2284 pcc->msr_mask = (1ull << MSR_POW) |
2285 (1ull << MSR_CE) |
2286 (1ull << MSR_EE) |
2287 (1ull << MSR_PR) |
2288 (1ull << MSR_FP) |
2289 (1ull << MSR_ME) |
2290 (1ull << MSR_FE0) |
2291 (1ull << MSR_DWE) |
2292 (1ull << MSR_DE) |
2293 (1ull << MSR_FE1) |
2294 (1ull << MSR_IR) |
2295 (1ull << MSR_DR);
2296 pcc->mmu_model = POWERPC_MMU_BOOKE;
2297 pcc->excp_model = POWERPC_EXCP_BOOKE;
2298 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2299 pcc->bfd_mach = bfd_mach_ppc_403;
2300 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2301 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2302 }
2303
init_proc_440GP(CPUPPCState * env)2304 static void init_proc_440GP(CPUPPCState *env)
2305 {
2306 register_BookE_sprs(env, 0x000000000000FFFFULL);
2307 register_440_sprs(env);
2308 register_usprgh_sprs(env);
2309
2310 init_tlbs_emb(env);
2311 init_excp_BookE(env);
2312 env->dcache_line_size = 32;
2313 env->icache_line_size = 32;
2314 /* XXX: TODO: allocate internal IRQ controller */
2315
2316 SET_FIT_PERIOD(12, 16, 20, 24);
2317 SET_WDT_PERIOD(20, 24, 28, 32);
2318 }
2319
2320 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2321 {
2322 DeviceClass *dc = DEVICE_CLASS(oc);
2323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2324
2325 dc->desc = "PowerPC 440 GP";
2326 pcc->init_proc = init_proc_440GP;
2327 pcc->check_pow = check_pow_nocheck;
2328 pcc->check_attn = check_attn_none;
2329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2330 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2331 PPC_CACHE | PPC_CACHE_ICBI |
2332 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2333 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2334 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2335 PPC_440_SPEC;
2336 pcc->msr_mask = (1ull << MSR_POW) |
2337 (1ull << MSR_CE) |
2338 (1ull << MSR_EE) |
2339 (1ull << MSR_PR) |
2340 (1ull << MSR_FP) |
2341 (1ull << MSR_ME) |
2342 (1ull << MSR_FE0) |
2343 (1ull << MSR_DWE) |
2344 (1ull << MSR_DE) |
2345 (1ull << MSR_FE1) |
2346 (1ull << MSR_IR) |
2347 (1ull << MSR_DR);
2348 pcc->mmu_model = POWERPC_MMU_BOOKE;
2349 pcc->excp_model = POWERPC_EXCP_BOOKE;
2350 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2351 pcc->bfd_mach = bfd_mach_ppc_403;
2352 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2353 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2354 }
2355
init_proc_440x5(CPUPPCState * env)2356 static void init_proc_440x5(CPUPPCState *env)
2357 {
2358 register_BookE_sprs(env, 0x000000000000FFFFULL);
2359 register_440_sprs(env);
2360 register_usprgh_sprs(env);
2361
2362 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374
2375 spr_register(env, SPR_440_CCR1, "CCR1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379
2380 init_tlbs_emb(env);
2381 init_excp_BookE(env);
2382 env->dcache_line_size = 32;
2383 env->icache_line_size = 32;
2384 ppc40x_irq_init(env_archcpu(env));
2385
2386 SET_FIT_PERIOD(12, 16, 20, 24);
2387 SET_WDT_PERIOD(20, 24, 28, 32);
2388 }
2389
2390 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2391 {
2392 DeviceClass *dc = DEVICE_CLASS(oc);
2393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2394
2395 dc->desc = "PowerPC 440x5";
2396 pcc->init_proc = init_proc_440x5;
2397 pcc->check_pow = check_pow_nocheck;
2398 pcc->check_attn = check_attn_none;
2399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2400 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2401 PPC_CACHE | PPC_CACHE_ICBI |
2402 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2403 PPC_MEM_TLBSYNC | PPC_MFTB |
2404 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2405 PPC_440_SPEC;
2406 pcc->msr_mask = (1ull << MSR_POW) |
2407 (1ull << MSR_CE) |
2408 (1ull << MSR_EE) |
2409 (1ull << MSR_PR) |
2410 (1ull << MSR_FP) |
2411 (1ull << MSR_ME) |
2412 (1ull << MSR_FE0) |
2413 (1ull << MSR_DWE) |
2414 (1ull << MSR_DE) |
2415 (1ull << MSR_FE1) |
2416 (1ull << MSR_IR) |
2417 (1ull << MSR_DR);
2418 pcc->mmu_model = POWERPC_MMU_BOOKE;
2419 pcc->excp_model = POWERPC_EXCP_BOOKE;
2420 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2421 pcc->bfd_mach = bfd_mach_ppc_403;
2422 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2423 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2424 }
2425
2426 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2427 {
2428 DeviceClass *dc = DEVICE_CLASS(oc);
2429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2430
2431 dc->desc = "PowerPC 440x5 with double precision FPU";
2432 pcc->init_proc = init_proc_440x5;
2433 pcc->check_pow = check_pow_nocheck;
2434 pcc->check_attn = check_attn_none;
2435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2436 PPC_FLOAT | PPC_FLOAT_FSQRT |
2437 PPC_FLOAT_STFIWX |
2438 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2439 PPC_CACHE | PPC_CACHE_ICBI |
2440 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2441 PPC_MEM_TLBSYNC | PPC_MFTB |
2442 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2443 PPC_440_SPEC;
2444 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2445 pcc->msr_mask = (1ull << MSR_POW) |
2446 (1ull << MSR_CE) |
2447 (1ull << MSR_EE) |
2448 (1ull << MSR_PR) |
2449 (1ull << MSR_FP) |
2450 (1ull << MSR_ME) |
2451 (1ull << MSR_FE0) |
2452 (1ull << MSR_DWE) |
2453 (1ull << MSR_DE) |
2454 (1ull << MSR_FE1) |
2455 (1ull << MSR_IR) |
2456 (1ull << MSR_DR);
2457 pcc->mmu_model = POWERPC_MMU_BOOKE;
2458 pcc->excp_model = POWERPC_EXCP_BOOKE;
2459 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2460 pcc->bfd_mach = bfd_mach_ppc_403;
2461 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2462 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2463 }
2464
init_proc_MPC5xx(CPUPPCState * env)2465 static void init_proc_MPC5xx(CPUPPCState *env)
2466 {
2467 register_5xx_8xx_sprs(env);
2468 register_5xx_sprs(env);
2469 init_excp_MPC5xx(env);
2470 env->dcache_line_size = 32;
2471 env->icache_line_size = 32;
2472 /* XXX: TODO: allocate internal IRQ controller */
2473 }
2474
POWERPC_FAMILY(MPC5xx)2475 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2476 {
2477 DeviceClass *dc = DEVICE_CLASS(oc);
2478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2479
2480 dc->desc = "Freescale 5xx cores (aka RCPU)";
2481 pcc->init_proc = init_proc_MPC5xx;
2482 pcc->check_pow = check_pow_none;
2483 pcc->check_attn = check_attn_none;
2484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2485 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2486 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2487 PPC_MFTB;
2488 pcc->msr_mask = (1ull << MSR_ILE) |
2489 (1ull << MSR_EE) |
2490 (1ull << MSR_PR) |
2491 (1ull << MSR_FP) |
2492 (1ull << MSR_ME) |
2493 (1ull << MSR_FE0) |
2494 (1ull << MSR_SE) |
2495 (1ull << MSR_DE) |
2496 (1ull << MSR_FE1) |
2497 (1ull << MSR_EP) |
2498 (1ull << MSR_RI) |
2499 (1ull << MSR_LE);
2500 pcc->mmu_model = POWERPC_MMU_REAL;
2501 pcc->excp_model = POWERPC_EXCP_6xx;
2502 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2503 pcc->bfd_mach = bfd_mach_ppc_505;
2504 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2505 POWERPC_FLAG_BUS_CLK;
2506 }
2507
init_proc_MPC8xx(CPUPPCState * env)2508 static void init_proc_MPC8xx(CPUPPCState *env)
2509 {
2510 register_5xx_8xx_sprs(env);
2511 register_8xx_sprs(env);
2512 init_excp_MPC8xx(env);
2513 env->dcache_line_size = 32;
2514 env->icache_line_size = 32;
2515 /* XXX: TODO: allocate internal IRQ controller */
2516 }
2517
POWERPC_FAMILY(MPC8xx)2518 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2519 {
2520 DeviceClass *dc = DEVICE_CLASS(oc);
2521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2522
2523 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2524 pcc->init_proc = init_proc_MPC8xx;
2525 pcc->check_pow = check_pow_none;
2526 pcc->check_attn = check_attn_none;
2527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2528 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2529 PPC_CACHE_ICBI | PPC_MFTB;
2530 pcc->msr_mask = (1ull << MSR_ILE) |
2531 (1ull << MSR_EE) |
2532 (1ull << MSR_PR) |
2533 (1ull << MSR_FP) |
2534 (1ull << MSR_ME) |
2535 (1ull << MSR_SE) |
2536 (1ull << MSR_DE) |
2537 (1ull << MSR_EP) |
2538 (1ull << MSR_IR) |
2539 (1ull << MSR_DR) |
2540 (1ull << MSR_RI) |
2541 (1ull << MSR_LE);
2542 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2543 pcc->excp_model = POWERPC_EXCP_6xx;
2544 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2545 pcc->bfd_mach = bfd_mach_ppc_860;
2546 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2547 POWERPC_FLAG_BUS_CLK;
2548 }
2549
2550 /* Freescale 82xx cores (aka PowerQUICC-II) */
2551
init_proc_G2(CPUPPCState * env)2552 static void init_proc_G2(CPUPPCState *env)
2553 {
2554 register_non_embedded_sprs(env);
2555 register_sdr1_sprs(env);
2556 register_G2_sprs(env);
2557
2558 /* Memory management */
2559 register_low_BATs(env);
2560 register_high_BATs(env);
2561 register_6xx_7xx_soft_tlb(env, 64, 2);
2562 init_excp_G2(env);
2563 env->dcache_line_size = 32;
2564 env->icache_line_size = 32;
2565 /* Allocate hardware IRQ controller */
2566 ppc6xx_irq_init(env_archcpu(env));
2567 }
2568
POWERPC_FAMILY(G2)2569 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2570 {
2571 DeviceClass *dc = DEVICE_CLASS(oc);
2572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2573
2574 dc->desc = "PowerPC G2";
2575 pcc->init_proc = init_proc_G2;
2576 pcc->check_pow = check_pow_hid0;
2577 pcc->check_attn = check_attn_none;
2578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2580 PPC_FLOAT_STFIWX |
2581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2582 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2584 PPC_SEGMENT | PPC_EXTERN;
2585 pcc->msr_mask = (1ull << MSR_POW) |
2586 (1ull << MSR_TGPR) |
2587 (1ull << MSR_EE) |
2588 (1ull << MSR_PR) |
2589 (1ull << MSR_FP) |
2590 (1ull << MSR_ME) |
2591 (1ull << MSR_FE0) |
2592 (1ull << MSR_SE) |
2593 (1ull << MSR_DE) |
2594 (1ull << MSR_FE1) |
2595 (1ull << MSR_AL) |
2596 (1ull << MSR_EP) |
2597 (1ull << MSR_IR) |
2598 (1ull << MSR_DR) |
2599 (1ull << MSR_RI);
2600 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2601 pcc->excp_model = POWERPC_EXCP_6xx;
2602 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2603 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2604 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2605 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2606 }
2607
POWERPC_FAMILY(G2LE)2608 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2609 {
2610 DeviceClass *dc = DEVICE_CLASS(oc);
2611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2612
2613 dc->desc = "PowerPC G2LE";
2614 pcc->init_proc = init_proc_G2;
2615 pcc->check_pow = check_pow_hid0;
2616 pcc->check_attn = check_attn_none;
2617 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2618 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2619 PPC_FLOAT_STFIWX |
2620 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2621 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2622 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2623 PPC_SEGMENT | PPC_EXTERN;
2624 pcc->msr_mask = (1ull << MSR_POW) |
2625 (1ull << MSR_TGPR) |
2626 (1ull << MSR_ILE) |
2627 (1ull << MSR_EE) |
2628 (1ull << MSR_PR) |
2629 (1ull << MSR_FP) |
2630 (1ull << MSR_ME) |
2631 (1ull << MSR_FE0) |
2632 (1ull << MSR_SE) |
2633 (1ull << MSR_DE) |
2634 (1ull << MSR_FE1) |
2635 (1ull << MSR_AL) |
2636 (1ull << MSR_EP) |
2637 (1ull << MSR_IR) |
2638 (1ull << MSR_DR) |
2639 (1ull << MSR_RI) |
2640 (1ull << MSR_LE);
2641 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2642 pcc->excp_model = POWERPC_EXCP_6xx;
2643 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2644 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2645 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2646 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2647 }
2648
init_proc_e200(CPUPPCState * env)2649 static void init_proc_e200(CPUPPCState *env)
2650 {
2651 register_BookE_sprs(env, 0x000000070000FFFFULL);
2652
2653 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2654 &spr_read_spefscr, &spr_write_spefscr,
2655 &spr_read_spefscr, &spr_write_spefscr,
2656 0x00000000);
2657 /* Memory management */
2658 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2659 register_usprgh_sprs(env);
2660
2661 spr_register(env, SPR_HID0, "HID0",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665
2666 spr_register(env, SPR_HID1, "HID1",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670
2671 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675
2676 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2677 SPR_NOACCESS, SPR_NOACCESS,
2678 &spr_read_generic, &spr_write_generic,
2679 0x00000000);
2680
2681 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
2685
2686 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
2690
2691 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
2695
2696 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2697 &spr_read_generic, SPR_NOACCESS,
2698 &spr_read_generic, SPR_NOACCESS,
2699 0x00000000);
2700
2701 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
2705
2706 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
2710
2711 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715
2716 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2717 SPR_NOACCESS, SPR_NOACCESS,
2718 &spr_read_generic, &spr_write_generic,
2719 0x00000000);
2720
2721 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2722 SPR_NOACCESS, SPR_NOACCESS,
2723 &spr_read_generic, &spr_write_generic,
2724 0x00000000);
2725
2726 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2727 SPR_NOACCESS, SPR_NOACCESS,
2728 &spr_read_generic, &spr_write_generic,
2729 0x00000000);
2730
2731 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2732 SPR_NOACCESS, SPR_NOACCESS,
2733 &spr_read_generic, &spr_write_generic,
2734 0x00000000); /* TOFIX */
2735 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2736 SPR_NOACCESS, SPR_NOACCESS,
2737 &spr_read_generic, &spr_write_generic,
2738 0x00000000);
2739 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2740 SPR_NOACCESS, SPR_NOACCESS,
2741 &spr_read_generic, &spr_write_generic,
2742 0x00000000);
2743
2744 init_tlbs_emb(env);
2745 init_excp_e200(env, 0xFFFF0000UL);
2746 env->dcache_line_size = 32;
2747 env->icache_line_size = 32;
2748 /* XXX: TODO: allocate internal IRQ controller */
2749 }
2750
POWERPC_FAMILY(e200)2751 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2752 {
2753 DeviceClass *dc = DEVICE_CLASS(oc);
2754 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2755
2756 dc->desc = "e200 core";
2757 pcc->init_proc = init_proc_e200;
2758 pcc->check_pow = check_pow_hid0;
2759 pcc->check_attn = check_attn_none;
2760 /*
2761 * XXX: unimplemented instructions:
2762 * dcblc
2763 * dcbtlst
2764 * dcbtstls
2765 * icblc
2766 * icbtls
2767 * tlbivax
2768 * all SPE multiply-accumulate instructions
2769 */
2770 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2771 PPC_SPE | PPC_SPE_SINGLE |
2772 PPC_WRTEE | PPC_RFDI |
2773 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2775 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2776 PPC_BOOKE;
2777 pcc->msr_mask = (1ull << MSR_UCLE) |
2778 (1ull << MSR_SPE) |
2779 (1ull << MSR_POW) |
2780 (1ull << MSR_CE) |
2781 (1ull << MSR_EE) |
2782 (1ull << MSR_PR) |
2783 (1ull << MSR_FP) |
2784 (1ull << MSR_ME) |
2785 (1ull << MSR_FE0) |
2786 (1ull << MSR_DWE) |
2787 (1ull << MSR_DE) |
2788 (1ull << MSR_FE1) |
2789 (1ull << MSR_IR) |
2790 (1ull << MSR_DR);
2791 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2792 pcc->excp_model = POWERPC_EXCP_BOOKE;
2793 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2794 pcc->bfd_mach = bfd_mach_ppc_860;
2795 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2796 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2797 POWERPC_FLAG_BUS_CLK;
2798 }
2799
2800 enum fsl_e500_version {
2801 fsl_e500v1,
2802 fsl_e500v2,
2803 fsl_e500mc,
2804 fsl_e5500,
2805 fsl_e6500,
2806 };
2807
init_proc_e500(CPUPPCState * env,int version)2808 static void init_proc_e500(CPUPPCState *env, int version)
2809 {
2810 uint32_t tlbncfg[2];
2811 uint64_t ivor_mask;
2812 uint64_t ivpr_mask = 0xFFFF0000ULL;
2813 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2814 | 0x0020; /* 32 kb */
2815 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2816 | 0x0020; /* 32 kb */
2817 uint32_t mmucfg = 0;
2818 #if !defined(CONFIG_USER_ONLY)
2819 int i;
2820 #endif
2821
2822 /*
2823 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2824 * complain when accessing them.
2825 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2826 */
2827 switch (version) {
2828 case fsl_e500v1:
2829 case fsl_e500v2:
2830 default:
2831 ivor_mask = 0x0000000F0000FFFFULL;
2832 break;
2833 case fsl_e500mc:
2834 case fsl_e5500:
2835 ivor_mask = 0x000003FE0000FFFFULL;
2836 break;
2837 case fsl_e6500:
2838 ivor_mask = 0x000003FF0000FFFFULL;
2839 break;
2840 }
2841 register_BookE_sprs(env, ivor_mask);
2842
2843 spr_register(env, SPR_USPRG3, "USPRG3",
2844 &spr_read_ureg, SPR_NOACCESS,
2845 &spr_read_ureg, SPR_NOACCESS,
2846 0x00000000);
2847
2848 /* Processor identification */
2849 spr_register(env, SPR_BOOKE_PIR, "PIR",
2850 SPR_NOACCESS, SPR_NOACCESS,
2851 &spr_read_generic, &spr_write_pir,
2852 0x00000000);
2853
2854 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2855 &spr_read_spefscr, &spr_write_spefscr,
2856 &spr_read_spefscr, &spr_write_spefscr,
2857 0x00000000);
2858 #if !defined(CONFIG_USER_ONLY)
2859 /* Memory management */
2860 env->nb_pids = 3;
2861 env->nb_ways = 2;
2862 switch (version) {
2863 case fsl_e500v1:
2864 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2865 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2866 break;
2867 case fsl_e500v2:
2868 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2869 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2870 break;
2871 case fsl_e500mc:
2872 case fsl_e5500:
2873 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2874 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2875 break;
2876 case fsl_e6500:
2877 mmucfg = 0x6510B45;
2878 env->nb_pids = 1;
2879 tlbncfg[0] = 0x08052400;
2880 tlbncfg[1] = 0x40028040;
2881 break;
2882 default:
2883 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2884 env->spr[SPR_PVR]);
2885 }
2886 #endif
2887 /* Cache sizes */
2888 switch (version) {
2889 case fsl_e500v1:
2890 case fsl_e500v2:
2891 env->dcache_line_size = 32;
2892 env->icache_line_size = 32;
2893 break;
2894 case fsl_e500mc:
2895 case fsl_e5500:
2896 env->dcache_line_size = 64;
2897 env->icache_line_size = 64;
2898 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2899 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2900 break;
2901 case fsl_e6500:
2902 env->dcache_line_size = 32;
2903 env->icache_line_size = 32;
2904 l1cfg0 |= 0x0F83820;
2905 l1cfg1 |= 0x0B83820;
2906 break;
2907 default:
2908 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2909 env->spr[SPR_PVR]);
2910 }
2911 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2912 register_usprgh_sprs(env);
2913
2914 spr_register(env, SPR_HID0, "HID0",
2915 SPR_NOACCESS, SPR_NOACCESS,
2916 &spr_read_generic, &spr_write_generic,
2917 0x00000000);
2918
2919 spr_register(env, SPR_HID1, "HID1",
2920 SPR_NOACCESS, SPR_NOACCESS,
2921 &spr_read_generic, &spr_write_generic,
2922 0x00000000);
2923
2924 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2925 SPR_NOACCESS, SPR_NOACCESS,
2926 &spr_read_generic, &spr_write_generic,
2927 0x00000000);
2928
2929 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2930 SPR_NOACCESS, SPR_NOACCESS,
2931 &spr_read_generic, &spr_write_generic,
2932 0x00000000);
2933
2934 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2935 SPR_NOACCESS, SPR_NOACCESS,
2936 &spr_read_generic, &spr_write_generic,
2937 0x00000000);
2938
2939 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2940 SPR_NOACCESS, SPR_NOACCESS,
2941 &spr_read_generic, &spr_write_generic,
2942 0x00000000);
2943
2944 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2945 SPR_NOACCESS, SPR_NOACCESS,
2946 &spr_read_generic, &spr_write_generic,
2947 0x00000000);
2948
2949 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2950 SPR_NOACCESS, SPR_NOACCESS,
2951 &spr_read_generic, &spr_write_generic,
2952 0x00000000);
2953
2954 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2955 &spr_read_generic, SPR_NOACCESS,
2956 &spr_read_generic, SPR_NOACCESS,
2957 l1cfg0);
2958 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2959 &spr_read_generic, SPR_NOACCESS,
2960 &spr_read_generic, SPR_NOACCESS,
2961 l1cfg1);
2962 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2963 SPR_NOACCESS, SPR_NOACCESS,
2964 &spr_read_generic, &spr_write_e500_l1csr0,
2965 0x00000000);
2966 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2967 SPR_NOACCESS, SPR_NOACCESS,
2968 &spr_read_generic, &spr_write_e500_l1csr1,
2969 0x00000000);
2970 if (version != fsl_e500v1 && version != fsl_e500v2) {
2971 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2972 SPR_NOACCESS, SPR_NOACCESS,
2973 &spr_read_generic, &spr_write_e500_l2csr0,
2974 0x00000000);
2975 }
2976 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2977 SPR_NOACCESS, SPR_NOACCESS,
2978 &spr_read_generic, &spr_write_generic,
2979 0x00000000);
2980 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2981 SPR_NOACCESS, SPR_NOACCESS,
2982 &spr_read_generic, &spr_write_generic,
2983 0x00000000);
2984 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2985 SPR_NOACCESS, SPR_NOACCESS,
2986 &spr_read_generic, &spr_write_booke206_mmucsr0,
2987 0x00000000);
2988 spr_register(env, SPR_BOOKE_EPR, "EPR",
2989 SPR_NOACCESS, SPR_NOACCESS,
2990 &spr_read_generic, SPR_NOACCESS,
2991 0x00000000);
2992 /* XXX better abstract into Emb.xxx features */
2993 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2994 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2995 SPR_NOACCESS, SPR_NOACCESS,
2996 &spr_read_generic, &spr_write_generic,
2997 0x00000000);
2998 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2999 SPR_NOACCESS, SPR_NOACCESS,
3000 &spr_read_mas73, &spr_write_mas73,
3001 0x00000000);
3002 ivpr_mask = (target_ulong)~0xFFFFULL;
3003 }
3004
3005 if (version == fsl_e6500) {
3006 /* Thread identification */
3007 spr_register(env, SPR_TIR, "TIR",
3008 SPR_NOACCESS, SPR_NOACCESS,
3009 &spr_read_generic, SPR_NOACCESS,
3010 0x00000000);
3011 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3012 SPR_NOACCESS, SPR_NOACCESS,
3013 &spr_read_generic, SPR_NOACCESS,
3014 0x00000004);
3015 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3016 SPR_NOACCESS, SPR_NOACCESS,
3017 &spr_read_generic, SPR_NOACCESS,
3018 0x7FFFFFFC);
3019 }
3020
3021 #if !defined(CONFIG_USER_ONLY)
3022 env->nb_tlb = 0;
3023 env->tlb_type = TLB_MAS;
3024 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3025 env->nb_tlb += booke206_tlb_size(env, i);
3026 }
3027 #endif
3028
3029 init_excp_e200(env, ivpr_mask);
3030 /* Allocate hardware IRQ controller */
3031 ppce500_irq_init(env_archcpu(env));
3032 }
3033
init_proc_e500v1(CPUPPCState * env)3034 static void init_proc_e500v1(CPUPPCState *env)
3035 {
3036 init_proc_e500(env, fsl_e500v1);
3037 }
3038
POWERPC_FAMILY(e500v1)3039 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3040 {
3041 DeviceClass *dc = DEVICE_CLASS(oc);
3042 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3043
3044 dc->desc = "e500v1 core";
3045 pcc->init_proc = init_proc_e500v1;
3046 pcc->check_pow = check_pow_hid0;
3047 pcc->check_attn = check_attn_none;
3048 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3049 PPC_SPE | PPC_SPE_SINGLE |
3050 PPC_WRTEE | PPC_RFDI |
3051 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3052 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3053 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3054 pcc->insns_flags2 = PPC2_BOOKE206;
3055 pcc->msr_mask = (1ull << MSR_UCLE) |
3056 (1ull << MSR_SPE) |
3057 (1ull << MSR_POW) |
3058 (1ull << MSR_CE) |
3059 (1ull << MSR_EE) |
3060 (1ull << MSR_PR) |
3061 (1ull << MSR_FP) |
3062 (1ull << MSR_ME) |
3063 (1ull << MSR_FE0) |
3064 (1ull << MSR_DWE) |
3065 (1ull << MSR_DE) |
3066 (1ull << MSR_FE1) |
3067 (1ull << MSR_IR) |
3068 (1ull << MSR_DR);
3069 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3070 pcc->excp_model = POWERPC_EXCP_BOOKE;
3071 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3072 pcc->bfd_mach = bfd_mach_ppc_860;
3073 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3074 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3075 POWERPC_FLAG_BUS_CLK;
3076 }
3077
init_proc_e500v2(CPUPPCState * env)3078 static void init_proc_e500v2(CPUPPCState *env)
3079 {
3080 init_proc_e500(env, fsl_e500v2);
3081 }
3082
POWERPC_FAMILY(e500v2)3083 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3084 {
3085 DeviceClass *dc = DEVICE_CLASS(oc);
3086 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3087
3088 dc->desc = "e500v2 core";
3089 pcc->init_proc = init_proc_e500v2;
3090 pcc->check_pow = check_pow_hid0;
3091 pcc->check_attn = check_attn_none;
3092 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3093 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3094 PPC_WRTEE | PPC_RFDI |
3095 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3096 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3097 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3098 pcc->insns_flags2 = PPC2_BOOKE206;
3099 pcc->msr_mask = (1ull << MSR_UCLE) |
3100 (1ull << MSR_SPE) |
3101 (1ull << MSR_POW) |
3102 (1ull << MSR_CE) |
3103 (1ull << MSR_EE) |
3104 (1ull << MSR_PR) |
3105 (1ull << MSR_FP) |
3106 (1ull << MSR_ME) |
3107 (1ull << MSR_FE0) |
3108 (1ull << MSR_DWE) |
3109 (1ull << MSR_DE) |
3110 (1ull << MSR_FE1) |
3111 (1ull << MSR_IR) |
3112 (1ull << MSR_DR);
3113 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3114 pcc->excp_model = POWERPC_EXCP_BOOKE;
3115 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3116 pcc->bfd_mach = bfd_mach_ppc_860;
3117 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3118 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3119 POWERPC_FLAG_BUS_CLK;
3120 }
3121
init_proc_e500mc(CPUPPCState * env)3122 static void init_proc_e500mc(CPUPPCState *env)
3123 {
3124 init_proc_e500(env, fsl_e500mc);
3125 }
3126
POWERPC_FAMILY(e500mc)3127 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3128 {
3129 DeviceClass *dc = DEVICE_CLASS(oc);
3130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3131
3132 dc->desc = "e500mc core";
3133 pcc->init_proc = init_proc_e500mc;
3134 pcc->check_pow = check_pow_none;
3135 pcc->check_attn = check_attn_none;
3136 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3137 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3138 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3139 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3140 PPC_FLOAT | PPC_FLOAT_FRES |
3141 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3142 PPC_FLOAT_STFIWX | PPC_WAIT |
3143 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3144 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3145 pcc->msr_mask = (1ull << MSR_GS) |
3146 (1ull << MSR_UCLE) |
3147 (1ull << MSR_CE) |
3148 (1ull << MSR_EE) |
3149 (1ull << MSR_PR) |
3150 (1ull << MSR_FP) |
3151 (1ull << MSR_ME) |
3152 (1ull << MSR_FE0) |
3153 (1ull << MSR_DE) |
3154 (1ull << MSR_FE1) |
3155 (1ull << MSR_IR) |
3156 (1ull << MSR_DR) |
3157 (1ull << MSR_PX) |
3158 (1ull << MSR_RI);
3159 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3160 pcc->excp_model = POWERPC_EXCP_BOOKE;
3161 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3162 /* FIXME: figure out the correct flag for e500mc */
3163 pcc->bfd_mach = bfd_mach_ppc_e500;
3164 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3165 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3166 }
3167
3168 #ifdef TARGET_PPC64
init_proc_e5500(CPUPPCState * env)3169 static void init_proc_e5500(CPUPPCState *env)
3170 {
3171 init_proc_e500(env, fsl_e5500);
3172 }
3173
POWERPC_FAMILY(e5500)3174 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3175 {
3176 DeviceClass *dc = DEVICE_CLASS(oc);
3177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3178
3179 dc->desc = "e5500 core";
3180 pcc->init_proc = init_proc_e5500;
3181 pcc->check_pow = check_pow_none;
3182 pcc->check_attn = check_attn_none;
3183 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3184 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3185 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3186 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3187 PPC_FLOAT | PPC_FLOAT_FRES |
3188 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3189 PPC_FLOAT_STFIWX | PPC_WAIT |
3190 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3191 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3192 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3193 PPC2_FP_CVT_S64;
3194 pcc->msr_mask = (1ull << MSR_CM) |
3195 (1ull << MSR_GS) |
3196 (1ull << MSR_UCLE) |
3197 (1ull << MSR_CE) |
3198 (1ull << MSR_EE) |
3199 (1ull << MSR_PR) |
3200 (1ull << MSR_FP) |
3201 (1ull << MSR_ME) |
3202 (1ull << MSR_FE0) |
3203 (1ull << MSR_DE) |
3204 (1ull << MSR_FE1) |
3205 (1ull << MSR_IR) |
3206 (1ull << MSR_DR) |
3207 (1ull << MSR_PX) |
3208 (1ull << MSR_RI);
3209 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3210 pcc->excp_model = POWERPC_EXCP_BOOKE;
3211 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3212 /* FIXME: figure out the correct flag for e5500 */
3213 pcc->bfd_mach = bfd_mach_ppc_e500;
3214 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3215 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3216 }
3217
init_proc_e6500(CPUPPCState * env)3218 static void init_proc_e6500(CPUPPCState *env)
3219 {
3220 init_proc_e500(env, fsl_e6500);
3221 }
3222
POWERPC_FAMILY(e6500)3223 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3224 {
3225 DeviceClass *dc = DEVICE_CLASS(oc);
3226 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3227
3228 dc->desc = "e6500 core";
3229 pcc->init_proc = init_proc_e6500;
3230 pcc->check_pow = check_pow_none;
3231 pcc->check_attn = check_attn_none;
3232 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3233 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3234 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3235 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3236 PPC_FLOAT | PPC_FLOAT_FRES |
3237 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3238 PPC_FLOAT_STFIWX | PPC_WAIT |
3239 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3240 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3241 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3242 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3243 pcc->msr_mask = (1ull << MSR_CM) |
3244 (1ull << MSR_GS) |
3245 (1ull << MSR_UCLE) |
3246 (1ull << MSR_CE) |
3247 (1ull << MSR_EE) |
3248 (1ull << MSR_PR) |
3249 (1ull << MSR_FP) |
3250 (1ull << MSR_ME) |
3251 (1ull << MSR_FE0) |
3252 (1ull << MSR_DE) |
3253 (1ull << MSR_FE1) |
3254 (1ull << MSR_IS) |
3255 (1ull << MSR_DS) |
3256 (1ull << MSR_PX) |
3257 (1ull << MSR_RI) |
3258 (1ull << MSR_VR);
3259 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3260 pcc->excp_model = POWERPC_EXCP_BOOKE;
3261 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3262 pcc->bfd_mach = bfd_mach_ppc_e500;
3263 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3264 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3265 }
3266
3267 #endif
3268
3269 /* Non-embedded PowerPC */
init_proc_603(CPUPPCState * env)3270 static void init_proc_603(CPUPPCState *env)
3271 {
3272 register_non_embedded_sprs(env);
3273 register_sdr1_sprs(env);
3274 register_603_sprs(env);
3275
3276 /* Memory management */
3277 register_low_BATs(env);
3278 register_6xx_7xx_soft_tlb(env, 64, 2);
3279 init_excp_603(env);
3280 env->dcache_line_size = 32;
3281 env->icache_line_size = 32;
3282 /* Allocate hardware IRQ controller */
3283 ppc6xx_irq_init(env_archcpu(env));
3284 }
3285
3286 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3287 {
3288 DeviceClass *dc = DEVICE_CLASS(oc);
3289 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3290
3291 dc->desc = "PowerPC 603";
3292 pcc->init_proc = init_proc_603;
3293 pcc->check_pow = check_pow_hid0;
3294 pcc->check_attn = check_attn_none;
3295 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3296 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3297 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3298 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3299 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3300 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3301 PPC_SEGMENT | PPC_EXTERN;
3302 pcc->msr_mask = (1ull << MSR_POW) |
3303 (1ull << MSR_TGPR) |
3304 (1ull << MSR_ILE) |
3305 (1ull << MSR_EE) |
3306 (1ull << MSR_PR) |
3307 (1ull << MSR_FP) |
3308 (1ull << MSR_ME) |
3309 (1ull << MSR_FE0) |
3310 (1ull << MSR_SE) |
3311 (1ull << MSR_DE) |
3312 (1ull << MSR_FE1) |
3313 (1ull << MSR_EP) |
3314 (1ull << MSR_IR) |
3315 (1ull << MSR_DR) |
3316 (1ull << MSR_RI) |
3317 (1ull << MSR_LE);
3318 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3319 pcc->excp_model = POWERPC_EXCP_6xx;
3320 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3321 pcc->bfd_mach = bfd_mach_ppc_603;
3322 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3323 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3324 }
3325
3326 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3327 {
3328 DeviceClass *dc = DEVICE_CLASS(oc);
3329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3330
3331 dc->desc = "PowerPC 603e";
3332 pcc->init_proc = init_proc_603;
3333 pcc->check_pow = check_pow_hid0;
3334 pcc->check_attn = check_attn_none;
3335 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3336 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3337 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3338 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3339 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3340 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3341 PPC_SEGMENT | PPC_EXTERN;
3342 pcc->msr_mask = (1ull << MSR_POW) |
3343 (1ull << MSR_TGPR) |
3344 (1ull << MSR_ILE) |
3345 (1ull << MSR_EE) |
3346 (1ull << MSR_PR) |
3347 (1ull << MSR_FP) |
3348 (1ull << MSR_ME) |
3349 (1ull << MSR_FE0) |
3350 (1ull << MSR_SE) |
3351 (1ull << MSR_DE) |
3352 (1ull << MSR_FE1) |
3353 (1ull << MSR_EP) |
3354 (1ull << MSR_IR) |
3355 (1ull << MSR_DR) |
3356 (1ull << MSR_RI) |
3357 (1ull << MSR_LE);
3358 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3359 pcc->excp_model = POWERPC_EXCP_6xx;
3360 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3361 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3362 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3363 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3364 }
3365
init_proc_e300(CPUPPCState * env)3366 static void init_proc_e300(CPUPPCState *env)
3367 {
3368 init_proc_603(env);
3369 register_e300_sprs(env);
3370 }
3371
POWERPC_FAMILY(e300)3372 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3373 {
3374 DeviceClass *dc = DEVICE_CLASS(oc);
3375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3376
3377 dc->desc = "e300 core";
3378 pcc->init_proc = init_proc_e300;
3379 pcc->check_pow = check_pow_hid0;
3380 pcc->check_attn = check_attn_none;
3381 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3382 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3383 PPC_FLOAT_STFIWX |
3384 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3385 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3386 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3387 PPC_SEGMENT | PPC_EXTERN;
3388 pcc->msr_mask = (1ull << MSR_POW) |
3389 (1ull << MSR_TGPR) |
3390 (1ull << MSR_ILE) |
3391 (1ull << MSR_EE) |
3392 (1ull << MSR_PR) |
3393 (1ull << MSR_FP) |
3394 (1ull << MSR_ME) |
3395 (1ull << MSR_FE0) |
3396 (1ull << MSR_SE) |
3397 (1ull << MSR_DE) |
3398 (1ull << MSR_FE1) |
3399 (1ull << MSR_AL) |
3400 (1ull << MSR_EP) |
3401 (1ull << MSR_IR) |
3402 (1ull << MSR_DR) |
3403 (1ull << MSR_RI) |
3404 (1ull << MSR_LE);
3405 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3406 pcc->excp_model = POWERPC_EXCP_6xx;
3407 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3408 pcc->bfd_mach = bfd_mach_ppc_603;
3409 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3410 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3411 }
3412
init_proc_604(CPUPPCState * env)3413 static void init_proc_604(CPUPPCState *env)
3414 {
3415 register_non_embedded_sprs(env);
3416 register_sdr1_sprs(env);
3417 register_604_sprs(env);
3418
3419 /* Memory management */
3420 register_low_BATs(env);
3421 init_excp_604(env);
3422 env->dcache_line_size = 32;
3423 env->icache_line_size = 32;
3424 /* Allocate hardware IRQ controller */
3425 ppc6xx_irq_init(env_archcpu(env));
3426 }
3427
3428 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3429 {
3430 DeviceClass *dc = DEVICE_CLASS(oc);
3431 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3432
3433 dc->desc = "PowerPC 604";
3434 pcc->init_proc = init_proc_604;
3435 pcc->check_pow = check_pow_nocheck;
3436 pcc->check_attn = check_attn_none;
3437 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3438 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3439 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3440 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3441 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3442 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3443 PPC_SEGMENT | PPC_EXTERN;
3444 pcc->msr_mask = (1ull << MSR_POW) |
3445 (1ull << MSR_ILE) |
3446 (1ull << MSR_EE) |
3447 (1ull << MSR_PR) |
3448 (1ull << MSR_FP) |
3449 (1ull << MSR_ME) |
3450 (1ull << MSR_FE0) |
3451 (1ull << MSR_SE) |
3452 (1ull << MSR_DE) |
3453 (1ull << MSR_FE1) |
3454 (1ull << MSR_EP) |
3455 (1ull << MSR_IR) |
3456 (1ull << MSR_DR) |
3457 (1ull << MSR_PMM) |
3458 (1ull << MSR_RI) |
3459 (1ull << MSR_LE);
3460 pcc->mmu_model = POWERPC_MMU_32B;
3461 pcc->excp_model = POWERPC_EXCP_6xx;
3462 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3463 pcc->bfd_mach = bfd_mach_ppc_604;
3464 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3465 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3466 }
3467
init_proc_604E(CPUPPCState * env)3468 static void init_proc_604E(CPUPPCState *env)
3469 {
3470 init_proc_604(env);
3471 register_604e_sprs(env);
3472 }
3473
3474 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3475 {
3476 DeviceClass *dc = DEVICE_CLASS(oc);
3477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3478
3479 dc->desc = "PowerPC 604E";
3480 pcc->init_proc = init_proc_604E;
3481 pcc->check_pow = check_pow_nocheck;
3482 pcc->check_attn = check_attn_none;
3483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3484 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3485 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3486 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3487 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3488 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3489 PPC_SEGMENT | PPC_EXTERN;
3490 pcc->msr_mask = (1ull << MSR_POW) |
3491 (1ull << MSR_ILE) |
3492 (1ull << MSR_EE) |
3493 (1ull << MSR_PR) |
3494 (1ull << MSR_FP) |
3495 (1ull << MSR_ME) |
3496 (1ull << MSR_FE0) |
3497 (1ull << MSR_SE) |
3498 (1ull << MSR_DE) |
3499 (1ull << MSR_FE1) |
3500 (1ull << MSR_EP) |
3501 (1ull << MSR_IR) |
3502 (1ull << MSR_DR) |
3503 (1ull << MSR_PMM) |
3504 (1ull << MSR_RI) |
3505 (1ull << MSR_LE);
3506 pcc->mmu_model = POWERPC_MMU_32B;
3507 pcc->excp_model = POWERPC_EXCP_6xx;
3508 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3509 pcc->bfd_mach = bfd_mach_ppc_604;
3510 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3511 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3512 }
3513
init_proc_740(CPUPPCState * env)3514 static void init_proc_740(CPUPPCState *env)
3515 {
3516 register_non_embedded_sprs(env);
3517 register_sdr1_sprs(env);
3518 register_7xx_sprs(env);
3519 /* Thermal management */
3520 register_thrm_sprs(env);
3521
3522 /* Memory management */
3523 register_low_BATs(env);
3524 init_excp_7x0(env);
3525 env->dcache_line_size = 32;
3526 env->icache_line_size = 32;
3527 /* Allocate hardware IRQ controller */
3528 ppc6xx_irq_init(env_archcpu(env));
3529 }
3530
3531 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3532 {
3533 DeviceClass *dc = DEVICE_CLASS(oc);
3534 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3535
3536 dc->desc = "PowerPC 740";
3537 pcc->init_proc = init_proc_740;
3538 pcc->check_pow = check_pow_hid0;
3539 pcc->check_attn = check_attn_none;
3540 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3541 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3542 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3543 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3544 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3545 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3546 PPC_SEGMENT | PPC_EXTERN;
3547 pcc->msr_mask = (1ull << MSR_POW) |
3548 (1ull << MSR_ILE) |
3549 (1ull << MSR_EE) |
3550 (1ull << MSR_PR) |
3551 (1ull << MSR_FP) |
3552 (1ull << MSR_ME) |
3553 (1ull << MSR_FE0) |
3554 (1ull << MSR_SE) |
3555 (1ull << MSR_DE) |
3556 (1ull << MSR_FE1) |
3557 (1ull << MSR_EP) |
3558 (1ull << MSR_IR) |
3559 (1ull << MSR_DR) |
3560 (1ull << MSR_PMM) |
3561 (1ull << MSR_RI) |
3562 (1ull << MSR_LE);
3563 pcc->mmu_model = POWERPC_MMU_32B;
3564 pcc->excp_model = POWERPC_EXCP_7xx;
3565 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3566 pcc->bfd_mach = bfd_mach_ppc_750;
3567 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3568 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3569 }
3570
init_proc_750(CPUPPCState * env)3571 static void init_proc_750(CPUPPCState *env)
3572 {
3573 register_non_embedded_sprs(env);
3574 register_sdr1_sprs(env);
3575 register_7xx_sprs(env);
3576
3577 spr_register(env, SPR_L2CR, "L2CR",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, spr_access_nop,
3580 0x00000000);
3581 /* Thermal management */
3582 register_thrm_sprs(env);
3583
3584 /* Memory management */
3585 register_low_BATs(env);
3586 /*
3587 * XXX: high BATs are also present but are known to be bugged on
3588 * die version 1.x
3589 */
3590 init_excp_7x0(env);
3591 env->dcache_line_size = 32;
3592 env->icache_line_size = 32;
3593 /* Allocate hardware IRQ controller */
3594 ppc6xx_irq_init(env_archcpu(env));
3595 }
3596
3597 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3598 {
3599 DeviceClass *dc = DEVICE_CLASS(oc);
3600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3601
3602 dc->desc = "PowerPC 750";
3603 pcc->init_proc = init_proc_750;
3604 pcc->check_pow = check_pow_hid0;
3605 pcc->check_attn = check_attn_none;
3606 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3608 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3609 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3610 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3611 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3612 PPC_SEGMENT | PPC_EXTERN;
3613 pcc->msr_mask = (1ull << MSR_POW) |
3614 (1ull << MSR_ILE) |
3615 (1ull << MSR_EE) |
3616 (1ull << MSR_PR) |
3617 (1ull << MSR_FP) |
3618 (1ull << MSR_ME) |
3619 (1ull << MSR_FE0) |
3620 (1ull << MSR_SE) |
3621 (1ull << MSR_DE) |
3622 (1ull << MSR_FE1) |
3623 (1ull << MSR_EP) |
3624 (1ull << MSR_IR) |
3625 (1ull << MSR_DR) |
3626 (1ull << MSR_PMM) |
3627 (1ull << MSR_RI) |
3628 (1ull << MSR_LE);
3629 pcc->mmu_model = POWERPC_MMU_32B;
3630 pcc->excp_model = POWERPC_EXCP_7xx;
3631 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3632 pcc->bfd_mach = bfd_mach_ppc_750;
3633 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3634 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3635 }
3636
init_proc_750cl(CPUPPCState * env)3637 static void init_proc_750cl(CPUPPCState *env)
3638 {
3639 register_non_embedded_sprs(env);
3640 register_sdr1_sprs(env);
3641 register_7xx_sprs(env);
3642
3643 spr_register(env, SPR_L2CR, "L2CR",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, spr_access_nop,
3646 0x00000000);
3647 /* Thermal management */
3648 /* Those registers are fake on 750CL */
3649 spr_register(env, SPR_THRM1, "THRM1",
3650 SPR_NOACCESS, SPR_NOACCESS,
3651 &spr_read_generic, &spr_write_generic,
3652 0x00000000);
3653 spr_register(env, SPR_THRM2, "THRM2",
3654 SPR_NOACCESS, SPR_NOACCESS,
3655 &spr_read_generic, &spr_write_generic,
3656 0x00000000);
3657 spr_register(env, SPR_THRM3, "THRM3",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661
3662 spr_register(env, SPR_750_TDCL, "TDCL",
3663 SPR_NOACCESS, SPR_NOACCESS,
3664 &spr_read_generic, &spr_write_generic,
3665 0x00000000);
3666 spr_register(env, SPR_750_TDCH, "TDCH",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* DMA */
3671 spr_register(env, SPR_750_WPAR, "WPAR",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 spr_register(env, SPR_750_DMAL, "DMAL",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 spr_register(env, SPR_750_DMAU, "DMAU",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 /* Hardware implementation registers */
3684 spr_register(env, SPR_750CL_HID2, "HID2",
3685 SPR_NOACCESS, SPR_NOACCESS,
3686 &spr_read_generic, &spr_write_generic,
3687 0x00000000);
3688
3689 spr_register(env, SPR_750CL_HID4, "HID4",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693 /* Quantization registers */
3694 spr_register(env, SPR_750_GQR0, "GQR0",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3697 0x00000000);
3698
3699 spr_register(env, SPR_750_GQR1, "GQR1",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_generic,
3702 0x00000000);
3703
3704 spr_register(env, SPR_750_GQR2, "GQR2",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_generic,
3707 0x00000000);
3708
3709 spr_register(env, SPR_750_GQR3, "GQR3",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713
3714 spr_register(env, SPR_750_GQR4, "GQR4",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718
3719 spr_register(env, SPR_750_GQR5, "GQR5",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723
3724 spr_register(env, SPR_750_GQR6, "GQR6",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728
3729 spr_register(env, SPR_750_GQR7, "GQR7",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* Memory management */
3734 register_low_BATs(env);
3735 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3736 register_high_BATs(env);
3737 init_excp_750cl(env);
3738 env->dcache_line_size = 32;
3739 env->icache_line_size = 32;
3740 /* Allocate hardware IRQ controller */
3741 ppc6xx_irq_init(env_archcpu(env));
3742 }
3743
3744 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3745 {
3746 DeviceClass *dc = DEVICE_CLASS(oc);
3747 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3748
3749 dc->desc = "PowerPC 750 CL";
3750 pcc->init_proc = init_proc_750cl;
3751 pcc->check_pow = check_pow_hid0;
3752 pcc->check_attn = check_attn_none;
3753 /*
3754 * XXX: not implemented:
3755 * cache lock instructions:
3756 * dcbz_l
3757 * floating point paired instructions
3758 * psq_lux
3759 * psq_lx
3760 * psq_stux
3761 * psq_stx
3762 * ps_abs
3763 * ps_add
3764 * ps_cmpo0
3765 * ps_cmpo1
3766 * ps_cmpu0
3767 * ps_cmpu1
3768 * ps_div
3769 * ps_madd
3770 * ps_madds0
3771 * ps_madds1
3772 * ps_merge00
3773 * ps_merge01
3774 * ps_merge10
3775 * ps_merge11
3776 * ps_mr
3777 * ps_msub
3778 * ps_mul
3779 * ps_muls0
3780 * ps_muls1
3781 * ps_nabs
3782 * ps_neg
3783 * ps_nmadd
3784 * ps_nmsub
3785 * ps_res
3786 * ps_rsqrte
3787 * ps_sel
3788 * ps_sub
3789 * ps_sum0
3790 * ps_sum1
3791 */
3792 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3794 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3795 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3796 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3797 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3798 PPC_SEGMENT | PPC_EXTERN;
3799 pcc->msr_mask = (1ull << MSR_POW) |
3800 (1ull << MSR_ILE) |
3801 (1ull << MSR_EE) |
3802 (1ull << MSR_PR) |
3803 (1ull << MSR_FP) |
3804 (1ull << MSR_ME) |
3805 (1ull << MSR_FE0) |
3806 (1ull << MSR_SE) |
3807 (1ull << MSR_DE) |
3808 (1ull << MSR_FE1) |
3809 (1ull << MSR_EP) |
3810 (1ull << MSR_IR) |
3811 (1ull << MSR_DR) |
3812 (1ull << MSR_PMM) |
3813 (1ull << MSR_RI) |
3814 (1ull << MSR_LE);
3815 pcc->mmu_model = POWERPC_MMU_32B;
3816 pcc->excp_model = POWERPC_EXCP_7xx;
3817 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3818 pcc->bfd_mach = bfd_mach_ppc_750;
3819 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3820 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3821 }
3822
init_proc_750cx(CPUPPCState * env)3823 static void init_proc_750cx(CPUPPCState *env)
3824 {
3825 register_non_embedded_sprs(env);
3826 register_sdr1_sprs(env);
3827 register_7xx_sprs(env);
3828
3829 spr_register(env, SPR_L2CR, "L2CR",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, spr_access_nop,
3832 0x00000000);
3833 /* Thermal management */
3834 register_thrm_sprs(env);
3835
3836 spr_register(env, SPR_SDA, "SDA",
3837 SPR_NOACCESS, SPR_NOACCESS,
3838 &spr_read_generic, &spr_write_generic,
3839 0x00000000);
3840
3841 /* Memory management */
3842 register_low_BATs(env);
3843 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3844 register_high_BATs(env);
3845 init_excp_750cx(env);
3846 env->dcache_line_size = 32;
3847 env->icache_line_size = 32;
3848 /* Allocate hardware IRQ controller */
3849 ppc6xx_irq_init(env_archcpu(env));
3850 }
3851
3852 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3853 {
3854 DeviceClass *dc = DEVICE_CLASS(oc);
3855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3856
3857 dc->desc = "PowerPC 750CX";
3858 pcc->init_proc = init_proc_750cx;
3859 pcc->check_pow = check_pow_hid0;
3860 pcc->check_attn = check_attn_none;
3861 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3862 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3863 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3865 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3867 PPC_SEGMENT | PPC_EXTERN;
3868 pcc->msr_mask = (1ull << MSR_POW) |
3869 (1ull << MSR_ILE) |
3870 (1ull << MSR_EE) |
3871 (1ull << MSR_PR) |
3872 (1ull << MSR_FP) |
3873 (1ull << MSR_ME) |
3874 (1ull << MSR_FE0) |
3875 (1ull << MSR_SE) |
3876 (1ull << MSR_DE) |
3877 (1ull << MSR_FE1) |
3878 (1ull << MSR_EP) |
3879 (1ull << MSR_IR) |
3880 (1ull << MSR_DR) |
3881 (1ull << MSR_PMM) |
3882 (1ull << MSR_RI) |
3883 (1ull << MSR_LE);
3884 pcc->mmu_model = POWERPC_MMU_32B;
3885 pcc->excp_model = POWERPC_EXCP_7xx;
3886 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3887 pcc->bfd_mach = bfd_mach_ppc_750;
3888 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3889 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3890 }
3891
init_proc_750fx(CPUPPCState * env)3892 static void init_proc_750fx(CPUPPCState *env)
3893 {
3894 register_non_embedded_sprs(env);
3895 register_sdr1_sprs(env);
3896 register_7xx_sprs(env);
3897
3898 spr_register(env, SPR_L2CR, "L2CR",
3899 SPR_NOACCESS, SPR_NOACCESS,
3900 &spr_read_generic, spr_access_nop,
3901 0x00000000);
3902 /* Thermal management */
3903 register_thrm_sprs(env);
3904
3905 spr_register(env, SPR_750_THRM4, "THRM4",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* Hardware implementation registers */
3910 spr_register(env, SPR_750FX_HID2, "HID2",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* Memory management */
3915 register_low_BATs(env);
3916 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3917 register_high_BATs(env);
3918 init_excp_7x0(env);
3919 env->dcache_line_size = 32;
3920 env->icache_line_size = 32;
3921 /* Allocate hardware IRQ controller */
3922 ppc6xx_irq_init(env_archcpu(env));
3923 }
3924
3925 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3926 {
3927 DeviceClass *dc = DEVICE_CLASS(oc);
3928 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3929
3930 dc->desc = "PowerPC 750FX";
3931 pcc->init_proc = init_proc_750fx;
3932 pcc->check_pow = check_pow_hid0;
3933 pcc->check_attn = check_attn_none;
3934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3938 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3940 PPC_SEGMENT | PPC_EXTERN;
3941 pcc->msr_mask = (1ull << MSR_POW) |
3942 (1ull << MSR_ILE) |
3943 (1ull << MSR_EE) |
3944 (1ull << MSR_PR) |
3945 (1ull << MSR_FP) |
3946 (1ull << MSR_ME) |
3947 (1ull << MSR_FE0) |
3948 (1ull << MSR_SE) |
3949 (1ull << MSR_DE) |
3950 (1ull << MSR_FE1) |
3951 (1ull << MSR_EP) |
3952 (1ull << MSR_IR) |
3953 (1ull << MSR_DR) |
3954 (1ull << MSR_PMM) |
3955 (1ull << MSR_RI) |
3956 (1ull << MSR_LE);
3957 pcc->mmu_model = POWERPC_MMU_32B;
3958 pcc->excp_model = POWERPC_EXCP_7xx;
3959 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3960 pcc->bfd_mach = bfd_mach_ppc_750;
3961 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3962 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3963 }
3964
init_proc_750gx(CPUPPCState * env)3965 static void init_proc_750gx(CPUPPCState *env)
3966 {
3967 register_non_embedded_sprs(env);
3968 register_sdr1_sprs(env);
3969 register_7xx_sprs(env);
3970
3971 spr_register(env, SPR_L2CR, "L2CR",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, spr_access_nop,
3974 0x00000000);
3975 /* Thermal management */
3976 register_thrm_sprs(env);
3977
3978 spr_register(env, SPR_750_THRM4, "THRM4",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* Hardware implementation registers */
3983 spr_register(env, SPR_750FX_HID2, "HID2",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* Memory management */
3988 register_low_BATs(env);
3989 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3990 register_high_BATs(env);
3991 init_excp_7x0(env);
3992 env->dcache_line_size = 32;
3993 env->icache_line_size = 32;
3994 /* Allocate hardware IRQ controller */
3995 ppc6xx_irq_init(env_archcpu(env));
3996 }
3997
3998 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3999 {
4000 DeviceClass *dc = DEVICE_CLASS(oc);
4001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4002
4003 dc->desc = "PowerPC 750GX";
4004 pcc->init_proc = init_proc_750gx;
4005 pcc->check_pow = check_pow_hid0;
4006 pcc->check_attn = check_attn_none;
4007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4009 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4011 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4013 PPC_SEGMENT | PPC_EXTERN;
4014 pcc->msr_mask = (1ull << MSR_POW) |
4015 (1ull << MSR_ILE) |
4016 (1ull << MSR_EE) |
4017 (1ull << MSR_PR) |
4018 (1ull << MSR_FP) |
4019 (1ull << MSR_ME) |
4020 (1ull << MSR_FE0) |
4021 (1ull << MSR_SE) |
4022 (1ull << MSR_DE) |
4023 (1ull << MSR_FE1) |
4024 (1ull << MSR_EP) |
4025 (1ull << MSR_IR) |
4026 (1ull << MSR_DR) |
4027 (1ull << MSR_PMM) |
4028 (1ull << MSR_RI) |
4029 (1ull << MSR_LE);
4030 pcc->mmu_model = POWERPC_MMU_32B;
4031 pcc->excp_model = POWERPC_EXCP_7xx;
4032 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4033 pcc->bfd_mach = bfd_mach_ppc_750;
4034 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4035 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4036 }
4037
init_proc_745(CPUPPCState * env)4038 static void init_proc_745(CPUPPCState *env)
4039 {
4040 register_non_embedded_sprs(env);
4041 register_sdr1_sprs(env);
4042 register_7xx_sprs(env);
4043 register_745_sprs(env);
4044 /* Thermal management */
4045 register_thrm_sprs(env);
4046
4047 /* Memory management */
4048 register_low_BATs(env);
4049 register_high_BATs(env);
4050 register_6xx_7xx_soft_tlb(env, 64, 2);
4051 init_excp_7x5(env);
4052 env->dcache_line_size = 32;
4053 env->icache_line_size = 32;
4054 /* Allocate hardware IRQ controller */
4055 ppc6xx_irq_init(env_archcpu(env));
4056 }
4057
4058 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4059 {
4060 DeviceClass *dc = DEVICE_CLASS(oc);
4061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4062
4063 dc->desc = "PowerPC 745";
4064 pcc->init_proc = init_proc_745;
4065 pcc->check_pow = check_pow_hid0;
4066 pcc->check_attn = check_attn_none;
4067 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4068 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4069 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4070 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4071 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4072 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4073 PPC_SEGMENT | PPC_EXTERN;
4074 pcc->msr_mask = (1ull << MSR_POW) |
4075 (1ull << MSR_ILE) |
4076 (1ull << MSR_EE) |
4077 (1ull << MSR_PR) |
4078 (1ull << MSR_FP) |
4079 (1ull << MSR_ME) |
4080 (1ull << MSR_FE0) |
4081 (1ull << MSR_SE) |
4082 (1ull << MSR_DE) |
4083 (1ull << MSR_FE1) |
4084 (1ull << MSR_EP) |
4085 (1ull << MSR_IR) |
4086 (1ull << MSR_DR) |
4087 (1ull << MSR_PMM) |
4088 (1ull << MSR_RI) |
4089 (1ull << MSR_LE);
4090 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4091 pcc->excp_model = POWERPC_EXCP_7xx;
4092 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4093 pcc->bfd_mach = bfd_mach_ppc_750;
4094 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4095 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4096 }
4097
init_proc_755(CPUPPCState * env)4098 static void init_proc_755(CPUPPCState *env)
4099 {
4100 init_proc_745(env);
4101 register_755_sprs(env);
4102 }
4103
4104 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4105 {
4106 DeviceClass *dc = DEVICE_CLASS(oc);
4107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4108
4109 dc->desc = "PowerPC 755";
4110 pcc->init_proc = init_proc_755;
4111 pcc->check_pow = check_pow_hid0;
4112 pcc->check_attn = check_attn_none;
4113 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4114 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4115 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4116 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4117 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4118 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4119 PPC_SEGMENT | PPC_EXTERN;
4120 pcc->msr_mask = (1ull << MSR_POW) |
4121 (1ull << MSR_ILE) |
4122 (1ull << MSR_EE) |
4123 (1ull << MSR_PR) |
4124 (1ull << MSR_FP) |
4125 (1ull << MSR_ME) |
4126 (1ull << MSR_FE0) |
4127 (1ull << MSR_SE) |
4128 (1ull << MSR_DE) |
4129 (1ull << MSR_FE1) |
4130 (1ull << MSR_EP) |
4131 (1ull << MSR_IR) |
4132 (1ull << MSR_DR) |
4133 (1ull << MSR_PMM) |
4134 (1ull << MSR_RI) |
4135 (1ull << MSR_LE);
4136 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4137 pcc->excp_model = POWERPC_EXCP_7xx;
4138 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4139 pcc->bfd_mach = bfd_mach_ppc_750;
4140 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4141 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4142 }
4143
init_proc_7400(CPUPPCState * env)4144 static void init_proc_7400(CPUPPCState *env)
4145 {
4146 register_non_embedded_sprs(env);
4147 register_sdr1_sprs(env);
4148 register_74xx_sprs(env);
4149 vscr_init(env, 0x00010000);
4150
4151 spr_register(env, SPR_UBAMR, "UBAMR",
4152 &spr_read_ureg, SPR_NOACCESS,
4153 &spr_read_ureg, SPR_NOACCESS,
4154 0x00000000);
4155
4156 spr_register(env, SPR_MSSCR1, "MSSCR1",
4157 SPR_NOACCESS, SPR_NOACCESS,
4158 &spr_read_generic, &spr_write_generic,
4159 0x00000000);
4160 /* Thermal management */
4161 register_thrm_sprs(env);
4162 /* Memory management */
4163 register_low_BATs(env);
4164 init_excp_7400(env);
4165 env->dcache_line_size = 32;
4166 env->icache_line_size = 32;
4167 /* Allocate hardware IRQ controller */
4168 ppc6xx_irq_init(env_archcpu(env));
4169 }
4170
4171 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4172 {
4173 DeviceClass *dc = DEVICE_CLASS(oc);
4174 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4175
4176 dc->desc = "PowerPC 7400 (aka G4)";
4177 pcc->init_proc = init_proc_7400;
4178 pcc->check_pow = check_pow_hid0;
4179 pcc->check_attn = check_attn_none;
4180 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4181 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4182 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4183 PPC_FLOAT_STFIWX |
4184 PPC_CACHE | PPC_CACHE_ICBI |
4185 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4186 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4187 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4188 PPC_MEM_TLBIA |
4189 PPC_SEGMENT | PPC_EXTERN |
4190 PPC_ALTIVEC;
4191 pcc->msr_mask = (1ull << MSR_VR) |
4192 (1ull << MSR_POW) |
4193 (1ull << MSR_ILE) |
4194 (1ull << MSR_EE) |
4195 (1ull << MSR_PR) |
4196 (1ull << MSR_FP) |
4197 (1ull << MSR_ME) |
4198 (1ull << MSR_FE0) |
4199 (1ull << MSR_SE) |
4200 (1ull << MSR_DE) |
4201 (1ull << MSR_FE1) |
4202 (1ull << MSR_EP) |
4203 (1ull << MSR_IR) |
4204 (1ull << MSR_DR) |
4205 (1ull << MSR_PMM) |
4206 (1ull << MSR_RI) |
4207 (1ull << MSR_LE);
4208 pcc->mmu_model = POWERPC_MMU_32B;
4209 pcc->excp_model = POWERPC_EXCP_74xx;
4210 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4211 pcc->bfd_mach = bfd_mach_ppc_7400;
4212 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4213 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4214 POWERPC_FLAG_BUS_CLK;
4215 }
4216
init_proc_7410(CPUPPCState * env)4217 static void init_proc_7410(CPUPPCState *env)
4218 {
4219 register_non_embedded_sprs(env);
4220 register_sdr1_sprs(env);
4221 register_74xx_sprs(env);
4222 vscr_init(env, 0x00010000);
4223
4224 spr_register(env, SPR_UBAMR, "UBAMR",
4225 &spr_read_ureg, SPR_NOACCESS,
4226 &spr_read_ureg, SPR_NOACCESS,
4227 0x00000000);
4228 /* Thermal management */
4229 register_thrm_sprs(env);
4230 /* L2PMCR */
4231
4232 spr_register(env, SPR_L2PMCR, "L2PMCR",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* LDSTDB */
4237
4238 spr_register(env, SPR_LDSTDB, "LDSTDB",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* Memory management */
4243 register_low_BATs(env);
4244 init_excp_7400(env);
4245 env->dcache_line_size = 32;
4246 env->icache_line_size = 32;
4247 /* Allocate hardware IRQ controller */
4248 ppc6xx_irq_init(env_archcpu(env));
4249 }
4250
4251 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4252 {
4253 DeviceClass *dc = DEVICE_CLASS(oc);
4254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4255
4256 dc->desc = "PowerPC 7410 (aka G4)";
4257 pcc->init_proc = init_proc_7410;
4258 pcc->check_pow = check_pow_hid0;
4259 pcc->check_attn = check_attn_none;
4260 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4261 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4262 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4263 PPC_FLOAT_STFIWX |
4264 PPC_CACHE | PPC_CACHE_ICBI |
4265 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4266 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4268 PPC_MEM_TLBIA |
4269 PPC_SEGMENT | PPC_EXTERN |
4270 PPC_ALTIVEC;
4271 pcc->msr_mask = (1ull << MSR_VR) |
4272 (1ull << MSR_POW) |
4273 (1ull << MSR_ILE) |
4274 (1ull << MSR_EE) |
4275 (1ull << MSR_PR) |
4276 (1ull << MSR_FP) |
4277 (1ull << MSR_ME) |
4278 (1ull << MSR_FE0) |
4279 (1ull << MSR_SE) |
4280 (1ull << MSR_DE) |
4281 (1ull << MSR_FE1) |
4282 (1ull << MSR_EP) |
4283 (1ull << MSR_IR) |
4284 (1ull << MSR_DR) |
4285 (1ull << MSR_PMM) |
4286 (1ull << MSR_RI) |
4287 (1ull << MSR_LE);
4288 pcc->mmu_model = POWERPC_MMU_32B;
4289 pcc->excp_model = POWERPC_EXCP_74xx;
4290 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4291 pcc->bfd_mach = bfd_mach_ppc_7400;
4292 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4293 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4294 POWERPC_FLAG_BUS_CLK;
4295 }
4296
init_proc_7440(CPUPPCState * env)4297 static void init_proc_7440(CPUPPCState *env)
4298 {
4299 register_non_embedded_sprs(env);
4300 register_sdr1_sprs(env);
4301 register_74xx_sprs(env);
4302 vscr_init(env, 0x00010000);
4303
4304 spr_register(env, SPR_UBAMR, "UBAMR",
4305 &spr_read_ureg, SPR_NOACCESS,
4306 &spr_read_ureg, SPR_NOACCESS,
4307 0x00000000);
4308 /* LDSTCR */
4309 spr_register(env, SPR_LDSTCR, "LDSTCR",
4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* ICTRL */
4314 spr_register(env, SPR_ICTRL, "ICTRL",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, &spr_write_generic,
4317 0x00000000);
4318 /* MSSSR0 */
4319 spr_register(env, SPR_MSSSR0, "MSSSR0",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_generic,
4322 0x00000000);
4323 /* PMC */
4324 spr_register(env, SPR_7XX_PMC5, "PMC5",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328
4329 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4330 &spr_read_ureg, SPR_NOACCESS,
4331 &spr_read_ureg, SPR_NOACCESS,
4332 0x00000000);
4333
4334 spr_register(env, SPR_7XX_PMC6, "PMC6",
4335 SPR_NOACCESS, SPR_NOACCESS,
4336 &spr_read_generic, &spr_write_generic,
4337 0x00000000);
4338
4339 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4340 &spr_read_ureg, SPR_NOACCESS,
4341 &spr_read_ureg, SPR_NOACCESS,
4342 0x00000000);
4343 /* Memory management */
4344 register_low_BATs(env);
4345 init_excp_7450(env);
4346 env->dcache_line_size = 32;
4347 env->icache_line_size = 32;
4348 /* Allocate hardware IRQ controller */
4349 ppc6xx_irq_init(env_archcpu(env));
4350 }
4351
4352 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4353 {
4354 DeviceClass *dc = DEVICE_CLASS(oc);
4355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4356
4357 dc->desc = "PowerPC 7440 (aka G4)";
4358 pcc->init_proc = init_proc_7440;
4359 pcc->check_pow = check_pow_hid0_74xx;
4360 pcc->check_attn = check_attn_none;
4361 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4362 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4363 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4364 PPC_FLOAT_STFIWX |
4365 PPC_CACHE | PPC_CACHE_ICBI |
4366 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4367 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4368 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4369 PPC_MEM_TLBIA |
4370 PPC_SEGMENT | PPC_EXTERN |
4371 PPC_ALTIVEC;
4372 pcc->msr_mask = (1ull << MSR_VR) |
4373 (1ull << MSR_POW) |
4374 (1ull << MSR_ILE) |
4375 (1ull << MSR_EE) |
4376 (1ull << MSR_PR) |
4377 (1ull << MSR_FP) |
4378 (1ull << MSR_ME) |
4379 (1ull << MSR_FE0) |
4380 (1ull << MSR_SE) |
4381 (1ull << MSR_DE) |
4382 (1ull << MSR_FE1) |
4383 (1ull << MSR_EP) |
4384 (1ull << MSR_IR) |
4385 (1ull << MSR_DR) |
4386 (1ull << MSR_PMM) |
4387 (1ull << MSR_RI) |
4388 (1ull << MSR_LE);
4389 pcc->mmu_model = POWERPC_MMU_32B;
4390 pcc->excp_model = POWERPC_EXCP_74xx;
4391 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4392 pcc->bfd_mach = bfd_mach_ppc_7400;
4393 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4394 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4395 POWERPC_FLAG_BUS_CLK;
4396 }
4397
init_proc_7450(CPUPPCState * env)4398 static void init_proc_7450(CPUPPCState *env)
4399 {
4400 register_non_embedded_sprs(env);
4401 register_sdr1_sprs(env);
4402 register_74xx_sprs(env);
4403 vscr_init(env, 0x00010000);
4404 /* Level 3 cache control */
4405 register_l3_ctrl(env);
4406 /* L3ITCR1 */
4407 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411 /* L3ITCR2 */
4412 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* L3ITCR3 */
4417 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* L3OHCR */
4422 spr_register(env, SPR_L3OHCR, "L3OHCR",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
4426
4427 spr_register(env, SPR_UBAMR, "UBAMR",
4428 &spr_read_ureg, SPR_NOACCESS,
4429 &spr_read_ureg, SPR_NOACCESS,
4430 0x00000000);
4431 /* LDSTCR */
4432 spr_register(env, SPR_LDSTCR, "LDSTCR",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000);
4436 /* ICTRL */
4437 spr_register(env, SPR_ICTRL, "ICTRL",
4438 SPR_NOACCESS, SPR_NOACCESS,
4439 &spr_read_generic, &spr_write_generic,
4440 0x00000000);
4441 /* MSSSR0 */
4442 spr_register(env, SPR_MSSSR0, "MSSSR0",
4443 SPR_NOACCESS, SPR_NOACCESS,
4444 &spr_read_generic, &spr_write_generic,
4445 0x00000000);
4446 /* PMC */
4447 spr_register(env, SPR_7XX_PMC5, "PMC5",
4448 SPR_NOACCESS, SPR_NOACCESS,
4449 &spr_read_generic, &spr_write_generic,
4450 0x00000000);
4451
4452 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4453 &spr_read_ureg, SPR_NOACCESS,
4454 &spr_read_ureg, SPR_NOACCESS,
4455 0x00000000);
4456
4457 spr_register(env, SPR_7XX_PMC6, "PMC6",
4458 SPR_NOACCESS, SPR_NOACCESS,
4459 &spr_read_generic, &spr_write_generic,
4460 0x00000000);
4461
4462 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4463 &spr_read_ureg, SPR_NOACCESS,
4464 &spr_read_ureg, SPR_NOACCESS,
4465 0x00000000);
4466 /* Memory management */
4467 register_low_BATs(env);
4468 init_excp_7450(env);
4469 env->dcache_line_size = 32;
4470 env->icache_line_size = 32;
4471 /* Allocate hardware IRQ controller */
4472 ppc6xx_irq_init(env_archcpu(env));
4473 }
4474
4475 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4476 {
4477 DeviceClass *dc = DEVICE_CLASS(oc);
4478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4479
4480 dc->desc = "PowerPC 7450 (aka G4)";
4481 pcc->init_proc = init_proc_7450;
4482 pcc->check_pow = check_pow_hid0_74xx;
4483 pcc->check_attn = check_attn_none;
4484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4485 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4486 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4487 PPC_FLOAT_STFIWX |
4488 PPC_CACHE | PPC_CACHE_ICBI |
4489 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4490 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4491 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4492 PPC_MEM_TLBIA |
4493 PPC_SEGMENT | PPC_EXTERN |
4494 PPC_ALTIVEC;
4495 pcc->msr_mask = (1ull << MSR_VR) |
4496 (1ull << MSR_POW) |
4497 (1ull << MSR_ILE) |
4498 (1ull << MSR_EE) |
4499 (1ull << MSR_PR) |
4500 (1ull << MSR_FP) |
4501 (1ull << MSR_ME) |
4502 (1ull << MSR_FE0) |
4503 (1ull << MSR_SE) |
4504 (1ull << MSR_DE) |
4505 (1ull << MSR_FE1) |
4506 (1ull << MSR_EP) |
4507 (1ull << MSR_IR) |
4508 (1ull << MSR_DR) |
4509 (1ull << MSR_PMM) |
4510 (1ull << MSR_RI) |
4511 (1ull << MSR_LE);
4512 pcc->mmu_model = POWERPC_MMU_32B;
4513 pcc->excp_model = POWERPC_EXCP_74xx;
4514 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4515 pcc->bfd_mach = bfd_mach_ppc_7400;
4516 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4517 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4518 POWERPC_FLAG_BUS_CLK;
4519 }
4520
init_proc_7445(CPUPPCState * env)4521 static void init_proc_7445(CPUPPCState *env)
4522 {
4523 register_non_embedded_sprs(env);
4524 register_sdr1_sprs(env);
4525 register_74xx_sprs(env);
4526 vscr_init(env, 0x00010000);
4527 /* LDSTCR */
4528 spr_register(env, SPR_LDSTCR, "LDSTCR",
4529 SPR_NOACCESS, SPR_NOACCESS,
4530 &spr_read_generic, &spr_write_generic,
4531 0x00000000);
4532 /* ICTRL */
4533 spr_register(env, SPR_ICTRL, "ICTRL",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 /* MSSSR0 */
4538 spr_register(env, SPR_MSSSR0, "MSSSR0",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542 /* PMC */
4543 spr_register(env, SPR_7XX_PMC5, "PMC5",
4544 SPR_NOACCESS, SPR_NOACCESS,
4545 &spr_read_generic, &spr_write_generic,
4546 0x00000000);
4547
4548 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4549 &spr_read_ureg, SPR_NOACCESS,
4550 &spr_read_ureg, SPR_NOACCESS,
4551 0x00000000);
4552
4553 spr_register(env, SPR_7XX_PMC6, "PMC6",
4554 SPR_NOACCESS, SPR_NOACCESS,
4555 &spr_read_generic, &spr_write_generic,
4556 0x00000000);
4557
4558 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4559 &spr_read_ureg, SPR_NOACCESS,
4560 &spr_read_ureg, SPR_NOACCESS,
4561 0x00000000);
4562 /* SPRGs */
4563 spr_register(env, SPR_SPRG4, "SPRG4",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, &spr_write_generic,
4566 0x00000000);
4567 spr_register(env, SPR_USPRG4, "USPRG4",
4568 &spr_read_ureg, SPR_NOACCESS,
4569 &spr_read_ureg, SPR_NOACCESS,
4570 0x00000000);
4571 spr_register(env, SPR_SPRG5, "SPRG5",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575 spr_register(env, SPR_USPRG5, "USPRG5",
4576 &spr_read_ureg, SPR_NOACCESS,
4577 &spr_read_ureg, SPR_NOACCESS,
4578 0x00000000);
4579 spr_register(env, SPR_SPRG6, "SPRG6",
4580 SPR_NOACCESS, SPR_NOACCESS,
4581 &spr_read_generic, &spr_write_generic,
4582 0x00000000);
4583 spr_register(env, SPR_USPRG6, "USPRG6",
4584 &spr_read_ureg, SPR_NOACCESS,
4585 &spr_read_ureg, SPR_NOACCESS,
4586 0x00000000);
4587 spr_register(env, SPR_SPRG7, "SPRG7",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 spr_register(env, SPR_USPRG7, "USPRG7",
4592 &spr_read_ureg, SPR_NOACCESS,
4593 &spr_read_ureg, SPR_NOACCESS,
4594 0x00000000);
4595 /* Memory management */
4596 register_low_BATs(env);
4597 register_high_BATs(env);
4598 init_excp_7450(env);
4599 env->dcache_line_size = 32;
4600 env->icache_line_size = 32;
4601 /* Allocate hardware IRQ controller */
4602 ppc6xx_irq_init(env_archcpu(env));
4603 }
4604
4605 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4606 {
4607 DeviceClass *dc = DEVICE_CLASS(oc);
4608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4609
4610 dc->desc = "PowerPC 7445 (aka G4)";
4611 pcc->init_proc = init_proc_7445;
4612 pcc->check_pow = check_pow_hid0_74xx;
4613 pcc->check_attn = check_attn_none;
4614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4616 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4617 PPC_FLOAT_STFIWX |
4618 PPC_CACHE | PPC_CACHE_ICBI |
4619 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4620 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4621 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4622 PPC_MEM_TLBIA |
4623 PPC_SEGMENT | PPC_EXTERN |
4624 PPC_ALTIVEC;
4625 pcc->msr_mask = (1ull << MSR_VR) |
4626 (1ull << MSR_POW) |
4627 (1ull << MSR_ILE) |
4628 (1ull << MSR_EE) |
4629 (1ull << MSR_PR) |
4630 (1ull << MSR_FP) |
4631 (1ull << MSR_ME) |
4632 (1ull << MSR_FE0) |
4633 (1ull << MSR_SE) |
4634 (1ull << MSR_DE) |
4635 (1ull << MSR_FE1) |
4636 (1ull << MSR_EP) |
4637 (1ull << MSR_IR) |
4638 (1ull << MSR_DR) |
4639 (1ull << MSR_PMM) |
4640 (1ull << MSR_RI) |
4641 (1ull << MSR_LE);
4642 pcc->mmu_model = POWERPC_MMU_32B;
4643 pcc->excp_model = POWERPC_EXCP_74xx;
4644 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4645 pcc->bfd_mach = bfd_mach_ppc_7400;
4646 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4647 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4648 POWERPC_FLAG_BUS_CLK;
4649 }
4650
init_proc_7455(CPUPPCState * env)4651 static void init_proc_7455(CPUPPCState *env)
4652 {
4653 register_non_embedded_sprs(env);
4654 register_sdr1_sprs(env);
4655 register_74xx_sprs(env);
4656 vscr_init(env, 0x00010000);
4657 /* Level 3 cache control */
4658 register_l3_ctrl(env);
4659 /* LDSTCR */
4660 spr_register(env, SPR_LDSTCR, "LDSTCR",
4661 SPR_NOACCESS, SPR_NOACCESS,
4662 &spr_read_generic, &spr_write_generic,
4663 0x00000000);
4664 /* ICTRL */
4665 spr_register(env, SPR_ICTRL, "ICTRL",
4666 SPR_NOACCESS, SPR_NOACCESS,
4667 &spr_read_generic, &spr_write_generic,
4668 0x00000000);
4669 /* MSSSR0 */
4670 spr_register(env, SPR_MSSSR0, "MSSSR0",
4671 SPR_NOACCESS, SPR_NOACCESS,
4672 &spr_read_generic, &spr_write_generic,
4673 0x00000000);
4674 /* PMC */
4675 spr_register(env, SPR_7XX_PMC5, "PMC5",
4676 SPR_NOACCESS, SPR_NOACCESS,
4677 &spr_read_generic, &spr_write_generic,
4678 0x00000000);
4679
4680 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4681 &spr_read_ureg, SPR_NOACCESS,
4682 &spr_read_ureg, SPR_NOACCESS,
4683 0x00000000);
4684
4685 spr_register(env, SPR_7XX_PMC6, "PMC6",
4686 SPR_NOACCESS, SPR_NOACCESS,
4687 &spr_read_generic, &spr_write_generic,
4688 0x00000000);
4689
4690 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4691 &spr_read_ureg, SPR_NOACCESS,
4692 &spr_read_ureg, SPR_NOACCESS,
4693 0x00000000);
4694 /* SPRGs */
4695 spr_register(env, SPR_SPRG4, "SPRG4",
4696 SPR_NOACCESS, SPR_NOACCESS,
4697 &spr_read_generic, &spr_write_generic,
4698 0x00000000);
4699 spr_register(env, SPR_USPRG4, "USPRG4",
4700 &spr_read_ureg, SPR_NOACCESS,
4701 &spr_read_ureg, SPR_NOACCESS,
4702 0x00000000);
4703 spr_register(env, SPR_SPRG5, "SPRG5",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 spr_register(env, SPR_USPRG5, "USPRG5",
4708 &spr_read_ureg, SPR_NOACCESS,
4709 &spr_read_ureg, SPR_NOACCESS,
4710 0x00000000);
4711 spr_register(env, SPR_SPRG6, "SPRG6",
4712 SPR_NOACCESS, SPR_NOACCESS,
4713 &spr_read_generic, &spr_write_generic,
4714 0x00000000);
4715 spr_register(env, SPR_USPRG6, "USPRG6",
4716 &spr_read_ureg, SPR_NOACCESS,
4717 &spr_read_ureg, SPR_NOACCESS,
4718 0x00000000);
4719 spr_register(env, SPR_SPRG7, "SPRG7",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, &spr_write_generic,
4722 0x00000000);
4723 spr_register(env, SPR_USPRG7, "USPRG7",
4724 &spr_read_ureg, SPR_NOACCESS,
4725 &spr_read_ureg, SPR_NOACCESS,
4726 0x00000000);
4727 /* Memory management */
4728 register_low_BATs(env);
4729 register_high_BATs(env);
4730 init_excp_7450(env);
4731 env->dcache_line_size = 32;
4732 env->icache_line_size = 32;
4733 /* Allocate hardware IRQ controller */
4734 ppc6xx_irq_init(env_archcpu(env));
4735 }
4736
4737 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4738 {
4739 DeviceClass *dc = DEVICE_CLASS(oc);
4740 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4741
4742 dc->desc = "PowerPC 7455 (aka G4)";
4743 pcc->init_proc = init_proc_7455;
4744 pcc->check_pow = check_pow_hid0_74xx;
4745 pcc->check_attn = check_attn_none;
4746 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4747 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4748 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4749 PPC_FLOAT_STFIWX |
4750 PPC_CACHE | PPC_CACHE_ICBI |
4751 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4752 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4753 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4754 PPC_MEM_TLBIA |
4755 PPC_SEGMENT | PPC_EXTERN |
4756 PPC_ALTIVEC;
4757 pcc->msr_mask = (1ull << MSR_VR) |
4758 (1ull << MSR_POW) |
4759 (1ull << MSR_ILE) |
4760 (1ull << MSR_EE) |
4761 (1ull << MSR_PR) |
4762 (1ull << MSR_FP) |
4763 (1ull << MSR_ME) |
4764 (1ull << MSR_FE0) |
4765 (1ull << MSR_SE) |
4766 (1ull << MSR_DE) |
4767 (1ull << MSR_FE1) |
4768 (1ull << MSR_EP) |
4769 (1ull << MSR_IR) |
4770 (1ull << MSR_DR) |
4771 (1ull << MSR_PMM) |
4772 (1ull << MSR_RI) |
4773 (1ull << MSR_LE);
4774 pcc->mmu_model = POWERPC_MMU_32B;
4775 pcc->excp_model = POWERPC_EXCP_74xx;
4776 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4777 pcc->bfd_mach = bfd_mach_ppc_7400;
4778 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4779 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4780 POWERPC_FLAG_BUS_CLK;
4781 }
4782
init_proc_7457(CPUPPCState * env)4783 static void init_proc_7457(CPUPPCState *env)
4784 {
4785 register_non_embedded_sprs(env);
4786 register_sdr1_sprs(env);
4787 register_74xx_sprs(env);
4788 vscr_init(env, 0x00010000);
4789 /* Level 3 cache control */
4790 register_l3_ctrl(env);
4791 /* L3ITCR1 */
4792 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 /* L3ITCR2 */
4797 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801 /* L3ITCR3 */
4802 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4803 SPR_NOACCESS, SPR_NOACCESS,
4804 &spr_read_generic, &spr_write_generic,
4805 0x00000000);
4806 /* L3OHCR */
4807 spr_register(env, SPR_L3OHCR, "L3OHCR",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 /* LDSTCR */
4812 spr_register(env, SPR_LDSTCR, "LDSTCR",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* ICTRL */
4817 spr_register(env, SPR_ICTRL, "ICTRL",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* MSSSR0 */
4822 spr_register(env, SPR_MSSSR0, "MSSSR0",
4823 SPR_NOACCESS, SPR_NOACCESS,
4824 &spr_read_generic, &spr_write_generic,
4825 0x00000000);
4826 /* PMC */
4827 spr_register(env, SPR_7XX_PMC5, "PMC5",
4828 SPR_NOACCESS, SPR_NOACCESS,
4829 &spr_read_generic, &spr_write_generic,
4830 0x00000000);
4831
4832 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4833 &spr_read_ureg, SPR_NOACCESS,
4834 &spr_read_ureg, SPR_NOACCESS,
4835 0x00000000);
4836
4837 spr_register(env, SPR_7XX_PMC6, "PMC6",
4838 SPR_NOACCESS, SPR_NOACCESS,
4839 &spr_read_generic, &spr_write_generic,
4840 0x00000000);
4841
4842 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4843 &spr_read_ureg, SPR_NOACCESS,
4844 &spr_read_ureg, SPR_NOACCESS,
4845 0x00000000);
4846 /* SPRGs */
4847 spr_register(env, SPR_SPRG4, "SPRG4",
4848 SPR_NOACCESS, SPR_NOACCESS,
4849 &spr_read_generic, &spr_write_generic,
4850 0x00000000);
4851 spr_register(env, SPR_USPRG4, "USPRG4",
4852 &spr_read_ureg, SPR_NOACCESS,
4853 &spr_read_ureg, SPR_NOACCESS,
4854 0x00000000);
4855 spr_register(env, SPR_SPRG5, "SPRG5",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 spr_register(env, SPR_USPRG5, "USPRG5",
4860 &spr_read_ureg, SPR_NOACCESS,
4861 &spr_read_ureg, SPR_NOACCESS,
4862 0x00000000);
4863 spr_register(env, SPR_SPRG6, "SPRG6",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 spr_register(env, SPR_USPRG6, "USPRG6",
4868 &spr_read_ureg, SPR_NOACCESS,
4869 &spr_read_ureg, SPR_NOACCESS,
4870 0x00000000);
4871 spr_register(env, SPR_SPRG7, "SPRG7",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 spr_register(env, SPR_USPRG7, "USPRG7",
4876 &spr_read_ureg, SPR_NOACCESS,
4877 &spr_read_ureg, SPR_NOACCESS,
4878 0x00000000);
4879 /* Memory management */
4880 register_low_BATs(env);
4881 register_high_BATs(env);
4882 init_excp_7450(env);
4883 env->dcache_line_size = 32;
4884 env->icache_line_size = 32;
4885 /* Allocate hardware IRQ controller */
4886 ppc6xx_irq_init(env_archcpu(env));
4887 }
4888
4889 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4890 {
4891 DeviceClass *dc = DEVICE_CLASS(oc);
4892 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4893
4894 dc->desc = "PowerPC 7457 (aka G4)";
4895 pcc->init_proc = init_proc_7457;
4896 pcc->check_pow = check_pow_hid0_74xx;
4897 pcc->check_attn = check_attn_none;
4898 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4899 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4900 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4901 PPC_FLOAT_STFIWX |
4902 PPC_CACHE | PPC_CACHE_ICBI |
4903 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4904 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4905 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4906 PPC_MEM_TLBIA |
4907 PPC_SEGMENT | PPC_EXTERN |
4908 PPC_ALTIVEC;
4909 pcc->msr_mask = (1ull << MSR_VR) |
4910 (1ull << MSR_POW) |
4911 (1ull << MSR_ILE) |
4912 (1ull << MSR_EE) |
4913 (1ull << MSR_PR) |
4914 (1ull << MSR_FP) |
4915 (1ull << MSR_ME) |
4916 (1ull << MSR_FE0) |
4917 (1ull << MSR_SE) |
4918 (1ull << MSR_DE) |
4919 (1ull << MSR_FE1) |
4920 (1ull << MSR_EP) |
4921 (1ull << MSR_IR) |
4922 (1ull << MSR_DR) |
4923 (1ull << MSR_PMM) |
4924 (1ull << MSR_RI) |
4925 (1ull << MSR_LE);
4926 pcc->mmu_model = POWERPC_MMU_32B;
4927 pcc->excp_model = POWERPC_EXCP_74xx;
4928 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4929 pcc->bfd_mach = bfd_mach_ppc_7400;
4930 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4931 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4932 POWERPC_FLAG_BUS_CLK;
4933 }
4934
init_proc_e600(CPUPPCState * env)4935 static void init_proc_e600(CPUPPCState *env)
4936 {
4937 register_non_embedded_sprs(env);
4938 register_sdr1_sprs(env);
4939 register_74xx_sprs(env);
4940 vscr_init(env, 0x00010000);
4941
4942 spr_register(env, SPR_UBAMR, "UBAMR",
4943 &spr_read_ureg, SPR_NOACCESS,
4944 &spr_read_ureg, SPR_NOACCESS,
4945 0x00000000);
4946
4947 spr_register(env, SPR_LDSTCR, "LDSTCR",
4948 SPR_NOACCESS, SPR_NOACCESS,
4949 &spr_read_generic, &spr_write_generic,
4950 0x00000000);
4951
4952 spr_register(env, SPR_ICTRL, "ICTRL",
4953 SPR_NOACCESS, SPR_NOACCESS,
4954 &spr_read_generic, &spr_write_generic,
4955 0x00000000);
4956
4957 spr_register(env, SPR_MSSSR0, "MSSSR0",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961
4962 spr_register(env, SPR_7XX_PMC5, "PMC5",
4963 SPR_NOACCESS, SPR_NOACCESS,
4964 &spr_read_generic, &spr_write_generic,
4965 0x00000000);
4966
4967 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4968 &spr_read_ureg, SPR_NOACCESS,
4969 &spr_read_ureg, SPR_NOACCESS,
4970 0x00000000);
4971
4972 spr_register(env, SPR_7XX_PMC6, "PMC6",
4973 SPR_NOACCESS, SPR_NOACCESS,
4974 &spr_read_generic, &spr_write_generic,
4975 0x00000000);
4976
4977 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4978 &spr_read_ureg, SPR_NOACCESS,
4979 &spr_read_ureg, SPR_NOACCESS,
4980 0x00000000);
4981 /* SPRGs */
4982 spr_register(env, SPR_SPRG4, "SPRG4",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0x00000000);
4986 spr_register(env, SPR_USPRG4, "USPRG4",
4987 &spr_read_ureg, SPR_NOACCESS,
4988 &spr_read_ureg, SPR_NOACCESS,
4989 0x00000000);
4990 spr_register(env, SPR_SPRG5, "SPRG5",
4991 SPR_NOACCESS, SPR_NOACCESS,
4992 &spr_read_generic, &spr_write_generic,
4993 0x00000000);
4994 spr_register(env, SPR_USPRG5, "USPRG5",
4995 &spr_read_ureg, SPR_NOACCESS,
4996 &spr_read_ureg, SPR_NOACCESS,
4997 0x00000000);
4998 spr_register(env, SPR_SPRG6, "SPRG6",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 spr_register(env, SPR_USPRG6, "USPRG6",
5003 &spr_read_ureg, SPR_NOACCESS,
5004 &spr_read_ureg, SPR_NOACCESS,
5005 0x00000000);
5006 spr_register(env, SPR_SPRG7, "SPRG7",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 spr_register(env, SPR_USPRG7, "USPRG7",
5011 &spr_read_ureg, SPR_NOACCESS,
5012 &spr_read_ureg, SPR_NOACCESS,
5013 0x00000000);
5014 /* Memory management */
5015 register_low_BATs(env);
5016 register_high_BATs(env);
5017 init_excp_7450(env);
5018 env->dcache_line_size = 32;
5019 env->icache_line_size = 32;
5020 /* Allocate hardware IRQ controller */
5021 ppc6xx_irq_init(env_archcpu(env));
5022 }
5023
POWERPC_FAMILY(e600)5024 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5025 {
5026 DeviceClass *dc = DEVICE_CLASS(oc);
5027 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5028
5029 dc->desc = "PowerPC e600";
5030 pcc->init_proc = init_proc_e600;
5031 pcc->check_pow = check_pow_hid0_74xx;
5032 pcc->check_attn = check_attn_none;
5033 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5035 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5036 PPC_FLOAT_STFIWX |
5037 PPC_CACHE | PPC_CACHE_ICBI |
5038 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5039 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5040 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5041 PPC_MEM_TLBIA |
5042 PPC_SEGMENT | PPC_EXTERN |
5043 PPC_ALTIVEC;
5044 pcc->insns_flags2 = PPC_NONE;
5045 pcc->msr_mask = (1ull << MSR_VR) |
5046 (1ull << MSR_POW) |
5047 (1ull << MSR_ILE) |
5048 (1ull << MSR_EE) |
5049 (1ull << MSR_PR) |
5050 (1ull << MSR_FP) |
5051 (1ull << MSR_ME) |
5052 (1ull << MSR_FE0) |
5053 (1ull << MSR_SE) |
5054 (1ull << MSR_DE) |
5055 (1ull << MSR_FE1) |
5056 (1ull << MSR_EP) |
5057 (1ull << MSR_IR) |
5058 (1ull << MSR_DR) |
5059 (1ull << MSR_PMM) |
5060 (1ull << MSR_RI) |
5061 (1ull << MSR_LE);
5062 pcc->mmu_model = POWERPC_MMU_32B;
5063 pcc->excp_model = POWERPC_EXCP_74xx;
5064 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5065 pcc->bfd_mach = bfd_mach_ppc_7400;
5066 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5067 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5068 POWERPC_FLAG_BUS_CLK;
5069 }
5070
5071 #if defined(TARGET_PPC64)
5072 #if defined(CONFIG_USER_ONLY)
5073 #define POWERPC970_HID5_INIT 0x00000080
5074 #else
5075 #define POWERPC970_HID5_INIT 0x00000000
5076 #endif
5077
check_pow_970(CPUPPCState * env)5078 static int check_pow_970(CPUPPCState *env)
5079 {
5080 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5081 return 1;
5082 }
5083
5084 return 0;
5085 }
5086
register_970_hid_sprs(CPUPPCState * env)5087 static void register_970_hid_sprs(CPUPPCState *env)
5088 {
5089 /* Hardware implementation registers */
5090 spr_register(env, SPR_HID0, "HID0",
5091 SPR_NOACCESS, SPR_NOACCESS,
5092 &spr_read_generic, &spr_write_clear,
5093 0x60000000);
5094 spr_register(env, SPR_HID1, "HID1",
5095 SPR_NOACCESS, SPR_NOACCESS,
5096 &spr_read_generic, &spr_write_generic,
5097 0x00000000);
5098 spr_register(env, SPR_970_HID5, "HID5",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_generic,
5101 POWERPC970_HID5_INIT);
5102 }
5103
register_970_hior_sprs(CPUPPCState * env)5104 static void register_970_hior_sprs(CPUPPCState *env)
5105 {
5106 spr_register(env, SPR_HIOR, "HIOR",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 &spr_read_hior, &spr_write_hior,
5109 0x00000000);
5110 }
5111
register_book3s_ctrl_sprs(CPUPPCState * env)5112 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5113 {
5114 spr_register(env, SPR_CTRL, "CTRL",
5115 SPR_NOACCESS, SPR_NOACCESS,
5116 SPR_NOACCESS, &spr_write_CTRL,
5117 0x00000000);
5118 spr_register(env, SPR_UCTRL, "UCTRL",
5119 &spr_read_ureg, SPR_NOACCESS,
5120 &spr_read_ureg, SPR_NOACCESS,
5121 0x00000000);
5122 }
5123
register_book3s_altivec_sprs(CPUPPCState * env)5124 static void register_book3s_altivec_sprs(CPUPPCState *env)
5125 {
5126 if (!(env->insns_flags & PPC_ALTIVEC)) {
5127 return;
5128 }
5129
5130 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5131 &spr_read_generic, &spr_write_generic32,
5132 &spr_read_generic, &spr_write_generic32,
5133 KVM_REG_PPC_VRSAVE, 0x00000000);
5134
5135 }
5136
register_book3s_dbg_sprs(CPUPPCState * env)5137 static void register_book3s_dbg_sprs(CPUPPCState *env)
5138 {
5139 /*
5140 * TODO: different specs define different scopes for these,
5141 * will have to address this:
5142 * 970: super/write and super/read
5143 * powerisa 2.03..2.04: hypv/write and super/read.
5144 * powerisa 2.05 and newer: hypv/write and hypv/read.
5145 */
5146 spr_register_kvm(env, SPR_DABR, "DABR",
5147 SPR_NOACCESS, SPR_NOACCESS,
5148 &spr_read_generic, &spr_write_generic,
5149 KVM_REG_PPC_DABR, 0x00000000);
5150 spr_register_kvm(env, SPR_DABRX, "DABRX",
5151 SPR_NOACCESS, SPR_NOACCESS,
5152 &spr_read_generic, &spr_write_generic,
5153 KVM_REG_PPC_DABRX, 0x00000000);
5154 }
5155
register_book3s_207_dbg_sprs(CPUPPCState * env)5156 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5157 {
5158 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 SPR_NOACCESS, SPR_NOACCESS,
5161 &spr_read_generic, &spr_write_dawr0,
5162 KVM_REG_PPC_DAWR, 0x00000000);
5163 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 SPR_NOACCESS, SPR_NOACCESS,
5166 &spr_read_generic, &spr_write_dawrx0,
5167 KVM_REG_PPC_DAWRX, 0x00000000);
5168 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5169 SPR_NOACCESS, SPR_NOACCESS,
5170 SPR_NOACCESS, SPR_NOACCESS,
5171 &spr_read_generic, &spr_write_ciabr,
5172 KVM_REG_PPC_CIABR, 0x00000000);
5173 }
5174
register_970_dbg_sprs(CPUPPCState * env)5175 static void register_970_dbg_sprs(CPUPPCState *env)
5176 {
5177 /* Breakpoints */
5178 spr_register(env, SPR_IABR, "IABR",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 }
5183
register_book3s_pmu_sup_sprs(CPUPPCState * env)5184 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5185 {
5186 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_MMCR0,
5189 KVM_REG_PPC_MMCR0, 0x80000000);
5190 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 &spr_read_generic, &spr_write_MMCR1,
5193 KVM_REG_PPC_MMCR1, 0x00000000);
5194 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, &spr_write_MMCRA,
5197 KVM_REG_PPC_MMCRA, 0x00000000);
5198 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5199 SPR_NOACCESS, SPR_NOACCESS,
5200 &spr_read_PMC, &spr_write_PMC,
5201 KVM_REG_PPC_PMC1, 0x00000000);
5202 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5203 SPR_NOACCESS, SPR_NOACCESS,
5204 &spr_read_PMC, &spr_write_PMC,
5205 KVM_REG_PPC_PMC2, 0x00000000);
5206 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5207 SPR_NOACCESS, SPR_NOACCESS,
5208 &spr_read_PMC, &spr_write_PMC,
5209 KVM_REG_PPC_PMC3, 0x00000000);
5210 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_PMC, &spr_write_PMC,
5213 KVM_REG_PPC_PMC4, 0x00000000);
5214 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5215 SPR_NOACCESS, SPR_NOACCESS,
5216 &spr_read_PMC, &spr_write_PMC,
5217 KVM_REG_PPC_PMC5, 0x00000000);
5218 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5219 SPR_NOACCESS, SPR_NOACCESS,
5220 &spr_read_PMC, &spr_write_PMC,
5221 KVM_REG_PPC_PMC6, 0x00000000);
5222 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5223 SPR_NOACCESS, SPR_NOACCESS,
5224 &spr_read_generic, &spr_write_generic,
5225 KVM_REG_PPC_SIAR, 0x00000000);
5226 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5227 SPR_NOACCESS, SPR_NOACCESS,
5228 &spr_read_generic, &spr_write_generic,
5229 KVM_REG_PPC_SDAR, 0x00000000);
5230 }
5231
register_book3s_pmu_user_sprs(CPUPPCState * env)5232 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5233 {
5234 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5235 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5236 &spr_read_ureg, &spr_write_ureg,
5237 0x80000000);
5238 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5239 &spr_read_ureg, SPR_NOACCESS,
5240 &spr_read_ureg, &spr_write_ureg,
5241 0x00000000);
5242 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5243 &spr_read_ureg, SPR_NOACCESS,
5244 &spr_read_ureg, &spr_write_ureg,
5245 0x00000000);
5246 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5247 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5248 &spr_read_ureg, &spr_write_ureg,
5249 0x00000000);
5250 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5251 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5252 &spr_read_ureg, &spr_write_ureg,
5253 0x00000000);
5254 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5255 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5256 &spr_read_ureg, &spr_write_ureg,
5257 0x00000000);
5258 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5259 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5260 &spr_read_ureg, &spr_write_ureg,
5261 0x00000000);
5262 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5263 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5264 &spr_read_ureg, &spr_write_ureg,
5265 0x00000000);
5266 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5267 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5268 &spr_read_ureg, &spr_write_ureg,
5269 0x00000000);
5270 spr_register(env, SPR_POWER_USIAR, "USIAR",
5271 &spr_read_ureg, SPR_NOACCESS,
5272 &spr_read_ureg, &spr_write_ureg,
5273 0x00000000);
5274 spr_register(env, SPR_POWER_USDAR, "USDAR",
5275 &spr_read_ureg, SPR_NOACCESS,
5276 &spr_read_ureg, &spr_write_ureg,
5277 0x00000000);
5278 }
5279
register_970_pmu_sup_sprs(CPUPPCState * env)5280 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5281 {
5282 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 KVM_REG_PPC_PMC7, 0x00000000);
5286 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5287 SPR_NOACCESS, SPR_NOACCESS,
5288 &spr_read_generic, &spr_write_generic,
5289 KVM_REG_PPC_PMC8, 0x00000000);
5290 }
5291
register_970_pmu_user_sprs(CPUPPCState * env)5292 static void register_970_pmu_user_sprs(CPUPPCState *env)
5293 {
5294 spr_register(env, SPR_970_UPMC7, "UPMC7",
5295 &spr_read_ureg, SPR_NOACCESS,
5296 &spr_read_ureg, &spr_write_ureg,
5297 0x00000000);
5298 spr_register(env, SPR_970_UPMC8, "UPMC8",
5299 &spr_read_ureg, SPR_NOACCESS,
5300 &spr_read_ureg, &spr_write_ureg,
5301 0x00000000);
5302 }
5303
register_power8_pmu_sup_sprs(CPUPPCState * env)5304 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5305 {
5306 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 KVM_REG_PPC_MMCR2, 0x00000000);
5310 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 KVM_REG_PPC_MMCRS, 0x00000000);
5314 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5315 SPR_NOACCESS, SPR_NOACCESS,
5316 &spr_read_generic, &spr_write_generic,
5317 KVM_REG_PPC_SIER, 0x00000000);
5318 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 KVM_REG_PPC_SPMC1, 0x00000000);
5322 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 &spr_read_generic, &spr_write_generic,
5325 KVM_REG_PPC_SPMC2, 0x00000000);
5326 spr_register_kvm(env, SPR_TACR, "TACR",
5327 SPR_NOACCESS, SPR_NOACCESS,
5328 &spr_read_generic, &spr_write_generic,
5329 KVM_REG_PPC_TACR, 0x00000000);
5330 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5331 SPR_NOACCESS, SPR_NOACCESS,
5332 &spr_read_generic, &spr_write_generic,
5333 KVM_REG_PPC_TCSCR, 0x00000000);
5334 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5335 SPR_NOACCESS, SPR_NOACCESS,
5336 &spr_read_generic, &spr_write_generic,
5337 KVM_REG_PPC_CSIGR, 0x00000000);
5338 }
5339
register_power8_pmu_user_sprs(CPUPPCState * env)5340 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5341 {
5342 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5343 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5344 &spr_read_ureg, &spr_write_ureg,
5345 0x00000000);
5346 spr_register(env, SPR_POWER_USIER, "USIER",
5347 &spr_read_generic, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 }
5351
register_power10_pmu_sup_sprs(CPUPPCState * env)5352 static void register_power10_pmu_sup_sprs(CPUPPCState *env)
5353 {
5354 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
5355 SPR_NOACCESS, SPR_NOACCESS,
5356 &spr_read_generic, &spr_write_generic,
5357 KVM_REG_PPC_MMCR3, 0x00000000);
5358 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
5359 SPR_NOACCESS, SPR_NOACCESS,
5360 &spr_read_generic, &spr_write_generic,
5361 KVM_REG_PPC_SIER2, 0x00000000);
5362 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
5363 SPR_NOACCESS, SPR_NOACCESS,
5364 &spr_read_generic, &spr_write_generic,
5365 KVM_REG_PPC_SIER3, 0x00000000);
5366 }
5367
register_power10_pmu_user_sprs(CPUPPCState * env)5368 static void register_power10_pmu_user_sprs(CPUPPCState *env)
5369 {
5370 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
5371 &spr_read_generic, &spr_write_generic,
5372 &spr_read_generic, &spr_write_generic,
5373 0x00000000);
5374 spr_register(env, SPR_POWER_USIER2, "USIER2",
5375 &spr_read_generic, SPR_NOACCESS,
5376 &spr_read_generic, &spr_write_generic,
5377 0x00000000);
5378 spr_register(env, SPR_POWER_USIER3, "USIER3",
5379 &spr_read_generic, SPR_NOACCESS,
5380 &spr_read_generic, &spr_write_generic,
5381 0x00000000);
5382 }
5383
register_power5p_ear_sprs(CPUPPCState * env)5384 static void register_power5p_ear_sprs(CPUPPCState *env)
5385 {
5386 /* External access control */
5387 spr_register(env, SPR_EAR, "EAR",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 &spr_read_generic, &spr_write_generic,
5390 0x00000000);
5391 }
5392
register_power5p_tb_sprs(CPUPPCState * env)5393 static void register_power5p_tb_sprs(CPUPPCState *env)
5394 {
5395 /* TBU40 (High 40 bits of the Timebase register */
5396 spr_register_hv(env, SPR_TBU40, "TBU40",
5397 SPR_NOACCESS, SPR_NOACCESS,
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 SPR_NOACCESS, &spr_write_tbu40,
5400 0x00000000);
5401 }
5402
register_970_lpar_sprs(CPUPPCState * env)5403 static void register_970_lpar_sprs(CPUPPCState *env)
5404 {
5405 #if !defined(CONFIG_USER_ONLY)
5406 /*
5407 * PPC970: HID4 covers things later controlled by the LPCR and
5408 * RMOR in later CPUs, but with a different encoding. We only
5409 * support the 970 in "Apple mode" which has all hypervisor
5410 * facilities disabled by strapping, so we can basically just
5411 * ignore it
5412 */
5413 spr_register(env, SPR_970_HID4, "HID4",
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 #endif
5418 }
5419
register_power5p_lpar_sprs(CPUPPCState * env)5420 static void register_power5p_lpar_sprs(CPUPPCState *env)
5421 {
5422 #if !defined(CONFIG_USER_ONLY)
5423 /* Logical partitioning */
5424 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_lpcr,
5428 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5429 spr_register_hv(env, SPR_HDEC, "HDEC",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 SPR_NOACCESS, SPR_NOACCESS,
5432 &spr_read_hdecr, &spr_write_hdecr, 0);
5433 #endif
5434 }
5435
register_book3s_ids_sprs(CPUPPCState * env)5436 static void register_book3s_ids_sprs(CPUPPCState *env)
5437 {
5438 /* FIXME: Will need to deal with thread vs core only SPRs */
5439
5440 /* Processor identification */
5441 spr_register_hv(env, SPR_PIR, "PIR",
5442 SPR_NOACCESS, SPR_NOACCESS,
5443 &spr_read_generic, SPR_NOACCESS,
5444 &spr_read_generic, NULL,
5445 0x00000000);
5446 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_lpidr,
5450 0x00000000);
5451 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_core_write_generic32,
5460 0x00000000);
5461 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5472 SPR_NOACCESS, SPR_NOACCESS,
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 SPR_NOACCESS, SPR_NOACCESS,
5479 &spr_read_generic, &spr_write_generic,
5480 0x00000000);
5481 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 SPR_NOACCESS, SPR_NOACCESS,
5484 &spr_read_generic, &spr_write_generic,
5485 0x00000000);
5486 spr_register_hv(env, SPR_HDAR, "HDAR",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 SPR_NOACCESS, SPR_NOACCESS,
5489 &spr_read_generic, &spr_write_generic,
5490 0x00000000);
5491 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 SPR_NOACCESS, SPR_NOACCESS,
5494 &spr_read_generic, &spr_write_generic32,
5495 0x00000000);
5496 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 SPR_NOACCESS, SPR_NOACCESS,
5499 &spr_read_generic, &spr_core_write_generic,
5500 0x00000000);
5501 }
5502
register_rmor_sprs(CPUPPCState * env)5503 static void register_rmor_sprs(CPUPPCState *env)
5504 {
5505 spr_register_hv(env, SPR_RMOR, "RMOR",
5506 SPR_NOACCESS, SPR_NOACCESS,
5507 SPR_NOACCESS, SPR_NOACCESS,
5508 &spr_read_generic, &spr_write_generic,
5509 0x00000000);
5510 }
5511
register_power8_ids_sprs(CPUPPCState * env)5512 static void register_power8_ids_sprs(CPUPPCState *env)
5513 {
5514 /* Thread identification */
5515 spr_register(env, SPR_TIR, "TIR",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, SPR_NOACCESS,
5518 0x00000000);
5519 }
5520
register_book3s_purr_sprs(CPUPPCState * env)5521 static void register_book3s_purr_sprs(CPUPPCState *env)
5522 {
5523 #if !defined(CONFIG_USER_ONLY)
5524 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5525 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5526 &spr_read_purr, SPR_NOACCESS,
5527 &spr_read_purr, SPR_NOACCESS,
5528 &spr_read_purr, &spr_write_purr,
5529 KVM_REG_PPC_PURR, 0x00000000);
5530 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5531 &spr_read_purr, SPR_NOACCESS,
5532 &spr_read_purr, SPR_NOACCESS,
5533 &spr_read_purr, &spr_write_purr,
5534 KVM_REG_PPC_SPURR, 0x00000000);
5535 #endif
5536 }
5537
register_power6_dbg_sprs(CPUPPCState * env)5538 static void register_power6_dbg_sprs(CPUPPCState *env)
5539 {
5540 #if !defined(CONFIG_USER_ONLY)
5541 spr_register(env, SPR_CFAR, "CFAR",
5542 SPR_NOACCESS, SPR_NOACCESS,
5543 &spr_read_cfar, &spr_write_cfar,
5544 0x00000000);
5545 #endif
5546 }
5547
register_power5p_common_sprs(CPUPPCState * env)5548 static void register_power5p_common_sprs(CPUPPCState *env)
5549 {
5550 spr_register_kvm(env, SPR_PPR, "PPR",
5551 &spr_read_generic, &spr_write_generic,
5552 &spr_read_generic, &spr_write_generic,
5553 KVM_REG_PPC_PPR, 0x00000000);
5554 }
5555
register_power6_common_sprs(CPUPPCState * env)5556 static void register_power6_common_sprs(CPUPPCState *env)
5557 {
5558 #if !defined(CONFIG_USER_ONLY)
5559 spr_register_kvm(env, SPR_DSCR, "DSCR",
5560 SPR_NOACCESS, SPR_NOACCESS,
5561 &spr_read_generic, &spr_write_generic,
5562 KVM_REG_PPC_DSCR, 0x00000000);
5563 #endif
5564 /*
5565 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5566 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5567 */
5568 spr_register_hv(env, SPR_PCR, "PCR",
5569 SPR_NOACCESS, SPR_NOACCESS,
5570 SPR_NOACCESS, SPR_NOACCESS,
5571 &spr_read_generic, &spr_write_pcr,
5572 0x00000000);
5573 }
5574
register_HEIR32_spr(CPUPPCState * env)5575 static void register_HEIR32_spr(CPUPPCState *env)
5576 {
5577 spr_register_hv(env, SPR_HEIR, "HEIR",
5578 SPR_NOACCESS, SPR_NOACCESS,
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic32,
5581 0x00000000);
5582 }
5583
register_HEIR64_spr(CPUPPCState * env)5584 static void register_HEIR64_spr(CPUPPCState *env)
5585 {
5586 spr_register_hv(env, SPR_HEIR, "HEIR",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic,
5590 0x00000000);
5591 }
5592
register_power7_common_sprs(CPUPPCState * env)5593 static void register_power7_common_sprs(CPUPPCState *env)
5594 {
5595 spr_register(env, SPR_PPR32, "PPR32",
5596 &spr_read_ppr32, &spr_write_ppr32,
5597 &spr_read_ppr32, &spr_write_ppr32,
5598 0x00000000);
5599 }
5600
register_power8_tce_address_control_sprs(CPUPPCState * env)5601 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5602 {
5603 spr_register_kvm(env, SPR_TAR, "TAR",
5604 &spr_read_tar, &spr_write_tar,
5605 &spr_read_generic, &spr_write_generic,
5606 KVM_REG_PPC_TAR, 0x00000000);
5607 }
5608
register_power8_tm_sprs(CPUPPCState * env)5609 static void register_power8_tm_sprs(CPUPPCState *env)
5610 {
5611 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5612 &spr_read_tm, &spr_write_tm,
5613 &spr_read_tm, &spr_write_tm,
5614 KVM_REG_PPC_TFHAR, 0x00000000);
5615 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5616 &spr_read_tm, &spr_write_tm,
5617 &spr_read_tm, &spr_write_tm,
5618 KVM_REG_PPC_TFIAR, 0x00000000);
5619 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5620 &spr_read_tm, &spr_write_tm,
5621 &spr_read_tm, &spr_write_tm,
5622 KVM_REG_PPC_TEXASR, 0x00000000);
5623 spr_register(env, SPR_TEXASRU, "TEXASRU",
5624 &spr_read_tm_upper32, &spr_write_tm_upper32,
5625 &spr_read_tm_upper32, &spr_write_tm_upper32,
5626 0x00000000);
5627 }
5628
register_power8_ebb_sprs(CPUPPCState * env)5629 static void register_power8_ebb_sprs(CPUPPCState *env)
5630 {
5631 spr_register(env, SPR_BESCRS, "BESCRS",
5632 &spr_read_ebb, &spr_write_ebb,
5633 &spr_read_generic, &spr_write_generic,
5634 0x00000000);
5635 spr_register(env, SPR_BESCRSU, "BESCRSU",
5636 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5637 &spr_read_prev_upper32, &spr_write_prev_upper32,
5638 0x00000000);
5639 spr_register(env, SPR_BESCRR, "BESCRR",
5640 &spr_read_ebb, &spr_write_ebb,
5641 &spr_read_generic, &spr_write_generic,
5642 0x00000000);
5643 spr_register(env, SPR_BESCRRU, "BESCRRU",
5644 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5645 &spr_read_prev_upper32, &spr_write_prev_upper32,
5646 0x00000000);
5647 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5648 &spr_read_ebb, &spr_write_ebb,
5649 &spr_read_generic, &spr_write_generic,
5650 KVM_REG_PPC_EBBHR, 0x00000000);
5651 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5652 &spr_read_ebb, &spr_write_ebb,
5653 &spr_read_generic, &spr_write_generic,
5654 KVM_REG_PPC_EBBRR, 0x00000000);
5655 spr_register_kvm(env, SPR_BESCR, "BESCR",
5656 &spr_read_ebb, &spr_write_ebb,
5657 &spr_read_generic, &spr_write_generic,
5658 KVM_REG_PPC_BESCR, 0x00000000);
5659 }
5660
5661 /* Virtual Time Base */
register_vtb_sprs(CPUPPCState * env)5662 static void register_vtb_sprs(CPUPPCState *env)
5663 {
5664 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5665 SPR_NOACCESS, SPR_NOACCESS,
5666 &spr_read_vtb, SPR_NOACCESS,
5667 &spr_read_vtb, &spr_write_vtb,
5668 KVM_REG_PPC_VTB, 0x00000000);
5669 }
5670
register_power8_fscr_sprs(CPUPPCState * env)5671 static void register_power8_fscr_sprs(CPUPPCState *env)
5672 {
5673 #if defined(CONFIG_USER_ONLY)
5674 target_ulong initval = 1ULL << FSCR_TAR;
5675 #else
5676 target_ulong initval = 0;
5677 #endif
5678 spr_register_kvm(env, SPR_FSCR, "FSCR",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 KVM_REG_PPC_FSCR, initval);
5682 }
5683
register_power8_pspb_sprs(CPUPPCState * env)5684 static void register_power8_pspb_sprs(CPUPPCState *env)
5685 {
5686 spr_register_kvm(env, SPR_PSPB, "PSPB",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic32,
5689 KVM_REG_PPC_PSPB, 0);
5690 }
5691
register_power8_dpdes_sprs(CPUPPCState * env)5692 static void register_power8_dpdes_sprs(CPUPPCState *env)
5693 {
5694 #if !defined(CONFIG_USER_ONLY)
5695 /* Directed Privileged Door-bell Exception State, used for IPI */
5696 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5697 SPR_NOACCESS, SPR_NOACCESS,
5698 &spr_read_dpdes, SPR_NOACCESS,
5699 &spr_read_dpdes, &spr_write_dpdes,
5700 KVM_REG_PPC_DPDES, 0x00000000);
5701 #endif
5702 }
5703
register_power8_ic_sprs(CPUPPCState * env)5704 static void register_power8_ic_sprs(CPUPPCState *env)
5705 {
5706 #if !defined(CONFIG_USER_ONLY)
5707 spr_register_hv(env, SPR_IC, "IC",
5708 SPR_NOACCESS, SPR_NOACCESS,
5709 &spr_read_generic, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0);
5712 #endif
5713 }
5714
5715 /* SPRs specific to IBM POWER CPUs */
register_power_common_book4_sprs(CPUPPCState * env)5716 static void register_power_common_book4_sprs(CPUPPCState *env)
5717 {
5718 #if !defined(CONFIG_USER_ONLY)
5719 spr_register_hv(env, SPR_HID0, "HID0",
5720 SPR_NOACCESS, SPR_NOACCESS,
5721 SPR_NOACCESS, SPR_NOACCESS,
5722 &spr_read_generic, &spr_core_write_generic,
5723 0x00000000);
5724 spr_register_hv(env, SPR_TSCR, "TSCR",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_core_write_generic32,
5728 0x00000000);
5729 spr_register_hv(env, SPR_HMER, "HMER",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_hmer,
5733 0x00000000);
5734 spr_register_hv(env, SPR_HMEER, "HMEER",
5735 SPR_NOACCESS, SPR_NOACCESS,
5736 SPR_NOACCESS, SPR_NOACCESS,
5737 &spr_read_generic, &spr_core_write_generic,
5738 0x00000000);
5739 spr_register_hv(env, SPR_TFMR, "TFMR",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 SPR_NOACCESS, SPR_NOACCESS,
5742 &spr_read_tfmr, &spr_write_tfmr,
5743 0x00000000);
5744 spr_register_hv(env, SPR_TRIG1, "TRIG1",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_access_nop, &spr_write_generic,
5747 &spr_access_nop, &spr_write_generic,
5748 0x00000000);
5749 spr_register_hv(env, SPR_TRIG2, "TRIG2",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_access_nop, &spr_write_generic,
5752 &spr_access_nop, &spr_write_generic,
5753 0x00000000);
5754 spr_register_hv(env, SPR_LDBAR, "LDBAR",
5755 SPR_NOACCESS, SPR_NOACCESS,
5756 SPR_NOACCESS, SPR_NOACCESS,
5757 &spr_read_generic, &spr_core_lpar_write_generic,
5758 0x00000000);
5759 spr_register_hv(env, SPR_POWER_TTR, "TTR",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 SPR_NOACCESS, SPR_NOACCESS,
5762 &spr_read_generic, &spr_core_write_generic,
5763 0x00000000);
5764 #endif
5765 }
5766
register_power9_book4_sprs(CPUPPCState * env)5767 static void register_power9_book4_sprs(CPUPPCState *env)
5768 {
5769 /* Add a number of P9 book4 registers */
5770 register_power_common_book4_sprs(env);
5771 #if !defined(CONFIG_USER_ONLY)
5772 spr_register_kvm(env, SPR_WORT, "WORT",
5773 SPR_NOACCESS, SPR_NOACCESS,
5774 &spr_read_generic, &spr_write_generic,
5775 KVM_REG_PPC_WORT, 0);
5776 #endif
5777 }
5778
register_power8_book4_sprs(CPUPPCState * env)5779 static void register_power8_book4_sprs(CPUPPCState *env)
5780 {
5781 /* Add a number of P8 book4 registers */
5782 register_power_common_book4_sprs(env);
5783 #if !defined(CONFIG_USER_ONLY)
5784 spr_register_kvm(env, SPR_ACOP, "ACOP",
5785 SPR_NOACCESS, SPR_NOACCESS,
5786 &spr_read_generic, &spr_write_generic,
5787 KVM_REG_PPC_ACOP, 0);
5788 /* PID is only in BookE in ISA v2.07 */
5789 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5790 SPR_NOACCESS, SPR_NOACCESS,
5791 &spr_read_generic, &spr_write_pidr,
5792 KVM_REG_PPC_PID, 0);
5793 spr_register_kvm(env, SPR_WORT, "WORT",
5794 SPR_NOACCESS, SPR_NOACCESS,
5795 &spr_read_generic, &spr_write_generic,
5796 KVM_REG_PPC_WORT, 0);
5797 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
5798 spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 SPR_NOACCESS, SPR_NOACCESS,
5801 &spr_read_generic, &spr_write_sprc,
5802 0x00000000);
5803 spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
5804 SPR_NOACCESS, SPR_NOACCESS,
5805 SPR_NOACCESS, SPR_NOACCESS,
5806 &spr_read_sprd, &spr_write_sprd,
5807 0x00000000);
5808 #endif
5809 }
5810
register_power7_book4_sprs(CPUPPCState * env)5811 static void register_power7_book4_sprs(CPUPPCState *env)
5812 {
5813 /* Add a number of P7 book4 registers */
5814 #if !defined(CONFIG_USER_ONLY)
5815 register_power_common_book4_sprs(env);
5816 spr_register_kvm(env, SPR_ACOP, "ACOP",
5817 SPR_NOACCESS, SPR_NOACCESS,
5818 &spr_read_generic, &spr_write_generic,
5819 KVM_REG_PPC_ACOP, 0);
5820 /* PID is only in BookE in ISA v2.06 */
5821 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5822 SPR_NOACCESS, SPR_NOACCESS,
5823 &spr_read_generic, &spr_write_generic32,
5824 KVM_REG_PPC_PID, 0);
5825 #endif
5826 }
5827
register_power8_rpr_sprs(CPUPPCState * env)5828 static void register_power8_rpr_sprs(CPUPPCState *env)
5829 {
5830 #if !defined(CONFIG_USER_ONLY)
5831 spr_register_hv(env, SPR_RPR, "RPR",
5832 SPR_NOACCESS, SPR_NOACCESS,
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_core_write_generic,
5835 0x00000103070F1F3F);
5836 #endif
5837 }
5838
register_power9_mmu_sprs(CPUPPCState * env)5839 static void register_power9_mmu_sprs(CPUPPCState *env)
5840 {
5841 #if !defined(CONFIG_USER_ONLY)
5842 /* Partition Table Control */
5843 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5844 SPR_NOACCESS, SPR_NOACCESS,
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_ptcr,
5847 KVM_REG_PPC_PTCR, 0x00000000);
5848 /* Address Segment Descriptor Register */
5849 spr_register_hv(env, SPR_ASDR, "ASDR",
5850 SPR_NOACCESS, SPR_NOACCESS,
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x0000000000000000);
5854 /* PID is part of the BookS ISA from v3.0 */
5855 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5856 SPR_NOACCESS, SPR_NOACCESS,
5857 &spr_read_generic, &spr_write_pidr,
5858 KVM_REG_PPC_PID, 0);
5859 #endif
5860 }
5861
register_power10_hash_sprs(CPUPPCState * env)5862 static void register_power10_hash_sprs(CPUPPCState *env)
5863 {
5864 /*
5865 * it's the OS responsibility to generate a random value for the registers
5866 * in each process' context. So, initialize it with 0 here.
5867 */
5868 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5869 #if defined(CONFIG_USER_ONLY)
5870 /* in linux-user, setup the hash register with a random value */
5871 GRand *rand = g_rand_new();
5872 hashkeyr_initial_value =
5873 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5874 hashpkeyr_initial_value =
5875 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5876 g_rand_free(rand);
5877 #endif
5878 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR",
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 &spr_read_generic, &spr_write_generic,
5881 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value);
5882 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_generic,
5886 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value);
5887 }
5888
register_power10_dexcr_sprs(CPUPPCState * env)5889 static void register_power10_dexcr_sprs(CPUPPCState *env)
5890 {
5891 spr_register_kvm(env, SPR_DEXCR, "DEXCR",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR,
5894 0);
5895
5896 spr_register(env, SPR_UDEXCR, "UDEXCR",
5897 &spr_read_dexcr_ureg, SPR_NOACCESS,
5898 &spr_read_dexcr_ureg, SPR_NOACCESS,
5899 0);
5900
5901 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0);
5906
5907 spr_register(env, SPR_UHDEXCR, "UHDEXCR",
5908 &spr_read_dexcr_ureg, SPR_NOACCESS,
5909 &spr_read_dexcr_ureg, SPR_NOACCESS,
5910 0);
5911 }
5912
5913 /*
5914 * Initialize PMU counter overflow timers for Power8 and
5915 * newer Power chips when using TCG.
5916 */
init_tcg_pmu_power8(CPUPPCState * env)5917 static void init_tcg_pmu_power8(CPUPPCState *env)
5918 {
5919 /* Init PMU overflow timers */
5920 if (tcg_enabled()) {
5921 cpu_ppc_pmu_init(env);
5922 }
5923 }
5924
init_proc_book3s_common(CPUPPCState * env)5925 static void init_proc_book3s_common(CPUPPCState *env)
5926 {
5927 register_non_embedded_sprs(env);
5928 register_book3s_altivec_sprs(env);
5929 register_book3s_pmu_sup_sprs(env);
5930 register_book3s_pmu_user_sprs(env);
5931 register_book3s_ctrl_sprs(env);
5932 /*
5933 * Can't find information on what this should be on reset. This
5934 * value is the one used by 74xx processors.
5935 */
5936 vscr_init(env, 0x00010000);
5937
5938 spr_register(env, SPR_USPRG3, "USPRG3",
5939 &spr_read_ureg, SPR_NOACCESS,
5940 &spr_read_ureg, SPR_NOACCESS,
5941 0x00000000);
5942 }
5943
init_proc_970(CPUPPCState * env)5944 static void init_proc_970(CPUPPCState *env)
5945 {
5946 /* Common Registers */
5947 init_proc_book3s_common(env);
5948 register_sdr1_sprs(env);
5949 register_book3s_dbg_sprs(env);
5950
5951 /* 970 Specific Registers */
5952 register_970_hid_sprs(env);
5953 register_970_hior_sprs(env);
5954 register_low_BATs(env);
5955 register_970_pmu_sup_sprs(env);
5956 register_970_pmu_user_sprs(env);
5957 register_970_lpar_sprs(env);
5958 register_970_dbg_sprs(env);
5959
5960 /* env variables */
5961 env->dcache_line_size = 128;
5962 env->icache_line_size = 128;
5963
5964 /* Allocate hardware IRQ controller */
5965 init_excp_970(env);
5966 ppc970_irq_init(env_archcpu(env));
5967 }
5968
5969 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
5970 {
5971 DeviceClass *dc = DEVICE_CLASS(oc);
5972 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5973
5974 dc->desc = "PowerPC 970";
5975 pcc->init_proc = init_proc_970;
5976 pcc->check_pow = check_pow_970;
5977 pcc->check_attn = check_attn_hid0;
5978 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5979 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5980 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5981 PPC_FLOAT_STFIWX |
5982 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5983 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5984 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5985 PPC_64B | PPC_ALTIVEC |
5986 PPC_SEGMENT_64B | PPC_SLBI;
5987 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
5988 pcc->msr_mask = (1ull << MSR_SF) |
5989 (1ull << MSR_VR) |
5990 (1ull << MSR_POW) |
5991 (1ull << MSR_EE) |
5992 (1ull << MSR_PR) |
5993 (1ull << MSR_FP) |
5994 (1ull << MSR_ME) |
5995 (1ull << MSR_FE0) |
5996 (1ull << MSR_SE) |
5997 (1ull << MSR_DE) |
5998 (1ull << MSR_FE1) |
5999 (1ull << MSR_IR) |
6000 (1ull << MSR_DR) |
6001 (1ull << MSR_PMM) |
6002 (1ull << MSR_RI);
6003 pcc->mmu_model = POWERPC_MMU_64B;
6004 #if !defined(CONFIG_USER_ONLY)
6005 pcc->hash64_opts = &ppc_hash64_opts_basic;
6006 #endif
6007 pcc->excp_model = POWERPC_EXCP_970;
6008 pcc->bus_model = PPC_FLAGS_INPUT_970;
6009 pcc->bfd_mach = bfd_mach_ppc64;
6010 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6011 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6012 POWERPC_FLAG_BUS_CLK;
6013 pcc->l1_dcache_size = 0x8000;
6014 pcc->l1_icache_size = 0x10000;
6015 }
6016
init_proc_power5plus(CPUPPCState * env)6017 static void init_proc_power5plus(CPUPPCState *env)
6018 {
6019 /* Common Registers */
6020 init_proc_book3s_common(env);
6021 register_sdr1_sprs(env);
6022 register_book3s_dbg_sprs(env);
6023
6024 /* POWER5+ Specific Registers */
6025 register_970_hid_sprs(env);
6026 register_970_hior_sprs(env);
6027 register_low_BATs(env);
6028 register_970_pmu_sup_sprs(env);
6029 register_970_pmu_user_sprs(env);
6030 register_power5p_common_sprs(env);
6031 register_power5p_lpar_sprs(env);
6032 register_power5p_ear_sprs(env);
6033 register_power5p_tb_sprs(env);
6034
6035 /* env variables */
6036 env->dcache_line_size = 128;
6037 env->icache_line_size = 128;
6038
6039 /* Allocate hardware IRQ controller */
6040 init_excp_970(env);
6041 ppc970_irq_init(env_archcpu(env));
6042 }
6043
POWERPC_FAMILY(POWER5P)6044 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6045 {
6046 DeviceClass *dc = DEVICE_CLASS(oc);
6047 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6048
6049 dc->fw_name = "PowerPC,POWER5";
6050 dc->desc = "POWER5+";
6051 pcc->init_proc = init_proc_power5plus;
6052 pcc->check_pow = check_pow_970;
6053 pcc->check_attn = check_attn_hid0;
6054 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6055 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6056 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6057 PPC_FLOAT_STFIWX |
6058 PPC_FLOAT_EXT |
6059 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6060 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6061 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6062 PPC_64B |
6063 PPC_POPCNTB |
6064 PPC_SEGMENT_64B | PPC_SLBI;
6065 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6066 pcc->msr_mask = (1ull << MSR_SF) |
6067 (1ull << MSR_VR) |
6068 (1ull << MSR_POW) |
6069 (1ull << MSR_EE) |
6070 (1ull << MSR_PR) |
6071 (1ull << MSR_FP) |
6072 (1ull << MSR_ME) |
6073 (1ull << MSR_FE0) |
6074 (1ull << MSR_SE) |
6075 (1ull << MSR_DE) |
6076 (1ull << MSR_FE1) |
6077 (1ull << MSR_IR) |
6078 (1ull << MSR_DR) |
6079 (1ull << MSR_PMM) |
6080 (1ull << MSR_RI);
6081 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6082 LPCR_RMI | LPCR_HDICE;
6083 pcc->mmu_model = POWERPC_MMU_2_03;
6084 #if !defined(CONFIG_USER_ONLY)
6085 pcc->hash64_opts = &ppc_hash64_opts_basic;
6086 pcc->lrg_decr_bits = 32;
6087 #endif
6088 pcc->excp_model = POWERPC_EXCP_970;
6089 pcc->bus_model = PPC_FLAGS_INPUT_970;
6090 pcc->bfd_mach = bfd_mach_ppc64;
6091 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6092 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6093 POWERPC_FLAG_BUS_CLK;
6094 pcc->l1_dcache_size = 0x8000;
6095 pcc->l1_icache_size = 0x10000;
6096 }
6097
init_proc_POWER7(CPUPPCState * env)6098 static void init_proc_POWER7(CPUPPCState *env)
6099 {
6100 /* Common Registers */
6101 init_proc_book3s_common(env);
6102 register_sdr1_sprs(env);
6103 register_book3s_dbg_sprs(env);
6104
6105 /* POWER7 Specific Registers */
6106 register_book3s_ids_sprs(env);
6107 register_rmor_sprs(env);
6108 register_amr_sprs(env);
6109 register_book3s_purr_sprs(env);
6110 register_power5p_common_sprs(env);
6111 register_power5p_lpar_sprs(env);
6112 register_power5p_ear_sprs(env);
6113 register_power5p_tb_sprs(env);
6114 register_power6_common_sprs(env);
6115 register_HEIR32_spr(env);
6116 register_power6_dbg_sprs(env);
6117 register_power7_common_sprs(env);
6118 register_power7_book4_sprs(env);
6119
6120 /* env variables */
6121 env->dcache_line_size = 128;
6122 env->icache_line_size = 128;
6123
6124 /* Allocate hardware IRQ controller */
6125 init_excp_POWER7(env);
6126 ppcPOWER7_irq_init(env_archcpu(env));
6127 }
6128
ppc_pvr_match_power7(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6129 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6130 {
6131 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6132 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6133
6134 if (!best) {
6135 if (base == CPU_POWERPC_POWER7_BASE) {
6136 return true;
6137 }
6138 if (base == CPU_POWERPC_POWER7P_BASE) {
6139 return true;
6140 }
6141 }
6142
6143 if (base != pcc_base) {
6144 return false;
6145 }
6146
6147 return true;
6148 }
6149
POWERPC_FAMILY(POWER7)6150 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6151 {
6152 DeviceClass *dc = DEVICE_CLASS(oc);
6153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6154
6155 dc->fw_name = "PowerPC,POWER7";
6156 dc->desc = "POWER7";
6157 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS;
6158 pcc->pvr_match = ppc_pvr_match_power7;
6159 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6160 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6161 pcc->init_proc = init_proc_POWER7;
6162 pcc->check_pow = check_pow_nocheck;
6163 pcc->check_attn = check_attn_hid0;
6164 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6165 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6166 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6167 PPC_FLOAT_FRSQRTES |
6168 PPC_FLOAT_STFIWX |
6169 PPC_FLOAT_EXT |
6170 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6171 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6172 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6173 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6174 PPC_SEGMENT_64B | PPC_SLBI |
6175 PPC_POPCNTB | PPC_POPCNTWD |
6176 PPC_CILDST;
6177 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6178 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6179 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6180 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6181 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6182 pcc->msr_mask = (1ull << MSR_SF) |
6183 (1ull << MSR_VR) |
6184 (1ull << MSR_VSX) |
6185 (1ull << MSR_EE) |
6186 (1ull << MSR_PR) |
6187 (1ull << MSR_FP) |
6188 (1ull << MSR_ME) |
6189 (1ull << MSR_FE0) |
6190 (1ull << MSR_SE) |
6191 (1ull << MSR_DE) |
6192 (1ull << MSR_FE1) |
6193 (1ull << MSR_IR) |
6194 (1ull << MSR_DR) |
6195 (1ull << MSR_PMM) |
6196 (1ull << MSR_RI) |
6197 (1ull << MSR_LE);
6198 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6199 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6200 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6201 LPCR_MER | LPCR_TC |
6202 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6203 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6204 pcc->mmu_model = POWERPC_MMU_2_06;
6205 #if !defined(CONFIG_USER_ONLY)
6206 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6207 pcc->lrg_decr_bits = 32;
6208 #endif
6209 pcc->excp_model = POWERPC_EXCP_POWER7;
6210 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6211 pcc->bfd_mach = bfd_mach_ppc64;
6212 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6213 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6214 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6215 POWERPC_FLAG_VSX;
6216 pcc->l1_dcache_size = 0x8000;
6217 pcc->l1_icache_size = 0x8000;
6218 }
6219
bhrb_init_state(CPUPPCState * env,target_long num_entries_log2)6220 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2)
6221 {
6222 if (env->flags & POWERPC_FLAG_BHRB) {
6223 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) {
6224 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2;
6225 }
6226 env->bhrb_num_entries = 1 << num_entries_log2;
6227 env->bhrb_base = (intptr_t)&env->bhrb[0];
6228 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1;
6229 }
6230 }
6231
bhrb_reset_state(CPUPPCState * env)6232 static void bhrb_reset_state(CPUPPCState *env)
6233 {
6234 if (env->flags & POWERPC_FLAG_BHRB) {
6235 env->bhrb_offset = 0;
6236 env->bhrb_filter = 0;
6237 memset(env->bhrb, 0, sizeof(env->bhrb));
6238 }
6239 }
6240
6241 #define POWER8_BHRB_ENTRIES_LOG2 5
init_proc_POWER8(CPUPPCState * env)6242 static void init_proc_POWER8(CPUPPCState *env)
6243 {
6244 /* Common Registers */
6245 init_proc_book3s_common(env);
6246 register_sdr1_sprs(env);
6247 register_book3s_207_dbg_sprs(env);
6248
6249 /* Common TCG PMU */
6250 init_tcg_pmu_power8(env);
6251
6252 /* POWER8 Specific Registers */
6253 register_book3s_ids_sprs(env);
6254 register_rmor_sprs(env);
6255 register_amr_sprs(env);
6256 register_iamr_sprs(env);
6257 register_book3s_purr_sprs(env);
6258 register_power5p_common_sprs(env);
6259 register_power5p_lpar_sprs(env);
6260 register_power5p_ear_sprs(env);
6261 register_power5p_tb_sprs(env);
6262 register_power6_common_sprs(env);
6263 register_HEIR32_spr(env);
6264 register_power6_dbg_sprs(env);
6265 register_power7_common_sprs(env);
6266 register_power8_tce_address_control_sprs(env);
6267 register_power8_ids_sprs(env);
6268 register_power8_ebb_sprs(env);
6269 register_power8_fscr_sprs(env);
6270 register_power8_pmu_sup_sprs(env);
6271 register_power8_pmu_user_sprs(env);
6272 register_power8_tm_sprs(env);
6273 register_power8_pspb_sprs(env);
6274 register_power8_dpdes_sprs(env);
6275 register_vtb_sprs(env);
6276 register_power8_ic_sprs(env);
6277 register_power8_book4_sprs(env);
6278 register_power8_rpr_sprs(env);
6279
6280 /* env variables */
6281 env->dcache_line_size = 128;
6282 env->icache_line_size = 128;
6283
6284 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2);
6285
6286 /* Allocate hardware IRQ controller */
6287 init_excp_POWER8(env);
6288 ppcPOWER7_irq_init(env_archcpu(env));
6289 }
6290
ppc_pvr_match_power8(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6291 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6292 {
6293 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6294 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6295
6296 if (!best) {
6297 if (base == CPU_POWERPC_POWER8_BASE) {
6298 return true;
6299 }
6300 if (base == CPU_POWERPC_POWER8E_BASE) {
6301 return true;
6302 }
6303 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6304 return true;
6305 }
6306 }
6307 if (base != pcc_base) {
6308 return false;
6309 }
6310
6311 return true;
6312 }
6313
POWERPC_FAMILY(POWER8)6314 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6315 {
6316 DeviceClass *dc = DEVICE_CLASS(oc);
6317 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6318
6319 dc->fw_name = "PowerPC,POWER8";
6320 dc->desc = "POWER8";
6321 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07;
6322 pcc->pvr_match = ppc_pvr_match_power8;
6323 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6324 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6325 pcc->init_proc = init_proc_POWER8;
6326 pcc->check_pow = check_pow_nocheck;
6327 pcc->check_attn = check_attn_hid0;
6328 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6329 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6330 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6331 PPC_FLOAT_FRSQRTES |
6332 PPC_FLOAT_STFIWX |
6333 PPC_FLOAT_EXT |
6334 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6335 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6336 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6337 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6338 PPC_SEGMENT_64B | PPC_SLBI |
6339 PPC_POPCNTB | PPC_POPCNTWD |
6340 PPC_CILDST;
6341 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6342 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6343 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6344 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6345 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6346 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6347 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6348 PPC2_BCDA_ISA206;
6349 pcc->msr_mask = (1ull << MSR_SF) |
6350 (1ull << MSR_HV) |
6351 (1ull << MSR_TM) |
6352 (1ull << MSR_VR) |
6353 (1ull << MSR_VSX) |
6354 (1ull << MSR_EE) |
6355 (1ull << MSR_PR) |
6356 (1ull << MSR_FP) |
6357 (1ull << MSR_ME) |
6358 (1ull << MSR_FE0) |
6359 (1ull << MSR_SE) |
6360 (1ull << MSR_DE) |
6361 (1ull << MSR_FE1) |
6362 (1ull << MSR_IR) |
6363 (1ull << MSR_DR) |
6364 (1ull << MSR_PMM) |
6365 (1ull << MSR_RI) |
6366 (1ull << MSR_TS0) |
6367 (1ull << MSR_TS1) |
6368 (1ull << MSR_LE);
6369 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6370 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6371 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6372 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6373 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6374 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6375 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6376 pcc->mmu_model = POWERPC_MMU_2_07;
6377 #if !defined(CONFIG_USER_ONLY)
6378 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6379 pcc->lrg_decr_bits = 32;
6380 pcc->n_host_threads = 8;
6381 #endif
6382 pcc->excp_model = POWERPC_EXCP_POWER8;
6383 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6384 pcc->bfd_mach = bfd_mach_ppc64;
6385 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6386 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6387 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6388 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6389 pcc->l1_dcache_size = 0x8000;
6390 pcc->l1_icache_size = 0x8000;
6391 }
6392
6393 #ifndef CONFIG_USER_ONLY
6394 /*
6395 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6396 * Encoded as array of int_32s in the form:
6397 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6398 * x -> AP encoding
6399 * y -> radix mode supported page size (encoded as a shift)
6400 */
6401 static struct ppc_radix_page_info POWER9_radix_page_info = {
6402 .count = 4,
6403 .entries = {
6404 0x0000000c, /* 4K - enc: 0x0 */
6405 0xa0000010, /* 64K - enc: 0x5 */
6406 0x20000015, /* 2M - enc: 0x1 */
6407 0x4000001e /* 1G - enc: 0x2 */
6408 }
6409 };
6410 #endif /* CONFIG_USER_ONLY */
6411
6412 #define POWER9_BHRB_ENTRIES_LOG2 5
register_power9_common_sprs(CPUPPCState * env)6413 static void register_power9_common_sprs(CPUPPCState *env)
6414 {
6415 /* Common Registers */
6416 init_proc_book3s_common(env);
6417 register_book3s_207_dbg_sprs(env);
6418
6419 /* Common TCG PMU */
6420 init_tcg_pmu_power8(env);
6421
6422 /* POWER8 Specific Registers */
6423 register_book3s_ids_sprs(env);
6424 register_amr_sprs(env);
6425 register_iamr_sprs(env);
6426 register_book3s_purr_sprs(env);
6427 register_power5p_common_sprs(env);
6428 register_power5p_lpar_sprs(env);
6429 register_power5p_ear_sprs(env);
6430 register_power5p_tb_sprs(env);
6431 register_power6_common_sprs(env);
6432 register_power6_dbg_sprs(env);
6433 register_power7_common_sprs(env);
6434 register_power8_tce_address_control_sprs(env);
6435 register_power8_ids_sprs(env);
6436 register_power8_ebb_sprs(env);
6437 register_power8_fscr_sprs(env);
6438 register_power8_pmu_sup_sprs(env);
6439 register_power8_pmu_user_sprs(env);
6440 register_power8_tm_sprs(env);
6441 register_power8_pspb_sprs(env);
6442 register_power8_dpdes_sprs(env);
6443 register_vtb_sprs(env);
6444 register_power8_ic_sprs(env);
6445 register_power9_book4_sprs(env);
6446 register_power8_rpr_sprs(env);
6447 register_power9_mmu_sprs(env);
6448
6449 /* FIXME: Filter fields properly based on privilege level */
6450 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6451 spr_read_generic, spr_write_generic,
6452 KVM_REG_PPC_PSSCR, 0);
6453
6454 }
6455
init_proc_POWER9(CPUPPCState * env)6456 static void init_proc_POWER9(CPUPPCState *env)
6457 {
6458 register_power9_common_sprs(env);
6459 register_HEIR32_spr(env);
6460 /* POWER9 Specific registers */
6461 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6462 spr_read_generic, spr_write_generic,
6463 KVM_REG_PPC_TIDR, 0);
6464 /* env variables */
6465 env->dcache_line_size = 128;
6466 env->icache_line_size = 128;
6467
6468 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2);
6469
6470 /* Allocate hardware IRQ controller */
6471 init_excp_POWER9(env);
6472 ppcPOWER9_irq_init(env_archcpu(env));
6473 }
6474
ppc_pvr_match_power9(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6475 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6476 {
6477 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6478 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6479
6480 if (!best) {
6481 if (base == CPU_POWERPC_POWER9_BASE) {
6482 return true;
6483 }
6484 }
6485
6486 if (base != pcc_base) {
6487 return false;
6488 }
6489
6490 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) {
6491 /* Major DD version does not match */
6492 return false;
6493 }
6494
6495 if ((pvr & 0x0f00) == 0x200) {
6496 if ((pvr & 0xf) < 2) {
6497 /* DD2.0, DD2.1 match power9_v2.0 */
6498 if ((pcc->pvr & 0xf) == 0) {
6499 return true;
6500 }
6501 } else {
6502 /* DD2.2, DD2.3 match power9_v2.2 */
6503 if ((pcc->pvr & 0xf) == 2) {
6504 return true;
6505 }
6506 }
6507 }
6508
6509 return false;
6510 }
6511
POWERPC_FAMILY(POWER9)6512 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6513 {
6514 DeviceClass *dc = DEVICE_CLASS(oc);
6515 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6516
6517 dc->fw_name = "PowerPC,POWER9";
6518 dc->desc = "POWER9";
6519 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00;
6520 pcc->pvr_match = ppc_pvr_match_power9;
6521 pcc->pcr_mask = PPC_PCR_MASK_POWER9;
6522 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9;
6523 pcc->init_proc = init_proc_POWER9;
6524 pcc->check_pow = check_pow_nocheck;
6525 pcc->check_attn = check_attn_hid0_power9;
6526 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9;
6527 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9;
6528 pcc->msr_mask = PPC_MSR_MASK_POWER9;
6529 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9;
6530 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6531 pcc->mmu_model = POWERPC_MMU_3_00;
6532 #if !defined(CONFIG_USER_ONLY)
6533 /* segment page size remain the same */
6534 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6535 pcc->radix_page_info = &POWER9_radix_page_info;
6536 pcc->lrg_decr_bits = 56;
6537 pcc->n_host_threads = 4;
6538 #endif
6539 pcc->excp_model = POWERPC_EXCP_POWER9;
6540 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6541 pcc->bfd_mach = bfd_mach_ppc64;
6542 pcc->flags = POWERPC_FLAGS_POWER9;
6543 pcc->l1_dcache_size = 0x8000;
6544 pcc->l1_icache_size = 0x8000;
6545 }
6546
6547 #ifndef CONFIG_USER_ONLY
6548 /*
6549 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6550 * Encoded as array of int_32s in the form:
6551 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6552 * x -> AP encoding
6553 * y -> radix mode supported page size (encoded as a shift)
6554 */
6555 static struct ppc_radix_page_info POWER10_radix_page_info = {
6556 .count = 4,
6557 .entries = {
6558 0x0000000c, /* 4K - enc: 0x0 */
6559 0xa0000010, /* 64K - enc: 0x5 */
6560 0x20000015, /* 2M - enc: 0x1 */
6561 0x4000001e /* 1G - enc: 0x2 */
6562 }
6563 };
6564 #endif /* !CONFIG_USER_ONLY */
6565
6566 #define POWER10_BHRB_ENTRIES_LOG2 5
init_proc_POWER10(CPUPPCState * env)6567 static void init_proc_POWER10(CPUPPCState *env)
6568 {
6569 register_power9_common_sprs(env);
6570 register_HEIR64_spr(env);
6571 register_power10_hash_sprs(env);
6572 register_power10_dexcr_sprs(env);
6573 register_power10_pmu_sup_sprs(env);
6574 register_power10_pmu_user_sprs(env);
6575 /* env variables */
6576 env->dcache_line_size = 128;
6577 env->icache_line_size = 128;
6578
6579 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2);
6580
6581 /* Allocate hardware IRQ controller */
6582 init_excp_POWER10(env);
6583 ppcPOWER9_irq_init(env_archcpu(env));
6584 }
6585
ppc_pvr_match_power10(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6586 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6587 {
6588 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6589 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6590
6591 if (!best) {
6592 if (base == CPU_POWERPC_POWER10_BASE) {
6593 return true;
6594 }
6595 }
6596
6597 if (base != pcc_base) {
6598 return false;
6599 }
6600
6601 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6602 /* Major DD version matches power10_v2.0 */
6603 return true;
6604 }
6605
6606 return false;
6607 }
6608
POWERPC_FAMILY(POWER10)6609 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6610 {
6611 DeviceClass *dc = DEVICE_CLASS(oc);
6612 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6613
6614 dc->fw_name = "PowerPC,POWER10";
6615 dc->desc = "POWER10";
6616 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10;
6617 pcc->pvr_match = ppc_pvr_match_power10;
6618 pcc->pcr_mask = PPC_PCR_MASK_POWER10;
6619 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10;
6620 pcc->init_proc = init_proc_POWER10;
6621 pcc->check_pow = check_pow_nocheck;
6622 pcc->check_attn = check_attn_hid0_power9;
6623 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10;
6624 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10;
6625 pcc->msr_mask = PPC_MSR_MASK_POWER10;
6626 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10;
6627
6628 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6629 pcc->mmu_model = POWERPC_MMU_3_00;
6630 #if !defined(CONFIG_USER_ONLY)
6631 /* segment page size remain the same */
6632 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6633 pcc->radix_page_info = &POWER10_radix_page_info;
6634 pcc->lrg_decr_bits = 56;
6635 #endif
6636 pcc->excp_model = POWERPC_EXCP_POWER10;
6637 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6638 pcc->bfd_mach = bfd_mach_ppc64;
6639 pcc->flags = POWERPC_FLAGS_POWER10;
6640 pcc->l1_dcache_size = 0x8000;
6641 pcc->l1_icache_size = 0x8000;
6642 }
6643
init_proc_POWER11(CPUPPCState * env)6644 static void init_proc_POWER11(CPUPPCState *env)
6645 {
6646 init_proc_POWER10(env);
6647 }
6648
ppc_pvr_match_power11(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6649 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6650 {
6651 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6652 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6653
6654 if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
6655 return true;
6656 }
6657
6658 if (base != pcc_base) {
6659 return false;
6660 }
6661
6662 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6663 return true;
6664 }
6665
6666 return false;
6667 }
6668
POWERPC_FAMILY(POWER11)6669 POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data)
6670 {
6671 DeviceClass *dc = DEVICE_CLASS(oc);
6672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6673
6674 dc->fw_name = "PowerPC,POWER11";
6675 dc->desc = "POWER11";
6676 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11;
6677 pcc->pvr_match = ppc_pvr_match_power11;
6678 pcc->pcr_mask = PPC_PCR_MASK_POWER11;
6679 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11;
6680 pcc->init_proc = init_proc_POWER11;
6681 pcc->check_pow = check_pow_nocheck;
6682 pcc->check_attn = check_attn_hid0_power9;
6683 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11;
6684 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11;
6685 pcc->msr_mask = PPC_MSR_MASK_POWER11;
6686 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11;
6687
6688 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6689 pcc->mmu_model = POWERPC_MMU_3_00;
6690 #if !defined(CONFIG_USER_ONLY)
6691 /* segment page size remain the same */
6692 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6693 pcc->radix_page_info = &POWER10_radix_page_info;
6694 pcc->lrg_decr_bits = 56;
6695 #endif
6696 pcc->excp_model = POWERPC_EXCP_POWER11;
6697 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6698 pcc->bfd_mach = bfd_mach_ppc64;
6699 pcc->flags = POWERPC_FLAGS_POWER11;
6700 pcc->l1_dcache_size = 0x8000;
6701 pcc->l1_icache_size = 0x8000;
6702 }
6703
6704 #if !defined(CONFIG_USER_ONLY)
cpu_ppc_set_vhyp(PowerPCCPU * cpu,PPCVirtualHypervisor * vhyp)6705 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6706 {
6707 CPUPPCState *env = &cpu->env;
6708
6709 cpu->vhyp = vhyp;
6710 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp);
6711
6712 /*
6713 * With a virtual hypervisor mode we never allow the CPU to go
6714 * hypervisor mode itself
6715 */
6716 env->msr_mask &= ~MSR_HVB;
6717 }
6718
cpu_ppc_set_1lpar(PowerPCCPU * cpu)6719 void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
6720 {
6721 CPUPPCState *env = &cpu->env;
6722
6723 /*
6724 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6725 * between threads. powernv be in either mode, and it mostly affects
6726 * supervisor visible registers and instructions.
6727 */
6728 if (env->flags & POWERPC_FLAG_SMT) {
6729 env->flags |= POWERPC_FLAG_SMT_1LPAR;
6730 }
6731 }
6732 #endif /* !defined(CONFIG_USER_ONLY) */
6733
6734 #endif /* defined(TARGET_PPC64) */
6735
6736 /*****************************************************************************/
6737 /* Generic CPU instantiation routine */
init_ppc_proc(PowerPCCPU * cpu)6738 static void init_ppc_proc(PowerPCCPU *cpu)
6739 {
6740 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6741 CPUPPCState *env = &cpu->env;
6742 #if !defined(CONFIG_USER_ONLY)
6743 int i;
6744
6745 /* Set all exception vectors to an invalid address */
6746 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6747 env->excp_vectors[i] = (target_ulong)(-1ULL);
6748 }
6749 env->ivor_mask = 0x00000000;
6750 env->ivpr_mask = 0x00000000;
6751 /* Default MMU definitions */
6752 env->nb_BATs = 0;
6753 env->nb_tlb = 0;
6754 env->nb_ways = 0;
6755 env->tlb_type = TLB_NONE;
6756 #endif
6757 /* Register SPR common to all PowerPC implementations */
6758 register_generic_sprs(cpu);
6759
6760 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6761 (*pcc->init_proc)(env);
6762
6763 /* MSR bits & flags consistency checks */
6764 if (env->msr_mask & (1 << 25)) {
6765 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6766 case POWERPC_FLAG_SPE:
6767 case POWERPC_FLAG_VRE:
6768 break;
6769 default:
6770 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6771 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6772 exit(1);
6773 }
6774 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6775 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6776 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6777 exit(1);
6778 }
6779 if (env->msr_mask & (1 << 17)) {
6780 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6781 case POWERPC_FLAG_TGPR:
6782 case POWERPC_FLAG_CE:
6783 break;
6784 default:
6785 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6786 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6787 exit(1);
6788 }
6789 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6790 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6791 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6792 exit(1);
6793 }
6794 if (env->msr_mask & (1 << 10)) {
6795 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6796 POWERPC_FLAG_UBLE)) {
6797 case POWERPC_FLAG_SE:
6798 case POWERPC_FLAG_DWE:
6799 case POWERPC_FLAG_UBLE:
6800 break;
6801 default:
6802 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6803 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6804 "POWERPC_FLAG_UBLE\n");
6805 exit(1);
6806 }
6807 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6808 POWERPC_FLAG_UBLE)) {
6809 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6810 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6811 "POWERPC_FLAG_UBLE\n");
6812 exit(1);
6813 }
6814 if (env->msr_mask & (1 << 9)) {
6815 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6816 case POWERPC_FLAG_BE:
6817 case POWERPC_FLAG_DE:
6818 break;
6819 default:
6820 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6821 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6822 exit(1);
6823 }
6824 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6825 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6826 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6827 exit(1);
6828 }
6829 if (env->msr_mask & (1 << 2)) {
6830 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6831 case POWERPC_FLAG_PX:
6832 case POWERPC_FLAG_PMM:
6833 break;
6834 default:
6835 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6836 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6837 exit(1);
6838 }
6839 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6840 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6841 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6842 exit(1);
6843 }
6844 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6845 fprintf(stderr, "PowerPC flags inconsistency\n"
6846 "Should define the time-base and decrementer clock source\n");
6847 exit(1);
6848 }
6849 /* Allocate TLBs buffer when needed */
6850 #if !defined(CONFIG_USER_ONLY)
6851 if (env->nb_tlb) {
6852 switch (env->tlb_type) {
6853 case TLB_6XX:
6854 /* 6xx has separate TLBs for instructions and data hence times 2 */
6855 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
6856 break;
6857 case TLB_EMB:
6858 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
6859 break;
6860 case TLB_MAS:
6861 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
6862 break;
6863 }
6864 /* Pre-compute some useful values */
6865 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6866 }
6867 #endif
6868 if (env->check_pow == NULL) {
6869 warn_report("no power management check handler registered."
6870 " Attempt QEMU to crash very soon !");
6871 }
6872
6873 if (env->check_attn == NULL) {
6874 warn_report("no attn check handler registered."
6875 " Attempt QEMU to crash very soon !");
6876 }
6877 }
6878
6879
ppc_cpu_realize(DeviceState * dev,Error ** errp)6880 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6881 {
6882 CPUState *cs = CPU(dev);
6883 PowerPCCPU *cpu = POWERPC_CPU(dev);
6884 CPUPPCState *env = &cpu->env;
6885 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6886 Error *local_err = NULL;
6887
6888 cpu_exec_realizefn(cs, &local_err);
6889 if (local_err != NULL) {
6890 error_propagate(errp, local_err);
6891 return;
6892 }
6893 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6894 cpu->vcpu_id = cs->cpu_index;
6895 }
6896
6897 if (tcg_enabled()) {
6898 if (ppc_fixup_cpu(cpu) != 0) {
6899 error_setg(errp, "Unable to emulate selected CPU with TCG");
6900 goto unrealize;
6901 }
6902 }
6903
6904 create_ppc_opcodes(cpu, &local_err);
6905 if (local_err != NULL) {
6906 error_propagate(errp, local_err);
6907 goto unrealize;
6908 }
6909 init_ppc_proc(cpu);
6910
6911 ppc_gdb_init(cs, pcc);
6912 qemu_init_vcpu(cs);
6913
6914 pcc->parent_realize(dev, errp);
6915
6916 if (!ppc_cpu_core_single_threaded(cs)) {
6917 env->flags |= POWERPC_FLAG_SMT;
6918 }
6919
6920 return;
6921
6922 unrealize:
6923 cpu_exec_unrealizefn(cs);
6924 }
6925
ppc_cpu_unrealize(DeviceState * dev)6926 static void ppc_cpu_unrealize(DeviceState *dev)
6927 {
6928 PowerPCCPU *cpu = POWERPC_CPU(dev);
6929 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6930
6931 pcc->parent_unrealize(dev);
6932
6933 cpu_remove_sync(CPU(cpu));
6934
6935 destroy_ppc_opcodes(cpu);
6936 }
6937
ppc_cpu_compare_class_pvr(gconstpointer a,gconstpointer b)6938 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6939 {
6940 ObjectClass *oc = (ObjectClass *)a;
6941 uint32_t pvr = *(uint32_t *)b;
6942 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6943
6944 /* -cpu host does a PVR lookup during construction */
6945 if (unlikely(strcmp(object_class_get_name(oc),
6946 TYPE_HOST_POWERPC_CPU) == 0)) {
6947 return -1;
6948 }
6949
6950 return pcc->pvr == pvr ? 0 : -1;
6951 }
6952
ppc_cpu_class_by_pvr(uint32_t pvr)6953 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6954 {
6955 GSList *list, *item;
6956 PowerPCCPUClass *pcc = NULL;
6957
6958 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6959 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6960 if (item != NULL) {
6961 pcc = POWERPC_CPU_CLASS(item->data);
6962 }
6963 g_slist_free(list);
6964
6965 return pcc;
6966 }
6967
ppc_cpu_compare_class_pvr_mask(gconstpointer a,gconstpointer b)6968 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6969 {
6970 ObjectClass *oc = (ObjectClass *)a;
6971 uint32_t pvr = *(uint32_t *)b;
6972 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6973
6974 /* -cpu host does a PVR lookup during construction */
6975 if (unlikely(strcmp(object_class_get_name(oc),
6976 TYPE_HOST_POWERPC_CPU) == 0)) {
6977 return -1;
6978 }
6979
6980 if (pcc->pvr_match(pcc, pvr, true)) {
6981 return 0;
6982 }
6983
6984 return -1;
6985 }
6986
ppc_cpu_class_by_pvr_mask(uint32_t pvr)6987 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6988 {
6989 GSList *list, *item;
6990 PowerPCCPUClass *pcc = NULL;
6991
6992 list = object_class_get_list(TYPE_POWERPC_CPU, true);
6993 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
6994 if (item != NULL) {
6995 pcc = POWERPC_CPU_CLASS(item->data);
6996 }
6997 g_slist_free(list);
6998
6999 return pcc;
7000 }
7001
ppc_cpu_lookup_alias(const char * alias)7002 static const char *ppc_cpu_lookup_alias(const char *alias)
7003 {
7004 int ai;
7005
7006 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7007 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7008 return ppc_cpu_aliases[ai].model;
7009 }
7010 }
7011
7012 return NULL;
7013 }
7014
ppc_cpu_class_by_name(const char * name)7015 ObjectClass *ppc_cpu_class_by_name(const char *name)
7016 {
7017 char *cpu_model, *typename;
7018 ObjectClass *oc;
7019 const char *p;
7020 unsigned long pvr;
7021
7022 /*
7023 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7024 * 0x prefix if present)
7025 */
7026 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7027 int len = p - name;
7028 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7029 if ((len == 8) && (*p == '\0')) {
7030 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7031 }
7032 }
7033
7034 /*
7035 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
7036 * do not have a "max" CPU with all possible emulated features enabled.
7037 * Return the default CPU type for the machine because that has greater
7038 * chance of being useful as the "max" CPU.
7039 */
7040 #if !defined(CONFIG_USER_ONLY)
7041 if (strcmp(name, "max") == 0) {
7042 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
7043 if (mc) {
7044 return object_class_by_name(mc->default_cpu_type);
7045 }
7046 }
7047 #endif
7048
7049 cpu_model = g_ascii_strdown(name, -1);
7050 p = ppc_cpu_lookup_alias(cpu_model);
7051 if (p) {
7052 g_free(cpu_model);
7053 cpu_model = g_strdup(p);
7054 }
7055
7056 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7057 oc = object_class_by_name(typename);
7058 g_free(typename);
7059 g_free(cpu_model);
7060
7061 return oc;
7062 }
7063
ppc_cpu_get_family_class(PowerPCCPUClass * pcc)7064 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7065 {
7066 ObjectClass *oc = OBJECT_CLASS(pcc);
7067
7068 while (oc && !object_class_is_abstract(oc)) {
7069 oc = object_class_get_parent(oc);
7070 }
7071 assert(oc);
7072
7073 return POWERPC_CPU_CLASS(oc);
7074 }
7075
7076 /* Sort by PVR, ordering special case "host" last. */
ppc_cpu_list_compare(gconstpointer a,gconstpointer b)7077 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7078 {
7079 ObjectClass *oc_a = (ObjectClass *)a;
7080 ObjectClass *oc_b = (ObjectClass *)b;
7081 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7082 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7083 const char *name_a = object_class_get_name(oc_a);
7084 const char *name_b = object_class_get_name(oc_b);
7085
7086 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7087 return 1;
7088 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7089 return -1;
7090 } else {
7091 /* Avoid an integer overflow during subtraction */
7092 if (pcc_a->pvr < pcc_b->pvr) {
7093 return -1;
7094 } else if (pcc_a->pvr > pcc_b->pvr) {
7095 return 1;
7096 } else {
7097 return 0;
7098 }
7099 }
7100 }
7101
ppc_cpu_list_entry(gpointer data,gpointer user_data)7102 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7103 {
7104 ObjectClass *oc = data;
7105 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7106 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7107 const char *typename = object_class_get_name(oc);
7108 char *name;
7109 int i;
7110
7111 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7112 return;
7113 }
7114
7115 name = cpu_model_from_type(typename);
7116 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr);
7117 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7118 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7119 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7120
7121 if (alias_oc != oc) {
7122 continue;
7123 }
7124 /*
7125 * If running with KVM, we might update the family alias later, so
7126 * avoid printing the wrong alias here and use "preferred" instead
7127 */
7128 if (strcmp(alias->alias, family->desc) == 0) {
7129 qemu_printf(" %-16s (alias for preferred %s CPU)\n",
7130 alias->alias, family->desc);
7131 } else {
7132 qemu_printf(" %-16s (alias for %s)\n",
7133 alias->alias, name);
7134 }
7135 }
7136 g_free(name);
7137 }
7138
ppc_cpu_list(void)7139 void ppc_cpu_list(void)
7140 {
7141 GSList *list;
7142
7143 qemu_printf("Available CPUs:\n");
7144 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7145 list = g_slist_sort(list, ppc_cpu_list_compare);
7146 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7147 g_slist_free(list);
7148
7149 #ifdef CONFIG_KVM
7150 qemu_printf("\n");
7151 qemu_printf(" %s\n", "host");
7152 #endif
7153 }
7154
ppc_cpu_set_pc(CPUState * cs,vaddr value)7155 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7156 {
7157 PowerPCCPU *cpu = POWERPC_CPU(cs);
7158
7159 cpu->env.nip = value;
7160 }
7161
ppc_cpu_get_pc(CPUState * cs)7162 static vaddr ppc_cpu_get_pc(CPUState *cs)
7163 {
7164 PowerPCCPU *cpu = POWERPC_CPU(cs);
7165
7166 return cpu->env.nip;
7167 }
7168
7169 #ifdef CONFIG_TCG
ppc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)7170 static void ppc_restore_state_to_opc(CPUState *cs,
7171 const TranslationBlock *tb,
7172 const uint64_t *data)
7173 {
7174 PowerPCCPU *cpu = POWERPC_CPU(cs);
7175
7176 cpu->env.nip = data[0];
7177 }
7178 #endif /* CONFIG_TCG */
7179
ppc_cpu_has_work(CPUState * cs)7180 static bool ppc_cpu_has_work(CPUState *cs)
7181 {
7182 return cs->interrupt_request & CPU_INTERRUPT_HARD;
7183 }
7184
ppc_cpu_mmu_index(CPUState * cs,bool ifetch)7185 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
7186 {
7187 return ppc_env_mmu_index(cpu_env(cs), ifetch);
7188 }
7189
ppc_cpu_reset_hold(Object * obj,ResetType type)7190 static void ppc_cpu_reset_hold(Object *obj, ResetType type)
7191 {
7192 CPUState *cs = CPU(obj);
7193 PowerPCCPU *cpu = POWERPC_CPU(cs);
7194 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
7195 CPUPPCState *env = &cpu->env;
7196 target_ulong msr;
7197 int i;
7198
7199 if (pcc->parent_phases.hold) {
7200 pcc->parent_phases.hold(obj, type);
7201 }
7202
7203 msr = (target_ulong)0;
7204 msr |= (target_ulong)MSR_HVB;
7205 msr |= (target_ulong)1 << MSR_EP;
7206 #if defined(DO_SINGLE_STEP) && 0
7207 /* Single step trace mode */
7208 msr |= (target_ulong)1 << MSR_SE;
7209 msr |= (target_ulong)1 << MSR_BE;
7210 #endif
7211 #if defined(CONFIG_USER_ONLY)
7212 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7213 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7214 msr |= (target_ulong)1 << MSR_FE1;
7215 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7216 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7217 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7218 msr |= (target_ulong)1 << MSR_PR;
7219 #if defined(TARGET_PPC64)
7220 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7221 #endif
7222 #if !TARGET_BIG_ENDIAN
7223 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7224 if (!((env->msr_mask >> MSR_LE) & 1)) {
7225 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7226 exit(1);
7227 }
7228 #endif
7229 #endif
7230
7231 #if defined(TARGET_PPC64)
7232 if (mmu_is_64bit(env->mmu_model)) {
7233 msr |= (1ULL << MSR_SF);
7234 }
7235 #endif
7236
7237 hreg_store_msr(env, msr, 1);
7238
7239 #if !defined(CONFIG_USER_ONLY)
7240 env->nip = env->hreset_vector | env->excp_prefix;
7241
7242 if (tcg_enabled()) {
7243 cpu_breakpoint_remove_all(cs, BP_CPU);
7244 cpu_watchpoint_remove_all(cs, BP_CPU);
7245 if (env->mmu_model != POWERPC_MMU_REAL) {
7246 ppc_tlb_invalidate_all(env);
7247 }
7248 pmu_mmcr01a_updated(env);
7249 }
7250
7251 /* clean any pending stop state */
7252 env->resume_as_sreset = 0;
7253 #endif
7254 hreg_compute_hflags(env);
7255 env->reserve_addr = (target_ulong)-1ULL;
7256 /* Be sure no exception or interrupt is pending */
7257 env->pending_interrupts = 0;
7258 cs->exception_index = POWERPC_EXCP_NONE;
7259 env->error_code = 0;
7260 ppc_irq_reset(cpu);
7261
7262 /* tininess for underflow is detected before rounding */
7263 set_float_detect_tininess(float_tininess_before_rounding,
7264 &env->fp_status);
7265 /*
7266 * PowerPC propagation rules:
7267 * 1. A if it sNaN or qNaN
7268 * 2. B if it sNaN or qNaN
7269 * A signaling NaN is always silenced before returning it.
7270 */
7271 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
7272 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
7273
7274 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7275 ppc_spr_t *spr = &env->spr_cb[i];
7276
7277 if (!spr->name) {
7278 continue;
7279 }
7280 env->spr[i] = spr->default_value;
7281 }
7282
7283 #if defined(TARGET_PPC64)
7284 bhrb_reset_state(env);
7285 #endif
7286 }
7287
7288 #ifndef CONFIG_USER_ONLY
7289
ppc_cpu_is_big_endian(CPUState * cs)7290 static bool ppc_cpu_is_big_endian(CPUState *cs)
7291 {
7292 cpu_synchronize_state(cs);
7293
7294 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
7295 }
7296
ppc_get_irq_stats(InterruptStatsProvider * obj,uint64_t ** irq_counts,unsigned int * nb_irqs)7297 static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
7298 uint64_t **irq_counts, unsigned int *nb_irqs)
7299 {
7300 CPUPPCState *env = &POWERPC_CPU(obj)->env;
7301
7302 *irq_counts = env->excp_stats;
7303 *nb_irqs = ARRAY_SIZE(env->excp_stats);
7304 return true;
7305 }
7306
7307 #ifdef CONFIG_TCG
ppc_cpu_exec_enter(CPUState * cs)7308 static void ppc_cpu_exec_enter(CPUState *cs)
7309 {
7310 PowerPCCPU *cpu = POWERPC_CPU(cs);
7311
7312 if (cpu->vhyp) {
7313 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu);
7314 }
7315 }
7316
ppc_cpu_exec_exit(CPUState * cs)7317 static void ppc_cpu_exec_exit(CPUState *cs)
7318 {
7319 PowerPCCPU *cpu = POWERPC_CPU(cs);
7320
7321 if (cpu->vhyp) {
7322 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
7323 }
7324 }
7325 #endif /* CONFIG_TCG */
7326
7327 #endif /* !CONFIG_USER_ONLY */
7328
ppc_cpu_instance_init(Object * obj)7329 static void ppc_cpu_instance_init(Object *obj)
7330 {
7331 PowerPCCPU *cpu = POWERPC_CPU(obj);
7332 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7333 CPUPPCState *env = &cpu->env;
7334
7335 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7336
7337 env->msr_mask = pcc->msr_mask;
7338 env->mmu_model = pcc->mmu_model;
7339 env->excp_model = pcc->excp_model;
7340 env->bus_model = pcc->bus_model;
7341 env->insns_flags = pcc->insns_flags;
7342 env->insns_flags2 = pcc->insns_flags2;
7343 env->flags = pcc->flags;
7344 env->bfd_mach = pcc->bfd_mach;
7345 env->check_pow = pcc->check_pow;
7346 env->check_attn = pcc->check_attn;
7347
7348 /*
7349 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7350 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7351 * mode support will remain, thus enforcing that we cannot use
7352 * priv. instructions in guest in PAPR mode. For 970 we currently
7353 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7354 * 970. If we ever want to support 970 HV mode, we'll have to add
7355 * a processor attribute of some sort.
7356 */
7357 #if !defined(CONFIG_USER_ONLY)
7358 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7359 #endif
7360
7361 ppc_hash64_init(cpu);
7362 }
7363
ppc_cpu_instance_finalize(Object * obj)7364 static void ppc_cpu_instance_finalize(Object *obj)
7365 {
7366 PowerPCCPU *cpu = POWERPC_CPU(obj);
7367
7368 ppc_hash64_finalize(cpu);
7369 }
7370
ppc_pvr_match_default(PowerPCCPUClass * pcc,uint32_t pvr,bool best)7371 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7372 {
7373 return pcc->pvr == pvr;
7374 }
7375
ppc_disas_set_info(CPUState * cs,disassemble_info * info)7376 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7377 {
7378 CPUPPCState *env = cpu_env(cs);
7379
7380 if ((env->hflags >> MSR_LE) & 1) {
7381 info->endian = BFD_ENDIAN_LITTLE;
7382 }
7383 info->mach = env->bfd_mach;
7384 if (!env->bfd_mach) {
7385 #ifdef TARGET_PPC64
7386 info->mach = bfd_mach_ppc64;
7387 #else
7388 info->mach = bfd_mach_ppc;
7389 #endif
7390 }
7391
7392 info->cap_arch = CS_ARCH_PPC;
7393 #ifdef TARGET_PPC64
7394 info->cap_mode = CS_MODE_64;
7395 #endif
7396 }
7397
7398 static Property ppc_cpu_properties[] = {
7399 /* add default property here */
7400 DEFINE_PROP_END_OF_LIST(),
7401 };
7402
7403 #ifndef CONFIG_USER_ONLY
7404 #include "hw/core/sysemu-cpu-ops.h"
7405
7406 static const struct SysemuCPUOps ppc_sysemu_ops = {
7407 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7408 .write_elf32_note = ppc32_cpu_write_elf32_note,
7409 .write_elf64_note = ppc64_cpu_write_elf64_note,
7410 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7411 .legacy_vmsd = &vmstate_ppc_cpu,
7412 };
7413 #endif
7414
7415 #ifdef CONFIG_TCG
7416 #include "hw/core/tcg-cpu-ops.h"
7417
7418 static const TCGCPUOps ppc_tcg_ops = {
7419 .initialize = ppc_translate_init,
7420 .restore_state_to_opc = ppc_restore_state_to_opc,
7421
7422 #ifdef CONFIG_USER_ONLY
7423 .record_sigsegv = ppc_cpu_record_sigsegv,
7424 #else
7425 .tlb_fill = ppc_cpu_tlb_fill,
7426 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7427 .cpu_exec_halt = ppc_cpu_has_work,
7428 .do_interrupt = ppc_cpu_do_interrupt,
7429 .cpu_exec_enter = ppc_cpu_exec_enter,
7430 .cpu_exec_exit = ppc_cpu_exec_exit,
7431 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7432 .do_transaction_failed = ppc_cpu_do_transaction_failed,
7433 .debug_excp_handler = ppc_cpu_debug_excp_handler,
7434 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
7435 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
7436 #endif /* !CONFIG_USER_ONLY */
7437 };
7438 #endif /* CONFIG_TCG */
7439
ppc_cpu_class_init(ObjectClass * oc,void * data)7440 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7441 {
7442 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7443 CPUClass *cc = CPU_CLASS(oc);
7444 DeviceClass *dc = DEVICE_CLASS(oc);
7445 ResettableClass *rc = RESETTABLE_CLASS(oc);
7446
7447 device_class_set_parent_realize(dc, ppc_cpu_realize,
7448 &pcc->parent_realize);
7449 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7450 &pcc->parent_unrealize);
7451 pcc->pvr_match = ppc_pvr_match_default;
7452 device_class_set_props(dc, ppc_cpu_properties);
7453
7454 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7455 &pcc->parent_phases);
7456
7457 cc->class_by_name = ppc_cpu_class_by_name;
7458 cc->has_work = ppc_cpu_has_work;
7459 cc->mmu_index = ppc_cpu_mmu_index;
7460 cc->dump_state = ppc_cpu_dump_state;
7461 cc->set_pc = ppc_cpu_set_pc;
7462 cc->get_pc = ppc_cpu_get_pc;
7463 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7464 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7465 #ifndef CONFIG_USER_ONLY
7466 cc->sysemu_ops = &ppc_sysemu_ops;
7467 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
7468
7469 /* check_prot_access_type relies on MMU access and PAGE bits relations */
7470 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 &&
7471 MMU_INST_FETCH == 2 && PAGE_READ == 1 &&
7472 PAGE_WRITE == 2 && PAGE_EXEC == 4);
7473 #endif
7474
7475 cc->gdb_num_core_regs = 71;
7476 #ifdef USE_APPLE_GDB
7477 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7478 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7479 cc->gdb_num_core_regs = 71 + 32;
7480 #endif
7481
7482 cc->gdb_arch_name = ppc_gdb_arch_name;
7483 #if defined(TARGET_PPC64)
7484 cc->gdb_core_xml_file = "power64-core.xml";
7485 #else
7486 cc->gdb_core_xml_file = "power-core.xml";
7487 #endif
7488 cc->disas_set_info = ppc_disas_set_info;
7489
7490 dc->fw_name = "PowerPC,UNKNOWN";
7491
7492 #ifdef CONFIG_TCG
7493 cc->tcg_ops = &ppc_tcg_ops;
7494 #endif /* CONFIG_TCG */
7495 }
7496
7497 static const TypeInfo ppc_cpu_type_info = {
7498 .name = TYPE_POWERPC_CPU,
7499 .parent = TYPE_CPU,
7500 .instance_size = sizeof(PowerPCCPU),
7501 .instance_align = __alignof__(PowerPCCPU),
7502 .instance_init = ppc_cpu_instance_init,
7503 .instance_finalize = ppc_cpu_instance_finalize,
7504 .abstract = true,
7505 .class_size = sizeof(PowerPCCPUClass),
7506 .class_init = ppc_cpu_class_init,
7507 #ifndef CONFIG_USER_ONLY
7508 .interfaces = (InterfaceInfo[]) {
7509 { TYPE_INTERRUPT_STATS_PROVIDER },
7510 { }
7511 },
7512 #endif
7513 };
7514
7515 #ifndef CONFIG_USER_ONLY
7516 static const TypeInfo ppc_vhyp_type_info = {
7517 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7518 .parent = TYPE_INTERFACE,
7519 .class_size = sizeof(PPCVirtualHypervisorClass),
7520 };
7521 #endif
7522
ppc_cpu_register_types(void)7523 static void ppc_cpu_register_types(void)
7524 {
7525 type_register_static(&ppc_cpu_type_info);
7526 #ifndef CONFIG_USER_ONLY
7527 type_register_static(&ppc_vhyp_type_info);
7528 #endif
7529 }
7530
ppc_cpu_dump_state(CPUState * cs,FILE * f,int flags)7531 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7532 {
7533 #define RGPL 4
7534 #define RFPL 4
7535
7536 CPUPPCState *env = cpu_env(cs);
7537 int i;
7538
7539 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7540 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7541 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7542 cs->cpu_index);
7543 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7544 "%08x iidx %d didx %d\n",
7545 env->msr, env->spr[SPR_HID0], env->hflags,
7546 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
7547 #if !defined(CONFIG_USER_ONLY)
7548 if (env->tb_env) {
7549 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7550 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7551 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7552 }
7553 #else
7554 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7555 cpu_ppc_load_tbl(env));
7556 #endif
7557 for (i = 0; i < 32; i++) {
7558 if ((i & (RGPL - 1)) == 0) {
7559 qemu_fprintf(f, "GPR%02d", i);
7560 }
7561 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7562 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7563 qemu_fprintf(f, "\n");
7564 }
7565 }
7566 qemu_fprintf(f, "CR ");
7567 for (i = 0; i < 8; i++)
7568 qemu_fprintf(f, "%01x", env->crf[i]);
7569 qemu_fprintf(f, " [");
7570 for (i = 0; i < 8; i++) {
7571 char a = '-';
7572 if (env->crf[i] & 0x08) {
7573 a = 'L';
7574 } else if (env->crf[i] & 0x04) {
7575 a = 'G';
7576 } else if (env->crf[i] & 0x02) {
7577 a = 'E';
7578 }
7579 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7580 }
7581 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n",
7582 (int)env->reserve_length, env->reserve_addr);
7583
7584 if (flags & CPU_DUMP_FPU) {
7585 for (i = 0; i < 32; i++) {
7586 if ((i & (RFPL - 1)) == 0) {
7587 qemu_fprintf(f, "FPR%02d", i);
7588 }
7589 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7590 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7591 qemu_fprintf(f, "\n");
7592 }
7593 }
7594 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7595 }
7596
7597 #if !defined(CONFIG_USER_ONLY)
7598 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7599 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7600 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7601 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7602
7603 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7604 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7605 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7606 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7607
7608 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7609 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7610 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7611 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7612
7613 switch (env->excp_model) {
7614 #if defined(TARGET_PPC64)
7615 case POWERPC_EXCP_POWER7:
7616 case POWERPC_EXCP_POWER8:
7617 case POWERPC_EXCP_POWER9:
7618 case POWERPC_EXCP_POWER10:
7619 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7620 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7621 break;
7622 #endif
7623 case POWERPC_EXCP_BOOKE:
7624 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7625 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7626 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7627 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7628
7629 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7630 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7631 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7632 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7633
7634 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7635 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7636 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7637 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7638
7639 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7640 " EPR " TARGET_FMT_lx "\n",
7641 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7642 env->spr[SPR_BOOKE_EPR]);
7643
7644 /* FSL-specific */
7645 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7646 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7647 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7648 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7649
7650 /*
7651 * IVORs are left out as they are large and do not change often --
7652 * they can be read with "p $ivor0", "p $ivor1", etc.
7653 */
7654 break;
7655 case POWERPC_EXCP_40x:
7656 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7657 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7658 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7659 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7660
7661 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7662 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7663 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7664 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7665 break;
7666 default:
7667 break;
7668 }
7669
7670 #if defined(TARGET_PPC64)
7671 if (env->flags & POWERPC_FLAG_CFAR) {
7672 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7673 }
7674 #endif
7675
7676 if (env->spr_cb[SPR_LPCR].name) {
7677 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7678 }
7679
7680 switch (env->mmu_model) {
7681 case POWERPC_MMU_32B:
7682 case POWERPC_MMU_SOFT_6xx:
7683 #if defined(TARGET_PPC64)
7684 case POWERPC_MMU_64B:
7685 case POWERPC_MMU_2_03:
7686 case POWERPC_MMU_2_06:
7687 case POWERPC_MMU_2_07:
7688 case POWERPC_MMU_3_00:
7689 #endif
7690 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7691 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7692 }
7693 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7694 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7695 }
7696 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7697 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7698 break;
7699 case POWERPC_MMU_BOOKE206:
7700 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7701 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7702 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7703 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7704
7705 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7706 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7707 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7708 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7709
7710 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7711 " TLB1CFG " TARGET_FMT_lx "\n",
7712 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7713 env->spr[SPR_BOOKE_TLB1CFG]);
7714 break;
7715 default:
7716 break;
7717 }
7718 #endif
7719
7720 #undef RGPL
7721 #undef RFPL
7722 }
7723 type_init(ppc_cpu_register_types)
7724