xref: /openbmc/qemu/target/ppc/cpu.h (revision 8d7ebae4) 
1 /*
2  *  PowerPC emulation cpu definitions for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22 
23 #include "qemu/int128.h"
24 #include "exec/cpu-defs.h"
25 #include "cpu-qom.h"
26 #include "qom/object.h"
27 
28 #define TCG_GUEST_DEFAULT_MO 0
29 
30 #define TARGET_PAGE_BITS_64K 16
31 #define TARGET_PAGE_BITS_16M 24
32 
33 #if defined(TARGET_PPC64)
34 #define PPC_ELF_MACHINE     EM_PPC64
35 #else
36 #define PPC_ELF_MACHINE     EM_PPC
37 #endif
38 
39 #define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
40 #define PPC_BIT32(bit)          (0x80000000 >> (bit))
41 #define PPC_BIT8(bit)           (0x80 >> (bit))
42 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
43 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
44                                  PPC_BIT32(bs))
45 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
46 
47 /*****************************************************************************/
48 /* Exception vectors definitions                                             */
49 enum {
50     POWERPC_EXCP_NONE    = -1,
51     /* The 64 first entries are used by the PowerPC embedded specification   */
52     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
53     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
54     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
55     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
56     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
57     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
58     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
59     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
60     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
61     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
62     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
63     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
64     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
65     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
66     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
67     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
68     /* Vectors 16 to 31 are reserved                                         */
69     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
70     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
71     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
72     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
73     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
74     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
75     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
76     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
77     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
78     /* Vectors 42 to 63 are reserved                                         */
79     /* Exceptions defined in the PowerPC server specification                */
80     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
81     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
82     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
83     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
84     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
85     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
86     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
87     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
88     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
89     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
90     /* 40x specific exceptions                                               */
91     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
92     /* 601 specific exceptions                                               */
93     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
94     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
95     /* 602 specific exceptions                                               */
96     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
97     /* 602/603 specific exceptions                                           */
98     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
99     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
100     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
101     /* Exceptions available on most PowerPC                                  */
102     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
103     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
104     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
105     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
106     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
107     /* 7xx/74xx specific exceptions                                          */
108     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
109     /* 74xx specific exceptions                                              */
110     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
111     /* 970FX specific exceptions                                             */
112     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
113     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
114     /* Freescale embedded cores specific exceptions                          */
115     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
116     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
117     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
118     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
119     /* VSX Unavailable (Power ISA 2.06 and later)                            */
120     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
121     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
122     /* Additional ISA 2.06 and later server exceptions                       */
123     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
124     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
125     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
126     /* Server doorbell variants */
127     POWERPC_EXCP_SDOOR    = 99,
128     POWERPC_EXCP_SDOOR_HV = 100,
129     /* ISA 3.00 additions */
130     POWERPC_EXCP_HVIRT    = 101,
131     POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
132     /* EOL                                                                   */
133     POWERPC_EXCP_NB       = 103,
134     /* QEMU exceptions: special cases we want to stop translation            */
135     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
136 };
137 
138 /* Exceptions error codes                                                    */
139 enum {
140     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
141     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
142     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
143     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
144     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
145     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
146     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
147     POWERPC_EXCP_ALIGN_INSN    = 0x07,  /* Pref. insn x-ing 64-byte boundary */
148     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
149     /* FP exceptions                                                         */
150     POWERPC_EXCP_FP            = 0x10,
151     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
152     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
153     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
154     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
155     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
156     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
157     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
158     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
159     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
160     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
161     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
162     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
163     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
164     /* Invalid instruction                                                   */
165     POWERPC_EXCP_INVAL         = 0x20,
166     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
167     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
168     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
169     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
170     /* Privileged instruction                                                */
171     POWERPC_EXCP_PRIV          = 0x30,
172     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
173     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
174     /* Trap                                                                  */
175     POWERPC_EXCP_TRAP          = 0x40,
176 };
177 
178 #define PPC_INPUT(env) ((env)->bus_model)
179 
180 /*****************************************************************************/
181 typedef struct opc_handler_t opc_handler_t;
182 
183 /*****************************************************************************/
184 /* Types used to describe some PowerPC registers etc. */
185 typedef struct DisasContext DisasContext;
186 typedef struct ppc_spr_t ppc_spr_t;
187 typedef union ppc_tlb_t ppc_tlb_t;
188 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
189 
190 /* SPR access micro-ops generations callbacks */
191 struct ppc_spr_t {
192     const char *name;
193     target_ulong default_value;
194 #ifndef CONFIG_USER_ONLY
195     unsigned int gdb_id;
196 #endif
197 #ifdef CONFIG_TCG
198     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
199     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
200 # ifndef CONFIG_USER_ONLY
201     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
202     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
203     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
204     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
205 # endif
206 #endif
207 #ifdef CONFIG_KVM
208     /*
209      * We (ab)use the fact that all the SPRs will have ids for the
210      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
211      * don't sync this
212      */
213     uint64_t one_reg_id;
214 #endif
215 };
216 
217 /* VSX/Altivec registers (128 bits) */
218 typedef union _ppc_vsr_t {
219     uint8_t u8[16];
220     uint16_t u16[8];
221     uint32_t u32[4];
222     uint64_t u64[2];
223     int8_t s8[16];
224     int16_t s16[8];
225     int32_t s32[4];
226     int64_t s64[2];
227     float32 f32[4];
228     float64 f64[2];
229     float128 f128;
230 #ifdef CONFIG_INT128
231     __uint128_t u128;
232 #endif
233     Int128  s128;
234 } ppc_vsr_t;
235 
236 typedef ppc_vsr_t ppc_avr_t;
237 typedef ppc_vsr_t ppc_fprp_t;
238 
239 #if !defined(CONFIG_USER_ONLY)
240 /* Software TLB cache */
241 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
242 struct ppc6xx_tlb_t {
243     target_ulong pte0;
244     target_ulong pte1;
245     target_ulong EPN;
246 };
247 
248 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
249 struct ppcemb_tlb_t {
250     uint64_t RPN;
251     target_ulong EPN;
252     target_ulong PID;
253     target_ulong size;
254     uint32_t prot;
255     uint32_t attr; /* Storage attributes */
256 };
257 
258 typedef struct ppcmas_tlb_t {
259      uint32_t mas8;
260      uint32_t mas1;
261      uint64_t mas2;
262      uint64_t mas7_3;
263 } ppcmas_tlb_t;
264 
265 union ppc_tlb_t {
266     ppc6xx_tlb_t *tlb6;
267     ppcemb_tlb_t *tlbe;
268     ppcmas_tlb_t *tlbm;
269 };
270 
271 /* possible TLB variants */
272 #define TLB_NONE               0
273 #define TLB_6XX                1
274 #define TLB_EMB                2
275 #define TLB_MAS                3
276 #endif
277 
278 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
279 
280 typedef struct ppc_slb_t ppc_slb_t;
281 struct ppc_slb_t {
282     uint64_t esid;
283     uint64_t vsid;
284     const PPCHash64SegmentPageSizes *sps;
285 };
286 
287 #define MAX_SLB_ENTRIES         64
288 #define SEGMENT_SHIFT_256M      28
289 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
290 
291 #define SEGMENT_SHIFT_1T        40
292 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
293 
294 typedef struct ppc_v3_pate_t {
295     uint64_t dw0;
296     uint64_t dw1;
297 } ppc_v3_pate_t;
298 
299 /* PMU related structs and defines */
300 #define PMU_COUNTERS_NUM 6
301 typedef enum {
302     PMU_EVENT_INVALID = 0,
303     PMU_EVENT_INACTIVE,
304     PMU_EVENT_CYCLES,
305     PMU_EVENT_INSTRUCTIONS,
306     PMU_EVENT_INSN_RUN_LATCH,
307 } PMUEventType;
308 
309 /*****************************************************************************/
310 /* Machine state register bits definition                                    */
311 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
312 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
313 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
314 #define MSR_HV   60 /* hypervisor state                               hflags */
315 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
316 #define MSR_TS1  33
317 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
318 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
319 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
320 #define MSR_GS   28 /* guest state for BookE                                 */
321 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
322 #define MSR_VR   25 /* altivec available                            x hflags */
323 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
324 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
325 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
326 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
327 #define MSR_S    22 /* Secure state                                          */
328 #define MSR_KEY  19 /* key bit on 603e                                       */
329 #define MSR_POW  18 /* Power management                                      */
330 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
331 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
332 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
333 #define MSR_EE   15 /* External interrupt enable                             */
334 #define MSR_PR   14 /* Problem state                                  hflags */
335 #define MSR_FP   13 /* Floating point available                       hflags */
336 #define MSR_ME   12 /* Machine check interrupt enable                        */
337 #define MSR_FE0  11 /* Floating point exception mode 0                       */
338 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
339 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
340 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
341 #define MSR_BE   9  /* Branch trace enable                          x hflags */
342 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
343 #define MSR_FE1  8  /* Floating point exception mode 1                       */
344 #define MSR_AL   7  /* AL bit on POWER                                       */
345 #define MSR_EP   6  /* Exception prefix on 601                               */
346 #define MSR_IR   5  /* Instruction relocate                                  */
347 #define MSR_DR   4  /* Data relocate                                         */
348 #define MSR_IS   5  /* Instruction address space (BookE)                     */
349 #define MSR_DS   4  /* Data address space (BookE)                            */
350 #define MSR_PE   3  /* Protection enable on 403                              */
351 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
352 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
353 #define MSR_RI   1  /* Recoverable interrupt                        1        */
354 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
355 
356 /* PMU bits */
357 #define MMCR0_FC     PPC_BIT(32)         /* Freeze Counters  */
358 #define MMCR0_PMAO   PPC_BIT(56)         /* Perf Monitor Alert Ocurred */
359 #define MMCR0_PMAE   PPC_BIT(37)         /* Perf Monitor Alert Enable */
360 #define MMCR0_EBE    PPC_BIT(43)         /* Perf Monitor EBB Enable */
361 #define MMCR0_FCECE  PPC_BIT(38)         /* FC on Enabled Cond or Event */
362 #define MMCR0_PMCC0  PPC_BIT(44)         /* PMC Control bit 0 */
363 #define MMCR0_PMCC1  PPC_BIT(45)         /* PMC Control bit 1 */
364 #define MMCR0_PMCC   PPC_BITMASK(44, 45) /* PMC Control */
365 #define MMCR0_FC14   PPC_BIT(58)         /* PMC Freeze Counters 1-4 bit */
366 #define MMCR0_FC56   PPC_BIT(59)         /* PMC Freeze Counters 5-6 bit */
367 #define MMCR0_PMC1CE PPC_BIT(48)         /* MMCR0 PMC1 Condition Enabled */
368 #define MMCR0_PMCjCE PPC_BIT(49)         /* MMCR0 PMCj Condition Enabled */
369 /* MMCR0 userspace r/w mask */
370 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
371 /* MMCR2 userspace r/w mask */
372 #define MMCR2_FC1P0  PPC_BIT(1)          /* MMCR2 FCnP0 for PMC1 */
373 #define MMCR2_FC2P0  PPC_BIT(10)         /* MMCR2 FCnP0 for PMC2 */
374 #define MMCR2_FC3P0  PPC_BIT(19)         /* MMCR2 FCnP0 for PMC3 */
375 #define MMCR2_FC4P0  PPC_BIT(28)         /* MMCR2 FCnP0 for PMC4 */
376 #define MMCR2_FC5P0  PPC_BIT(37)         /* MMCR2 FCnP0 for PMC5 */
377 #define MMCR2_FC6P0  PPC_BIT(46)         /* MMCR2 FCnP0 for PMC6 */
378 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
379                          MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
380 
381 #define MMCR1_EVT_SIZE 8
382 /* extract64() does a right shift before extracting */
383 #define MMCR1_PMC1SEL_START 32
384 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
385 #define MMCR1_PMC2SEL_START 40
386 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
387 #define MMCR1_PMC3SEL_START 48
388 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
389 #define MMCR1_PMC4SEL_START 56
390 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
391 
392 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
393 #define CTRL_RUN PPC_BIT(63)
394 
395 /* EBB/BESCR bits */
396 /* Global Enable */
397 #define BESCR_GE PPC_BIT(0)
398 /* External Event-based Exception Enable */
399 #define BESCR_EE PPC_BIT(30)
400 /* Performance Monitor Event-based Exception Enable */
401 #define BESCR_PME PPC_BIT(31)
402 /* External Event-based Exception Occurred */
403 #define BESCR_EEO PPC_BIT(62)
404 /* Performance Monitor Event-based Exception Occurred */
405 #define BESCR_PMEO PPC_BIT(63)
406 #define BESCR_INVALID PPC_BITMASK(32, 33)
407 
408 /* LPCR bits */
409 #define LPCR_VPM0         PPC_BIT(0)
410 #define LPCR_VPM1         PPC_BIT(1)
411 #define LPCR_ISL          PPC_BIT(2)
412 #define LPCR_KBV          PPC_BIT(3)
413 #define LPCR_DPFD_SHIFT   (63 - 11)
414 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
415 #define LPCR_VRMASD_SHIFT (63 - 16)
416 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
417 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
418 #define LPCR_PECE_U_SHIFT (63 - 19)
419 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
420 #define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
421 #define LPCR_RMLS_SHIFT   (63 - 37)   /* RMLS (removed in ISA v3.0) */
422 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
423 #define LPCR_HAIL         PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
424 #define LPCR_ILE          PPC_BIT(38)
425 #define LPCR_AIL_SHIFT    (63 - 40)   /* Alternate interrupt location */
426 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
427 #define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
428 #define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
429 #define LPCR_HR           PPC_BIT(43) /* Host Radix */
430 #define LPCR_ONL          PPC_BIT(45)
431 #define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
432 #define LPCR_P7_PECE0     PPC_BIT(49)
433 #define LPCR_P7_PECE1     PPC_BIT(50)
434 #define LPCR_P7_PECE2     PPC_BIT(51)
435 #define LPCR_P8_PECE0     PPC_BIT(47)
436 #define LPCR_P8_PECE1     PPC_BIT(48)
437 #define LPCR_P8_PECE2     PPC_BIT(49)
438 #define LPCR_P8_PECE3     PPC_BIT(50)
439 #define LPCR_P8_PECE4     PPC_BIT(51)
440 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
441 #define LPCR_PECE_L_SHIFT (63 - 51)
442 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
443 #define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
444 #define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
445 #define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
446 #define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
447 #define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
448 #define LPCR_MER          PPC_BIT(52)
449 #define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
450 #define LPCR_TC           PPC_BIT(54)
451 #define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
452 #define LPCR_LPES0        PPC_BIT(60)
453 #define LPCR_LPES1        PPC_BIT(61)
454 #define LPCR_RMI          PPC_BIT(62)
455 #define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
456 #define LPCR_HDICE        PPC_BIT(63)
457 
458 /* PSSCR bits */
459 #define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
460 #define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
461 
462 /* HFSCR bits */
463 #define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
464 #define HFSCR_IC_MSGP  0xA
465 
466 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
467 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
468 #if defined(TARGET_PPC64)
469 #define msr_hv   ((env->msr >> MSR_HV)   & 1)
470 #else
471 #define msr_hv   (0)
472 #endif
473 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
474 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
475 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
476 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
477 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
478 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
479 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
480 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
481 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
482 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
483 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
484 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
485 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
486 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
487 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
488 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
489 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
490 #define msr_me   ((env->msr >> MSR_ME)   & 1)
491 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
492 #define msr_se   ((env->msr >> MSR_SE)   & 1)
493 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
494 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
495 #define msr_be   ((env->msr >> MSR_BE)   & 1)
496 #define msr_de   ((env->msr >> MSR_DE)   & 1)
497 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
498 #define msr_al   ((env->msr >> MSR_AL)   & 1)
499 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
500 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
501 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
502 #define msr_is   ((env->msr >> MSR_IS)   & 1)
503 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
504 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
505 #define msr_px   ((env->msr >> MSR_PX)   & 1)
506 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
507 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
508 #define msr_le   ((env->msr >> MSR_LE)   & 1)
509 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
510 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
511 
512 #define DBCR0_ICMP (1 << 27)
513 #define DBCR0_BRT (1 << 26)
514 #define DBSR_ICMP (1 << 27)
515 #define DBSR_BRT (1 << 26)
516 
517 /* Hypervisor bit is more specific */
518 #if defined(TARGET_PPC64)
519 #define MSR_HVB (1ULL << MSR_HV)
520 #else
521 #define MSR_HVB (0ULL)
522 #endif
523 
524 /* DSISR */
525 #define DSISR_NOPTE              0x40000000
526 /* Not permitted by access authority of encoded access authority */
527 #define DSISR_PROTFAULT          0x08000000
528 #define DSISR_ISSTORE            0x02000000
529 /* Not permitted by virtual page class key protection */
530 #define DSISR_AMR                0x00200000
531 /* Unsupported Radix Tree Configuration */
532 #define DSISR_R_BADCONFIG        0x00080000
533 #define DSISR_ATOMIC_RC          0x00040000
534 /* Unable to translate address of (guest) pde or process/page table entry */
535 #define DSISR_PRTABLE_FAULT      0x00020000
536 
537 /* SRR1 error code fields */
538 
539 #define SRR1_NOPTE               DSISR_NOPTE
540 /* Not permitted due to no-execute or guard bit set */
541 #define SRR1_NOEXEC_GUARD        0x10000000
542 #define SRR1_PROTFAULT           DSISR_PROTFAULT
543 #define SRR1_IAMR                DSISR_AMR
544 
545 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
546 
547 #define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
548 
549 #define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
550 #define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
551 #define SRR1_WAKEEE             0x00200000 /* External interrupt */
552 #define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
553 #define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
554 #define SRR1_WAKERESET          0x00100000 /* System reset */
555 #define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
556 #define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
557 
558 /* SRR1[46:47] power-saving exit mode */
559 
560 #define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
561 
562 #define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
563 #define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
564 #define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
565 
566 /* Facility Status and Control (FSCR) bits */
567 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
568 #define FSCR_TAR        (63 - 55) /* Target Address Register */
569 #define FSCR_SCV        (63 - 51) /* System call vectored */
570 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
571 #define FSCR_IC_MASK    (0xFFULL)
572 #define FSCR_IC_POS     (63 - 7)
573 #define FSCR_IC_DSCR_SPR3   2
574 #define FSCR_IC_PMU         3
575 #define FSCR_IC_BHRB        4
576 #define FSCR_IC_TM          5
577 #define FSCR_IC_EBB         7
578 #define FSCR_IC_TAR         8
579 #define FSCR_IC_SCV        12
580 
581 /* Exception state register bits definition                                  */
582 #define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
583 #define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
584 #define ESR_PTR   PPC_BIT(38) /* Trap                                   */
585 #define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
586 #define ESR_ST    PPC_BIT(40) /* Store Operation                        */
587 #define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
588 #define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
589 #define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
590 #define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
591 #define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
592 #define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
593 #define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
594 #define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
595 #define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
596 #define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
597 #define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
598 
599 /* Transaction EXception And Summary Register bits                           */
600 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
601 #define TEXASR_DISALLOWED                        (63 - 8)
602 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
603 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
604 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
605 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
606 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
607 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
608 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
609 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
610 #define TEXASR_ABORT                             (63 - 31)
611 #define TEXASR_SUSPENDED                         (63 - 32)
612 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
613 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
614 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
615 #define TEXASR_TFIAR_EXACT                       (63 - 37)
616 #define TEXASR_ROT                               (63 - 38)
617 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
618 
619 enum {
620     POWERPC_FLAG_NONE     = 0x00000000,
621     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
622     POWERPC_FLAG_SPE      = 0x00000001,
623     POWERPC_FLAG_VRE      = 0x00000002,
624     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
625     POWERPC_FLAG_TGPR     = 0x00000004,
626     POWERPC_FLAG_CE       = 0x00000008,
627     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
628     POWERPC_FLAG_SE       = 0x00000010,
629     POWERPC_FLAG_DWE      = 0x00000020,
630     POWERPC_FLAG_UBLE     = 0x00000040,
631     /* Flag for MSR bit 9 signification (BE/DE)                              */
632     POWERPC_FLAG_BE       = 0x00000080,
633     POWERPC_FLAG_DE       = 0x00000100,
634     /* Flag for MSR bit 2 signification (PX/PMM)                             */
635     POWERPC_FLAG_PX       = 0x00000200,
636     POWERPC_FLAG_PMM      = 0x00000400,
637     /* Flag for special features                                             */
638     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
639     POWERPC_FLAG_RTC_CLK  = 0x00010000,
640     POWERPC_FLAG_BUS_CLK  = 0x00020000,
641     /* Has CFAR                                                              */
642     POWERPC_FLAG_CFAR     = 0x00040000,
643     /* Has VSX                                                               */
644     POWERPC_FLAG_VSX      = 0x00080000,
645     /* Has Transaction Memory (ISA 2.07)                                     */
646     POWERPC_FLAG_TM       = 0x00100000,
647     /* Has SCV (ISA 3.00)                                                    */
648     POWERPC_FLAG_SCV      = 0x00200000,
649     /* Has HID0 for LE bit (601)                                             */
650     POWERPC_FLAG_HID0_LE  = 0x00400000,
651 };
652 
653 /*
654  * Bits for env->hflags.
655  *
656  * Most of these bits overlap with corresponding bits in MSR,
657  * but some come from other sources.  Those that do come from
658  * the MSR are validated in hreg_compute_hflags.
659  */
660 enum {
661     HFLAGS_LE = 0,   /* MSR_LE -- comes from elsewhere on 601 */
662     HFLAGS_HV = 1,   /* computed from MSR_HV and other state */
663     HFLAGS_64 = 2,   /* computed from MSR_CE and MSR_SF */
664     HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
665     HFLAGS_DR = 4,   /* MSR_DR */
666     HFLAGS_HR = 5,   /* computed from SPR_LPCR[HR] */
667     HFLAGS_SPE = 6,  /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
668     HFLAGS_TM = 8,   /* computed from MSR_TM */
669     HFLAGS_BE = 9,   /* MSR_BE -- from elsewhere on embedded ppc */
670     HFLAGS_SE = 10,  /* MSR_SE -- from elsewhere on embedded ppc */
671     HFLAGS_FP = 13,  /* MSR_FP */
672     HFLAGS_PR = 14,  /* MSR_PR */
673     HFLAGS_PMCC0 = 15,  /* MMCR0 PMCC bit 0 */
674     HFLAGS_PMCC1 = 16,  /* MMCR0 PMCC bit 1 */
675     HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */
676     HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
677     HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
678 
679     HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
680     HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
681 };
682 
683 /*****************************************************************************/
684 /* Floating point status and control register                                */
685 #define FPSCR_DRN2   34 /* Decimal Floating-Point rounding control           */
686 #define FPSCR_DRN1   33 /* Decimal Floating-Point rounding control           */
687 #define FPSCR_DRN0   32 /* Decimal Floating-Point rounding control           */
688 #define FPSCR_FX     31 /* Floating-point exception summary                  */
689 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
690 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
691 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
692 #define FPSCR_UX     27 /* Floating-point underflow exception                */
693 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
694 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
695 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
696 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
697 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
698 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
699 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
700 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
701 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
702 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
703 #define FPSCR_C      16 /* Floating-point result class descriptor            */
704 #define FPSCR_FL     15 /* Floating-point less than or negative              */
705 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
706 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
707 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
708 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
709 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
710 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
711 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
712 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
713 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
714 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
715 #define FPSCR_UE     5  /* Floating-point underflow exception enable          */
716 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
717 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
718 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
719 #define FPSCR_RN1    1
720 #define FPSCR_RN0    0  /* Floating-point rounding control                   */
721 #define fpscr_drn    (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
722 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
723 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
724 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
725 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
726 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
727 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
728 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
729 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
730 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
731 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
732 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
733 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
734 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
735 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
736 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
737 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
738 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
739 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
740 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
741 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
742 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
743 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
744 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN0)    & 0x3)
745 /* Invalid operation exception summary */
746 #define FPSCR_IX     ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
747                       (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
748                       (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
749                       (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
750                       (1 << FPSCR_VXCVI))
751 /* exception summary */
752 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
753 /* enabled exception summary */
754 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
755                    0x1F)
756 
757 #define FP_DRN2         (1ull << FPSCR_DRN2)
758 #define FP_DRN1         (1ull << FPSCR_DRN1)
759 #define FP_DRN0         (1ull << FPSCR_DRN0)
760 #define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
761 #define FP_FX           (1ull << FPSCR_FX)
762 #define FP_FEX          (1ull << FPSCR_FEX)
763 #define FP_VX           (1ull << FPSCR_VX)
764 #define FP_OX           (1ull << FPSCR_OX)
765 #define FP_UX           (1ull << FPSCR_UX)
766 #define FP_ZX           (1ull << FPSCR_ZX)
767 #define FP_XX           (1ull << FPSCR_XX)
768 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
769 #define FP_VXISI        (1ull << FPSCR_VXISI)
770 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
771 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
772 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
773 #define FP_VXVC         (1ull << FPSCR_VXVC)
774 #define FP_FR           (1ull << FPSCR_FR)
775 #define FP_FI           (1ull << FPSCR_FI)
776 #define FP_C            (1ull << FPSCR_C)
777 #define FP_FL           (1ull << FPSCR_FL)
778 #define FP_FG           (1ull << FPSCR_FG)
779 #define FP_FE           (1ull << FPSCR_FE)
780 #define FP_FU           (1ull << FPSCR_FU)
781 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
782 #define FP_FPRF         (FP_C | FP_FPCC)
783 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
784 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
785 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
786 #define FP_VE           (1ull << FPSCR_VE)
787 #define FP_OE           (1ull << FPSCR_OE)
788 #define FP_UE           (1ull << FPSCR_UE)
789 #define FP_ZE           (1ull << FPSCR_ZE)
790 #define FP_XE           (1ull << FPSCR_XE)
791 #define FP_NI           (1ull << FPSCR_NI)
792 #define FP_RN1          (1ull << FPSCR_RN1)
793 #define FP_RN0          (1ull << FPSCR_RN0)
794 #define FP_RN           (FP_RN1 | FP_RN0)
795 
796 #define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
797 #define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
798 
799 /* the exception bits which can be cleared by mcrfs - includes FX */
800 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
801                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
802                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
803                           FP_VXSQRT | FP_VXCVI)
804 
805 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
806 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) |        \
807                            FP_FEX | FP_VX | PPC_BIT(52)))
808 
809 /*****************************************************************************/
810 /* Vector status and control register */
811 #define VSCR_NJ         16 /* Vector non-java */
812 #define VSCR_SAT        0 /* Vector saturation */
813 
814 /*****************************************************************************/
815 /* BookE e500 MMU registers */
816 
817 #define MAS0_NV_SHIFT      0
818 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
819 
820 #define MAS0_WQ_SHIFT      12
821 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
822 /* Write TLB entry regardless of reservation */
823 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
824 /* Write TLB entry only already in use */
825 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
826 /* Clear TLB entry */
827 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
828 
829 #define MAS0_HES_SHIFT     14
830 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
831 
832 #define MAS0_ESEL_SHIFT    16
833 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
834 
835 #define MAS0_TLBSEL_SHIFT  28
836 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
837 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
838 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
839 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
840 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
841 
842 #define MAS0_ATSEL_SHIFT   31
843 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
844 #define MAS0_ATSEL_TLB     0
845 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
846 
847 #define MAS1_TSIZE_SHIFT   7
848 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
849 
850 #define MAS1_TS_SHIFT      12
851 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
852 
853 #define MAS1_IND_SHIFT     13
854 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
855 
856 #define MAS1_TID_SHIFT     16
857 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
858 
859 #define MAS1_IPROT_SHIFT   30
860 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
861 
862 #define MAS1_VALID_SHIFT   31
863 #define MAS1_VALID         0x80000000
864 
865 #define MAS2_EPN_SHIFT     12
866 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
867 
868 #define MAS2_ACM_SHIFT     6
869 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
870 
871 #define MAS2_VLE_SHIFT     5
872 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
873 
874 #define MAS2_W_SHIFT       4
875 #define MAS2_W             (1 << MAS2_W_SHIFT)
876 
877 #define MAS2_I_SHIFT       3
878 #define MAS2_I             (1 << MAS2_I_SHIFT)
879 
880 #define MAS2_M_SHIFT       2
881 #define MAS2_M             (1 << MAS2_M_SHIFT)
882 
883 #define MAS2_G_SHIFT       1
884 #define MAS2_G             (1 << MAS2_G_SHIFT)
885 
886 #define MAS2_E_SHIFT       0
887 #define MAS2_E             (1 << MAS2_E_SHIFT)
888 
889 #define MAS3_RPN_SHIFT     12
890 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
891 
892 #define MAS3_U0                 0x00000200
893 #define MAS3_U1                 0x00000100
894 #define MAS3_U2                 0x00000080
895 #define MAS3_U3                 0x00000040
896 #define MAS3_UX                 0x00000020
897 #define MAS3_SX                 0x00000010
898 #define MAS3_UW                 0x00000008
899 #define MAS3_SW                 0x00000004
900 #define MAS3_UR                 0x00000002
901 #define MAS3_SR                 0x00000001
902 #define MAS3_SPSIZE_SHIFT       1
903 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
904 
905 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
906 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
907 #define MAS4_TIDSELD_MASK       0x00030000
908 #define MAS4_TIDSELD_PID0       0x00000000
909 #define MAS4_TIDSELD_PID1       0x00010000
910 #define MAS4_TIDSELD_PID2       0x00020000
911 #define MAS4_TIDSELD_PIDZ       0x00030000
912 #define MAS4_INDD               0x00008000      /* Default IND */
913 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
914 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
915 #define MAS4_ACMD               0x00000040
916 #define MAS4_VLED               0x00000020
917 #define MAS4_WD                 0x00000010
918 #define MAS4_ID                 0x00000008
919 #define MAS4_MD                 0x00000004
920 #define MAS4_GD                 0x00000002
921 #define MAS4_ED                 0x00000001
922 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
923 #define MAS4_WIMGED_SHIFT       0
924 
925 #define MAS5_SGS                0x80000000
926 #define MAS5_SLPID_MASK         0x00000fff
927 
928 #define MAS6_SPID0              0x3fff0000
929 #define MAS6_SPID1              0x00007ffe
930 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
931 #define MAS6_SAS                0x00000001
932 #define MAS6_SPID               MAS6_SPID0
933 #define MAS6_SIND               0x00000002      /* Indirect page */
934 #define MAS6_SIND_SHIFT         1
935 #define MAS6_SPID_MASK          0x3fff0000
936 #define MAS6_SPID_SHIFT         16
937 #define MAS6_ISIZE_MASK         0x00000f80
938 #define MAS6_ISIZE_SHIFT        7
939 
940 #define MAS7_RPN                0xffffffff
941 
942 #define MAS8_TGS                0x80000000
943 #define MAS8_VF                 0x40000000
944 #define MAS8_TLBPID             0x00000fff
945 
946 /* Bit definitions for MMUCFG */
947 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
948 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
949 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
950 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
951 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
952 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
953 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
954 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
955 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
956 
957 /* Bit definitions for MMUCSR0 */
958 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
959 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
960 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
961 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
962 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
963                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
964 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
965 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
966 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
967 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
968 
969 /* TLBnCFG encoding */
970 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
971 #define TLBnCFG_HES             0x00002000      /* HW select supported */
972 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
973 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
974 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
975 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
976 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
977 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
978 #define TLBnCFG_MINSIZE_SHIFT   20
979 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
980 #define TLBnCFG_MAXSIZE_SHIFT   16
981 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
982 #define TLBnCFG_ASSOC_SHIFT     24
983 
984 /* TLBnPS encoding */
985 #define TLBnPS_4K               0x00000004
986 #define TLBnPS_8K               0x00000008
987 #define TLBnPS_16K              0x00000010
988 #define TLBnPS_32K              0x00000020
989 #define TLBnPS_64K              0x00000040
990 #define TLBnPS_128K             0x00000080
991 #define TLBnPS_256K             0x00000100
992 #define TLBnPS_512K             0x00000200
993 #define TLBnPS_1M               0x00000400
994 #define TLBnPS_2M               0x00000800
995 #define TLBnPS_4M               0x00001000
996 #define TLBnPS_8M               0x00002000
997 #define TLBnPS_16M              0x00004000
998 #define TLBnPS_32M              0x00008000
999 #define TLBnPS_64M              0x00010000
1000 #define TLBnPS_128M             0x00020000
1001 #define TLBnPS_256M             0x00040000
1002 #define TLBnPS_512M             0x00080000
1003 #define TLBnPS_1G               0x00100000
1004 #define TLBnPS_2G               0x00200000
1005 #define TLBnPS_4G               0x00400000
1006 #define TLBnPS_8G               0x00800000
1007 #define TLBnPS_16G              0x01000000
1008 #define TLBnPS_32G              0x02000000
1009 #define TLBnPS_64G              0x04000000
1010 #define TLBnPS_128G             0x08000000
1011 #define TLBnPS_256G             0x10000000
1012 
1013 /* tlbilx action encoding */
1014 #define TLBILX_T_ALL                    0
1015 #define TLBILX_T_TID                    1
1016 #define TLBILX_T_FULLMATCH              3
1017 #define TLBILX_T_CLASS0                 4
1018 #define TLBILX_T_CLASS1                 5
1019 #define TLBILX_T_CLASS2                 6
1020 #define TLBILX_T_CLASS3                 7
1021 
1022 /* BookE 2.06 helper defines */
1023 
1024 #define BOOKE206_FLUSH_TLB0    (1 << 0)
1025 #define BOOKE206_FLUSH_TLB1    (1 << 1)
1026 #define BOOKE206_FLUSH_TLB2    (1 << 2)
1027 #define BOOKE206_FLUSH_TLB3    (1 << 3)
1028 
1029 /* number of possible TLBs */
1030 #define BOOKE206_MAX_TLBN      4
1031 
1032 #define EPID_EPID_SHIFT 0x0
1033 #define EPID_EPID 0xFF
1034 #define EPID_ELPID_SHIFT 0x10
1035 #define EPID_ELPID 0x3F0000
1036 #define EPID_EGS 0x20000000
1037 #define EPID_EGS_SHIFT 29
1038 #define EPID_EAS 0x40000000
1039 #define EPID_EAS_SHIFT 30
1040 #define EPID_EPR 0x80000000
1041 #define EPID_EPR_SHIFT 31
1042 /* We don't support EGS and ELPID */
1043 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1044 
1045 /*****************************************************************************/
1046 /* Server and Embedded Processor Control */
1047 
1048 #define DBELL_TYPE_SHIFT               27
1049 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
1050 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
1051 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
1052 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
1053 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
1054 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
1055 
1056 #define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
1057 
1058 #define DBELL_BRDCAST                  PPC_BIT(37)
1059 #define DBELL_LPIDTAG_SHIFT            14
1060 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
1061 #define DBELL_PIRTAG_MASK              0x3fff
1062 
1063 #define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
1064 
1065 #define PPC_PAGE_SIZES_MAX_SZ   8
1066 
1067 struct ppc_radix_page_info {
1068     uint32_t count;
1069     uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1070 };
1071 
1072 /*****************************************************************************/
1073 /* The whole PowerPC CPU context */
1074 
1075 /*
1076  * PowerPC needs eight modes for different hypervisor/supervisor/guest
1077  * + real/paged mode combinations. The other two modes are for
1078  * external PID load/store.
1079  */
1080 #define PPC_TLB_EPID_LOAD 8
1081 #define PPC_TLB_EPID_STORE 9
1082 
1083 #define PPC_CPU_OPCODES_LEN          0x40
1084 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1085 
1086 struct CPUPPCState {
1087     /* Most commonly used resources during translated code execution first */
1088     target_ulong gpr[32];  /* general purpose registers */
1089     target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1090     target_ulong lr;
1091     target_ulong ctr;
1092     uint32_t crf[8];       /* condition register */
1093 #if defined(TARGET_PPC64)
1094     target_ulong cfar;
1095 #endif
1096     target_ulong xer;      /* XER (with SO, OV, CA split out) */
1097     target_ulong so;
1098     target_ulong ov;
1099     target_ulong ca;
1100     target_ulong ov32;
1101     target_ulong ca32;
1102 
1103     target_ulong reserve_addr; /* Reservation address */
1104     target_ulong reserve_val;  /* Reservation value */
1105     target_ulong reserve_val2;
1106 
1107     /* These are used in supervisor mode only */
1108     target_ulong msr;      /* machine state register */
1109     target_ulong tgpr[4];  /* temporary general purpose registers, */
1110                            /* used to speed-up TLB assist handlers */
1111 
1112     target_ulong nip;      /* next instruction pointer */
1113     uint64_t retxh;        /* high part of 128-bit helper return */
1114 
1115     /* when a memory exception occurs, the access type is stored here */
1116     int access_type;
1117 
1118 #if !defined(CONFIG_USER_ONLY)
1119     /* MMU context, only relevant for full system emulation */
1120 #if defined(TARGET_PPC64)
1121     ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1122 #endif
1123     target_ulong sr[32];   /* segment registers */
1124     uint32_t nb_BATs;      /* number of BATs */
1125     target_ulong DBAT[2][8];
1126     target_ulong IBAT[2][8];
1127     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1128     int32_t nb_tlb;  /* Total number of TLB */
1129     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1130     int nb_ways;     /* Number of ways in the TLB set */
1131     int last_way;    /* Last used way used to allocate TLB in a LRU way */
1132     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1133     int nb_pids;     /* Number of available PID registers */
1134     int tlb_type;    /* Type of TLB we're dealing with */
1135     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1136     target_ulong pb[4]; /* 403 dedicated access protection registers */
1137     bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1138     bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1139     uint32_t tlb_need_flush; /* Delayed flush needed */
1140 #define TLB_NEED_LOCAL_FLUSH   0x1
1141 #define TLB_NEED_GLOBAL_FLUSH  0x2
1142 #endif
1143 
1144     /* Other registers */
1145     target_ulong spr[1024]; /* special purpose registers */
1146     ppc_spr_t spr_cb[1024];
1147     /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1148     uint8_t pmc_ins_cnt;
1149     uint8_t pmc_cyc_cnt;
1150     /* Vector status and control register, minus VSCR_SAT */
1151     uint32_t vscr;
1152     /* VSX registers (including FP and AVR) */
1153     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1154     /* Non-zero if and only if VSCR_SAT should be set */
1155     ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1156     /* SPE registers */
1157     uint64_t spe_acc;
1158     uint32_t spe_fscr;
1159     /* SPE and Altivec share status as they'll never be used simultaneously */
1160     float_status vec_status;
1161     float_status fp_status; /* Floating point execution context */
1162     target_ulong fpscr;     /* Floating point status and control register */
1163 
1164     /* Internal devices resources */
1165     ppc_tb_t *tb_env;      /* Time base and decrementer */
1166     ppc_dcr_t *dcr_env;    /* Device control registers */
1167 
1168     int dcache_line_size;
1169     int icache_line_size;
1170 
1171     /* These resources are used during exception processing */
1172     /* CPU model definition */
1173     target_ulong msr_mask;
1174     powerpc_mmu_t mmu_model;
1175     powerpc_excp_t excp_model;
1176     powerpc_input_t bus_model;
1177     int bfd_mach;
1178     uint32_t flags;
1179     uint64_t insns_flags;
1180     uint64_t insns_flags2;
1181 
1182     int error_code;
1183     uint32_t pending_interrupts;
1184 #if !defined(CONFIG_USER_ONLY)
1185     /*
1186      * This is the IRQ controller, which is implementation dependent and only
1187      * relevant when emulating a complete machine. Note that this isn't used
1188      * by recent Book3s compatible CPUs (POWER7 and newer).
1189      */
1190     uint32_t irq_input_state;
1191     void **irq_inputs;
1192 
1193     target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1194     target_ulong excp_prefix;
1195     target_ulong ivor_mask;
1196     target_ulong ivpr_mask;
1197     target_ulong hreset_vector;
1198     hwaddr mpic_iack;
1199     bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1200     bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1201                       /* instructions and SPRs are diallowed if MSR:HV is 0 */
1202     /*
1203      * On P7/P8/P9, set when in PM state so we need to handle resume in a
1204      * special way (such as routing some resume causes to 0x100, i.e. sreset).
1205      */
1206     bool resume_as_sreset;
1207 #endif
1208 
1209     /* These resources are used only in TCG */
1210     uint32_t hflags;
1211     target_ulong hflags_compat_nmsr; /* for migration compatibility */
1212 
1213     /* Power management */
1214     int (*check_pow)(CPUPPCState *env);
1215 
1216 #if !defined(CONFIG_USER_ONLY)
1217     void *load_info;  /* holds boot loading state */
1218 #endif
1219 
1220     /* booke timers */
1221 
1222     /*
1223      * Specifies bit locations of the Time Base used to signal a fixed timer
1224      * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1225      *
1226      * 0 selects the least significant bit, 63 selects the most significant bit
1227      */
1228     uint8_t fit_period[4];
1229     uint8_t wdt_period[4];
1230 
1231     /* Transactional memory state */
1232     target_ulong tm_gpr[32];
1233     ppc_avr_t tm_vsr[64];
1234     uint64_t tm_cr;
1235     uint64_t tm_lr;
1236     uint64_t tm_ctr;
1237     uint64_t tm_fpscr;
1238     uint64_t tm_amr;
1239     uint64_t tm_ppr;
1240     uint64_t tm_vrsave;
1241     uint32_t tm_vscr;
1242     uint64_t tm_dscr;
1243     uint64_t tm_tar;
1244 
1245     /*
1246      * Timers used to fire performance monitor alerts
1247      * when counting cycles.
1248      */
1249     QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1250 
1251     /*
1252      * PMU base time value used by the PMU to calculate
1253      * running cycles.
1254      */
1255     uint64_t pmu_base_time;
1256 };
1257 
1258 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1259 do {                                            \
1260     env->fit_period[0] = (a_);                  \
1261     env->fit_period[1] = (b_);                  \
1262     env->fit_period[2] = (c_);                  \
1263     env->fit_period[3] = (d_);                  \
1264  } while (0)
1265 
1266 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1267 do {                                            \
1268     env->wdt_period[0] = (a_);                  \
1269     env->wdt_period[1] = (b_);                  \
1270     env->wdt_period[2] = (c_);                  \
1271     env->wdt_period[3] = (d_);                  \
1272  } while (0)
1273 
1274 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1275 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1276 
1277 /**
1278  * PowerPCCPU:
1279  * @env: #CPUPPCState
1280  * @vcpu_id: vCPU identifier given to KVM
1281  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1282  *
1283  * A PowerPC CPU.
1284  */
1285 struct PowerPCCPU {
1286     /*< private >*/
1287     CPUState parent_obj;
1288     /*< public >*/
1289 
1290     CPUNegativeOffsetState neg;
1291     CPUPPCState env;
1292 
1293     int vcpu_id;
1294     uint32_t compat_pvr;
1295     PPCVirtualHypervisor *vhyp;
1296     void *machine_data;
1297     int32_t node_id; /* NUMA node this CPU belongs to */
1298     PPCHash64Options *hash64_opts;
1299 
1300     /* Those resources are used only during code translation */
1301     /* opcode handlers */
1302     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1303 
1304     /* Fields related to migration compatibility hacks */
1305     bool pre_2_8_migration;
1306     target_ulong mig_msr_mask;
1307     uint64_t mig_insns_flags;
1308     uint64_t mig_insns_flags2;
1309     uint32_t mig_nb_BATs;
1310     bool pre_2_10_migration;
1311     bool pre_3_0_migration;
1312     int32_t mig_slb_nr;
1313 };
1314 
1315 
1316 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1317 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1318 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1319 
1320 #ifndef CONFIG_USER_ONLY
1321 struct PPCVirtualHypervisorClass {
1322     InterfaceClass parent;
1323     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1324     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1325     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1326                                          hwaddr ptex, int n);
1327     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1328                         const ppc_hash_pte64_t *hptes,
1329                         hwaddr ptex, int n);
1330     void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1331     void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1332     void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1333     target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1334     void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1335     void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1336 };
1337 
1338 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1339 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1340                      PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1341 #endif /* CONFIG_USER_ONLY */
1342 
1343 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1344 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1345 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1346 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1347 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1348 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1349 #ifndef CONFIG_USER_ONLY
1350 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1351 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1352 #endif
1353 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1354                                int cpuid, void *opaque);
1355 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1356                                int cpuid, void *opaque);
1357 #ifndef CONFIG_USER_ONLY
1358 void ppc_cpu_do_interrupt(CPUState *cpu);
1359 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1360 void ppc_cpu_do_system_reset(CPUState *cs);
1361 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1362 extern const VMStateDescription vmstate_ppc_cpu;
1363 #endif
1364 
1365 /*****************************************************************************/
1366 void ppc_translate_init(void);
1367 
1368 #if !defined(CONFIG_USER_ONLY)
1369 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1370 #endif /* !defined(CONFIG_USER_ONLY) */
1371 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1372 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1373 
1374 void ppc_cpu_list(void);
1375 
1376 /* Time-base and decrementer management */
1377 #ifndef NO_CPU_IO_DEFS
1378 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1379 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1380 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1381 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1382 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1383 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1384 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1385 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1386 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1387 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1388 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1389 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1390 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1391 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1392 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1393 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1394 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1395 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1396 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1397 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1398 #if !defined(CONFIG_USER_ONLY)
1399 void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1400 void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1401 target_ulong load_40x_pit(CPUPPCState *env);
1402 void store_40x_pit(CPUPPCState *env, target_ulong val);
1403 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1404 void store_40x_sler(CPUPPCState *env, uint32_t val);
1405 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1406 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1407 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1408 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1409 void ppc_tlb_invalidate_all(CPUPPCState *env);
1410 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1411 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1412 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1413                             hwaddr *raddrp, target_ulong address,
1414                             uint32_t pid);
1415 int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
1416                             hwaddr *raddrp,
1417                             target_ulong address, uint32_t pid, int ext,
1418                             int i);
1419 hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
1420                                         ppcmas_tlb_t *tlb);
1421 #endif
1422 #endif
1423 
1424 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1425 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1426                                  const char *caller, uint32_t cause);
1427 
1428 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1429 {
1430     uint64_t gprv;
1431 
1432     gprv = env->gpr[gprn];
1433     if (env->flags & POWERPC_FLAG_SPE) {
1434         /*
1435          * If the CPU implements the SPE extension, we have to get the
1436          * high bits of the GPR from the gprh storage area
1437          */
1438         gprv &= 0xFFFFFFFFULL;
1439         gprv |= (uint64_t)env->gprh[gprn] << 32;
1440     }
1441 
1442     return gprv;
1443 }
1444 
1445 /* Device control registers */
1446 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1447 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1448 
1449 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1450 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1451 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1452 
1453 #define cpu_list ppc_cpu_list
1454 
1455 /* MMU modes definitions */
1456 #define MMU_USER_IDX 0
1457 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1458 {
1459 #ifdef CONFIG_USER_ONLY
1460     return MMU_USER_IDX;
1461 #else
1462     return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1463 #endif
1464 }
1465 
1466 /* Compatibility modes */
1467 #if defined(TARGET_PPC64)
1468 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1469                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1470 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1471                            uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1472 
1473 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1474 
1475 #if !defined(CONFIG_USER_ONLY)
1476 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1477 #endif
1478 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1479 void ppc_compat_add_property(Object *obj, const char *name,
1480                              uint32_t *compat_pvr, const char *basedesc);
1481 #endif /* defined(TARGET_PPC64) */
1482 
1483 typedef CPUPPCState CPUArchState;
1484 typedef PowerPCCPU ArchCPU;
1485 
1486 #include "exec/cpu-all.h"
1487 
1488 /*****************************************************************************/
1489 /* CRF definitions */
1490 #define CRF_LT_BIT    3
1491 #define CRF_GT_BIT    2
1492 #define CRF_EQ_BIT    1
1493 #define CRF_SO_BIT    0
1494 #define CRF_LT        (1 << CRF_LT_BIT)
1495 #define CRF_GT        (1 << CRF_GT_BIT)
1496 #define CRF_EQ        (1 << CRF_EQ_BIT)
1497 #define CRF_SO        (1 << CRF_SO_BIT)
1498 /* For SPE extensions */
1499 #define CRF_CH        (1 << CRF_LT_BIT)
1500 #define CRF_CL        (1 << CRF_GT_BIT)
1501 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1502 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1503 
1504 /* XER definitions */
1505 #define XER_SO  31
1506 #define XER_OV  30
1507 #define XER_CA  29
1508 #define XER_OV32  19
1509 #define XER_CA32  18
1510 #define XER_CMP  8
1511 #define XER_BC   0
1512 #define xer_so  (env->so)
1513 #define xer_ov  (env->ov)
1514 #define xer_ca  (env->ca)
1515 #define xer_ov32  (env->ov)
1516 #define xer_ca32  (env->ca)
1517 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1518 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1519 
1520 /* SPR definitions */
1521 #define SPR_MQ                (0x000)
1522 #define SPR_XER               (0x001)
1523 #define SPR_601_VRTCU         (0x004)
1524 #define SPR_601_VRTCL         (0x005)
1525 #define SPR_601_UDECR         (0x006)
1526 #define SPR_LR                (0x008)
1527 #define SPR_CTR               (0x009)
1528 #define SPR_UAMR              (0x00D)
1529 #define SPR_DSCR              (0x011)
1530 #define SPR_DSISR             (0x012)
1531 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1532 #define SPR_601_RTCU          (0x014)
1533 #define SPR_601_RTCL          (0x015)
1534 #define SPR_DECR              (0x016)
1535 #define SPR_SDR1              (0x019)
1536 #define SPR_SRR0              (0x01A)
1537 #define SPR_SRR1              (0x01B)
1538 #define SPR_CFAR              (0x01C)
1539 #define SPR_AMR               (0x01D)
1540 #define SPR_ACOP              (0x01F)
1541 #define SPR_BOOKE_PID         (0x030)
1542 #define SPR_BOOKS_PID         (0x030)
1543 #define SPR_BOOKE_DECAR       (0x036)
1544 #define SPR_BOOKE_CSRR0       (0x03A)
1545 #define SPR_BOOKE_CSRR1       (0x03B)
1546 #define SPR_BOOKE_DEAR        (0x03D)
1547 #define SPR_IAMR              (0x03D)
1548 #define SPR_BOOKE_ESR         (0x03E)
1549 #define SPR_BOOKE_IVPR        (0x03F)
1550 #define SPR_MPC_EIE           (0x050)
1551 #define SPR_MPC_EID           (0x051)
1552 #define SPR_MPC_NRI           (0x052)
1553 #define SPR_TFHAR             (0x080)
1554 #define SPR_TFIAR             (0x081)
1555 #define SPR_TEXASR            (0x082)
1556 #define SPR_TEXASRU           (0x083)
1557 #define SPR_UCTRL             (0x088)
1558 #define SPR_TIDR              (0x090)
1559 #define SPR_MPC_CMPA          (0x090)
1560 #define SPR_MPC_CMPB          (0x091)
1561 #define SPR_MPC_CMPC          (0x092)
1562 #define SPR_MPC_CMPD          (0x093)
1563 #define SPR_MPC_ECR           (0x094)
1564 #define SPR_MPC_DER           (0x095)
1565 #define SPR_MPC_COUNTA        (0x096)
1566 #define SPR_MPC_COUNTB        (0x097)
1567 #define SPR_CTRL              (0x098)
1568 #define SPR_MPC_CMPE          (0x098)
1569 #define SPR_MPC_CMPF          (0x099)
1570 #define SPR_FSCR              (0x099)
1571 #define SPR_MPC_CMPG          (0x09A)
1572 #define SPR_MPC_CMPH          (0x09B)
1573 #define SPR_MPC_LCTRL1        (0x09C)
1574 #define SPR_MPC_LCTRL2        (0x09D)
1575 #define SPR_UAMOR             (0x09D)
1576 #define SPR_MPC_ICTRL         (0x09E)
1577 #define SPR_MPC_BAR           (0x09F)
1578 #define SPR_PSPB              (0x09F)
1579 #define SPR_DPDES             (0x0B0)
1580 #define SPR_DAWR0             (0x0B4)
1581 #define SPR_RPR               (0x0BA)
1582 #define SPR_CIABR             (0x0BB)
1583 #define SPR_DAWRX0            (0x0BC)
1584 #define SPR_HFSCR             (0x0BE)
1585 #define SPR_VRSAVE            (0x100)
1586 #define SPR_USPRG0            (0x100)
1587 #define SPR_USPRG1            (0x101)
1588 #define SPR_USPRG2            (0x102)
1589 #define SPR_USPRG3            (0x103)
1590 #define SPR_USPRG4            (0x104)
1591 #define SPR_USPRG5            (0x105)
1592 #define SPR_USPRG6            (0x106)
1593 #define SPR_USPRG7            (0x107)
1594 #define SPR_VTBL              (0x10C)
1595 #define SPR_VTBU              (0x10D)
1596 #define SPR_SPRG0             (0x110)
1597 #define SPR_SPRG1             (0x111)
1598 #define SPR_SPRG2             (0x112)
1599 #define SPR_SPRG3             (0x113)
1600 #define SPR_SPRG4             (0x114)
1601 #define SPR_SCOMC             (0x114)
1602 #define SPR_SPRG5             (0x115)
1603 #define SPR_SCOMD             (0x115)
1604 #define SPR_SPRG6             (0x116)
1605 #define SPR_SPRG7             (0x117)
1606 #define SPR_ASR               (0x118)
1607 #define SPR_EAR               (0x11A)
1608 #define SPR_TBL               (0x11C)
1609 #define SPR_TBU               (0x11D)
1610 #define SPR_TBU40             (0x11E)
1611 #define SPR_SVR               (0x11E)
1612 #define SPR_BOOKE_PIR         (0x11E)
1613 #define SPR_PVR               (0x11F)
1614 #define SPR_HSPRG0            (0x130)
1615 #define SPR_BOOKE_DBSR        (0x130)
1616 #define SPR_HSPRG1            (0x131)
1617 #define SPR_HDSISR            (0x132)
1618 #define SPR_HDAR              (0x133)
1619 #define SPR_BOOKE_EPCR        (0x133)
1620 #define SPR_SPURR             (0x134)
1621 #define SPR_BOOKE_DBCR0       (0x134)
1622 #define SPR_IBCR              (0x135)
1623 #define SPR_PURR              (0x135)
1624 #define SPR_BOOKE_DBCR1       (0x135)
1625 #define SPR_DBCR              (0x136)
1626 #define SPR_HDEC              (0x136)
1627 #define SPR_BOOKE_DBCR2       (0x136)
1628 #define SPR_HIOR              (0x137)
1629 #define SPR_MBAR              (0x137)
1630 #define SPR_RMOR              (0x138)
1631 #define SPR_BOOKE_IAC1        (0x138)
1632 #define SPR_HRMOR             (0x139)
1633 #define SPR_BOOKE_IAC2        (0x139)
1634 #define SPR_HSRR0             (0x13A)
1635 #define SPR_BOOKE_IAC3        (0x13A)
1636 #define SPR_HSRR1             (0x13B)
1637 #define SPR_BOOKE_IAC4        (0x13B)
1638 #define SPR_BOOKE_DAC1        (0x13C)
1639 #define SPR_MMCRH             (0x13C)
1640 #define SPR_DABR2             (0x13D)
1641 #define SPR_BOOKE_DAC2        (0x13D)
1642 #define SPR_TFMR              (0x13D)
1643 #define SPR_BOOKE_DVC1        (0x13E)
1644 #define SPR_LPCR              (0x13E)
1645 #define SPR_BOOKE_DVC2        (0x13F)
1646 #define SPR_LPIDR             (0x13F)
1647 #define SPR_BOOKE_TSR         (0x150)
1648 #define SPR_HMER              (0x150)
1649 #define SPR_HMEER             (0x151)
1650 #define SPR_PCR               (0x152)
1651 #define SPR_BOOKE_LPIDR       (0x152)
1652 #define SPR_BOOKE_TCR         (0x154)
1653 #define SPR_BOOKE_TLB0PS      (0x158)
1654 #define SPR_BOOKE_TLB1PS      (0x159)
1655 #define SPR_BOOKE_TLB2PS      (0x15A)
1656 #define SPR_BOOKE_TLB3PS      (0x15B)
1657 #define SPR_AMOR              (0x15D)
1658 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1659 #define SPR_BOOKE_IVOR0       (0x190)
1660 #define SPR_BOOKE_IVOR1       (0x191)
1661 #define SPR_BOOKE_IVOR2       (0x192)
1662 #define SPR_BOOKE_IVOR3       (0x193)
1663 #define SPR_BOOKE_IVOR4       (0x194)
1664 #define SPR_BOOKE_IVOR5       (0x195)
1665 #define SPR_BOOKE_IVOR6       (0x196)
1666 #define SPR_BOOKE_IVOR7       (0x197)
1667 #define SPR_BOOKE_IVOR8       (0x198)
1668 #define SPR_BOOKE_IVOR9       (0x199)
1669 #define SPR_BOOKE_IVOR10      (0x19A)
1670 #define SPR_BOOKE_IVOR11      (0x19B)
1671 #define SPR_BOOKE_IVOR12      (0x19C)
1672 #define SPR_BOOKE_IVOR13      (0x19D)
1673 #define SPR_BOOKE_IVOR14      (0x19E)
1674 #define SPR_BOOKE_IVOR15      (0x19F)
1675 #define SPR_BOOKE_IVOR38      (0x1B0)
1676 #define SPR_BOOKE_IVOR39      (0x1B1)
1677 #define SPR_BOOKE_IVOR40      (0x1B2)
1678 #define SPR_BOOKE_IVOR41      (0x1B3)
1679 #define SPR_BOOKE_IVOR42      (0x1B4)
1680 #define SPR_BOOKE_GIVOR2      (0x1B8)
1681 #define SPR_BOOKE_GIVOR3      (0x1B9)
1682 #define SPR_BOOKE_GIVOR4      (0x1BA)
1683 #define SPR_BOOKE_GIVOR8      (0x1BB)
1684 #define SPR_BOOKE_GIVOR13     (0x1BC)
1685 #define SPR_BOOKE_GIVOR14     (0x1BD)
1686 #define SPR_TIR               (0x1BE)
1687 #define SPR_PTCR              (0x1D0)
1688 #define SPR_BOOKE_SPEFSCR     (0x200)
1689 #define SPR_Exxx_BBEAR        (0x201)
1690 #define SPR_Exxx_BBTAR        (0x202)
1691 #define SPR_Exxx_L1CFG0       (0x203)
1692 #define SPR_Exxx_L1CFG1       (0x204)
1693 #define SPR_Exxx_NPIDR        (0x205)
1694 #define SPR_ATBL              (0x20E)
1695 #define SPR_ATBU              (0x20F)
1696 #define SPR_IBAT0U            (0x210)
1697 #define SPR_BOOKE_IVOR32      (0x210)
1698 #define SPR_RCPU_MI_GRA       (0x210)
1699 #define SPR_IBAT0L            (0x211)
1700 #define SPR_BOOKE_IVOR33      (0x211)
1701 #define SPR_IBAT1U            (0x212)
1702 #define SPR_BOOKE_IVOR34      (0x212)
1703 #define SPR_IBAT1L            (0x213)
1704 #define SPR_BOOKE_IVOR35      (0x213)
1705 #define SPR_IBAT2U            (0x214)
1706 #define SPR_BOOKE_IVOR36      (0x214)
1707 #define SPR_IBAT2L            (0x215)
1708 #define SPR_BOOKE_IVOR37      (0x215)
1709 #define SPR_IBAT3U            (0x216)
1710 #define SPR_IBAT3L            (0x217)
1711 #define SPR_DBAT0U            (0x218)
1712 #define SPR_RCPU_L2U_GRA      (0x218)
1713 #define SPR_DBAT0L            (0x219)
1714 #define SPR_DBAT1U            (0x21A)
1715 #define SPR_DBAT1L            (0x21B)
1716 #define SPR_DBAT2U            (0x21C)
1717 #define SPR_DBAT2L            (0x21D)
1718 #define SPR_DBAT3U            (0x21E)
1719 #define SPR_DBAT3L            (0x21F)
1720 #define SPR_IBAT4U            (0x230)
1721 #define SPR_RPCU_BBCMCR       (0x230)
1722 #define SPR_MPC_IC_CST        (0x230)
1723 #define SPR_Exxx_CTXCR        (0x230)
1724 #define SPR_IBAT4L            (0x231)
1725 #define SPR_MPC_IC_ADR        (0x231)
1726 #define SPR_Exxx_DBCR3        (0x231)
1727 #define SPR_IBAT5U            (0x232)
1728 #define SPR_MPC_IC_DAT        (0x232)
1729 #define SPR_Exxx_DBCNT        (0x232)
1730 #define SPR_IBAT5L            (0x233)
1731 #define SPR_IBAT6U            (0x234)
1732 #define SPR_IBAT6L            (0x235)
1733 #define SPR_IBAT7U            (0x236)
1734 #define SPR_IBAT7L            (0x237)
1735 #define SPR_DBAT4U            (0x238)
1736 #define SPR_RCPU_L2U_MCR      (0x238)
1737 #define SPR_MPC_DC_CST        (0x238)
1738 #define SPR_Exxx_ALTCTXCR     (0x238)
1739 #define SPR_DBAT4L            (0x239)
1740 #define SPR_MPC_DC_ADR        (0x239)
1741 #define SPR_DBAT5U            (0x23A)
1742 #define SPR_BOOKE_MCSRR0      (0x23A)
1743 #define SPR_MPC_DC_DAT        (0x23A)
1744 #define SPR_DBAT5L            (0x23B)
1745 #define SPR_BOOKE_MCSRR1      (0x23B)
1746 #define SPR_DBAT6U            (0x23C)
1747 #define SPR_BOOKE_MCSR        (0x23C)
1748 #define SPR_DBAT6L            (0x23D)
1749 #define SPR_Exxx_MCAR         (0x23D)
1750 #define SPR_DBAT7U            (0x23E)
1751 #define SPR_BOOKE_DSRR0       (0x23E)
1752 #define SPR_DBAT7L            (0x23F)
1753 #define SPR_BOOKE_DSRR1       (0x23F)
1754 #define SPR_BOOKE_SPRG8       (0x25C)
1755 #define SPR_BOOKE_SPRG9       (0x25D)
1756 #define SPR_BOOKE_MAS0        (0x270)
1757 #define SPR_BOOKE_MAS1        (0x271)
1758 #define SPR_BOOKE_MAS2        (0x272)
1759 #define SPR_BOOKE_MAS3        (0x273)
1760 #define SPR_BOOKE_MAS4        (0x274)
1761 #define SPR_BOOKE_MAS5        (0x275)
1762 #define SPR_BOOKE_MAS6        (0x276)
1763 #define SPR_BOOKE_PID1        (0x279)
1764 #define SPR_BOOKE_PID2        (0x27A)
1765 #define SPR_MPC_DPDR          (0x280)
1766 #define SPR_MPC_IMMR          (0x288)
1767 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1768 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1769 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1770 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1771 #define SPR_BOOKE_EPR         (0x2BE)
1772 #define SPR_PERF0             (0x300)
1773 #define SPR_RCPU_MI_RBA0      (0x300)
1774 #define SPR_MPC_MI_CTR        (0x300)
1775 #define SPR_POWER_USIER       (0x300)
1776 #define SPR_PERF1             (0x301)
1777 #define SPR_RCPU_MI_RBA1      (0x301)
1778 #define SPR_POWER_UMMCR2      (0x301)
1779 #define SPR_PERF2             (0x302)
1780 #define SPR_RCPU_MI_RBA2      (0x302)
1781 #define SPR_MPC_MI_AP         (0x302)
1782 #define SPR_POWER_UMMCRA      (0x302)
1783 #define SPR_PERF3             (0x303)
1784 #define SPR_RCPU_MI_RBA3      (0x303)
1785 #define SPR_MPC_MI_EPN        (0x303)
1786 #define SPR_POWER_UPMC1       (0x303)
1787 #define SPR_PERF4             (0x304)
1788 #define SPR_POWER_UPMC2       (0x304)
1789 #define SPR_PERF5             (0x305)
1790 #define SPR_MPC_MI_TWC        (0x305)
1791 #define SPR_POWER_UPMC3       (0x305)
1792 #define SPR_PERF6             (0x306)
1793 #define SPR_MPC_MI_RPN        (0x306)
1794 #define SPR_POWER_UPMC4       (0x306)
1795 #define SPR_PERF7             (0x307)
1796 #define SPR_POWER_UPMC5       (0x307)
1797 #define SPR_PERF8             (0x308)
1798 #define SPR_RCPU_L2U_RBA0     (0x308)
1799 #define SPR_MPC_MD_CTR        (0x308)
1800 #define SPR_POWER_UPMC6       (0x308)
1801 #define SPR_PERF9             (0x309)
1802 #define SPR_RCPU_L2U_RBA1     (0x309)
1803 #define SPR_MPC_MD_CASID      (0x309)
1804 #define SPR_970_UPMC7         (0X309)
1805 #define SPR_PERFA             (0x30A)
1806 #define SPR_RCPU_L2U_RBA2     (0x30A)
1807 #define SPR_MPC_MD_AP         (0x30A)
1808 #define SPR_970_UPMC8         (0X30A)
1809 #define SPR_PERFB             (0x30B)
1810 #define SPR_RCPU_L2U_RBA3     (0x30B)
1811 #define SPR_MPC_MD_EPN        (0x30B)
1812 #define SPR_POWER_UMMCR0      (0X30B)
1813 #define SPR_PERFC             (0x30C)
1814 #define SPR_MPC_MD_TWB        (0x30C)
1815 #define SPR_POWER_USIAR       (0X30C)
1816 #define SPR_PERFD             (0x30D)
1817 #define SPR_MPC_MD_TWC        (0x30D)
1818 #define SPR_POWER_USDAR       (0X30D)
1819 #define SPR_PERFE             (0x30E)
1820 #define SPR_MPC_MD_RPN        (0x30E)
1821 #define SPR_POWER_UMMCR1      (0X30E)
1822 #define SPR_PERFF             (0x30F)
1823 #define SPR_MPC_MD_TW         (0x30F)
1824 #define SPR_UPERF0            (0x310)
1825 #define SPR_POWER_SIER        (0x310)
1826 #define SPR_UPERF1            (0x311)
1827 #define SPR_POWER_MMCR2       (0x311)
1828 #define SPR_UPERF2            (0x312)
1829 #define SPR_POWER_MMCRA       (0X312)
1830 #define SPR_UPERF3            (0x313)
1831 #define SPR_POWER_PMC1        (0X313)
1832 #define SPR_UPERF4            (0x314)
1833 #define SPR_POWER_PMC2        (0X314)
1834 #define SPR_UPERF5            (0x315)
1835 #define SPR_POWER_PMC3        (0X315)
1836 #define SPR_UPERF6            (0x316)
1837 #define SPR_POWER_PMC4        (0X316)
1838 #define SPR_UPERF7            (0x317)
1839 #define SPR_POWER_PMC5        (0X317)
1840 #define SPR_UPERF8            (0x318)
1841 #define SPR_POWER_PMC6        (0X318)
1842 #define SPR_UPERF9            (0x319)
1843 #define SPR_970_PMC7          (0X319)
1844 #define SPR_UPERFA            (0x31A)
1845 #define SPR_970_PMC8          (0X31A)
1846 #define SPR_UPERFB            (0x31B)
1847 #define SPR_POWER_MMCR0       (0X31B)
1848 #define SPR_UPERFC            (0x31C)
1849 #define SPR_POWER_SIAR        (0X31C)
1850 #define SPR_UPERFD            (0x31D)
1851 #define SPR_POWER_SDAR        (0X31D)
1852 #define SPR_UPERFE            (0x31E)
1853 #define SPR_POWER_MMCR1       (0X31E)
1854 #define SPR_UPERFF            (0x31F)
1855 #define SPR_RCPU_MI_RA0       (0x320)
1856 #define SPR_MPC_MI_DBCAM      (0x320)
1857 #define SPR_BESCRS            (0x320)
1858 #define SPR_RCPU_MI_RA1       (0x321)
1859 #define SPR_MPC_MI_DBRAM0     (0x321)
1860 #define SPR_BESCRSU           (0x321)
1861 #define SPR_RCPU_MI_RA2       (0x322)
1862 #define SPR_MPC_MI_DBRAM1     (0x322)
1863 #define SPR_BESCRR            (0x322)
1864 #define SPR_RCPU_MI_RA3       (0x323)
1865 #define SPR_BESCRRU           (0x323)
1866 #define SPR_EBBHR             (0x324)
1867 #define SPR_EBBRR             (0x325)
1868 #define SPR_BESCR             (0x326)
1869 #define SPR_RCPU_L2U_RA0      (0x328)
1870 #define SPR_MPC_MD_DBCAM      (0x328)
1871 #define SPR_RCPU_L2U_RA1      (0x329)
1872 #define SPR_MPC_MD_DBRAM0     (0x329)
1873 #define SPR_RCPU_L2U_RA2      (0x32A)
1874 #define SPR_MPC_MD_DBRAM1     (0x32A)
1875 #define SPR_RCPU_L2U_RA3      (0x32B)
1876 #define SPR_TAR               (0x32F)
1877 #define SPR_ASDR              (0x330)
1878 #define SPR_IC                (0x350)
1879 #define SPR_VTB               (0x351)
1880 #define SPR_MMCRC             (0x353)
1881 #define SPR_PSSCR             (0x357)
1882 #define SPR_440_INV0          (0x370)
1883 #define SPR_440_INV1          (0x371)
1884 #define SPR_440_INV2          (0x372)
1885 #define SPR_440_INV3          (0x373)
1886 #define SPR_440_ITV0          (0x374)
1887 #define SPR_440_ITV1          (0x375)
1888 #define SPR_440_ITV2          (0x376)
1889 #define SPR_440_ITV3          (0x377)
1890 #define SPR_440_CCR1          (0x378)
1891 #define SPR_TACR              (0x378)
1892 #define SPR_TCSCR             (0x379)
1893 #define SPR_CSIGR             (0x37a)
1894 #define SPR_DCRIPR            (0x37B)
1895 #define SPR_POWER_SPMC1       (0x37C)
1896 #define SPR_POWER_SPMC2       (0x37D)
1897 #define SPR_POWER_MMCRS       (0x37E)
1898 #define SPR_WORT              (0x37F)
1899 #define SPR_PPR               (0x380)
1900 #define SPR_750_GQR0          (0x390)
1901 #define SPR_440_DNV0          (0x390)
1902 #define SPR_750_GQR1          (0x391)
1903 #define SPR_440_DNV1          (0x391)
1904 #define SPR_750_GQR2          (0x392)
1905 #define SPR_440_DNV2          (0x392)
1906 #define SPR_750_GQR3          (0x393)
1907 #define SPR_440_DNV3          (0x393)
1908 #define SPR_750_GQR4          (0x394)
1909 #define SPR_440_DTV0          (0x394)
1910 #define SPR_750_GQR5          (0x395)
1911 #define SPR_440_DTV1          (0x395)
1912 #define SPR_750_GQR6          (0x396)
1913 #define SPR_440_DTV2          (0x396)
1914 #define SPR_750_GQR7          (0x397)
1915 #define SPR_440_DTV3          (0x397)
1916 #define SPR_750_THRM4         (0x398)
1917 #define SPR_750CL_HID2        (0x398)
1918 #define SPR_440_DVLIM         (0x398)
1919 #define SPR_750_WPAR          (0x399)
1920 #define SPR_440_IVLIM         (0x399)
1921 #define SPR_TSCR              (0x399)
1922 #define SPR_750_DMAU          (0x39A)
1923 #define SPR_750_DMAL          (0x39B)
1924 #define SPR_440_RSTCFG        (0x39B)
1925 #define SPR_BOOKE_DCDBTRL     (0x39C)
1926 #define SPR_BOOKE_DCDBTRH     (0x39D)
1927 #define SPR_BOOKE_ICDBTRL     (0x39E)
1928 #define SPR_BOOKE_ICDBTRH     (0x39F)
1929 #define SPR_74XX_UMMCR2       (0x3A0)
1930 #define SPR_7XX_UPMC5         (0x3A1)
1931 #define SPR_7XX_UPMC6         (0x3A2)
1932 #define SPR_UBAMR             (0x3A7)
1933 #define SPR_7XX_UMMCR0        (0x3A8)
1934 #define SPR_7XX_UPMC1         (0x3A9)
1935 #define SPR_7XX_UPMC2         (0x3AA)
1936 #define SPR_7XX_USIAR         (0x3AB)
1937 #define SPR_7XX_UMMCR1        (0x3AC)
1938 #define SPR_7XX_UPMC3         (0x3AD)
1939 #define SPR_7XX_UPMC4         (0x3AE)
1940 #define SPR_USDA              (0x3AF)
1941 #define SPR_40x_ZPR           (0x3B0)
1942 #define SPR_BOOKE_MAS7        (0x3B0)
1943 #define SPR_74XX_MMCR2        (0x3B0)
1944 #define SPR_7XX_PMC5          (0x3B1)
1945 #define SPR_40x_PID           (0x3B1)
1946 #define SPR_7XX_PMC6          (0x3B2)
1947 #define SPR_440_MMUCR         (0x3B2)
1948 #define SPR_4xx_CCR0          (0x3B3)
1949 #define SPR_BOOKE_EPLC        (0x3B3)
1950 #define SPR_405_IAC3          (0x3B4)
1951 #define SPR_BOOKE_EPSC        (0x3B4)
1952 #define SPR_405_IAC4          (0x3B5)
1953 #define SPR_405_DVC1          (0x3B6)
1954 #define SPR_405_DVC2          (0x3B7)
1955 #define SPR_BAMR              (0x3B7)
1956 #define SPR_7XX_MMCR0         (0x3B8)
1957 #define SPR_7XX_PMC1          (0x3B9)
1958 #define SPR_40x_SGR           (0x3B9)
1959 #define SPR_7XX_PMC2          (0x3BA)
1960 #define SPR_40x_DCWR          (0x3BA)
1961 #define SPR_7XX_SIAR          (0x3BB)
1962 #define SPR_405_SLER          (0x3BB)
1963 #define SPR_7XX_MMCR1         (0x3BC)
1964 #define SPR_405_SU0R          (0x3BC)
1965 #define SPR_401_SKR           (0x3BC)
1966 #define SPR_7XX_PMC3          (0x3BD)
1967 #define SPR_405_DBCR1         (0x3BD)
1968 #define SPR_7XX_PMC4          (0x3BE)
1969 #define SPR_SDA               (0x3BF)
1970 #define SPR_403_VTBL          (0x3CC)
1971 #define SPR_403_VTBU          (0x3CD)
1972 #define SPR_DMISS             (0x3D0)
1973 #define SPR_DCMP              (0x3D1)
1974 #define SPR_HASH1             (0x3D2)
1975 #define SPR_HASH2             (0x3D3)
1976 #define SPR_BOOKE_ICDBDR      (0x3D3)
1977 #define SPR_TLBMISS           (0x3D4)
1978 #define SPR_IMISS             (0x3D4)
1979 #define SPR_40x_ESR           (0x3D4)
1980 #define SPR_PTEHI             (0x3D5)
1981 #define SPR_ICMP              (0x3D5)
1982 #define SPR_40x_DEAR          (0x3D5)
1983 #define SPR_PTELO             (0x3D6)
1984 #define SPR_RPA               (0x3D6)
1985 #define SPR_40x_EVPR          (0x3D6)
1986 #define SPR_L3PM              (0x3D7)
1987 #define SPR_403_CDBCR         (0x3D7)
1988 #define SPR_L3ITCR0           (0x3D8)
1989 #define SPR_TCR               (0x3D8)
1990 #define SPR_40x_TSR           (0x3D8)
1991 #define SPR_IBR               (0x3DA)
1992 #define SPR_40x_TCR           (0x3DA)
1993 #define SPR_ESASRR            (0x3DB)
1994 #define SPR_40x_PIT           (0x3DB)
1995 #define SPR_403_TBL           (0x3DC)
1996 #define SPR_403_TBU           (0x3DD)
1997 #define SPR_SEBR              (0x3DE)
1998 #define SPR_40x_SRR2          (0x3DE)
1999 #define SPR_SER               (0x3DF)
2000 #define SPR_40x_SRR3          (0x3DF)
2001 #define SPR_L3OHCR            (0x3E8)
2002 #define SPR_L3ITCR1           (0x3E9)
2003 #define SPR_L3ITCR2           (0x3EA)
2004 #define SPR_L3ITCR3           (0x3EB)
2005 #define SPR_HID0              (0x3F0)
2006 #define SPR_40x_DBSR          (0x3F0)
2007 #define SPR_HID1              (0x3F1)
2008 #define SPR_IABR              (0x3F2)
2009 #define SPR_40x_DBCR0         (0x3F2)
2010 #define SPR_601_HID2          (0x3F2)
2011 #define SPR_Exxx_L1CSR0       (0x3F2)
2012 #define SPR_ICTRL             (0x3F3)
2013 #define SPR_HID2              (0x3F3)
2014 #define SPR_750CL_HID4        (0x3F3)
2015 #define SPR_Exxx_L1CSR1       (0x3F3)
2016 #define SPR_440_DBDR          (0x3F3)
2017 #define SPR_LDSTDB            (0x3F4)
2018 #define SPR_750_TDCL          (0x3F4)
2019 #define SPR_40x_IAC1          (0x3F4)
2020 #define SPR_MMUCSR0           (0x3F4)
2021 #define SPR_970_HID4          (0x3F4)
2022 #define SPR_DABR              (0x3F5)
2023 #define DABR_MASK (~(target_ulong)0x7)
2024 #define SPR_Exxx_BUCSR        (0x3F5)
2025 #define SPR_40x_IAC2          (0x3F5)
2026 #define SPR_601_HID5          (0x3F5)
2027 #define SPR_40x_DAC1          (0x3F6)
2028 #define SPR_MSSCR0            (0x3F6)
2029 #define SPR_970_HID5          (0x3F6)
2030 #define SPR_MSSSR0            (0x3F7)
2031 #define SPR_MSSCR1            (0x3F7)
2032 #define SPR_DABRX             (0x3F7)
2033 #define SPR_40x_DAC2          (0x3F7)
2034 #define SPR_MMUCFG            (0x3F7)
2035 #define SPR_LDSTCR            (0x3F8)
2036 #define SPR_L2PMCR            (0x3F8)
2037 #define SPR_750FX_HID2        (0x3F8)
2038 #define SPR_Exxx_L1FINV0      (0x3F8)
2039 #define SPR_L2CR              (0x3F9)
2040 #define SPR_Exxx_L2CSR0       (0x3F9)
2041 #define SPR_L3CR              (0x3FA)
2042 #define SPR_750_TDCH          (0x3FA)
2043 #define SPR_IABR2             (0x3FA)
2044 #define SPR_40x_DCCR          (0x3FA)
2045 #define SPR_ICTC              (0x3FB)
2046 #define SPR_40x_ICCR          (0x3FB)
2047 #define SPR_THRM1             (0x3FC)
2048 #define SPR_403_PBL1          (0x3FC)
2049 #define SPR_SP                (0x3FD)
2050 #define SPR_THRM2             (0x3FD)
2051 #define SPR_403_PBU1          (0x3FD)
2052 #define SPR_604_HID13         (0x3FD)
2053 #define SPR_LT                (0x3FE)
2054 #define SPR_THRM3             (0x3FE)
2055 #define SPR_RCPU_FPECR        (0x3FE)
2056 #define SPR_403_PBL2          (0x3FE)
2057 #define SPR_PIR               (0x3FF)
2058 #define SPR_403_PBU2          (0x3FF)
2059 #define SPR_601_HID15         (0x3FF)
2060 #define SPR_604_HID15         (0x3FF)
2061 #define SPR_E500_SVR          (0x3FF)
2062 
2063 /* Disable MAS Interrupt Updates for Hypervisor */
2064 #define EPCR_DMIUH            (1 << 22)
2065 /* Disable Guest TLB Management Instructions */
2066 #define EPCR_DGTMI            (1 << 23)
2067 /* Guest Interrupt Computation Mode */
2068 #define EPCR_GICM             (1 << 24)
2069 /* Interrupt Computation Mode */
2070 #define EPCR_ICM              (1 << 25)
2071 /* Disable Embedded Hypervisor Debug */
2072 #define EPCR_DUVD             (1 << 26)
2073 /* Instruction Storage Interrupt Directed to Guest State */
2074 #define EPCR_ISIGS            (1 << 27)
2075 /* Data Storage Interrupt Directed to Guest State */
2076 #define EPCR_DSIGS            (1 << 28)
2077 /* Instruction TLB Error Interrupt Directed to Guest State */
2078 #define EPCR_ITLBGS           (1 << 29)
2079 /* Data TLB Error Interrupt Directed to Guest State */
2080 #define EPCR_DTLBGS           (1 << 30)
2081 /* External Input Interrupt Directed to Guest State */
2082 #define EPCR_EXTGS            (1 << 31)
2083 
2084 #define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
2085 #define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
2086 #define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
2087 #define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
2088 #define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
2089 
2090 #define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
2091 #define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
2092 #define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
2093 #define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
2094 #define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
2095 
2096 /* E500 L2CSR0 */
2097 #define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
2098 #define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
2099 #define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
2100 
2101 /* HID0 bits */
2102 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2103 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2104 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
2105 #define HID0_HILE           PPC_BIT(19) /* POWER8 */
2106 #define HID0_POWER9_HILE    PPC_BIT(4)
2107 
2108 /*****************************************************************************/
2109 /* PowerPC Instructions types definitions                                    */
2110 enum {
2111     PPC_NONE           = 0x0000000000000000ULL,
2112     /* PowerPC base instructions set                                         */
2113     PPC_INSNS_BASE     = 0x0000000000000001ULL,
2114     /*   integer operations instructions                                     */
2115 #define PPC_INTEGER PPC_INSNS_BASE
2116     /*   flow control instructions                                           */
2117 #define PPC_FLOW    PPC_INSNS_BASE
2118     /*   virtual memory instructions                                         */
2119 #define PPC_MEM     PPC_INSNS_BASE
2120     /*   ld/st with reservation instructions                                 */
2121 #define PPC_RES     PPC_INSNS_BASE
2122     /*   spr/msr access instructions                                         */
2123 #define PPC_MISC    PPC_INSNS_BASE
2124     /* Deprecated instruction sets                                           */
2125     /*   Original POWER instruction set                                      */
2126     PPC_POWER          = 0x0000000000000002ULL,
2127     /*   POWER2 instruction set extension                                    */
2128     PPC_POWER2         = 0x0000000000000004ULL,
2129     /*   Power RTC support                                                   */
2130     PPC_POWER_RTC      = 0x0000000000000008ULL,
2131     /*   Power-to-PowerPC bridge (601)                                       */
2132     PPC_POWER_BR       = 0x0000000000000010ULL,
2133     /* 64 bits PowerPC instruction set                                       */
2134     PPC_64B            = 0x0000000000000020ULL,
2135     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2136     PPC_64BX           = 0x0000000000000040ULL,
2137     /*   64 bits hypervisor extensions                                       */
2138     PPC_64H            = 0x0000000000000080ULL,
2139     /*   New wait instruction (PowerPC 2.0x)                                 */
2140     PPC_WAIT           = 0x0000000000000100ULL,
2141     /*   Time base mftb instruction                                          */
2142     PPC_MFTB           = 0x0000000000000200ULL,
2143 
2144     /* Fixed-point unit extensions                                           */
2145     /*   PowerPC 602 specific                                                */
2146     PPC_602_SPEC       = 0x0000000000000400ULL,
2147     /*   isel instruction                                                    */
2148     PPC_ISEL           = 0x0000000000000800ULL,
2149     /*   popcntb instruction                                                 */
2150     PPC_POPCNTB        = 0x0000000000001000ULL,
2151     /*   string load / store                                                 */
2152     PPC_STRING         = 0x0000000000002000ULL,
2153     /*   real mode cache inhibited load / store                              */
2154     PPC_CILDST         = 0x0000000000004000ULL,
2155 
2156     /* Floating-point unit extensions                                        */
2157     /*   Optional floating point instructions                                */
2158     PPC_FLOAT          = 0x0000000000010000ULL,
2159     /* New floating-point extensions (PowerPC 2.0x)                          */
2160     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2161     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2162     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2163     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2164     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2165     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2166     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2167 
2168     /* Vector/SIMD extensions                                                */
2169     /*   Altivec support                                                     */
2170     PPC_ALTIVEC        = 0x0000000001000000ULL,
2171     /*   PowerPC 2.03 SPE extension                                          */
2172     PPC_SPE            = 0x0000000002000000ULL,
2173     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2174     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2175     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2176     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2177 
2178     /* Optional memory control instructions                                  */
2179     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2180     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2181     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2182     /*   sync instruction                                                    */
2183     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2184     /*   eieio instruction                                                   */
2185     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2186 
2187     /* Cache control instructions                                            */
2188     PPC_CACHE          = 0x0000000200000000ULL,
2189     /*   icbi instruction                                                    */
2190     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2191     /*   dcbz instruction                                                    */
2192     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2193     /*   dcba instruction                                                    */
2194     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2195     /*   Freescale cache locking instructions                                */
2196     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2197 
2198     /* MMU related extensions                                                */
2199     /*   external control instructions                                       */
2200     PPC_EXTERN         = 0x0000010000000000ULL,
2201     /*   segment register access instructions                                */
2202     PPC_SEGMENT        = 0x0000020000000000ULL,
2203     /*   PowerPC 6xx TLB management instructions                             */
2204     PPC_6xx_TLB        = 0x0000040000000000ULL,
2205     /*   PowerPC 40x TLB management instructions                             */
2206     PPC_40x_TLB        = 0x0000100000000000ULL,
2207     /*   segment register access instructions for PowerPC 64 "bridge"        */
2208     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2209     /*   SLB management                                                      */
2210     PPC_SLBI           = 0x0000400000000000ULL,
2211 
2212     /* Embedded PowerPC dedicated instructions                               */
2213     PPC_WRTEE          = 0x0001000000000000ULL,
2214     /* PowerPC 40x exception model                                           */
2215     PPC_40x_EXCP       = 0x0002000000000000ULL,
2216     /* PowerPC 405 Mac instructions                                          */
2217     PPC_405_MAC        = 0x0004000000000000ULL,
2218     /* PowerPC 440 specific instructions                                     */
2219     PPC_440_SPEC       = 0x0008000000000000ULL,
2220     /* BookE (embedded) PowerPC specification                                */
2221     PPC_BOOKE          = 0x0010000000000000ULL,
2222     /* mfapidi instruction                                                   */
2223     PPC_MFAPIDI        = 0x0020000000000000ULL,
2224     /* tlbiva instruction                                                    */
2225     PPC_TLBIVA         = 0x0040000000000000ULL,
2226     /* tlbivax instruction                                                   */
2227     PPC_TLBIVAX        = 0x0080000000000000ULL,
2228     /* PowerPC 4xx dedicated instructions                                    */
2229     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2230     /* PowerPC 40x ibct instructions                                         */
2231     PPC_40x_ICBT       = 0x0200000000000000ULL,
2232     /* rfmci is not implemented in all BookE PowerPC                         */
2233     PPC_RFMCI          = 0x0400000000000000ULL,
2234     /* rfdi instruction                                                      */
2235     PPC_RFDI           = 0x0800000000000000ULL,
2236     /* DCR accesses                                                          */
2237     PPC_DCR            = 0x1000000000000000ULL,
2238     /* DCR extended accesse                                                  */
2239     PPC_DCRX           = 0x2000000000000000ULL,
2240     /* user-mode DCR access, implemented in PowerPC 460                      */
2241     PPC_DCRUX          = 0x4000000000000000ULL,
2242     /* popcntw and popcntd instructions                                      */
2243     PPC_POPCNTWD       = 0x8000000000000000ULL,
2244 
2245 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2246                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2247                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2248                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2249                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2250                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2251                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2252                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2253                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2254                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2255                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2256                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2257                         | PPC_CACHE | PPC_CACHE_ICBI \
2258                         | PPC_CACHE_DCBZ \
2259                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2260                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2261                         | PPC_40x_TLB | PPC_SEGMENT_64B \
2262                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2263                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2264                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2265                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2266                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2267                         | PPC_POPCNTWD | PPC_CILDST)
2268 
2269     /* extended type values */
2270 
2271     /* BookE 2.06 PowerPC specification                                      */
2272     PPC2_BOOKE206      = 0x0000000000000001ULL,
2273     /* VSX (extensions to Altivec / VMX)                                     */
2274     PPC2_VSX           = 0x0000000000000002ULL,
2275     /* Decimal Floating Point (DFP)                                          */
2276     PPC2_DFP           = 0x0000000000000004ULL,
2277     /* Embedded.Processor Control                                            */
2278     PPC2_PRCNTL        = 0x0000000000000008ULL,
2279     /* Byte-reversed, indexed, double-word load and store                    */
2280     PPC2_DBRX          = 0x0000000000000010ULL,
2281     /* Book I 2.05 PowerPC specification                                     */
2282     PPC2_ISA205        = 0x0000000000000020ULL,
2283     /* VSX additions in ISA 2.07                                             */
2284     PPC2_VSX207        = 0x0000000000000040ULL,
2285     /* ISA 2.06B bpermd                                                      */
2286     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2287     /* ISA 2.06B divide extended variants                                    */
2288     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2289     /* ISA 2.06B larx/stcx. instructions                                     */
2290     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2291     /* ISA 2.06B floating point integer conversion                           */
2292     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2293     /* ISA 2.06B floating point test instructions                            */
2294     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2295     /* ISA 2.07 bctar instruction                                            */
2296     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2297     /* ISA 2.07 load/store quadword                                          */
2298     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2299     /* ISA 2.07 Altivec                                                      */
2300     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2301     /* PowerISA 2.07 Book3s specification                                    */
2302     PPC2_ISA207S       = 0x0000000000008000ULL,
2303     /* Double precision floating point conversion for signed integer 64      */
2304     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2305     /* Transactional Memory (ISA 2.07, Book II)                              */
2306     PPC2_TM            = 0x0000000000020000ULL,
2307     /* Server PM instructgions (ISA 2.06, Book III)                          */
2308     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2309     /* POWER ISA 3.0                                                         */
2310     PPC2_ISA300        = 0x0000000000080000ULL,
2311     /* POWER ISA 3.1                                                         */
2312     PPC2_ISA310        = 0x0000000000100000ULL,
2313 
2314 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2315                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2316                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2317                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2318                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2319                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2320                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2321                         PPC2_ISA300 | PPC2_ISA310)
2322 };
2323 
2324 /*****************************************************************************/
2325 /*
2326  * Memory access type :
2327  * may be needed for precise access rights control and precise exceptions.
2328  */
2329 enum {
2330     /* Type of instruction that generated the access */
2331     ACCESS_CODE  = 0x10, /* Code fetch access                */
2332     ACCESS_INT   = 0x20, /* Integer load/store access        */
2333     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2334     ACCESS_RES   = 0x40, /* load/store with reservation      */
2335     ACCESS_EXT   = 0x50, /* external access                  */
2336     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2337 };
2338 
2339 /*
2340  * Hardware interrupt sources:
2341  *   all those exception can be raised simulteaneously
2342  */
2343 /* Input pins definitions */
2344 enum {
2345     /* 6xx bus input pins */
2346     PPC6xx_INPUT_HRESET     = 0,
2347     PPC6xx_INPUT_SRESET     = 1,
2348     PPC6xx_INPUT_CKSTP_IN   = 2,
2349     PPC6xx_INPUT_MCP        = 3,
2350     PPC6xx_INPUT_SMI        = 4,
2351     PPC6xx_INPUT_INT        = 5,
2352     PPC6xx_INPUT_TBEN       = 6,
2353     PPC6xx_INPUT_WAKEUP     = 7,
2354     PPC6xx_INPUT_NB,
2355 };
2356 
2357 enum {
2358     /* Embedded PowerPC input pins */
2359     PPCBookE_INPUT_HRESET     = 0,
2360     PPCBookE_INPUT_SRESET     = 1,
2361     PPCBookE_INPUT_CKSTP_IN   = 2,
2362     PPCBookE_INPUT_MCP        = 3,
2363     PPCBookE_INPUT_SMI        = 4,
2364     PPCBookE_INPUT_INT        = 5,
2365     PPCBookE_INPUT_CINT       = 6,
2366     PPCBookE_INPUT_NB,
2367 };
2368 
2369 enum {
2370     /* PowerPC E500 input pins */
2371     PPCE500_INPUT_RESET_CORE = 0,
2372     PPCE500_INPUT_MCK        = 1,
2373     PPCE500_INPUT_CINT       = 3,
2374     PPCE500_INPUT_INT        = 4,
2375     PPCE500_INPUT_DEBUG      = 6,
2376     PPCE500_INPUT_NB,
2377 };
2378 
2379 enum {
2380     /* PowerPC 40x input pins */
2381     PPC40x_INPUT_RESET_CORE = 0,
2382     PPC40x_INPUT_RESET_CHIP = 1,
2383     PPC40x_INPUT_RESET_SYS  = 2,
2384     PPC40x_INPUT_CINT       = 3,
2385     PPC40x_INPUT_INT        = 4,
2386     PPC40x_INPUT_HALT       = 5,
2387     PPC40x_INPUT_DEBUG      = 6,
2388     PPC40x_INPUT_NB,
2389 };
2390 
2391 enum {
2392     /* RCPU input pins */
2393     PPCRCPU_INPUT_PORESET   = 0,
2394     PPCRCPU_INPUT_HRESET    = 1,
2395     PPCRCPU_INPUT_SRESET    = 2,
2396     PPCRCPU_INPUT_IRQ0      = 3,
2397     PPCRCPU_INPUT_IRQ1      = 4,
2398     PPCRCPU_INPUT_IRQ2      = 5,
2399     PPCRCPU_INPUT_IRQ3      = 6,
2400     PPCRCPU_INPUT_IRQ4      = 7,
2401     PPCRCPU_INPUT_IRQ5      = 8,
2402     PPCRCPU_INPUT_IRQ6      = 9,
2403     PPCRCPU_INPUT_IRQ7      = 10,
2404     PPCRCPU_INPUT_NB,
2405 };
2406 
2407 #if defined(TARGET_PPC64)
2408 enum {
2409     /* PowerPC 970 input pins */
2410     PPC970_INPUT_HRESET     = 0,
2411     PPC970_INPUT_SRESET     = 1,
2412     PPC970_INPUT_CKSTP      = 2,
2413     PPC970_INPUT_TBEN       = 3,
2414     PPC970_INPUT_MCP        = 4,
2415     PPC970_INPUT_INT        = 5,
2416     PPC970_INPUT_THINT      = 6,
2417     PPC970_INPUT_NB,
2418 };
2419 
2420 enum {
2421     /* POWER7 input pins */
2422     POWER7_INPUT_INT        = 0,
2423     /*
2424      * POWER7 probably has other inputs, but we don't care about them
2425      * for any existing machine.  We can wire these up when we need
2426      * them
2427      */
2428     POWER7_INPUT_NB,
2429 };
2430 
2431 enum {
2432     /* POWER9 input pins */
2433     POWER9_INPUT_INT        = 0,
2434     POWER9_INPUT_HINT       = 1,
2435     POWER9_INPUT_NB,
2436 };
2437 #endif
2438 
2439 /* Hardware exceptions definitions */
2440 enum {
2441     /* External hardware exception sources */
2442     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2443     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2444     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2445     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2446     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2447     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2448     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2449     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2450     /* Internal hardware exception sources */
2451     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2452     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2453     PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
2454     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2455     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2456     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2457     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2458     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2459     PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
2460     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2461     PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
2462 };
2463 
2464 /* Processor Compatibility mask (PCR) */
2465 enum {
2466     PCR_COMPAT_2_05     = PPC_BIT(62),
2467     PCR_COMPAT_2_06     = PPC_BIT(61),
2468     PCR_COMPAT_2_07     = PPC_BIT(60),
2469     PCR_COMPAT_3_00     = PPC_BIT(59),
2470     PCR_COMPAT_3_10     = PPC_BIT(58),
2471     PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2472     PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2473     PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2474 };
2475 
2476 /* HMER/HMEER */
2477 enum {
2478     HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2479     HMER_PROC_RECV_DONE         = PPC_BIT(2),
2480     HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2481     HMER_TFAC_ERROR             = PPC_BIT(4),
2482     HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2483     HMER_XSCOM_FAIL             = PPC_BIT(8),
2484     HMER_XSCOM_DONE             = PPC_BIT(9),
2485     HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2486     HMER_WARN_RISE              = PPC_BIT(14),
2487     HMER_WARN_FALL              = PPC_BIT(15),
2488     HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2489     HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2490     HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2491     HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2492 };
2493 
2494 /*****************************************************************************/
2495 
2496 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2497 target_ulong cpu_read_xer(const CPUPPCState *env);
2498 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2499 
2500 /*
2501  * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2502  * have PPC_SEGMENT_64B.
2503  */
2504 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2505 
2506 #ifdef CONFIG_DEBUG_TCG
2507 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2508                           target_ulong *cs_base, uint32_t *flags);
2509 #else
2510 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2511                                         target_ulong *cs_base, uint32_t *flags)
2512 {
2513     *pc = env->nip;
2514     *cs_base = 0;
2515     *flags = env->hflags;
2516 }
2517 #endif
2518 
2519 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2520 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2521                                       uintptr_t raddr);
2522 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2523                                        uint32_t error_code);
2524 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2525                                           uint32_t error_code, uintptr_t raddr);
2526 
2527 #if !defined(CONFIG_USER_ONLY)
2528 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2529 {
2530     uintptr_t tlbml = (uintptr_t)tlbm;
2531     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2532 
2533     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2534 }
2535 
2536 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2537 {
2538     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2539     int r = tlbncfg & TLBnCFG_N_ENTRY;
2540     return r;
2541 }
2542 
2543 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2544 {
2545     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2546     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2547     return r;
2548 }
2549 
2550 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2551 {
2552     int id = booke206_tlbm_id(env, tlbm);
2553     int end = 0;
2554     int i;
2555 
2556     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2557         end += booke206_tlb_size(env, i);
2558         if (id < end) {
2559             return i;
2560         }
2561     }
2562 
2563     cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2564     return 0;
2565 }
2566 
2567 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2568 {
2569     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2570     int tlbid = booke206_tlbm_id(env, tlb);
2571     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2572 }
2573 
2574 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2575                                               target_ulong ea, int way)
2576 {
2577     int r;
2578     uint32_t ways = booke206_tlb_ways(env, tlbn);
2579     int ways_bits = ctz32(ways);
2580     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2581     int i;
2582 
2583     way &= ways - 1;
2584     ea >>= MAS2_EPN_SHIFT;
2585     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2586     r = (ea << ways_bits) | way;
2587 
2588     if (r >= booke206_tlb_size(env, tlbn)) {
2589         return NULL;
2590     }
2591 
2592     /* bump up to tlbn index */
2593     for (i = 0; i < tlbn; i++) {
2594         r += booke206_tlb_size(env, i);
2595     }
2596 
2597     return &env->tlb.tlbm[r];
2598 }
2599 
2600 /* returns bitmap of supported page sizes for a given TLB */
2601 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2602 {
2603     uint32_t ret = 0;
2604 
2605     if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2606         /* MAV2 */
2607         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2608     } else {
2609         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2610         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2611         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2612         int i;
2613         for (i = min; i <= max; i++) {
2614             ret |= (1 << (i << 1));
2615         }
2616     }
2617 
2618     return ret;
2619 }
2620 
2621 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2622                                             ppcmas_tlb_t *tlb)
2623 {
2624     uint8_t i;
2625     int32_t tsize = -1;
2626 
2627     for (i = 0; i < 32; i++) {
2628         if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2629             if (tsize == -1) {
2630                 tsize = i;
2631             } else {
2632                 return;
2633             }
2634         }
2635     }
2636 
2637     /* TLBnPS unimplemented? Odd.. */
2638     assert(tsize != -1);
2639     tlb->mas1 &= ~MAS1_TSIZE_MASK;
2640     tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2641 }
2642 
2643 #endif
2644 
2645 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2646 {
2647     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2648         return msr & (1ULL << MSR_CM);
2649     }
2650 
2651     return msr & (1ULL << MSR_SF);
2652 }
2653 
2654 /**
2655  * Check whether register rx is in the range between start and
2656  * start + nregs (as needed by the LSWX and LSWI instructions)
2657  */
2658 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2659 {
2660     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2661            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2662 }
2663 
2664 /* Accessors for FP, VMX and VSX registers */
2665 #if defined(HOST_WORDS_BIGENDIAN)
2666 #define VsrB(i) u8[i]
2667 #define VsrSB(i) s8[i]
2668 #define VsrH(i) u16[i]
2669 #define VsrSH(i) s16[i]
2670 #define VsrW(i) u32[i]
2671 #define VsrSW(i) s32[i]
2672 #define VsrD(i) u64[i]
2673 #define VsrSD(i) s64[i]
2674 #else
2675 #define VsrB(i) u8[15 - (i)]
2676 #define VsrSB(i) s8[15 - (i)]
2677 #define VsrH(i) u16[7 - (i)]
2678 #define VsrSH(i) s16[7 - (i)]
2679 #define VsrW(i) u32[3 - (i)]
2680 #define VsrSW(i) s32[3 - (i)]
2681 #define VsrD(i) u64[1 - (i)]
2682 #define VsrSD(i) s64[1 - (i)]
2683 #endif
2684 
2685 static inline int vsr64_offset(int i, bool high)
2686 {
2687     return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2688 }
2689 
2690 static inline int vsr_full_offset(int i)
2691 {
2692     return offsetof(CPUPPCState, vsr[i].u64[0]);
2693 }
2694 
2695 static inline int fpr_offset(int i)
2696 {
2697     return vsr64_offset(i, true);
2698 }
2699 
2700 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2701 {
2702     return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2703 }
2704 
2705 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2706 {
2707     return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2708 }
2709 
2710 static inline long avr64_offset(int i, bool high)
2711 {
2712     return vsr64_offset(i + 32, high);
2713 }
2714 
2715 static inline int avr_full_offset(int i)
2716 {
2717     return vsr_full_offset(i + 32);
2718 }
2719 
2720 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2721 {
2722     return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2723 }
2724 
2725 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2726 {
2727     /* We can test whether the SPR is defined by checking for a valid name */
2728     return cpu->env.spr_cb[spr].name != NULL;
2729 }
2730 
2731 #if !defined(CONFIG_USER_ONLY)
2732 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2733 {
2734     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2735     CPUPPCState *env = &cpu->env;
2736     bool ile;
2737 
2738     if (hv && env->has_hv_mode) {
2739         if (is_isa300(pcc)) {
2740             ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2741         } else {
2742             ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2743         }
2744 
2745     } else if (pcc->lpcr_mask & LPCR_ILE) {
2746         ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2747     } else {
2748         ile = !!(msr_ile);
2749     }
2750 
2751     return ile;
2752 }
2753 #endif
2754 
2755 void dump_mmu(CPUPPCState *env);
2756 
2757 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2758 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
2759 uint32_t ppc_get_vscr(CPUPPCState *env);
2760 #endif /* PPC_CPU_H */
2761