1 /* 2 * PowerPC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_CPU_H 21 #define PPC_CPU_H 22 23 #include "qemu/int128.h" 24 #include "exec/cpu-defs.h" 25 #include "cpu-qom.h" 26 #include "qom/object.h" 27 28 #define TCG_GUEST_DEFAULT_MO 0 29 30 #define TARGET_PAGE_BITS_64K 16 31 #define TARGET_PAGE_BITS_16M 24 32 33 #if defined(TARGET_PPC64) 34 #define PPC_ELF_MACHINE EM_PPC64 35 #else 36 #define PPC_ELF_MACHINE EM_PPC 37 #endif 38 39 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) 40 #define PPC_BIT32(bit) (0x80000000 >> (bit)) 41 #define PPC_BIT8(bit) (0x80 >> (bit)) 42 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 43 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ 44 PPC_BIT32(bs)) 45 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs)) 46 47 /*****************************************************************************/ 48 /* Exception vectors definitions */ 49 enum { 50 POWERPC_EXCP_NONE = -1, 51 /* The 64 first entries are used by the PowerPC embedded specification */ 52 POWERPC_EXCP_CRITICAL = 0, /* Critical input */ 53 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ 54 POWERPC_EXCP_DSI = 2, /* Data storage exception */ 55 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ 56 POWERPC_EXCP_EXTERNAL = 4, /* External input */ 57 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ 58 POWERPC_EXCP_PROGRAM = 6, /* Program exception */ 59 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ 60 POWERPC_EXCP_SYSCALL = 8, /* System call exception */ 61 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ 62 POWERPC_EXCP_DECR = 10, /* Decrementer exception */ 63 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ 64 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ 65 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ 66 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ 67 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ 68 /* Vectors 16 to 31 are reserved */ 69 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ 70 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ 71 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ 72 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ 73 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ 74 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ 75 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */ 76 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/ 77 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */ 78 /* Vectors 42 to 63 are reserved */ 79 /* Exceptions defined in the PowerPC server specification */ 80 POWERPC_EXCP_RESET = 64, /* System reset exception */ 81 POWERPC_EXCP_DSEG = 65, /* Data segment exception */ 82 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ 83 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ 84 POWERPC_EXCP_TRACE = 68, /* Trace exception */ 85 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ 86 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ 87 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ 88 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ 89 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ 90 /* 40x specific exceptions */ 91 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ 92 /* Vectors 75-76 are 601 specific exceptions */ 93 /* 602 specific exceptions */ 94 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ 95 /* 602/603 specific exceptions */ 96 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ 97 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ 98 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ 99 /* Exceptions available on most PowerPC */ 100 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ 101 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ 102 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ 103 POWERPC_EXCP_SMI = 84, /* System management interrupt */ 104 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ 105 /* 7xx/74xx specific exceptions */ 106 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ 107 /* 74xx specific exceptions */ 108 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ 109 /* 970FX specific exceptions */ 110 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ 111 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ 112 /* Freescale embedded cores specific exceptions */ 113 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ 114 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ 115 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ 116 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ 117 /* VSX Unavailable (Power ISA 2.06 and later) */ 118 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */ 119 POWERPC_EXCP_FU = 95, /* Facility Unavailable */ 120 /* Additional ISA 2.06 and later server exceptions */ 121 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */ 122 POWERPC_EXCP_HV_MAINT = 97, /* HMI */ 123 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */ 124 /* Server doorbell variants */ 125 POWERPC_EXCP_SDOOR = 99, 126 POWERPC_EXCP_SDOOR_HV = 100, 127 /* ISA 3.00 additions */ 128 POWERPC_EXCP_HVIRT = 101, 129 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */ 130 /* EOL */ 131 POWERPC_EXCP_NB = 103, 132 /* QEMU exceptions: special cases we want to stop translation */ 133 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ 134 }; 135 136 /* Exceptions error codes */ 137 enum { 138 /* Exception subtypes for POWERPC_EXCP_ALIGN */ 139 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ 140 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ 141 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ 142 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ 143 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ 144 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ 145 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ 146 /* Exception subtypes for POWERPC_EXCP_PROGRAM */ 147 /* FP exceptions */ 148 POWERPC_EXCP_FP = 0x10, 149 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ 150 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ 151 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ 152 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ 153 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ 154 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ 155 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ 156 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ 157 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ 158 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ 159 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ 160 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ 161 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ 162 /* Invalid instruction */ 163 POWERPC_EXCP_INVAL = 0x20, 164 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ 165 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ 166 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ 167 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ 168 /* Privileged instruction */ 169 POWERPC_EXCP_PRIV = 0x30, 170 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ 171 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ 172 /* Trap */ 173 POWERPC_EXCP_TRAP = 0x40, 174 }; 175 176 #define PPC_INPUT(env) ((env)->bus_model) 177 178 /*****************************************************************************/ 179 typedef struct opc_handler_t opc_handler_t; 180 181 /*****************************************************************************/ 182 /* Types used to describe some PowerPC registers etc. */ 183 typedef struct DisasContext DisasContext; 184 typedef struct ppc_spr_t ppc_spr_t; 185 typedef union ppc_tlb_t ppc_tlb_t; 186 typedef struct ppc_hash_pte64 ppc_hash_pte64_t; 187 188 /* SPR access micro-ops generations callbacks */ 189 struct ppc_spr_t { 190 const char *name; 191 target_ulong default_value; 192 #ifndef CONFIG_USER_ONLY 193 unsigned int gdb_id; 194 #endif 195 #ifdef CONFIG_TCG 196 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); 197 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); 198 # ifndef CONFIG_USER_ONLY 199 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); 200 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); 201 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); 202 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); 203 # endif 204 #endif 205 #ifdef CONFIG_KVM 206 /* 207 * We (ab)use the fact that all the SPRs will have ids for the 208 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, 209 * don't sync this 210 */ 211 uint64_t one_reg_id; 212 #endif 213 }; 214 215 /* VSX/Altivec registers (128 bits) */ 216 typedef union _ppc_vsr_t { 217 uint8_t u8[16]; 218 uint16_t u16[8]; 219 uint32_t u32[4]; 220 uint64_t u64[2]; 221 int8_t s8[16]; 222 int16_t s16[8]; 223 int32_t s32[4]; 224 int64_t s64[2]; 225 float32 f32[4]; 226 float64 f64[2]; 227 float128 f128; 228 #ifdef CONFIG_INT128 229 __uint128_t u128; 230 #endif 231 Int128 s128; 232 } ppc_vsr_t; 233 234 typedef ppc_vsr_t ppc_avr_t; 235 typedef ppc_vsr_t ppc_fprp_t; 236 237 #if !defined(CONFIG_USER_ONLY) 238 /* Software TLB cache */ 239 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; 240 struct ppc6xx_tlb_t { 241 target_ulong pte0; 242 target_ulong pte1; 243 target_ulong EPN; 244 }; 245 246 typedef struct ppcemb_tlb_t ppcemb_tlb_t; 247 struct ppcemb_tlb_t { 248 uint64_t RPN; 249 target_ulong EPN; 250 target_ulong PID; 251 target_ulong size; 252 uint32_t prot; 253 uint32_t attr; /* Storage attributes */ 254 }; 255 256 typedef struct ppcmas_tlb_t { 257 uint32_t mas8; 258 uint32_t mas1; 259 uint64_t mas2; 260 uint64_t mas7_3; 261 } ppcmas_tlb_t; 262 263 union ppc_tlb_t { 264 ppc6xx_tlb_t *tlb6; 265 ppcemb_tlb_t *tlbe; 266 ppcmas_tlb_t *tlbm; 267 }; 268 269 /* possible TLB variants */ 270 #define TLB_NONE 0 271 #define TLB_6XX 1 272 #define TLB_EMB 2 273 #define TLB_MAS 3 274 #endif 275 276 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes; 277 278 typedef struct ppc_slb_t ppc_slb_t; 279 struct ppc_slb_t { 280 uint64_t esid; 281 uint64_t vsid; 282 const PPCHash64SegmentPageSizes *sps; 283 }; 284 285 #define MAX_SLB_ENTRIES 64 286 #define SEGMENT_SHIFT_256M 28 287 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) 288 289 #define SEGMENT_SHIFT_1T 40 290 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) 291 292 typedef struct ppc_v3_pate_t { 293 uint64_t dw0; 294 uint64_t dw1; 295 } ppc_v3_pate_t; 296 297 /* PMU related structs and defines */ 298 #define PMU_COUNTERS_NUM 6 299 typedef enum { 300 PMU_EVENT_INVALID = 0, 301 PMU_EVENT_INACTIVE, 302 PMU_EVENT_CYCLES, 303 PMU_EVENT_INSTRUCTIONS, 304 PMU_EVENT_INSN_RUN_LATCH, 305 } PMUEventType; 306 307 /*****************************************************************************/ 308 /* Machine state register bits definition */ 309 #define MSR_SF 63 /* Sixty-four-bit mode hflags */ 310 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ 311 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ 312 #define MSR_HV 60 /* hypervisor state hflags */ 313 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ 314 #define MSR_TS1 33 315 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */ 316 #define MSR_CM 31 /* Computation mode for BookE hflags */ 317 #define MSR_ICM 30 /* Interrupt computation mode for BookE */ 318 #define MSR_GS 28 /* guest state for BookE */ 319 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ 320 #define MSR_VR 25 /* altivec available x hflags */ 321 #define MSR_SPE 25 /* SPE enable for BookE x hflags */ 322 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */ 323 #define MSR_S 22 /* Secure state */ 324 #define MSR_KEY 19 /* key bit on 603e */ 325 #define MSR_POW 18 /* Power management */ 326 #define MSR_WE 18 /* Wait State Enable on 405 */ 327 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ 328 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ 329 #define MSR_ILE 16 /* Interrupt little-endian mode */ 330 #define MSR_EE 15 /* External interrupt enable */ 331 #define MSR_PR 14 /* Problem state hflags */ 332 #define MSR_FP 13 /* Floating point available hflags */ 333 #define MSR_ME 12 /* Machine check interrupt enable */ 334 #define MSR_FE0 11 /* Floating point exception mode 0 */ 335 #define MSR_SE 10 /* Single-step trace enable x hflags */ 336 #define MSR_DWE 10 /* Debug wait enable on 405 x */ 337 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ 338 #define MSR_BE 9 /* Branch trace enable x hflags */ 339 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ 340 #define MSR_FE1 8 /* Floating point exception mode 1 */ 341 #define MSR_AL 7 /* AL bit on POWER */ 342 #define MSR_EP 6 /* Exception prefix on 601 */ 343 #define MSR_IR 5 /* Instruction relocate */ 344 #define MSR_DR 4 /* Data relocate */ 345 #define MSR_IS 5 /* Instruction address space (BookE) */ 346 #define MSR_DS 4 /* Data address space (BookE) */ 347 #define MSR_PE 3 /* Protection enable on 403 */ 348 #define MSR_PX 2 /* Protection exclusive on 403 x */ 349 #define MSR_PMM 2 /* Performance monitor mark on POWER x */ 350 #define MSR_RI 1 /* Recoverable interrupt 1 */ 351 #define MSR_LE 0 /* Little-endian mode 1 hflags */ 352 353 /* PMU bits */ 354 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ 355 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ 356 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */ 357 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ 358 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ 359 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */ 360 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */ 361 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ 362 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ 363 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ 364 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ 365 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ 366 /* MMCR0 userspace r/w mask */ 367 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) 368 /* MMCR2 userspace r/w mask */ 369 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */ 370 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */ 371 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */ 372 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */ 373 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */ 374 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */ 375 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \ 376 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) 377 378 #define MMCR1_EVT_SIZE 8 379 /* extract64() does a right shift before extracting */ 380 #define MMCR1_PMC1SEL_START 32 381 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) 382 #define MMCR1_PMC2SEL_START 40 383 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) 384 #define MMCR1_PMC3SEL_START 48 385 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) 386 #define MMCR1_PMC4SEL_START 56 387 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) 388 389 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ 390 #define CTRL_RUN PPC_BIT(63) 391 392 /* EBB/BESCR bits */ 393 /* Global Enable */ 394 #define BESCR_GE PPC_BIT(0) 395 /* External Event-based Exception Enable */ 396 #define BESCR_EE PPC_BIT(30) 397 /* Performance Monitor Event-based Exception Enable */ 398 #define BESCR_PME PPC_BIT(31) 399 /* External Event-based Exception Occurred */ 400 #define BESCR_EEO PPC_BIT(62) 401 /* Performance Monitor Event-based Exception Occurred */ 402 #define BESCR_PMEO PPC_BIT(63) 403 #define BESCR_INVALID PPC_BITMASK(32, 33) 404 405 /* LPCR bits */ 406 #define LPCR_VPM0 PPC_BIT(0) 407 #define LPCR_VPM1 PPC_BIT(1) 408 #define LPCR_ISL PPC_BIT(2) 409 #define LPCR_KBV PPC_BIT(3) 410 #define LPCR_DPFD_SHIFT (63 - 11) 411 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) 412 #define LPCR_VRMASD_SHIFT (63 - 16) 413 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) 414 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ 415 #define LPCR_PECE_U_SHIFT (63 - 19) 416 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) 417 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ 418 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */ 419 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) 420 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */ 421 #define LPCR_ILE PPC_BIT(38) 422 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ 423 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) 424 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ 425 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ 426 #define LPCR_HR PPC_BIT(43) /* Host Radix */ 427 #define LPCR_ONL PPC_BIT(45) 428 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */ 429 #define LPCR_P7_PECE0 PPC_BIT(49) 430 #define LPCR_P7_PECE1 PPC_BIT(50) 431 #define LPCR_P7_PECE2 PPC_BIT(51) 432 #define LPCR_P8_PECE0 PPC_BIT(47) 433 #define LPCR_P8_PECE1 PPC_BIT(48) 434 #define LPCR_P8_PECE2 PPC_BIT(49) 435 #define LPCR_P8_PECE3 PPC_BIT(50) 436 #define LPCR_P8_PECE4 PPC_BIT(51) 437 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ 438 #define LPCR_PECE_L_SHIFT (63 - 51) 439 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) 440 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */ 441 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */ 442 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */ 443 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */ 444 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */ 445 #define LPCR_MER PPC_BIT(52) 446 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */ 447 #define LPCR_TC PPC_BIT(54) 448 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */ 449 #define LPCR_LPES0 PPC_BIT(60) 450 #define LPCR_LPES1 PPC_BIT(61) 451 #define LPCR_RMI PPC_BIT(62) 452 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */ 453 #define LPCR_HDICE PPC_BIT(63) 454 455 /* PSSCR bits */ 456 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ 457 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ 458 459 /* HFSCR bits */ 460 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ 461 #define HFSCR_IC_MSGP 0xA 462 463 #define msr_sf ((env->msr >> MSR_SF) & 1) 464 #define msr_isf ((env->msr >> MSR_ISF) & 1) 465 #if defined(TARGET_PPC64) 466 #define msr_hv ((env->msr >> MSR_HV) & 1) 467 #else 468 #define msr_hv (0) 469 #endif 470 #define msr_cm ((env->msr >> MSR_CM) & 1) 471 #define msr_icm ((env->msr >> MSR_ICM) & 1) 472 #define msr_gs ((env->msr >> MSR_GS) & 1) 473 #define msr_ucle ((env->msr >> MSR_UCLE) & 1) 474 #define msr_vr ((env->msr >> MSR_VR) & 1) 475 #define msr_spe ((env->msr >> MSR_SPE) & 1) 476 #define msr_vsx ((env->msr >> MSR_VSX) & 1) 477 #define msr_key ((env->msr >> MSR_KEY) & 1) 478 #define msr_pow ((env->msr >> MSR_POW) & 1) 479 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) 480 #define msr_ce ((env->msr >> MSR_CE) & 1) 481 #define msr_ile ((env->msr >> MSR_ILE) & 1) 482 #define msr_ee ((env->msr >> MSR_EE) & 1) 483 #define msr_pr ((env->msr >> MSR_PR) & 1) 484 #define msr_fp ((env->msr >> MSR_FP) & 1) 485 #define msr_me ((env->msr >> MSR_ME) & 1) 486 #define msr_fe0 ((env->msr >> MSR_FE0) & 1) 487 #define msr_se ((env->msr >> MSR_SE) & 1) 488 #define msr_dwe ((env->msr >> MSR_DWE) & 1) 489 #define msr_uble ((env->msr >> MSR_UBLE) & 1) 490 #define msr_be ((env->msr >> MSR_BE) & 1) 491 #define msr_de ((env->msr >> MSR_DE) & 1) 492 #define msr_fe1 ((env->msr >> MSR_FE1) & 1) 493 #define msr_al ((env->msr >> MSR_AL) & 1) 494 #define msr_ep ((env->msr >> MSR_EP) & 1) 495 #define msr_ir ((env->msr >> MSR_IR) & 1) 496 #define msr_dr ((env->msr >> MSR_DR) & 1) 497 #define msr_is ((env->msr >> MSR_IS) & 1) 498 #define msr_ds ((env->msr >> MSR_DS) & 1) 499 #define msr_pe ((env->msr >> MSR_PE) & 1) 500 #define msr_px ((env->msr >> MSR_PX) & 1) 501 #define msr_pmm ((env->msr >> MSR_PMM) & 1) 502 #define msr_ri ((env->msr >> MSR_RI) & 1) 503 #define msr_le ((env->msr >> MSR_LE) & 1) 504 #define msr_ts ((env->msr >> MSR_TS1) & 3) 505 #define msr_tm ((env->msr >> MSR_TM) & 1) 506 507 #define DBCR0_ICMP (1 << 27) 508 #define DBCR0_BRT (1 << 26) 509 #define DBSR_ICMP (1 << 27) 510 #define DBSR_BRT (1 << 26) 511 512 /* Hypervisor bit is more specific */ 513 #if defined(TARGET_PPC64) 514 #define MSR_HVB (1ULL << MSR_HV) 515 #else 516 #define MSR_HVB (0ULL) 517 #endif 518 519 /* DSISR */ 520 #define DSISR_NOPTE 0x40000000 521 /* Not permitted by access authority of encoded access authority */ 522 #define DSISR_PROTFAULT 0x08000000 523 #define DSISR_ISSTORE 0x02000000 524 /* Not permitted by virtual page class key protection */ 525 #define DSISR_AMR 0x00200000 526 /* Unsupported Radix Tree Configuration */ 527 #define DSISR_R_BADCONFIG 0x00080000 528 #define DSISR_ATOMIC_RC 0x00040000 529 /* Unable to translate address of (guest) pde or process/page table entry */ 530 #define DSISR_PRTABLE_FAULT 0x00020000 531 532 /* SRR1 error code fields */ 533 534 #define SRR1_NOPTE DSISR_NOPTE 535 /* Not permitted due to no-execute or guard bit set */ 536 #define SRR1_NOEXEC_GUARD 0x10000000 537 #define SRR1_PROTFAULT DSISR_PROTFAULT 538 #define SRR1_IAMR DSISR_AMR 539 540 /* SRR1[42:45] wakeup fields for System Reset Interrupt */ 541 542 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */ 543 544 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ 545 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */ 546 #define SRR1_WAKEEE 0x00200000 /* External interrupt */ 547 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 548 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */ 549 #define SRR1_WAKERESET 0x00100000 /* System reset */ 550 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */ 551 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */ 552 553 /* SRR1[46:47] power-saving exit mode */ 554 555 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */ 556 557 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */ 558 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */ 559 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */ 560 561 /* Facility Status and Control (FSCR) bits */ 562 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ 563 #define FSCR_TAR (63 - 55) /* Target Address Register */ 564 #define FSCR_SCV (63 - 51) /* System call vectored */ 565 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */ 566 #define FSCR_IC_MASK (0xFFULL) 567 #define FSCR_IC_POS (63 - 7) 568 #define FSCR_IC_DSCR_SPR3 2 569 #define FSCR_IC_PMU 3 570 #define FSCR_IC_BHRB 4 571 #define FSCR_IC_TM 5 572 #define FSCR_IC_EBB 7 573 #define FSCR_IC_TAR 8 574 #define FSCR_IC_SCV 12 575 576 /* Exception state register bits definition */ 577 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */ 578 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */ 579 #define ESR_PTR PPC_BIT(38) /* Trap */ 580 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */ 581 #define ESR_ST PPC_BIT(40) /* Store Operation */ 582 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */ 583 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */ 584 #define ESR_BO PPC_BIT(46) /* Byte Ordering */ 585 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */ 586 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */ 587 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */ 588 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */ 589 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */ 590 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */ 591 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */ 592 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */ 593 594 /* Transaction EXception And Summary Register bits */ 595 #define TEXASR_FAILURE_PERSISTENT (63 - 7) 596 #define TEXASR_DISALLOWED (63 - 8) 597 #define TEXASR_NESTING_OVERFLOW (63 - 9) 598 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) 599 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) 600 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) 601 #define TEXASR_TRANSACTION_CONFLICT (63 - 13) 602 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) 603 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) 604 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) 605 #define TEXASR_ABORT (63 - 31) 606 #define TEXASR_SUSPENDED (63 - 32) 607 #define TEXASR_PRIVILEGE_HV (63 - 34) 608 #define TEXASR_PRIVILEGE_PR (63 - 35) 609 #define TEXASR_FAILURE_SUMMARY (63 - 36) 610 #define TEXASR_TFIAR_EXACT (63 - 37) 611 #define TEXASR_ROT (63 - 38) 612 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ 613 614 enum { 615 POWERPC_FLAG_NONE = 0x00000000, 616 /* Flag for MSR bit 25 signification (VRE/SPE) */ 617 POWERPC_FLAG_SPE = 0x00000001, 618 POWERPC_FLAG_VRE = 0x00000002, 619 /* Flag for MSR bit 17 signification (TGPR/CE) */ 620 POWERPC_FLAG_TGPR = 0x00000004, 621 POWERPC_FLAG_CE = 0x00000008, 622 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ 623 POWERPC_FLAG_SE = 0x00000010, 624 POWERPC_FLAG_DWE = 0x00000020, 625 POWERPC_FLAG_UBLE = 0x00000040, 626 /* Flag for MSR bit 9 signification (BE/DE) */ 627 POWERPC_FLAG_BE = 0x00000080, 628 POWERPC_FLAG_DE = 0x00000100, 629 /* Flag for MSR bit 2 signification (PX/PMM) */ 630 POWERPC_FLAG_PX = 0x00000200, 631 POWERPC_FLAG_PMM = 0x00000400, 632 /* Flag for special features */ 633 /* Decrementer clock */ 634 POWERPC_FLAG_BUS_CLK = 0x00020000, 635 /* Has CFAR */ 636 POWERPC_FLAG_CFAR = 0x00040000, 637 /* Has VSX */ 638 POWERPC_FLAG_VSX = 0x00080000, 639 /* Has Transaction Memory (ISA 2.07) */ 640 POWERPC_FLAG_TM = 0x00100000, 641 /* Has SCV (ISA 3.00) */ 642 POWERPC_FLAG_SCV = 0x00200000, 643 }; 644 645 /* 646 * Bits for env->hflags. 647 * 648 * Most of these bits overlap with corresponding bits in MSR, 649 * but some come from other sources. Those that do come from 650 * the MSR are validated in hreg_compute_hflags. 651 */ 652 enum { 653 HFLAGS_LE = 0, /* MSR_LE */ 654 HFLAGS_HV = 1, /* computed from MSR_HV and other state */ 655 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ 656 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ 657 HFLAGS_DR = 4, /* MSR_DR */ 658 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */ 659 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ 660 HFLAGS_TM = 8, /* computed from MSR_TM */ 661 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ 662 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ 663 HFLAGS_FP = 13, /* MSR_FP */ 664 HFLAGS_PR = 14, /* MSR_PR */ 665 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */ 666 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */ 667 HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */ 668 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ 669 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ 670 671 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */ 672 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */ 673 }; 674 675 /*****************************************************************************/ 676 /* Floating point status and control register */ 677 #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */ 678 #define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */ 679 #define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */ 680 #define FPSCR_FX 31 /* Floating-point exception summary */ 681 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ 682 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ 683 #define FPSCR_OX 28 /* Floating-point overflow exception */ 684 #define FPSCR_UX 27 /* Floating-point underflow exception */ 685 #define FPSCR_ZX 26 /* Floating-point zero divide exception */ 686 #define FPSCR_XX 25 /* Floating-point inexact exception */ 687 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ 688 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ 689 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ 690 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ 691 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ 692 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ 693 #define FPSCR_FR 18 /* Floating-point fraction rounded */ 694 #define FPSCR_FI 17 /* Floating-point fraction inexact */ 695 #define FPSCR_C 16 /* Floating-point result class descriptor */ 696 #define FPSCR_FL 15 /* Floating-point less than or negative */ 697 #define FPSCR_FG 14 /* Floating-point greater than or negative */ 698 #define FPSCR_FE 13 /* Floating-point equal or zero */ 699 #define FPSCR_FU 12 /* Floating-point unordered or NaN */ 700 #define FPSCR_FPCC 12 /* Floating-point condition code */ 701 #define FPSCR_FPRF 12 /* Floating-point result flags */ 702 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ 703 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ 704 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ 705 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ 706 #define FPSCR_OE 6 /* Floating-point overflow exception enable */ 707 #define FPSCR_UE 5 /* Floating-point underflow exception enable */ 708 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ 709 #define FPSCR_XE 3 /* Floating-point inexact exception enable */ 710 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ 711 #define FPSCR_RN1 1 712 #define FPSCR_RN0 0 /* Floating-point rounding control */ 713 #define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0) 714 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) 715 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) 716 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) 717 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) 718 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) 719 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) 720 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) 721 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) 722 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) 723 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) 724 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) 725 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) 726 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) 727 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) 728 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) 729 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) 730 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) 731 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) 732 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) 733 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) 734 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) 735 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) 736 #define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3) 737 /* Invalid operation exception summary */ 738 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ 739 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ 740 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ 741 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ 742 (1 << FPSCR_VXCVI)) 743 /* exception summary */ 744 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) 745 /* enabled exception summary */ 746 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ 747 0x1F) 748 749 #define FP_DRN2 (1ull << FPSCR_DRN2) 750 #define FP_DRN1 (1ull << FPSCR_DRN1) 751 #define FP_DRN0 (1ull << FPSCR_DRN0) 752 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0) 753 #define FP_FX (1ull << FPSCR_FX) 754 #define FP_FEX (1ull << FPSCR_FEX) 755 #define FP_VX (1ull << FPSCR_VX) 756 #define FP_OX (1ull << FPSCR_OX) 757 #define FP_UX (1ull << FPSCR_UX) 758 #define FP_ZX (1ull << FPSCR_ZX) 759 #define FP_XX (1ull << FPSCR_XX) 760 #define FP_VXSNAN (1ull << FPSCR_VXSNAN) 761 #define FP_VXISI (1ull << FPSCR_VXISI) 762 #define FP_VXIDI (1ull << FPSCR_VXIDI) 763 #define FP_VXZDZ (1ull << FPSCR_VXZDZ) 764 #define FP_VXIMZ (1ull << FPSCR_VXIMZ) 765 #define FP_VXVC (1ull << FPSCR_VXVC) 766 #define FP_FR (1ull << FPSCR_FR) 767 #define FP_FI (1ull << FPSCR_FI) 768 #define FP_C (1ull << FPSCR_C) 769 #define FP_FL (1ull << FPSCR_FL) 770 #define FP_FG (1ull << FPSCR_FG) 771 #define FP_FE (1ull << FPSCR_FE) 772 #define FP_FU (1ull << FPSCR_FU) 773 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU) 774 #define FP_FPRF (FP_C | FP_FPCC) 775 #define FP_VXSOFT (1ull << FPSCR_VXSOFT) 776 #define FP_VXSQRT (1ull << FPSCR_VXSQRT) 777 #define FP_VXCVI (1ull << FPSCR_VXCVI) 778 #define FP_VE (1ull << FPSCR_VE) 779 #define FP_OE (1ull << FPSCR_OE) 780 #define FP_UE (1ull << FPSCR_UE) 781 #define FP_ZE (1ull << FPSCR_ZE) 782 #define FP_XE (1ull << FPSCR_XE) 783 #define FP_NI (1ull << FPSCR_NI) 784 #define FP_RN1 (1ull << FPSCR_RN1) 785 #define FP_RN0 (1ull << FPSCR_RN0) 786 #define FP_RN (FP_RN1 | FP_RN0) 787 788 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE) 789 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF) 790 791 /* the exception bits which can be cleared by mcrfs - includes FX */ 792 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \ 793 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \ 794 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ 795 FP_VXSQRT | FP_VXCVI) 796 797 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ 798 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \ 799 FP_FEX | FP_VX | PPC_BIT(52))) 800 801 /*****************************************************************************/ 802 /* Vector status and control register */ 803 #define VSCR_NJ 16 /* Vector non-java */ 804 #define VSCR_SAT 0 /* Vector saturation */ 805 806 /*****************************************************************************/ 807 /* BookE e500 MMU registers */ 808 809 #define MAS0_NV_SHIFT 0 810 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) 811 812 #define MAS0_WQ_SHIFT 12 813 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) 814 /* Write TLB entry regardless of reservation */ 815 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) 816 /* Write TLB entry only already in use */ 817 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) 818 /* Clear TLB entry */ 819 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) 820 821 #define MAS0_HES_SHIFT 14 822 #define MAS0_HES (1 << MAS0_HES_SHIFT) 823 824 #define MAS0_ESEL_SHIFT 16 825 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) 826 827 #define MAS0_TLBSEL_SHIFT 28 828 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) 829 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) 830 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) 831 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) 832 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) 833 834 #define MAS0_ATSEL_SHIFT 31 835 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) 836 #define MAS0_ATSEL_TLB 0 837 #define MAS0_ATSEL_LRAT MAS0_ATSEL 838 839 #define MAS1_TSIZE_SHIFT 7 840 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) 841 842 #define MAS1_TS_SHIFT 12 843 #define MAS1_TS (1 << MAS1_TS_SHIFT) 844 845 #define MAS1_IND_SHIFT 13 846 #define MAS1_IND (1 << MAS1_IND_SHIFT) 847 848 #define MAS1_TID_SHIFT 16 849 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) 850 851 #define MAS1_IPROT_SHIFT 30 852 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) 853 854 #define MAS1_VALID_SHIFT 31 855 #define MAS1_VALID 0x80000000 856 857 #define MAS2_EPN_SHIFT 12 858 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT) 859 860 #define MAS2_ACM_SHIFT 6 861 #define MAS2_ACM (1 << MAS2_ACM_SHIFT) 862 863 #define MAS2_VLE_SHIFT 5 864 #define MAS2_VLE (1 << MAS2_VLE_SHIFT) 865 866 #define MAS2_W_SHIFT 4 867 #define MAS2_W (1 << MAS2_W_SHIFT) 868 869 #define MAS2_I_SHIFT 3 870 #define MAS2_I (1 << MAS2_I_SHIFT) 871 872 #define MAS2_M_SHIFT 2 873 #define MAS2_M (1 << MAS2_M_SHIFT) 874 875 #define MAS2_G_SHIFT 1 876 #define MAS2_G (1 << MAS2_G_SHIFT) 877 878 #define MAS2_E_SHIFT 0 879 #define MAS2_E (1 << MAS2_E_SHIFT) 880 881 #define MAS3_RPN_SHIFT 12 882 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) 883 884 #define MAS3_U0 0x00000200 885 #define MAS3_U1 0x00000100 886 #define MAS3_U2 0x00000080 887 #define MAS3_U3 0x00000040 888 #define MAS3_UX 0x00000020 889 #define MAS3_SX 0x00000010 890 #define MAS3_UW 0x00000008 891 #define MAS3_SW 0x00000004 892 #define MAS3_UR 0x00000002 893 #define MAS3_SR 0x00000001 894 #define MAS3_SPSIZE_SHIFT 1 895 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) 896 897 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT 898 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK 899 #define MAS4_TIDSELD_MASK 0x00030000 900 #define MAS4_TIDSELD_PID0 0x00000000 901 #define MAS4_TIDSELD_PID1 0x00010000 902 #define MAS4_TIDSELD_PID2 0x00020000 903 #define MAS4_TIDSELD_PIDZ 0x00030000 904 #define MAS4_INDD 0x00008000 /* Default IND */ 905 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT 906 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK 907 #define MAS4_ACMD 0x00000040 908 #define MAS4_VLED 0x00000020 909 #define MAS4_WD 0x00000010 910 #define MAS4_ID 0x00000008 911 #define MAS4_MD 0x00000004 912 #define MAS4_GD 0x00000002 913 #define MAS4_ED 0x00000001 914 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 915 #define MAS4_WIMGED_SHIFT 0 916 917 #define MAS5_SGS 0x80000000 918 #define MAS5_SLPID_MASK 0x00000fff 919 920 #define MAS6_SPID0 0x3fff0000 921 #define MAS6_SPID1 0x00007ffe 922 #define MAS6_ISIZE(x) MAS1_TSIZE(x) 923 #define MAS6_SAS 0x00000001 924 #define MAS6_SPID MAS6_SPID0 925 #define MAS6_SIND 0x00000002 /* Indirect page */ 926 #define MAS6_SIND_SHIFT 1 927 #define MAS6_SPID_MASK 0x3fff0000 928 #define MAS6_SPID_SHIFT 16 929 #define MAS6_ISIZE_MASK 0x00000f80 930 #define MAS6_ISIZE_SHIFT 7 931 932 #define MAS7_RPN 0xffffffff 933 934 #define MAS8_TGS 0x80000000 935 #define MAS8_VF 0x40000000 936 #define MAS8_TLBPID 0x00000fff 937 938 /* Bit definitions for MMUCFG */ 939 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 940 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 941 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 942 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 943 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 944 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 945 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 946 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 947 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 948 949 /* Bit definitions for MMUCSR0 */ 950 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 951 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 952 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 953 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 954 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 955 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 956 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 957 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 958 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 959 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 960 961 /* TLBnCFG encoding */ 962 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 963 #define TLBnCFG_HES 0x00002000 /* HW select supported */ 964 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */ 965 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 966 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 967 #define TLBnCFG_IND 0x00020000 /* IND entries supported */ 968 #define TLBnCFG_PT 0x00040000 /* Can load from page table */ 969 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 970 #define TLBnCFG_MINSIZE_SHIFT 20 971 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 972 #define TLBnCFG_MAXSIZE_SHIFT 16 973 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 974 #define TLBnCFG_ASSOC_SHIFT 24 975 976 /* TLBnPS encoding */ 977 #define TLBnPS_4K 0x00000004 978 #define TLBnPS_8K 0x00000008 979 #define TLBnPS_16K 0x00000010 980 #define TLBnPS_32K 0x00000020 981 #define TLBnPS_64K 0x00000040 982 #define TLBnPS_128K 0x00000080 983 #define TLBnPS_256K 0x00000100 984 #define TLBnPS_512K 0x00000200 985 #define TLBnPS_1M 0x00000400 986 #define TLBnPS_2M 0x00000800 987 #define TLBnPS_4M 0x00001000 988 #define TLBnPS_8M 0x00002000 989 #define TLBnPS_16M 0x00004000 990 #define TLBnPS_32M 0x00008000 991 #define TLBnPS_64M 0x00010000 992 #define TLBnPS_128M 0x00020000 993 #define TLBnPS_256M 0x00040000 994 #define TLBnPS_512M 0x00080000 995 #define TLBnPS_1G 0x00100000 996 #define TLBnPS_2G 0x00200000 997 #define TLBnPS_4G 0x00400000 998 #define TLBnPS_8G 0x00800000 999 #define TLBnPS_16G 0x01000000 1000 #define TLBnPS_32G 0x02000000 1001 #define TLBnPS_64G 0x04000000 1002 #define TLBnPS_128G 0x08000000 1003 #define TLBnPS_256G 0x10000000 1004 1005 /* tlbilx action encoding */ 1006 #define TLBILX_T_ALL 0 1007 #define TLBILX_T_TID 1 1008 #define TLBILX_T_FULLMATCH 3 1009 #define TLBILX_T_CLASS0 4 1010 #define TLBILX_T_CLASS1 5 1011 #define TLBILX_T_CLASS2 6 1012 #define TLBILX_T_CLASS3 7 1013 1014 /* BookE 2.06 helper defines */ 1015 1016 #define BOOKE206_FLUSH_TLB0 (1 << 0) 1017 #define BOOKE206_FLUSH_TLB1 (1 << 1) 1018 #define BOOKE206_FLUSH_TLB2 (1 << 2) 1019 #define BOOKE206_FLUSH_TLB3 (1 << 3) 1020 1021 /* number of possible TLBs */ 1022 #define BOOKE206_MAX_TLBN 4 1023 1024 #define EPID_EPID_SHIFT 0x0 1025 #define EPID_EPID 0xFF 1026 #define EPID_ELPID_SHIFT 0x10 1027 #define EPID_ELPID 0x3F0000 1028 #define EPID_EGS 0x20000000 1029 #define EPID_EGS_SHIFT 29 1030 #define EPID_EAS 0x40000000 1031 #define EPID_EAS_SHIFT 30 1032 #define EPID_EPR 0x80000000 1033 #define EPID_EPR_SHIFT 31 1034 /* We don't support EGS and ELPID */ 1035 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR) 1036 1037 /*****************************************************************************/ 1038 /* Server and Embedded Processor Control */ 1039 1040 #define DBELL_TYPE_SHIFT 27 1041 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT) 1042 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT) 1043 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT) 1044 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT) 1045 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT) 1046 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT) 1047 1048 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT) 1049 1050 #define DBELL_BRDCAST PPC_BIT(37) 1051 #define DBELL_LPIDTAG_SHIFT 14 1052 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) 1053 #define DBELL_PIRTAG_MASK 0x3fff 1054 1055 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63) 1056 1057 #define PPC_PAGE_SIZES_MAX_SZ 8 1058 1059 struct ppc_radix_page_info { 1060 uint32_t count; 1061 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; 1062 }; 1063 1064 /*****************************************************************************/ 1065 /* The whole PowerPC CPU context */ 1066 1067 /* 1068 * PowerPC needs eight modes for different hypervisor/supervisor/guest 1069 * + real/paged mode combinations. The other two modes are for 1070 * external PID load/store. 1071 */ 1072 #define PPC_TLB_EPID_LOAD 8 1073 #define PPC_TLB_EPID_STORE 9 1074 1075 #define PPC_CPU_OPCODES_LEN 0x40 1076 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 1077 1078 struct CPUPPCState { 1079 /* Most commonly used resources during translated code execution first */ 1080 target_ulong gpr[32]; /* general purpose registers */ 1081 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */ 1082 target_ulong lr; 1083 target_ulong ctr; 1084 uint32_t crf[8]; /* condition register */ 1085 #if defined(TARGET_PPC64) 1086 target_ulong cfar; 1087 #endif 1088 target_ulong xer; /* XER (with SO, OV, CA split out) */ 1089 target_ulong so; 1090 target_ulong ov; 1091 target_ulong ca; 1092 target_ulong ov32; 1093 target_ulong ca32; 1094 1095 target_ulong reserve_addr; /* Reservation address */ 1096 target_ulong reserve_val; /* Reservation value */ 1097 target_ulong reserve_val2; 1098 1099 /* These are used in supervisor mode only */ 1100 target_ulong msr; /* machine state register */ 1101 target_ulong tgpr[4]; /* temporary general purpose registers, */ 1102 /* used to speed-up TLB assist handlers */ 1103 1104 target_ulong nip; /* next instruction pointer */ 1105 uint64_t retxh; /* high part of 128-bit helper return */ 1106 1107 /* when a memory exception occurs, the access type is stored here */ 1108 int access_type; 1109 1110 #if !defined(CONFIG_USER_ONLY) 1111 /* MMU context, only relevant for full system emulation */ 1112 #if defined(TARGET_PPC64) 1113 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ 1114 #endif 1115 target_ulong sr[32]; /* segment registers */ 1116 uint32_t nb_BATs; /* number of BATs */ 1117 target_ulong DBAT[2][8]; 1118 target_ulong IBAT[2][8]; 1119 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ 1120 int32_t nb_tlb; /* Total number of TLB */ 1121 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ 1122 int nb_ways; /* Number of ways in the TLB set */ 1123 int last_way; /* Last used way used to allocate TLB in a LRU way */ 1124 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ 1125 int nb_pids; /* Number of available PID registers */ 1126 int tlb_type; /* Type of TLB we're dealing with */ 1127 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ 1128 bool tlb_dirty; /* Set to non-zero when modifying TLB */ 1129 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ 1130 uint32_t tlb_need_flush; /* Delayed flush needed */ 1131 #define TLB_NEED_LOCAL_FLUSH 0x1 1132 #define TLB_NEED_GLOBAL_FLUSH 0x2 1133 #endif 1134 1135 /* Other registers */ 1136 target_ulong spr[1024]; /* special purpose registers */ 1137 ppc_spr_t spr_cb[1024]; 1138 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */ 1139 uint8_t pmc_ins_cnt; 1140 uint8_t pmc_cyc_cnt; 1141 /* Vector status and control register, minus VSCR_SAT */ 1142 uint32_t vscr; 1143 /* VSX registers (including FP and AVR) */ 1144 ppc_vsr_t vsr[64] QEMU_ALIGNED(16); 1145 /* Non-zero if and only if VSCR_SAT should be set */ 1146 ppc_vsr_t vscr_sat QEMU_ALIGNED(16); 1147 /* SPE registers */ 1148 uint64_t spe_acc; 1149 uint32_t spe_fscr; 1150 /* SPE and Altivec share status as they'll never be used simultaneously */ 1151 float_status vec_status; 1152 float_status fp_status; /* Floating point execution context */ 1153 target_ulong fpscr; /* Floating point status and control register */ 1154 1155 /* Internal devices resources */ 1156 ppc_tb_t *tb_env; /* Time base and decrementer */ 1157 ppc_dcr_t *dcr_env; /* Device control registers */ 1158 1159 int dcache_line_size; 1160 int icache_line_size; 1161 1162 /* These resources are used during exception processing */ 1163 /* CPU model definition */ 1164 target_ulong msr_mask; 1165 powerpc_mmu_t mmu_model; 1166 powerpc_excp_t excp_model; 1167 powerpc_input_t bus_model; 1168 int bfd_mach; 1169 uint32_t flags; 1170 uint64_t insns_flags; 1171 uint64_t insns_flags2; 1172 1173 int error_code; 1174 uint32_t pending_interrupts; 1175 #if !defined(CONFIG_USER_ONLY) 1176 /* 1177 * This is the IRQ controller, which is implementation dependent and only 1178 * relevant when emulating a complete machine. Note that this isn't used 1179 * by recent Book3s compatible CPUs (POWER7 and newer). 1180 */ 1181 uint32_t irq_input_state; 1182 void **irq_inputs; 1183 1184 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */ 1185 target_ulong excp_prefix; 1186 target_ulong ivor_mask; 1187 target_ulong ivpr_mask; 1188 target_ulong hreset_vector; 1189 hwaddr mpic_iack; 1190 bool mpic_proxy; /* true if the external proxy facility mode is enabled */ 1191 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */ 1192 /* instructions and SPRs are diallowed if MSR:HV is 0 */ 1193 /* 1194 * On P7/P8/P9, set when in PM state so we need to handle resume in a 1195 * special way (such as routing some resume causes to 0x100, i.e. sreset). 1196 */ 1197 bool resume_as_sreset; 1198 #endif 1199 1200 /* These resources are used only in TCG */ 1201 uint32_t hflags; 1202 target_ulong hflags_compat_nmsr; /* for migration compatibility */ 1203 1204 /* Power management */ 1205 int (*check_pow)(CPUPPCState *env); 1206 1207 #if !defined(CONFIG_USER_ONLY) 1208 void *load_info; /* holds boot loading state */ 1209 #endif 1210 1211 /* booke timers */ 1212 1213 /* 1214 * Specifies bit locations of the Time Base used to signal a fixed timer 1215 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer) 1216 * 1217 * 0 selects the least significant bit, 63 selects the most significant bit 1218 */ 1219 uint8_t fit_period[4]; 1220 uint8_t wdt_period[4]; 1221 1222 /* Transactional memory state */ 1223 target_ulong tm_gpr[32]; 1224 ppc_avr_t tm_vsr[64]; 1225 uint64_t tm_cr; 1226 uint64_t tm_lr; 1227 uint64_t tm_ctr; 1228 uint64_t tm_fpscr; 1229 uint64_t tm_amr; 1230 uint64_t tm_ppr; 1231 uint64_t tm_vrsave; 1232 uint32_t tm_vscr; 1233 uint64_t tm_dscr; 1234 uint64_t tm_tar; 1235 1236 /* 1237 * Timers used to fire performance monitor alerts 1238 * when counting cycles. 1239 */ 1240 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM]; 1241 1242 /* 1243 * PMU base time value used by the PMU to calculate 1244 * running cycles. 1245 */ 1246 uint64_t pmu_base_time; 1247 }; 1248 1249 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ 1250 do { \ 1251 env->fit_period[0] = (a_); \ 1252 env->fit_period[1] = (b_); \ 1253 env->fit_period[2] = (c_); \ 1254 env->fit_period[3] = (d_); \ 1255 } while (0) 1256 1257 #define SET_WDT_PERIOD(a_, b_, c_, d_) \ 1258 do { \ 1259 env->wdt_period[0] = (a_); \ 1260 env->wdt_period[1] = (b_); \ 1261 env->wdt_period[2] = (c_); \ 1262 env->wdt_period[3] = (d_); \ 1263 } while (0) 1264 1265 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; 1266 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; 1267 1268 /** 1269 * PowerPCCPU: 1270 * @env: #CPUPPCState 1271 * @vcpu_id: vCPU identifier given to KVM 1272 * @compat_pvr: Current logical PVR, zero if in "raw" mode 1273 * 1274 * A PowerPC CPU. 1275 */ 1276 struct PowerPCCPU { 1277 /*< private >*/ 1278 CPUState parent_obj; 1279 /*< public >*/ 1280 1281 CPUNegativeOffsetState neg; 1282 CPUPPCState env; 1283 1284 int vcpu_id; 1285 uint32_t compat_pvr; 1286 PPCVirtualHypervisor *vhyp; 1287 void *machine_data; 1288 int32_t node_id; /* NUMA node this CPU belongs to */ 1289 PPCHash64Options *hash64_opts; 1290 1291 /* Those resources are used only during code translation */ 1292 /* opcode handlers */ 1293 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; 1294 1295 /* Fields related to migration compatibility hacks */ 1296 bool pre_2_8_migration; 1297 target_ulong mig_msr_mask; 1298 uint64_t mig_insns_flags; 1299 uint64_t mig_insns_flags2; 1300 uint32_t mig_nb_BATs; 1301 bool pre_2_10_migration; 1302 bool pre_3_0_migration; 1303 int32_t mig_slb_nr; 1304 }; 1305 1306 1307 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); 1308 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); 1309 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc); 1310 1311 #ifndef CONFIG_USER_ONLY 1312 struct PPCVirtualHypervisorClass { 1313 InterfaceClass parent; 1314 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); 1315 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp); 1316 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp, 1317 hwaddr ptex, int n); 1318 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp, 1319 const ppc_hash_pte64_t *hptes, 1320 hwaddr ptex, int n); 1321 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1); 1322 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1); 1323 void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry); 1324 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp); 1325 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); 1326 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); 1327 }; 1328 1329 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor" 1330 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass, 1331 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR) 1332 #endif /* CONFIG_USER_ONLY */ 1333 1334 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 1335 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1336 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1337 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg); 1338 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1339 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); 1340 #ifndef CONFIG_USER_ONLY 1341 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); 1342 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); 1343 #endif 1344 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1345 int cpuid, void *opaque); 1346 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1347 int cpuid, void *opaque); 1348 #ifndef CONFIG_USER_ONLY 1349 void ppc_cpu_do_interrupt(CPUState *cpu); 1350 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); 1351 void ppc_cpu_do_system_reset(CPUState *cs); 1352 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); 1353 extern const VMStateDescription vmstate_ppc_cpu; 1354 #endif 1355 1356 /*****************************************************************************/ 1357 void ppc_translate_init(void); 1358 1359 #if !defined(CONFIG_USER_ONLY) 1360 void ppc_store_sdr1(CPUPPCState *env, target_ulong value); 1361 #endif /* !defined(CONFIG_USER_ONLY) */ 1362 void ppc_store_msr(CPUPPCState *env, target_ulong value); 1363 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); 1364 1365 void ppc_cpu_list(void); 1366 1367 /* Time-base and decrementer management */ 1368 #ifndef NO_CPU_IO_DEFS 1369 uint64_t cpu_ppc_load_tbl(CPUPPCState *env); 1370 uint32_t cpu_ppc_load_tbu(CPUPPCState *env); 1371 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value); 1372 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value); 1373 uint64_t cpu_ppc_load_atbl(CPUPPCState *env); 1374 uint32_t cpu_ppc_load_atbu(CPUPPCState *env); 1375 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value); 1376 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value); 1377 uint64_t cpu_ppc_load_vtb(CPUPPCState *env); 1378 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value); 1379 bool ppc_decr_clear_on_delivery(CPUPPCState *env); 1380 target_ulong cpu_ppc_load_decr(CPUPPCState *env); 1381 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); 1382 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env); 1383 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value); 1384 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value); 1385 uint64_t cpu_ppc_load_purr(CPUPPCState *env); 1386 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value); 1387 #if !defined(CONFIG_USER_ONLY) 1388 target_ulong load_40x_pit(CPUPPCState *env); 1389 void store_40x_pit(CPUPPCState *env, target_ulong val); 1390 void store_40x_dbcr0(CPUPPCState *env, uint32_t val); 1391 void store_40x_sler(CPUPPCState *env, uint32_t val); 1392 void store_40x_tcr(CPUPPCState *env, target_ulong val); 1393 void store_40x_tsr(CPUPPCState *env, target_ulong val); 1394 void store_booke_tcr(CPUPPCState *env, target_ulong val); 1395 void store_booke_tsr(CPUPPCState *env, target_ulong val); 1396 void ppc_tlb_invalidate_all(CPUPPCState *env); 1397 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr); 1398 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); 1399 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, 1400 hwaddr *raddrp, target_ulong address, 1401 uint32_t pid); 1402 int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, 1403 hwaddr *raddrp, 1404 target_ulong address, uint32_t pid, int ext, 1405 int i); 1406 hwaddr booke206_tlb_to_page_size(CPUPPCState *env, 1407 ppcmas_tlb_t *tlb); 1408 #endif 1409 #endif 1410 1411 void ppc_store_fpscr(CPUPPCState *env, target_ulong val); 1412 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, 1413 const char *caller, uint32_t cause); 1414 1415 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) 1416 { 1417 uint64_t gprv; 1418 1419 gprv = env->gpr[gprn]; 1420 if (env->flags & POWERPC_FLAG_SPE) { 1421 /* 1422 * If the CPU implements the SPE extension, we have to get the 1423 * high bits of the GPR from the gprh storage area 1424 */ 1425 gprv &= 0xFFFFFFFFULL; 1426 gprv |= (uint64_t)env->gprh[gprn] << 32; 1427 } 1428 1429 return gprv; 1430 } 1431 1432 /* Device control registers */ 1433 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); 1434 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); 1435 1436 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 1437 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 1438 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU 1439 1440 #define cpu_list ppc_cpu_list 1441 1442 /* MMU modes definitions */ 1443 #define MMU_USER_IDX 0 1444 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) 1445 { 1446 #ifdef CONFIG_USER_ONLY 1447 return MMU_USER_IDX; 1448 #else 1449 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; 1450 #endif 1451 } 1452 1453 /* Compatibility modes */ 1454 #if defined(TARGET_PPC64) 1455 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, 1456 uint32_t min_compat_pvr, uint32_t max_compat_pvr); 1457 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr, 1458 uint32_t min_compat_pvr, uint32_t max_compat_pvr); 1459 1460 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp); 1461 1462 #if !defined(CONFIG_USER_ONLY) 1463 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp); 1464 #endif 1465 int ppc_compat_max_vthreads(PowerPCCPU *cpu); 1466 void ppc_compat_add_property(Object *obj, const char *name, 1467 uint32_t *compat_pvr, const char *basedesc); 1468 #endif /* defined(TARGET_PPC64) */ 1469 1470 typedef CPUPPCState CPUArchState; 1471 typedef PowerPCCPU ArchCPU; 1472 1473 #include "exec/cpu-all.h" 1474 1475 /*****************************************************************************/ 1476 /* CRF definitions */ 1477 #define CRF_LT_BIT 3 1478 #define CRF_GT_BIT 2 1479 #define CRF_EQ_BIT 1 1480 #define CRF_SO_BIT 0 1481 #define CRF_LT (1 << CRF_LT_BIT) 1482 #define CRF_GT (1 << CRF_GT_BIT) 1483 #define CRF_EQ (1 << CRF_EQ_BIT) 1484 #define CRF_SO (1 << CRF_SO_BIT) 1485 /* For SPE extensions */ 1486 #define CRF_CH (1 << CRF_LT_BIT) 1487 #define CRF_CL (1 << CRF_GT_BIT) 1488 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT) 1489 #define CRF_CH_AND_CL (1 << CRF_SO_BIT) 1490 1491 /* XER definitions */ 1492 #define XER_SO 31 1493 #define XER_OV 30 1494 #define XER_CA 29 1495 #define XER_OV32 19 1496 #define XER_CA32 18 1497 #define XER_CMP 8 1498 #define XER_BC 0 1499 #define xer_so (env->so) 1500 #define xer_ov (env->ov) 1501 #define xer_ca (env->ca) 1502 #define xer_ov32 (env->ov) 1503 #define xer_ca32 (env->ca) 1504 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) 1505 #define xer_bc ((env->xer >> XER_BC) & 0x7F) 1506 1507 /* SPR definitions */ 1508 #define SPR_MQ (0x000) 1509 #define SPR_XER (0x001) 1510 #define SPR_LR (0x008) 1511 #define SPR_CTR (0x009) 1512 #define SPR_UAMR (0x00D) 1513 #define SPR_DSCR (0x011) 1514 #define SPR_DSISR (0x012) 1515 #define SPR_DAR (0x013) 1516 #define SPR_DECR (0x016) 1517 #define SPR_SDR1 (0x019) 1518 #define SPR_SRR0 (0x01A) 1519 #define SPR_SRR1 (0x01B) 1520 #define SPR_CFAR (0x01C) 1521 #define SPR_AMR (0x01D) 1522 #define SPR_ACOP (0x01F) 1523 #define SPR_BOOKE_PID (0x030) 1524 #define SPR_BOOKS_PID (0x030) 1525 #define SPR_BOOKE_DECAR (0x036) 1526 #define SPR_BOOKE_CSRR0 (0x03A) 1527 #define SPR_BOOKE_CSRR1 (0x03B) 1528 #define SPR_BOOKE_DEAR (0x03D) 1529 #define SPR_IAMR (0x03D) 1530 #define SPR_BOOKE_ESR (0x03E) 1531 #define SPR_BOOKE_IVPR (0x03F) 1532 #define SPR_MPC_EIE (0x050) 1533 #define SPR_MPC_EID (0x051) 1534 #define SPR_MPC_NRI (0x052) 1535 #define SPR_TFHAR (0x080) 1536 #define SPR_TFIAR (0x081) 1537 #define SPR_TEXASR (0x082) 1538 #define SPR_TEXASRU (0x083) 1539 #define SPR_UCTRL (0x088) 1540 #define SPR_TIDR (0x090) 1541 #define SPR_MPC_CMPA (0x090) 1542 #define SPR_MPC_CMPB (0x091) 1543 #define SPR_MPC_CMPC (0x092) 1544 #define SPR_MPC_CMPD (0x093) 1545 #define SPR_MPC_ECR (0x094) 1546 #define SPR_MPC_DER (0x095) 1547 #define SPR_MPC_COUNTA (0x096) 1548 #define SPR_MPC_COUNTB (0x097) 1549 #define SPR_CTRL (0x098) 1550 #define SPR_MPC_CMPE (0x098) 1551 #define SPR_MPC_CMPF (0x099) 1552 #define SPR_FSCR (0x099) 1553 #define SPR_MPC_CMPG (0x09A) 1554 #define SPR_MPC_CMPH (0x09B) 1555 #define SPR_MPC_LCTRL1 (0x09C) 1556 #define SPR_MPC_LCTRL2 (0x09D) 1557 #define SPR_UAMOR (0x09D) 1558 #define SPR_MPC_ICTRL (0x09E) 1559 #define SPR_MPC_BAR (0x09F) 1560 #define SPR_PSPB (0x09F) 1561 #define SPR_DPDES (0x0B0) 1562 #define SPR_DAWR0 (0x0B4) 1563 #define SPR_RPR (0x0BA) 1564 #define SPR_CIABR (0x0BB) 1565 #define SPR_DAWRX0 (0x0BC) 1566 #define SPR_HFSCR (0x0BE) 1567 #define SPR_VRSAVE (0x100) 1568 #define SPR_USPRG0 (0x100) 1569 #define SPR_USPRG1 (0x101) 1570 #define SPR_USPRG2 (0x102) 1571 #define SPR_USPRG3 (0x103) 1572 #define SPR_USPRG4 (0x104) 1573 #define SPR_USPRG5 (0x105) 1574 #define SPR_USPRG6 (0x106) 1575 #define SPR_USPRG7 (0x107) 1576 #define SPR_VTBL (0x10C) 1577 #define SPR_VTBU (0x10D) 1578 #define SPR_SPRG0 (0x110) 1579 #define SPR_SPRG1 (0x111) 1580 #define SPR_SPRG2 (0x112) 1581 #define SPR_SPRG3 (0x113) 1582 #define SPR_SPRG4 (0x114) 1583 #define SPR_SCOMC (0x114) 1584 #define SPR_SPRG5 (0x115) 1585 #define SPR_SCOMD (0x115) 1586 #define SPR_SPRG6 (0x116) 1587 #define SPR_SPRG7 (0x117) 1588 #define SPR_ASR (0x118) 1589 #define SPR_EAR (0x11A) 1590 #define SPR_TBL (0x11C) 1591 #define SPR_TBU (0x11D) 1592 #define SPR_TBU40 (0x11E) 1593 #define SPR_SVR (0x11E) 1594 #define SPR_BOOKE_PIR (0x11E) 1595 #define SPR_PVR (0x11F) 1596 #define SPR_HSPRG0 (0x130) 1597 #define SPR_BOOKE_DBSR (0x130) 1598 #define SPR_HSPRG1 (0x131) 1599 #define SPR_HDSISR (0x132) 1600 #define SPR_HDAR (0x133) 1601 #define SPR_BOOKE_EPCR (0x133) 1602 #define SPR_SPURR (0x134) 1603 #define SPR_BOOKE_DBCR0 (0x134) 1604 #define SPR_IBCR (0x135) 1605 #define SPR_PURR (0x135) 1606 #define SPR_BOOKE_DBCR1 (0x135) 1607 #define SPR_DBCR (0x136) 1608 #define SPR_HDEC (0x136) 1609 #define SPR_BOOKE_DBCR2 (0x136) 1610 #define SPR_HIOR (0x137) 1611 #define SPR_MBAR (0x137) 1612 #define SPR_RMOR (0x138) 1613 #define SPR_BOOKE_IAC1 (0x138) 1614 #define SPR_HRMOR (0x139) 1615 #define SPR_BOOKE_IAC2 (0x139) 1616 #define SPR_HSRR0 (0x13A) 1617 #define SPR_BOOKE_IAC3 (0x13A) 1618 #define SPR_HSRR1 (0x13B) 1619 #define SPR_BOOKE_IAC4 (0x13B) 1620 #define SPR_BOOKE_DAC1 (0x13C) 1621 #define SPR_MMCRH (0x13C) 1622 #define SPR_DABR2 (0x13D) 1623 #define SPR_BOOKE_DAC2 (0x13D) 1624 #define SPR_TFMR (0x13D) 1625 #define SPR_BOOKE_DVC1 (0x13E) 1626 #define SPR_LPCR (0x13E) 1627 #define SPR_BOOKE_DVC2 (0x13F) 1628 #define SPR_LPIDR (0x13F) 1629 #define SPR_BOOKE_TSR (0x150) 1630 #define SPR_HMER (0x150) 1631 #define SPR_HMEER (0x151) 1632 #define SPR_PCR (0x152) 1633 #define SPR_BOOKE_LPIDR (0x152) 1634 #define SPR_BOOKE_TCR (0x154) 1635 #define SPR_BOOKE_TLB0PS (0x158) 1636 #define SPR_BOOKE_TLB1PS (0x159) 1637 #define SPR_BOOKE_TLB2PS (0x15A) 1638 #define SPR_BOOKE_TLB3PS (0x15B) 1639 #define SPR_AMOR (0x15D) 1640 #define SPR_BOOKE_MAS7_MAS3 (0x174) 1641 #define SPR_BOOKE_IVOR0 (0x190) 1642 #define SPR_BOOKE_IVOR1 (0x191) 1643 #define SPR_BOOKE_IVOR2 (0x192) 1644 #define SPR_BOOKE_IVOR3 (0x193) 1645 #define SPR_BOOKE_IVOR4 (0x194) 1646 #define SPR_BOOKE_IVOR5 (0x195) 1647 #define SPR_BOOKE_IVOR6 (0x196) 1648 #define SPR_BOOKE_IVOR7 (0x197) 1649 #define SPR_BOOKE_IVOR8 (0x198) 1650 #define SPR_BOOKE_IVOR9 (0x199) 1651 #define SPR_BOOKE_IVOR10 (0x19A) 1652 #define SPR_BOOKE_IVOR11 (0x19B) 1653 #define SPR_BOOKE_IVOR12 (0x19C) 1654 #define SPR_BOOKE_IVOR13 (0x19D) 1655 #define SPR_BOOKE_IVOR14 (0x19E) 1656 #define SPR_BOOKE_IVOR15 (0x19F) 1657 #define SPR_BOOKE_IVOR38 (0x1B0) 1658 #define SPR_BOOKE_IVOR39 (0x1B1) 1659 #define SPR_BOOKE_IVOR40 (0x1B2) 1660 #define SPR_BOOKE_IVOR41 (0x1B3) 1661 #define SPR_BOOKE_IVOR42 (0x1B4) 1662 #define SPR_BOOKE_GIVOR2 (0x1B8) 1663 #define SPR_BOOKE_GIVOR3 (0x1B9) 1664 #define SPR_BOOKE_GIVOR4 (0x1BA) 1665 #define SPR_BOOKE_GIVOR8 (0x1BB) 1666 #define SPR_BOOKE_GIVOR13 (0x1BC) 1667 #define SPR_BOOKE_GIVOR14 (0x1BD) 1668 #define SPR_TIR (0x1BE) 1669 #define SPR_PTCR (0x1D0) 1670 #define SPR_BOOKE_SPEFSCR (0x200) 1671 #define SPR_Exxx_BBEAR (0x201) 1672 #define SPR_Exxx_BBTAR (0x202) 1673 #define SPR_Exxx_L1CFG0 (0x203) 1674 #define SPR_Exxx_L1CFG1 (0x204) 1675 #define SPR_Exxx_NPIDR (0x205) 1676 #define SPR_ATBL (0x20E) 1677 #define SPR_ATBU (0x20F) 1678 #define SPR_IBAT0U (0x210) 1679 #define SPR_BOOKE_IVOR32 (0x210) 1680 #define SPR_RCPU_MI_GRA (0x210) 1681 #define SPR_IBAT0L (0x211) 1682 #define SPR_BOOKE_IVOR33 (0x211) 1683 #define SPR_IBAT1U (0x212) 1684 #define SPR_BOOKE_IVOR34 (0x212) 1685 #define SPR_IBAT1L (0x213) 1686 #define SPR_BOOKE_IVOR35 (0x213) 1687 #define SPR_IBAT2U (0x214) 1688 #define SPR_BOOKE_IVOR36 (0x214) 1689 #define SPR_IBAT2L (0x215) 1690 #define SPR_BOOKE_IVOR37 (0x215) 1691 #define SPR_IBAT3U (0x216) 1692 #define SPR_IBAT3L (0x217) 1693 #define SPR_DBAT0U (0x218) 1694 #define SPR_RCPU_L2U_GRA (0x218) 1695 #define SPR_DBAT0L (0x219) 1696 #define SPR_DBAT1U (0x21A) 1697 #define SPR_DBAT1L (0x21B) 1698 #define SPR_DBAT2U (0x21C) 1699 #define SPR_DBAT2L (0x21D) 1700 #define SPR_DBAT3U (0x21E) 1701 #define SPR_DBAT3L (0x21F) 1702 #define SPR_IBAT4U (0x230) 1703 #define SPR_RPCU_BBCMCR (0x230) 1704 #define SPR_MPC_IC_CST (0x230) 1705 #define SPR_Exxx_CTXCR (0x230) 1706 #define SPR_IBAT4L (0x231) 1707 #define SPR_MPC_IC_ADR (0x231) 1708 #define SPR_Exxx_DBCR3 (0x231) 1709 #define SPR_IBAT5U (0x232) 1710 #define SPR_MPC_IC_DAT (0x232) 1711 #define SPR_Exxx_DBCNT (0x232) 1712 #define SPR_IBAT5L (0x233) 1713 #define SPR_IBAT6U (0x234) 1714 #define SPR_IBAT6L (0x235) 1715 #define SPR_IBAT7U (0x236) 1716 #define SPR_IBAT7L (0x237) 1717 #define SPR_DBAT4U (0x238) 1718 #define SPR_RCPU_L2U_MCR (0x238) 1719 #define SPR_MPC_DC_CST (0x238) 1720 #define SPR_Exxx_ALTCTXCR (0x238) 1721 #define SPR_DBAT4L (0x239) 1722 #define SPR_MPC_DC_ADR (0x239) 1723 #define SPR_DBAT5U (0x23A) 1724 #define SPR_BOOKE_MCSRR0 (0x23A) 1725 #define SPR_MPC_DC_DAT (0x23A) 1726 #define SPR_DBAT5L (0x23B) 1727 #define SPR_BOOKE_MCSRR1 (0x23B) 1728 #define SPR_DBAT6U (0x23C) 1729 #define SPR_BOOKE_MCSR (0x23C) 1730 #define SPR_DBAT6L (0x23D) 1731 #define SPR_Exxx_MCAR (0x23D) 1732 #define SPR_DBAT7U (0x23E) 1733 #define SPR_BOOKE_DSRR0 (0x23E) 1734 #define SPR_DBAT7L (0x23F) 1735 #define SPR_BOOKE_DSRR1 (0x23F) 1736 #define SPR_BOOKE_SPRG8 (0x25C) 1737 #define SPR_BOOKE_SPRG9 (0x25D) 1738 #define SPR_BOOKE_MAS0 (0x270) 1739 #define SPR_BOOKE_MAS1 (0x271) 1740 #define SPR_BOOKE_MAS2 (0x272) 1741 #define SPR_BOOKE_MAS3 (0x273) 1742 #define SPR_BOOKE_MAS4 (0x274) 1743 #define SPR_BOOKE_MAS5 (0x275) 1744 #define SPR_BOOKE_MAS6 (0x276) 1745 #define SPR_BOOKE_PID1 (0x279) 1746 #define SPR_BOOKE_PID2 (0x27A) 1747 #define SPR_MPC_DPDR (0x280) 1748 #define SPR_MPC_IMMR (0x288) 1749 #define SPR_BOOKE_TLB0CFG (0x2B0) 1750 #define SPR_BOOKE_TLB1CFG (0x2B1) 1751 #define SPR_BOOKE_TLB2CFG (0x2B2) 1752 #define SPR_BOOKE_TLB3CFG (0x2B3) 1753 #define SPR_BOOKE_EPR (0x2BE) 1754 #define SPR_PERF0 (0x300) 1755 #define SPR_RCPU_MI_RBA0 (0x300) 1756 #define SPR_MPC_MI_CTR (0x300) 1757 #define SPR_POWER_USIER (0x300) 1758 #define SPR_PERF1 (0x301) 1759 #define SPR_RCPU_MI_RBA1 (0x301) 1760 #define SPR_POWER_UMMCR2 (0x301) 1761 #define SPR_PERF2 (0x302) 1762 #define SPR_RCPU_MI_RBA2 (0x302) 1763 #define SPR_MPC_MI_AP (0x302) 1764 #define SPR_POWER_UMMCRA (0x302) 1765 #define SPR_PERF3 (0x303) 1766 #define SPR_RCPU_MI_RBA3 (0x303) 1767 #define SPR_MPC_MI_EPN (0x303) 1768 #define SPR_POWER_UPMC1 (0x303) 1769 #define SPR_PERF4 (0x304) 1770 #define SPR_POWER_UPMC2 (0x304) 1771 #define SPR_PERF5 (0x305) 1772 #define SPR_MPC_MI_TWC (0x305) 1773 #define SPR_POWER_UPMC3 (0x305) 1774 #define SPR_PERF6 (0x306) 1775 #define SPR_MPC_MI_RPN (0x306) 1776 #define SPR_POWER_UPMC4 (0x306) 1777 #define SPR_PERF7 (0x307) 1778 #define SPR_POWER_UPMC5 (0x307) 1779 #define SPR_PERF8 (0x308) 1780 #define SPR_RCPU_L2U_RBA0 (0x308) 1781 #define SPR_MPC_MD_CTR (0x308) 1782 #define SPR_POWER_UPMC6 (0x308) 1783 #define SPR_PERF9 (0x309) 1784 #define SPR_RCPU_L2U_RBA1 (0x309) 1785 #define SPR_MPC_MD_CASID (0x309) 1786 #define SPR_970_UPMC7 (0X309) 1787 #define SPR_PERFA (0x30A) 1788 #define SPR_RCPU_L2U_RBA2 (0x30A) 1789 #define SPR_MPC_MD_AP (0x30A) 1790 #define SPR_970_UPMC8 (0X30A) 1791 #define SPR_PERFB (0x30B) 1792 #define SPR_RCPU_L2U_RBA3 (0x30B) 1793 #define SPR_MPC_MD_EPN (0x30B) 1794 #define SPR_POWER_UMMCR0 (0X30B) 1795 #define SPR_PERFC (0x30C) 1796 #define SPR_MPC_MD_TWB (0x30C) 1797 #define SPR_POWER_USIAR (0X30C) 1798 #define SPR_PERFD (0x30D) 1799 #define SPR_MPC_MD_TWC (0x30D) 1800 #define SPR_POWER_USDAR (0X30D) 1801 #define SPR_PERFE (0x30E) 1802 #define SPR_MPC_MD_RPN (0x30E) 1803 #define SPR_POWER_UMMCR1 (0X30E) 1804 #define SPR_PERFF (0x30F) 1805 #define SPR_MPC_MD_TW (0x30F) 1806 #define SPR_UPERF0 (0x310) 1807 #define SPR_POWER_SIER (0x310) 1808 #define SPR_UPERF1 (0x311) 1809 #define SPR_POWER_MMCR2 (0x311) 1810 #define SPR_UPERF2 (0x312) 1811 #define SPR_POWER_MMCRA (0X312) 1812 #define SPR_UPERF3 (0x313) 1813 #define SPR_POWER_PMC1 (0X313) 1814 #define SPR_UPERF4 (0x314) 1815 #define SPR_POWER_PMC2 (0X314) 1816 #define SPR_UPERF5 (0x315) 1817 #define SPR_POWER_PMC3 (0X315) 1818 #define SPR_UPERF6 (0x316) 1819 #define SPR_POWER_PMC4 (0X316) 1820 #define SPR_UPERF7 (0x317) 1821 #define SPR_POWER_PMC5 (0X317) 1822 #define SPR_UPERF8 (0x318) 1823 #define SPR_POWER_PMC6 (0X318) 1824 #define SPR_UPERF9 (0x319) 1825 #define SPR_970_PMC7 (0X319) 1826 #define SPR_UPERFA (0x31A) 1827 #define SPR_970_PMC8 (0X31A) 1828 #define SPR_UPERFB (0x31B) 1829 #define SPR_POWER_MMCR0 (0X31B) 1830 #define SPR_UPERFC (0x31C) 1831 #define SPR_POWER_SIAR (0X31C) 1832 #define SPR_UPERFD (0x31D) 1833 #define SPR_POWER_SDAR (0X31D) 1834 #define SPR_UPERFE (0x31E) 1835 #define SPR_POWER_MMCR1 (0X31E) 1836 #define SPR_UPERFF (0x31F) 1837 #define SPR_RCPU_MI_RA0 (0x320) 1838 #define SPR_MPC_MI_DBCAM (0x320) 1839 #define SPR_BESCRS (0x320) 1840 #define SPR_RCPU_MI_RA1 (0x321) 1841 #define SPR_MPC_MI_DBRAM0 (0x321) 1842 #define SPR_BESCRSU (0x321) 1843 #define SPR_RCPU_MI_RA2 (0x322) 1844 #define SPR_MPC_MI_DBRAM1 (0x322) 1845 #define SPR_BESCRR (0x322) 1846 #define SPR_RCPU_MI_RA3 (0x323) 1847 #define SPR_BESCRRU (0x323) 1848 #define SPR_EBBHR (0x324) 1849 #define SPR_EBBRR (0x325) 1850 #define SPR_BESCR (0x326) 1851 #define SPR_RCPU_L2U_RA0 (0x328) 1852 #define SPR_MPC_MD_DBCAM (0x328) 1853 #define SPR_RCPU_L2U_RA1 (0x329) 1854 #define SPR_MPC_MD_DBRAM0 (0x329) 1855 #define SPR_RCPU_L2U_RA2 (0x32A) 1856 #define SPR_MPC_MD_DBRAM1 (0x32A) 1857 #define SPR_RCPU_L2U_RA3 (0x32B) 1858 #define SPR_TAR (0x32F) 1859 #define SPR_ASDR (0x330) 1860 #define SPR_IC (0x350) 1861 #define SPR_VTB (0x351) 1862 #define SPR_MMCRC (0x353) 1863 #define SPR_PSSCR (0x357) 1864 #define SPR_440_INV0 (0x370) 1865 #define SPR_440_INV1 (0x371) 1866 #define SPR_440_INV2 (0x372) 1867 #define SPR_440_INV3 (0x373) 1868 #define SPR_440_ITV0 (0x374) 1869 #define SPR_440_ITV1 (0x375) 1870 #define SPR_440_ITV2 (0x376) 1871 #define SPR_440_ITV3 (0x377) 1872 #define SPR_440_CCR1 (0x378) 1873 #define SPR_TACR (0x378) 1874 #define SPR_TCSCR (0x379) 1875 #define SPR_CSIGR (0x37a) 1876 #define SPR_DCRIPR (0x37B) 1877 #define SPR_POWER_SPMC1 (0x37C) 1878 #define SPR_POWER_SPMC2 (0x37D) 1879 #define SPR_POWER_MMCRS (0x37E) 1880 #define SPR_WORT (0x37F) 1881 #define SPR_PPR (0x380) 1882 #define SPR_750_GQR0 (0x390) 1883 #define SPR_440_DNV0 (0x390) 1884 #define SPR_750_GQR1 (0x391) 1885 #define SPR_440_DNV1 (0x391) 1886 #define SPR_750_GQR2 (0x392) 1887 #define SPR_440_DNV2 (0x392) 1888 #define SPR_750_GQR3 (0x393) 1889 #define SPR_440_DNV3 (0x393) 1890 #define SPR_750_GQR4 (0x394) 1891 #define SPR_440_DTV0 (0x394) 1892 #define SPR_750_GQR5 (0x395) 1893 #define SPR_440_DTV1 (0x395) 1894 #define SPR_750_GQR6 (0x396) 1895 #define SPR_440_DTV2 (0x396) 1896 #define SPR_750_GQR7 (0x397) 1897 #define SPR_440_DTV3 (0x397) 1898 #define SPR_750_THRM4 (0x398) 1899 #define SPR_750CL_HID2 (0x398) 1900 #define SPR_440_DVLIM (0x398) 1901 #define SPR_750_WPAR (0x399) 1902 #define SPR_440_IVLIM (0x399) 1903 #define SPR_TSCR (0x399) 1904 #define SPR_750_DMAU (0x39A) 1905 #define SPR_750_DMAL (0x39B) 1906 #define SPR_440_RSTCFG (0x39B) 1907 #define SPR_BOOKE_DCDBTRL (0x39C) 1908 #define SPR_BOOKE_DCDBTRH (0x39D) 1909 #define SPR_BOOKE_ICDBTRL (0x39E) 1910 #define SPR_BOOKE_ICDBTRH (0x39F) 1911 #define SPR_74XX_UMMCR2 (0x3A0) 1912 #define SPR_7XX_UPMC5 (0x3A1) 1913 #define SPR_7XX_UPMC6 (0x3A2) 1914 #define SPR_UBAMR (0x3A7) 1915 #define SPR_7XX_UMMCR0 (0x3A8) 1916 #define SPR_7XX_UPMC1 (0x3A9) 1917 #define SPR_7XX_UPMC2 (0x3AA) 1918 #define SPR_7XX_USIAR (0x3AB) 1919 #define SPR_7XX_UMMCR1 (0x3AC) 1920 #define SPR_7XX_UPMC3 (0x3AD) 1921 #define SPR_7XX_UPMC4 (0x3AE) 1922 #define SPR_USDA (0x3AF) 1923 #define SPR_40x_ZPR (0x3B0) 1924 #define SPR_BOOKE_MAS7 (0x3B0) 1925 #define SPR_74XX_MMCR2 (0x3B0) 1926 #define SPR_7XX_PMC5 (0x3B1) 1927 #define SPR_40x_PID (0x3B1) 1928 #define SPR_7XX_PMC6 (0x3B2) 1929 #define SPR_440_MMUCR (0x3B2) 1930 #define SPR_4xx_CCR0 (0x3B3) 1931 #define SPR_BOOKE_EPLC (0x3B3) 1932 #define SPR_405_IAC3 (0x3B4) 1933 #define SPR_BOOKE_EPSC (0x3B4) 1934 #define SPR_405_IAC4 (0x3B5) 1935 #define SPR_405_DVC1 (0x3B6) 1936 #define SPR_405_DVC2 (0x3B7) 1937 #define SPR_BAMR (0x3B7) 1938 #define SPR_7XX_MMCR0 (0x3B8) 1939 #define SPR_7XX_PMC1 (0x3B9) 1940 #define SPR_40x_SGR (0x3B9) 1941 #define SPR_7XX_PMC2 (0x3BA) 1942 #define SPR_40x_DCWR (0x3BA) 1943 #define SPR_7XX_SIAR (0x3BB) 1944 #define SPR_405_SLER (0x3BB) 1945 #define SPR_7XX_MMCR1 (0x3BC) 1946 #define SPR_405_SU0R (0x3BC) 1947 #define SPR_401_SKR (0x3BC) 1948 #define SPR_7XX_PMC3 (0x3BD) 1949 #define SPR_405_DBCR1 (0x3BD) 1950 #define SPR_7XX_PMC4 (0x3BE) 1951 #define SPR_SDA (0x3BF) 1952 #define SPR_403_VTBL (0x3CC) 1953 #define SPR_403_VTBU (0x3CD) 1954 #define SPR_DMISS (0x3D0) 1955 #define SPR_DCMP (0x3D1) 1956 #define SPR_HASH1 (0x3D2) 1957 #define SPR_HASH2 (0x3D3) 1958 #define SPR_BOOKE_ICDBDR (0x3D3) 1959 #define SPR_TLBMISS (0x3D4) 1960 #define SPR_IMISS (0x3D4) 1961 #define SPR_40x_ESR (0x3D4) 1962 #define SPR_PTEHI (0x3D5) 1963 #define SPR_ICMP (0x3D5) 1964 #define SPR_40x_DEAR (0x3D5) 1965 #define SPR_PTELO (0x3D6) 1966 #define SPR_RPA (0x3D6) 1967 #define SPR_40x_EVPR (0x3D6) 1968 #define SPR_L3PM (0x3D7) 1969 #define SPR_403_CDBCR (0x3D7) 1970 #define SPR_L3ITCR0 (0x3D8) 1971 #define SPR_TCR (0x3D8) 1972 #define SPR_40x_TSR (0x3D8) 1973 #define SPR_IBR (0x3DA) 1974 #define SPR_40x_TCR (0x3DA) 1975 #define SPR_ESASRR (0x3DB) 1976 #define SPR_40x_PIT (0x3DB) 1977 #define SPR_403_TBL (0x3DC) 1978 #define SPR_403_TBU (0x3DD) 1979 #define SPR_SEBR (0x3DE) 1980 #define SPR_40x_SRR2 (0x3DE) 1981 #define SPR_SER (0x3DF) 1982 #define SPR_40x_SRR3 (0x3DF) 1983 #define SPR_L3OHCR (0x3E8) 1984 #define SPR_L3ITCR1 (0x3E9) 1985 #define SPR_L3ITCR2 (0x3EA) 1986 #define SPR_L3ITCR3 (0x3EB) 1987 #define SPR_HID0 (0x3F0) 1988 #define SPR_40x_DBSR (0x3F0) 1989 #define SPR_HID1 (0x3F1) 1990 #define SPR_IABR (0x3F2) 1991 #define SPR_40x_DBCR0 (0x3F2) 1992 #define SPR_Exxx_L1CSR0 (0x3F2) 1993 #define SPR_ICTRL (0x3F3) 1994 #define SPR_HID2 (0x3F3) 1995 #define SPR_750CL_HID4 (0x3F3) 1996 #define SPR_Exxx_L1CSR1 (0x3F3) 1997 #define SPR_440_DBDR (0x3F3) 1998 #define SPR_LDSTDB (0x3F4) 1999 #define SPR_750_TDCL (0x3F4) 2000 #define SPR_40x_IAC1 (0x3F4) 2001 #define SPR_MMUCSR0 (0x3F4) 2002 #define SPR_970_HID4 (0x3F4) 2003 #define SPR_DABR (0x3F5) 2004 #define DABR_MASK (~(target_ulong)0x7) 2005 #define SPR_Exxx_BUCSR (0x3F5) 2006 #define SPR_40x_IAC2 (0x3F5) 2007 #define SPR_40x_DAC1 (0x3F6) 2008 #define SPR_MSSCR0 (0x3F6) 2009 #define SPR_970_HID5 (0x3F6) 2010 #define SPR_MSSSR0 (0x3F7) 2011 #define SPR_MSSCR1 (0x3F7) 2012 #define SPR_DABRX (0x3F7) 2013 #define SPR_40x_DAC2 (0x3F7) 2014 #define SPR_MMUCFG (0x3F7) 2015 #define SPR_LDSTCR (0x3F8) 2016 #define SPR_L2PMCR (0x3F8) 2017 #define SPR_750FX_HID2 (0x3F8) 2018 #define SPR_Exxx_L1FINV0 (0x3F8) 2019 #define SPR_L2CR (0x3F9) 2020 #define SPR_Exxx_L2CSR0 (0x3F9) 2021 #define SPR_L3CR (0x3FA) 2022 #define SPR_750_TDCH (0x3FA) 2023 #define SPR_IABR2 (0x3FA) 2024 #define SPR_40x_DCCR (0x3FA) 2025 #define SPR_ICTC (0x3FB) 2026 #define SPR_40x_ICCR (0x3FB) 2027 #define SPR_THRM1 (0x3FC) 2028 #define SPR_403_PBL1 (0x3FC) 2029 #define SPR_SP (0x3FD) 2030 #define SPR_THRM2 (0x3FD) 2031 #define SPR_403_PBU1 (0x3FD) 2032 #define SPR_604_HID13 (0x3FD) 2033 #define SPR_LT (0x3FE) 2034 #define SPR_THRM3 (0x3FE) 2035 #define SPR_RCPU_FPECR (0x3FE) 2036 #define SPR_403_PBL2 (0x3FE) 2037 #define SPR_PIR (0x3FF) 2038 #define SPR_403_PBU2 (0x3FF) 2039 #define SPR_604_HID15 (0x3FF) 2040 #define SPR_E500_SVR (0x3FF) 2041 2042 /* Disable MAS Interrupt Updates for Hypervisor */ 2043 #define EPCR_DMIUH (1 << 22) 2044 /* Disable Guest TLB Management Instructions */ 2045 #define EPCR_DGTMI (1 << 23) 2046 /* Guest Interrupt Computation Mode */ 2047 #define EPCR_GICM (1 << 24) 2048 /* Interrupt Computation Mode */ 2049 #define EPCR_ICM (1 << 25) 2050 /* Disable Embedded Hypervisor Debug */ 2051 #define EPCR_DUVD (1 << 26) 2052 /* Instruction Storage Interrupt Directed to Guest State */ 2053 #define EPCR_ISIGS (1 << 27) 2054 /* Data Storage Interrupt Directed to Guest State */ 2055 #define EPCR_DSIGS (1 << 28) 2056 /* Instruction TLB Error Interrupt Directed to Guest State */ 2057 #define EPCR_ITLBGS (1 << 29) 2058 /* Data TLB Error Interrupt Directed to Guest State */ 2059 #define EPCR_DTLBGS (1 << 30) 2060 /* External Input Interrupt Directed to Guest State */ 2061 #define EPCR_EXTGS (1 << 31) 2062 2063 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 2064 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ 2065 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ 2066 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 2067 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 2068 2069 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 2070 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ 2071 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ 2072 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 2073 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 2074 2075 /* E500 L2CSR0 */ 2076 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */ 2077 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */ 2078 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */ 2079 2080 /* HID0 bits */ 2081 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ 2082 #define HID0_DOZE (1 << 23) /* pre-2.06 */ 2083 #define HID0_NAP (1 << 22) /* pre-2.06 */ 2084 #define HID0_HILE PPC_BIT(19) /* POWER8 */ 2085 #define HID0_POWER9_HILE PPC_BIT(4) 2086 2087 /*****************************************************************************/ 2088 /* PowerPC Instructions types definitions */ 2089 enum { 2090 PPC_NONE = 0x0000000000000000ULL, 2091 /* PowerPC base instructions set */ 2092 PPC_INSNS_BASE = 0x0000000000000001ULL, 2093 /* integer operations instructions */ 2094 #define PPC_INTEGER PPC_INSNS_BASE 2095 /* flow control instructions */ 2096 #define PPC_FLOW PPC_INSNS_BASE 2097 /* virtual memory instructions */ 2098 #define PPC_MEM PPC_INSNS_BASE 2099 /* ld/st with reservation instructions */ 2100 #define PPC_RES PPC_INSNS_BASE 2101 /* spr/msr access instructions */ 2102 #define PPC_MISC PPC_INSNS_BASE 2103 /* 64 bits PowerPC instruction set */ 2104 PPC_64B = 0x0000000000000020ULL, 2105 /* New 64 bits extensions (PowerPC 2.0x) */ 2106 PPC_64BX = 0x0000000000000040ULL, 2107 /* 64 bits hypervisor extensions */ 2108 PPC_64H = 0x0000000000000080ULL, 2109 /* New wait instruction (PowerPC 2.0x) */ 2110 PPC_WAIT = 0x0000000000000100ULL, 2111 /* Time base mftb instruction */ 2112 PPC_MFTB = 0x0000000000000200ULL, 2113 2114 /* Fixed-point unit extensions */ 2115 /* isel instruction */ 2116 PPC_ISEL = 0x0000000000000800ULL, 2117 /* popcntb instruction */ 2118 PPC_POPCNTB = 0x0000000000001000ULL, 2119 /* string load / store */ 2120 PPC_STRING = 0x0000000000002000ULL, 2121 /* real mode cache inhibited load / store */ 2122 PPC_CILDST = 0x0000000000004000ULL, 2123 2124 /* Floating-point unit extensions */ 2125 /* Optional floating point instructions */ 2126 PPC_FLOAT = 0x0000000000010000ULL, 2127 /* New floating-point extensions (PowerPC 2.0x) */ 2128 PPC_FLOAT_EXT = 0x0000000000020000ULL, 2129 PPC_FLOAT_FSQRT = 0x0000000000040000ULL, 2130 PPC_FLOAT_FRES = 0x0000000000080000ULL, 2131 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, 2132 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, 2133 PPC_FLOAT_FSEL = 0x0000000000400000ULL, 2134 PPC_FLOAT_STFIWX = 0x0000000000800000ULL, 2135 2136 /* Vector/SIMD extensions */ 2137 /* Altivec support */ 2138 PPC_ALTIVEC = 0x0000000001000000ULL, 2139 /* PowerPC 2.03 SPE extension */ 2140 PPC_SPE = 0x0000000002000000ULL, 2141 /* PowerPC 2.03 SPE single-precision floating-point extension */ 2142 PPC_SPE_SINGLE = 0x0000000004000000ULL, 2143 /* PowerPC 2.03 SPE double-precision floating-point extension */ 2144 PPC_SPE_DOUBLE = 0x0000000008000000ULL, 2145 2146 /* Optional memory control instructions */ 2147 PPC_MEM_TLBIA = 0x0000000010000000ULL, 2148 PPC_MEM_TLBIE = 0x0000000020000000ULL, 2149 PPC_MEM_TLBSYNC = 0x0000000040000000ULL, 2150 /* sync instruction */ 2151 PPC_MEM_SYNC = 0x0000000080000000ULL, 2152 /* eieio instruction */ 2153 PPC_MEM_EIEIO = 0x0000000100000000ULL, 2154 2155 /* Cache control instructions */ 2156 PPC_CACHE = 0x0000000200000000ULL, 2157 /* icbi instruction */ 2158 PPC_CACHE_ICBI = 0x0000000400000000ULL, 2159 /* dcbz instruction */ 2160 PPC_CACHE_DCBZ = 0x0000000800000000ULL, 2161 /* dcba instruction */ 2162 PPC_CACHE_DCBA = 0x0000002000000000ULL, 2163 /* Freescale cache locking instructions */ 2164 PPC_CACHE_LOCK = 0x0000004000000000ULL, 2165 2166 /* MMU related extensions */ 2167 /* external control instructions */ 2168 PPC_EXTERN = 0x0000010000000000ULL, 2169 /* segment register access instructions */ 2170 PPC_SEGMENT = 0x0000020000000000ULL, 2171 /* PowerPC 6xx TLB management instructions */ 2172 PPC_6xx_TLB = 0x0000040000000000ULL, 2173 /* PowerPC 40x TLB management instructions */ 2174 PPC_40x_TLB = 0x0000100000000000ULL, 2175 /* segment register access instructions for PowerPC 64 "bridge" */ 2176 PPC_SEGMENT_64B = 0x0000200000000000ULL, 2177 /* SLB management */ 2178 PPC_SLBI = 0x0000400000000000ULL, 2179 2180 /* Embedded PowerPC dedicated instructions */ 2181 PPC_WRTEE = 0x0001000000000000ULL, 2182 /* PowerPC 40x exception model */ 2183 PPC_40x_EXCP = 0x0002000000000000ULL, 2184 /* PowerPC 405 Mac instructions */ 2185 PPC_405_MAC = 0x0004000000000000ULL, 2186 /* PowerPC 440 specific instructions */ 2187 PPC_440_SPEC = 0x0008000000000000ULL, 2188 /* BookE (embedded) PowerPC specification */ 2189 PPC_BOOKE = 0x0010000000000000ULL, 2190 /* mfapidi instruction */ 2191 PPC_MFAPIDI = 0x0020000000000000ULL, 2192 /* tlbiva instruction */ 2193 PPC_TLBIVA = 0x0040000000000000ULL, 2194 /* tlbivax instruction */ 2195 PPC_TLBIVAX = 0x0080000000000000ULL, 2196 /* PowerPC 4xx dedicated instructions */ 2197 PPC_4xx_COMMON = 0x0100000000000000ULL, 2198 /* PowerPC 40x ibct instructions */ 2199 PPC_40x_ICBT = 0x0200000000000000ULL, 2200 /* rfmci is not implemented in all BookE PowerPC */ 2201 PPC_RFMCI = 0x0400000000000000ULL, 2202 /* rfdi instruction */ 2203 PPC_RFDI = 0x0800000000000000ULL, 2204 /* DCR accesses */ 2205 PPC_DCR = 0x1000000000000000ULL, 2206 /* DCR extended accesse */ 2207 PPC_DCRX = 0x2000000000000000ULL, 2208 /* user-mode DCR access, implemented in PowerPC 460 */ 2209 PPC_DCRUX = 0x4000000000000000ULL, 2210 /* popcntw and popcntd instructions */ 2211 PPC_POPCNTWD = 0x8000000000000000ULL, 2212 2213 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \ 2214 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ 2215 | PPC_ISEL | PPC_POPCNTB \ 2216 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ 2217 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ 2218 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ 2219 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \ 2220 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \ 2221 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \ 2222 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ 2223 | PPC_MEM_SYNC | PPC_MEM_EIEIO \ 2224 | PPC_CACHE | PPC_CACHE_ICBI \ 2225 | PPC_CACHE_DCBZ \ 2226 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ 2227 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ 2228 | PPC_40x_TLB | PPC_SEGMENT_64B \ 2229 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ 2230 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ 2231 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ 2232 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ 2233 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ 2234 | PPC_POPCNTWD | PPC_CILDST) 2235 2236 /* extended type values */ 2237 2238 /* BookE 2.06 PowerPC specification */ 2239 PPC2_BOOKE206 = 0x0000000000000001ULL, 2240 /* VSX (extensions to Altivec / VMX) */ 2241 PPC2_VSX = 0x0000000000000002ULL, 2242 /* Decimal Floating Point (DFP) */ 2243 PPC2_DFP = 0x0000000000000004ULL, 2244 /* Embedded.Processor Control */ 2245 PPC2_PRCNTL = 0x0000000000000008ULL, 2246 /* Byte-reversed, indexed, double-word load and store */ 2247 PPC2_DBRX = 0x0000000000000010ULL, 2248 /* Book I 2.05 PowerPC specification */ 2249 PPC2_ISA205 = 0x0000000000000020ULL, 2250 /* VSX additions in ISA 2.07 */ 2251 PPC2_VSX207 = 0x0000000000000040ULL, 2252 /* ISA 2.06B bpermd */ 2253 PPC2_PERM_ISA206 = 0x0000000000000080ULL, 2254 /* ISA 2.06B divide extended variants */ 2255 PPC2_DIVE_ISA206 = 0x0000000000000100ULL, 2256 /* ISA 2.06B larx/stcx. instructions */ 2257 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, 2258 /* ISA 2.06B floating point integer conversion */ 2259 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, 2260 /* ISA 2.06B floating point test instructions */ 2261 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, 2262 /* ISA 2.07 bctar instruction */ 2263 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, 2264 /* ISA 2.07 load/store quadword */ 2265 PPC2_LSQ_ISA207 = 0x0000000000002000ULL, 2266 /* ISA 2.07 Altivec */ 2267 PPC2_ALTIVEC_207 = 0x0000000000004000ULL, 2268 /* PowerISA 2.07 Book3s specification */ 2269 PPC2_ISA207S = 0x0000000000008000ULL, 2270 /* Double precision floating point conversion for signed integer 64 */ 2271 PPC2_FP_CVT_S64 = 0x0000000000010000ULL, 2272 /* Transactional Memory (ISA 2.07, Book II) */ 2273 PPC2_TM = 0x0000000000020000ULL, 2274 /* Server PM instructgions (ISA 2.06, Book III) */ 2275 PPC2_PM_ISA206 = 0x0000000000040000ULL, 2276 /* POWER ISA 3.0 */ 2277 PPC2_ISA300 = 0x0000000000080000ULL, 2278 /* POWER ISA 3.1 */ 2279 PPC2_ISA310 = 0x0000000000100000ULL, 2280 2281 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ 2282 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ 2283 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ 2284 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ 2285 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ 2286 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ 2287 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ 2288 PPC2_ISA300 | PPC2_ISA310) 2289 }; 2290 2291 /*****************************************************************************/ 2292 /* 2293 * Memory access type : 2294 * may be needed for precise access rights control and precise exceptions. 2295 */ 2296 enum { 2297 /* Type of instruction that generated the access */ 2298 ACCESS_CODE = 0x10, /* Code fetch access */ 2299 ACCESS_INT = 0x20, /* Integer load/store access */ 2300 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 2301 ACCESS_RES = 0x40, /* load/store with reservation */ 2302 ACCESS_EXT = 0x50, /* external access */ 2303 ACCESS_CACHE = 0x60, /* Cache manipulation */ 2304 }; 2305 2306 /* 2307 * Hardware interrupt sources: 2308 * all those exception can be raised simulteaneously 2309 */ 2310 /* Input pins definitions */ 2311 enum { 2312 /* 6xx bus input pins */ 2313 PPC6xx_INPUT_HRESET = 0, 2314 PPC6xx_INPUT_SRESET = 1, 2315 PPC6xx_INPUT_CKSTP_IN = 2, 2316 PPC6xx_INPUT_MCP = 3, 2317 PPC6xx_INPUT_SMI = 4, 2318 PPC6xx_INPUT_INT = 5, 2319 PPC6xx_INPUT_TBEN = 6, 2320 PPC6xx_INPUT_WAKEUP = 7, 2321 PPC6xx_INPUT_NB, 2322 }; 2323 2324 enum { 2325 /* Embedded PowerPC input pins */ 2326 PPCBookE_INPUT_HRESET = 0, 2327 PPCBookE_INPUT_SRESET = 1, 2328 PPCBookE_INPUT_CKSTP_IN = 2, 2329 PPCBookE_INPUT_MCP = 3, 2330 PPCBookE_INPUT_SMI = 4, 2331 PPCBookE_INPUT_INT = 5, 2332 PPCBookE_INPUT_CINT = 6, 2333 PPCBookE_INPUT_NB, 2334 }; 2335 2336 enum { 2337 /* PowerPC E500 input pins */ 2338 PPCE500_INPUT_RESET_CORE = 0, 2339 PPCE500_INPUT_MCK = 1, 2340 PPCE500_INPUT_CINT = 3, 2341 PPCE500_INPUT_INT = 4, 2342 PPCE500_INPUT_DEBUG = 6, 2343 PPCE500_INPUT_NB, 2344 }; 2345 2346 enum { 2347 /* PowerPC 40x input pins */ 2348 PPC40x_INPUT_RESET_CORE = 0, 2349 PPC40x_INPUT_RESET_CHIP = 1, 2350 PPC40x_INPUT_RESET_SYS = 2, 2351 PPC40x_INPUT_CINT = 3, 2352 PPC40x_INPUT_INT = 4, 2353 PPC40x_INPUT_HALT = 5, 2354 PPC40x_INPUT_DEBUG = 6, 2355 PPC40x_INPUT_NB, 2356 }; 2357 2358 enum { 2359 /* RCPU input pins */ 2360 PPCRCPU_INPUT_PORESET = 0, 2361 PPCRCPU_INPUT_HRESET = 1, 2362 PPCRCPU_INPUT_SRESET = 2, 2363 PPCRCPU_INPUT_IRQ0 = 3, 2364 PPCRCPU_INPUT_IRQ1 = 4, 2365 PPCRCPU_INPUT_IRQ2 = 5, 2366 PPCRCPU_INPUT_IRQ3 = 6, 2367 PPCRCPU_INPUT_IRQ4 = 7, 2368 PPCRCPU_INPUT_IRQ5 = 8, 2369 PPCRCPU_INPUT_IRQ6 = 9, 2370 PPCRCPU_INPUT_IRQ7 = 10, 2371 PPCRCPU_INPUT_NB, 2372 }; 2373 2374 #if defined(TARGET_PPC64) 2375 enum { 2376 /* PowerPC 970 input pins */ 2377 PPC970_INPUT_HRESET = 0, 2378 PPC970_INPUT_SRESET = 1, 2379 PPC970_INPUT_CKSTP = 2, 2380 PPC970_INPUT_TBEN = 3, 2381 PPC970_INPUT_MCP = 4, 2382 PPC970_INPUT_INT = 5, 2383 PPC970_INPUT_THINT = 6, 2384 PPC970_INPUT_NB, 2385 }; 2386 2387 enum { 2388 /* POWER7 input pins */ 2389 POWER7_INPUT_INT = 0, 2390 /* 2391 * POWER7 probably has other inputs, but we don't care about them 2392 * for any existing machine. We can wire these up when we need 2393 * them 2394 */ 2395 POWER7_INPUT_NB, 2396 }; 2397 2398 enum { 2399 /* POWER9 input pins */ 2400 POWER9_INPUT_INT = 0, 2401 POWER9_INPUT_HINT = 1, 2402 POWER9_INPUT_NB, 2403 }; 2404 #endif 2405 2406 /* Hardware exceptions definitions */ 2407 enum { 2408 /* External hardware exception sources */ 2409 PPC_INTERRUPT_RESET = 0, /* Reset exception */ 2410 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ 2411 PPC_INTERRUPT_MCK, /* Machine check exception */ 2412 PPC_INTERRUPT_EXT, /* External interrupt */ 2413 PPC_INTERRUPT_SMI, /* System management interrupt */ 2414 PPC_INTERRUPT_CEXT, /* Critical external interrupt */ 2415 PPC_INTERRUPT_DEBUG, /* External debug exception */ 2416 PPC_INTERRUPT_THERM, /* Thermal exception */ 2417 /* Internal hardware exception sources */ 2418 PPC_INTERRUPT_DECR, /* Decrementer exception */ 2419 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ 2420 PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt */ 2421 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ 2422 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ 2423 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ 2424 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ 2425 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ 2426 PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ 2427 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ 2428 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */ 2429 }; 2430 2431 /* Processor Compatibility mask (PCR) */ 2432 enum { 2433 PCR_COMPAT_2_05 = PPC_BIT(62), 2434 PCR_COMPAT_2_06 = PPC_BIT(61), 2435 PCR_COMPAT_2_07 = PPC_BIT(60), 2436 PCR_COMPAT_3_00 = PPC_BIT(59), 2437 PCR_COMPAT_3_10 = PPC_BIT(58), 2438 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */ 2439 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */ 2440 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */ 2441 }; 2442 2443 /* HMER/HMEER */ 2444 enum { 2445 HMER_MALFUNCTION_ALERT = PPC_BIT(0), 2446 HMER_PROC_RECV_DONE = PPC_BIT(2), 2447 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3), 2448 HMER_TFAC_ERROR = PPC_BIT(4), 2449 HMER_TFMR_PARITY_ERROR = PPC_BIT(5), 2450 HMER_XSCOM_FAIL = PPC_BIT(8), 2451 HMER_XSCOM_DONE = PPC_BIT(9), 2452 HMER_PROC_RECV_AGAIN = PPC_BIT(11), 2453 HMER_WARN_RISE = PPC_BIT(14), 2454 HMER_WARN_FALL = PPC_BIT(15), 2455 HMER_SCOM_FIR_HMI = PPC_BIT(16), 2456 HMER_TRIG_FIR_HMI = PPC_BIT(17), 2457 HMER_HYP_RESOURCE_ERR = PPC_BIT(20), 2458 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23), 2459 }; 2460 2461 /*****************************************************************************/ 2462 2463 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) 2464 target_ulong cpu_read_xer(const CPUPPCState *env); 2465 void cpu_write_xer(CPUPPCState *env, target_ulong xer); 2466 2467 /* 2468 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer, 2469 * have PPC_SEGMENT_64B. 2470 */ 2471 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) 2472 2473 #ifdef CONFIG_DEBUG_TCG 2474 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 2475 target_ulong *cs_base, uint32_t *flags); 2476 #else 2477 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 2478 target_ulong *cs_base, uint32_t *flags) 2479 { 2480 *pc = env->nip; 2481 *cs_base = 0; 2482 *flags = env->hflags; 2483 } 2484 #endif 2485 2486 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); 2487 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, 2488 uintptr_t raddr); 2489 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception, 2490 uint32_t error_code); 2491 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 2492 uint32_t error_code, uintptr_t raddr); 2493 2494 #if !defined(CONFIG_USER_ONLY) 2495 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2496 { 2497 uintptr_t tlbml = (uintptr_t)tlbm; 2498 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; 2499 2500 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); 2501 } 2502 2503 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn) 2504 { 2505 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2506 int r = tlbncfg & TLBnCFG_N_ENTRY; 2507 return r; 2508 } 2509 2510 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn) 2511 { 2512 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2513 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT; 2514 return r; 2515 } 2516 2517 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2518 { 2519 int id = booke206_tlbm_id(env, tlbm); 2520 int end = 0; 2521 int i; 2522 2523 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 2524 end += booke206_tlb_size(env, i); 2525 if (id < end) { 2526 return i; 2527 } 2528 } 2529 2530 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id); 2531 return 0; 2532 } 2533 2534 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb) 2535 { 2536 int tlbn = booke206_tlbm_to_tlbn(env, tlb); 2537 int tlbid = booke206_tlbm_id(env, tlb); 2538 return tlbid & (booke206_tlb_ways(env, tlbn) - 1); 2539 } 2540 2541 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn, 2542 target_ulong ea, int way) 2543 { 2544 int r; 2545 uint32_t ways = booke206_tlb_ways(env, tlbn); 2546 int ways_bits = ctz32(ways); 2547 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn)); 2548 int i; 2549 2550 way &= ways - 1; 2551 ea >>= MAS2_EPN_SHIFT; 2552 ea &= (1 << (tlb_bits - ways_bits)) - 1; 2553 r = (ea << ways_bits) | way; 2554 2555 if (r >= booke206_tlb_size(env, tlbn)) { 2556 return NULL; 2557 } 2558 2559 /* bump up to tlbn index */ 2560 for (i = 0; i < tlbn; i++) { 2561 r += booke206_tlb_size(env, i); 2562 } 2563 2564 return &env->tlb.tlbm[r]; 2565 } 2566 2567 /* returns bitmap of supported page sizes for a given TLB */ 2568 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) 2569 { 2570 uint32_t ret = 0; 2571 2572 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { 2573 /* MAV2 */ 2574 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; 2575 } else { 2576 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2577 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; 2578 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; 2579 int i; 2580 for (i = min; i <= max; i++) { 2581 ret |= (1 << (i << 1)); 2582 } 2583 } 2584 2585 return ret; 2586 } 2587 2588 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn, 2589 ppcmas_tlb_t *tlb) 2590 { 2591 uint8_t i; 2592 int32_t tsize = -1; 2593 2594 for (i = 0; i < 32; i++) { 2595 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { 2596 if (tsize == -1) { 2597 tsize = i; 2598 } else { 2599 return; 2600 } 2601 } 2602 } 2603 2604 /* TLBnPS unimplemented? Odd.. */ 2605 assert(tsize != -1); 2606 tlb->mas1 &= ~MAS1_TSIZE_MASK; 2607 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; 2608 } 2609 2610 #endif 2611 2612 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) 2613 { 2614 if (env->mmu_model == POWERPC_MMU_BOOKE206) { 2615 return msr & (1ULL << MSR_CM); 2616 } 2617 2618 return msr & (1ULL << MSR_SF); 2619 } 2620 2621 /** 2622 * Check whether register rx is in the range between start and 2623 * start + nregs (as needed by the LSWX and LSWI instructions) 2624 */ 2625 static inline bool lsw_reg_in_range(int start, int nregs, int rx) 2626 { 2627 return (start + nregs <= 32 && rx >= start && rx < start + nregs) || 2628 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); 2629 } 2630 2631 /* Accessors for FP, VMX and VSX registers */ 2632 #if defined(HOST_WORDS_BIGENDIAN) 2633 #define VsrB(i) u8[i] 2634 #define VsrSB(i) s8[i] 2635 #define VsrH(i) u16[i] 2636 #define VsrSH(i) s16[i] 2637 #define VsrW(i) u32[i] 2638 #define VsrSW(i) s32[i] 2639 #define VsrD(i) u64[i] 2640 #define VsrSD(i) s64[i] 2641 #else 2642 #define VsrB(i) u8[15 - (i)] 2643 #define VsrSB(i) s8[15 - (i)] 2644 #define VsrH(i) u16[7 - (i)] 2645 #define VsrSH(i) s16[7 - (i)] 2646 #define VsrW(i) u32[3 - (i)] 2647 #define VsrSW(i) s32[3 - (i)] 2648 #define VsrD(i) u64[1 - (i)] 2649 #define VsrSD(i) s64[1 - (i)] 2650 #endif 2651 2652 static inline int vsr64_offset(int i, bool high) 2653 { 2654 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1)); 2655 } 2656 2657 static inline int vsr_full_offset(int i) 2658 { 2659 return offsetof(CPUPPCState, vsr[i].u64[0]); 2660 } 2661 2662 static inline int fpr_offset(int i) 2663 { 2664 return vsr64_offset(i, true); 2665 } 2666 2667 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) 2668 { 2669 return (uint64_t *)((uintptr_t)env + fpr_offset(i)); 2670 } 2671 2672 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) 2673 { 2674 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false)); 2675 } 2676 2677 static inline long avr64_offset(int i, bool high) 2678 { 2679 return vsr64_offset(i + 32, high); 2680 } 2681 2682 static inline int avr_full_offset(int i) 2683 { 2684 return vsr_full_offset(i + 32); 2685 } 2686 2687 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) 2688 { 2689 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i)); 2690 } 2691 2692 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr) 2693 { 2694 /* We can test whether the SPR is defined by checking for a valid name */ 2695 return cpu->env.spr_cb[spr].name != NULL; 2696 } 2697 2698 #if !defined(CONFIG_USER_ONLY) 2699 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) 2700 { 2701 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 2702 CPUPPCState *env = &cpu->env; 2703 bool ile; 2704 2705 if (hv && env->has_hv_mode) { 2706 if (is_isa300(pcc)) { 2707 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE); 2708 } else { 2709 ile = !!(env->spr[SPR_HID0] & HID0_HILE); 2710 } 2711 2712 } else if (pcc->lpcr_mask & LPCR_ILE) { 2713 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); 2714 } else { 2715 ile = !!(msr_ile); 2716 } 2717 2718 return ile; 2719 } 2720 #endif 2721 2722 void dump_mmu(CPUPPCState *env); 2723 2724 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); 2725 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); 2726 uint32_t ppc_get_vscr(CPUPPCState *env); 2727 #endif /* PPC_CPU_H */ 2728