xref: /openbmc/qemu/target/ppc/cpu.h (revision 3f53bc61) 
1 /*
2  *  PowerPC emulation cpu definitions for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22 
23 #include "qemu-common.h"
24 #include "qemu/int128.h"
25 
26 //#define PPC_EMULATE_32BITS_HYPV
27 
28 #if defined (TARGET_PPC64)
29 /* PowerPC 64 definitions */
30 #define TARGET_LONG_BITS 64
31 #define TARGET_PAGE_BITS 12
32 
33 /* Note that the official physical address space bits is 62-M where M
34    is implementation dependent.  I've not looked up M for the set of
35    cpus we emulate at the system level.  */
36 #define TARGET_PHYS_ADDR_SPACE_BITS 62
37 
38 /* Note that the PPC environment architecture talks about 80 bit virtual
39    addresses, with segmentation.  Obviously that's not all visible to a
40    single process, which is all we're concerned with here.  */
41 #ifdef TARGET_ABI32
42 # define TARGET_VIRT_ADDR_SPACE_BITS 32
43 #else
44 # define TARGET_VIRT_ADDR_SPACE_BITS 64
45 #endif
46 
47 #define TARGET_PAGE_BITS_64K 16
48 #define TARGET_PAGE_BITS_16M 24
49 
50 #else /* defined (TARGET_PPC64) */
51 /* PowerPC 32 definitions */
52 #define TARGET_LONG_BITS 32
53 
54 #if defined(TARGET_PPCEMB)
55 /* Specific definitions for PowerPC embedded */
56 /* BookE have 36 bits physical address space */
57 #if defined(CONFIG_USER_ONLY)
58 /* It looks like a lot of Linux programs assume page size
59  * is 4kB long. This is evil, but we have to deal with it...
60  */
61 #define TARGET_PAGE_BITS 12
62 #else /* defined(CONFIG_USER_ONLY) */
63 /* Pages can be 1 kB small */
64 #define TARGET_PAGE_BITS 10
65 #endif /* defined(CONFIG_USER_ONLY) */
66 #else /* defined(TARGET_PPCEMB) */
67 /* "standard" PowerPC 32 definitions */
68 #define TARGET_PAGE_BITS 12
69 #endif /* defined(TARGET_PPCEMB) */
70 
71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
73 
74 #endif /* defined (TARGET_PPC64) */
75 
76 #define CPUArchState struct CPUPPCState
77 
78 #include "exec/cpu-defs.h"
79 #include "cpu-qom.h"
80 #include "fpu/softfloat.h"
81 
82 #if defined (TARGET_PPC64)
83 #define PPC_ELF_MACHINE     EM_PPC64
84 #else
85 #define PPC_ELF_MACHINE     EM_PPC
86 #endif
87 
88 /*****************************************************************************/
89 /* Exception vectors definitions                                             */
90 enum {
91     POWERPC_EXCP_NONE    = -1,
92     /* The 64 first entries are used by the PowerPC embedded specification   */
93     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
94     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
95     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
96     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
97     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
98     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
99     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
100     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
101     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
102     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
103     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
104     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
105     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
106     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
107     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
108     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
109     /* Vectors 16 to 31 are reserved                                         */
110     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
111     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
112     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
113     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
114     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
115     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
116     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
117     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
118     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
119     /* Vectors 42 to 63 are reserved                                         */
120     /* Exceptions defined in the PowerPC server specification                */
121     /* Server doorbell variants */
122 #define POWERPC_EXCP_SDOOR      POWERPC_EXCP_GDOORI
123 #define POWERPC_EXCP_SDOOR_HV   POWERPC_EXCP_DOORI
124     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
125     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
126     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
127     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
128     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
129     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
130     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
131     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
132     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
133     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
134     /* 40x specific exceptions                                               */
135     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
136     /* 601 specific exceptions                                               */
137     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
138     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
139     /* 602 specific exceptions                                               */
140     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
141     /* 602/603 specific exceptions                                           */
142     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
143     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
144     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
145     /* Exceptions available on most PowerPC                                  */
146     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
147     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
148     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
149     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
150     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
151     /* 7xx/74xx specific exceptions                                          */
152     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
153     /* 74xx specific exceptions                                              */
154     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
155     /* 970FX specific exceptions                                             */
156     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
157     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
158     /* Freescale embedded cores specific exceptions                          */
159     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
160     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
161     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
162     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
163     /* VSX Unavailable (Power ISA 2.06 and later)                            */
164     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
165     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
166     /* Additional ISA 2.06 and later server exceptions                       */
167     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
168     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
169     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
170     /* EOL                                                                   */
171     POWERPC_EXCP_NB       = 99,
172     /* QEMU exceptions: used internally during code translation              */
173     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
174     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
175     /* QEMU exceptions: special cases we want to stop translation            */
176     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
177     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
178     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
179 };
180 
181 /* Exceptions error codes                                                    */
182 enum {
183     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
184     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
185     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
186     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
187     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
188     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
189     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
190     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
191     /* FP exceptions                                                         */
192     POWERPC_EXCP_FP            = 0x10,
193     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
194     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
195     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
196     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
197     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
198     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
199     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
200     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
201     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
202     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
203     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
204     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
205     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
206     /* Invalid instruction                                                   */
207     POWERPC_EXCP_INVAL         = 0x20,
208     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
209     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
210     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
211     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
212     /* Privileged instruction                                                */
213     POWERPC_EXCP_PRIV          = 0x30,
214     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
215     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
216     /* Trap                                                                  */
217     POWERPC_EXCP_TRAP          = 0x40,
218 };
219 
220 #define PPC_INPUT(env) (env->bus_model)
221 
222 /*****************************************************************************/
223 typedef struct opc_handler_t opc_handler_t;
224 
225 /*****************************************************************************/
226 /* Types used to describe some PowerPC registers etc. */
227 typedef struct DisasContext DisasContext;
228 typedef struct ppc_spr_t ppc_spr_t;
229 typedef union ppc_avr_t ppc_avr_t;
230 typedef union ppc_tlb_t ppc_tlb_t;
231 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
232 
233 /* SPR access micro-ops generations callbacks */
234 struct ppc_spr_t {
235     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
236     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
237 #if !defined(CONFIG_USER_ONLY)
238     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
239     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
240     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
241     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
242 #endif
243     const char *name;
244     target_ulong default_value;
245 #ifdef CONFIG_KVM
246     /* We (ab)use the fact that all the SPRs will have ids for the
247      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
248      * don't sync this */
249     uint64_t one_reg_id;
250 #endif
251 };
252 
253 /* Altivec registers (128 bits) */
254 union ppc_avr_t {
255     float32 f[4];
256     uint8_t u8[16];
257     uint16_t u16[8];
258     uint32_t u32[4];
259     int8_t s8[16];
260     int16_t s16[8];
261     int32_t s32[4];
262     uint64_t u64[2];
263     int64_t s64[2];
264 #ifdef CONFIG_INT128
265     __uint128_t u128;
266 #endif
267     Int128 s128;
268 };
269 
270 #if !defined(CONFIG_USER_ONLY)
271 /* Software TLB cache */
272 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
273 struct ppc6xx_tlb_t {
274     target_ulong pte0;
275     target_ulong pte1;
276     target_ulong EPN;
277 };
278 
279 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
280 struct ppcemb_tlb_t {
281     uint64_t RPN;
282     target_ulong EPN;
283     target_ulong PID;
284     target_ulong size;
285     uint32_t prot;
286     uint32_t attr; /* Storage attributes */
287 };
288 
289 typedef struct ppcmas_tlb_t {
290      uint32_t mas8;
291      uint32_t mas1;
292      uint64_t mas2;
293      uint64_t mas7_3;
294 } ppcmas_tlb_t;
295 
296 union ppc_tlb_t {
297     ppc6xx_tlb_t *tlb6;
298     ppcemb_tlb_t *tlbe;
299     ppcmas_tlb_t *tlbm;
300 };
301 
302 /* possible TLB variants */
303 #define TLB_NONE               0
304 #define TLB_6XX                1
305 #define TLB_EMB                2
306 #define TLB_MAS                3
307 #endif
308 
309 typedef struct ppc_slb_t ppc_slb_t;
310 struct ppc_slb_t {
311     uint64_t esid;
312     uint64_t vsid;
313     const struct ppc_one_seg_page_size *sps;
314 };
315 
316 #define MAX_SLB_ENTRIES         64
317 #define SEGMENT_SHIFT_256M      28
318 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
319 
320 #define SEGMENT_SHIFT_1T        40
321 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
322 
323 
324 /*****************************************************************************/
325 /* Machine state register bits definition                                    */
326 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
327 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
328 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
329 #define MSR_SHV  60 /* hypervisor state                               hflags */
330 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
331 #define MSR_TS1  33
332 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
333 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
334 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
335 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
336 #define MSR_GS   28 /* guest state for BookE                                 */
337 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
338 #define MSR_VR   25 /* altivec available                            x hflags */
339 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
340 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
341 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
342 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
343 #define MSR_KEY  19 /* key bit on 603e                                       */
344 #define MSR_POW  18 /* Power management                                      */
345 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
346 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
347 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
348 #define MSR_EE   15 /* External interrupt enable                             */
349 #define MSR_PR   14 /* Problem state                                  hflags */
350 #define MSR_FP   13 /* Floating point available                       hflags */
351 #define MSR_ME   12 /* Machine check interrupt enable                        */
352 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
353 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
354 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
355 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
356 #define MSR_BE   9  /* Branch trace enable                          x hflags */
357 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
358 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
359 #define MSR_AL   7  /* AL bit on POWER                                       */
360 #define MSR_EP   6  /* Exception prefix on 601                               */
361 #define MSR_IR   5  /* Instruction relocate                                  */
362 #define MSR_DR   4  /* Data relocate                                         */
363 #define MSR_IS   5  /* Instruction address space (BookE)                     */
364 #define MSR_DS   4  /* Data address space (BookE)                            */
365 #define MSR_PE   3  /* Protection enable on 403                              */
366 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
367 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
368 #define MSR_RI   1  /* Recoverable interrupt                        1        */
369 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
370 
371 /* LPCR bits */
372 #define LPCR_VPM0         (1ull << (63 - 0))
373 #define LPCR_VPM1         (1ull << (63 - 1))
374 #define LPCR_ISL          (1ull << (63 - 2))
375 #define LPCR_KBV          (1ull << (63 - 3))
376 #define LPCR_DPFD_SHIFT   (63 - 11)
377 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
378 #define LPCR_VRMASD_SHIFT (63 - 16)
379 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
380 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
381 #define LPCR_PECE_U_SHIFT (63 - 19)
382 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
383 #define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
384 #define LPCR_RMLS_SHIFT   (63 - 37)
385 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
386 #define LPCR_ILE          (1ull << (63 - 38))
387 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
388 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
389 #define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
390 #define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
391 #define LPCR_ONL          (1ull << (63 - 45))
392 #define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
393 #define LPCR_P7_PECE0     (1ull << (63 - 49))
394 #define LPCR_P7_PECE1     (1ull << (63 - 50))
395 #define LPCR_P7_PECE2     (1ull << (63 - 51))
396 #define LPCR_P8_PECE0     (1ull << (63 - 47))
397 #define LPCR_P8_PECE1     (1ull << (63 - 48))
398 #define LPCR_P8_PECE2     (1ull << (63 - 49))
399 #define LPCR_P8_PECE3     (1ull << (63 - 50))
400 #define LPCR_P8_PECE4     (1ull << (63 - 51))
401 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
402 #define LPCR_PECE_L_SHIFT (63 - 51)
403 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
404 #define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
405 #define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
406 #define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
407 #define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
408 #define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
409 #define LPCR_MER          (1ull << (63 - 52))
410 #define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
411 #define LPCR_TC           (1ull << (63 - 54))
412 #define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
413 #define LPCR_LPES0        (1ull << (63 - 60))
414 #define LPCR_LPES1        (1ull << (63 - 61))
415 #define LPCR_RMI          (1ull << (63 - 62))
416 #define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
417 #define LPCR_HDICE        (1ull << (63 - 63))
418 
419 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
420 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
421 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
422 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
423 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
424 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
425 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
426 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
427 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
428 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
429 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
430 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
431 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
432 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
433 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
434 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
435 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
436 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
437 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
438 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
439 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
440 #define msr_me   ((env->msr >> MSR_ME)   & 1)
441 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
442 #define msr_se   ((env->msr >> MSR_SE)   & 1)
443 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
444 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
445 #define msr_be   ((env->msr >> MSR_BE)   & 1)
446 #define msr_de   ((env->msr >> MSR_DE)   & 1)
447 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
448 #define msr_al   ((env->msr >> MSR_AL)   & 1)
449 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
450 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
451 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
452 #define msr_is   ((env->msr >> MSR_IS)   & 1)
453 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
454 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
455 #define msr_px   ((env->msr >> MSR_PX)   & 1)
456 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
457 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
458 #define msr_le   ((env->msr >> MSR_LE)   & 1)
459 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
460 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
461 
462 /* Hypervisor bit is more specific */
463 #if defined(TARGET_PPC64)
464 #define MSR_HVB (1ULL << MSR_SHV)
465 #define msr_hv  msr_shv
466 #else
467 #if defined(PPC_EMULATE_32BITS_HYPV)
468 #define MSR_HVB (1ULL << MSR_THV)
469 #define msr_hv  msr_thv
470 #else
471 #define MSR_HVB (0ULL)
472 #define msr_hv  (0)
473 #endif
474 #endif
475 
476 /* DSISR */
477 #define DSISR_NOPTE              0x40000000
478 /* Not permitted by access authority of encoded access authority */
479 #define DSISR_PROTFAULT          0x08000000
480 #define DSISR_ISSTORE            0x02000000
481 /* Not permitted by virtual page class key protection */
482 #define DSISR_AMR                0x00200000
483 
484 /* SRR1 error code fields */
485 
486 #define SRR1_NOPTE               DSISR_NOPTE
487 /* Not permitted due to no-execute or guard bit set */
488 #define SRR1_NOEXEC_GUARD        0x10000000
489 #define SRR1_PROTFAULT           DSISR_PROTFAULT
490 #define SRR1_IAMR                DSISR_AMR
491 
492 /* Facility Status and Control (FSCR) bits */
493 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
494 #define FSCR_TAR        (63 - 55) /* Target Address Register */
495 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
496 #define FSCR_IC_MASK    (0xFFULL)
497 #define FSCR_IC_POS     (63 - 7)
498 #define FSCR_IC_DSCR_SPR3   2
499 #define FSCR_IC_PMU         3
500 #define FSCR_IC_BHRB        4
501 #define FSCR_IC_TM          5
502 #define FSCR_IC_EBB         7
503 #define FSCR_IC_TAR         8
504 
505 /* Exception state register bits definition                                  */
506 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
507 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
508 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
509 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
510 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
511 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
512 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
513 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
514 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
515 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
516 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
517 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
518 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
519 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
520 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
521 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
522 
523 /* Transaction EXception And Summary Register bits                           */
524 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
525 #define TEXASR_DISALLOWED                        (63 - 8)
526 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
527 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
528 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
529 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
530 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
531 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
532 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
533 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
534 #define TEXASR_ABORT                             (63 - 31)
535 #define TEXASR_SUSPENDED                         (63 - 32)
536 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
537 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
538 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
539 #define TEXASR_TFIAR_EXACT                       (63 - 37)
540 #define TEXASR_ROT                               (63 - 38)
541 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
542 
543 enum {
544     POWERPC_FLAG_NONE     = 0x00000000,
545     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
546     POWERPC_FLAG_SPE      = 0x00000001,
547     POWERPC_FLAG_VRE      = 0x00000002,
548     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
549     POWERPC_FLAG_TGPR     = 0x00000004,
550     POWERPC_FLAG_CE       = 0x00000008,
551     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
552     POWERPC_FLAG_SE       = 0x00000010,
553     POWERPC_FLAG_DWE      = 0x00000020,
554     POWERPC_FLAG_UBLE     = 0x00000040,
555     /* Flag for MSR bit 9 signification (BE/DE)                              */
556     POWERPC_FLAG_BE       = 0x00000080,
557     POWERPC_FLAG_DE       = 0x00000100,
558     /* Flag for MSR bit 2 signification (PX/PMM)                             */
559     POWERPC_FLAG_PX       = 0x00000200,
560     POWERPC_FLAG_PMM      = 0x00000400,
561     /* Flag for special features                                             */
562     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
563     POWERPC_FLAG_RTC_CLK  = 0x00010000,
564     POWERPC_FLAG_BUS_CLK  = 0x00020000,
565     /* Has CFAR                                                              */
566     POWERPC_FLAG_CFAR     = 0x00040000,
567     /* Has VSX                                                               */
568     POWERPC_FLAG_VSX      = 0x00080000,
569     /* Has Transaction Memory (ISA 2.07)                                     */
570     POWERPC_FLAG_TM       = 0x00100000,
571 };
572 
573 /*****************************************************************************/
574 /* Floating point status and control register                                */
575 #define FPSCR_FX     31 /* Floating-point exception summary                  */
576 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
577 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
578 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
579 #define FPSCR_UX     27 /* Floating-point underflow exception                */
580 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
581 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
582 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
583 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
584 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
585 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
586 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
587 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
588 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
589 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
590 #define FPSCR_C      16 /* Floating-point result class descriptor            */
591 #define FPSCR_FL     15 /* Floating-point less than or negative              */
592 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
593 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
594 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
595 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
596 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
597 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
598 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
599 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
600 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
601 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
602 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
603 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
604 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
605 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
606 #define FPSCR_RN1    1
607 #define FPSCR_RN     0  /* Floating-point rounding control                   */
608 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
609 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
610 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
611 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
612 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
613 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
614 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
615 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
616 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
617 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
618 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
619 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
620 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
621 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
622 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
623 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
624 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
625 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
626 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
627 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
628 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
629 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
630 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
631 /* Invalid operation exception summary */
632 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
633                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
634                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
635                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
636                                   (1 << FPSCR_VXCVI)))
637 /* exception summary */
638 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
639 /* enabled exception summary */
640 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
641                    0x1F)
642 
643 #define FP_FX		(1ull << FPSCR_FX)
644 #define FP_FEX		(1ull << FPSCR_FEX)
645 #define FP_VX		(1ull << FPSCR_VX)
646 #define FP_OX		(1ull << FPSCR_OX)
647 #define FP_UX		(1ull << FPSCR_UX)
648 #define FP_ZX		(1ull << FPSCR_ZX)
649 #define FP_XX		(1ull << FPSCR_XX)
650 #define FP_VXSNAN	(1ull << FPSCR_VXSNAN)
651 #define FP_VXISI	(1ull << FPSCR_VXISI)
652 #define FP_VXIDI	(1ull << FPSCR_VXIDI)
653 #define FP_VXZDZ	(1ull << FPSCR_VXZDZ)
654 #define FP_VXIMZ	(1ull << FPSCR_VXIMZ)
655 #define FP_VXVC		(1ull << FPSCR_VXVC)
656 #define FP_FR		(1ull << FSPCR_FR)
657 #define FP_FI		(1ull << FPSCR_FI)
658 #define FP_C		(1ull << FPSCR_C)
659 #define FP_FL		(1ull << FPSCR_FL)
660 #define FP_FG		(1ull << FPSCR_FG)
661 #define FP_FE		(1ull << FPSCR_FE)
662 #define FP_FU		(1ull << FPSCR_FU)
663 #define FP_FPCC		(FP_FL | FP_FG | FP_FE | FP_FU)
664 #define FP_FPRF		(FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
665 #define FP_VXSOFT	(1ull << FPSCR_VXSOFT)
666 #define FP_VXSQRT	(1ull << FPSCR_VXSQRT)
667 #define FP_VXCVI	(1ull << FPSCR_VXCVI)
668 #define FP_VE		(1ull << FPSCR_VE)
669 #define FP_OE		(1ull << FPSCR_OE)
670 #define FP_UE		(1ull << FPSCR_UE)
671 #define FP_ZE		(1ull << FPSCR_ZE)
672 #define FP_XE		(1ull << FPSCR_XE)
673 #define FP_NI		(1ull << FPSCR_NI)
674 #define FP_RN1		(1ull << FPSCR_RN1)
675 #define FP_RN		(1ull << FPSCR_RN)
676 
677 /* the exception bits which can be cleared by mcrfs - includes FX */
678 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
679                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
680                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
681                           FP_VXSQRT | FP_VXCVI)
682 
683 /*****************************************************************************/
684 /* Vector status and control register */
685 #define VSCR_NJ		16 /* Vector non-java */
686 #define VSCR_SAT	0 /* Vector saturation */
687 #define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)
688 #define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)
689 
690 /*****************************************************************************/
691 /* BookE e500 MMU registers */
692 
693 #define MAS0_NV_SHIFT      0
694 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
695 
696 #define MAS0_WQ_SHIFT      12
697 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
698 /* Write TLB entry regardless of reservation */
699 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
700 /* Write TLB entry only already in use */
701 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
702 /* Clear TLB entry */
703 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
704 
705 #define MAS0_HES_SHIFT     14
706 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
707 
708 #define MAS0_ESEL_SHIFT    16
709 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
710 
711 #define MAS0_TLBSEL_SHIFT  28
712 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
713 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
714 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
715 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
716 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
717 
718 #define MAS0_ATSEL_SHIFT   31
719 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
720 #define MAS0_ATSEL_TLB     0
721 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
722 
723 #define MAS1_TSIZE_SHIFT   7
724 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
725 
726 #define MAS1_TS_SHIFT      12
727 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
728 
729 #define MAS1_IND_SHIFT     13
730 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
731 
732 #define MAS1_TID_SHIFT     16
733 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
734 
735 #define MAS1_IPROT_SHIFT   30
736 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
737 
738 #define MAS1_VALID_SHIFT   31
739 #define MAS1_VALID         0x80000000
740 
741 #define MAS2_EPN_SHIFT     12
742 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
743 
744 #define MAS2_ACM_SHIFT     6
745 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
746 
747 #define MAS2_VLE_SHIFT     5
748 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
749 
750 #define MAS2_W_SHIFT       4
751 #define MAS2_W             (1 << MAS2_W_SHIFT)
752 
753 #define MAS2_I_SHIFT       3
754 #define MAS2_I             (1 << MAS2_I_SHIFT)
755 
756 #define MAS2_M_SHIFT       2
757 #define MAS2_M             (1 << MAS2_M_SHIFT)
758 
759 #define MAS2_G_SHIFT       1
760 #define MAS2_G             (1 << MAS2_G_SHIFT)
761 
762 #define MAS2_E_SHIFT       0
763 #define MAS2_E             (1 << MAS2_E_SHIFT)
764 
765 #define MAS3_RPN_SHIFT     12
766 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
767 
768 #define MAS3_U0                 0x00000200
769 #define MAS3_U1                 0x00000100
770 #define MAS3_U2                 0x00000080
771 #define MAS3_U3                 0x00000040
772 #define MAS3_UX                 0x00000020
773 #define MAS3_SX                 0x00000010
774 #define MAS3_UW                 0x00000008
775 #define MAS3_SW                 0x00000004
776 #define MAS3_UR                 0x00000002
777 #define MAS3_SR                 0x00000001
778 #define MAS3_SPSIZE_SHIFT       1
779 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
780 
781 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
782 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
783 #define MAS4_TIDSELD_MASK       0x00030000
784 #define MAS4_TIDSELD_PID0       0x00000000
785 #define MAS4_TIDSELD_PID1       0x00010000
786 #define MAS4_TIDSELD_PID2       0x00020000
787 #define MAS4_TIDSELD_PIDZ       0x00030000
788 #define MAS4_INDD               0x00008000      /* Default IND */
789 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
790 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
791 #define MAS4_ACMD               0x00000040
792 #define MAS4_VLED               0x00000020
793 #define MAS4_WD                 0x00000010
794 #define MAS4_ID                 0x00000008
795 #define MAS4_MD                 0x00000004
796 #define MAS4_GD                 0x00000002
797 #define MAS4_ED                 0x00000001
798 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
799 #define MAS4_WIMGED_SHIFT       0
800 
801 #define MAS5_SGS                0x80000000
802 #define MAS5_SLPID_MASK         0x00000fff
803 
804 #define MAS6_SPID0              0x3fff0000
805 #define MAS6_SPID1              0x00007ffe
806 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
807 #define MAS6_SAS                0x00000001
808 #define MAS6_SPID               MAS6_SPID0
809 #define MAS6_SIND               0x00000002      /* Indirect page */
810 #define MAS6_SIND_SHIFT         1
811 #define MAS6_SPID_MASK          0x3fff0000
812 #define MAS6_SPID_SHIFT         16
813 #define MAS6_ISIZE_MASK         0x00000f80
814 #define MAS6_ISIZE_SHIFT        7
815 
816 #define MAS7_RPN                0xffffffff
817 
818 #define MAS8_TGS                0x80000000
819 #define MAS8_VF                 0x40000000
820 #define MAS8_TLBPID             0x00000fff
821 
822 /* Bit definitions for MMUCFG */
823 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
824 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
825 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
826 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
827 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
828 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
829 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
830 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
831 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
832 
833 /* Bit definitions for MMUCSR0 */
834 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
835 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
836 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
837 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
838 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
839                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
840 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
841 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
842 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
843 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
844 
845 /* TLBnCFG encoding */
846 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
847 #define TLBnCFG_HES             0x00002000      /* HW select supported */
848 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
849 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
850 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
851 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
852 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
853 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
854 #define TLBnCFG_MINSIZE_SHIFT   20
855 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
856 #define TLBnCFG_MAXSIZE_SHIFT   16
857 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
858 #define TLBnCFG_ASSOC_SHIFT     24
859 
860 /* TLBnPS encoding */
861 #define TLBnPS_4K               0x00000004
862 #define TLBnPS_8K               0x00000008
863 #define TLBnPS_16K              0x00000010
864 #define TLBnPS_32K              0x00000020
865 #define TLBnPS_64K              0x00000040
866 #define TLBnPS_128K             0x00000080
867 #define TLBnPS_256K             0x00000100
868 #define TLBnPS_512K             0x00000200
869 #define TLBnPS_1M               0x00000400
870 #define TLBnPS_2M               0x00000800
871 #define TLBnPS_4M               0x00001000
872 #define TLBnPS_8M               0x00002000
873 #define TLBnPS_16M              0x00004000
874 #define TLBnPS_32M              0x00008000
875 #define TLBnPS_64M              0x00010000
876 #define TLBnPS_128M             0x00020000
877 #define TLBnPS_256M             0x00040000
878 #define TLBnPS_512M             0x00080000
879 #define TLBnPS_1G               0x00100000
880 #define TLBnPS_2G               0x00200000
881 #define TLBnPS_4G               0x00400000
882 #define TLBnPS_8G               0x00800000
883 #define TLBnPS_16G              0x01000000
884 #define TLBnPS_32G              0x02000000
885 #define TLBnPS_64G              0x04000000
886 #define TLBnPS_128G             0x08000000
887 #define TLBnPS_256G             0x10000000
888 
889 /* tlbilx action encoding */
890 #define TLBILX_T_ALL                    0
891 #define TLBILX_T_TID                    1
892 #define TLBILX_T_FULLMATCH              3
893 #define TLBILX_T_CLASS0                 4
894 #define TLBILX_T_CLASS1                 5
895 #define TLBILX_T_CLASS2                 6
896 #define TLBILX_T_CLASS3                 7
897 
898 /* BookE 2.06 helper defines */
899 
900 #define BOOKE206_FLUSH_TLB0    (1 << 0)
901 #define BOOKE206_FLUSH_TLB1    (1 << 1)
902 #define BOOKE206_FLUSH_TLB2    (1 << 2)
903 #define BOOKE206_FLUSH_TLB3    (1 << 3)
904 
905 /* number of possible TLBs */
906 #define BOOKE206_MAX_TLBN      4
907 
908 /*****************************************************************************/
909 /* Embedded.Processor Control */
910 
911 #define DBELL_TYPE_SHIFT               27
912 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
913 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
914 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
915 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
916 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
917 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
918 
919 #define DBELL_BRDCAST                  (1 << 26)
920 #define DBELL_LPIDTAG_SHIFT            14
921 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
922 #define DBELL_PIRTAG_MASK              0x3fff
923 
924 /*****************************************************************************/
925 /* Segment page size information, used by recent hash MMUs
926  * The format of this structure mirrors kvm_ppc_smmu_info
927  */
928 
929 #define PPC_PAGE_SIZES_MAX_SZ   8
930 
931 struct ppc_one_page_size {
932     uint32_t page_shift;  /* Page shift (or 0) */
933     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
934 };
935 
936 struct ppc_one_seg_page_size {
937     uint32_t page_shift;  /* Base page shift of segment (or 0) */
938     uint32_t slb_enc;     /* SLB encoding for BookS */
939     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
940 };
941 
942 struct ppc_segment_page_sizes {
943     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
944 };
945 
946 
947 /*****************************************************************************/
948 /* The whole PowerPC CPU context */
949 #define NB_MMU_MODES    8
950 
951 #define PPC_CPU_OPCODES_LEN          0x40
952 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
953 
954 struct CPUPPCState {
955     /* First are the most commonly used resources
956      * during translated code execution
957      */
958     /* general purpose registers */
959     target_ulong gpr[32];
960     /* Storage for GPR MSB, used by the SPE extension */
961     target_ulong gprh[32];
962     /* LR */
963     target_ulong lr;
964     /* CTR */
965     target_ulong ctr;
966     /* condition register */
967     uint32_t crf[8];
968 #if defined(TARGET_PPC64)
969     /* CFAR */
970     target_ulong cfar;
971 #endif
972     /* XER (with SO, OV, CA split out) */
973     target_ulong xer;
974     target_ulong so;
975     target_ulong ov;
976     target_ulong ca;
977     target_ulong ov32;
978     target_ulong ca32;
979     /* Reservation address */
980     target_ulong reserve_addr;
981     /* Reservation value */
982     target_ulong reserve_val;
983     target_ulong reserve_val2;
984     /* Reservation store address */
985     target_ulong reserve_ea;
986     /* Reserved store source register and size */
987     target_ulong reserve_info;
988 
989     /* Those ones are used in supervisor mode only */
990     /* machine state register */
991     target_ulong msr;
992     /* temporary general purpose registers */
993     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
994 
995     /* Floating point execution context */
996     float_status fp_status;
997     /* floating point registers */
998     float64 fpr[32];
999     /* floating point status and control register */
1000     target_ulong fpscr;
1001 
1002     /* Next instruction pointer */
1003     target_ulong nip;
1004 
1005     int access_type; /* when a memory exception occurs, the access
1006                         type is stored here */
1007 
1008     CPU_COMMON
1009 
1010     /* MMU context - only relevant for full system emulation */
1011 #if !defined(CONFIG_USER_ONLY)
1012 #if defined(TARGET_PPC64)
1013     /* PowerPC 64 SLB area */
1014     ppc_slb_t slb[MAX_SLB_ENTRIES];
1015     int32_t slb_nr;
1016     /* tcg TLB needs flush (deferred slb inval instruction typically) */
1017 #endif
1018     /* segment registers */
1019     target_ulong sr[32];
1020     /* BATs */
1021     uint32_t nb_BATs;
1022     target_ulong DBAT[2][8];
1023     target_ulong IBAT[2][8];
1024     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1025     int32_t nb_tlb;      /* Total number of TLB                              */
1026     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1027     int nb_ways;     /* Number of ways in the TLB set                        */
1028     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1029     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1030     int nb_pids;     /* Number of available PID registers                    */
1031     int tlb_type;    /* Type of TLB we're dealing with                       */
1032     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1033     /* 403 dedicated access protection registers */
1034     target_ulong pb[4];
1035     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1036     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1037     uint32_t tlb_need_flush; /* Delayed flush needed */
1038 #define TLB_NEED_LOCAL_FLUSH   0x1
1039 #define TLB_NEED_GLOBAL_FLUSH  0x2
1040 #endif
1041 
1042     /* Other registers */
1043     /* Special purpose registers */
1044     target_ulong spr[1024];
1045     ppc_spr_t spr_cb[1024];
1046     /* Altivec registers */
1047     ppc_avr_t avr[32];
1048     uint32_t vscr;
1049     /* VSX registers */
1050     uint64_t vsr[32];
1051     /* SPE registers */
1052     uint64_t spe_acc;
1053     uint32_t spe_fscr;
1054     /* SPE and Altivec can share a status since they will never be used
1055      * simultaneously */
1056     float_status vec_status;
1057 
1058     /* Internal devices resources */
1059     /* Time base and decrementer */
1060     ppc_tb_t *tb_env;
1061     /* Device control registers */
1062     ppc_dcr_t *dcr_env;
1063 
1064     int dcache_line_size;
1065     int icache_line_size;
1066 
1067     /* Those resources are used during exception processing */
1068     /* CPU model definition */
1069     target_ulong msr_mask;
1070     powerpc_mmu_t mmu_model;
1071     powerpc_excp_t excp_model;
1072     powerpc_input_t bus_model;
1073     int bfd_mach;
1074     uint32_t flags;
1075     uint64_t insns_flags;
1076     uint64_t insns_flags2;
1077 #if defined(TARGET_PPC64)
1078     struct ppc_segment_page_sizes sps;
1079     ppc_slb_t vrma_slb;
1080     target_ulong rmls;
1081     bool ci_large_pages;
1082 #endif
1083 
1084 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1085     uint64_t vpa_addr;
1086     uint64_t slb_shadow_addr, slb_shadow_size;
1087     uint64_t dtl_addr, dtl_size;
1088 #endif /* TARGET_PPC64 */
1089 
1090     int error_code;
1091     uint32_t pending_interrupts;
1092 #if !defined(CONFIG_USER_ONLY)
1093     /* This is the IRQ controller, which is implementation dependent
1094      * and only relevant when emulating a complete machine.
1095      */
1096     uint32_t irq_input_state;
1097     void **irq_inputs;
1098     /* Exception vectors */
1099     target_ulong excp_vectors[POWERPC_EXCP_NB];
1100     target_ulong excp_prefix;
1101     target_ulong ivor_mask;
1102     target_ulong ivpr_mask;
1103     target_ulong hreset_vector;
1104     hwaddr mpic_iack;
1105     /* true when the external proxy facility mode is enabled */
1106     bool mpic_proxy;
1107     /* set when the processor has an HV mode, thus HV priv
1108      * instructions and SPRs are diallowed if MSR:HV is 0
1109      */
1110     bool has_hv_mode;
1111     /* On P7/P8, set when in PM state, we need to handle resume
1112      * in a special way (such as routing some resume causes to
1113      * 0x100), so flag this here.
1114      */
1115     bool in_pm_state;
1116 #endif
1117 
1118     /* Those resources are used only during code translation */
1119     /* opcode handlers */
1120     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1121 
1122     /* Those resources are used only in QEMU core */
1123     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1124     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1125     int immu_idx;         /* precomputed MMU index to speed up insn access */
1126     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1127 
1128     /* Power management */
1129     int (*check_pow)(CPUPPCState *env);
1130 
1131 #if !defined(CONFIG_USER_ONLY)
1132     void *load_info;    /* Holds boot loading state.  */
1133 #endif
1134 
1135     /* booke timers */
1136 
1137     /* Specifies bit locations of the Time Base used to signal a fixed timer
1138      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1139      *
1140      * 0 selects the least significant bit.
1141      * 63 selects the most significant bit.
1142      */
1143     uint8_t fit_period[4];
1144     uint8_t wdt_period[4];
1145 
1146     /* Transactional memory state */
1147     target_ulong tm_gpr[32];
1148     ppc_avr_t tm_vsr[64];
1149     uint64_t tm_cr;
1150     uint64_t tm_lr;
1151     uint64_t tm_ctr;
1152     uint64_t tm_fpscr;
1153     uint64_t tm_amr;
1154     uint64_t tm_ppr;
1155     uint64_t tm_vrsave;
1156     uint32_t tm_vscr;
1157     uint64_t tm_dscr;
1158     uint64_t tm_tar;
1159 };
1160 
1161 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1162 do {                                            \
1163     env->fit_period[0] = (a_);                  \
1164     env->fit_period[1] = (b_);                  \
1165     env->fit_period[2] = (c_);                  \
1166     env->fit_period[3] = (d_);                  \
1167  } while (0)
1168 
1169 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1170 do {                                            \
1171     env->wdt_period[0] = (a_);                  \
1172     env->wdt_period[1] = (b_);                  \
1173     env->wdt_period[2] = (c_);                  \
1174     env->wdt_period[3] = (d_);                  \
1175  } while (0)
1176 
1177 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1178 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1179 
1180 /**
1181  * PowerPCCPU:
1182  * @env: #CPUPPCState
1183  * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1184  * @max_compat: Maximal supported logical PVR from the command line
1185  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1186  *
1187  * A PowerPC CPU.
1188  */
1189 struct PowerPCCPU {
1190     /*< private >*/
1191     CPUState parent_obj;
1192     /*< public >*/
1193 
1194     CPUPPCState env;
1195     int cpu_dt_id;
1196     uint32_t max_compat;
1197     uint32_t compat_pvr;
1198     PPCVirtualHypervisor *vhyp;
1199 
1200     /* Fields related to migration compatibility hacks */
1201     bool pre_2_8_migration;
1202     target_ulong mig_msr_mask;
1203     uint64_t mig_insns_flags;
1204     uint64_t mig_insns_flags2;
1205     uint32_t mig_nb_BATs;
1206 };
1207 
1208 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1209 {
1210     return container_of(env, PowerPCCPU, env);
1211 }
1212 
1213 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1214 
1215 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1216 
1217 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1218 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1219 
1220 struct PPCVirtualHypervisor {
1221     Object parent;
1222 };
1223 
1224 struct PPCVirtualHypervisorClass {
1225     InterfaceClass parent;
1226     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1227     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1228     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1229                                          hwaddr ptex, int n);
1230     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1231                         const ppc_hash_pte64_t *hptes,
1232                         hwaddr ptex, int n);
1233     void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1234                        uint64_t pte0, uint64_t pte1);
1235     uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1236 };
1237 
1238 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1239 #define PPC_VIRTUAL_HYPERVISOR(obj)                 \
1240     OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1241 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass)         \
1242     OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1243                        TYPE_PPC_VIRTUAL_HYPERVISOR)
1244 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1245     OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1246                      TYPE_PPC_VIRTUAL_HYPERVISOR)
1247 
1248 void ppc_cpu_do_interrupt(CPUState *cpu);
1249 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1250 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1251                         int flags);
1252 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1253                              fprintf_function cpu_fprintf, int flags);
1254 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1255 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1256 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1257 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1258 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1259 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1260                                int cpuid, void *opaque);
1261 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1262                                int cpuid, void *opaque);
1263 #ifndef CONFIG_USER_ONLY
1264 void ppc_cpu_do_system_reset(CPUState *cs);
1265 extern const struct VMStateDescription vmstate_ppc_cpu;
1266 #endif
1267 
1268 /*****************************************************************************/
1269 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1270 void ppc_translate_init(void);
1271 const char *ppc_cpu_lookup_alias(const char *alias);
1272 /* you can call this signal handler from your SIGBUS and SIGSEGV
1273    signal handlers to inform the virtual CPU of exceptions. non zero
1274    is returned if the signal was handled by the virtual CPU.  */
1275 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1276                             void *puc);
1277 #if defined(CONFIG_USER_ONLY)
1278 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1279                              int mmu_idx);
1280 #endif
1281 
1282 #if !defined(CONFIG_USER_ONLY)
1283 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1284 #endif /* !defined(CONFIG_USER_ONLY) */
1285 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1286 
1287 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1288 #if defined(TARGET_PPC64)
1289 #endif
1290 
1291 /* Time-base and decrementer management */
1292 #ifndef NO_CPU_IO_DEFS
1293 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1294 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1295 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1296 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1297 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1298 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1299 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1300 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1301 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1302 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1303 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1304 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1305 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1306 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1307 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1308 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1309 #if !defined(CONFIG_USER_ONLY)
1310 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1311 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1312 target_ulong load_40x_pit (CPUPPCState *env);
1313 void store_40x_pit (CPUPPCState *env, target_ulong val);
1314 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1315 void store_40x_sler (CPUPPCState *env, uint32_t val);
1316 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1317 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1318 void ppc_tlb_invalidate_all (CPUPPCState *env);
1319 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1320 void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1321 #endif
1322 #endif
1323 
1324 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1325 
1326 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1327 {
1328     uint64_t gprv;
1329 
1330     gprv = env->gpr[gprn];
1331     if (env->flags & POWERPC_FLAG_SPE) {
1332         /* If the CPU implements the SPE extension, we have to get the
1333          * high bits of the GPR from the gprh storage area
1334          */
1335         gprv &= 0xFFFFFFFFULL;
1336         gprv |= (uint64_t)env->gprh[gprn] << 32;
1337     }
1338 
1339     return gprv;
1340 }
1341 
1342 /* Device control registers */
1343 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1344 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1345 
1346 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1347 
1348 #define cpu_signal_handler cpu_ppc_signal_handler
1349 #define cpu_list ppc_cpu_list
1350 
1351 /* MMU modes definitions */
1352 #define MMU_USER_IDX 0
1353 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1354 {
1355     return ifetch ? env->immu_idx : env->dmmu_idx;
1356 }
1357 
1358 /* Compatibility modes */
1359 #if defined(TARGET_PPC64)
1360 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1361                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1362 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1363 #if !defined(CONFIG_USER_ONLY)
1364 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1365 #endif
1366 int ppc_compat_max_threads(PowerPCCPU *cpu);
1367 #endif /* defined(TARGET_PPC64) */
1368 
1369 #include "exec/cpu-all.h"
1370 
1371 /*****************************************************************************/
1372 /* CRF definitions */
1373 #define CRF_LT_BIT    3
1374 #define CRF_GT_BIT    2
1375 #define CRF_EQ_BIT    1
1376 #define CRF_SO_BIT    0
1377 #define CRF_LT        (1 << CRF_LT_BIT)
1378 #define CRF_GT        (1 << CRF_GT_BIT)
1379 #define CRF_EQ        (1 << CRF_EQ_BIT)
1380 #define CRF_SO        (1 << CRF_SO_BIT)
1381 /* For SPE extensions */
1382 #define CRF_CH        (1 << CRF_LT_BIT)
1383 #define CRF_CL        (1 << CRF_GT_BIT)
1384 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1385 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1386 
1387 /* XER definitions */
1388 #define XER_SO  31
1389 #define XER_OV  30
1390 #define XER_CA  29
1391 #define XER_OV32  19
1392 #define XER_CA32  18
1393 #define XER_CMP  8
1394 #define XER_BC   0
1395 #define xer_so  (env->so)
1396 #define xer_ov  (env->ov)
1397 #define xer_ca  (env->ca)
1398 #define xer_ov32  (env->ov)
1399 #define xer_ca32  (env->ca)
1400 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1401 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1402 
1403 /* SPR definitions */
1404 #define SPR_MQ                (0x000)
1405 #define SPR_XER               (0x001)
1406 #define SPR_601_VRTCU         (0x004)
1407 #define SPR_601_VRTCL         (0x005)
1408 #define SPR_601_UDECR         (0x006)
1409 #define SPR_LR                (0x008)
1410 #define SPR_CTR               (0x009)
1411 #define SPR_UAMR              (0x00D)
1412 #define SPR_DSCR              (0x011)
1413 #define SPR_DSISR             (0x012)
1414 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1415 #define SPR_601_RTCU          (0x014)
1416 #define SPR_601_RTCL          (0x015)
1417 #define SPR_DECR              (0x016)
1418 #define SPR_SDR1              (0x019)
1419 #define SPR_SRR0              (0x01A)
1420 #define SPR_SRR1              (0x01B)
1421 #define SPR_CFAR              (0x01C)
1422 #define SPR_AMR               (0x01D)
1423 #define SPR_ACOP              (0x01F)
1424 #define SPR_BOOKE_PID         (0x030)
1425 #define SPR_BOOKS_PID         (0x030)
1426 #define SPR_BOOKE_DECAR       (0x036)
1427 #define SPR_BOOKE_CSRR0       (0x03A)
1428 #define SPR_BOOKE_CSRR1       (0x03B)
1429 #define SPR_BOOKE_DEAR        (0x03D)
1430 #define SPR_IAMR              (0x03D)
1431 #define SPR_BOOKE_ESR         (0x03E)
1432 #define SPR_BOOKE_IVPR        (0x03F)
1433 #define SPR_MPC_EIE           (0x050)
1434 #define SPR_MPC_EID           (0x051)
1435 #define SPR_MPC_NRI           (0x052)
1436 #define SPR_TFHAR             (0x080)
1437 #define SPR_TFIAR             (0x081)
1438 #define SPR_TEXASR            (0x082)
1439 #define SPR_TEXASRU           (0x083)
1440 #define SPR_UCTRL             (0x088)
1441 #define SPR_MPC_CMPA          (0x090)
1442 #define SPR_MPC_CMPB          (0x091)
1443 #define SPR_MPC_CMPC          (0x092)
1444 #define SPR_MPC_CMPD          (0x093)
1445 #define SPR_MPC_ECR           (0x094)
1446 #define SPR_MPC_DER           (0x095)
1447 #define SPR_MPC_COUNTA        (0x096)
1448 #define SPR_MPC_COUNTB        (0x097)
1449 #define SPR_CTRL              (0x098)
1450 #define SPR_MPC_CMPE          (0x098)
1451 #define SPR_MPC_CMPF          (0x099)
1452 #define SPR_FSCR              (0x099)
1453 #define SPR_MPC_CMPG          (0x09A)
1454 #define SPR_MPC_CMPH          (0x09B)
1455 #define SPR_MPC_LCTRL1        (0x09C)
1456 #define SPR_MPC_LCTRL2        (0x09D)
1457 #define SPR_UAMOR             (0x09D)
1458 #define SPR_MPC_ICTRL         (0x09E)
1459 #define SPR_MPC_BAR           (0x09F)
1460 #define SPR_PSPB              (0x09F)
1461 #define SPR_DAWR              (0x0B4)
1462 #define SPR_RPR               (0x0BA)
1463 #define SPR_CIABR             (0x0BB)
1464 #define SPR_DAWRX             (0x0BC)
1465 #define SPR_HFSCR             (0x0BE)
1466 #define SPR_VRSAVE            (0x100)
1467 #define SPR_USPRG0            (0x100)
1468 #define SPR_USPRG1            (0x101)
1469 #define SPR_USPRG2            (0x102)
1470 #define SPR_USPRG3            (0x103)
1471 #define SPR_USPRG4            (0x104)
1472 #define SPR_USPRG5            (0x105)
1473 #define SPR_USPRG6            (0x106)
1474 #define SPR_USPRG7            (0x107)
1475 #define SPR_VTBL              (0x10C)
1476 #define SPR_VTBU              (0x10D)
1477 #define SPR_SPRG0             (0x110)
1478 #define SPR_SPRG1             (0x111)
1479 #define SPR_SPRG2             (0x112)
1480 #define SPR_SPRG3             (0x113)
1481 #define SPR_SPRG4             (0x114)
1482 #define SPR_SCOMC             (0x114)
1483 #define SPR_SPRG5             (0x115)
1484 #define SPR_SCOMD             (0x115)
1485 #define SPR_SPRG6             (0x116)
1486 #define SPR_SPRG7             (0x117)
1487 #define SPR_ASR               (0x118)
1488 #define SPR_EAR               (0x11A)
1489 #define SPR_TBL               (0x11C)
1490 #define SPR_TBU               (0x11D)
1491 #define SPR_TBU40             (0x11E)
1492 #define SPR_SVR               (0x11E)
1493 #define SPR_BOOKE_PIR         (0x11E)
1494 #define SPR_PVR               (0x11F)
1495 #define SPR_HSPRG0            (0x130)
1496 #define SPR_BOOKE_DBSR        (0x130)
1497 #define SPR_HSPRG1            (0x131)
1498 #define SPR_HDSISR            (0x132)
1499 #define SPR_HDAR              (0x133)
1500 #define SPR_BOOKE_EPCR        (0x133)
1501 #define SPR_SPURR             (0x134)
1502 #define SPR_BOOKE_DBCR0       (0x134)
1503 #define SPR_IBCR              (0x135)
1504 #define SPR_PURR              (0x135)
1505 #define SPR_BOOKE_DBCR1       (0x135)
1506 #define SPR_DBCR              (0x136)
1507 #define SPR_HDEC              (0x136)
1508 #define SPR_BOOKE_DBCR2       (0x136)
1509 #define SPR_HIOR              (0x137)
1510 #define SPR_MBAR              (0x137)
1511 #define SPR_RMOR              (0x138)
1512 #define SPR_BOOKE_IAC1        (0x138)
1513 #define SPR_HRMOR             (0x139)
1514 #define SPR_BOOKE_IAC2        (0x139)
1515 #define SPR_HSRR0             (0x13A)
1516 #define SPR_BOOKE_IAC3        (0x13A)
1517 #define SPR_HSRR1             (0x13B)
1518 #define SPR_BOOKE_IAC4        (0x13B)
1519 #define SPR_BOOKE_DAC1        (0x13C)
1520 #define SPR_MMCRH             (0x13C)
1521 #define SPR_DABR2             (0x13D)
1522 #define SPR_BOOKE_DAC2        (0x13D)
1523 #define SPR_TFMR              (0x13D)
1524 #define SPR_BOOKE_DVC1        (0x13E)
1525 #define SPR_LPCR              (0x13E)
1526 #define SPR_BOOKE_DVC2        (0x13F)
1527 #define SPR_LPIDR             (0x13F)
1528 #define SPR_BOOKE_TSR         (0x150)
1529 #define SPR_HMER              (0x150)
1530 #define SPR_HMEER             (0x151)
1531 #define SPR_PCR               (0x152)
1532 #define SPR_BOOKE_LPIDR       (0x152)
1533 #define SPR_BOOKE_TCR         (0x154)
1534 #define SPR_BOOKE_TLB0PS      (0x158)
1535 #define SPR_BOOKE_TLB1PS      (0x159)
1536 #define SPR_BOOKE_TLB2PS      (0x15A)
1537 #define SPR_BOOKE_TLB3PS      (0x15B)
1538 #define SPR_AMOR              (0x15D)
1539 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1540 #define SPR_BOOKE_IVOR0       (0x190)
1541 #define SPR_BOOKE_IVOR1       (0x191)
1542 #define SPR_BOOKE_IVOR2       (0x192)
1543 #define SPR_BOOKE_IVOR3       (0x193)
1544 #define SPR_BOOKE_IVOR4       (0x194)
1545 #define SPR_BOOKE_IVOR5       (0x195)
1546 #define SPR_BOOKE_IVOR6       (0x196)
1547 #define SPR_BOOKE_IVOR7       (0x197)
1548 #define SPR_BOOKE_IVOR8       (0x198)
1549 #define SPR_BOOKE_IVOR9       (0x199)
1550 #define SPR_BOOKE_IVOR10      (0x19A)
1551 #define SPR_BOOKE_IVOR11      (0x19B)
1552 #define SPR_BOOKE_IVOR12      (0x19C)
1553 #define SPR_BOOKE_IVOR13      (0x19D)
1554 #define SPR_BOOKE_IVOR14      (0x19E)
1555 #define SPR_BOOKE_IVOR15      (0x19F)
1556 #define SPR_BOOKE_IVOR38      (0x1B0)
1557 #define SPR_BOOKE_IVOR39      (0x1B1)
1558 #define SPR_BOOKE_IVOR40      (0x1B2)
1559 #define SPR_BOOKE_IVOR41      (0x1B3)
1560 #define SPR_BOOKE_IVOR42      (0x1B4)
1561 #define SPR_BOOKE_GIVOR2      (0x1B8)
1562 #define SPR_BOOKE_GIVOR3      (0x1B9)
1563 #define SPR_BOOKE_GIVOR4      (0x1BA)
1564 #define SPR_BOOKE_GIVOR8      (0x1BB)
1565 #define SPR_BOOKE_GIVOR13     (0x1BC)
1566 #define SPR_BOOKE_GIVOR14     (0x1BD)
1567 #define SPR_TIR               (0x1BE)
1568 #define SPR_BOOKE_SPEFSCR     (0x200)
1569 #define SPR_Exxx_BBEAR        (0x201)
1570 #define SPR_Exxx_BBTAR        (0x202)
1571 #define SPR_Exxx_L1CFG0       (0x203)
1572 #define SPR_Exxx_L1CFG1       (0x204)
1573 #define SPR_Exxx_NPIDR        (0x205)
1574 #define SPR_ATBL              (0x20E)
1575 #define SPR_ATBU              (0x20F)
1576 #define SPR_IBAT0U            (0x210)
1577 #define SPR_BOOKE_IVOR32      (0x210)
1578 #define SPR_RCPU_MI_GRA       (0x210)
1579 #define SPR_IBAT0L            (0x211)
1580 #define SPR_BOOKE_IVOR33      (0x211)
1581 #define SPR_IBAT1U            (0x212)
1582 #define SPR_BOOKE_IVOR34      (0x212)
1583 #define SPR_IBAT1L            (0x213)
1584 #define SPR_BOOKE_IVOR35      (0x213)
1585 #define SPR_IBAT2U            (0x214)
1586 #define SPR_BOOKE_IVOR36      (0x214)
1587 #define SPR_IBAT2L            (0x215)
1588 #define SPR_BOOKE_IVOR37      (0x215)
1589 #define SPR_IBAT3U            (0x216)
1590 #define SPR_IBAT3L            (0x217)
1591 #define SPR_DBAT0U            (0x218)
1592 #define SPR_RCPU_L2U_GRA      (0x218)
1593 #define SPR_DBAT0L            (0x219)
1594 #define SPR_DBAT1U            (0x21A)
1595 #define SPR_DBAT1L            (0x21B)
1596 #define SPR_DBAT2U            (0x21C)
1597 #define SPR_DBAT2L            (0x21D)
1598 #define SPR_DBAT3U            (0x21E)
1599 #define SPR_DBAT3L            (0x21F)
1600 #define SPR_IBAT4U            (0x230)
1601 #define SPR_RPCU_BBCMCR       (0x230)
1602 #define SPR_MPC_IC_CST        (0x230)
1603 #define SPR_Exxx_CTXCR        (0x230)
1604 #define SPR_IBAT4L            (0x231)
1605 #define SPR_MPC_IC_ADR        (0x231)
1606 #define SPR_Exxx_DBCR3        (0x231)
1607 #define SPR_IBAT5U            (0x232)
1608 #define SPR_MPC_IC_DAT        (0x232)
1609 #define SPR_Exxx_DBCNT        (0x232)
1610 #define SPR_IBAT5L            (0x233)
1611 #define SPR_IBAT6U            (0x234)
1612 #define SPR_IBAT6L            (0x235)
1613 #define SPR_IBAT7U            (0x236)
1614 #define SPR_IBAT7L            (0x237)
1615 #define SPR_DBAT4U            (0x238)
1616 #define SPR_RCPU_L2U_MCR      (0x238)
1617 #define SPR_MPC_DC_CST        (0x238)
1618 #define SPR_Exxx_ALTCTXCR     (0x238)
1619 #define SPR_DBAT4L            (0x239)
1620 #define SPR_MPC_DC_ADR        (0x239)
1621 #define SPR_DBAT5U            (0x23A)
1622 #define SPR_BOOKE_MCSRR0      (0x23A)
1623 #define SPR_MPC_DC_DAT        (0x23A)
1624 #define SPR_DBAT5L            (0x23B)
1625 #define SPR_BOOKE_MCSRR1      (0x23B)
1626 #define SPR_DBAT6U            (0x23C)
1627 #define SPR_BOOKE_MCSR        (0x23C)
1628 #define SPR_DBAT6L            (0x23D)
1629 #define SPR_Exxx_MCAR         (0x23D)
1630 #define SPR_DBAT7U            (0x23E)
1631 #define SPR_BOOKE_DSRR0       (0x23E)
1632 #define SPR_DBAT7L            (0x23F)
1633 #define SPR_BOOKE_DSRR1       (0x23F)
1634 #define SPR_BOOKE_SPRG8       (0x25C)
1635 #define SPR_BOOKE_SPRG9       (0x25D)
1636 #define SPR_BOOKE_MAS0        (0x270)
1637 #define SPR_BOOKE_MAS1        (0x271)
1638 #define SPR_BOOKE_MAS2        (0x272)
1639 #define SPR_BOOKE_MAS3        (0x273)
1640 #define SPR_BOOKE_MAS4        (0x274)
1641 #define SPR_BOOKE_MAS5        (0x275)
1642 #define SPR_BOOKE_MAS6        (0x276)
1643 #define SPR_BOOKE_PID1        (0x279)
1644 #define SPR_BOOKE_PID2        (0x27A)
1645 #define SPR_MPC_DPDR          (0x280)
1646 #define SPR_MPC_IMMR          (0x288)
1647 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1648 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1649 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1650 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1651 #define SPR_BOOKE_EPR         (0x2BE)
1652 #define SPR_PERF0             (0x300)
1653 #define SPR_RCPU_MI_RBA0      (0x300)
1654 #define SPR_MPC_MI_CTR        (0x300)
1655 #define SPR_POWER_USIER       (0x300)
1656 #define SPR_PERF1             (0x301)
1657 #define SPR_RCPU_MI_RBA1      (0x301)
1658 #define SPR_POWER_UMMCR2      (0x301)
1659 #define SPR_PERF2             (0x302)
1660 #define SPR_RCPU_MI_RBA2      (0x302)
1661 #define SPR_MPC_MI_AP         (0x302)
1662 #define SPR_POWER_UMMCRA      (0x302)
1663 #define SPR_PERF3             (0x303)
1664 #define SPR_RCPU_MI_RBA3      (0x303)
1665 #define SPR_MPC_MI_EPN        (0x303)
1666 #define SPR_POWER_UPMC1       (0x303)
1667 #define SPR_PERF4             (0x304)
1668 #define SPR_POWER_UPMC2       (0x304)
1669 #define SPR_PERF5             (0x305)
1670 #define SPR_MPC_MI_TWC        (0x305)
1671 #define SPR_POWER_UPMC3       (0x305)
1672 #define SPR_PERF6             (0x306)
1673 #define SPR_MPC_MI_RPN        (0x306)
1674 #define SPR_POWER_UPMC4       (0x306)
1675 #define SPR_PERF7             (0x307)
1676 #define SPR_POWER_UPMC5       (0x307)
1677 #define SPR_PERF8             (0x308)
1678 #define SPR_RCPU_L2U_RBA0     (0x308)
1679 #define SPR_MPC_MD_CTR        (0x308)
1680 #define SPR_POWER_UPMC6       (0x308)
1681 #define SPR_PERF9             (0x309)
1682 #define SPR_RCPU_L2U_RBA1     (0x309)
1683 #define SPR_MPC_MD_CASID      (0x309)
1684 #define SPR_970_UPMC7         (0X309)
1685 #define SPR_PERFA             (0x30A)
1686 #define SPR_RCPU_L2U_RBA2     (0x30A)
1687 #define SPR_MPC_MD_AP         (0x30A)
1688 #define SPR_970_UPMC8         (0X30A)
1689 #define SPR_PERFB             (0x30B)
1690 #define SPR_RCPU_L2U_RBA3     (0x30B)
1691 #define SPR_MPC_MD_EPN        (0x30B)
1692 #define SPR_POWER_UMMCR0      (0X30B)
1693 #define SPR_PERFC             (0x30C)
1694 #define SPR_MPC_MD_TWB        (0x30C)
1695 #define SPR_POWER_USIAR       (0X30C)
1696 #define SPR_PERFD             (0x30D)
1697 #define SPR_MPC_MD_TWC        (0x30D)
1698 #define SPR_POWER_USDAR       (0X30D)
1699 #define SPR_PERFE             (0x30E)
1700 #define SPR_MPC_MD_RPN        (0x30E)
1701 #define SPR_POWER_UMMCR1      (0X30E)
1702 #define SPR_PERFF             (0x30F)
1703 #define SPR_MPC_MD_TW         (0x30F)
1704 #define SPR_UPERF0            (0x310)
1705 #define SPR_POWER_SIER        (0x310)
1706 #define SPR_UPERF1            (0x311)
1707 #define SPR_POWER_MMCR2       (0x311)
1708 #define SPR_UPERF2            (0x312)
1709 #define SPR_POWER_MMCRA       (0X312)
1710 #define SPR_UPERF3            (0x313)
1711 #define SPR_POWER_PMC1        (0X313)
1712 #define SPR_UPERF4            (0x314)
1713 #define SPR_POWER_PMC2        (0X314)
1714 #define SPR_UPERF5            (0x315)
1715 #define SPR_POWER_PMC3        (0X315)
1716 #define SPR_UPERF6            (0x316)
1717 #define SPR_POWER_PMC4        (0X316)
1718 #define SPR_UPERF7            (0x317)
1719 #define SPR_POWER_PMC5        (0X317)
1720 #define SPR_UPERF8            (0x318)
1721 #define SPR_POWER_PMC6        (0X318)
1722 #define SPR_UPERF9            (0x319)
1723 #define SPR_970_PMC7          (0X319)
1724 #define SPR_UPERFA            (0x31A)
1725 #define SPR_970_PMC8          (0X31A)
1726 #define SPR_UPERFB            (0x31B)
1727 #define SPR_POWER_MMCR0       (0X31B)
1728 #define SPR_UPERFC            (0x31C)
1729 #define SPR_POWER_SIAR        (0X31C)
1730 #define SPR_UPERFD            (0x31D)
1731 #define SPR_POWER_SDAR        (0X31D)
1732 #define SPR_UPERFE            (0x31E)
1733 #define SPR_POWER_MMCR1       (0X31E)
1734 #define SPR_UPERFF            (0x31F)
1735 #define SPR_RCPU_MI_RA0       (0x320)
1736 #define SPR_MPC_MI_DBCAM      (0x320)
1737 #define SPR_BESCRS            (0x320)
1738 #define SPR_RCPU_MI_RA1       (0x321)
1739 #define SPR_MPC_MI_DBRAM0     (0x321)
1740 #define SPR_BESCRSU           (0x321)
1741 #define SPR_RCPU_MI_RA2       (0x322)
1742 #define SPR_MPC_MI_DBRAM1     (0x322)
1743 #define SPR_BESCRR            (0x322)
1744 #define SPR_RCPU_MI_RA3       (0x323)
1745 #define SPR_BESCRRU           (0x323)
1746 #define SPR_EBBHR             (0x324)
1747 #define SPR_EBBRR             (0x325)
1748 #define SPR_BESCR             (0x326)
1749 #define SPR_RCPU_L2U_RA0      (0x328)
1750 #define SPR_MPC_MD_DBCAM      (0x328)
1751 #define SPR_RCPU_L2U_RA1      (0x329)
1752 #define SPR_MPC_MD_DBRAM0     (0x329)
1753 #define SPR_RCPU_L2U_RA2      (0x32A)
1754 #define SPR_MPC_MD_DBRAM1     (0x32A)
1755 #define SPR_RCPU_L2U_RA3      (0x32B)
1756 #define SPR_TAR               (0x32F)
1757 #define SPR_IC                (0x350)
1758 #define SPR_VTB               (0x351)
1759 #define SPR_MMCRC             (0x353)
1760 #define SPR_440_INV0          (0x370)
1761 #define SPR_440_INV1          (0x371)
1762 #define SPR_440_INV2          (0x372)
1763 #define SPR_440_INV3          (0x373)
1764 #define SPR_440_ITV0          (0x374)
1765 #define SPR_440_ITV1          (0x375)
1766 #define SPR_440_ITV2          (0x376)
1767 #define SPR_440_ITV3          (0x377)
1768 #define SPR_440_CCR1          (0x378)
1769 #define SPR_TACR              (0x378)
1770 #define SPR_TCSCR             (0x379)
1771 #define SPR_CSIGR             (0x37a)
1772 #define SPR_DCRIPR            (0x37B)
1773 #define SPR_POWER_SPMC1       (0x37C)
1774 #define SPR_POWER_SPMC2       (0x37D)
1775 #define SPR_POWER_MMCRS       (0x37E)
1776 #define SPR_WORT              (0x37F)
1777 #define SPR_PPR               (0x380)
1778 #define SPR_750_GQR0          (0x390)
1779 #define SPR_440_DNV0          (0x390)
1780 #define SPR_750_GQR1          (0x391)
1781 #define SPR_440_DNV1          (0x391)
1782 #define SPR_750_GQR2          (0x392)
1783 #define SPR_440_DNV2          (0x392)
1784 #define SPR_750_GQR3          (0x393)
1785 #define SPR_440_DNV3          (0x393)
1786 #define SPR_750_GQR4          (0x394)
1787 #define SPR_440_DTV0          (0x394)
1788 #define SPR_750_GQR5          (0x395)
1789 #define SPR_440_DTV1          (0x395)
1790 #define SPR_750_GQR6          (0x396)
1791 #define SPR_440_DTV2          (0x396)
1792 #define SPR_750_GQR7          (0x397)
1793 #define SPR_440_DTV3          (0x397)
1794 #define SPR_750_THRM4         (0x398)
1795 #define SPR_750CL_HID2        (0x398)
1796 #define SPR_440_DVLIM         (0x398)
1797 #define SPR_750_WPAR          (0x399)
1798 #define SPR_440_IVLIM         (0x399)
1799 #define SPR_TSCR              (0x399)
1800 #define SPR_750_DMAU          (0x39A)
1801 #define SPR_750_DMAL          (0x39B)
1802 #define SPR_440_RSTCFG        (0x39B)
1803 #define SPR_BOOKE_DCDBTRL     (0x39C)
1804 #define SPR_BOOKE_DCDBTRH     (0x39D)
1805 #define SPR_BOOKE_ICDBTRL     (0x39E)
1806 #define SPR_BOOKE_ICDBTRH     (0x39F)
1807 #define SPR_74XX_UMMCR2       (0x3A0)
1808 #define SPR_7XX_UPMC5         (0x3A1)
1809 #define SPR_7XX_UPMC6         (0x3A2)
1810 #define SPR_UBAMR             (0x3A7)
1811 #define SPR_7XX_UMMCR0        (0x3A8)
1812 #define SPR_7XX_UPMC1         (0x3A9)
1813 #define SPR_7XX_UPMC2         (0x3AA)
1814 #define SPR_7XX_USIAR         (0x3AB)
1815 #define SPR_7XX_UMMCR1        (0x3AC)
1816 #define SPR_7XX_UPMC3         (0x3AD)
1817 #define SPR_7XX_UPMC4         (0x3AE)
1818 #define SPR_USDA              (0x3AF)
1819 #define SPR_40x_ZPR           (0x3B0)
1820 #define SPR_BOOKE_MAS7        (0x3B0)
1821 #define SPR_74XX_MMCR2        (0x3B0)
1822 #define SPR_7XX_PMC5          (0x3B1)
1823 #define SPR_40x_PID           (0x3B1)
1824 #define SPR_7XX_PMC6          (0x3B2)
1825 #define SPR_440_MMUCR         (0x3B2)
1826 #define SPR_4xx_CCR0          (0x3B3)
1827 #define SPR_BOOKE_EPLC        (0x3B3)
1828 #define SPR_405_IAC3          (0x3B4)
1829 #define SPR_BOOKE_EPSC        (0x3B4)
1830 #define SPR_405_IAC4          (0x3B5)
1831 #define SPR_405_DVC1          (0x3B6)
1832 #define SPR_405_DVC2          (0x3B7)
1833 #define SPR_BAMR              (0x3B7)
1834 #define SPR_7XX_MMCR0         (0x3B8)
1835 #define SPR_7XX_PMC1          (0x3B9)
1836 #define SPR_40x_SGR           (0x3B9)
1837 #define SPR_7XX_PMC2          (0x3BA)
1838 #define SPR_40x_DCWR          (0x3BA)
1839 #define SPR_7XX_SIAR          (0x3BB)
1840 #define SPR_405_SLER          (0x3BB)
1841 #define SPR_7XX_MMCR1         (0x3BC)
1842 #define SPR_405_SU0R          (0x3BC)
1843 #define SPR_401_SKR           (0x3BC)
1844 #define SPR_7XX_PMC3          (0x3BD)
1845 #define SPR_405_DBCR1         (0x3BD)
1846 #define SPR_7XX_PMC4          (0x3BE)
1847 #define SPR_SDA               (0x3BF)
1848 #define SPR_403_VTBL          (0x3CC)
1849 #define SPR_403_VTBU          (0x3CD)
1850 #define SPR_DMISS             (0x3D0)
1851 #define SPR_DCMP              (0x3D1)
1852 #define SPR_HASH1             (0x3D2)
1853 #define SPR_HASH2             (0x3D3)
1854 #define SPR_BOOKE_ICDBDR      (0x3D3)
1855 #define SPR_TLBMISS           (0x3D4)
1856 #define SPR_IMISS             (0x3D4)
1857 #define SPR_40x_ESR           (0x3D4)
1858 #define SPR_PTEHI             (0x3D5)
1859 #define SPR_ICMP              (0x3D5)
1860 #define SPR_40x_DEAR          (0x3D5)
1861 #define SPR_PTELO             (0x3D6)
1862 #define SPR_RPA               (0x3D6)
1863 #define SPR_40x_EVPR          (0x3D6)
1864 #define SPR_L3PM              (0x3D7)
1865 #define SPR_403_CDBCR         (0x3D7)
1866 #define SPR_L3ITCR0           (0x3D8)
1867 #define SPR_TCR               (0x3D8)
1868 #define SPR_40x_TSR           (0x3D8)
1869 #define SPR_IBR               (0x3DA)
1870 #define SPR_40x_TCR           (0x3DA)
1871 #define SPR_ESASRR            (0x3DB)
1872 #define SPR_40x_PIT           (0x3DB)
1873 #define SPR_403_TBL           (0x3DC)
1874 #define SPR_403_TBU           (0x3DD)
1875 #define SPR_SEBR              (0x3DE)
1876 #define SPR_40x_SRR2          (0x3DE)
1877 #define SPR_SER               (0x3DF)
1878 #define SPR_40x_SRR3          (0x3DF)
1879 #define SPR_L3OHCR            (0x3E8)
1880 #define SPR_L3ITCR1           (0x3E9)
1881 #define SPR_L3ITCR2           (0x3EA)
1882 #define SPR_L3ITCR3           (0x3EB)
1883 #define SPR_HID0              (0x3F0)
1884 #define SPR_40x_DBSR          (0x3F0)
1885 #define SPR_HID1              (0x3F1)
1886 #define SPR_IABR              (0x3F2)
1887 #define SPR_40x_DBCR0         (0x3F2)
1888 #define SPR_601_HID2          (0x3F2)
1889 #define SPR_Exxx_L1CSR0       (0x3F2)
1890 #define SPR_ICTRL             (0x3F3)
1891 #define SPR_HID2              (0x3F3)
1892 #define SPR_750CL_HID4        (0x3F3)
1893 #define SPR_Exxx_L1CSR1       (0x3F3)
1894 #define SPR_440_DBDR          (0x3F3)
1895 #define SPR_LDSTDB            (0x3F4)
1896 #define SPR_750_TDCL          (0x3F4)
1897 #define SPR_40x_IAC1          (0x3F4)
1898 #define SPR_MMUCSR0           (0x3F4)
1899 #define SPR_970_HID4          (0x3F4)
1900 #define SPR_DABR              (0x3F5)
1901 #define DABR_MASK (~(target_ulong)0x7)
1902 #define SPR_Exxx_BUCSR        (0x3F5)
1903 #define SPR_40x_IAC2          (0x3F5)
1904 #define SPR_601_HID5          (0x3F5)
1905 #define SPR_40x_DAC1          (0x3F6)
1906 #define SPR_MSSCR0            (0x3F6)
1907 #define SPR_970_HID5          (0x3F6)
1908 #define SPR_MSSSR0            (0x3F7)
1909 #define SPR_MSSCR1            (0x3F7)
1910 #define SPR_DABRX             (0x3F7)
1911 #define SPR_40x_DAC2          (0x3F7)
1912 #define SPR_MMUCFG            (0x3F7)
1913 #define SPR_LDSTCR            (0x3F8)
1914 #define SPR_L2PMCR            (0x3F8)
1915 #define SPR_750FX_HID2        (0x3F8)
1916 #define SPR_Exxx_L1FINV0      (0x3F8)
1917 #define SPR_L2CR              (0x3F9)
1918 #define SPR_L3CR              (0x3FA)
1919 #define SPR_750_TDCH          (0x3FA)
1920 #define SPR_IABR2             (0x3FA)
1921 #define SPR_40x_DCCR          (0x3FA)
1922 #define SPR_ICTC              (0x3FB)
1923 #define SPR_40x_ICCR          (0x3FB)
1924 #define SPR_THRM1             (0x3FC)
1925 #define SPR_403_PBL1          (0x3FC)
1926 #define SPR_SP                (0x3FD)
1927 #define SPR_THRM2             (0x3FD)
1928 #define SPR_403_PBU1          (0x3FD)
1929 #define SPR_604_HID13         (0x3FD)
1930 #define SPR_LT                (0x3FE)
1931 #define SPR_THRM3             (0x3FE)
1932 #define SPR_RCPU_FPECR        (0x3FE)
1933 #define SPR_403_PBL2          (0x3FE)
1934 #define SPR_PIR               (0x3FF)
1935 #define SPR_403_PBU2          (0x3FF)
1936 #define SPR_601_HID15         (0x3FF)
1937 #define SPR_604_HID15         (0x3FF)
1938 #define SPR_E500_SVR          (0x3FF)
1939 
1940 /* Disable MAS Interrupt Updates for Hypervisor */
1941 #define EPCR_DMIUH            (1 << 22)
1942 /* Disable Guest TLB Management Instructions */
1943 #define EPCR_DGTMI            (1 << 23)
1944 /* Guest Interrupt Computation Mode */
1945 #define EPCR_GICM             (1 << 24)
1946 /* Interrupt Computation Mode */
1947 #define EPCR_ICM              (1 << 25)
1948 /* Disable Embedded Hypervisor Debug */
1949 #define EPCR_DUVD             (1 << 26)
1950 /* Instruction Storage Interrupt Directed to Guest State */
1951 #define EPCR_ISIGS            (1 << 27)
1952 /* Data Storage Interrupt Directed to Guest State */
1953 #define EPCR_DSIGS            (1 << 28)
1954 /* Instruction TLB Error Interrupt Directed to Guest State */
1955 #define EPCR_ITLBGS           (1 << 29)
1956 /* Data TLB Error Interrupt Directed to Guest State */
1957 #define EPCR_DTLBGS           (1 << 30)
1958 /* External Input Interrupt Directed to Guest State */
1959 #define EPCR_EXTGS            (1 << 31)
1960 
1961 #define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
1962 #define   L1CSR0_CUL		0x00000400	/* (D-)Cache Unable to Lock */
1963 #define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
1964 #define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
1965 #define   L1CSR0_DCE		0x00000001	/* Data Cache Enable */
1966 
1967 #define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
1968 #define   L1CSR1_ICUL		0x00000400	/* I-Cache Unable to Lock */
1969 #define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
1970 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
1971 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
1972 
1973 /* HID0 bits */
1974 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1975 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1976 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
1977 #define HID0_HILE           (1ull << (63 - 19)) /* POWER8 */
1978 
1979 /*****************************************************************************/
1980 /* PowerPC Instructions types definitions                                    */
1981 enum {
1982     PPC_NONE           = 0x0000000000000000ULL,
1983     /* PowerPC base instructions set                                         */
1984     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1985     /*   integer operations instructions                                     */
1986 #define PPC_INTEGER PPC_INSNS_BASE
1987     /*   flow control instructions                                           */
1988 #define PPC_FLOW    PPC_INSNS_BASE
1989     /*   virtual memory instructions                                         */
1990 #define PPC_MEM     PPC_INSNS_BASE
1991     /*   ld/st with reservation instructions                                 */
1992 #define PPC_RES     PPC_INSNS_BASE
1993     /*   spr/msr access instructions                                         */
1994 #define PPC_MISC    PPC_INSNS_BASE
1995     /* Deprecated instruction sets                                           */
1996     /*   Original POWER instruction set                                      */
1997     PPC_POWER          = 0x0000000000000002ULL,
1998     /*   POWER2 instruction set extension                                    */
1999     PPC_POWER2         = 0x0000000000000004ULL,
2000     /*   Power RTC support                                                   */
2001     PPC_POWER_RTC      = 0x0000000000000008ULL,
2002     /*   Power-to-PowerPC bridge (601)                                       */
2003     PPC_POWER_BR       = 0x0000000000000010ULL,
2004     /* 64 bits PowerPC instruction set                                       */
2005     PPC_64B            = 0x0000000000000020ULL,
2006     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2007     PPC_64BX           = 0x0000000000000040ULL,
2008     /*   64 bits hypervisor extensions                                       */
2009     PPC_64H            = 0x0000000000000080ULL,
2010     /*   New wait instruction (PowerPC 2.0x)                                 */
2011     PPC_WAIT           = 0x0000000000000100ULL,
2012     /*   Time base mftb instruction                                          */
2013     PPC_MFTB           = 0x0000000000000200ULL,
2014 
2015     /* Fixed-point unit extensions                                           */
2016     /*   PowerPC 602 specific                                                */
2017     PPC_602_SPEC       = 0x0000000000000400ULL,
2018     /*   isel instruction                                                    */
2019     PPC_ISEL           = 0x0000000000000800ULL,
2020     /*   popcntb instruction                                                 */
2021     PPC_POPCNTB        = 0x0000000000001000ULL,
2022     /*   string load / store                                                 */
2023     PPC_STRING         = 0x0000000000002000ULL,
2024     /*   real mode cache inhibited load / store                              */
2025     PPC_CILDST         = 0x0000000000004000ULL,
2026 
2027     /* Floating-point unit extensions                                        */
2028     /*   Optional floating point instructions                                */
2029     PPC_FLOAT          = 0x0000000000010000ULL,
2030     /* New floating-point extensions (PowerPC 2.0x)                          */
2031     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2032     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2033     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2034     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2035     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2036     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2037     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2038 
2039     /* Vector/SIMD extensions                                                */
2040     /*   Altivec support                                                     */
2041     PPC_ALTIVEC        = 0x0000000001000000ULL,
2042     /*   PowerPC 2.03 SPE extension                                          */
2043     PPC_SPE            = 0x0000000002000000ULL,
2044     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2045     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2046     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2047     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2048 
2049     /* Optional memory control instructions                                  */
2050     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2051     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2052     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2053     /*   sync instruction                                                    */
2054     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2055     /*   eieio instruction                                                   */
2056     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2057 
2058     /* Cache control instructions                                            */
2059     PPC_CACHE          = 0x0000000200000000ULL,
2060     /*   icbi instruction                                                    */
2061     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2062     /*   dcbz instruction                                                    */
2063     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2064     /*   dcba instruction                                                    */
2065     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2066     /*   Freescale cache locking instructions                                */
2067     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2068 
2069     /* MMU related extensions                                                */
2070     /*   external control instructions                                       */
2071     PPC_EXTERN         = 0x0000010000000000ULL,
2072     /*   segment register access instructions                                */
2073     PPC_SEGMENT        = 0x0000020000000000ULL,
2074     /*   PowerPC 6xx TLB management instructions                             */
2075     PPC_6xx_TLB        = 0x0000040000000000ULL,
2076     /* PowerPC 74xx TLB management instructions                              */
2077     PPC_74xx_TLB       = 0x0000080000000000ULL,
2078     /*   PowerPC 40x TLB management instructions                             */
2079     PPC_40x_TLB        = 0x0000100000000000ULL,
2080     /*   segment register access instructions for PowerPC 64 "bridge"        */
2081     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2082     /*   SLB management                                                      */
2083     PPC_SLBI           = 0x0000400000000000ULL,
2084 
2085     /* Embedded PowerPC dedicated instructions                               */
2086     PPC_WRTEE          = 0x0001000000000000ULL,
2087     /* PowerPC 40x exception model                                           */
2088     PPC_40x_EXCP       = 0x0002000000000000ULL,
2089     /* PowerPC 405 Mac instructions                                          */
2090     PPC_405_MAC        = 0x0004000000000000ULL,
2091     /* PowerPC 440 specific instructions                                     */
2092     PPC_440_SPEC       = 0x0008000000000000ULL,
2093     /* BookE (embedded) PowerPC specification                                */
2094     PPC_BOOKE          = 0x0010000000000000ULL,
2095     /* mfapidi instruction                                                   */
2096     PPC_MFAPIDI        = 0x0020000000000000ULL,
2097     /* tlbiva instruction                                                    */
2098     PPC_TLBIVA         = 0x0040000000000000ULL,
2099     /* tlbivax instruction                                                   */
2100     PPC_TLBIVAX        = 0x0080000000000000ULL,
2101     /* PowerPC 4xx dedicated instructions                                    */
2102     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2103     /* PowerPC 40x ibct instructions                                         */
2104     PPC_40x_ICBT       = 0x0200000000000000ULL,
2105     /* rfmci is not implemented in all BookE PowerPC                         */
2106     PPC_RFMCI          = 0x0400000000000000ULL,
2107     /* rfdi instruction                                                      */
2108     PPC_RFDI           = 0x0800000000000000ULL,
2109     /* DCR accesses                                                          */
2110     PPC_DCR            = 0x1000000000000000ULL,
2111     /* DCR extended accesse                                                  */
2112     PPC_DCRX           = 0x2000000000000000ULL,
2113     /* user-mode DCR access, implemented in PowerPC 460                      */
2114     PPC_DCRUX          = 0x4000000000000000ULL,
2115     /* popcntw and popcntd instructions                                      */
2116     PPC_POPCNTWD       = 0x8000000000000000ULL,
2117 
2118 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2119                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2120                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2121                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2122                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2123                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2124                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2125                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2126                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2127                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2128                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2129                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2130                         | PPC_CACHE | PPC_CACHE_ICBI \
2131                         | PPC_CACHE_DCBZ \
2132                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2133                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2134                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2135                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2136                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2137                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2138                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2139                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2140                         | PPC_POPCNTWD | PPC_CILDST)
2141 
2142     /* extended type values */
2143 
2144     /* BookE 2.06 PowerPC specification                                      */
2145     PPC2_BOOKE206      = 0x0000000000000001ULL,
2146     /* VSX (extensions to Altivec / VMX)                                     */
2147     PPC2_VSX           = 0x0000000000000002ULL,
2148     /* Decimal Floating Point (DFP)                                          */
2149     PPC2_DFP           = 0x0000000000000004ULL,
2150     /* Embedded.Processor Control                                            */
2151     PPC2_PRCNTL        = 0x0000000000000008ULL,
2152     /* Byte-reversed, indexed, double-word load and store                    */
2153     PPC2_DBRX          = 0x0000000000000010ULL,
2154     /* Book I 2.05 PowerPC specification                                     */
2155     PPC2_ISA205        = 0x0000000000000020ULL,
2156     /* VSX additions in ISA 2.07                                             */
2157     PPC2_VSX207        = 0x0000000000000040ULL,
2158     /* ISA 2.06B bpermd                                                      */
2159     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2160     /* ISA 2.06B divide extended variants                                    */
2161     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2162     /* ISA 2.06B larx/stcx. instructions                                     */
2163     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2164     /* ISA 2.06B floating point integer conversion                           */
2165     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2166     /* ISA 2.06B floating point test instructions                            */
2167     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2168     /* ISA 2.07 bctar instruction                                            */
2169     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2170     /* ISA 2.07 load/store quadword                                          */
2171     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2172     /* ISA 2.07 Altivec                                                      */
2173     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2174     /* PowerISA 2.07 Book3s specification                                    */
2175     PPC2_ISA207S       = 0x0000000000008000ULL,
2176     /* Double precision floating point conversion for signed integer 64      */
2177     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2178     /* Transactional Memory (ISA 2.07, Book II)                              */
2179     PPC2_TM            = 0x0000000000020000ULL,
2180     /* Server PM instructgions (ISA 2.06, Book III)                          */
2181     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2182     /* POWER ISA 3.0                                                         */
2183     PPC2_ISA300        = 0x0000000000080000ULL,
2184 
2185 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2186                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2187                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2188                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2189                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2190                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2191                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2192                         PPC2_ISA300)
2193 };
2194 
2195 /*****************************************************************************/
2196 /* Memory access type :
2197  * may be needed for precise access rights control and precise exceptions.
2198  */
2199 enum {
2200     /* 1 bit to define user level / supervisor access */
2201     ACCESS_USER  = 0x00,
2202     ACCESS_SUPER = 0x01,
2203     /* Type of instruction that generated the access */
2204     ACCESS_CODE  = 0x10, /* Code fetch access                */
2205     ACCESS_INT   = 0x20, /* Integer load/store access        */
2206     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2207     ACCESS_RES   = 0x40, /* load/store with reservation      */
2208     ACCESS_EXT   = 0x50, /* external access                  */
2209     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2210 };
2211 
2212 /* Hardware interruption sources:
2213  * all those exception can be raised simulteaneously
2214  */
2215 /* Input pins definitions */
2216 enum {
2217     /* 6xx bus input pins */
2218     PPC6xx_INPUT_HRESET     = 0,
2219     PPC6xx_INPUT_SRESET     = 1,
2220     PPC6xx_INPUT_CKSTP_IN   = 2,
2221     PPC6xx_INPUT_MCP        = 3,
2222     PPC6xx_INPUT_SMI        = 4,
2223     PPC6xx_INPUT_INT        = 5,
2224     PPC6xx_INPUT_TBEN       = 6,
2225     PPC6xx_INPUT_WAKEUP     = 7,
2226     PPC6xx_INPUT_NB,
2227 };
2228 
2229 enum {
2230     /* Embedded PowerPC input pins */
2231     PPCBookE_INPUT_HRESET     = 0,
2232     PPCBookE_INPUT_SRESET     = 1,
2233     PPCBookE_INPUT_CKSTP_IN   = 2,
2234     PPCBookE_INPUT_MCP        = 3,
2235     PPCBookE_INPUT_SMI        = 4,
2236     PPCBookE_INPUT_INT        = 5,
2237     PPCBookE_INPUT_CINT       = 6,
2238     PPCBookE_INPUT_NB,
2239 };
2240 
2241 enum {
2242     /* PowerPC E500 input pins */
2243     PPCE500_INPUT_RESET_CORE = 0,
2244     PPCE500_INPUT_MCK        = 1,
2245     PPCE500_INPUT_CINT       = 3,
2246     PPCE500_INPUT_INT        = 4,
2247     PPCE500_INPUT_DEBUG      = 6,
2248     PPCE500_INPUT_NB,
2249 };
2250 
2251 enum {
2252     /* PowerPC 40x input pins */
2253     PPC40x_INPUT_RESET_CORE = 0,
2254     PPC40x_INPUT_RESET_CHIP = 1,
2255     PPC40x_INPUT_RESET_SYS  = 2,
2256     PPC40x_INPUT_CINT       = 3,
2257     PPC40x_INPUT_INT        = 4,
2258     PPC40x_INPUT_HALT       = 5,
2259     PPC40x_INPUT_DEBUG      = 6,
2260     PPC40x_INPUT_NB,
2261 };
2262 
2263 enum {
2264     /* RCPU input pins */
2265     PPCRCPU_INPUT_PORESET   = 0,
2266     PPCRCPU_INPUT_HRESET    = 1,
2267     PPCRCPU_INPUT_SRESET    = 2,
2268     PPCRCPU_INPUT_IRQ0      = 3,
2269     PPCRCPU_INPUT_IRQ1      = 4,
2270     PPCRCPU_INPUT_IRQ2      = 5,
2271     PPCRCPU_INPUT_IRQ3      = 6,
2272     PPCRCPU_INPUT_IRQ4      = 7,
2273     PPCRCPU_INPUT_IRQ5      = 8,
2274     PPCRCPU_INPUT_IRQ6      = 9,
2275     PPCRCPU_INPUT_IRQ7      = 10,
2276     PPCRCPU_INPUT_NB,
2277 };
2278 
2279 #if defined(TARGET_PPC64)
2280 enum {
2281     /* PowerPC 970 input pins */
2282     PPC970_INPUT_HRESET     = 0,
2283     PPC970_INPUT_SRESET     = 1,
2284     PPC970_INPUT_CKSTP      = 2,
2285     PPC970_INPUT_TBEN       = 3,
2286     PPC970_INPUT_MCP        = 4,
2287     PPC970_INPUT_INT        = 5,
2288     PPC970_INPUT_THINT      = 6,
2289     PPC970_INPUT_NB,
2290 };
2291 
2292 enum {
2293     /* POWER7 input pins */
2294     POWER7_INPUT_INT        = 0,
2295     /* POWER7 probably has other inputs, but we don't care about them
2296      * for any existing machine.  We can wire these up when we need
2297      * them */
2298     POWER7_INPUT_NB,
2299 };
2300 #endif
2301 
2302 /* Hardware exceptions definitions */
2303 enum {
2304     /* External hardware exception sources */
2305     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2306     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2307     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2308     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2309     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2310     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2311     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2312     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2313     /* Internal hardware exception sources */
2314     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2315     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2316     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2317     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2318     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2319     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2320     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2321     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2322     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2323     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2324 };
2325 
2326 /* Processor Compatibility mask (PCR) */
2327 enum {
2328     PCR_COMPAT_2_05     = 1ull << (63-62),
2329     PCR_COMPAT_2_06     = 1ull << (63-61),
2330     PCR_COMPAT_2_07     = 1ull << (63-60),
2331     PCR_COMPAT_3_00     = 1ull << (63-59),
2332     PCR_VEC_DIS         = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2333     PCR_VSX_DIS         = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2334     PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2335 };
2336 
2337 /* HMER/HMEER */
2338 enum {
2339     HMER_MALFUNCTION_ALERT      = 1ull << (63 - 0),
2340     HMER_PROC_RECV_DONE         = 1ull << (63 - 2),
2341     HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2342     HMER_TFAC_ERROR             = 1ull << (63 - 4),
2343     HMER_TFMR_PARITY_ERROR      = 1ull << (63 - 5),
2344     HMER_XSCOM_FAIL             = 1ull << (63 - 8),
2345     HMER_XSCOM_DONE             = 1ull << (63 - 9),
2346     HMER_PROC_RECV_AGAIN        = 1ull << (63 - 11),
2347     HMER_WARN_RISE              = 1ull << (63 - 14),
2348     HMER_WARN_FALL              = 1ull << (63 - 15),
2349     HMER_SCOM_FIR_HMI           = 1ull << (63 - 16),
2350     HMER_TRIG_FIR_HMI           = 1ull << (63 - 17),
2351     HMER_HYP_RESOURCE_ERR       = 1ull << (63 - 20),
2352     HMER_XSCOM_STATUS_MASK      = 7ull << (63 - 23),
2353     HMER_XSCOM_STATUS_LSH       = (63 - 23),
2354 };
2355 
2356 /* Alternate Interrupt Location (AIL) */
2357 enum {
2358     AIL_NONE                = 0,
2359     AIL_RESERVED            = 1,
2360     AIL_0001_8000           = 2,
2361     AIL_C000_0000_0000_4000 = 3,
2362 };
2363 
2364 /*****************************************************************************/
2365 
2366 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2367 target_ulong cpu_read_xer(CPUPPCState *env);
2368 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2369 
2370 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2371                                         target_ulong *cs_base, uint32_t *flags)
2372 {
2373     *pc = env->nip;
2374     *cs_base = 0;
2375     *flags = env->hflags;
2376 }
2377 
2378 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2379 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2380                                       uintptr_t raddr);
2381 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2382                                        uint32_t error_code);
2383 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2384                                           uint32_t error_code, uintptr_t raddr);
2385 
2386 #if !defined(CONFIG_USER_ONLY)
2387 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2388 {
2389     uintptr_t tlbml = (uintptr_t)tlbm;
2390     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2391 
2392     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2393 }
2394 
2395 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2396 {
2397     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2398     int r = tlbncfg & TLBnCFG_N_ENTRY;
2399     return r;
2400 }
2401 
2402 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2403 {
2404     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2405     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2406     return r;
2407 }
2408 
2409 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2410 {
2411     int id = booke206_tlbm_id(env, tlbm);
2412     int end = 0;
2413     int i;
2414 
2415     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2416         end += booke206_tlb_size(env, i);
2417         if (id < end) {
2418             return i;
2419         }
2420     }
2421 
2422     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2423     return 0;
2424 }
2425 
2426 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2427 {
2428     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2429     int tlbid = booke206_tlbm_id(env, tlb);
2430     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2431 }
2432 
2433 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2434                                               target_ulong ea, int way)
2435 {
2436     int r;
2437     uint32_t ways = booke206_tlb_ways(env, tlbn);
2438     int ways_bits = ctz32(ways);
2439     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2440     int i;
2441 
2442     way &= ways - 1;
2443     ea >>= MAS2_EPN_SHIFT;
2444     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2445     r = (ea << ways_bits) | way;
2446 
2447     if (r >= booke206_tlb_size(env, tlbn)) {
2448         return NULL;
2449     }
2450 
2451     /* bump up to tlbn index */
2452     for (i = 0; i < tlbn; i++) {
2453         r += booke206_tlb_size(env, i);
2454     }
2455 
2456     return &env->tlb.tlbm[r];
2457 }
2458 
2459 /* returns bitmap of supported page sizes for a given TLB */
2460 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2461 {
2462     bool mav2 = false;
2463     uint32_t ret = 0;
2464 
2465     if (mav2) {
2466         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2467     } else {
2468         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2469         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2470         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2471         int i;
2472         for (i = min; i <= max; i++) {
2473             ret |= (1 << (i << 1));
2474         }
2475     }
2476 
2477     return ret;
2478 }
2479 
2480 #endif
2481 
2482 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2483 {
2484     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2485         return msr & (1ULL << MSR_CM);
2486     }
2487 
2488     return msr & (1ULL << MSR_SF);
2489 }
2490 
2491 /**
2492  * Check whether register rx is in the range between start and
2493  * start + nregs (as needed by the LSWX and LSWI instructions)
2494  */
2495 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2496 {
2497     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2498            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2499 }
2500 
2501 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2502 
2503 /**
2504  * ppc_get_vcpu_dt_id:
2505  * @cs: a PowerPCCPU struct.
2506  *
2507  * Returns a device-tree ID for a CPU.
2508  */
2509 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2510 
2511 /**
2512  * ppc_get_vcpu_by_dt_id:
2513  * @cpu_dt_id: a device tree id
2514  *
2515  * Searches for a CPU by @cpu_dt_id.
2516  *
2517  * Returns: a PowerPCCPU struct
2518  */
2519 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2520 
2521 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2522 #endif /* PPC_CPU_H */
2523