xref: /openbmc/qemu/target/ppc/cpu.h (revision 2b74dd91)
1 /*
2  *  PowerPC emulation cpu definitions for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22 
23 #include "qemu/int128.h"
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
27 #include "qom/object.h"
28 #include "hw/registerfields.h"
29 
30 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
31 
32 #define TARGET_PAGE_BITS_64K 16
33 #define TARGET_PAGE_BITS_16M 24
34 
35 #if defined(TARGET_PPC64)
36 #define PPC_ELF_MACHINE     EM_PPC64
37 #else
38 #define PPC_ELF_MACHINE     EM_PPC
39 #endif
40 
41 #define PPC_BIT_NR(bit)         (63 - (bit))
42 #define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
43 #define PPC_BIT32(bit)          (0x80000000 >> (bit))
44 #define PPC_BIT8(bit)           (0x80 >> (bit))
45 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
46 #define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
47                                  PPC_BIT32(bs))
48 #define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
49 
50 /*
51  * QEMU version of the GETFIELD/SETFIELD macros from skiboot
52  *
53  * It might be better to use the existing extract64() and
54  * deposit64() but this means that all the register definitions will
55  * change and become incompatible with the ones found in skiboot.
56  */
57 #define MASK_TO_LSH(m)          (__builtin_ffsll(m) - 1)
58 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
59 #define SETFIELD(m, v, val) \
60         (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
61 
62 /*****************************************************************************/
63 /* Exception vectors definitions                                             */
64 enum {
65     POWERPC_EXCP_NONE    = -1,
66     /* The 64 first entries are used by the PowerPC embedded specification   */
67     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
68     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
69     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
70     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
71     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
72     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
73     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
74     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
75     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
76     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
77     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
78     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
79     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
80     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
81     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
82     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
83     /* Vectors 16 to 31 are reserved                                         */
84     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
85     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
86     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
87     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
88     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
89     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
90     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
91     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
92     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
93     /* Vectors 42 to 63 are reserved                                         */
94     /* Exceptions defined in the PowerPC server specification                */
95     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
96     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
97     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
98     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
99     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
100     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
101     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
102     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
103     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
104     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
105     /* 40x specific exceptions                                               */
106     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
107     /* Vectors 75-76 are 601 specific exceptions                             */
108     /* 602 specific exceptions                                               */
109     POWERPC_EXCP_EMUL      = 77, /* Emulation trap exception                 */
110     /* 602/603 specific exceptions                                           */
111     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
112     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
113     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
114     /* Exceptions available on most PowerPC                                  */
115     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
116     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
117     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
118     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
119     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
120     /* 7xx/74xx specific exceptions                                          */
121     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
122     /* 74xx specific exceptions                                              */
123     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
124     /* 970FX specific exceptions                                             */
125     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
126     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
127     /* Freescale embedded cores specific exceptions                          */
128     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
129     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
130     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
131     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
132     /* VSX Unavailable (Power ISA 2.06 and later)                            */
133     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
134     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
135     /* Additional ISA 2.06 and later server exceptions                       */
136     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
137     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
138     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
139     /* Server doorbell variants */
140     POWERPC_EXCP_SDOOR    = 99,
141     POWERPC_EXCP_SDOOR_HV = 100,
142     /* ISA 3.00 additions */
143     POWERPC_EXCP_HVIRT    = 101,
144     POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
145     POWERPC_EXCP_PERFM_EBB = 103,    /* Performance Monitor EBB Exception    */
146     POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception               */
147     /* EOL                                                                   */
148     POWERPC_EXCP_NB       = 105,
149     /* QEMU exceptions: special cases we want to stop translation            */
150     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
151 };
152 
153 /* Exceptions error codes                                                    */
154 enum {
155     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
156     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
157     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
158     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
159     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
160     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
161     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
162     POWERPC_EXCP_ALIGN_INSN    = 0x07,  /* Pref. insn x-ing 64-byte boundary */
163     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
164     /* FP exceptions                                                         */
165     POWERPC_EXCP_FP            = 0x10,
166     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
167     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
168     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
169     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
170     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
171     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
172     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
173     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
174     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
175     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
176     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
177     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
178     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
179     /* Invalid instruction                                                   */
180     POWERPC_EXCP_INVAL         = 0x20,
181     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
182     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
183     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
184     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
185     /* Privileged instruction                                                */
186     POWERPC_EXCP_PRIV          = 0x30,
187     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
188     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
189     /* Trap                                                                  */
190     POWERPC_EXCP_TRAP          = 0x40,
191 };
192 
193 /* Exception model                                                           */
194 typedef enum powerpc_excp_t {
195     POWERPC_EXCP_UNKNOWN   = 0,
196     /* Standard PowerPC exception model */
197     POWERPC_EXCP_STD,
198     /* PowerPC 40x exception model      */
199     POWERPC_EXCP_40x,
200     /* PowerPC 603/604/G2 exception model */
201     POWERPC_EXCP_6xx,
202     /* PowerPC 7xx exception model      */
203     POWERPC_EXCP_7xx,
204     /* PowerPC 74xx exception model     */
205     POWERPC_EXCP_74xx,
206     /* BookE exception model            */
207     POWERPC_EXCP_BOOKE,
208     /* PowerPC 970 exception model      */
209     POWERPC_EXCP_970,
210     /* POWER7 exception model           */
211     POWERPC_EXCP_POWER7,
212     /* POWER8 exception model           */
213     POWERPC_EXCP_POWER8,
214     /* POWER9 exception model           */
215     POWERPC_EXCP_POWER9,
216     /* POWER10 exception model           */
217     POWERPC_EXCP_POWER10,
218 } powerpc_excp_t;
219 
220 /*****************************************************************************/
221 /* MMU model                                                                 */
222 typedef enum powerpc_mmu_t {
223     POWERPC_MMU_UNKNOWN    = 0x00000000,
224     /* Standard 32 bits PowerPC MMU                            */
225     POWERPC_MMU_32B        = 0x00000001,
226     /* PowerPC 6xx MMU with software TLB                       */
227     POWERPC_MMU_SOFT_6xx   = 0x00000002,
228     /*
229      * PowerPC 74xx MMU with software TLB (this has been
230      * disabled, see git history for more information.
231      * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
232      */
233     POWERPC_MMU_SOFT_74xx  = 0x00000003,
234     /* PowerPC 4xx MMU with software TLB                       */
235     POWERPC_MMU_SOFT_4xx   = 0x00000004,
236     /* PowerPC MMU in real mode only                           */
237     POWERPC_MMU_REAL       = 0x00000006,
238     /* Freescale MPC8xx MMU model                              */
239     POWERPC_MMU_MPC8xx     = 0x00000007,
240     /* BookE MMU model                                         */
241     POWERPC_MMU_BOOKE      = 0x00000008,
242     /* BookE 2.06 MMU model                                    */
243     POWERPC_MMU_BOOKE206   = 0x00000009,
244 #define POWERPC_MMU_64       0x00010000
245     /* 64 bits PowerPC MMU                                     */
246     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
247     /* Architecture 2.03 and later (has LPCR) */
248     POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,
249     /* Architecture 2.06 variant                               */
250     POWERPC_MMU_2_06       = POWERPC_MMU_64 | 0x00000003,
251     /* Architecture 2.07 variant                               */
252     POWERPC_MMU_2_07       = POWERPC_MMU_64 | 0x00000004,
253     /* Architecture 3.00 variant                               */
254     POWERPC_MMU_3_00       = POWERPC_MMU_64 | 0x00000005,
255 } powerpc_mmu_t;
256 
257 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
258 {
259     return mmu_model & POWERPC_MMU_64;
260 }
261 
262 /*****************************************************************************/
263 /* Input pins model                                                          */
264 typedef enum powerpc_input_t {
265     PPC_FLAGS_INPUT_UNKNOWN = 0,
266     /* PowerPC 6xx bus                  */
267     PPC_FLAGS_INPUT_6xx,
268     /* BookE bus                        */
269     PPC_FLAGS_INPUT_BookE,
270     /* PowerPC 405 bus                  */
271     PPC_FLAGS_INPUT_405,
272     /* PowerPC 970 bus                  */
273     PPC_FLAGS_INPUT_970,
274     /* PowerPC POWER7 bus               */
275     PPC_FLAGS_INPUT_POWER7,
276     /* PowerPC POWER9 bus               */
277     PPC_FLAGS_INPUT_POWER9,
278     /* Freescale RCPU bus               */
279     PPC_FLAGS_INPUT_RCPU,
280 } powerpc_input_t;
281 
282 #define PPC_INPUT(env) ((env)->bus_model)
283 
284 /*****************************************************************************/
285 typedef struct opc_handler_t opc_handler_t;
286 
287 /*****************************************************************************/
288 /* Types used to describe some PowerPC registers etc. */
289 typedef struct DisasContext DisasContext;
290 typedef struct ppc_dcr_t ppc_dcr_t;
291 typedef struct ppc_spr_t ppc_spr_t;
292 typedef struct ppc_tb_t ppc_tb_t;
293 typedef union ppc_tlb_t ppc_tlb_t;
294 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
295 typedef struct PPCHash64Options PPCHash64Options;
296 
297 typedef struct CPUArchState CPUPPCState;
298 
299 /* SPR access micro-ops generations callbacks */
300 struct ppc_spr_t {
301     const char *name;
302     target_ulong default_value;
303 #ifndef CONFIG_USER_ONLY
304     unsigned int gdb_id;
305 #endif
306 #ifdef CONFIG_TCG
307     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
308     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
309 # ifndef CONFIG_USER_ONLY
310     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
311     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
312     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
313     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
314 # endif
315 #endif
316 #ifdef CONFIG_KVM
317     /*
318      * We (ab)use the fact that all the SPRs will have ids for the
319      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
320      * don't sync this
321      */
322     uint64_t one_reg_id;
323 #endif
324 };
325 
326 /* VSX/Altivec registers (128 bits) */
327 typedef union _ppc_vsr_t {
328     uint8_t u8[16];
329     uint16_t u16[8];
330     uint32_t u32[4];
331     uint64_t u64[2];
332     int8_t s8[16];
333     int16_t s16[8];
334     int32_t s32[4];
335     int64_t s64[2];
336     float16 f16[8];
337     float32 f32[4];
338     float64 f64[2];
339     float128 f128;
340 #ifdef CONFIG_INT128
341     __uint128_t u128;
342 #endif
343     Int128 s128;
344 } ppc_vsr_t;
345 
346 typedef ppc_vsr_t ppc_avr_t;
347 typedef ppc_vsr_t ppc_fprp_t;
348 typedef ppc_vsr_t ppc_acc_t;
349 
350 #if !defined(CONFIG_USER_ONLY)
351 /* Software TLB cache */
352 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
353 struct ppc6xx_tlb_t {
354     target_ulong pte0;
355     target_ulong pte1;
356     target_ulong EPN;
357 };
358 
359 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
360 struct ppcemb_tlb_t {
361     uint64_t RPN;
362     target_ulong EPN;
363     target_ulong PID;
364     target_ulong size;
365     uint32_t prot;
366     uint32_t attr; /* Storage attributes */
367 };
368 
369 typedef struct ppcmas_tlb_t {
370      uint32_t mas8;
371      uint32_t mas1;
372      uint64_t mas2;
373      uint64_t mas7_3;
374 } ppcmas_tlb_t;
375 
376 union ppc_tlb_t {
377     ppc6xx_tlb_t *tlb6;
378     ppcemb_tlb_t *tlbe;
379     ppcmas_tlb_t *tlbm;
380 };
381 
382 /* possible TLB variants */
383 #define TLB_NONE               0
384 #define TLB_6XX                1
385 #define TLB_EMB                2
386 #define TLB_MAS                3
387 #endif
388 
389 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
390 
391 typedef struct ppc_slb_t ppc_slb_t;
392 struct ppc_slb_t {
393     uint64_t esid;
394     uint64_t vsid;
395     const PPCHash64SegmentPageSizes *sps;
396 };
397 
398 #define MAX_SLB_ENTRIES         64
399 #define SEGMENT_SHIFT_256M      28
400 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
401 
402 #define SEGMENT_SHIFT_1T        40
403 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
404 
405 typedef struct ppc_v3_pate_t {
406     uint64_t dw0;
407     uint64_t dw1;
408 } ppc_v3_pate_t;
409 
410 /* PMU related structs and defines */
411 #define PMU_COUNTERS_NUM 6
412 typedef enum {
413     PMU_EVENT_INVALID = 0,
414     PMU_EVENT_INACTIVE,
415     PMU_EVENT_CYCLES,
416     PMU_EVENT_INSTRUCTIONS,
417     PMU_EVENT_INSN_RUN_LATCH,
418 } PMUEventType;
419 
420 /*****************************************************************************/
421 /* Machine state register bits definition                                    */
422 #define MSR_SF   PPC_BIT_NR(0)  /* Sixty-four-bit mode                hflags */
423 #define MSR_TAG  PPC_BIT_NR(1)  /* Tag-active mode (POWERx ?)                */
424 #define MSR_ISF  PPC_BIT_NR(2)  /* Sixty-four-bit interrupt mode on 630      */
425 #define MSR_HV   PPC_BIT_NR(3)  /* hypervisor state                   hflags */
426 #define MSR_TS0  PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s)      */
427 #define MSR_TS1  PPC_BIT_NR(30)
428 #define MSR_TM   PPC_BIT_NR(31) /* Transactional Memory Available (Book3s)   */
429 #define MSR_CM   PPC_BIT_NR(32) /* Computation mode for BookE         hflags */
430 #define MSR_ICM  PPC_BIT_NR(33) /* Interrupt computation mode for BookE      */
431 #define MSR_GS   PPC_BIT_NR(35) /* guest state for BookE                     */
432 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE     */
433 #define MSR_VR   PPC_BIT_NR(38) /* altivec available                x hflags */
434 #define MSR_SPE  PPC_BIT_NR(38) /* SPE enable for BookE             x hflags */
435 #define MSR_VSX  PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
436 #define MSR_S    PPC_BIT_NR(41) /* Secure state                              */
437 #define MSR_KEY  PPC_BIT_NR(44) /* key bit on 603e                           */
438 #define MSR_POW  PPC_BIT_NR(45) /* Power management                          */
439 #define MSR_WE   PPC_BIT_NR(45) /* Wait State Enable on 405                  */
440 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603            x        */
441 #define MSR_CE   PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x    */
442 #define MSR_ILE  PPC_BIT_NR(47) /* Interrupt little-endian mode              */
443 #define MSR_EE   PPC_BIT_NR(48) /* External interrupt enable                 */
444 #define MSR_PR   PPC_BIT_NR(49) /* Problem state                      hflags */
445 #define MSR_FP   PPC_BIT_NR(50) /* Floating point available           hflags */
446 #define MSR_ME   PPC_BIT_NR(51) /* Machine check interrupt enable            */
447 #define MSR_FE0  PPC_BIT_NR(52) /* Floating point exception mode 0           */
448 #define MSR_SE   PPC_BIT_NR(53) /* Single-step trace enable         x hflags */
449 #define MSR_DWE  PPC_BIT_NR(53) /* Debug wait enable on 405         x        */
450 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500     x        */
451 #define MSR_BE   PPC_BIT_NR(54) /* Branch trace enable              x hflags */
452 #define MSR_DE   PPC_BIT_NR(54) /* Debug int. enable on embedded PPC   x     */
453 #define MSR_FE1  PPC_BIT_NR(55) /* Floating point exception mode 1           */
454 #define MSR_AL   PPC_BIT_NR(56) /* AL bit on POWER                           */
455 #define MSR_EP   PPC_BIT_NR(57) /* Exception prefix on 601                   */
456 #define MSR_IR   PPC_BIT_NR(58) /* Instruction relocate                      */
457 #define MSR_IS   PPC_BIT_NR(58) /* Instruction address space (BookE)         */
458 #define MSR_DR   PPC_BIT_NR(59) /* Data relocate                             */
459 #define MSR_DS   PPC_BIT_NR(59) /* Data address space (BookE)                */
460 #define MSR_PE   PPC_BIT_NR(60) /* Protection enable on 403                  */
461 #define MSR_PX   PPC_BIT_NR(61) /* Protection exclusive on 403        x      */
462 #define MSR_PMM  PPC_BIT_NR(61) /* Performance monitor mark on POWER  x      */
463 #define MSR_RI   PPC_BIT_NR(62) /* Recoverable interrupt            1        */
464 #define MSR_LE   PPC_BIT_NR(63) /* Little-endian mode               1 hflags */
465 
466 FIELD(MSR, SF, MSR_SF, 1)
467 FIELD(MSR, TAG, MSR_TAG, 1)
468 FIELD(MSR, ISF, MSR_ISF, 1)
469 #if defined(TARGET_PPC64)
470 FIELD(MSR, HV, MSR_HV, 1)
471 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
472 #else
473 #define FIELD_EX64_HV(storage) 0
474 #endif
475 FIELD(MSR, TS0, MSR_TS0, 1)
476 FIELD(MSR, TS1, MSR_TS1, 1)
477 FIELD(MSR, TS, MSR_TS0, 2)
478 FIELD(MSR, TM, MSR_TM, 1)
479 FIELD(MSR, CM, MSR_CM, 1)
480 FIELD(MSR, ICM, MSR_ICM, 1)
481 FIELD(MSR, GS, MSR_GS, 1)
482 FIELD(MSR, UCLE, MSR_UCLE, 1)
483 FIELD(MSR, VR, MSR_VR, 1)
484 FIELD(MSR, SPE, MSR_SPE, 1)
485 FIELD(MSR, VSX, MSR_VSX, 1)
486 FIELD(MSR, S, MSR_S, 1)
487 FIELD(MSR, KEY, MSR_KEY, 1)
488 FIELD(MSR, POW, MSR_POW, 1)
489 FIELD(MSR, WE, MSR_WE, 1)
490 FIELD(MSR, TGPR, MSR_TGPR, 1)
491 FIELD(MSR, CE, MSR_CE, 1)
492 FIELD(MSR, ILE, MSR_ILE, 1)
493 FIELD(MSR, EE, MSR_EE, 1)
494 FIELD(MSR, PR, MSR_PR, 1)
495 FIELD(MSR, FP, MSR_FP, 1)
496 FIELD(MSR, ME, MSR_ME, 1)
497 FIELD(MSR, FE0, MSR_FE0, 1)
498 FIELD(MSR, SE, MSR_SE, 1)
499 FIELD(MSR, DWE, MSR_DWE, 1)
500 FIELD(MSR, UBLE, MSR_UBLE, 1)
501 FIELD(MSR, BE, MSR_BE, 1)
502 FIELD(MSR, DE, MSR_DE, 1)
503 FIELD(MSR, FE1, MSR_FE1, 1)
504 FIELD(MSR, AL, MSR_AL, 1)
505 FIELD(MSR, EP, MSR_EP, 1)
506 FIELD(MSR, IR, MSR_IR, 1)
507 FIELD(MSR, DR, MSR_DR, 1)
508 FIELD(MSR, IS, MSR_IS, 1)
509 FIELD(MSR, DS, MSR_DS, 1)
510 FIELD(MSR, PE, MSR_PE, 1)
511 FIELD(MSR, PX, MSR_PX, 1)
512 FIELD(MSR, PMM, MSR_PMM, 1)
513 FIELD(MSR, RI, MSR_RI, 1)
514 FIELD(MSR, LE, MSR_LE, 1)
515 
516 /*
517  * FE0 and FE1 bits are not side-by-side
518  * so we can't combine them using FIELD()
519  */
520 #define FIELD_EX64_FE(msr) \
521     ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
522 
523 /* PMU bits */
524 #define MMCR0_FC     PPC_BIT(32)         /* Freeze Counters  */
525 #define MMCR0_PMAO   PPC_BIT(56)         /* Perf Monitor Alert Occurred */
526 #define MMCR0_PMAE   PPC_BIT(37)         /* Perf Monitor Alert Enable */
527 #define MMCR0_EBE    PPC_BIT(43)         /* Perf Monitor EBB Enable */
528 #define MMCR0_FCECE  PPC_BIT(38)         /* FC on Enabled Cond or Event */
529 #define MMCR0_PMCC0  PPC_BIT(44)         /* PMC Control bit 0 */
530 #define MMCR0_PMCC1  PPC_BIT(45)         /* PMC Control bit 1 */
531 #define MMCR0_PMCC   PPC_BITMASK(44, 45) /* PMC Control */
532 #define MMCR0_FC14   PPC_BIT(58)         /* PMC Freeze Counters 1-4 bit */
533 #define MMCR0_FC56   PPC_BIT(59)         /* PMC Freeze Counters 5-6 bit */
534 #define MMCR0_PMC1CE PPC_BIT(48)         /* MMCR0 PMC1 Condition Enabled */
535 #define MMCR0_PMCjCE PPC_BIT(49)         /* MMCR0 PMCj Condition Enabled */
536 #define MMCR0_FCP    PPC_BIT(34)         /* Freeze Counters/BHRB if PR=1 */
537 #define MMCR0_FCPC   PPC_BIT(51)         /* Condition for FCP bit */
538 #define MMCR0_BHRBA_NR PPC_BIT_NR(42)    /* BHRB Available */
539 /* MMCR0 userspace r/w mask */
540 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
541 /* MMCR2 userspace r/w mask */
542 #define MMCR2_FC1P0  PPC_BIT(1)          /* MMCR2 FCnP0 for PMC1 */
543 #define MMCR2_FC2P0  PPC_BIT(10)         /* MMCR2 FCnP0 for PMC2 */
544 #define MMCR2_FC3P0  PPC_BIT(19)         /* MMCR2 FCnP0 for PMC3 */
545 #define MMCR2_FC4P0  PPC_BIT(28)         /* MMCR2 FCnP0 for PMC4 */
546 #define MMCR2_FC5P0  PPC_BIT(37)         /* MMCR2 FCnP0 for PMC5 */
547 #define MMCR2_FC6P0  PPC_BIT(46)         /* MMCR2 FCnP0 for PMC6 */
548 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
549                          MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
550 
551 #define MMCRA_BHRBRD    PPC_BIT(26)         /* BHRB Recording Disable */
552 #define MMCRA_IFM_MASK  PPC_BITMASK(32, 33) /* BHRB Instruction Filtering */
553 #define MMCRA_IFM_SHIFT PPC_BIT_NR(33)
554 
555 #define MMCR1_EVT_SIZE 8
556 /* extract64() does a right shift before extracting */
557 #define MMCR1_PMC1SEL_START 32
558 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
559 #define MMCR1_PMC2SEL_START 40
560 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
561 #define MMCR1_PMC3SEL_START 48
562 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
563 #define MMCR1_PMC4SEL_START 56
564 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
565 
566 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
567 #define CTRL_RUN PPC_BIT(63)
568 
569 /* EBB/BESCR bits */
570 /* Global Enable */
571 #define BESCR_GE PPC_BIT(0)
572 /* External Event-based Exception Enable */
573 #define BESCR_EE PPC_BIT(30)
574 /* Performance Monitor Event-based Exception Enable */
575 #define BESCR_PME PPC_BIT(31)
576 /* External Event-based Exception Occurred */
577 #define BESCR_EEO PPC_BIT(62)
578 /* Performance Monitor Event-based Exception Occurred */
579 #define BESCR_PMEO PPC_BIT(63)
580 #define BESCR_INVALID PPC_BITMASK(32, 33)
581 
582 /* LPCR bits */
583 #define LPCR_VPM0         PPC_BIT(0)
584 #define LPCR_VPM1         PPC_BIT(1)
585 #define LPCR_ISL          PPC_BIT(2)
586 #define LPCR_KBV          PPC_BIT(3)
587 #define LPCR_DPFD_SHIFT   (63 - 11)
588 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
589 #define LPCR_VRMASD_SHIFT (63 - 16)
590 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
591 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
592 #define LPCR_PECE_U_SHIFT (63 - 19)
593 #define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
594 #define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
595 #define LPCR_RMLS_SHIFT   (63 - 37)   /* RMLS (removed in ISA v3.0) */
596 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
597 #define LPCR_HAIL         PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
598 #define LPCR_ILE          PPC_BIT(38)
599 #define LPCR_AIL_SHIFT    (63 - 40)   /* Alternate interrupt location */
600 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
601 #define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
602 #define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
603 #define LPCR_HR           PPC_BIT(43) /* Host Radix */
604 #define LPCR_ONL          PPC_BIT(45)
605 #define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
606 #define LPCR_P7_PECE0     PPC_BIT(49)
607 #define LPCR_P7_PECE1     PPC_BIT(50)
608 #define LPCR_P7_PECE2     PPC_BIT(51)
609 #define LPCR_P8_PECE0     PPC_BIT(47)
610 #define LPCR_P8_PECE1     PPC_BIT(48)
611 #define LPCR_P8_PECE2     PPC_BIT(49)
612 #define LPCR_P8_PECE3     PPC_BIT(50)
613 #define LPCR_P8_PECE4     PPC_BIT(51)
614 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
615 #define LPCR_PECE_L_SHIFT (63 - 51)
616 #define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
617 #define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
618 #define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
619 #define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
620 #define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
621 #define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
622 #define LPCR_MER          PPC_BIT(52)
623 #define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
624 #define LPCR_TC           PPC_BIT(54)
625 #define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
626 #define LPCR_LPES0        PPC_BIT(60)
627 #define LPCR_LPES1        PPC_BIT(61)
628 #define LPCR_RMI          PPC_BIT(62)
629 #define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
630 #define LPCR_HDICE        PPC_BIT(63)
631 
632 /* PSSCR bits */
633 #define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
634 #define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
635 
636 /* HFSCR bits */
637 #define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
638 #define HFSCR_BHRB     PPC_BIT(59) /* BHRB Instructions */
639 #define HFSCR_IC_MSGP  0xA
640 
641 #define DBCR0_ICMP (1 << 27)
642 #define DBCR0_BRT (1 << 26)
643 #define DBSR_ICMP (1 << 27)
644 #define DBSR_BRT (1 << 26)
645 
646 /* Hypervisor bit is more specific */
647 #if defined(TARGET_PPC64)
648 #define MSR_HVB (1ULL << MSR_HV)
649 #else
650 #define MSR_HVB (0ULL)
651 #endif
652 
653 /* DSISR */
654 #define DSISR_NOPTE              0x40000000
655 /* Not permitted by access authority of encoded access authority */
656 #define DSISR_PROTFAULT          0x08000000
657 #define DSISR_ISSTORE            0x02000000
658 /* Not permitted by virtual page class key protection */
659 #define DSISR_AMR                0x00200000
660 /* Unsupported Radix Tree Configuration */
661 #define DSISR_R_BADCONFIG        0x00080000
662 #define DSISR_ATOMIC_RC          0x00040000
663 /* Unable to translate address of (guest) pde or process/page table entry */
664 #define DSISR_PRTABLE_FAULT      0x00020000
665 
666 /* SRR1 error code fields */
667 
668 #define SRR1_NOPTE               DSISR_NOPTE
669 /* Not permitted due to no-execute or guard bit set */
670 #define SRR1_NOEXEC_GUARD        0x10000000
671 #define SRR1_PROTFAULT           DSISR_PROTFAULT
672 #define SRR1_IAMR                DSISR_AMR
673 
674 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
675 
676 #define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
677 
678 #define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
679 #define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
680 #define SRR1_WAKEEE             0x00200000 /* External interrupt */
681 #define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
682 #define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
683 #define SRR1_WAKERESET          0x00100000 /* System reset */
684 #define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
685 #define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
686 
687 /* SRR1[46:47] power-saving exit mode */
688 
689 #define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
690 
691 #define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
692 #define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
693 #define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
694 
695 /* Facility Status and Control (FSCR) bits */
696 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
697 #define FSCR_TAR        (63 - 55) /* Target Address Register */
698 #define FSCR_SCV        (63 - 51) /* System call vectored */
699 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
700 #define FSCR_IC_MASK    (0xFFULL)
701 #define FSCR_IC_POS     (63 - 7)
702 #define FSCR_IC_DSCR_SPR3   2
703 #define FSCR_IC_PMU         3
704 #define FSCR_IC_BHRB        4
705 #define FSCR_IC_TM          5
706 #define FSCR_IC_EBB         7
707 #define FSCR_IC_TAR         8
708 #define FSCR_IC_SCV        12
709 
710 /* Exception state register bits definition                                  */
711 #define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
712 #define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
713 #define ESR_PTR   PPC_BIT(38) /* Trap                                   */
714 #define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
715 #define ESR_ST    PPC_BIT(40) /* Store Operation                        */
716 #define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
717 #define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
718 #define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
719 #define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
720 #define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
721 #define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
722 #define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
723 #define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
724 #define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
725 #define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
726 #define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
727 
728 /* Transaction EXception And Summary Register bits                           */
729 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
730 #define TEXASR_DISALLOWED                        (63 - 8)
731 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
732 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
733 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
734 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
735 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
736 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
737 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
738 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
739 #define TEXASR_ABORT                             (63 - 31)
740 #define TEXASR_SUSPENDED                         (63 - 32)
741 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
742 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
743 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
744 #define TEXASR_TFIAR_EXACT                       (63 - 37)
745 #define TEXASR_ROT                               (63 - 38)
746 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
747 
748 enum {
749     POWERPC_FLAG_NONE     = 0x00000000,
750     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
751     POWERPC_FLAG_SPE      = 0x00000001,
752     POWERPC_FLAG_VRE      = 0x00000002,
753     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
754     POWERPC_FLAG_TGPR     = 0x00000004,
755     POWERPC_FLAG_CE       = 0x00000008,
756     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
757     POWERPC_FLAG_SE       = 0x00000010,
758     POWERPC_FLAG_DWE      = 0x00000020,
759     POWERPC_FLAG_UBLE     = 0x00000040,
760     /* Flag for MSR bit 9 signification (BE/DE)                              */
761     POWERPC_FLAG_BE       = 0x00000080,
762     POWERPC_FLAG_DE       = 0x00000100,
763     /* Flag for MSR bit 2 signification (PX/PMM)                             */
764     POWERPC_FLAG_PX       = 0x00000200,
765     POWERPC_FLAG_PMM      = 0x00000400,
766     /* Flag for special features                                             */
767     /* Decrementer clock                                                     */
768     POWERPC_FLAG_BUS_CLK  = 0x00020000,
769     /* Has CFAR                                                              */
770     POWERPC_FLAG_CFAR     = 0x00040000,
771     /* Has VSX                                                               */
772     POWERPC_FLAG_VSX      = 0x00080000,
773     /* Has Transaction Memory (ISA 2.07)                                     */
774     POWERPC_FLAG_TM       = 0x00100000,
775     /* Has SCV (ISA 3.00)                                                    */
776     POWERPC_FLAG_SCV      = 0x00200000,
777     /* Has >1 thread per core                                                */
778     POWERPC_FLAG_SMT      = 0x00400000,
779     /* Using "LPAR per core" mode  (as opposed to per-thread)                */
780     POWERPC_FLAG_SMT_1LPAR = 0x00800000,
781     /* Has BHRB */
782     POWERPC_FLAG_BHRB      = 0x01000000,
783 };
784 
785 /*
786  * Bits for env->hflags.
787  *
788  * Most of these bits overlap with corresponding bits in MSR,
789  * but some come from other sources.  Those that do come from
790  * the MSR are validated in hreg_compute_hflags.
791  */
792 enum {
793     HFLAGS_LE = 0,   /* MSR_LE */
794     HFLAGS_HV = 1,   /* computed from MSR_HV and other state */
795     HFLAGS_64 = 2,   /* computed from MSR_CE and MSR_SF */
796     HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
797     HFLAGS_DR = 4,   /* MSR_DR */
798     HFLAGS_HR = 5,   /* computed from SPR_LPCR[HR] */
799     HFLAGS_SPE = 6,  /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
800     HFLAGS_TM = 8,   /* computed from MSR_TM */
801     HFLAGS_BE = 9,   /* MSR_BE -- from elsewhere on embedded ppc */
802     HFLAGS_SE = 10,  /* MSR_SE -- from elsewhere on embedded ppc */
803     HFLAGS_FP = 13,  /* MSR_FP */
804     HFLAGS_PR = 14,  /* MSR_PR */
805     HFLAGS_PMCC0 = 15,  /* MMCR0 PMCC bit 0 */
806     HFLAGS_PMCC1 = 16,  /* MMCR0 PMCC bit 1 */
807     HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
808     HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
809     HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
810     HFLAGS_BHRB_ENABLE = 20, /* Summary flag for enabling BHRB */
811     HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
812     HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
813 
814     HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
815     HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
816 };
817 
818 /*****************************************************************************/
819 /* Floating point status and control register                                */
820 #define FPSCR_DRN2   PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
821 #define FPSCR_DRN1   PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
822 #define FPSCR_DRN0   PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
823 #define FPSCR_FX     PPC_BIT_NR(32) /* Floating-point exception summary      */
824 #define FPSCR_FEX    PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
825 #define FPSCR_VX     PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
826 #define FPSCR_OX     PPC_BIT_NR(35) /* Floating-point overflow exception     */
827 #define FPSCR_UX     PPC_BIT_NR(36) /* Floating-point underflow exception    */
828 #define FPSCR_ZX     PPC_BIT_NR(37) /* Floating-point zero divide exception  */
829 #define FPSCR_XX     PPC_BIT_NR(38) /* Floating-point inexact exception      */
830 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
831 #define FPSCR_VXISI  PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
832 #define FPSCR_VXIDI  PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
833 #define FPSCR_VXZDZ  PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
834 #define FPSCR_VXIMZ  PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
835 #define FPSCR_VXVC   PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
836 #define FPSCR_FR     PPC_BIT_NR(45) /* Floating-point fraction rounded       */
837 #define FPSCR_FI     PPC_BIT_NR(46) /* Floating-point fraction inexact       */
838 #define FPSCR_C      PPC_BIT_NR(47) /* Floating-point result class descriptor*/
839 #define FPSCR_FL     PPC_BIT_NR(48) /* Floating-point less than or negative  */
840 #define FPSCR_FG     PPC_BIT_NR(49) /* Floating-point greater than or neg.   */
841 #define FPSCR_FE     PPC_BIT_NR(50) /* Floating-point equal or zero          */
842 #define FPSCR_FU     PPC_BIT_NR(51) /* Floating-point unordered or NaN       */
843 #define FPSCR_FPCC   PPC_BIT_NR(51) /* Floating-point condition code         */
844 #define FPSCR_FPRF   PPC_BIT_NR(51) /* Floating-point result flags           */
845 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
846 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
847 #define FPSCR_VXCVI  PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
848 #define FPSCR_VE     PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
849 #define FPSCR_OE     PPC_BIT_NR(57) /* Floating-point overflow excp. enable  */
850 #define FPSCR_UE     PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
851 #define FPSCR_ZE     PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
852 #define FPSCR_XE     PPC_BIT_NR(60) /* Floating-point inexact excp. enable   */
853 #define FPSCR_NI     PPC_BIT_NR(61) /* Floating-point non-IEEE mode          */
854 #define FPSCR_RN1    PPC_BIT_NR(62)
855 #define FPSCR_RN0    PPC_BIT_NR(63) /* Floating-point rounding control       */
856 /* Invalid operation exception summary */
857 #define FPSCR_IX     ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
858                       (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
859                       (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
860                       (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
861                       (1 << FPSCR_VXCVI))
862 
863 FIELD(FPSCR, FI, FPSCR_FI, 1)
864 
865 #define FP_DRN2         (1ull << FPSCR_DRN2)
866 #define FP_DRN1         (1ull << FPSCR_DRN1)
867 #define FP_DRN0         (1ull << FPSCR_DRN0)
868 #define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
869 #define FP_FX           (1ull << FPSCR_FX)
870 #define FP_FEX          (1ull << FPSCR_FEX)
871 #define FP_VX           (1ull << FPSCR_VX)
872 #define FP_OX           (1ull << FPSCR_OX)
873 #define FP_UX           (1ull << FPSCR_UX)
874 #define FP_ZX           (1ull << FPSCR_ZX)
875 #define FP_XX           (1ull << FPSCR_XX)
876 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
877 #define FP_VXISI        (1ull << FPSCR_VXISI)
878 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
879 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
880 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
881 #define FP_VXVC         (1ull << FPSCR_VXVC)
882 #define FP_FR           (1ull << FPSCR_FR)
883 #define FP_FI           (1ull << FPSCR_FI)
884 #define FP_C            (1ull << FPSCR_C)
885 #define FP_FL           (1ull << FPSCR_FL)
886 #define FP_FG           (1ull << FPSCR_FG)
887 #define FP_FE           (1ull << FPSCR_FE)
888 #define FP_FU           (1ull << FPSCR_FU)
889 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
890 #define FP_FPRF         (FP_C | FP_FPCC)
891 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
892 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
893 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
894 #define FP_VE           (1ull << FPSCR_VE)
895 #define FP_OE           (1ull << FPSCR_OE)
896 #define FP_UE           (1ull << FPSCR_UE)
897 #define FP_ZE           (1ull << FPSCR_ZE)
898 #define FP_XE           (1ull << FPSCR_XE)
899 #define FP_NI           (1ull << FPSCR_NI)
900 #define FP_RN1          (1ull << FPSCR_RN1)
901 #define FP_RN0          (1ull << FPSCR_RN0)
902 #define FP_RN           (FP_RN1 | FP_RN0)
903 
904 #define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
905 #define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
906 
907 /* the exception bits which can be cleared by mcrfs - includes FX */
908 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
909                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
910                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
911                           FP_VXSQRT | FP_VXCVI)
912 
913 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
914 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) |        \
915                            FP_FEX | FP_VX | PPC_BIT(52)))
916 
917 /*****************************************************************************/
918 /* Vector status and control register */
919 #define VSCR_NJ         16 /* Vector non-java */
920 #define VSCR_SAT        0 /* Vector saturation */
921 
922 /*****************************************************************************/
923 /* BookE e500 MMU registers */
924 
925 #define MAS0_NV_SHIFT      0
926 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
927 
928 #define MAS0_WQ_SHIFT      12
929 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
930 /* Write TLB entry regardless of reservation */
931 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
932 /* Write TLB entry only already in use */
933 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
934 /* Clear TLB entry */
935 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
936 
937 #define MAS0_HES_SHIFT     14
938 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
939 
940 #define MAS0_ESEL_SHIFT    16
941 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
942 
943 #define MAS0_TLBSEL_SHIFT  28
944 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
945 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
946 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
947 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
948 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
949 
950 #define MAS0_ATSEL_SHIFT   31
951 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
952 #define MAS0_ATSEL_TLB     0
953 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
954 
955 #define MAS1_TSIZE_SHIFT   7
956 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
957 
958 #define MAS1_TS_SHIFT      12
959 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
960 
961 #define MAS1_IND_SHIFT     13
962 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
963 
964 #define MAS1_TID_SHIFT     16
965 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
966 
967 #define MAS1_IPROT_SHIFT   30
968 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
969 
970 #define MAS1_VALID_SHIFT   31
971 #define MAS1_VALID         0x80000000
972 
973 #define MAS2_EPN_SHIFT     12
974 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
975 
976 #define MAS2_ACM_SHIFT     6
977 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
978 
979 #define MAS2_VLE_SHIFT     5
980 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
981 
982 #define MAS2_W_SHIFT       4
983 #define MAS2_W             (1 << MAS2_W_SHIFT)
984 
985 #define MAS2_I_SHIFT       3
986 #define MAS2_I             (1 << MAS2_I_SHIFT)
987 
988 #define MAS2_M_SHIFT       2
989 #define MAS2_M             (1 << MAS2_M_SHIFT)
990 
991 #define MAS2_G_SHIFT       1
992 #define MAS2_G             (1 << MAS2_G_SHIFT)
993 
994 #define MAS2_E_SHIFT       0
995 #define MAS2_E             (1 << MAS2_E_SHIFT)
996 
997 #define MAS3_RPN_SHIFT     12
998 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
999 
1000 #define MAS3_U0                 0x00000200
1001 #define MAS3_U1                 0x00000100
1002 #define MAS3_U2                 0x00000080
1003 #define MAS3_U3                 0x00000040
1004 #define MAS3_UX                 0x00000020
1005 #define MAS3_SX                 0x00000010
1006 #define MAS3_UW                 0x00000008
1007 #define MAS3_SW                 0x00000004
1008 #define MAS3_UR                 0x00000002
1009 #define MAS3_SR                 0x00000001
1010 #define MAS3_SPSIZE_SHIFT       1
1011 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
1012 
1013 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
1014 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
1015 #define MAS4_TIDSELD_MASK       0x00030000
1016 #define MAS4_TIDSELD_PID0       0x00000000
1017 #define MAS4_TIDSELD_PID1       0x00010000
1018 #define MAS4_TIDSELD_PID2       0x00020000
1019 #define MAS4_TIDSELD_PIDZ       0x00030000
1020 #define MAS4_INDD               0x00008000      /* Default IND */
1021 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
1022 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
1023 #define MAS4_ACMD               0x00000040
1024 #define MAS4_VLED               0x00000020
1025 #define MAS4_WD                 0x00000010
1026 #define MAS4_ID                 0x00000008
1027 #define MAS4_MD                 0x00000004
1028 #define MAS4_GD                 0x00000002
1029 #define MAS4_ED                 0x00000001
1030 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
1031 #define MAS4_WIMGED_SHIFT       0
1032 
1033 #define MAS5_SGS                0x80000000
1034 #define MAS5_SLPID_MASK         0x00000fff
1035 
1036 #define MAS6_SPID0              0x3fff0000
1037 #define MAS6_SPID1              0x00007ffe
1038 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
1039 #define MAS6_SAS                0x00000001
1040 #define MAS6_SPID               MAS6_SPID0
1041 #define MAS6_SIND               0x00000002      /* Indirect page */
1042 #define MAS6_SIND_SHIFT         1
1043 #define MAS6_SPID_MASK          0x3fff0000
1044 #define MAS6_SPID_SHIFT         16
1045 #define MAS6_ISIZE_MASK         0x00000f80
1046 #define MAS6_ISIZE_SHIFT        7
1047 
1048 #define MAS7_RPN                0xffffffff
1049 
1050 #define MAS8_TGS                0x80000000
1051 #define MAS8_VF                 0x40000000
1052 #define MAS8_TLBPID             0x00000fff
1053 
1054 /* Bit definitions for MMUCFG */
1055 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
1056 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
1057 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
1058 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
1059 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
1060 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
1061 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
1062 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
1063 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
1064 
1065 /* Bit definitions for MMUCSR0 */
1066 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
1067 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
1068 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
1069 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
1070 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
1071                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
1072 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
1073 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
1074 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
1075 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
1076 
1077 /* TLBnCFG encoding */
1078 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
1079 #define TLBnCFG_HES             0x00002000      /* HW select supported */
1080 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
1081 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
1082 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
1083 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
1084 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
1085 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
1086 #define TLBnCFG_MINSIZE_SHIFT   20
1087 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
1088 #define TLBnCFG_MAXSIZE_SHIFT   16
1089 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
1090 #define TLBnCFG_ASSOC_SHIFT     24
1091 
1092 /* TLBnPS encoding */
1093 #define TLBnPS_4K               0x00000004
1094 #define TLBnPS_8K               0x00000008
1095 #define TLBnPS_16K              0x00000010
1096 #define TLBnPS_32K              0x00000020
1097 #define TLBnPS_64K              0x00000040
1098 #define TLBnPS_128K             0x00000080
1099 #define TLBnPS_256K             0x00000100
1100 #define TLBnPS_512K             0x00000200
1101 #define TLBnPS_1M               0x00000400
1102 #define TLBnPS_2M               0x00000800
1103 #define TLBnPS_4M               0x00001000
1104 #define TLBnPS_8M               0x00002000
1105 #define TLBnPS_16M              0x00004000
1106 #define TLBnPS_32M              0x00008000
1107 #define TLBnPS_64M              0x00010000
1108 #define TLBnPS_128M             0x00020000
1109 #define TLBnPS_256M             0x00040000
1110 #define TLBnPS_512M             0x00080000
1111 #define TLBnPS_1G               0x00100000
1112 #define TLBnPS_2G               0x00200000
1113 #define TLBnPS_4G               0x00400000
1114 #define TLBnPS_8G               0x00800000
1115 #define TLBnPS_16G              0x01000000
1116 #define TLBnPS_32G              0x02000000
1117 #define TLBnPS_64G              0x04000000
1118 #define TLBnPS_128G             0x08000000
1119 #define TLBnPS_256G             0x10000000
1120 
1121 /* tlbilx action encoding */
1122 #define TLBILX_T_ALL                    0
1123 #define TLBILX_T_TID                    1
1124 #define TLBILX_T_FULLMATCH              3
1125 #define TLBILX_T_CLASS0                 4
1126 #define TLBILX_T_CLASS1                 5
1127 #define TLBILX_T_CLASS2                 6
1128 #define TLBILX_T_CLASS3                 7
1129 
1130 /* BookE 2.06 helper defines */
1131 
1132 #define BOOKE206_FLUSH_TLB0    (1 << 0)
1133 #define BOOKE206_FLUSH_TLB1    (1 << 1)
1134 #define BOOKE206_FLUSH_TLB2    (1 << 2)
1135 #define BOOKE206_FLUSH_TLB3    (1 << 3)
1136 
1137 /* number of possible TLBs */
1138 #define BOOKE206_MAX_TLBN      4
1139 
1140 #define EPID_EPID_SHIFT 0x0
1141 #define EPID_EPID 0xFF
1142 #define EPID_ELPID_SHIFT 0x10
1143 #define EPID_ELPID 0x3F0000
1144 #define EPID_EGS 0x20000000
1145 #define EPID_EGS_SHIFT 29
1146 #define EPID_EAS 0x40000000
1147 #define EPID_EAS_SHIFT 30
1148 #define EPID_EPR 0x80000000
1149 #define EPID_EPR_SHIFT 31
1150 /* We don't support EGS and ELPID */
1151 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1152 
1153 /*****************************************************************************/
1154 /* Server and Embedded Processor Control */
1155 
1156 #define DBELL_TYPE_SHIFT               27
1157 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
1158 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
1159 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
1160 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
1161 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
1162 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
1163 
1164 #define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
1165 
1166 #define DBELL_BRDCAST_MASK             PPC_BITMASK(37, 38)
1167 #define DBELL_BRDCAST_SHIFT            25
1168 #define DBELL_BRDCAST_SUBPROC          (0x1 << DBELL_BRDCAST_SHIFT)
1169 #define DBELL_BRDCAST_CORE             (0x2 << DBELL_BRDCAST_SHIFT)
1170 
1171 #define DBELL_LPIDTAG_SHIFT            14
1172 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
1173 #define DBELL_PIRTAG_MASK              0x3fff
1174 
1175 #define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
1176 
1177 #define PPC_PAGE_SIZES_MAX_SZ   8
1178 
1179 struct ppc_radix_page_info {
1180     uint32_t count;
1181     uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1182 };
1183 
1184 /*****************************************************************************/
1185 /* Dynamic Execution Control Register */
1186 
1187 #define DEXCR_ASPECT(name, num)                    \
1188 FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1)       \
1189 FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1)  \
1190 FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1)      \
1191 FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1192 
1193 DEXCR_ASPECT(SBHE, 0)
1194 DEXCR_ASPECT(IBRTPD, 1)
1195 DEXCR_ASPECT(SRAPD, 4)
1196 DEXCR_ASPECT(NPHIE, 5)
1197 DEXCR_ASPECT(PHIE, 6)
1198 
1199 /*****************************************************************************/
1200 /* The whole PowerPC CPU context */
1201 
1202 /*
1203  * PowerPC needs eight modes for different hypervisor/supervisor/guest
1204  * + real/paged mode combinations. The other two modes are for
1205  * external PID load/store.
1206  */
1207 #define PPC_TLB_EPID_LOAD 8
1208 #define PPC_TLB_EPID_STORE 9
1209 
1210 #define PPC_CPU_OPCODES_LEN          0x40
1211 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1212 
1213 #define BHRB_MAX_NUM_ENTRIES_LOG2 (5)
1214 #define BHRB_MAX_NUM_ENTRIES      (1 << BHRB_MAX_NUM_ENTRIES_LOG2)
1215 
1216 struct CPUArchState {
1217     /* Most commonly used resources during translated code execution first */
1218     target_ulong gpr[32];  /* general purpose registers */
1219     target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1220     target_ulong lr;
1221     target_ulong ctr;
1222     uint32_t crf[8];       /* condition register */
1223 #if defined(TARGET_PPC64)
1224     target_ulong cfar;
1225 #endif
1226     target_ulong xer;      /* XER (with SO, OV, CA split out) */
1227     target_ulong so;
1228     target_ulong ov;
1229     target_ulong ca;
1230     target_ulong ov32;
1231     target_ulong ca32;
1232 
1233     target_ulong reserve_addr;   /* Reservation address */
1234     target_ulong reserve_length; /* Reservation larx op size (bytes) */
1235     target_ulong reserve_val;    /* Reservation value */
1236 #if defined(TARGET_PPC64)
1237     target_ulong reserve_val2;
1238 #endif
1239 
1240     /* These are used in supervisor mode only */
1241     target_ulong msr;      /* machine state register */
1242     target_ulong tgpr[4];  /* temporary general purpose registers, */
1243                            /* used to speed-up TLB assist handlers */
1244 
1245     target_ulong nip;      /* next instruction pointer */
1246 
1247     /* when a memory exception occurs, the access type is stored here */
1248     int access_type;
1249 
1250     /* For SMT processors */
1251     bool has_smt_siblings;
1252     int core_index;
1253 
1254 #if !defined(CONFIG_USER_ONLY)
1255     /* MMU context, only relevant for full system emulation */
1256 #if defined(TARGET_PPC64)
1257     ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1258     struct CPUBreakpoint *ciabr_breakpoint;
1259     struct CPUWatchpoint *dawr0_watchpoint;
1260 #endif
1261     target_ulong sr[32];   /* segment registers */
1262     uint32_t nb_BATs;      /* number of BATs */
1263     target_ulong DBAT[2][8];
1264     target_ulong IBAT[2][8];
1265     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1266     int32_t nb_tlb;  /* Total number of TLB */
1267     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1268     int nb_ways;     /* Number of ways in the TLB set */
1269     int last_way;    /* Last used way used to allocate TLB in a LRU way */
1270     int nb_pids;     /* Number of available PID registers */
1271     int tlb_type;    /* Type of TLB we're dealing with */
1272     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1273 #ifdef CONFIG_KVM
1274     bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1275     bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1276 #endif /* CONFIG_KVM */
1277     uint32_t tlb_need_flush; /* Delayed flush needed */
1278 #define TLB_NEED_LOCAL_FLUSH   0x1
1279 #define TLB_NEED_GLOBAL_FLUSH  0x2
1280 #endif
1281 
1282     /* Other registers */
1283     target_ulong spr[1024]; /* special purpose registers */
1284     ppc_spr_t spr_cb[1024];
1285     /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1286     uint8_t pmc_ins_cnt;
1287     uint8_t pmc_cyc_cnt;
1288     /* Vector status and control register, minus VSCR_SAT */
1289     uint32_t vscr;
1290     /* VSX registers (including FP and AVR) */
1291     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1292     /* Non-zero if and only if VSCR_SAT should be set */
1293     ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1294     /* SPE registers */
1295     uint64_t spe_acc;
1296     uint32_t spe_fscr;
1297     /* SPE and Altivec share status as they'll never be used simultaneously */
1298     float_status vec_status;
1299     float_status fp_status; /* Floating point execution context */
1300     target_ulong fpscr;     /* Floating point status and control register */
1301 
1302     /* Internal devices resources */
1303     ppc_tb_t *tb_env;      /* Time base and decrementer */
1304     ppc_dcr_t *dcr_env;    /* Device control registers */
1305 
1306     int dcache_line_size;
1307     int icache_line_size;
1308 
1309 #ifdef TARGET_PPC64
1310     /* Branch History Rolling Buffer (BHRB) resources */
1311     target_ulong bhrb_num_entries;
1312     intptr_t     bhrb_base;
1313     target_ulong bhrb_filter;
1314     target_ulong bhrb_offset;
1315     target_ulong bhrb_offset_mask;
1316     uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
1317 #endif
1318 
1319     /* These resources are used during exception processing */
1320     /* CPU model definition */
1321     target_ulong msr_mask;
1322     powerpc_mmu_t mmu_model;
1323     powerpc_excp_t excp_model;
1324     powerpc_input_t bus_model;
1325     int bfd_mach;
1326     uint32_t flags;
1327     uint64_t insns_flags;
1328     uint64_t insns_flags2;
1329 
1330     int error_code;
1331     uint32_t pending_interrupts;
1332 #if !defined(CONFIG_USER_ONLY)
1333     uint64_t excp_stats[POWERPC_EXCP_NB];
1334     /*
1335      * This is the IRQ controller, which is implementation dependent and only
1336      * relevant when emulating a complete machine. Note that this isn't used
1337      * by recent Book3s compatible CPUs (POWER7 and newer).
1338      */
1339     uint32_t irq_input_state;
1340 
1341     target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1342     target_ulong excp_prefix;
1343     target_ulong ivor_mask;
1344     target_ulong ivpr_mask;
1345     target_ulong hreset_vector;
1346     hwaddr mpic_iack;
1347     bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1348     bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1349                       /* instructions and SPRs are diallowed if MSR:HV is 0 */
1350     /*
1351      * On P7/P8/P9, set when in PM state so we need to handle resume in a
1352      * special way (such as routing some resume causes to 0x100, i.e. sreset).
1353      */
1354     bool resume_as_sreset;
1355 #endif
1356 
1357     /* These resources are used only in TCG */
1358     uint32_t hflags;
1359     target_ulong hflags_compat_nmsr; /* for migration compatibility */
1360 
1361     /* Power management */
1362     int (*check_pow)(CPUPPCState *env);
1363 
1364     /* attn instruction enable */
1365     int (*check_attn)(CPUPPCState *env);
1366 
1367 #if !defined(CONFIG_USER_ONLY)
1368     void *load_info;  /* holds boot loading state */
1369 #endif
1370 
1371     /* booke timers */
1372 
1373     /*
1374      * Specifies bit locations of the Time Base used to signal a fixed timer
1375      * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1376      *
1377      * 0 selects the least significant bit, 63 selects the most significant bit
1378      */
1379     uint8_t fit_period[4];
1380     uint8_t wdt_period[4];
1381 
1382     /* Transactional memory state */
1383     target_ulong tm_gpr[32];
1384     ppc_avr_t tm_vsr[64];
1385     uint64_t tm_cr;
1386     uint64_t tm_lr;
1387     uint64_t tm_ctr;
1388     uint64_t tm_fpscr;
1389     uint64_t tm_amr;
1390     uint64_t tm_ppr;
1391     uint64_t tm_vrsave;
1392     uint32_t tm_vscr;
1393     uint64_t tm_dscr;
1394     uint64_t tm_tar;
1395 
1396     /*
1397      * Timers used to fire performance monitor alerts
1398      * when counting cycles.
1399      */
1400     QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1401 
1402     /*
1403      * PMU base time value used by the PMU to calculate
1404      * running cycles.
1405      */
1406     uint64_t pmu_base_time;
1407 };
1408 
1409 #define THREAD_SIBLING_FOREACH(cs, cs_sibling)                  \
1410     CPU_FOREACH(cs_sibling)                                     \
1411         if (POWERPC_CPU(cs)->env.core_index ==                  \
1412             POWERPC_CPU(cs_sibling)->env.core_index)
1413 
1414 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1415 do {                                            \
1416     env->fit_period[0] = (a_);                  \
1417     env->fit_period[1] = (b_);                  \
1418     env->fit_period[2] = (c_);                  \
1419     env->fit_period[3] = (d_);                  \
1420  } while (0)
1421 
1422 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1423 do {                                            \
1424     env->wdt_period[0] = (a_);                  \
1425     env->wdt_period[1] = (b_);                  \
1426     env->wdt_period[2] = (c_);                  \
1427     env->wdt_period[3] = (d_);                  \
1428  } while (0)
1429 
1430 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1431 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1432 
1433 /**
1434  * PowerPCCPU:
1435  * @env: #CPUPPCState
1436  * @vcpu_id: vCPU identifier given to KVM
1437  * @compat_pvr: Current logical PVR, zero if in "raw" mode
1438  *
1439  * A PowerPC CPU.
1440  */
1441 struct ArchCPU {
1442     CPUState parent_obj;
1443 
1444     CPUPPCState env;
1445 
1446     int vcpu_id;
1447     uint32_t compat_pvr;
1448     PPCVirtualHypervisor *vhyp;
1449     PPCVirtualHypervisorClass *vhyp_class;
1450     void *machine_data;
1451     int32_t node_id; /* NUMA node this CPU belongs to */
1452     PPCHash64Options *hash64_opts;
1453 
1454     /* Those resources are used only during code translation */
1455     /* opcode handlers */
1456     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1457 
1458     /* Fields related to migration compatibility hacks */
1459     bool pre_2_8_migration;
1460     target_ulong mig_msr_mask;
1461     uint64_t mig_insns_flags;
1462     uint64_t mig_insns_flags2;
1463     uint32_t mig_nb_BATs;
1464     bool pre_2_10_migration;
1465     bool pre_3_0_migration;
1466     int32_t mig_slb_nr;
1467 };
1468 
1469 /**
1470  * PowerPCCPUClass:
1471  * @parent_realize: The parent class' realize handler.
1472  * @parent_phases: The parent class' reset phase handlers.
1473  *
1474  * A PowerPC CPU model.
1475  */
1476 struct PowerPCCPUClass {
1477     CPUClass parent_class;
1478 
1479     DeviceRealize parent_realize;
1480     DeviceUnrealize parent_unrealize;
1481     ResettablePhases parent_phases;
1482     void (*parent_parse_features)(const char *type, char *str, Error **errp);
1483 
1484     uint32_t pvr;
1485     /*
1486      * If @best is false, match if pcc is in the family of pvr
1487      * Else match only if pcc is the best match for pvr in this family.
1488      */
1489     bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
1490     uint64_t pcr_mask;          /* Available bits in PCR register */
1491     uint64_t pcr_supported;     /* Bits for supported PowerISA versions */
1492     uint32_t svr;
1493     uint64_t insns_flags;
1494     uint64_t insns_flags2;
1495     uint64_t msr_mask;
1496     uint64_t lpcr_mask;         /* Available bits in the LPCR */
1497     uint64_t lpcr_pm;           /* Power-saving mode Exit Cause Enable bits */
1498     powerpc_mmu_t   mmu_model;
1499     powerpc_excp_t  excp_model;
1500     powerpc_input_t bus_model;
1501     uint32_t flags;
1502     int bfd_mach;
1503     uint32_t l1_dcache_size, l1_icache_size;
1504 #ifndef CONFIG_USER_ONLY
1505     GDBFeature gdb_spr;
1506 #endif
1507     const PPCHash64Options *hash64_opts;
1508     struct ppc_radix_page_info *radix_page_info;
1509     uint32_t lrg_decr_bits;
1510     int n_host_threads;
1511     void (*init_proc)(CPUPPCState *env);
1512     int  (*check_pow)(CPUPPCState *env);
1513     int  (*check_attn)(CPUPPCState *env);
1514 };
1515 
1516 static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
1517 {
1518     return !POWERPC_CPU(cs)->env.has_smt_siblings;
1519 }
1520 
1521 static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
1522 {
1523     return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) ||
1524            ppc_cpu_core_single_threaded(cs);
1525 }
1526 
1527 ObjectClass *ppc_cpu_class_by_name(const char *name);
1528 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1529 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1530 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1531 
1532 #ifndef CONFIG_USER_ONLY
1533 struct PPCVirtualHypervisorClass {
1534     InterfaceClass parent;
1535     bool (*cpu_in_nested)(PowerPCCPU *cpu);
1536     void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1537     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1538     hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1539     const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1540                                          hwaddr ptex, int n);
1541     void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1542                         const ppc_hash_pte64_t *hptes,
1543                         hwaddr ptex, int n);
1544     void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1545     void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1546     bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1547                      target_ulong lpid, ppc_v3_pate_t *entry);
1548     target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1549     void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1550     void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1551 };
1552 
1553 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1554 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1555                      PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1556 
1557 static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1558 {
1559     return cpu->vhyp_class->cpu_in_nested(cpu);
1560 }
1561 #endif /* CONFIG_USER_ONLY */
1562 
1563 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1564 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1565 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1566 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1567 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1568 #ifndef CONFIG_USER_ONLY
1569 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1570 #endif
1571 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1572                                int cpuid, DumpState *s);
1573 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1574                                int cpuid, DumpState *s);
1575 #ifndef CONFIG_USER_ONLY
1576 void ppc_maybe_interrupt(CPUPPCState *env);
1577 void ppc_cpu_do_interrupt(CPUState *cpu);
1578 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1579 void ppc_cpu_do_system_reset(CPUState *cs);
1580 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1581 extern const VMStateDescription vmstate_ppc_cpu;
1582 #endif
1583 
1584 /*****************************************************************************/
1585 void ppc_translate_init(void);
1586 
1587 #if !defined(CONFIG_USER_ONLY)
1588 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1589 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1590 void ppc_update_ciabr(CPUPPCState *env);
1591 void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
1592 void ppc_update_daw0(CPUPPCState *env);
1593 void ppc_store_dawr0(CPUPPCState *env, target_ulong value);
1594 void ppc_store_dawrx0(CPUPPCState *env, uint32_t value);
1595 #endif /* !defined(CONFIG_USER_ONLY) */
1596 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1597 
1598 void ppc_cpu_list(void);
1599 
1600 /* Time-base and decrementer management */
1601 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1602 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1603 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1604 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1605 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1606 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1607 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1608 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1609 void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
1610 void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
1611 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1612 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1613 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1614 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1615 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1616 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1617 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1618 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1619 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1620 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1621 #if !defined(CONFIG_USER_ONLY)
1622 target_ulong load_40x_pit(CPUPPCState *env);
1623 void store_40x_pit(CPUPPCState *env, target_ulong val);
1624 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1625 void store_40x_sler(CPUPPCState *env, uint32_t val);
1626 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1627 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1628 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1629 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1630 void ppc_tlb_invalidate_all(CPUPPCState *env);
1631 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1632 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1633 void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1634 #endif
1635 
1636 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1637 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1638                                  const char *caller, uint32_t cause);
1639 
1640 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1641 {
1642     uint64_t gprv;
1643 
1644     gprv = env->gpr[gprn];
1645     if (env->flags & POWERPC_FLAG_SPE) {
1646         /*
1647          * If the CPU implements the SPE extension, we have to get the
1648          * high bits of the GPR from the gprh storage area
1649          */
1650         gprv &= 0xFFFFFFFFULL;
1651         gprv |= (uint64_t)env->gprh[gprn] << 32;
1652     }
1653 
1654     return gprv;
1655 }
1656 
1657 /* Device control registers */
1658 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1659 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1660 
1661 #define cpu_list ppc_cpu_list
1662 
1663 /* MMU modes definitions */
1664 #define MMU_USER_IDX 0
1665 static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
1666 {
1667 #ifdef CONFIG_USER_ONLY
1668     return MMU_USER_IDX;
1669 #else
1670     return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1671 #endif
1672 }
1673 
1674 /* Compatibility modes */
1675 #if defined(TARGET_PPC64)
1676 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1677                       uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1678 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1679                            uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1680 
1681 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1682 
1683 #if !defined(CONFIG_USER_ONLY)
1684 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1685 int ppc_init_compat_all(uint32_t compat_pvr, Error **errp);
1686 #endif
1687 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1688 void ppc_compat_add_property(Object *obj, const char *name,
1689                              uint32_t *compat_pvr, const char *basedesc);
1690 #endif /* defined(TARGET_PPC64) */
1691 
1692 #include "exec/cpu-all.h"
1693 
1694 /*****************************************************************************/
1695 /* CRF definitions */
1696 #define CRF_LT_BIT    3
1697 #define CRF_GT_BIT    2
1698 #define CRF_EQ_BIT    1
1699 #define CRF_SO_BIT    0
1700 #define CRF_LT        (1 << CRF_LT_BIT)
1701 #define CRF_GT        (1 << CRF_GT_BIT)
1702 #define CRF_EQ        (1 << CRF_EQ_BIT)
1703 #define CRF_SO        (1 << CRF_SO_BIT)
1704 /* For SPE extensions */
1705 #define CRF_CH        (1 << CRF_LT_BIT)
1706 #define CRF_CL        (1 << CRF_GT_BIT)
1707 #define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
1708 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1709 
1710 /* XER definitions */
1711 #define XER_SO  31
1712 #define XER_OV  30
1713 #define XER_CA  29
1714 #define XER_OV32  19
1715 #define XER_CA32  18
1716 #define XER_CMP  8
1717 #define XER_BC   0
1718 #define xer_so  (env->so)
1719 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1720 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1721 
1722 /* SPR definitions */
1723 #define SPR_MQ                (0x000)
1724 #define SPR_XER               (0x001)
1725 #define SPR_LR                (0x008)
1726 #define SPR_CTR               (0x009)
1727 #define SPR_UAMR              (0x00D)
1728 #define SPR_DSCR              (0x011)
1729 #define SPR_DSISR             (0x012)
1730 #define SPR_DAR               (0x013)
1731 #define SPR_DECR              (0x016)
1732 #define SPR_SDR1              (0x019)
1733 #define SPR_SRR0              (0x01A)
1734 #define SPR_SRR1              (0x01B)
1735 #define SPR_CFAR              (0x01C)
1736 #define SPR_AMR               (0x01D)
1737 #define SPR_ACOP              (0x01F)
1738 #define SPR_BOOKE_PID         (0x030)
1739 #define SPR_BOOKS_PID         (0x030)
1740 #define SPR_BOOKE_DECAR       (0x036)
1741 #define SPR_BOOKE_CSRR0       (0x03A)
1742 #define SPR_BOOKE_CSRR1       (0x03B)
1743 #define SPR_BOOKE_DEAR        (0x03D)
1744 #define SPR_IAMR              (0x03D)
1745 #define SPR_BOOKE_ESR         (0x03E)
1746 #define SPR_BOOKE_IVPR        (0x03F)
1747 #define SPR_MPC_EIE           (0x050)
1748 #define SPR_MPC_EID           (0x051)
1749 #define SPR_MPC_NRI           (0x052)
1750 #define SPR_TFHAR             (0x080)
1751 #define SPR_TFIAR             (0x081)
1752 #define SPR_TEXASR            (0x082)
1753 #define SPR_TEXASRU           (0x083)
1754 #define SPR_UCTRL             (0x088)
1755 #define SPR_TIDR              (0x090)
1756 #define SPR_MPC_CMPA          (0x090)
1757 #define SPR_MPC_CMPB          (0x091)
1758 #define SPR_MPC_CMPC          (0x092)
1759 #define SPR_MPC_CMPD          (0x093)
1760 #define SPR_MPC_ECR           (0x094)
1761 #define SPR_MPC_DER           (0x095)
1762 #define SPR_MPC_COUNTA        (0x096)
1763 #define SPR_MPC_COUNTB        (0x097)
1764 #define SPR_CTRL              (0x098)
1765 #define SPR_MPC_CMPE          (0x098)
1766 #define SPR_MPC_CMPF          (0x099)
1767 #define SPR_FSCR              (0x099)
1768 #define SPR_MPC_CMPG          (0x09A)
1769 #define SPR_MPC_CMPH          (0x09B)
1770 #define SPR_MPC_LCTRL1        (0x09C)
1771 #define SPR_MPC_LCTRL2        (0x09D)
1772 #define SPR_UAMOR             (0x09D)
1773 #define SPR_MPC_ICTRL         (0x09E)
1774 #define SPR_MPC_BAR           (0x09F)
1775 #define SPR_PSPB              (0x09F)
1776 #define SPR_DPDES             (0x0B0)
1777 #define SPR_DAWR0             (0x0B4)
1778 #define SPR_DAWR1             (0x0B5)
1779 #define SPR_RPR               (0x0BA)
1780 #define SPR_CIABR             (0x0BB)
1781 #define SPR_DAWRX0            (0x0BC)
1782 #define SPR_DAWRX1            (0x0BD)
1783 #define SPR_HFSCR             (0x0BE)
1784 #define SPR_VRSAVE            (0x100)
1785 #define SPR_USPRG0            (0x100)
1786 #define SPR_USPRG1            (0x101)
1787 #define SPR_USPRG2            (0x102)
1788 #define SPR_USPRG3            (0x103)
1789 #define SPR_USPRG4            (0x104)
1790 #define SPR_USPRG5            (0x105)
1791 #define SPR_USPRG6            (0x106)
1792 #define SPR_USPRG7            (0x107)
1793 #define SPR_TBL               (0x10C)
1794 #define SPR_TBU               (0x10D)
1795 #define SPR_SPRG0             (0x110)
1796 #define SPR_SPRG1             (0x111)
1797 #define SPR_SPRG2             (0x112)
1798 #define SPR_SPRG3             (0x113)
1799 #define SPR_SPRG4             (0x114)
1800 #define SPR_POWER_SPRC        (0x114)
1801 #define SPR_SPRG5             (0x115)
1802 #define SPR_POWER_SPRD        (0x115)
1803 #define SPR_SPRG6             (0x116)
1804 #define SPR_SPRG7             (0x117)
1805 #define SPR_ASR               (0x118)
1806 #define SPR_EAR               (0x11A)
1807 #define SPR_WR_TBL            (0x11C)
1808 #define SPR_WR_TBU            (0x11D)
1809 #define SPR_TBU40             (0x11E)
1810 #define SPR_SVR               (0x11E)
1811 #define SPR_BOOKE_PIR         (0x11E)
1812 #define SPR_PVR               (0x11F)
1813 #define SPR_HSPRG0            (0x130)
1814 #define SPR_BOOKE_DBSR        (0x130)
1815 #define SPR_HSPRG1            (0x131)
1816 #define SPR_HDSISR            (0x132)
1817 #define SPR_HDAR              (0x133)
1818 #define SPR_BOOKE_EPCR        (0x133)
1819 #define SPR_SPURR             (0x134)
1820 #define SPR_BOOKE_DBCR0       (0x134)
1821 #define SPR_IBCR              (0x135)
1822 #define SPR_PURR              (0x135)
1823 #define SPR_BOOKE_DBCR1       (0x135)
1824 #define SPR_DBCR              (0x136)
1825 #define SPR_HDEC              (0x136)
1826 #define SPR_BOOKE_DBCR2       (0x136)
1827 #define SPR_HIOR              (0x137)
1828 #define SPR_MBAR              (0x137)
1829 #define SPR_RMOR              (0x138)
1830 #define SPR_BOOKE_IAC1        (0x138)
1831 #define SPR_HRMOR             (0x139)
1832 #define SPR_BOOKE_IAC2        (0x139)
1833 #define SPR_HSRR0             (0x13A)
1834 #define SPR_BOOKE_IAC3        (0x13A)
1835 #define SPR_HSRR1             (0x13B)
1836 #define SPR_BOOKE_IAC4        (0x13B)
1837 #define SPR_BOOKE_DAC1        (0x13C)
1838 #define SPR_MMCRH             (0x13C)
1839 #define SPR_DABR2             (0x13D)
1840 #define SPR_BOOKE_DAC2        (0x13D)
1841 #define SPR_TFMR              (0x13D)
1842 #define SPR_BOOKE_DVC1        (0x13E)
1843 #define SPR_LPCR              (0x13E)
1844 #define SPR_BOOKE_DVC2        (0x13F)
1845 #define SPR_LPIDR             (0x13F)
1846 #define SPR_BOOKE_TSR         (0x150)
1847 #define SPR_HMER              (0x150)
1848 #define SPR_HMEER             (0x151)
1849 #define SPR_PCR               (0x152)
1850 #define SPR_HEIR              (0x153)
1851 #define SPR_BOOKE_LPIDR       (0x152)
1852 #define SPR_BOOKE_TCR         (0x154)
1853 #define SPR_BOOKE_TLB0PS      (0x158)
1854 #define SPR_BOOKE_TLB1PS      (0x159)
1855 #define SPR_BOOKE_TLB2PS      (0x15A)
1856 #define SPR_BOOKE_TLB3PS      (0x15B)
1857 #define SPR_AMOR              (0x15D)
1858 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1859 #define SPR_BOOKE_IVOR0       (0x190)
1860 #define SPR_BOOKE_IVOR1       (0x191)
1861 #define SPR_BOOKE_IVOR2       (0x192)
1862 #define SPR_BOOKE_IVOR3       (0x193)
1863 #define SPR_BOOKE_IVOR4       (0x194)
1864 #define SPR_BOOKE_IVOR5       (0x195)
1865 #define SPR_BOOKE_IVOR6       (0x196)
1866 #define SPR_BOOKE_IVOR7       (0x197)
1867 #define SPR_BOOKE_IVOR8       (0x198)
1868 #define SPR_BOOKE_IVOR9       (0x199)
1869 #define SPR_BOOKE_IVOR10      (0x19A)
1870 #define SPR_BOOKE_IVOR11      (0x19B)
1871 #define SPR_BOOKE_IVOR12      (0x19C)
1872 #define SPR_BOOKE_IVOR13      (0x19D)
1873 #define SPR_BOOKE_IVOR14      (0x19E)
1874 #define SPR_BOOKE_IVOR15      (0x19F)
1875 #define SPR_BOOKE_IVOR38      (0x1B0)
1876 #define SPR_BOOKE_IVOR39      (0x1B1)
1877 #define SPR_BOOKE_IVOR40      (0x1B2)
1878 #define SPR_BOOKE_IVOR41      (0x1B3)
1879 #define SPR_BOOKE_IVOR42      (0x1B4)
1880 #define SPR_BOOKE_GIVOR2      (0x1B8)
1881 #define SPR_BOOKE_GIVOR3      (0x1B9)
1882 #define SPR_BOOKE_GIVOR4      (0x1BA)
1883 #define SPR_BOOKE_GIVOR8      (0x1BB)
1884 #define SPR_BOOKE_GIVOR13     (0x1BC)
1885 #define SPR_BOOKE_GIVOR14     (0x1BD)
1886 #define SPR_TIR               (0x1BE)
1887 #define SPR_UHDEXCR           (0x1C7)
1888 #define SPR_PTCR              (0x1D0)
1889 #define SPR_HASHKEYR          (0x1D4)
1890 #define SPR_HASHPKEYR         (0x1D5)
1891 #define SPR_HDEXCR            (0x1D7)
1892 #define SPR_BOOKE_SPEFSCR     (0x200)
1893 #define SPR_Exxx_BBEAR        (0x201)
1894 #define SPR_Exxx_BBTAR        (0x202)
1895 #define SPR_Exxx_L1CFG0       (0x203)
1896 #define SPR_Exxx_L1CFG1       (0x204)
1897 #define SPR_Exxx_NPIDR        (0x205)
1898 #define SPR_ATBL              (0x20E)
1899 #define SPR_ATBU              (0x20F)
1900 #define SPR_IBAT0U            (0x210)
1901 #define SPR_BOOKE_IVOR32      (0x210)
1902 #define SPR_RCPU_MI_GRA       (0x210)
1903 #define SPR_IBAT0L            (0x211)
1904 #define SPR_BOOKE_IVOR33      (0x211)
1905 #define SPR_IBAT1U            (0x212)
1906 #define SPR_BOOKE_IVOR34      (0x212)
1907 #define SPR_IBAT1L            (0x213)
1908 #define SPR_BOOKE_IVOR35      (0x213)
1909 #define SPR_IBAT2U            (0x214)
1910 #define SPR_BOOKE_IVOR36      (0x214)
1911 #define SPR_IBAT2L            (0x215)
1912 #define SPR_BOOKE_IVOR37      (0x215)
1913 #define SPR_IBAT3U            (0x216)
1914 #define SPR_IBAT3L            (0x217)
1915 #define SPR_DBAT0U            (0x218)
1916 #define SPR_RCPU_L2U_GRA      (0x218)
1917 #define SPR_DBAT0L            (0x219)
1918 #define SPR_DBAT1U            (0x21A)
1919 #define SPR_DBAT1L            (0x21B)
1920 #define SPR_DBAT2U            (0x21C)
1921 #define SPR_DBAT2L            (0x21D)
1922 #define SPR_DBAT3U            (0x21E)
1923 #define SPR_DBAT3L            (0x21F)
1924 #define SPR_IBAT4U            (0x230)
1925 #define SPR_RPCU_BBCMCR       (0x230)
1926 #define SPR_MPC_IC_CST        (0x230)
1927 #define SPR_Exxx_CTXCR        (0x230)
1928 #define SPR_IBAT4L            (0x231)
1929 #define SPR_MPC_IC_ADR        (0x231)
1930 #define SPR_Exxx_DBCR3        (0x231)
1931 #define SPR_IBAT5U            (0x232)
1932 #define SPR_MPC_IC_DAT        (0x232)
1933 #define SPR_Exxx_DBCNT        (0x232)
1934 #define SPR_IBAT5L            (0x233)
1935 #define SPR_IBAT6U            (0x234)
1936 #define SPR_IBAT6L            (0x235)
1937 #define SPR_IBAT7U            (0x236)
1938 #define SPR_IBAT7L            (0x237)
1939 #define SPR_DBAT4U            (0x238)
1940 #define SPR_RCPU_L2U_MCR      (0x238)
1941 #define SPR_MPC_DC_CST        (0x238)
1942 #define SPR_Exxx_ALTCTXCR     (0x238)
1943 #define SPR_DBAT4L            (0x239)
1944 #define SPR_MPC_DC_ADR        (0x239)
1945 #define SPR_DBAT5U            (0x23A)
1946 #define SPR_BOOKE_MCSRR0      (0x23A)
1947 #define SPR_MPC_DC_DAT        (0x23A)
1948 #define SPR_DBAT5L            (0x23B)
1949 #define SPR_BOOKE_MCSRR1      (0x23B)
1950 #define SPR_DBAT6U            (0x23C)
1951 #define SPR_BOOKE_MCSR        (0x23C)
1952 #define SPR_DBAT6L            (0x23D)
1953 #define SPR_Exxx_MCAR         (0x23D)
1954 #define SPR_DBAT7U            (0x23E)
1955 #define SPR_BOOKE_DSRR0       (0x23E)
1956 #define SPR_DBAT7L            (0x23F)
1957 #define SPR_BOOKE_DSRR1       (0x23F)
1958 #define SPR_BOOKE_SPRG8       (0x25C)
1959 #define SPR_BOOKE_SPRG9       (0x25D)
1960 #define SPR_BOOKE_MAS0        (0x270)
1961 #define SPR_BOOKE_MAS1        (0x271)
1962 #define SPR_BOOKE_MAS2        (0x272)
1963 #define SPR_BOOKE_MAS3        (0x273)
1964 #define SPR_BOOKE_MAS4        (0x274)
1965 #define SPR_BOOKE_MAS5        (0x275)
1966 #define SPR_BOOKE_MAS6        (0x276)
1967 #define SPR_BOOKE_PID1        (0x279)
1968 #define SPR_BOOKE_PID2        (0x27A)
1969 #define SPR_MPC_DPDR          (0x280)
1970 #define SPR_MPC_IMMR          (0x288)
1971 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1972 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1973 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1974 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1975 #define SPR_BOOKE_EPR         (0x2BE)
1976 #define SPR_POWER_USIER2      (0x2E0)
1977 #define SPR_POWER_USIER3      (0x2E1)
1978 #define SPR_POWER_UMMCR3      (0x2E2)
1979 #define SPR_POWER_SIER2       (0x2F0)
1980 #define SPR_POWER_SIER3       (0x2F1)
1981 #define SPR_POWER_MMCR3       (0x2F2)
1982 #define SPR_PERF0             (0x300)
1983 #define SPR_RCPU_MI_RBA0      (0x300)
1984 #define SPR_MPC_MI_CTR        (0x300)
1985 #define SPR_POWER_USIER       (0x300)
1986 #define SPR_PERF1             (0x301)
1987 #define SPR_RCPU_MI_RBA1      (0x301)
1988 #define SPR_POWER_UMMCR2      (0x301)
1989 #define SPR_PERF2             (0x302)
1990 #define SPR_RCPU_MI_RBA2      (0x302)
1991 #define SPR_MPC_MI_AP         (0x302)
1992 #define SPR_POWER_UMMCRA      (0x302)
1993 #define SPR_PERF3             (0x303)
1994 #define SPR_RCPU_MI_RBA3      (0x303)
1995 #define SPR_MPC_MI_EPN        (0x303)
1996 #define SPR_POWER_UPMC1       (0x303)
1997 #define SPR_PERF4             (0x304)
1998 #define SPR_POWER_UPMC2       (0x304)
1999 #define SPR_PERF5             (0x305)
2000 #define SPR_MPC_MI_TWC        (0x305)
2001 #define SPR_POWER_UPMC3       (0x305)
2002 #define SPR_PERF6             (0x306)
2003 #define SPR_MPC_MI_RPN        (0x306)
2004 #define SPR_POWER_UPMC4       (0x306)
2005 #define SPR_PERF7             (0x307)
2006 #define SPR_POWER_UPMC5       (0x307)
2007 #define SPR_PERF8             (0x308)
2008 #define SPR_RCPU_L2U_RBA0     (0x308)
2009 #define SPR_MPC_MD_CTR        (0x308)
2010 #define SPR_POWER_UPMC6       (0x308)
2011 #define SPR_PERF9             (0x309)
2012 #define SPR_RCPU_L2U_RBA1     (0x309)
2013 #define SPR_MPC_MD_CASID      (0x309)
2014 #define SPR_970_UPMC7         (0X309)
2015 #define SPR_PERFA             (0x30A)
2016 #define SPR_RCPU_L2U_RBA2     (0x30A)
2017 #define SPR_MPC_MD_AP         (0x30A)
2018 #define SPR_970_UPMC8         (0X30A)
2019 #define SPR_PERFB             (0x30B)
2020 #define SPR_RCPU_L2U_RBA3     (0x30B)
2021 #define SPR_MPC_MD_EPN        (0x30B)
2022 #define SPR_POWER_UMMCR0      (0X30B)
2023 #define SPR_PERFC             (0x30C)
2024 #define SPR_MPC_MD_TWB        (0x30C)
2025 #define SPR_POWER_USIAR       (0X30C)
2026 #define SPR_PERFD             (0x30D)
2027 #define SPR_MPC_MD_TWC        (0x30D)
2028 #define SPR_POWER_USDAR       (0X30D)
2029 #define SPR_PERFE             (0x30E)
2030 #define SPR_MPC_MD_RPN        (0x30E)
2031 #define SPR_POWER_UMMCR1      (0X30E)
2032 #define SPR_PERFF             (0x30F)
2033 #define SPR_MPC_MD_TW         (0x30F)
2034 #define SPR_UPERF0            (0x310)
2035 #define SPR_POWER_SIER        (0x310)
2036 #define SPR_UPERF1            (0x311)
2037 #define SPR_POWER_MMCR2       (0x311)
2038 #define SPR_UPERF2            (0x312)
2039 #define SPR_POWER_MMCRA       (0X312)
2040 #define SPR_UPERF3            (0x313)
2041 #define SPR_POWER_PMC1        (0X313)
2042 #define SPR_UPERF4            (0x314)
2043 #define SPR_POWER_PMC2        (0X314)
2044 #define SPR_UPERF5            (0x315)
2045 #define SPR_POWER_PMC3        (0X315)
2046 #define SPR_UPERF6            (0x316)
2047 #define SPR_POWER_PMC4        (0X316)
2048 #define SPR_UPERF7            (0x317)
2049 #define SPR_POWER_PMC5        (0X317)
2050 #define SPR_UPERF8            (0x318)
2051 #define SPR_POWER_PMC6        (0X318)
2052 #define SPR_UPERF9            (0x319)
2053 #define SPR_970_PMC7          (0X319)
2054 #define SPR_UPERFA            (0x31A)
2055 #define SPR_970_PMC8          (0X31A)
2056 #define SPR_UPERFB            (0x31B)
2057 #define SPR_POWER_MMCR0       (0X31B)
2058 #define SPR_UPERFC            (0x31C)
2059 #define SPR_POWER_SIAR        (0X31C)
2060 #define SPR_UPERFD            (0x31D)
2061 #define SPR_POWER_SDAR        (0X31D)
2062 #define SPR_UPERFE            (0x31E)
2063 #define SPR_POWER_MMCR1       (0X31E)
2064 #define SPR_UPERFF            (0x31F)
2065 #define SPR_RCPU_MI_RA0       (0x320)
2066 #define SPR_MPC_MI_DBCAM      (0x320)
2067 #define SPR_BESCRS            (0x320)
2068 #define SPR_RCPU_MI_RA1       (0x321)
2069 #define SPR_MPC_MI_DBRAM0     (0x321)
2070 #define SPR_BESCRSU           (0x321)
2071 #define SPR_RCPU_MI_RA2       (0x322)
2072 #define SPR_MPC_MI_DBRAM1     (0x322)
2073 #define SPR_BESCRR            (0x322)
2074 #define SPR_RCPU_MI_RA3       (0x323)
2075 #define SPR_BESCRRU           (0x323)
2076 #define SPR_EBBHR             (0x324)
2077 #define SPR_EBBRR             (0x325)
2078 #define SPR_BESCR             (0x326)
2079 #define SPR_RCPU_L2U_RA0      (0x328)
2080 #define SPR_MPC_MD_DBCAM      (0x328)
2081 #define SPR_RCPU_L2U_RA1      (0x329)
2082 #define SPR_MPC_MD_DBRAM0     (0x329)
2083 #define SPR_RCPU_L2U_RA2      (0x32A)
2084 #define SPR_MPC_MD_DBRAM1     (0x32A)
2085 #define SPR_RCPU_L2U_RA3      (0x32B)
2086 #define SPR_UDEXCR            (0x32C)
2087 #define SPR_TAR               (0x32F)
2088 #define SPR_ASDR              (0x330)
2089 #define SPR_DEXCR             (0x33C)
2090 #define SPR_IC                (0x350)
2091 #define SPR_VTB               (0x351)
2092 #define SPR_LDBAR             (0x352)
2093 #define SPR_MMCRC             (0x353)
2094 #define SPR_PSSCR             (0x357)
2095 #define SPR_440_INV0          (0x370)
2096 #define SPR_440_INV1          (0x371)
2097 #define SPR_TRIG1             (0x371)
2098 #define SPR_440_INV2          (0x372)
2099 #define SPR_TRIG2             (0x372)
2100 #define SPR_440_INV3          (0x373)
2101 #define SPR_440_ITV0          (0x374)
2102 #define SPR_440_ITV1          (0x375)
2103 #define SPR_440_ITV2          (0x376)
2104 #define SPR_440_ITV3          (0x377)
2105 #define SPR_440_CCR1          (0x378)
2106 #define SPR_TACR              (0x378)
2107 #define SPR_TCSCR             (0x379)
2108 #define SPR_CSIGR             (0x37a)
2109 #define SPR_DCRIPR            (0x37B)
2110 #define SPR_POWER_SPMC1       (0x37C)
2111 #define SPR_POWER_SPMC2       (0x37D)
2112 #define SPR_POWER_MMCRS       (0x37E)
2113 #define SPR_WORT              (0x37F)
2114 #define SPR_PPR               (0x380)
2115 #define SPR_PPR32             (0x382)
2116 #define SPR_750_GQR0          (0x390)
2117 #define SPR_440_DNV0          (0x390)
2118 #define SPR_750_GQR1          (0x391)
2119 #define SPR_440_DNV1          (0x391)
2120 #define SPR_750_GQR2          (0x392)
2121 #define SPR_440_DNV2          (0x392)
2122 #define SPR_750_GQR3          (0x393)
2123 #define SPR_440_DNV3          (0x393)
2124 #define SPR_750_GQR4          (0x394)
2125 #define SPR_440_DTV0          (0x394)
2126 #define SPR_750_GQR5          (0x395)
2127 #define SPR_440_DTV1          (0x395)
2128 #define SPR_750_GQR6          (0x396)
2129 #define SPR_440_DTV2          (0x396)
2130 #define SPR_750_GQR7          (0x397)
2131 #define SPR_440_DTV3          (0x397)
2132 #define SPR_750_THRM4         (0x398)
2133 #define SPR_750CL_HID2        (0x398)
2134 #define SPR_440_DVLIM         (0x398)
2135 #define SPR_750_WPAR          (0x399)
2136 #define SPR_440_IVLIM         (0x399)
2137 #define SPR_TSCR              (0x399)
2138 #define SPR_750_DMAU          (0x39A)
2139 #define SPR_POWER_TTR         (0x39A)
2140 #define SPR_750_DMAL          (0x39B)
2141 #define SPR_440_RSTCFG        (0x39B)
2142 #define SPR_BOOKE_DCDBTRL     (0x39C)
2143 #define SPR_BOOKE_DCDBTRH     (0x39D)
2144 #define SPR_BOOKE_ICDBTRL     (0x39E)
2145 #define SPR_BOOKE_ICDBTRH     (0x39F)
2146 #define SPR_74XX_UMMCR2       (0x3A0)
2147 #define SPR_7XX_UPMC5         (0x3A1)
2148 #define SPR_7XX_UPMC6         (0x3A2)
2149 #define SPR_UBAMR             (0x3A7)
2150 #define SPR_7XX_UMMCR0        (0x3A8)
2151 #define SPR_7XX_UPMC1         (0x3A9)
2152 #define SPR_7XX_UPMC2         (0x3AA)
2153 #define SPR_7XX_USIAR         (0x3AB)
2154 #define SPR_7XX_UMMCR1        (0x3AC)
2155 #define SPR_7XX_UPMC3         (0x3AD)
2156 #define SPR_7XX_UPMC4         (0x3AE)
2157 #define SPR_USDA              (0x3AF)
2158 #define SPR_40x_ZPR           (0x3B0)
2159 #define SPR_BOOKE_MAS7        (0x3B0)
2160 #define SPR_74XX_MMCR2        (0x3B0)
2161 #define SPR_7XX_PMC5          (0x3B1)
2162 #define SPR_40x_PID           (0x3B1)
2163 #define SPR_7XX_PMC6          (0x3B2)
2164 #define SPR_440_MMUCR         (0x3B2)
2165 #define SPR_4xx_CCR0          (0x3B3)
2166 #define SPR_BOOKE_EPLC        (0x3B3)
2167 #define SPR_405_IAC3          (0x3B4)
2168 #define SPR_BOOKE_EPSC        (0x3B4)
2169 #define SPR_405_IAC4          (0x3B5)
2170 #define SPR_405_DVC1          (0x3B6)
2171 #define SPR_405_DVC2          (0x3B7)
2172 #define SPR_BAMR              (0x3B7)
2173 #define SPR_7XX_MMCR0         (0x3B8)
2174 #define SPR_7XX_PMC1          (0x3B9)
2175 #define SPR_40x_SGR           (0x3B9)
2176 #define SPR_7XX_PMC2          (0x3BA)
2177 #define SPR_40x_DCWR          (0x3BA)
2178 #define SPR_7XX_SIAR          (0x3BB)
2179 #define SPR_405_SLER          (0x3BB)
2180 #define SPR_7XX_MMCR1         (0x3BC)
2181 #define SPR_405_SU0R          (0x3BC)
2182 #define SPR_401_SKR           (0x3BC)
2183 #define SPR_7XX_PMC3          (0x3BD)
2184 #define SPR_405_DBCR1         (0x3BD)
2185 #define SPR_7XX_PMC4          (0x3BE)
2186 #define SPR_SDA               (0x3BF)
2187 #define SPR_403_VTBL          (0x3CC)
2188 #define SPR_403_VTBU          (0x3CD)
2189 #define SPR_DMISS             (0x3D0)
2190 #define SPR_DCMP              (0x3D1)
2191 #define SPR_HASH1             (0x3D2)
2192 #define SPR_HASH2             (0x3D3)
2193 #define SPR_BOOKE_ICDBDR      (0x3D3)
2194 #define SPR_TLBMISS           (0x3D4)
2195 #define SPR_IMISS             (0x3D4)
2196 #define SPR_40x_ESR           (0x3D4)
2197 #define SPR_PTEHI             (0x3D5)
2198 #define SPR_ICMP              (0x3D5)
2199 #define SPR_40x_DEAR          (0x3D5)
2200 #define SPR_PTELO             (0x3D6)
2201 #define SPR_RPA               (0x3D6)
2202 #define SPR_40x_EVPR          (0x3D6)
2203 #define SPR_L3PM              (0x3D7)
2204 #define SPR_403_CDBCR         (0x3D7)
2205 #define SPR_L3ITCR0           (0x3D8)
2206 #define SPR_TCR               (0x3D8)
2207 #define SPR_40x_TSR           (0x3D8)
2208 #define SPR_IBR               (0x3DA)
2209 #define SPR_40x_TCR           (0x3DA)
2210 #define SPR_ESASRR            (0x3DB)
2211 #define SPR_40x_PIT           (0x3DB)
2212 #define SPR_403_TBL           (0x3DC)
2213 #define SPR_403_TBU           (0x3DD)
2214 #define SPR_SEBR              (0x3DE)
2215 #define SPR_40x_SRR2          (0x3DE)
2216 #define SPR_SER               (0x3DF)
2217 #define SPR_40x_SRR3          (0x3DF)
2218 #define SPR_L3OHCR            (0x3E8)
2219 #define SPR_L3ITCR1           (0x3E9)
2220 #define SPR_L3ITCR2           (0x3EA)
2221 #define SPR_L3ITCR3           (0x3EB)
2222 #define SPR_HID0              (0x3F0)
2223 #define SPR_40x_DBSR          (0x3F0)
2224 #define SPR_HID1              (0x3F1)
2225 #define SPR_IABR              (0x3F2)
2226 #define SPR_40x_DBCR0         (0x3F2)
2227 #define SPR_Exxx_L1CSR0       (0x3F2)
2228 #define SPR_ICTRL             (0x3F3)
2229 #define SPR_HID2              (0x3F3)
2230 #define SPR_750CL_HID4        (0x3F3)
2231 #define SPR_Exxx_L1CSR1       (0x3F3)
2232 #define SPR_440_DBDR          (0x3F3)
2233 #define SPR_LDSTDB            (0x3F4)
2234 #define SPR_750_TDCL          (0x3F4)
2235 #define SPR_40x_IAC1          (0x3F4)
2236 #define SPR_MMUCSR0           (0x3F4)
2237 #define SPR_970_HID4          (0x3F4)
2238 #define SPR_DABR              (0x3F5)
2239 #define DABR_MASK (~(target_ulong)0x7)
2240 #define SPR_Exxx_BUCSR        (0x3F5)
2241 #define SPR_40x_IAC2          (0x3F5)
2242 #define SPR_40x_DAC1          (0x3F6)
2243 #define SPR_MSSCR0            (0x3F6)
2244 #define SPR_970_HID5          (0x3F6)
2245 #define SPR_MSSSR0            (0x3F7)
2246 #define SPR_MSSCR1            (0x3F7)
2247 #define SPR_DABRX             (0x3F7)
2248 #define SPR_40x_DAC2          (0x3F7)
2249 #define SPR_MMUCFG            (0x3F7)
2250 #define SPR_LDSTCR            (0x3F8)
2251 #define SPR_L2PMCR            (0x3F8)
2252 #define SPR_750FX_HID2        (0x3F8)
2253 #define SPR_Exxx_L1FINV0      (0x3F8)
2254 #define SPR_L2CR              (0x3F9)
2255 #define SPR_Exxx_L2CSR0       (0x3F9)
2256 #define SPR_L3CR              (0x3FA)
2257 #define SPR_750_TDCH          (0x3FA)
2258 #define SPR_IABR2             (0x3FA)
2259 #define SPR_40x_DCCR          (0x3FA)
2260 #define SPR_ICTC              (0x3FB)
2261 #define SPR_40x_ICCR          (0x3FB)
2262 #define SPR_THRM1             (0x3FC)
2263 #define SPR_403_PBL1          (0x3FC)
2264 #define SPR_SP                (0x3FD)
2265 #define SPR_THRM2             (0x3FD)
2266 #define SPR_403_PBU1          (0x3FD)
2267 #define SPR_604_HID13         (0x3FD)
2268 #define SPR_LT                (0x3FE)
2269 #define SPR_THRM3             (0x3FE)
2270 #define SPR_RCPU_FPECR        (0x3FE)
2271 #define SPR_403_PBL2          (0x3FE)
2272 #define SPR_PIR               (0x3FF)
2273 #define SPR_403_PBU2          (0x3FF)
2274 #define SPR_604_HID15         (0x3FF)
2275 #define SPR_E500_SVR          (0x3FF)
2276 
2277 /* Disable MAS Interrupt Updates for Hypervisor */
2278 #define EPCR_DMIUH            (1 << 22)
2279 /* Disable Guest TLB Management Instructions */
2280 #define EPCR_DGTMI            (1 << 23)
2281 /* Guest Interrupt Computation Mode */
2282 #define EPCR_GICM             (1 << 24)
2283 /* Interrupt Computation Mode */
2284 #define EPCR_ICM              (1 << 25)
2285 /* Disable Embedded Hypervisor Debug */
2286 #define EPCR_DUVD             (1 << 26)
2287 /* Instruction Storage Interrupt Directed to Guest State */
2288 #define EPCR_ISIGS            (1 << 27)
2289 /* Data Storage Interrupt Directed to Guest State */
2290 #define EPCR_DSIGS            (1 << 28)
2291 /* Instruction TLB Error Interrupt Directed to Guest State */
2292 #define EPCR_ITLBGS           (1 << 29)
2293 /* Data TLB Error Interrupt Directed to Guest State */
2294 #define EPCR_DTLBGS           (1 << 30)
2295 /* External Input Interrupt Directed to Guest State */
2296 #define EPCR_EXTGS            (1 << 31)
2297 
2298 #define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
2299 #define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
2300 #define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
2301 #define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
2302 #define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
2303 
2304 #define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
2305 #define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
2306 #define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
2307 #define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
2308 #define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
2309 
2310 /* E500 L2CSR0 */
2311 #define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
2312 #define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
2313 #define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
2314 
2315 /* HID0 bits */
2316 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
2317 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
2318 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
2319 #define HID0_HILE           PPC_BIT(19) /* POWER8 */
2320 #define HID0_POWER9_HILE    PPC_BIT(4)
2321 #define HID0_ENABLE_ATTN    PPC_BIT(31) /* POWER8 */
2322 #define HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
2323 
2324 /*****************************************************************************/
2325 /* PowerPC Instructions types definitions                                    */
2326 enum {
2327     PPC_NONE           = 0x0000000000000000ULL,
2328     /* PowerPC base instructions set                                         */
2329     PPC_INSNS_BASE     = 0x0000000000000001ULL,
2330     /*   integer operations instructions                                     */
2331 #define PPC_INTEGER PPC_INSNS_BASE
2332     /*   flow control instructions                                           */
2333 #define PPC_FLOW    PPC_INSNS_BASE
2334     /*   virtual memory instructions                                         */
2335 #define PPC_MEM     PPC_INSNS_BASE
2336     /*   ld/st with reservation instructions                                 */
2337 #define PPC_RES     PPC_INSNS_BASE
2338     /*   spr/msr access instructions                                         */
2339 #define PPC_MISC    PPC_INSNS_BASE
2340     /* 64 bits PowerPC instruction set                                       */
2341     PPC_64B            = 0x0000000000000020ULL,
2342     /*   New 64 bits extensions (PowerPC 2.0x)                               */
2343     PPC_64BX           = 0x0000000000000040ULL,
2344     /*   64 bits hypervisor extensions                                       */
2345     PPC_64H            = 0x0000000000000080ULL,
2346     /*   New wait instruction (PowerPC 2.0x)                                 */
2347     PPC_WAIT           = 0x0000000000000100ULL,
2348     /*   Time base mftb instruction                                          */
2349     PPC_MFTB           = 0x0000000000000200ULL,
2350 
2351     /* Fixed-point unit extensions                                           */
2352     /*   isel instruction                                                    */
2353     PPC_ISEL           = 0x0000000000000800ULL,
2354     /*   popcntb instruction                                                 */
2355     PPC_POPCNTB        = 0x0000000000001000ULL,
2356     /*   string load / store                                                 */
2357     PPC_STRING         = 0x0000000000002000ULL,
2358     /*   real mode cache inhibited load / store                              */
2359     PPC_CILDST         = 0x0000000000004000ULL,
2360 
2361     /* Floating-point unit extensions                                        */
2362     /*   Optional floating point instructions                                */
2363     PPC_FLOAT          = 0x0000000000010000ULL,
2364     /* New floating-point extensions (PowerPC 2.0x)                          */
2365     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
2366     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
2367     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
2368     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
2369     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2370     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
2371     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
2372 
2373     /* Vector/SIMD extensions                                                */
2374     /*   Altivec support                                                     */
2375     PPC_ALTIVEC        = 0x0000000001000000ULL,
2376     /*   PowerPC 2.03 SPE extension                                          */
2377     PPC_SPE            = 0x0000000002000000ULL,
2378     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
2379     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
2380     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
2381     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
2382 
2383     /* Optional memory control instructions                                  */
2384     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
2385     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
2386     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
2387     /*   sync instruction                                                    */
2388     PPC_MEM_SYNC       = 0x0000000080000000ULL,
2389     /*   eieio instruction                                                   */
2390     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
2391 
2392     /* Cache control instructions                                            */
2393     PPC_CACHE          = 0x0000000200000000ULL,
2394     /*   icbi instruction                                                    */
2395     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
2396     /*   dcbz instruction                                                    */
2397     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
2398     /*   dcba instruction                                                    */
2399     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
2400     /*   Freescale cache locking instructions                                */
2401     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
2402 
2403     /* MMU related extensions                                                */
2404     /*   external control instructions                                       */
2405     PPC_EXTERN         = 0x0000010000000000ULL,
2406     /*   segment register access instructions                                */
2407     PPC_SEGMENT        = 0x0000020000000000ULL,
2408     /*   PowerPC 6xx TLB management instructions                             */
2409     PPC_6xx_TLB        = 0x0000040000000000ULL,
2410     /*   PowerPC 40x TLB management instructions                             */
2411     PPC_40x_TLB        = 0x0000100000000000ULL,
2412     /*   segment register access instructions for PowerPC 64 "bridge"        */
2413     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
2414     /*   SLB management                                                      */
2415     PPC_SLBI           = 0x0000400000000000ULL,
2416 
2417     /* Embedded PowerPC dedicated instructions                               */
2418     PPC_WRTEE          = 0x0001000000000000ULL,
2419     /* PowerPC 40x exception model                                           */
2420     PPC_40x_EXCP       = 0x0002000000000000ULL,
2421     /* PowerPC 405 Mac instructions                                          */
2422     PPC_405_MAC        = 0x0004000000000000ULL,
2423     /* PowerPC 440 specific instructions                                     */
2424     PPC_440_SPEC       = 0x0008000000000000ULL,
2425     /* BookE (embedded) PowerPC specification                                */
2426     PPC_BOOKE          = 0x0010000000000000ULL,
2427     /* mfapidi instruction                                                   */
2428     PPC_MFAPIDI        = 0x0020000000000000ULL,
2429     /* tlbiva instruction                                                    */
2430     PPC_TLBIVA         = 0x0040000000000000ULL,
2431     /* tlbivax instruction                                                   */
2432     PPC_TLBIVAX        = 0x0080000000000000ULL,
2433     /* PowerPC 4xx dedicated instructions                                    */
2434     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2435     /* PowerPC 40x ibct instructions                                         */
2436     PPC_40x_ICBT       = 0x0200000000000000ULL,
2437     /* rfmci is not implemented in all BookE PowerPC                         */
2438     PPC_RFMCI          = 0x0400000000000000ULL,
2439     /* rfdi instruction                                                      */
2440     PPC_RFDI           = 0x0800000000000000ULL,
2441     /* DCR accesses                                                          */
2442     PPC_DCR            = 0x1000000000000000ULL,
2443     /* DCR extended accesse                                                  */
2444     PPC_DCRX           = 0x2000000000000000ULL,
2445     /* popcntw and popcntd instructions                                      */
2446     PPC_POPCNTWD       = 0x8000000000000000ULL,
2447 
2448 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_64B \
2449                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2450                         | PPC_ISEL | PPC_POPCNTB \
2451                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2452                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2453                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2454                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2455                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2456                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2457                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2458                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2459                         | PPC_CACHE | PPC_CACHE_ICBI \
2460                         | PPC_CACHE_DCBZ \
2461                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2462                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2463                         | PPC_40x_TLB | PPC_SEGMENT_64B \
2464                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2465                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2466                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2467                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2468                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
2469                         | PPC_CILDST)
2470 
2471     /* extended type values */
2472 
2473     /* BookE 2.06 PowerPC specification                                      */
2474     PPC2_BOOKE206      = 0x0000000000000001ULL,
2475     /* VSX (extensions to Altivec / VMX)                                     */
2476     PPC2_VSX           = 0x0000000000000002ULL,
2477     /* Decimal Floating Point (DFP)                                          */
2478     PPC2_DFP           = 0x0000000000000004ULL,
2479     /* Embedded.Processor Control                                            */
2480     PPC2_PRCNTL        = 0x0000000000000008ULL,
2481     /* Byte-reversed, indexed, double-word load and store                    */
2482     PPC2_DBRX          = 0x0000000000000010ULL,
2483     /* Book I 2.05 PowerPC specification                                     */
2484     PPC2_ISA205        = 0x0000000000000020ULL,
2485     /* VSX additions in ISA 2.07                                             */
2486     PPC2_VSX207        = 0x0000000000000040ULL,
2487     /* ISA 2.06B bpermd                                                      */
2488     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2489     /* ISA 2.06B divide extended variants                                    */
2490     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2491     /* ISA 2.06B larx/stcx. instructions                                     */
2492     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2493     /* ISA 2.06B floating point integer conversion                           */
2494     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2495     /* ISA 2.06B floating point test instructions                            */
2496     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2497     /* ISA 2.07 bctar instruction                                            */
2498     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2499     /* ISA 2.07 load/store quadword                                          */
2500     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2501     /* ISA 2.07 Altivec                                                      */
2502     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2503     /* PowerISA 2.07 Book3s specification                                    */
2504     PPC2_ISA207S       = 0x0000000000008000ULL,
2505     /* Double precision floating point conversion for signed integer 64      */
2506     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2507     /* Transactional Memory (ISA 2.07, Book II)                              */
2508     PPC2_TM            = 0x0000000000020000ULL,
2509     /* Server PM instructgions (ISA 2.06, Book III)                          */
2510     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2511     /* POWER ISA 3.0                                                         */
2512     PPC2_ISA300        = 0x0000000000080000ULL,
2513     /* POWER ISA 3.1                                                         */
2514     PPC2_ISA310        = 0x0000000000100000ULL,
2515     /*   lwsync instruction                                                  */
2516     PPC2_MEM_LWSYNC    = 0x0000000000200000ULL,
2517     /* ISA 2.06 BCD assist instructions                                      */
2518     PPC2_BCDA_ISA206   = 0x0000000000400000ULL,
2519 
2520 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2521                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2522                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2523                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2524                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2525                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2526                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2527                         PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2528                         PPC2_BCDA_ISA206)
2529 };
2530 
2531 /*****************************************************************************/
2532 /*
2533  * Memory access type :
2534  * may be needed for precise access rights control and precise exceptions.
2535  */
2536 enum {
2537     /* Type of instruction that generated the access */
2538     ACCESS_CODE  = 0x10, /* Code fetch access                */
2539     ACCESS_INT   = 0x20, /* Integer load/store access        */
2540     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2541     ACCESS_RES   = 0x40, /* load/store with reservation      */
2542     ACCESS_EXT   = 0x50, /* external access                  */
2543     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2544 };
2545 
2546 /*
2547  * Hardware interrupt sources:
2548  *   all those exception can be raised simulteaneously
2549  */
2550 /* Input pins definitions */
2551 enum {
2552     /* 6xx bus input pins */
2553     PPC6xx_INPUT_HRESET     = 0,
2554     PPC6xx_INPUT_SRESET     = 1,
2555     PPC6xx_INPUT_CKSTP_IN   = 2,
2556     PPC6xx_INPUT_MCP        = 3,
2557     PPC6xx_INPUT_SMI        = 4,
2558     PPC6xx_INPUT_INT        = 5,
2559     PPC6xx_INPUT_TBEN       = 6,
2560     PPC6xx_INPUT_WAKEUP     = 7,
2561     PPC6xx_INPUT_NB,
2562 };
2563 
2564 enum {
2565     /* Embedded PowerPC input pins */
2566     PPCBookE_INPUT_HRESET     = 0,
2567     PPCBookE_INPUT_SRESET     = 1,
2568     PPCBookE_INPUT_CKSTP_IN   = 2,
2569     PPCBookE_INPUT_MCP        = 3,
2570     PPCBookE_INPUT_SMI        = 4,
2571     PPCBookE_INPUT_INT        = 5,
2572     PPCBookE_INPUT_CINT       = 6,
2573     PPCBookE_INPUT_NB,
2574 };
2575 
2576 enum {
2577     /* PowerPC E500 input pins */
2578     PPCE500_INPUT_RESET_CORE = 0,
2579     PPCE500_INPUT_MCK        = 1,
2580     PPCE500_INPUT_CINT       = 3,
2581     PPCE500_INPUT_INT        = 4,
2582     PPCE500_INPUT_DEBUG      = 6,
2583     PPCE500_INPUT_NB,
2584 };
2585 
2586 enum {
2587     /* PowerPC 40x input pins */
2588     PPC40x_INPUT_RESET_CORE = 0,
2589     PPC40x_INPUT_RESET_CHIP = 1,
2590     PPC40x_INPUT_RESET_SYS  = 2,
2591     PPC40x_INPUT_CINT       = 3,
2592     PPC40x_INPUT_INT        = 4,
2593     PPC40x_INPUT_HALT       = 5,
2594     PPC40x_INPUT_DEBUG      = 6,
2595     PPC40x_INPUT_NB,
2596 };
2597 
2598 enum {
2599     /* RCPU input pins */
2600     PPCRCPU_INPUT_PORESET   = 0,
2601     PPCRCPU_INPUT_HRESET    = 1,
2602     PPCRCPU_INPUT_SRESET    = 2,
2603     PPCRCPU_INPUT_IRQ0      = 3,
2604     PPCRCPU_INPUT_IRQ1      = 4,
2605     PPCRCPU_INPUT_IRQ2      = 5,
2606     PPCRCPU_INPUT_IRQ3      = 6,
2607     PPCRCPU_INPUT_IRQ4      = 7,
2608     PPCRCPU_INPUT_IRQ5      = 8,
2609     PPCRCPU_INPUT_IRQ6      = 9,
2610     PPCRCPU_INPUT_IRQ7      = 10,
2611     PPCRCPU_INPUT_NB,
2612 };
2613 
2614 #if defined(TARGET_PPC64)
2615 enum {
2616     /* PowerPC 970 input pins */
2617     PPC970_INPUT_HRESET     = 0,
2618     PPC970_INPUT_SRESET     = 1,
2619     PPC970_INPUT_CKSTP      = 2,
2620     PPC970_INPUT_TBEN       = 3,
2621     PPC970_INPUT_MCP        = 4,
2622     PPC970_INPUT_INT        = 5,
2623     PPC970_INPUT_THINT      = 6,
2624     PPC970_INPUT_NB,
2625 };
2626 
2627 enum {
2628     /* POWER7 input pins */
2629     POWER7_INPUT_INT        = 0,
2630     /*
2631      * POWER7 probably has other inputs, but we don't care about them
2632      * for any existing machine.  We can wire these up when we need
2633      * them
2634      */
2635     POWER7_INPUT_NB,
2636 };
2637 
2638 enum {
2639     /* POWER9 input pins */
2640     POWER9_INPUT_INT        = 0,
2641     POWER9_INPUT_HINT       = 1,
2642     POWER9_INPUT_NB,
2643 };
2644 #endif
2645 
2646 /* Hardware exceptions definitions */
2647 enum {
2648     /* External hardware exception sources */
2649     PPC_INTERRUPT_RESET     = 0x00001,  /* Reset exception                    */
2650     PPC_INTERRUPT_WAKEUP    = 0x00002,  /* Wakeup exception                   */
2651     PPC_INTERRUPT_MCK       = 0x00004,  /* Machine check exception            */
2652     PPC_INTERRUPT_EXT       = 0x00008,  /* External interrupt                 */
2653     PPC_INTERRUPT_SMI       = 0x00010,  /* System management interrupt        */
2654     PPC_INTERRUPT_CEXT      = 0x00020,  /* Critical external interrupt        */
2655     PPC_INTERRUPT_DEBUG     = 0x00040,  /* External debug exception           */
2656     PPC_INTERRUPT_THERM     = 0x00080,  /* Thermal exception                  */
2657     /* Internal hardware exception sources */
2658     PPC_INTERRUPT_DECR      = 0x00100, /* Decrementer exception               */
2659     PPC_INTERRUPT_HDECR     = 0x00200, /* Hypervisor decrementer exception    */
2660     PPC_INTERRUPT_PIT       = 0x00400, /* Programmable interval timer int.    */
2661     PPC_INTERRUPT_FIT       = 0x00800, /* Fixed interval timer interrupt      */
2662     PPC_INTERRUPT_WDT       = 0x01000, /* Watchdog timer interrupt            */
2663     PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt         */
2664     PPC_INTERRUPT_DOORBELL  = 0x04000, /* Doorbell interrupt                  */
2665     PPC_INTERRUPT_PERFM     = 0x08000, /* Performance monitor interrupt       */
2666     PPC_INTERRUPT_HMI       = 0x10000, /* Hypervisor Maintenance interrupt    */
2667     PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt       */
2668     PPC_INTERRUPT_HVIRT     = 0x40000, /* Hypervisor virtualization interrupt */
2669     PPC_INTERRUPT_EBB       = 0x80000, /* Event-based Branch exception        */
2670 };
2671 
2672 /* Processor Compatibility mask (PCR) */
2673 enum {
2674     PCR_COMPAT_2_05     = PPC_BIT(62),
2675     PCR_COMPAT_2_06     = PPC_BIT(61),
2676     PCR_COMPAT_2_07     = PPC_BIT(60),
2677     PCR_COMPAT_3_00     = PPC_BIT(59),
2678     PCR_COMPAT_3_10     = PPC_BIT(58),
2679     PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2680     PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2681     PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2682 };
2683 
2684 /* HMER/HMEER */
2685 enum {
2686     HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
2687     HMER_PROC_RECV_DONE         = PPC_BIT(2),
2688     HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2689     HMER_TFAC_ERROR             = PPC_BIT(4),
2690     HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
2691     HMER_XSCOM_FAIL             = PPC_BIT(8),
2692     HMER_XSCOM_DONE             = PPC_BIT(9),
2693     HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
2694     HMER_WARN_RISE              = PPC_BIT(14),
2695     HMER_WARN_FALL              = PPC_BIT(15),
2696     HMER_SCOM_FIR_HMI           = PPC_BIT(16),
2697     HMER_TRIG_FIR_HMI           = PPC_BIT(17),
2698     HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
2699     HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
2700 };
2701 
2702 /* TFMR */
2703 enum {
2704     TFMR_CONTROL_MASK           = PPC_BITMASK(0, 24),
2705     TFMR_MASK_HMI               = PPC_BIT(10),
2706     TFMR_TB_ECLIPZ              = PPC_BIT(14),
2707     TFMR_LOAD_TOD_MOD           = PPC_BIT(16),
2708     TFMR_MOVE_CHIP_TOD_TO_TB    = PPC_BIT(18),
2709     TFMR_CLEAR_TB_ERRORS        = PPC_BIT(24),
2710     TFMR_STATUS_MASK            = PPC_BITMASK(25, 63),
2711     TFMR_TBST_ENCODED           = PPC_BITMASK(28, 31), /* TBST = TB State */
2712     TFMR_TBST_LAST              = PPC_BITMASK(32, 35), /* Previous TBST */
2713     TFMR_TB_ENABLED             = PPC_BIT(40),
2714     TFMR_TB_VALID               = PPC_BIT(41),
2715     TFMR_TB_SYNC_OCCURED        = PPC_BIT(42),
2716     TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),
2717 };
2718 
2719 /* TFMR TBST (Time Base State Machine). */
2720 enum {
2721     TBST_RESET                  = 0x0,
2722     TBST_SEND_TOD_MOD           = 0x1,
2723     TBST_NOT_SET                = 0x2,
2724     TBST_SYNC_WAIT              = 0x6,
2725     TBST_GET_TOD                = 0x7,
2726     TBST_TB_RUNNING             = 0x8,
2727     TBST_TB_ERROR               = 0x9,
2728 };
2729 
2730 /*****************************************************************************/
2731 
2732 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2733 target_ulong cpu_read_xer(const CPUPPCState *env);
2734 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2735 
2736 /*
2737  * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2738  * have PPC_SEGMENT_64B.
2739  */
2740 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2741 
2742 #ifdef CONFIG_DEBUG_TCG
2743 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2744                           uint64_t *cs_base, uint32_t *flags);
2745 #else
2746 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2747                                         uint64_t *cs_base, uint32_t *flags)
2748 {
2749     *pc = env->nip;
2750     *cs_base = 0;
2751     *flags = env->hflags;
2752 }
2753 #endif
2754 
2755 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2756 G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2757                                    uintptr_t raddr);
2758 G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2759                                     uint32_t error_code);
2760 G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2761                                        uint32_t error_code, uintptr_t raddr);
2762 
2763 /* PERFM EBB helper*/
2764 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2765 void raise_ebb_perfm_exception(CPUPPCState *env);
2766 #endif
2767 
2768 #if !defined(CONFIG_USER_ONLY)
2769 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2770 {
2771     uintptr_t tlbml = (uintptr_t)tlbm;
2772     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2773 
2774     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2775 }
2776 
2777 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2778 {
2779     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2780     int r = tlbncfg & TLBnCFG_N_ENTRY;
2781     return r;
2782 }
2783 
2784 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2785 {
2786     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2787     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2788     return r;
2789 }
2790 
2791 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2792 {
2793     int id = booke206_tlbm_id(env, tlbm);
2794     int end = 0;
2795     int i;
2796 
2797     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2798         end += booke206_tlb_size(env, i);
2799         if (id < end) {
2800             return i;
2801         }
2802     }
2803 
2804     cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2805     return 0;
2806 }
2807 
2808 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2809 {
2810     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2811     int tlbid = booke206_tlbm_id(env, tlb);
2812     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2813 }
2814 
2815 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2816                                               target_ulong ea, int way)
2817 {
2818     int r;
2819     uint32_t ways = booke206_tlb_ways(env, tlbn);
2820     int ways_bits = ctz32(ways);
2821     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2822     int i;
2823 
2824     way &= ways - 1;
2825     ea >>= MAS2_EPN_SHIFT;
2826     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2827     r = (ea << ways_bits) | way;
2828 
2829     if (r >= booke206_tlb_size(env, tlbn)) {
2830         return NULL;
2831     }
2832 
2833     /* bump up to tlbn index */
2834     for (i = 0; i < tlbn; i++) {
2835         r += booke206_tlb_size(env, i);
2836     }
2837 
2838     return &env->tlb.tlbm[r];
2839 }
2840 
2841 /* returns bitmap of supported page sizes for a given TLB */
2842 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2843 {
2844     uint32_t ret = 0;
2845 
2846     if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2847         /* MAV2 */
2848         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2849     } else {
2850         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2851         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2852         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2853         int i;
2854         for (i = min; i <= max; i++) {
2855             ret |= (1 << (i << 1));
2856         }
2857     }
2858 
2859     return ret;
2860 }
2861 
2862 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2863                                             ppcmas_tlb_t *tlb)
2864 {
2865     uint8_t i;
2866     int32_t tsize = -1;
2867 
2868     for (i = 0; i < 32; i++) {
2869         if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2870             if (tsize == -1) {
2871                 tsize = i;
2872             } else {
2873                 return;
2874             }
2875         }
2876     }
2877 
2878     /* TLBnPS unimplemented? Odd.. */
2879     assert(tsize != -1);
2880     tlb->mas1 &= ~MAS1_TSIZE_MASK;
2881     tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2882 }
2883 
2884 static inline bool ppc_is_split_tlb(PowerPCCPU *cpu)
2885 {
2886     return cpu->env.tlb_type == TLB_6XX;
2887 }
2888 #endif
2889 
2890 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2891 {
2892     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2893         return msr & (1ULL << MSR_CM);
2894     }
2895 
2896     return msr & (1ULL << MSR_SF);
2897 }
2898 
2899 /**
2900  * Check whether register rx is in the range between start and
2901  * start + nregs (as needed by the LSWX and LSWI instructions)
2902  */
2903 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2904 {
2905     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2906            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2907 }
2908 
2909 /* Accessors for FP, VMX and VSX registers */
2910 #if HOST_BIG_ENDIAN
2911 #define VsrB(i) u8[i]
2912 #define VsrSB(i) s8[i]
2913 #define VsrH(i) u16[i]
2914 #define VsrSH(i) s16[i]
2915 #define VsrW(i) u32[i]
2916 #define VsrSW(i) s32[i]
2917 #define VsrD(i) u64[i]
2918 #define VsrSD(i) s64[i]
2919 #define VsrHF(i) f16[i]
2920 #define VsrSF(i) f32[i]
2921 #define VsrDF(i) f64[i]
2922 #else
2923 #define VsrB(i) u8[15 - (i)]
2924 #define VsrSB(i) s8[15 - (i)]
2925 #define VsrH(i) u16[7 - (i)]
2926 #define VsrSH(i) s16[7 - (i)]
2927 #define VsrW(i) u32[3 - (i)]
2928 #define VsrSW(i) s32[3 - (i)]
2929 #define VsrD(i) u64[1 - (i)]
2930 #define VsrSD(i) s64[1 - (i)]
2931 #define VsrHF(i) f16[7 - (i)]
2932 #define VsrSF(i) f32[3 - (i)]
2933 #define VsrDF(i) f64[1 - (i)]
2934 #endif
2935 
2936 static inline int vsr64_offset(int i, bool high)
2937 {
2938     return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2939 }
2940 
2941 static inline int vsr_full_offset(int i)
2942 {
2943     return offsetof(CPUPPCState, vsr[i].u64[0]);
2944 }
2945 
2946 static inline int acc_full_offset(int i)
2947 {
2948     return vsr_full_offset(i * 4);
2949 }
2950 
2951 static inline int fpr_offset(int i)
2952 {
2953     return vsr64_offset(i, true);
2954 }
2955 
2956 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2957 {
2958     return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2959 }
2960 
2961 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2962 {
2963     return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2964 }
2965 
2966 static inline long avr64_offset(int i, bool high)
2967 {
2968     return vsr64_offset(i + 32, high);
2969 }
2970 
2971 static inline int avr_full_offset(int i)
2972 {
2973     return vsr_full_offset(i + 32);
2974 }
2975 
2976 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2977 {
2978     return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2979 }
2980 
2981 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2982 {
2983     /* We can test whether the SPR is defined by checking for a valid name */
2984     return cpu->env.spr_cb[spr].name != NULL;
2985 }
2986 
2987 #if !defined(CONFIG_USER_ONLY)
2988 /* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
2989 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2990 {
2991     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2992     CPUPPCState *env = &cpu->env;
2993     bool ile;
2994 
2995     if (hv && env->has_hv_mode) {
2996         if (is_isa300(pcc)) {
2997             ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2998         } else {
2999             ile = !!(env->spr[SPR_HID0] & HID0_HILE);
3000         }
3001 
3002     } else if (pcc->lpcr_mask & LPCR_ILE) {
3003         ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
3004     } else {
3005         ile = FIELD_EX64(env->msr, MSR, ILE);
3006     }
3007 
3008     return ile;
3009 }
3010 #endif
3011 
3012 void dump_mmu(CPUPPCState *env);
3013 
3014 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
3015 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
3016 uint32_t ppc_get_vscr(CPUPPCState *env);
3017 void ppc_set_cr(CPUPPCState *env, uint64_t cr);
3018 uint64_t ppc_get_cr(const CPUPPCState *env);
3019 
3020 /*****************************************************************************/
3021 /* Power management enable checks                                            */
3022 static inline int check_pow_none(CPUPPCState *env)
3023 {
3024     return 0;
3025 }
3026 
3027 static inline int check_pow_nocheck(CPUPPCState *env)
3028 {
3029     return 1;
3030 }
3031 
3032 /* attn enable check                                                         */
3033 static inline int check_attn_none(CPUPPCState *env)
3034 {
3035     return 0;
3036 }
3037 
3038 /*****************************************************************************/
3039 /* PowerPC implementations definitions                                       */
3040 
3041 #define POWERPC_FAMILY(_name)                                               \
3042     static void                                                             \
3043     glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3044                                                                             \
3045     static const TypeInfo                                                   \
3046     glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3047         .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3048         .parent = TYPE_POWERPC_CPU,                                         \
3049         .abstract = true,                                                   \
3050         .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3051     };                                                                      \
3052                                                                             \
3053     static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3054     {                                                                       \
3055         type_register_static(                                               \
3056             &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3057     }                                                                       \
3058                                                                             \
3059     type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3060                                                                             \
3061     static void glue(glue(ppc_, _name), _cpu_family_class_init)
3062 
3063 
3064 #endif /* PPC_CPU_H */
3065